/* ** ################################################################### ** Processor: MIMX8QM6AVUFF ** Compilers: Keil ARM C/C++ Compiler ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** ** Reference manual: IMX8QMRM, Rev. E, Jun. 2018 ** Version: rev. 4.0, 2018-08-30 ** Build: b200930 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8QM6_cm4_core1 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. ** Copyright 2016-2018 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2016-06-02) ** Initial version. ** - rev. 2.0 (2017-05-04) ** RevA Header ER ** - rev. 3.0 (2018-01-29) ** RevB Header ER ** - rev. 4.0 (2018-08-30) ** RevC Header EAR ** ** ################################################################### */ /*! * @file MIMX8QM6_cm4_core1.h * @version 4.0 * @date 2018-08-30 * @brief CMSIS Peripheral Access Layer for MIMX8QM6_cm4_core1 * * CMSIS Peripheral Access Layer for MIMX8QM6_cm4_core1 */ #ifndef _MIMX8QM6_CM4_CORE1_H_ #define _MIMX8QM6_CM4_CORE1_H_ /**< Symbol preventing repeated inclusion */ /** Memory map major version (memory maps with equal major version number are * compatible) */ #define MCU_MEM_MAP_VERSION 0x0400U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U /* ---------------------------------------------------------------------------- -- Interrupt vector numbers ---------------------------------------------------------------------------- */ /*! * @addtogroup Interrupt_vector_numbers Interrupt vector numbers * @{ */ /** Interrupt Number Definitions */ #define NUMBER_OF_INT_VECTORS 611 /**< Number of interrupts in the Vector table */ typedef enum IRQn { /* Auxiliary constants */ NotAvail_IRQn = -128, /**< Not available device specific interrupt */ /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ /* Device specific interrupts */ Reserved16_IRQn = 0, /**< Reserved */ Reserved17_IRQn = 1, /**< Reserved */ Reserved18_IRQn = 2, /**< Reserved */ Reserved19_IRQn = 3, /**< Reserved */ Reserved20_IRQn = 4, /**< Reserved */ M4_1_MCM_IRQn = 5, /**< MCM IRQ */ Reserved22_IRQn = 6, /**< Reserved */ Reserved23_IRQn = 7, /**< Reserved */ Reserved24_IRQn = 8, /**< Reserved */ Reserved25_IRQn = 9, /**< Reserved */ Reserved26_IRQn = 10, /**< Reserved */ Reserved27_IRQn = 11, /**< Reserved */ Reserved28_IRQn = 12, /**< Reserved */ Reserved29_IRQn = 13, /**< Reserved */ Reserved30_IRQn = 14, /**< Reserved */ Reserved31_IRQn = 15, /**< Reserved */ Reserved32_IRQn = 16, /**< Reserved */ Reserved33_IRQn = 17, /**< Reserved */ Reserved34_IRQn = 18, /**< Reserved */ M4_1_TPM_IRQn = 19, /**< Timer PWM Module */ Reserved36_IRQn = 20, /**< Reserved */ Reserved37_IRQn = 21, /**< Reserved */ M4_1_LPIT_IRQn = 22, /**< Low-Power Periodic Interrupt Timer */ Reserved39_IRQn = 23, /**< Reserved */ Reserved40_IRQn = 24, /**< Reserved */ M4_1_LPUART_IRQn = 25, /**< Low Power UART */ Reserved42_IRQn = 26, /**< Reserved */ M4_1_LPI2C_IRQn = 27, /**< Low-Power I2C - Logical OR of master and slave interrupts */ Reserved44_IRQn = 28, /**< Reserved */ M4_1_MU0_B0_IRQn = 29, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 0, Logical OR of all general-purpose, TX, and RX interrupts */ Reserved46_IRQn = 30, /**< Reserved */ Reserved47_IRQn = 31, /**< Reserved */ IRQSTEER_0_IRQn = 32, /**< External interrupt 0 */ IRQSTEER_1_IRQn = 33, /**< External interrupt 1 */ IRQSTEER_2_IRQn = 34, /**< External interrupt 2 */ IRQSTEER_3_IRQn = 35, /**< External interrupt 3 */ IRQSTEER_4_IRQn = 36, /**< External interrupt 4 */ IRQSTEER_5_IRQn = 37, /**< External interrupt 5 */ IRQSTEER_6_IRQn = 38, /**< External interrupt 6 */ IRQSTEER_7_IRQn = 39, /**< External interrupt 7 */ Reserved56_IRQn = 40, /**< Reserved */ Reserved57_IRQn = 41, /**< Reserved */ Reserved58_IRQn = 42, /**< Reserved */ Reserved59_IRQn = 43, /**< Reserved */ M4_1_MU0_B1_IRQn = 44, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 1, Logical OR of all general-purpose, TX, and RX interrupts */ M4_1_MU0_B2_IRQn = 45, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 2, Logical OR of all general-purpose, TX, and RX interrupts */ M4_1_MU0_B3_IRQn = 46, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 3, Logical OR of all general-purpose, TX, and RX interrupts */ Reserved63_IRQn = 47, /**< Reserved */ Reserved64_IRQn = 48, /**< Reserved */ M4_1_MU1_A_IRQn = 49, /**< Messaging Unit 1 (IPC with System Controller) - Side A (MCU), Logical OR of all general-purpose, TX, and RX interrupts */ M4_1_SW_IRQn = 50, /**< Software interrupt (asserted/cleared via NVIC registers, INTISR[50] input tied low) */ A53_NEXTERRIRQ_IRQn = 83, /**< Shared Int Source nEXTERRIRQ from A53 Sub-System */ A53_NINTERRIRQ_IRQn = 84, /**< Shared Int Source nINTERRIRQ from A53 Sub-System */ A72_NEXTERRIRQ_IRQn = 85, /**< Shared Int Source nEXTERRIRQ from A72 Sub-System */ A72_NINTERRIRQ_IRQn = 86, /**< Shared Int Source nINTERRIRQ from A72 Sub-System */ VPU_NEXTERRIRQ_IRQn = 87, /**< Shared Int Source nEXTERRIRQ from VPU Sub-System */ CCI_NERRORIRQ_IRQn = 91, /**< Shared Int Source nERRORIRQ from CCI Sub-System */ CCI_NEVNTCNTOVERFLOW0_IRQn = 92, /**< Shared Int Source nEVNTCNTOVERFLOW[0] from CCI Sub-System */ CCI_NEVNTCNTOVERFLOW1_IRQn = 93, /**< Shared Int Source nEVNTCNTOVERFLOW[1] from CCI Sub-System */ CCI_NEVNTCNTOVERFLOW2_IRQn = 94, /**< Shared Int Source nEVNTCNTOVERFLOW[2] from CCI Sub-System */ CCI_NEVNTCNTOVERFLOW3_IRQn = 95, /**< Shared Int Source nEVNTCNTOVERFLOW[3] from CCI Sub-System */ CCI_NEVNTCNTOVERFLOW4_IRQn = 96, /**< Shared Int Source nEVNTCNTOVERFLOW[4] from CCI Sub-System */ M4_0_INT_OUT0_IRQn = 99, /**< Shared Int Source INT_OUT[0] from M4_0 Sub-System */ M4_0_INT_OUT1_IRQn = 100, /**< Shared Int Source INT_OUT[1] from M4_0 Sub-System */ M4_0_INT_OUT2_IRQn = 101, /**< Shared Int Source INT_OUT[2] from M4_0 Sub-System */ M4_0_INT_OUT3_IRQn = 102, /**< Shared Int Source INT_OUT[3] from M4_0 Sub-System */ M4_0_INT_OUT4_IRQn = 103, /**< Shared Int Source INT_OUT[4] from M4_0 Sub-System */ M4_0_INT_OUT5_IRQn = 104, /**< Shared Int Source INT_OUT[5] from M4_0 Sub-System */ M4_0_INT_OUT6_IRQn = 105, /**< Shared Int Source INT_OUT[6] from M4_0 Sub-System */ M4_0_INT_OUT7_IRQn = 106, /**< Shared Int Source INT_OUT[7] from M4_0 Sub-System */ M4_1_INT_OUT0_IRQn = 107, /**< Shared Int Source INT_OUT[0] from M4_1 Sub-System */ M4_1_INT_OUT1_IRQn = 108, /**< Shared Int Source INT_OUT[1] from M4_1 Sub-System */ M4_1_INT_OUT2_IRQn = 109, /**< Shared Int Source INT_OUT[2] from M4_1 Sub-System */ M4_1_INT_OUT3_IRQn = 110, /**< Shared Int Source INT_OUT[3] from M4_1 Sub-System */ M4_1_INT_OUT4_IRQn = 111, /**< Shared Int Source INT_OUT[4] from M4_1 Sub-System */ M4_1_INT_OUT5_IRQn = 112, /**< Shared Int Source INT_OUT[5] from M4_1 Sub-System */ M4_1_INT_OUT6_IRQn = 113, /**< Shared Int Source INT_OUT[6] from M4_1 Sub-System */ M4_1_INT_OUT7_IRQn = 114, /**< Shared Int Source INT_OUT[7] from M4_1 Sub-System */ DBLOG_COMB_IRPT_NS_IRQn = 115, /**< Shared Int Source comb_irpt_ns from DBLog Sub-System */ DBLOG_COMB_IRPT_S_IRQn = 116, /**< Shared Int Source comb_irpt_s from DBLog Sub-System */ DBLOG_GBL_FLT_IRPT_NS_IRQn = 117, /**< Shared Int Source gbl_flt_irpt_ns from DBLog Sub-System */ DBLOG_GBL_FLT_IRPT_S_IRQn = 118, /**< Shared Int Source gbl_flt_irpt_s from DBLog Sub-System */ DBLOG_PERF_IRPT_IMX8_0_IRQn = 119, /**< Shared Int Source perf_irpt_imx8_0 from DBLog Sub-System */ DBLOG_PERF_IRPT_IMX8_1_IRQn = 120, /**< Shared Int Source perf_irpt_imx8_1 from DBLog Sub-System */ DBLOG_PERF_IRPT_IMX8_2_IRQn = 121, /**< Shared Int Source perf_irpt_imx8_2 from DBLog Sub-System */ DBLOG_PERF_IRPT_IMX8_3_IRQn = 122, /**< Shared Int Source perf_irpt_imx8_3 from DBLog Sub-System */ DISPLAY0_INT_OUT0_IRQn = 123, /**< Shared Int Source INT_OUT[0] from Display0 Sub-System */ DISPLAY0_INT_OUT1_IRQn = 124, /**< Shared Int Source INT_OUT[1] from Display0 Sub-System */ DISPLAY0_INT_OUT2_IRQn = 125, /**< Shared Int Source INT_OUT[2] from Display0 Sub-System */ DISPLAY0_INT_OUT3_IRQn = 126, /**< Shared Int Source INT_OUT[3] from Display0 Sub-System */ DISPLAY0_INT_OUT4_IRQn = 127, /**< Shared Int Source INT_OUT[4] from Display0 Sub-System */ DISPLAY0_INT_OUT5_IRQn = 128, /**< Shared Int Source INT_OUT[5] from Display0 Sub-System */ DISPLAY0_INT_OUT6_IRQn = 129, /**< Shared Int Source INT_OUT[6] from Display0 Sub-System */ DISPLAY0_INT_OUT7_IRQn = 130, /**< Shared Int Source INT_OUT[7] from Display0 Sub-System */ DISPLAY0_RESERVED_IRQn = 131, /**< Shared Int Source Reserved from Display0 Sub-System */ DISPLAY0_INT_OUT9_IRQn = 132, /**< Shared Int Source INT_OUT[9] from Display0 Sub-System */ DISPLAY0_INT_OUT10_IRQn = 133, /**< Shared Int Source INT_OUT[10] from Display0 Sub-System */ DISPLAY0_INT_OUT11_IRQn = 134, /**< Shared Int Source INT_OUT[11] from Display0 Sub-System */ DISPLAY0_INT_OUT12_IRQn = 135, /**< Shared Int Source INT_OUT[12] from Display0 Sub-System */ LVDS0_INT_OUT_IRQn = 140, /**< Shared Int Source INT_OUT from LVDS0 Sub-System */ LVDS1_INT_OUT_IRQn = 141, /**< Shared Int Source INT_OUT from LVDS1 Sub-System */ MIPI_DSI0_INT_OUT_IRQn = 142, /**< Shared Int Source INT_OUT from MIPI_DSI0 Sub-System */ MIPI_DSI1_INT_OUT_IRQn = 143, /**< Shared Int Source INT_OUT from MIPI_DSI1 Sub-System */ HDMI_TX_INT_OUT_IRQn = 144, /**< Shared Int Source INT_OUT from HDMI_TX Sub-System */ GPU0_XAQ2_INTR_IRQn = 147, /**< Shared Int Source xaq2_intr from GPU0 Sub-System */ GPU1_XAQ2_INTR_IRQn = 148, /**< Shared Int Source xaq2_intr from GPU1 Sub-System */ DMA_EDMA0_INT_IRQn = 149, /**< Shared Int Source eDMA0_INT from DMA Sub-System */ DMA_EDMA0_ERR_INT_IRQn = 150, /**< Shared Int Source eDMA0_ERR_INT from DMA Sub-System */ DMA_EDMA1_INT_IRQn = 151, /**< Shared Int Source eDMA1_INT from DMA Sub-System */ DMA_EDMA1_ERR_INT_IRQn = 152, /**< Shared Int Source eDMA1_ERR_INT from DMA Sub-System */ HSIO_PCIEA_MSI_CTRL_INT_IRQn = 153, /**< Shared Int Source PCIeA_MSI_CTRL_INT from HSIO Sub-System */ HSIO_PCIEA_CLK_REQ_INT_IRQn = 154, /**< Shared Int Source PCIeA_CLK_REQ_INT from HSIO Sub-System */ HSIO_PCIEA_DMA_INT_IRQn = 155, /**< Shared Int Source PCIeA_DMA_INT from HSIO Sub-System */ HSIO_PCIEA_INT_D_IRQn = 156, /**< Shared Int Source PCIeA_INT_D from HSIO Sub-System */ HSIO_PCIEA_INT_C_IRQn = 157, /**< Shared Int Source PCIeA_INT_C from HSIO Sub-System */ HSIO_PCIEA_INT_B_IRQn = 158, /**< Shared Int Source PCIeA_INT_B from HSIO Sub-System */ HSIO_PCIEA_INT_A_IRQn = 159, /**< Shared Int Source PCIeA_INT_A from HSIO Sub-System */ HSIO_PCIEA_SMLH_REQ_RST_IRQn = 160, /**< Shared Int Source PCIeA_SMLH_REQ_RST from HSIO Sub-System */ HSIO_PCIEA_GPIO_WAKEUP0_IRQn = 161, /**< Shared Int Source PCIeA_GPIO_WAKEUP[0] from HSIO Sub-System */ HSIO_PCIEA_GPIO_WAKEUP1_IRQn = 162, /**< Shared Int Source PCIeA_GPIO_WAKEUP[1] from HSIO Sub-System */ LSIO_GPT0_INT_IRQn = 163, /**< Shared Int Source GPT0_INT from LSIO Sub-System */ LSIO_GPT1_INT_IRQn = 164, /**< Shared Int Source GPT1_INT from LSIO Sub-System */ LSIO_GPT2_INT_IRQn = 165, /**< Shared Int Source GPT2_INT from LSIO Sub-System */ LSIO_GPT3_INT_IRQn = 166, /**< Shared Int Source GPT3_INT from LSIO Sub-System */ LSIO_GPT4_INT_IRQn = 167, /**< Shared Int Source GPT4_INT from LSIO Sub-System */ LSIO_KPP_INT_IRQn = 168, /**< Shared Int Source KPP_INT from LSIO Sub-System */ HSIO_SATA_INT0_IRQn = 171, /**< Shared Int Source SATA_INT[0] from HSIO Sub-System */ HSIO_SATA_INT2_IRQn = 172, /**< Shared Int Source SATA_INT[2] from HSIO Sub-System */ LSIO_OCTASPI0_INT_IRQn = 175, /**< Shared Int Source OctaSPI0_INT from LSIO Sub-System */ LSIO_OCTASPI1_INT_IRQn = 176, /**< Shared Int Source OctaSPI1_INT from LSIO Sub-System */ LSIO_PWM0_INT_IRQn = 177, /**< Shared Int Source PWM0_INT from LSIO Sub-System */ LSIO_PWM1_INT_IRQn = 178, /**< Shared Int Source PWM1_INT from LSIO Sub-System */ LSIO_PWM2_INT_IRQn = 179, /**< Shared Int Source PWM2_INT from LSIO Sub-System */ LSIO_PWM3_INT_IRQn = 180, /**< Shared Int Source PWM3_INT from LSIO Sub-System */ LSIO_PWM4_INT_IRQn = 181, /**< Shared Int Source PWM4_INT from LSIO Sub-System */ LSIO_PWM5_INT_IRQn = 182, /**< Shared Int Source PWM5_INT from LSIO Sub-System */ LSIO_PWM6_INT_IRQn = 183, /**< Shared Int Source PWM6_INT from LSIO Sub-System */ LSIO_PWM7_INT_IRQn = 184, /**< Shared Int Source PWM7_INT from LSIO Sub-System */ HSIO_PCIEB_MSI_CTRL_INT_IRQn = 185, /**< Shared Int Source PCIeB_MSI_CTRL_INT from HSIO Sub-System */ HSIO_PCIEB_CLK_REQ_INT_IRQn = 186, /**< Shared Int Source PCIeB_CLK_REQ_INT from HSIO Sub-System */ HSIO_PCIEB_DMA_INT_IRQn = 187, /**< Shared Int Source PCIeB_DMA_INT from HSIO Sub-System */ HSIO_PCIEB_INT_D_IRQn = 188, /**< Shared Int Source PCIeB_INT_D from HSIO Sub-System */ HSIO_PCIEB_INT_C_IRQn = 189, /**< Shared Int Source PCIeB_INT_C from HSIO Sub-System */ HSIO_PCIEB_INT_B_IRQn = 190, /**< Shared Int Source PCIeB_INT_B from HSIO Sub-System */ HSIO_PCIEB_INT_A_IRQn = 191, /**< Shared Int Source PCIeB_INT_A from HSIO Sub-System */ HSIO_PCIEB_SMLH_REQ_RST_IRQn = 192, /**< Shared Int Source PCIeB_SMLH_REQ_RST from HSIO Sub-System */ HSIO_PCIEB_GPIO_WAKEUP0_IRQn = 193, /**< Shared Int Source PCIeB_GPIO_WAKEUP[0] from HSIO Sub-System */ HSIO_PCIEB_GPIO_WAKEUP1_IRQn = 194, /**< Shared Int Source PCIeB_GPIO_WAKEUP[1] from HSIO Sub-System */ SCU_INT_OUT0_IRQn = 195, /**< Shared Int Source INT_OUT[0] from SCU Sub-System */ SCU_INT_OUT1_IRQn = 196, /**< Shared Int Source INT_OUT[1] from SCU Sub-System */ SCU_INT_OUT2_IRQn = 197, /**< Shared Int Source INT_OUT[2] from SCU Sub-System */ SCU_INT_OUT3_IRQn = 198, /**< Shared Int Source INT_OUT[3] from SCU Sub-System */ SCU_INT_OUT4_IRQn = 199, /**< Shared Int Source INT_OUT[4] from SCU Sub-System */ SCU_INT_OUT5_IRQn = 200, /**< Shared Int Source INT_OUT[5] from SCU Sub-System */ SCU_INT_OUT6_IRQn = 201, /**< Shared Int Source INT_OUT[6] from SCU Sub-System */ SCU_INT_OUT7_IRQn = 202, /**< Shared Int Source INT_OUT[7] from SCU Sub-System */ SCU_SYS_COUNT_INT0_IRQn = 203, /**< Shared Int Source SYS_COUNT_INT[0] from SCU Sub-System */ SCU_SYS_COUNT_INT1_IRQn = 204, /**< Shared Int Source SYS_COUNT_INT[1] from SCU Sub-System */ SCU_SYS_COUNT_INT2_IRQn = 205, /**< Shared Int Source SYS_COUNT_INT[2] from SCU Sub-System */ SCU_SYS_COUNT_INT3_IRQn = 206, /**< Shared Int Source SYS_COUNT_INT[3] from SCU Sub-System */ DRC0_DFI_ALERT_ERR_IRQn = 211, /**< Shared Int Source DFI_ALERT_ERR from DRC0 Sub-System */ DRC1_DFI_ALERT_ERR_IRQn = 212, /**< Shared Int Source DFI_ALERT_ERR from DRC1 Sub-System */ DRC0_PERF_CNT_FULL_IRQn = 213, /**< Shared Int Source PERF_CNT_FULL from DRC0 Sub-System */ DRC1_PERF_CNT_FULL_IRQn = 214, /**< Shared Int Source PERF_CNT_FULL from DRC1 Sub-System */ LSIO_GPIO_INT0_IRQn = 219, /**< Shared Int Source GPIO_INT[0] from LSIO Sub-System */ LSIO_GPIO_INT1_IRQn = 220, /**< Shared Int Source GPIO_INT[1] from LSIO Sub-System */ LSIO_GPIO_INT2_IRQn = 221, /**< Shared Int Source GPIO_INT[2] from LSIO Sub-System */ LSIO_GPIO_INT3_IRQn = 222, /**< Shared Int Source GPIO_INT[3] from LSIO Sub-System */ LSIO_GPIO_INT4_IRQn = 223, /**< Shared Int Source GPIO_INT[4] from LSIO Sub-System */ LSIO_GPIO_INT5_IRQn = 224, /**< Shared Int Source GPIO_INT[5] from LSIO Sub-System */ LSIO_GPIO_INT6_IRQn = 225, /**< Shared Int Source GPIO_INT[6] from LSIO Sub-System */ LSIO_GPIO_INT7_IRQn = 226, /**< Shared Int Source GPIO_INT[7] from LSIO Sub-System */ DISPLAY1_INT_OUT0_IRQn = 235, /**< Shared Int Source INT_OUT[0] from Display1 Sub-System */ DISPLAY1_INT_OUT1_IRQn = 236, /**< Shared Int Source INT_OUT[1] from Display1 Sub-System */ DISPLAY1_INT_OUT2_IRQn = 237, /**< Shared Int Source INT_OUT[2] from Display1 Sub-System */ DISPLAY1_INT_OUT3_IRQn = 238, /**< Shared Int Source INT_OUT[3] from Display1 Sub-System */ DISPLAY1_INT_OUT4_IRQn = 239, /**< Shared Int Source INT_OUT[4] from Display1 Sub-System */ DISPLAY1_INT_OUT5_IRQn = 240, /**< Shared Int Source INT_OUT[5] from Display1 Sub-System */ DISPLAY1_INT_OUT6_IRQn = 241, /**< Shared Int Source INT_OUT[6] from Display1 Sub-System */ DISPLAY1_INT_OUT7_IRQn = 242, /**< Shared Int Source INT_OUT[7] from Display1 Sub-System */ DISPLAY1_RESERVED_IRQn = 243, /**< Shared Int Source Reserved from Display1 Sub-System */ DISPLAY1_INT_OUT9_IRQn = 244, /**< Shared Int Source INT_OUT[9] from Display1 Sub-System */ DISPLAY1_INT_OUT10_IRQn = 245, /**< Shared Int Source INT_OUT[10] from Display1 Sub-System */ DISPLAY1_INT_OUT11_IRQn = 246, /**< Shared Int Source INT_OUT[11] from Display1 Sub-System */ DISPLAY1_INT_OUT12_IRQn = 247, /**< Shared Int Source INT_OUT[12] from Display1 Sub-System */ VPU_SYS_INT0_IRQn = 251, /**< Shared Int Source SYS_INT[0] from VPU Sub-System */ VPU_SYS_INT1_IRQn = 252, /**< Shared Int Source SYS_INT[1] from VPU Sub-System */ LSIO_MU0_INT_IRQn = 259, /**< Shared Int Source MU0_INT from LSIO Sub-System */ LSIO_MU1_INT_IRQn = 260, /**< Shared Int Source MU1_INT from LSIO Sub-System */ LSIO_MU2_INT_IRQn = 261, /**< Shared Int Source MU2_INT from LSIO Sub-System */ LSIO_MU3_INT_IRQn = 262, /**< Shared Int Source MU3_INT from LSIO Sub-System */ LSIO_MU4_INT_IRQn = 263, /**< Shared Int Source MU4_INT from LSIO Sub-System */ LSIO_MU5_INT_A_IRQn = 267, /**< Shared Int Source MU5_INT_A from LSIO Sub-System */ LSIO_MU6_INT_A_IRQn = 268, /**< Shared Int Source MU6_INT_A from LSIO Sub-System */ LSIO_MU7_INT_A_IRQn = 269, /**< Shared Int Source MU7_INT_A from LSIO Sub-System */ LSIO_MU8_INT_A_IRQn = 270, /**< Shared Int Source MU8_INT_A from LSIO Sub-System */ LSIO_MU9_INT_A_IRQn = 271, /**< Shared Int Source MU9_INT_A from LSIO Sub-System */ LSIO_MU10_INT_A_IRQn = 272, /**< Shared Int Source MU10_INT_A from LSIO Sub-System */ LSIO_MU11_INT_A_IRQn = 273, /**< Shared Int Source MU11_INT_A from LSIO Sub-System */ LSIO_MU12_INT_A_IRQn = 274, /**< Shared Int Source MU12_INT_A from LSIO Sub-System */ LSIO_MU13_INT_A_IRQn = 275, /**< Shared Int Source MU13_INT_A from LSIO Sub-System */ LSIO_MU5_INT_B_IRQn = 283, /**< Shared Int Source MU5_INT_B from LSIO Sub-System */ LSIO_MU6_INT_B_IRQn = 284, /**< Shared Int Source MU6_INT_B from LSIO Sub-System */ LSIO_MU7_INT_B_IRQn = 285, /**< Shared Int Source MU7_INT_B from LSIO Sub-System */ LSIO_MU8_INT_B_IRQn = 286, /**< Shared Int Source MU8_INT_B from LSIO Sub-System */ LSIO_MU9_INT_B_IRQn = 287, /**< Shared Int Source MU9_INT_B from LSIO Sub-System */ LSIO_MU10_INT_B_IRQn = 288, /**< Shared Int Source MU10_INT_B from LSIO Sub-System */ LSIO_MU11_INT_B_IRQn = 289, /**< Shared Int Source MU11_INT_B from LSIO Sub-System */ LSIO_MU12_INT_B_IRQn = 290, /**< Shared Int Source MU12_INT_B from LSIO Sub-System */ LSIO_MU13_INT_B_IRQn = 291, /**< Shared Int Source MU13_INT_B from LSIO Sub-System */ DMA_SPI0_INT_IRQn = 299, /**< Shared Int Source SPI0_INT from DMA Sub-System */ DMA_SPI1_INT_IRQn = 300, /**< Shared Int Source SPI1_INT from DMA Sub-System */ DMA_SPI2_INT_IRQn = 301, /**< Shared Int Source SPI2_INT from DMA Sub-System */ DMA_SPI3_INT_IRQn = 302, /**< Shared Int Source SPI3_INT from DMA Sub-System */ DMA_I2C0_INT_IRQn = 303, /**< Shared Int Source I2C0_INT from DMA Sub-System */ DMA_I2C1_INT_IRQn = 304, /**< Shared Int Source I2C1_INT from DMA Sub-System */ DMA_I2C2_INT_IRQn = 305, /**< Shared Int Source I2C2_INT from DMA Sub-System */ DMA_I2C3_INT_IRQn = 306, /**< Shared Int Source I2C3_INT from DMA Sub-System */ DMA_I2C4_INT_IRQn = 307, /**< Shared Int Source I2C4_INT from DMA Sub-System */ DMA_UART0_INT_IRQn = 308, /**< Shared Int Source UART0_INT from DMA Sub-System */ DMA_UART1_INT_IRQn = 309, /**< Shared Int Source UART1_INT from DMA Sub-System */ DMA_UART2_INT_IRQn = 310, /**< Shared Int Source UART2_INT from DMA Sub-System */ DMA_UART3_INT_IRQn = 311, /**< Shared Int Source UART3_INT from DMA Sub-System */ DMA_UART4_INT_IRQn = 312, /**< Shared Int Source UART4_INT from DMA Sub-System */ DMA_SIM0_INT_IRQn = 313, /**< Shared Int Source SIM0_INT from DMA Sub-System */ DMA_SIM1_INT_IRQn = 314, /**< Shared Int Source SIM1_INT from DMA Sub-System */ CONNECTIVITY_USDHC0_INT_IRQn = 315, /**< Shared Int Source uSDHC0_INT from Connectivity Sub-System */ CONNECTIVITY_USDHC1_INT_IRQn = 316, /**< Shared Int Source uSDHC1_INT from Connectivity Sub-System */ CONNECTIVITY_USDHC2_INT_IRQn = 317, /**< Shared Int Source uSDHC2_INT from Connectivity Sub-System */ DMA_FLEXCAN0_INT_IRQn = 318, /**< Shared Int Source FlexCAN0_INT from DMA Sub-System */ DMA_FLEXCAN1_INT_IRQn = 319, /**< Shared Int Source FlexCAN1_INT from DMA Sub-System */ DMA_FLEXCAN2_INT_IRQn = 320, /**< Shared Int Source FlexCAN2_INT from DMA Sub-System */ DMA_FTM0_INT_IRQn = 321, /**< Shared Int Source FTM0_INT from DMA Sub-System */ DMA_FTM1_INT_IRQn = 322, /**< Shared Int Source FTM1_INT from DMA Sub-System */ DMA_ADC0_INT_IRQn = 323, /**< Shared Int Source ADC0_INT from DMA Sub-System */ DMA_ADC1_INT_IRQn = 324, /**< Shared Int Source ADC1_INT from DMA Sub-System */ DMA_EXTERNAL_DMA_INT_0_IRQn = 325, /**< Shared Int Source EXTERNAL_DMA_INT_0 from DMA Sub-System */ DMA_EXTERNAL_DMA_INT_1_IRQn = 326, /**< Shared Int Source EXTERNAL_DMA_INT_1 from DMA Sub-System */ DMA_EXTERNAL_DMA_INT_2_IRQn = 327, /**< Shared Int Source EXTERNAL_DMA_INT_2 from DMA Sub-System */ DMA_EXTERNAL_DMA_INT_3_IRQn = 328, /**< Shared Int Source EXTERNAL_DMA_INT_3 from DMA Sub-System */ DMA_EXTERNAL_DMA_INT_4_IRQn = 329, /**< Shared Int Source EXTERNAL_DMA_INT_4 from DMA Sub-System */ DMA_EXTERNAL_DMA_INT_5_IRQn = 330, /**< Shared Int Source EXTERNAL_DMA_INT_5 from DMA Sub-System */ CONNECTIVITY_ENET0_FRAME1_INT_IRQn = 339, /**< Shared Int Source ENET0_FRAME1_INT from Connectivity Sub-System */ CONNECTIVITY_ENET0_FRAME2_INT_IRQn = 340, /**< Shared Int Source ENET0_FRAME2_INT from Connectivity Sub-System */ CONNECTIVITY_ENET0_FRAME0_EVENT_INT_IRQn = 341, /**< Shared Int Source ENET0_FRAME0_EVENT_INT from Connectivity Sub-System */ CONNECTIVITY_ENET0_TIMER_INT_IRQn = 342, /**< Shared Int Source ENET0_TIMER_INT from Connectivity Sub-System */ CONNECTIVITY_ENET1_FRAME1_INT_IRQn = 343, /**< Shared Int Source ENET1_FRAME1_INT from Connectivity Sub-System */ CONNECTIVITY_ENET1_FRAME2_INT_IRQn = 344, /**< Shared Int Source ENET1_FRAME2_INT from Connectivity Sub-System */ CONNECTIVITY_ENET1_FRAME0_EVENT_INT_IRQn = 345, /**< Shared Int Source ENET1_FRAME0_EVENT_INT from Connectivity Sub-System */ CONNECTIVITY_ENET1_TIMER_INT_IRQn = 346, /**< Shared Int Source ENET1_TIMER_INT from Connectivity Sub-System */ CONNECTIVITY_DTCP_INT_IRQn = 347, /**< Shared Int Source DTCP_INT from Connectivity Sub-System */ CONNECTIVITY_MLB_INT_IRQn = 348, /**< Shared Int Source MLB_INT from Connectivity Sub-System */ CONNECTIVITY_MLB_AHB_INT_IRQn = 349, /**< Shared Int Source MLB_AHB_INT from Connectivity Sub-System */ CONNECTIVITY_USB_OTG_INT_IRQn = 350, /**< Shared Int Source USB_OTG_INT from Connectivity Sub-System */ CONNECTIVITY_USB_HOST_INT_IRQn = 351, /**< Shared Int Source USB_HOST_INT from Connectivity Sub-System */ CONNECTIVITY_UTMI_INT_IRQn = 352, /**< Shared Int Source UTMI_INT from Connectivity Sub-System */ CONNECTIVITY_WAKEUP_INT_IRQn = 353, /**< Shared Int Source WAKEUP_INT from Connectivity Sub-System */ CONNECTIVITY_USB3_INT_IRQn = 354, /**< Shared Int Source USB3_INT from Connectivity Sub-System */ CONNECTIVITY_ND_FLASH_BCH_INT_IRQn = 355, /**< Shared Int Source ND_FLASH_BCH_INT from Connectivity Sub-System */ CONNECTIVITY_ND_FLASH_GPMI_INT_IRQn = 356, /**< Shared Int Source ND_FLASH_GPMI_INT from Connectivity Sub-System */ CONNECTIVITY_APBHDMA_IRQn = 357, /**< Shared Int Source APBHDMA from Connectivity Sub-System */ CONNECTIVITY_DMA_INT_IRQn = 358, /**< Shared Int Source DMA_INT from Connectivity Sub-System */ CONNECTIVITY_DMA_ERR_INT_IRQn = 359, /**< Shared Int Source DMA_ERR_INT from Connectivity Sub-System */ IMAGING_MSI_INT_IRQn = 371, /**< Shared Int Source MSI_INT from Imaging Sub-System */ IMAGING_PDMA_STREAM0_INT_IRQn = 380, /**< Shared Int Source PDMA_STREAM0_INT from Imaging Sub-System */ IMAGING_PDMA_STREAM1_INT_IRQn = 381, /**< Shared Int Source PDMA_STREAM1_INT from Imaging Sub-System */ IMAGING_PDMA_STREAM2_INT_IRQn = 382, /**< Shared Int Source PDMA_STREAM2_INT from Imaging Sub-System */ IMAGING_PDMA_STREAM3_INT_IRQn = 383, /**< Shared Int Source PDMA_STREAM3_INT from Imaging Sub-System */ IMAGING_PDMA_STREAM4_INT_IRQn = 384, /**< Shared Int Source PDMA_STREAM4_INT from Imaging Sub-System */ IMAGING_PDMA_STREAM5_INT_IRQn = 385, /**< Shared Int Source PDMA_STREAM5_INT from Imaging Sub-System */ IMAGING_PDMA_STREAM6_INT_IRQn = 386, /**< Shared Int Source PDMA_STREAM6_INT from Imaging Sub-System */ IMAGING_PDMA_STREAM7_INT_IRQn = 387, /**< Shared Int Source PDMA_STREAM7_INT from Imaging Sub-System */ IMAGING_MJPEG_ENC0_INT_IRQn = 388, /**< Shared Int Source MJPEG_ENC0_INT from Imaging Sub-System */ IMAGING_MJPEG_ENC1_INT_IRQn = 389, /**< Shared Int Source MJPEG_ENC1_INT from Imaging Sub-System */ IMAGING_MJPEG_ENC2_INT_IRQn = 390, /**< Shared Int Source MJPEG_ENC2_INT from Imaging Sub-System */ IMAGING_MJPEG_ENC3_INT_IRQn = 391, /**< Shared Int Source MJPEG_ENC3_INT from Imaging Sub-System */ IMAGING_MJPEG_DEC0_INT_IRQn = 392, /**< Shared Int Source MJPEG_DEC0_INT from Imaging Sub-System */ IMAGING_MJPEG_DEC1_INT_IRQn = 393, /**< Shared Int Source MJPEG_DEC1_INT from Imaging Sub-System */ IMAGING_MJPEG_DEC2_INT_IRQn = 394, /**< Shared Int Source MJPEG_DEC2_INT from Imaging Sub-System */ IMAGING_MJPEG_DEC3_INT_IRQn = 395, /**< Shared Int Source MJPEG_DEC3_INT from Imaging Sub-System */ AUDIO_SAI0_MOD_INT_IRQn = 397, /**< Shared Int Source SAI0_MOD_INT from Audio Sub-System */ AUDIO_SAI0_DMA_INT_IRQn = 398, /**< Shared Int Source SAI0_DMA_INT from Audio Sub-System */ AUDIO_SAI1_MOD_INT_IRQn = 399, /**< Shared Int Source SAI1_MOD_INT from Audio Sub-System */ AUDIO_SAI1_DMA_INT_IRQn = 400, /**< Shared Int Source SAI1_DMA_INT from Audio Sub-System */ AUDIO_SAI2_MOD_INT_IRQn = 401, /**< Shared Int Source SAI2_MOD_INT from Audio Sub-System */ AUDIO_SAI2_DMA_INT_IRQn = 402, /**< Shared Int Source SAI2_DMA_INT from Audio Sub-System */ MIPI_CSI0_OUT_INT_IRQn = 403, /**< Shared Int Source OUT_INT from MIPI_CSI0 Sub-System */ MIPI_CSI1_OUT_INT_IRQn = 404, /**< Shared Int Source OUT_INT from MIPI_CSI1 Sub-System */ HDMI_RX_OUT_INT_IRQn = 405, /**< Shared Int Source OUT_INT from HDMI_RX Sub-System */ AUDIO_SAI3_MOD_INT_IRQn = 406, /**< Shared Int Source SAI3_MOD_INT from Audio Sub-System */ AUDIO_SAI3_DMA_INT_IRQn = 407, /**< Shared Int Source SAI3_DMA_INT from Audio Sub-System */ AUDIO_SAI_HDMI_RX_MOD_INT_IRQn = 408, /**< Shared Int Source SAI_HDMI_RX_MOD_INT from Audio Sub-System */ AUDIO_SAI_HDMI_RX_DMA_INT_IRQn = 409, /**< Shared Int Source SAI_HDMI_RX_DMA_INT from Audio Sub-System */ AUDIO_SAI_HDMI_TX_MOD_INT_IRQn = 410, /**< Shared Int Source SAI_HDMI_TX_MOD_INT from Audio Sub-System */ AUDIO_SAI_HDMI_TX_DMA_INT_IRQn = 411, /**< Shared Int Source SAI_HDMI_TX_DMA_INT from Audio Sub-System */ AUDIO_SAI6_MOD_INT_IRQn = 412, /**< Shared Int Source SAI6_MOD_INT from Audio Sub-System */ AUDIO_SAI6_DMA_INT_IRQn = 413, /**< Shared Int Source SAI6_DMA_INT from Audio Sub-System */ AUDIO_SAI7_MOD_INT_IRQn = 414, /**< Shared Int Source SAI7_MOD_INT from Audio Sub-System */ AUDIO_SAI7_DMA_INT_IRQn = 415, /**< Shared Int Source SAI7_DMA_INT from Audio Sub-System */ DMA_SPI0_MOD_INT_IRQn = 419, /**< Shared Int Source SPI0_MOD_INT from DMA Sub-System */ DMA_SPI1_MOD_INT_IRQn = 420, /**< Shared Int Source SPI1_MOD_INT from DMA Sub-System */ DMA_SPI2_MOD_INT_IRQn = 421, /**< Shared Int Source SPI2_MOD_INT from DMA Sub-System */ DMA_SPI3_MOD_INT_IRQn = 422, /**< Shared Int Source SPI3_MOD_INT from DMA Sub-System */ DMA_I2C0_MOD_INT_IRQn = 423, /**< Shared Int Source I2C0_MOD_INT from DMA Sub-System */ DMA_I2C1_MOD_INT_IRQn = 424, /**< Shared Int Source I2C1_MOD_INT from DMA Sub-System */ DMA_I2C2_MOD_INT_IRQn = 425, /**< Shared Int Source I2C2_MOD_INT from DMA Sub-System */ DMA_I2C3_MOD_INT_IRQn = 426, /**< Shared Int Source I2C3_MOD_INT from DMA Sub-System */ DMA_I2C4_MOD_INT_IRQn = 427, /**< Shared Int Source I2C4_MOD_INT from DMA Sub-System */ DMA_UART0_MOD_INT_IRQn = 428, /**< Shared Int Source UART0_MOD_INT from DMA Sub-System */ DMA_UART1_MOD_INT_IRQn = 429, /**< Shared Int Source UART1_MOD_INT from DMA Sub-System */ DMA_UART2_MOD_INT_IRQn = 430, /**< Shared Int Source UART2_MOD_INT from DMA Sub-System */ DMA_UART3_MOD_INT_IRQn = 431, /**< Shared Int Source UART3_MOD_INT from DMA Sub-System */ DMA_UART4_MOD_INT_IRQn = 432, /**< Shared Int Source UART4_MOD_INT from DMA Sub-System */ DMA_SIM0_MOD_INT_IRQn = 433, /**< Shared Int Source SIM0_MOD_INT from DMA Sub-System */ DMA_SIM1_MOD_INT_IRQn = 434, /**< Shared Int Source SIM1_MOD_INT from DMA Sub-System */ DMA_FLEXCAN0_MOD_INT_IRQn = 435, /**< Shared Int Source FLEXCAN0_MOD_INT from DMA Sub-System */ DMA_FLEXCAN1_MOD_INT_IRQn = 436, /**< Shared Int Source FLEXCAN1_MOD_INT from DMA Sub-System */ DMA_FLEXCAN2_MOD_INT_IRQn = 437, /**< Shared Int Source FLEXCAN2_MOD_INT from DMA Sub-System */ DMA_FTM0_MOD_INT_IRQn = 438, /**< Shared Int Source FTM0_MOD_INT from DMA Sub-System */ DMA_FTM1_MOD_INT_IRQn = 439, /**< Shared Int Source FTM1_MOD_INT from DMA Sub-System */ DMA_ADC0_MOD_INT_IRQn = 440, /**< Shared Int Source ADC0_MOD_INT from DMA Sub-System */ DMA_ADC1_MOD_INT_IRQn = 441, /**< Shared Int Source ADC1_MOD_INT from DMA Sub-System */ DMA_FLEXCAN0_DMA_INT_IRQn = 442, /**< Shared Int Source FLEXCAN0_DMA_INT from DMA Sub-System */ DMA_FLEXCAN1_DMA_INT_IRQn = 443, /**< Shared Int Source FLEXCAN1_DMA_INT from DMA Sub-System */ DMA_FLEXCAN2_DMA_INT_IRQn = 444, /**< Shared Int Source FLEXCAN2_DMA_INT from DMA Sub-System */ DMA_FTM0_DMA_INT_IRQn = 445, /**< Shared Int Source FTM0_DMA_INT from DMA Sub-System */ DMA_FTM1_DMA_INT_IRQn = 446, /**< Shared Int Source FTM1_DMA_INT from DMA Sub-System */ DMA_ADC0_DMA_INT_IRQn = 447, /**< Shared Int Source ADC0_DMA_INT from DMA Sub-System */ DMA_ADC1_DMA_INT_IRQn = 448, /**< Shared Int Source ADC1_DMA_INT from DMA Sub-System */ AUDIO_EDMA0_INT_IRQn = 451, /**< Shared Int Source eDMA0_INT from Audio Sub-System */ AUDIO_EDMA0_ERR_INT_IRQn = 452, /**< Shared Int Source eDMA0_ERR_INT from Audio Sub-System */ AUDIO_EDMA1_INT_IRQn = 453, /**< Shared Int Source eDMA1_INT from Audio Sub-System */ AUDIO_EDMA1_ERR_INT_IRQn = 454, /**< Shared Int Source eDMA1_ERR_INT from Audio Sub-System */ AUDIO_ASRC0_INT1_IRQn = 455, /**< Shared Int Source ASRC0_INT1 from Audio Sub-System */ AUDIO_ASRC0_INT2_IRQn = 456, /**< Shared Int Source ASRC0_INT2 from Audio Sub-System */ AUDIO_DMA0_CH0_INT_IRQn = 457, /**< Shared Int Source DMA0_CH0_INT from Audio Sub-System */ AUDIO_DMA0_CH1_INT_IRQn = 458, /**< Shared Int Source DMA0_CH1_INT from Audio Sub-System */ AUDIO_DMA0_CH2_INT_IRQn = 459, /**< Shared Int Source DMA0_CH2_INT from Audio Sub-System */ AUDIO_DMA0_CH3_INT_IRQn = 460, /**< Shared Int Source DMA0_CH3_INT from Audio Sub-System */ AUDIO_DMA0_CH4_INT_IRQn = 461, /**< Shared Int Source DMA0_CH4_INT from Audio Sub-System */ AUDIO_DMA0_CH5_INT_IRQn = 462, /**< Shared Int Source DMA0_CH5_INT from Audio Sub-System */ AUDIO_ASRC1_INT1_IRQn = 463, /**< Shared Int Source ASRC1_INT1 from Audio Sub-System */ AUDIO_ASRC1_INT2_IRQn = 464, /**< Shared Int Source ASRC1_INT2 from Audio Sub-System */ AUDIO_DMA1_CH0_INT_IRQn = 465, /**< Shared Int Source DMA1_CH0_INT from Audio Sub-System */ AUDIO_DMA1_CH1_INT_IRQn = 466, /**< Shared Int Source DMA1_CH1_INT from Audio Sub-System */ AUDIO_DMA1_CH2_INT_IRQn = 467, /**< Shared Int Source DMA1_CH2_INT from Audio Sub-System */ AUDIO_DMA1_CH3_INT_IRQn = 468, /**< Shared Int Source DMA1_CH3_INT from Audio Sub-System */ AUDIO_DMA1_CH4_INT_IRQn = 469, /**< Shared Int Source DMA1_CH4_INT from Audio Sub-System */ AUDIO_DMA1_CH5_INT_IRQn = 470, /**< Shared Int Source DMA1_CH5_INT from Audio Sub-System */ AUDIO_ESAI0_INT_IRQn = 471, /**< Shared Int Source ESAI0_INT from Audio Sub-System */ AUDIO_ESAI1_INT_IRQn = 472, /**< Shared Int Source ESAI1_INT from Audio Sub-System */ AUDIO_UNUSED_IRQn = 473, /**< Shared Int Source Unused from Audio Sub-System */ AUDIO_GPT0_INT_IRQn = 474, /**< Shared Int Source GPT0_INT from Audio Sub-System */ AUDIO_GPT1_INT_IRQn = 475, /**< Shared Int Source GPT1_INT from Audio Sub-System */ AUDIO_GPT2_INT_IRQn = 476, /**< Shared Int Source GPT2_INT from Audio Sub-System */ AUDIO_GPT3_INT_IRQn = 477, /**< Shared Int Source GPT3_INT from Audio Sub-System */ AUDIO_GPT4_INT_IRQn = 478, /**< Shared Int Source GPT4_INT from Audio Sub-System */ AUDIO_GPT5_INT_IRQn = 479, /**< Shared Int Source GPT5_INT from Audio Sub-System */ AUDIO_SAI0_INT_IRQn = 480, /**< Shared Int Source SAI0_INT from Audio Sub-System */ AUDIO_SAI1_INT_IRQn = 481, /**< Shared Int Source SAI1_INT from Audio Sub-System */ AUDIO_SAI2_INT_IRQn = 482, /**< Shared Int Source SAI2_INT from Audio Sub-System */ AUDIO_SAI3_INT_IRQn = 483, /**< Shared Int Source SAI3_INT from Audio Sub-System */ AUDIO_SAI_HDMI_RX_INT_IRQn = 484, /**< Shared Int Source SAI_HDMI_RX_INT from Audio Sub-System */ AUDIO_SAI_HDMI_TX_INT_IRQn = 485, /**< Shared Int Source SAI_HDMI_TX_INT from Audio Sub-System */ AUDIO_SAI6_INT_IRQn = 486, /**< Shared Int Source SAI6_INT from Audio Sub-System */ AUDIO_SAI7_INT_IRQn = 487, /**< Shared Int Source SAI7_INT from Audio Sub-System */ AUDIO_SPDIF0_RX_INT_IRQn = 488, /**< Shared Int Source SPDIF0_RX_INT from Audio Sub-System */ AUDIO_SPDIF0_TX_INT_IRQn = 489, /**< Shared Int Source SPDIF0_TX_INT from Audio Sub-System */ AUDIO_SPDIF1_RX_INT_IRQn = 490, /**< Shared Int Source SPDIF1_RX_INT from Audio Sub-System */ AUDIO_SPDIF1_TX_INT_IRQn = 491, /**< Shared Int Source SPDIF1_TX_INT from Audio Sub-System */ AUDIO_ESAI0_MOD_INT_IRQn = 492, /**< Shared Int Source ESAI0_MOD_INT from Audio Sub-System */ AUDIO_ESAI0_DMA_INT_IRQn = 493, /**< Shared Int Source ESAI0_DMA_INT from Audio Sub-System */ AUDIO_ESAI1_MOD_INT_IRQn = 494, /**< Shared Int Source ESAI1_MOD_INT from Audio Sub-System */ AUDIO_ESAI1_DMA_INT_IRQn = 495, /**< Shared Int Source ESAI1_DMA_INT from Audio Sub-System */ DMA_SPI0_DMA_RX_INT_IRQn = 499, /**< Shared Int Source SPI0_DMA_RX_INT from DMA Sub-System */ DMA_SPI0_DMA_TX_INT_IRQn = 500, /**< Shared Int Source SPI0_DMA_TX_INT from DMA Sub-System */ DMA_SPI1_DMA_RX_INT_IRQn = 501, /**< Shared Int Source SPI1_DMA_RX_INT from DMA Sub-System */ DMA_SPI1_DMA_TX_INT_IRQn = 502, /**< Shared Int Source SPI1_DMA_TX_INT from DMA Sub-System */ DMA_SPI2_DMA_RX_INT_IRQn = 503, /**< Shared Int Source SPI2_DMA_RX_INT from DMA Sub-System */ DMA_SPI2_DMA_TX_INT_IRQn = 504, /**< Shared Int Source SPI2_DMA_TX_INT from DMA Sub-System */ DMA_SPI3_DMA_RX_INT_IRQn = 505, /**< Shared Int Source SPI3_DMA_RX_INT from DMA Sub-System */ DMA_SPI3_DMA_TX_INT_IRQn = 506, /**< Shared Int Source SPI3_DMA_TX_INT from DMA Sub-System */ DMA_I2C0_DMA_RX_INT_IRQn = 507, /**< Shared Int Source I2C0_DMA_RX_INT from DMA Sub-System */ DMA_I2C0_DMA_TX_INT_IRQn = 508, /**< Shared Int Source I2C0_DMA_TX_INT from DMA Sub-System */ DMA_I2C1_DMA_RX_INT_IRQn = 509, /**< Shared Int Source I2C1_DMA_RX_INT from DMA Sub-System */ DMA_I2C1_DMA_TX_INT_IRQn = 510, /**< Shared Int Source I2C1_DMA_TX_INT from DMA Sub-System */ DMA_I2C2_DMA_RX_INT_IRQn = 511, /**< Shared Int Source I2C2_DMA_RX_INT from DMA Sub-System */ DMA_I2C2_DMA_TX_INT_IRQn = 512, /**< Shared Int Source I2C2_DMA_TX_INT from DMA Sub-System */ DMA_I2C3_DMA_RX_INT_IRQn = 513, /**< Shared Int Source I2C3_DMA_RX_INT from DMA Sub-System */ DMA_I2C3_DMA_TX_INT_IRQn = 514, /**< Shared Int Source I2C3_DMA_TX_INT from DMA Sub-System */ DMA_I2C4_DMA_RX_INT_IRQn = 515, /**< Shared Int Source I2C4_DMA_RX_INT from DMA Sub-System */ DMA_I2C4_DMA_TX_INT_IRQn = 516, /**< Shared Int Source I2C4_DMA_TX_INT from DMA Sub-System */ DMA_UART0_DMA_RX_INT_IRQn = 517, /**< Shared Int Source UART0_DMA_RX_INT from DMA Sub-System */ DMA_UART0_DMA_TX_INT_IRQn = 518, /**< Shared Int Source UART0_DMA_TX_INT from DMA Sub-System */ DMA_UART1_DMA_RX_INT_IRQn = 519, /**< Shared Int Source UART1_DMA_RX_INT from DMA Sub-System */ DMA_UART1_DMA_TX_INT_IRQn = 520, /**< Shared Int Source UART1_DMA_TX_INT from DMA Sub-System */ DMA_UART2_DMA_RX_INT_IRQn = 521, /**< Shared Int Source UART2_DMA_RX_INT from DMA Sub-System */ DMA_UART2_DMA_TX_INT_IRQn = 522, /**< Shared Int Source UART2_DMA_TX_INT from DMA Sub-System */ DMA_UART3_DMA_RX_INT_IRQn = 523, /**< Shared Int Source UART3_DMA_RX_INT from DMA Sub-System */ DMA_UART3_DMA_TX_INT_IRQn = 524, /**< Shared Int Source UART3_DMA_TX_INT from DMA Sub-System */ DMA_UART4_DMA_RX_INT_IRQn = 525, /**< Shared Int Source UART4_DMA_RX_INT from DMA Sub-System */ DMA_UART4_DMA_TX_INT_IRQn = 526, /**< Shared Int Source UART4_DMA_TX_INT from DMA Sub-System */ DMA_SIM0_DMA_RX_INT_IRQn = 527, /**< Shared Int Source SIM0_DMA_RX_INT from DMA Sub-System */ DMA_SIM0_DMA_TX_INT_IRQn = 528, /**< Shared Int Source SIM0_DMA_TX_INT from DMA Sub-System */ DMA_SIM1_DMA_RX_INT_IRQn = 529, /**< Shared Int Source SIM1_DMA_RX_INT from DMA Sub-System */ DMA_SIM1_DMA_TX_INT_IRQn = 530, /**< Shared Int Source SIM1_DMA_TX_INT from DMA Sub-System */ SECURITY_MU1_A_INT_IRQn = 531, /**< Shared Int Source MU1_A_INT from Security Sub-System */ SECURITY_MU2_A_INT_IRQn = 532, /**< Shared Int Source MU2_A_INT from Security Sub-System */ SECURITY_MU3_A_INT_IRQn = 533, /**< Shared Int Source MU3_A_INT from Security Sub-System */ SECURITY_CAAM_INT0_IRQn = 534, /**< Shared Int Source CAAM_INT0 from Security Sub-System */ SECURITY_CAAM_INT1_IRQn = 535, /**< Shared Int Source CAAM_INT1 from Security Sub-System */ SECURITY_CAAM_INT2_IRQn = 536, /**< Shared Int Source CAAM_INT2 from Security Sub-System */ SECURITY_CAAM_INT3_IRQn = 537, /**< Shared Int Source CAAM_INT3 from Security Sub-System */ SECURITY_CAAM_RTIC_INT_IRQn = 538, /**< Shared Int Source CAAM_RTIC_INT from Security Sub-System */ AUDIO_SPDIF0_RX_MOD_INT_IRQn = 539, /**< Shared Int Source SPDIF0_RX_MOD_INT from Audio Sub-System */ AUDIO_SPDIF0_RX_DMA_INT_IRQn = 540, /**< Shared Int Source SPDIF0_RX_DMA_INT from Audio Sub-System */ AUDIO_SPDIF0_TX_MOD_INT_IRQn = 541, /**< Shared Int Source SPDIF0_TX_MOD_INT from Audio Sub-System */ AUDIO_SPDIF0_TX_DMA_INT_IRQn = 542, /**< Shared Int Source SPDIF0_TX_DMA_INT from Audio Sub-System */ AUDIO_SPDIF1_RX_MOD_INT_IRQn = 543, /**< Shared Int Source SPDIF1_RX_MOD_INT from Audio Sub-System */ AUDIO_SPDIF1_RX_DMA_INT_IRQn = 544, /**< Shared Int Source SPDIF1_RX_DMA_INT from Audio Sub-System */ AUDIO_SPDIF1_TX_MOD_INT_IRQn = 545, /**< Shared Int Source SPDIF1_TX_MOD_INT from Audio Sub-System */ AUDIO_SPDIF1_TX_DMA_INT_IRQn = 546, /**< Shared Int Source SPDIF1_TX_DMA_INT from Audio Sub-System */ VPU_VPU_INT_0_IRQn = 547, /**< Shared Int Source VPU_INT_0 from VPU Sub-System */ VPU_VPU_INT_1_IRQn = 548, /**< Shared Int Source VPU_INT_1 from VPU Sub-System */ VPU_VPU_INT_2_IRQn = 549, /**< Shared Int Source VPU_INT_2 from VPU Sub-System */ VPU_VPU_INT_3_IRQn = 550, /**< Shared Int Source VPU_INT_3 from VPU Sub-System */ VPU_VPU_INT_4_IRQn = 551, /**< Shared Int Source VPU_INT_4 from VPU Sub-System */ VPU_VPU_INT_5_IRQn = 552, /**< Shared Int Source VPU_INT_5 from VPU Sub-System */ VPU_VPU_INT_6_IRQn = 553, /**< Shared Int Source VPU_INT_6 from VPU Sub-System */ VPU_VPU_INT_7_IRQn = 554, /**< Shared Int Source VPU_INT_7 from VPU Sub-System */ M4_1_INTMUX_SOURCE_TPM_IRQn = 564, /**< INTMUX Input source: TPM Interrupt */ M4_1_INTMUX_SOURCE_LPIT_IRQn = 567, /**< INTMUX Input source: LPIT Interrupt */ M4_1_INTMUX_SOURCE_LPUART_IRQn = 570, /**< INTMUX Input source: LPUART Interrupt */ M4_1_INTMUX_SOURCE_LPI2C_IRQn = 572, /**< INTMUX Input source: LPI2C Interrupt */ M4_1_INTMUX_SOURCE_MU0_A3_IRQn = 591, /**< INTMUX Input source: MU0_A3 Interrupt */ M4_1_INTMUX_SOURCE_MU0_A2_IRQn = 592, /**< INTMUX Input source: MU0_A2 Interrupt */ M4_1_INTMUX_SOURCE_MU0_A1_IRQn = 593, /**< INTMUX Input source: MU0_A1 Interrupt */ M4_1_INTMUX_SOURCE_MU0_A0_IRQn = 594 /**< INTMUX Input source: MU0_A0 Interrupt */ } IRQn_Type; /*! * @} */ /* end of group Interrupt_vector_numbers */ /* ---------------------------------------------------------------------------- -- Configuration of the Cortex-M4 Processor and Core Peripherals ---------------------------------------------------------------------------- */ /*! * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-M4 Processor and Core Peripherals * @{ */ #define __CM4_REV 0x0001 /**< Core revision r0p1 */ #define __MPU_PRESENT 1 /**< MPU present or not */ #define __NVIC_PRIO_BITS 4 /**< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1 /**< FPU present or not */ #include "core_cm4.h" /* Core Peripheral Access Layer */ #include "system_MIMX8QM6_cm4_core1.h" /* Device specific configuration file */ /*! * @} */ /* end of group Cortex_Core_Configuration */ /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup Peripheral_access_layer Device Peripheral Access Layer * @{ */ /* ** Start of section using anonymous unions */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #else #pragma push #pragma anon_unions #endif #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=extended #else #error Not supported compiler type #endif /* ---------------------------------------------------------------------------- -- ACM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ACM_Peripheral_Access_Layer ACM Peripheral Access Layer * @{ */ /** ACM - Register Layout Typedef */ typedef struct { __IO uint32_t AUD_CLK0_SEL; /**< Audio Clock Multiplexer #0 selector, offset: 0x0 */ uint8_t RESERVED_0[65532]; __IO uint32_t AUD_CLK1_SEL; /**< Audio Clock Multiplexer #1 selector, offset: 0x10000 */ uint8_t RESERVED_1[65532]; __IO uint32_t MCLKOUT0_SEL; /**< Master Clock Output #0 selector, offset: 0x20000 */ uint8_t RESERVED_2[65532]; __IO uint32_t MCLKOUT1_SEL; /**< Master Clock Output #1 selector, offset: 0x30000 */ uint8_t RESERVED_3[65532]; __IO uint32_t ASRC0_CLK_SEL; /**< ASRC #0 clock selector, offset: 0x40000 */ uint8_t RESERVED_4[131068]; __IO uint32_t ESAI0_CLK_SEL; /**< ESAI #0 clock selector, offset: 0x60000 */ uint8_t RESERVED_5[65532]; __IO uint32_t ESAI1_CLK_SEL; /**< ESAI #1 clock selector, offset: 0x70000 */ uint8_t RESERVED_6[65532]; __IO uint32_t GPT0_CLK_SEL; /**< GP Timer #0 clock selector, offset: 0x80000 */ __IO uint32_t GPT0_CAPIN1_SEL; /**< GP Timer #0 event capture input #1 selector, offset: 0x80004 */ __IO uint32_t GPT0_CAPIN2_SEL; /**< GP Timer #0 event capture input #2 selector, offset: 0x80008 */ uint8_t RESERVED_7[65524]; __IO uint32_t GPT1_CLK_SEL; /**< GP Timer #1 clock selector, offset: 0x90000 */ __IO uint32_t GPT1_CAPIN1_SEL; /**< GP Timer #1 event capture input #1 selector, offset: 0x90004 */ __IO uint32_t GPT1_CAPIN2_SEL; /**< GP Timer #1 event capture input #2 selector, offset: 0x90008 */ uint8_t RESERVED_8[65524]; __IO uint32_t GPT2_CLK_SEL; /**< GP Timer #2 clock selector, offset: 0xA0000 */ __IO uint32_t GPT2_CAPIN1_SEL; /**< GP Timer #2 event capture input #1 selector, offset: 0xA0004 */ __IO uint32_t GPT2_CAPIN2_SEL; /**< GP Timer #2 event capture input #2 selector, offset: 0xA0008 */ uint8_t RESERVED_9[65524]; __IO uint32_t GPT3_CLK_SEL; /**< GP Timer #3 clock selector, offset: 0xB0000 */ __IO uint32_t GPT3_CAPIN1_SEL; /**< GP Timer #3 event capture input #1 selector, offset: 0xB0004 */ __IO uint32_t GPT3_CAPIN2_SEL; /**< GP Timer #3 event capture input #2 selector, offset: 0xB0008 */ uint8_t RESERVED_10[65524]; __IO uint32_t GPT4_CLK_SEL; /**< GP Timer #4 clock selector, offset: 0xC0000 */ __IO uint32_t GPT4_CAPIN1_SEL; /**< GP Timer #4 event capture input #1 selector, offset: 0xC0004 */ __IO uint32_t GPT4_CAPIN2_SEL; /**< GP Timer #4 event capture input #2 selector, offset: 0xC0008 */ uint8_t RESERVED_11[65524]; __IO uint32_t GPT5_CLK_SEL; /**< GP Timer #5 clock selector, offset: 0xD0000 */ __IO uint32_t GPT5_CAPIN1_SEL; /**< GP Timer #5 event capture input #1 selector, offset: 0xD0004 */ __IO uint32_t GPT5_CAPIN2_SEL; /**< GP Timer #5 event capture input #2 selector, offset: 0xD0008 */ uint8_t RESERVED_12[65524]; __IO uint32_t SAI0_MCLK_SEL; /**< SAI #0 clock selector, offset: 0xE0000 */ uint8_t RESERVED_13[65532]; __IO uint32_t SAI1_MCLK_SEL; /**< SAI #1 clock selector, offset: 0xF0000 */ uint8_t RESERVED_14[65532]; __IO uint32_t SAI2_MCLK_SEL; /**< SAI #2 clock selector, offset: 0x100000 */ uint8_t RESERVED_15[65532]; __IO uint32_t SAI3_MCLK_SEL; /**< SAI #3 clock selector, offset: 0x110000 */ uint8_t RESERVED_16[65532]; __IO uint32_t SAI_HDMIRX0_MCLK_SEL; /**< SAI HDMI RX #0 clock selector, offset: 0x120000 */ uint8_t RESERVED_17[65532]; __IO uint32_t SAI_HDMITX0_MCLK_SEL; /**< SAI HDMI TX #0 clock selector, offset: 0x130000 */ __IO uint32_t SAI_HDMITX1_MCLK_SEL; /**< SAI HDMI TX #1 clock selector, offset: 0x130004 */ uint8_t RESERVED_18[65528]; __IO uint32_t SAI6_MCLK_SEL; /**< SAI #6 clock selector, offset: 0x140000 */ uint8_t RESERVED_19[65532]; __IO uint32_t SAI7_MCLK_SEL; /**< SAI #7 clock selector, offset: 0x150000 */ uint8_t RESERVED_20[65532]; __IO uint32_t TSAI0_MCLK_SEL; /**< TSAI #0 clock selector, offset: 0x160000 */ uint8_t RESERVED_21[65532]; __IO uint32_t TSAI1_MCLK_SEL; /**< TSAI #1 clock selector, offset: 0x170000 */ uint8_t RESERVED_22[65532]; __IO uint32_t TSAI2_MCLK_SEL; /**< TSAI #2 clock selector, offset: 0x180000 */ uint8_t RESERVED_23[65532]; __IO uint32_t TSAI3_MCLK_SEL; /**< TSAI #3 clock selector, offset: 0x190000 */ uint8_t RESERVED_24[65532]; __IO uint32_t SPDIF0_TX_CLK_SEL; /**< SPDI/F #0 clock selector, offset: 0x1A0000 */ uint8_t RESERVED_25[65532]; __IO uint32_t SPDIF1_TX_CLK_SEL; /**< SPDI/F #1 clock selector, offset: 0x1B0000 */ uint8_t RESERVED_26[65532]; __IO uint32_t MQS_HMCLK_SEL; /**< MQS HM clock selector, offset: 0x1C0000 */ } ACM_Type; /* ---------------------------------------------------------------------------- -- ACM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ACM_Register_Masks ACM Register Masks * @{ */ /*! @name AUD_CLK0_SEL - Audio Clock Multiplexer #0 selector */ /*! @{ */ #define ACM_AUD_CLK0_SEL_SEL_MASK (0x1FU) #define ACM_AUD_CLK0_SEL_SEL_SHIFT (0U) #define ACM_AUD_CLK0_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK0_SEL_SEL_SHIFT)) & ACM_AUD_CLK0_SEL_SEL_MASK) /*! @} */ /*! @name AUD_CLK1_SEL - Audio Clock Multiplexer #1 selector */ /*! @{ */ #define ACM_AUD_CLK1_SEL_SEL_MASK (0x1FU) #define ACM_AUD_CLK1_SEL_SEL_SHIFT (0U) #define ACM_AUD_CLK1_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK1_SEL_SEL_SHIFT)) & ACM_AUD_CLK1_SEL_SEL_MASK) /*! @} */ /*! @name MCLKOUT0_SEL - Master Clock Output #0 selector */ /*! @{ */ #define ACM_MCLKOUT0_SEL_SEL_MASK (0x7U) #define ACM_MCLKOUT0_SEL_SEL_SHIFT (0U) #define ACM_MCLKOUT0_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT0_SEL_SEL_SHIFT)) & ACM_MCLKOUT0_SEL_SEL_MASK) /*! @} */ /*! @name MCLKOUT1_SEL - Master Clock Output #1 selector */ /*! @{ */ #define ACM_MCLKOUT1_SEL_SEL_MASK (0x7U) #define ACM_MCLKOUT1_SEL_SEL_SHIFT (0U) #define ACM_MCLKOUT1_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT1_SEL_SEL_SHIFT)) & ACM_MCLKOUT1_SEL_SEL_MASK) /*! @} */ /*! @name ASRC0_CLK_SEL - ASRC #0 clock selector */ /*! @{ */ #define ACM_ASRC0_CLK_SEL_SEL_MASK (0x7U) #define ACM_ASRC0_CLK_SEL_SEL_SHIFT (0U) #define ACM_ASRC0_CLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_ASRC0_CLK_SEL_SEL_SHIFT)) & ACM_ASRC0_CLK_SEL_SEL_MASK) /*! @} */ /*! @name ESAI0_CLK_SEL - ESAI #0 clock selector */ /*! @{ */ #define ACM_ESAI0_CLK_SEL_SEL_MASK (0x3U) #define ACM_ESAI0_CLK_SEL_SEL_SHIFT (0U) #define ACM_ESAI0_CLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_ESAI0_CLK_SEL_SEL_SHIFT)) & ACM_ESAI0_CLK_SEL_SEL_MASK) /*! @} */ /*! @name ESAI1_CLK_SEL - ESAI #1 clock selector */ /*! @{ */ #define ACM_ESAI1_CLK_SEL_SEL_MASK (0x3U) #define ACM_ESAI1_CLK_SEL_SEL_SHIFT (0U) #define ACM_ESAI1_CLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_ESAI1_CLK_SEL_SEL_SHIFT)) & ACM_ESAI1_CLK_SEL_SEL_MASK) /*! @} */ /*! @name GPT0_CLK_SEL - GP Timer #0 clock selector */ /*! @{ */ #define ACM_GPT0_CLK_SEL_SEL_MASK (0x7U) #define ACM_GPT0_CLK_SEL_SEL_SHIFT (0U) #define ACM_GPT0_CLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT0_CLK_SEL_SEL_SHIFT)) & ACM_GPT0_CLK_SEL_SEL_MASK) /*! @} */ /*! @name GPT0_CAPIN1_SEL - GP Timer #0 event capture input #1 selector */ /*! @{ */ #define ACM_GPT0_CAPIN1_SEL_SEL_MASK (0x1FU) #define ACM_GPT0_CAPIN1_SEL_SEL_SHIFT (0U) #define ACM_GPT0_CAPIN1_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT0_CAPIN1_SEL_SEL_SHIFT)) & ACM_GPT0_CAPIN1_SEL_SEL_MASK) /*! @} */ /*! @name GPT0_CAPIN2_SEL - GP Timer #0 event capture input #2 selector */ /*! @{ */ #define ACM_GPT0_CAPIN2_SEL_SEL_MASK (0x1FU) #define ACM_GPT0_CAPIN2_SEL_SEL_SHIFT (0U) #define ACM_GPT0_CAPIN2_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT0_CAPIN2_SEL_SEL_SHIFT)) & ACM_GPT0_CAPIN2_SEL_SEL_MASK) /*! @} */ /*! @name GPT1_CLK_SEL - GP Timer #1 clock selector */ /*! @{ */ #define ACM_GPT1_CLK_SEL_SEL_MASK (0x7U) #define ACM_GPT1_CLK_SEL_SEL_SHIFT (0U) #define ACM_GPT1_CLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT1_CLK_SEL_SEL_SHIFT)) & ACM_GPT1_CLK_SEL_SEL_MASK) /*! @} */ /*! @name GPT1_CAPIN1_SEL - GP Timer #1 event capture input #1 selector */ /*! @{ */ #define ACM_GPT1_CAPIN1_SEL_SEL_MASK (0x1FU) #define ACM_GPT1_CAPIN1_SEL_SEL_SHIFT (0U) #define ACM_GPT1_CAPIN1_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT1_CAPIN1_SEL_SEL_SHIFT)) & ACM_GPT1_CAPIN1_SEL_SEL_MASK) /*! @} */ /*! @name GPT1_CAPIN2_SEL - GP Timer #1 event capture input #2 selector */ /*! @{ */ #define ACM_GPT1_CAPIN2_SEL_SEL_MASK (0x1FU) #define ACM_GPT1_CAPIN2_SEL_SEL_SHIFT (0U) #define ACM_GPT1_CAPIN2_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT1_CAPIN2_SEL_SEL_SHIFT)) & ACM_GPT1_CAPIN2_SEL_SEL_MASK) /*! @} */ /*! @name GPT2_CLK_SEL - GP Timer #2 clock selector */ /*! @{ */ #define ACM_GPT2_CLK_SEL_SEL_MASK (0x7U) #define ACM_GPT2_CLK_SEL_SEL_SHIFT (0U) #define ACM_GPT2_CLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT2_CLK_SEL_SEL_SHIFT)) & ACM_GPT2_CLK_SEL_SEL_MASK) /*! @} */ /*! @name GPT2_CAPIN1_SEL - GP Timer #2 event capture input #1 selector */ /*! @{ */ #define ACM_GPT2_CAPIN1_SEL_SEL_MASK (0x1FU) #define ACM_GPT2_CAPIN1_SEL_SEL_SHIFT (0U) #define ACM_GPT2_CAPIN1_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT2_CAPIN1_SEL_SEL_SHIFT)) & ACM_GPT2_CAPIN1_SEL_SEL_MASK) /*! @} */ /*! @name GPT2_CAPIN2_SEL - GP Timer #2 event capture input #2 selector */ /*! @{ */ #define ACM_GPT2_CAPIN2_SEL_SEL_MASK (0x1FU) #define ACM_GPT2_CAPIN2_SEL_SEL_SHIFT (0U) #define ACM_GPT2_CAPIN2_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT2_CAPIN2_SEL_SEL_SHIFT)) & ACM_GPT2_CAPIN2_SEL_SEL_MASK) /*! @} */ /*! @name GPT3_CLK_SEL - GP Timer #3 clock selector */ /*! @{ */ #define ACM_GPT3_CLK_SEL_SEL_MASK (0x7U) #define ACM_GPT3_CLK_SEL_SEL_SHIFT (0U) #define ACM_GPT3_CLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT3_CLK_SEL_SEL_SHIFT)) & ACM_GPT3_CLK_SEL_SEL_MASK) /*! @} */ /*! @name GPT3_CAPIN1_SEL - GP Timer #3 event capture input #1 selector */ /*! @{ */ #define ACM_GPT3_CAPIN1_SEL_SEL_MASK (0x1FU) #define ACM_GPT3_CAPIN1_SEL_SEL_SHIFT (0U) #define ACM_GPT3_CAPIN1_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT3_CAPIN1_SEL_SEL_SHIFT)) & ACM_GPT3_CAPIN1_SEL_SEL_MASK) /*! @} */ /*! @name GPT3_CAPIN2_SEL - GP Timer #3 event capture input #2 selector */ /*! @{ */ #define ACM_GPT3_CAPIN2_SEL_SEL_MASK (0x1FU) #define ACM_GPT3_CAPIN2_SEL_SEL_SHIFT (0U) #define ACM_GPT3_CAPIN2_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT3_CAPIN2_SEL_SEL_SHIFT)) & ACM_GPT3_CAPIN2_SEL_SEL_MASK) /*! @} */ /*! @name GPT4_CLK_SEL - GP Timer #4 clock selector */ /*! @{ */ #define ACM_GPT4_CLK_SEL_SEL_MASK (0x7U) #define ACM_GPT4_CLK_SEL_SEL_SHIFT (0U) #define ACM_GPT4_CLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT4_CLK_SEL_SEL_SHIFT)) & ACM_GPT4_CLK_SEL_SEL_MASK) /*! @} */ /*! @name GPT4_CAPIN1_SEL - GP Timer #4 event capture input #1 selector */ /*! @{ */ #define ACM_GPT4_CAPIN1_SEL_SEL_MASK (0x1FU) #define ACM_GPT4_CAPIN1_SEL_SEL_SHIFT (0U) #define ACM_GPT4_CAPIN1_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT4_CAPIN1_SEL_SEL_SHIFT)) & ACM_GPT4_CAPIN1_SEL_SEL_MASK) /*! @} */ /*! @name GPT4_CAPIN2_SEL - GP Timer #4 event capture input #2 selector */ /*! @{ */ #define ACM_GPT4_CAPIN2_SEL_SEL_MASK (0x1FU) #define ACM_GPT4_CAPIN2_SEL_SEL_SHIFT (0U) #define ACM_GPT4_CAPIN2_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT4_CAPIN2_SEL_SEL_SHIFT)) & ACM_GPT4_CAPIN2_SEL_SEL_MASK) /*! @} */ /*! @name GPT5_CLK_SEL - GP Timer #5 clock selector */ /*! @{ */ #define ACM_GPT5_CLK_SEL_SEL_MASK (0x7U) #define ACM_GPT5_CLK_SEL_SEL_SHIFT (0U) #define ACM_GPT5_CLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT5_CLK_SEL_SEL_SHIFT)) & ACM_GPT5_CLK_SEL_SEL_MASK) /*! @} */ /*! @name GPT5_CAPIN1_SEL - GP Timer #5 event capture input #1 selector */ /*! @{ */ #define ACM_GPT5_CAPIN1_SEL_SEL_MASK (0x1FU) #define ACM_GPT5_CAPIN1_SEL_SEL_SHIFT (0U) #define ACM_GPT5_CAPIN1_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT5_CAPIN1_SEL_SEL_SHIFT)) & ACM_GPT5_CAPIN1_SEL_SEL_MASK) /*! @} */ /*! @name GPT5_CAPIN2_SEL - GP Timer #5 event capture input #2 selector */ /*! @{ */ #define ACM_GPT5_CAPIN2_SEL_SEL_MASK (0x1FU) #define ACM_GPT5_CAPIN2_SEL_SEL_SHIFT (0U) #define ACM_GPT5_CAPIN2_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT5_CAPIN2_SEL_SEL_SHIFT)) & ACM_GPT5_CAPIN2_SEL_SEL_MASK) /*! @} */ /*! @name SAI0_MCLK_SEL - SAI #0 clock selector */ /*! @{ */ #define ACM_SAI0_MCLK_SEL_SEL_MASK (0x3U) #define ACM_SAI0_MCLK_SEL_SEL_SHIFT (0U) #define ACM_SAI0_MCLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SAI0_MCLK_SEL_SEL_SHIFT)) & ACM_SAI0_MCLK_SEL_SEL_MASK) /*! @} */ /*! @name SAI1_MCLK_SEL - SAI #1 clock selector */ /*! @{ */ #define ACM_SAI1_MCLK_SEL_SEL_MASK (0x3U) #define ACM_SAI1_MCLK_SEL_SEL_SHIFT (0U) #define ACM_SAI1_MCLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SAI1_MCLK_SEL_SEL_SHIFT)) & ACM_SAI1_MCLK_SEL_SEL_MASK) /*! @} */ /*! @name SAI2_MCLK_SEL - SAI #2 clock selector */ /*! @{ */ #define ACM_SAI2_MCLK_SEL_SEL_MASK (0x3U) #define ACM_SAI2_MCLK_SEL_SEL_SHIFT (0U) #define ACM_SAI2_MCLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SAI2_MCLK_SEL_SEL_SHIFT)) & ACM_SAI2_MCLK_SEL_SEL_MASK) /*! @} */ /*! @name SAI3_MCLK_SEL - SAI #3 clock selector */ /*! @{ */ #define ACM_SAI3_MCLK_SEL_SEL_MASK (0x3U) #define ACM_SAI3_MCLK_SEL_SEL_SHIFT (0U) #define ACM_SAI3_MCLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SAI3_MCLK_SEL_SEL_SHIFT)) & ACM_SAI3_MCLK_SEL_SEL_MASK) /*! @} */ /*! @name SAI_HDMIRX0_MCLK_SEL - SAI HDMI RX #0 clock selector */ /*! @{ */ #define ACM_SAI_HDMIRX0_MCLK_SEL_SEL_MASK (0x3U) #define ACM_SAI_HDMIRX0_MCLK_SEL_SEL_SHIFT (0U) #define ACM_SAI_HDMIRX0_MCLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SAI_HDMIRX0_MCLK_SEL_SEL_SHIFT)) & ACM_SAI_HDMIRX0_MCLK_SEL_SEL_MASK) /*! @} */ /*! @name SAI_HDMITX0_MCLK_SEL - SAI HDMI TX #0 clock selector */ /*! @{ */ #define ACM_SAI_HDMITX0_MCLK_SEL_SEL_MASK (0x3U) #define ACM_SAI_HDMITX0_MCLK_SEL_SEL_SHIFT (0U) #define ACM_SAI_HDMITX0_MCLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SAI_HDMITX0_MCLK_SEL_SEL_SHIFT)) & ACM_SAI_HDMITX0_MCLK_SEL_SEL_MASK) /*! @} */ /*! @name SAI_HDMITX1_MCLK_SEL - SAI HDMI TX #1 clock selector */ /*! @{ */ #define ACM_SAI_HDMITX1_MCLK_SEL_SEL_MASK (0x3U) #define ACM_SAI_HDMITX1_MCLK_SEL_SEL_SHIFT (0U) #define ACM_SAI_HDMITX1_MCLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SAI_HDMITX1_MCLK_SEL_SEL_SHIFT)) & ACM_SAI_HDMITX1_MCLK_SEL_SEL_MASK) /*! @} */ /*! @name SAI6_MCLK_SEL - SAI #6 clock selector */ /*! @{ */ #define ACM_SAI6_MCLK_SEL_SEL_MASK (0x3U) #define ACM_SAI6_MCLK_SEL_SEL_SHIFT (0U) #define ACM_SAI6_MCLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SAI6_MCLK_SEL_SEL_SHIFT)) & ACM_SAI6_MCLK_SEL_SEL_MASK) /*! @} */ /*! @name SAI7_MCLK_SEL - SAI #7 clock selector */ /*! @{ */ #define ACM_SAI7_MCLK_SEL_SEL_MASK (0x3U) #define ACM_SAI7_MCLK_SEL_SEL_SHIFT (0U) #define ACM_SAI7_MCLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SAI7_MCLK_SEL_SEL_SHIFT)) & ACM_SAI7_MCLK_SEL_SEL_MASK) /*! @} */ /*! @name TSAI0_MCLK_SEL - TSAI #0 clock selector */ /*! @{ */ #define ACM_TSAI0_MCLK_SEL_SEL_MASK (0x3U) #define ACM_TSAI0_MCLK_SEL_SEL_SHIFT (0U) #define ACM_TSAI0_MCLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_TSAI0_MCLK_SEL_SEL_SHIFT)) & ACM_TSAI0_MCLK_SEL_SEL_MASK) /*! @} */ /*! @name TSAI1_MCLK_SEL - TSAI #1 clock selector */ /*! @{ */ #define ACM_TSAI1_MCLK_SEL_SEL_MASK (0x3U) #define ACM_TSAI1_MCLK_SEL_SEL_SHIFT (0U) #define ACM_TSAI1_MCLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_TSAI1_MCLK_SEL_SEL_SHIFT)) & ACM_TSAI1_MCLK_SEL_SEL_MASK) /*! @} */ /*! @name TSAI2_MCLK_SEL - TSAI #2 clock selector */ /*! @{ */ #define ACM_TSAI2_MCLK_SEL_SEL_MASK (0x3U) #define ACM_TSAI2_MCLK_SEL_SEL_SHIFT (0U) #define ACM_TSAI2_MCLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_TSAI2_MCLK_SEL_SEL_SHIFT)) & ACM_TSAI2_MCLK_SEL_SEL_MASK) /*! @} */ /*! @name TSAI3_MCLK_SEL - TSAI #3 clock selector */ /*! @{ */ #define ACM_TSAI3_MCLK_SEL_SEL_MASK (0x3U) #define ACM_TSAI3_MCLK_SEL_SEL_SHIFT (0U) #define ACM_TSAI3_MCLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_TSAI3_MCLK_SEL_SEL_SHIFT)) & ACM_TSAI3_MCLK_SEL_SEL_MASK) /*! @} */ /*! @name SPDIF0_TX_CLK_SEL - SPDI/F #0 clock selector */ /*! @{ */ #define ACM_SPDIF0_TX_CLK_SEL_SEL_MASK (0x3U) #define ACM_SPDIF0_TX_CLK_SEL_SEL_SHIFT (0U) #define ACM_SPDIF0_TX_CLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SPDIF0_TX_CLK_SEL_SEL_SHIFT)) & ACM_SPDIF0_TX_CLK_SEL_SEL_MASK) /*! @} */ /*! @name SPDIF1_TX_CLK_SEL - SPDI/F #1 clock selector */ /*! @{ */ #define ACM_SPDIF1_TX_CLK_SEL_SEL_MASK (0x3U) #define ACM_SPDIF1_TX_CLK_SEL_SEL_SHIFT (0U) #define ACM_SPDIF1_TX_CLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SPDIF1_TX_CLK_SEL_SEL_SHIFT)) & ACM_SPDIF1_TX_CLK_SEL_SEL_MASK) /*! @} */ /*! @name MQS_HMCLK_SEL - MQS HM clock selector */ /*! @{ */ #define ACM_MQS_HMCLK_SEL_SEL_MASK (0x3U) #define ACM_MQS_HMCLK_SEL_SEL_SHIFT (0U) #define ACM_MQS_HMCLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MQS_HMCLK_SEL_SEL_SHIFT)) & ACM_MQS_HMCLK_SEL_SEL_MASK) /*! @} */ /*! * @} */ /* end of group ACM_Register_Masks */ /* ACM - Peripheral instance base addresses */ /** Peripheral AUDIO__ACM base address */ #define AUDIO__ACM_BASE (0x59E00000u) /** Peripheral AUDIO__ACM base pointer */ #define AUDIO__ACM ((ACM_Type *)AUDIO__ACM_BASE) /** Array initializer of ACM peripheral base addresses */ #define ACM_BASE_ADDRS { AUDIO__ACM_BASE } /** Array initializer of ACM peripheral base pointers */ #define ACM_BASE_PTRS { AUDIO__ACM } /*! * @} */ /* end of group ACM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ADC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer * @{ */ /** ADC - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ uint8_t RESERVED_1[8]; __IO uint32_t FCTRL; /**< ADC FIFO Control Register, offset: 0x30 */ __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ uint8_t RESERVED_2[136]; __IO uint32_t TCTRL[8]; /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_3[32]; struct { /* offset: 0x100, array step: 0x8 */ __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ } CMD[15]; uint8_t RESERVED_4[136]; __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_5[240]; __I uint32_t RESFIFO; /**< ADC Data Result FIFO Register, offset: 0x300 */ uint8_t RESERVED_6[3320]; __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */ } ADC_Type; /* ---------------------------------------------------------------------------- -- ADC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Masks ADC Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define ADC_VERID_RES_MASK (0x1U) #define ADC_VERID_RES_SHIFT (0U) /*! RES - Resolution * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. * 0b1..Up to 16-bit differential/15-bit single ended resolution supported. */ #define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) #define ADC_VERID_DIFFEN_MASK (0x2U) #define ADC_VERID_DIFFEN_SHIFT (1U) /*! DIFFEN - Differential Supported * 0b0..Differential operation not supported. * 0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented. */ #define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) #define ADC_VERID_MVI_MASK (0x8U) #define ADC_VERID_MVI_SHIFT (3U) /*! MVI - Multi Vref Implemented * 0b0..Single voltage reference high (VREFH) input supported. * 0b1..Multiple voltage reference high (VREFH) inputs supported. */ #define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) #define ADC_VERID_CSW_MASK (0x70U) #define ADC_VERID_CSW_SHIFT (4U) /*! CSW - Channel Scale Width * 0b000..Channel scaling not supported. * 0b001..Channel scaling supported. 1-bit CSCALE control field. * 0b110..Channel scaling supported. 6-bit CSCALE control field. */ #define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) #define ADC_VERID_VR1RNGI_MASK (0x100U) #define ADC_VERID_VR1RNGI_SHIFT (8U) /*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. * 0b1..Range control required. CFG[VREF1RNG] is implemented. */ #define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) #define ADC_VERID_IADCKI_MASK (0x200U) #define ADC_VERID_IADCKI_SHIFT (9U) /*! IADCKI - Internal ADC Clock implemented * 0b0..Internal clock source not implemented. * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. */ #define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) #define ADC_VERID_CALOFSI_MASK (0x400U) #define ADC_VERID_CALOFSI_SHIFT (10U) /*! CALOFSI - Calibration Offset Function Implemented * 0b0..Offset calibration and offset trimming not implemented. * 0b1..Offset calibration and offset trimming implemented. */ #define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) #define ADC_VERID_MINOR_MASK (0xFF0000U) #define ADC_VERID_MINOR_SHIFT (16U) #define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) #define ADC_VERID_MAJOR_MASK (0xFF000000U) #define ADC_VERID_MAJOR_SHIFT (24U) #define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define ADC_PARAM_TRIG_NUM_MASK (0xFFU) #define ADC_PARAM_TRIG_NUM_SHIFT (0U) #define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) #define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) #define ADC_PARAM_FIFOSIZE_SHIFT (8U) /*! FIFOSIZE - Result FIFO Depth * 0b00000001..Result FIFO depth = 1 dataword. * 0b00000100..Result FIFO depth = 4 datawords. * 0b00001000..Result FIFO depth = 8 datawords. * 0b00010000..Result FIFO depth = 16 datawords. * 0b00100000..Result FIFO depth = 32 datawords. * 0b01000000..Result FIFO depth = 64 datawords. */ #define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) #define ADC_PARAM_CV_NUM_MASK (0xFF0000U) #define ADC_PARAM_CV_NUM_SHIFT (16U) #define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) #define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) #define ADC_PARAM_CMD_NUM_SHIFT (24U) #define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) /*! @} */ /*! @name CTRL - ADC Control Register */ /*! @{ */ #define ADC_CTRL_ADCEN_MASK (0x1U) #define ADC_CTRL_ADCEN_SHIFT (0U) /*! ADCEN - ADC Enable * 0b0..ADC is disabled. * 0b1..ADC is enabled. */ #define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) #define ADC_CTRL_RST_MASK (0x2U) #define ADC_CTRL_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..ADC logic is not reset. * 0b1..ADC logic is reset. */ #define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) #define ADC_CTRL_DOZEN_MASK (0x4U) #define ADC_CTRL_DOZEN_SHIFT (2U) /*! DOZEN - Doze Enable * 0b0..ADC is enabled in Doze mode. * 0b1..ADC is disabled in Doze mode. */ #define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) #define ADC_CTRL_RSTFIFO_MASK (0x100U) #define ADC_CTRL_RSTFIFO_SHIFT (8U) /*! RSTFIFO - Reset FIFO * 0b0..No effect. * 0b1..FIFO is reset. */ #define ADC_CTRL_RSTFIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK) /*! @} */ /*! @name STAT - ADC Status Register */ /*! @{ */ #define ADC_STAT_RDY_MASK (0x1U) #define ADC_STAT_RDY_SHIFT (0U) /*! RDY - Result FIFO Ready Flag * 0b0..Result FIFO data level not above watermark level. * 0b1..Result FIFO holding data above watermark level. */ #define ADC_STAT_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK) #define ADC_STAT_FOF_MASK (0x2U) #define ADC_STAT_FOF_SHIFT (1U) /*! FOF - Result FIFO Overflow Flag * 0b0..No result FIFO overflow has occurred since the last time the flag was cleared. * 0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared. */ #define ADC_STAT_FOF(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK) #define ADC_STAT_TRGACT_MASK (0x70000U) #define ADC_STAT_TRGACT_SHIFT (16U) /*! TRGACT - Trigger Active * 0b000..Command (sequence) associated with Trigger 0 currently being executed. * 0b001..Command (sequence) associated with Trigger 1 currently being executed. * 0b010..Command (sequence) associated with Trigger 2 currently being executed. * 0b011-0b111..Command (sequence) from the associated Trigger number is currently being executed. */ #define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) #define ADC_STAT_CMDACT_MASK (0xF000000U) #define ADC_STAT_CMDACT_SHIFT (24U) /*! CMDACT - Command Active * 0b0000..No command is currently in progress. * 0b0001..Command 1 currently being executed. * 0b0010..Command 2 currently being executed. * 0b0011-0b1111..Associated command number is currently being executed. */ #define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) /*! @} */ /*! @name IE - Interrupt Enable Register */ /*! @{ */ #define ADC_IE_FWMIE_MASK (0x1U) #define ADC_IE_FWMIE_SHIFT (0U) /*! FWMIE - FIFO Watermark Interrupt Enable * 0b0..FIFO watermark interrupts are not enabled. * 0b1..FIFO watermark interrupts are enabled. */ #define ADC_IE_FWMIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK) #define ADC_IE_FOFIE_MASK (0x2U) #define ADC_IE_FOFIE_SHIFT (1U) /*! FOFIE - Result FIFO Overflow Interrupt Enable * 0b0..FIFO overflow interrupts are not enabled. * 0b1..FIFO overflow interrupts are enabled. */ #define ADC_IE_FOFIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK) /*! @} */ /*! @name DE - DMA Enable Register */ /*! @{ */ #define ADC_DE_FWMDE_MASK (0x1U) #define ADC_DE_FWMDE_SHIFT (0U) /*! FWMDE - FIFO Watermark DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled. */ #define ADC_DE_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK) /*! @} */ /*! @name CFG - ADC Configuration Register */ /*! @{ */ #define ADC_CFG_TPRICTRL_MASK (0x1U) #define ADC_CFG_TPRICTRL_SHIFT (0U) /*! TPRICTRL - ADC trigger priority control * 0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. * 0b1..If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true conversion. */ #define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) #define ADC_CFG_PWRSEL_MASK (0x30U) #define ADC_CFG_PWRSEL_SHIFT (4U) /*! PWRSEL - Power Configuration Select * 0b00..Level 1 (Lowest power setting) * 0b01..Level 2 * 0b10..Level 3 * 0b11..Level 4 (Highest power setting) */ #define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) #define ADC_CFG_REFSEL_MASK (0xC0U) #define ADC_CFG_REFSEL_SHIFT (6U) /*! REFSEL - Voltage Reference Selection * 0b00..(Default) Option 1 setting. * 0b01..Option 2 setting. * 0b10..Option 3 setting. * 0b11..Reserved */ #define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) #define ADC_CFG_PUDLY_MASK (0xFF0000U) #define ADC_CFG_PUDLY_SHIFT (16U) #define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) #define ADC_CFG_PWREN_MASK (0x10000000U) #define ADC_CFG_PWREN_SHIFT (28U) /*! PWREN - ADC Analog Pre-Enable * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any detected trigger does not begin ADC operation until the power up delay time has passed. */ #define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) /*! @} */ /*! @name PAUSE - ADC Pause Register */ /*! @{ */ #define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) #define ADC_PAUSE_PAUSEDLY_SHIFT (0U) #define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) #define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) #define ADC_PAUSE_PAUSEEN_SHIFT (31U) /*! PAUSEEN - PAUSE Option Enable * 0b0..Pause operation disabled * 0b1..Pause operation enabled */ #define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) /*! @} */ /*! @name FCTRL - ADC FIFO Control Register */ /*! @{ */ #define ADC_FCTRL_FCOUNT_MASK (0x1FU) #define ADC_FCTRL_FCOUNT_SHIFT (0U) #define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) #define ADC_FCTRL_FWMARK_MASK (0xF0000U) #define ADC_FCTRL_FWMARK_SHIFT (16U) #define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) /*! @} */ /*! @name SWTRIG - Software Trigger Register */ /*! @{ */ #define ADC_SWTRIG_SWT0_MASK (0x1U) #define ADC_SWTRIG_SWT0_SHIFT (0U) /*! SWT0 - Software trigger 0 event * 0b0..No trigger 0 event generated. * 0b1..Trigger 0 event generated. */ #define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) #define ADC_SWTRIG_SWT1_MASK (0x2U) #define ADC_SWTRIG_SWT1_SHIFT (1U) /*! SWT1 - Software trigger 1 event * 0b0..No trigger 1 event generated. * 0b1..Trigger 1 event generated. */ #define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) #define ADC_SWTRIG_SWT2_MASK (0x4U) #define ADC_SWTRIG_SWT2_SHIFT (2U) /*! SWT2 - Software trigger 2 event * 0b0..No trigger 2 event generated. * 0b1..Trigger 2 event generated. */ #define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) #define ADC_SWTRIG_SWT3_MASK (0x8U) #define ADC_SWTRIG_SWT3_SHIFT (3U) /*! SWT3 - Software trigger 3 event * 0b0..No trigger 3 event generated. * 0b1..Trigger 3 event generated. */ #define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) #define ADC_SWTRIG_SWT4_MASK (0x10U) #define ADC_SWTRIG_SWT4_SHIFT (4U) /*! SWT4 - Software trigger 4 event * 0b0..No trigger 4 event generated. * 0b1..Trigger 4 event generated. */ #define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) #define ADC_SWTRIG_SWT5_MASK (0x20U) #define ADC_SWTRIG_SWT5_SHIFT (5U) /*! SWT5 - Software trigger 5 event * 0b0..No trigger 5 event generated. * 0b1..Trigger 5 event generated. */ #define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) #define ADC_SWTRIG_SWT6_MASK (0x40U) #define ADC_SWTRIG_SWT6_SHIFT (6U) /*! SWT6 - Software trigger 6 event * 0b0..No trigger 6 event generated. * 0b1..Trigger 6 event generated. */ #define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) #define ADC_SWTRIG_SWT7_MASK (0x80U) #define ADC_SWTRIG_SWT7_SHIFT (7U) /*! SWT7 - Software trigger 7 event * 0b0..No trigger 7 event generated. * 0b1..Trigger 7 event generated. */ #define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) /*! @} */ /*! @name TCTRL - Trigger Control Register */ /*! @{ */ #define ADC_TCTRL_HTEN_MASK (0x1U) #define ADC_TCTRL_HTEN_SHIFT (0U) /*! HTEN - Trigger enable * 0b0..Hardware trigger source disabled * 0b1..Hardware trigger source enabled */ #define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) #define ADC_TCTRL_TPRI_MASK (0x700U) #define ADC_TCTRL_TPRI_SHIFT (8U) /*! TPRI - Trigger priority setting * 0b000..Set to highest priority, Level 1 * 0b001-0b110..Set to corresponding priority level * 0b111..Set to lowest priority, Level 8 */ #define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) #define ADC_TCTRL_TDLY_MASK (0xF0000U) #define ADC_TCTRL_TDLY_SHIFT (16U) #define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) #define ADC_TCTRL_TCMD_MASK (0xF000000U) #define ADC_TCTRL_TCMD_SHIFT (24U) /*! TCMD - Trigger command select * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. * 0b0001..CMD1 is executed * 0b0010-0b1110..Corresponding CMD is executed * 0b1111..CMD15 is executed */ #define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) /*! @} */ /* The count of ADC_TCTRL */ #define ADC_TCTRL_COUNT (8U) /*! @name CMDL - ADC Command Low Buffer Register */ /*! @{ */ #define ADC_CMDL_ADCH_MASK (0x1FU) #define ADC_CMDL_ADCH_SHIFT (0U) /*! ADCH - Input channel select * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. */ #define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) #define ADC_CMDL_ABSEL_MASK (0x20U) #define ADC_CMDL_ABSEL_SHIFT (5U) /*! ABSEL - A-side vs. B-side Select * 0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). * 0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). */ #define ADC_CMDL_ABSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK) #define ADC_CMDL_DIFF_MASK (0x40U) #define ADC_CMDL_DIFF_SHIFT (6U) /*! DIFF - Differential Mode Enable * 0b0..Single-ended mode. * 0b1..Differential mode. */ #define ADC_CMDL_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK) #define ADC_CMDL_CSCALE_MASK (0x2000U) #define ADC_CMDL_CSCALE_SHIFT (13U) /*! CSCALE - Channel Scale * 0b0..Scale selected analog channel (Factor of 30/64) * 0b1..(Default) Full scale (Factor of 1) */ #define ADC_CMDL_CSCALE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK) /*! @} */ /* The count of ADC_CMDL */ #define ADC_CMDL_COUNT (15U) /*! @name CMDH - ADC Command High Buffer Register */ /*! @{ */ #define ADC_CMDH_CMPEN_MASK (0x3U) #define ADC_CMDH_CMPEN_SHIFT (0U) /*! CMPEN - Compare Function Enable * 0b00..Compare disabled. * 0b01..Reserved * 0b10..Compare enabled. Store on true. * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. */ #define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) #define ADC_CMDH_LWI_MASK (0x80U) #define ADC_CMDH_LWI_SHIFT (7U) /*! LWI - Loop with Increment * 0b0..Auto channel increment disabled * 0b1..Auto channel increment enabled */ #define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) #define ADC_CMDH_STS_MASK (0x700U) #define ADC_CMDH_STS_SHIFT (8U) #define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) #define ADC_CMDH_AVGS_MASK (0x7000U) #define ADC_CMDH_AVGS_SHIFT (12U) /*! AVGS - Hardware Average Select * 0b000..Single conversion. * 0b001..2 conversions averaged. * 0b010..4 conversions averaged. * 0b011..8 conversions averaged. * 0b100..16 conversions averaged. * 0b101..32 conversions averaged. * 0b110..64 conversions averaged. * 0b111..128 conversions averaged. */ #define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) #define ADC_CMDH_LOOP_MASK (0xF0000U) #define ADC_CMDH_LOOP_SHIFT (16U) /*! LOOP - Loop Count Select * 0b0000..Looping not enabled. Command executes 1 time. * 0b0001..Loop 1 time. Command executes 2 times. * 0b0010..Loop 2 times. Command executes 3 times. * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. * 0b1111..Loop 15 times. Command executes 16 times. */ #define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) #define ADC_CMDH_NEXT_MASK (0xF000000U) #define ADC_CMDH_NEXT_SHIFT (24U) /*! NEXT - Next Command Select * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. * 0b0001..Select CMD1 command buffer register as next command. * 0b0010-0b1110..Select corresponding CMD command buffer register as next command * 0b1111..Select CMD15 command buffer register as next command. */ #define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) /*! @} */ /* The count of ADC_CMDH */ #define ADC_CMDH_COUNT (15U) /*! @name CV - Compare Value Register */ /*! @{ */ #define ADC_CV_CVL_MASK (0xFFFFU) #define ADC_CV_CVL_SHIFT (0U) #define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) #define ADC_CV_CVH_MASK (0xFFFF0000U) #define ADC_CV_CVH_SHIFT (16U) #define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) /*! @} */ /* The count of ADC_CV */ #define ADC_CV_COUNT (4U) /*! @name RESFIFO - ADC Data Result FIFO Register */ /*! @{ */ #define ADC_RESFIFO_D_MASK (0xFFFFU) #define ADC_RESFIFO_D_SHIFT (0U) #define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) #define ADC_RESFIFO_TSRC_MASK (0x70000U) #define ADC_RESFIFO_TSRC_SHIFT (16U) /*! TSRC - Trigger Source * 0b000..Trigger source 0 initiated this conversion. * 0b001..Trigger source 1 initiated this conversion. * 0b010-0b110..Corresponding trigger source initiated this conversion. * 0b111..Trigger source 7 initiated this conversion. */ #define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) #define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) #define ADC_RESFIFO_LOOPCNT_SHIFT (20U) /*! LOOPCNT - Loop count value * 0b0000..Result is from initial conversion in command. * 0b0001..Result is from second conversion in command. */ #define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) #define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) #define ADC_RESFIFO_CMDSRC_SHIFT (24U) /*! CMDSRC - Command Buffer Source * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. * 0b0001..CMD1 buffer used as control settings for this conversion. * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. * 0b1111..CMD15 buffer used as control settings for this conversion. */ #define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) #define ADC_RESFIFO_VALID_MASK (0x80000000U) #define ADC_RESFIFO_VALID_SHIFT (31U) /*! VALID - FIFO entry is valid * 0b0..FIFO is empty. Discard any read from RESFIFO. * 0b1..FIFO record read from RESFIFO is valid. */ #define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) /*! @} */ /*! @name TST - ADC Test Register */ /*! @{ */ #define ADC_TST_FOFFM_MASK (0x100U) #define ADC_TST_FOFFM_SHIFT (8U) /*! FOFFM - Force M-side offset * 0b0..Normal operation. No forced offset. * 0b1..Test configuration. Forced offset on MDAC. */ #define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK) #define ADC_TST_FOFFP_MASK (0x200U) #define ADC_TST_FOFFP_SHIFT (9U) /*! FOFFP - Force P-side offset * 0b0..Normal operation. No forced offset. * 0b1..Test configuration. Forced offset on PDAC. */ #define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK) #define ADC_TST_TMODE_MASK (0x1F0000U) #define ADC_TST_TMODE_SHIFT (16U) /*! TMODE - Test Mode Select * 0b00000..P-side redundancy check. Measure LSB offset cap. * 0b00001-0b00011..Reserved * 0b00100..P-side test. Bist_offset vs. lower order caps (bits 5-0) * 0b00101..P-side test. MSB_offset vs. lower order caps (bits 5-0) * 0b00110..P-side test. Bit 6 vs. lower order caps (bits 5-0) * 0b00111..P-side test. Bit 7 vs. lower order caps (bits 6-0) * 0b01000..P-side test. Bit 8 vs. lower order caps (bits 7-0) * 0b01001..P-side test. Bit 9 vs. lower order caps (bits 8-0) * 0b01010..P-side test. Bit 10 vs. lower order caps (bits 9-0) * 0b01011..P-side test. Bit 11 vs. lower order caps (bits 10-0) * 0b01100-0b01111..Reserved * 0b10000..M-side redundancy check. Measure LSB offset cap. * 0b10001-0b10011..Reserved * 0b10100..M-side test. Bist_offset vs. lower order caps (bits 5-0) * 0b10101..M-side test. MSB_offset vs. lower order caps (bits 5-0) * 0b10110..M-side test. Bit 6 vs. lower order caps (bits 5-0) * 0b10111..M-side test. Bit 7 vs. lower order caps (bits 6-0) * 0b11000..M-side test. Bit 8 vs. lower order caps (bits 7-0) * 0b11001..M-side test. Bit 9 vs. lower order caps (bits 8-0) * 0b11010..M-side test. Bit 10 vs. lower order caps (bits 9-0) * 0b11011..M-side test. Bit 11 vs. lower order caps (bits 10-0) * 0b11100..Transfer raw CMPOUT[15:13] value. No ADC conversion. Result is from most recent conversion. * 0b11101..Transfer raw CMPOUT[12:0] value. No ADC conversion. Result is from most recent conversion. * 0b11110..Transfer raw CM_CMPOUT[15:13] value. No ADC conversion. Result is from most recent conversion. * 0b11111..Transfer raw CM_CMPOUT[12:0] value. No ADC conversion. Result is from most recent conversion. */ #define ADC_TST_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TMODE_SHIFT)) & ADC_TST_TMODE_MASK) #define ADC_TST_TESTEN_MASK (0x800000U) #define ADC_TST_TESTEN_SHIFT (23U) /*! TESTEN - Enable test configuration * 0b0..Normal operation. Test configuration not enabled. * 0b1..Test configuration. TMODE select test operation to perform when ADC conversions are triggered. */ #define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK) /*! @} */ /*! * @} */ /* end of group ADC_Register_Masks */ /* ADC - Peripheral instance base addresses */ /** Peripheral DMA__ADC0 base address */ #define DMA__ADC0_BASE (0x5A880000u) /** Peripheral DMA__ADC0 base pointer */ #define DMA__ADC0 ((ADC_Type *)DMA__ADC0_BASE) /** Peripheral DMA__ADC1 base address */ #define DMA__ADC1_BASE (0x5A890000u) /** Peripheral DMA__ADC1 base pointer */ #define DMA__ADC1 ((ADC_Type *)DMA__ADC1_BASE) /** Array initializer of ADC peripheral base addresses */ #define ADC_BASE_ADDRS { DMA__ADC0_BASE, DMA__ADC1_BASE } /** Array initializer of ADC peripheral base pointers */ #define ADC_BASE_PTRS { DMA__ADC0, DMA__ADC1 } /** Interrupt vectors for the ADC peripheral type */ #define ADC_IRQS { DMA_ADC0_INT_IRQn, DMA_ADC1_INT_IRQn } /*! * @} */ /* end of group ADC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- APBH Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer * @{ */ /** APBH - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0 */ __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */ __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */ __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */ __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */ } CTRL0; struct { /* offset: 0x10 */ __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */ __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */ __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */ __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */ } CTRL1; struct { /* offset: 0x20 */ __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */ __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */ __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */ __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */ } CTRL2; struct { /* offset: 0x30 */ __IO uint32_t RW; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */ __IO uint32_t SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */ __IO uint32_t CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */ __IO uint32_t TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */ } CHANNEL_CTRL; uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */ uint8_t RESERVED_0[12]; __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */ uint8_t RESERVED_1[12]; __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */ uint8_t RESERVED_2[156]; __I uint32_t CH0_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x100 */ uint8_t RESERVED_3[12]; __IO uint32_t CH0_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x110 */ uint8_t RESERVED_4[12]; __I uint32_t CH0_CMD; /**< APBH DMA Channel n Command Register, offset: 0x120 */ uint8_t RESERVED_5[12]; __I uint32_t CH0_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x130 */ uint8_t RESERVED_6[12]; __IO uint32_t CH0_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x140 */ uint8_t RESERVED_7[12]; __I uint32_t CH0_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x150 */ uint8_t RESERVED_8[12]; __I uint32_t CH0_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x160 */ uint8_t RESERVED_9[12]; __I uint32_t CH1_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x170 */ uint8_t RESERVED_10[12]; __IO uint32_t CH1_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x180 */ uint8_t RESERVED_11[12]; __I uint32_t CH1_CMD; /**< APBH DMA Channel n Command Register, offset: 0x190 */ uint8_t RESERVED_12[12]; __I uint32_t CH1_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x1A0 */ uint8_t RESERVED_13[12]; __IO uint32_t CH1_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x1B0 */ uint8_t RESERVED_14[12]; __I uint32_t CH1_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1C0 */ uint8_t RESERVED_15[12]; __I uint32_t CH1_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1D0 */ uint8_t RESERVED_16[12]; __I uint32_t CH2_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x1E0 */ uint8_t RESERVED_17[12]; __IO uint32_t CH2_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x1F0 */ uint8_t RESERVED_18[12]; __I uint32_t CH2_CMD; /**< APBH DMA Channel n Command Register, offset: 0x200 */ uint8_t RESERVED_19[12]; __I uint32_t CH2_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x210 */ uint8_t RESERVED_20[12]; __IO uint32_t CH2_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x220 */ uint8_t RESERVED_21[12]; __I uint32_t CH2_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x230 */ uint8_t RESERVED_22[12]; __I uint32_t CH2_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x240 */ uint8_t RESERVED_23[12]; __I uint32_t CH3_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x250 */ uint8_t RESERVED_24[12]; __IO uint32_t CH3_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x260 */ uint8_t RESERVED_25[12]; __I uint32_t CH3_CMD; /**< APBH DMA Channel n Command Register, offset: 0x270 */ uint8_t RESERVED_26[12]; __I uint32_t CH3_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x280 */ uint8_t RESERVED_27[12]; __IO uint32_t CH3_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x290 */ uint8_t RESERVED_28[12]; __I uint32_t CH3_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2A0 */ uint8_t RESERVED_29[12]; __I uint32_t CH3_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2B0 */ uint8_t RESERVED_30[12]; __I uint32_t CH4_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x2C0 */ uint8_t RESERVED_31[12]; __IO uint32_t CH4_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x2D0 */ uint8_t RESERVED_32[12]; __I uint32_t CH4_CMD; /**< APBH DMA Channel n Command Register, offset: 0x2E0 */ uint8_t RESERVED_33[12]; __I uint32_t CH4_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x2F0 */ uint8_t RESERVED_34[12]; __IO uint32_t CH4_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x300 */ uint8_t RESERVED_35[12]; __I uint32_t CH4_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x310 */ uint8_t RESERVED_36[12]; __I uint32_t CH4_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x320 */ uint8_t RESERVED_37[12]; __I uint32_t CH5_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x330 */ uint8_t RESERVED_38[12]; __IO uint32_t CH5_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x340 */ uint8_t RESERVED_39[12]; __I uint32_t CH5_CMD; /**< APBH DMA Channel n Command Register, offset: 0x350 */ uint8_t RESERVED_40[12]; __I uint32_t CH5_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x360 */ uint8_t RESERVED_41[12]; __IO uint32_t CH5_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x370 */ uint8_t RESERVED_42[12]; __I uint32_t CH5_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x380 */ uint8_t RESERVED_43[12]; __I uint32_t CH5_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x390 */ uint8_t RESERVED_44[12]; __I uint32_t CH6_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x3A0 */ uint8_t RESERVED_45[12]; __IO uint32_t CH6_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x3B0 */ uint8_t RESERVED_46[12]; __I uint32_t CH6_CMD; /**< APBH DMA Channel n Command Register, offset: 0x3C0 */ uint8_t RESERVED_47[12]; __I uint32_t CH6_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x3D0 */ uint8_t RESERVED_48[12]; __IO uint32_t CH6_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x3E0 */ uint8_t RESERVED_49[12]; __I uint32_t CH6_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x3F0 */ uint8_t RESERVED_50[12]; __I uint32_t CH6_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x400 */ uint8_t RESERVED_51[12]; __I uint32_t CH7_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x410 */ uint8_t RESERVED_52[12]; __IO uint32_t CH7_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x420 */ uint8_t RESERVED_53[12]; __I uint32_t CH7_CMD; /**< APBH DMA Channel n Command Register, offset: 0x430 */ uint8_t RESERVED_54[12]; __I uint32_t CH7_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x440 */ uint8_t RESERVED_55[12]; __IO uint32_t CH7_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x450 */ uint8_t RESERVED_56[12]; __I uint32_t CH7_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x460 */ uint8_t RESERVED_57[12]; __I uint32_t CH7_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x470 */ uint8_t RESERVED_58[12]; __I uint32_t CH8_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x480 */ uint8_t RESERVED_59[12]; __IO uint32_t CH8_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x490 */ uint8_t RESERVED_60[12]; __I uint32_t CH8_CMD; /**< APBH DMA Channel n Command Register, offset: 0x4A0 */ uint8_t RESERVED_61[12]; __I uint32_t CH8_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x4B0 */ uint8_t RESERVED_62[12]; __IO uint32_t CH8_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x4C0 */ uint8_t RESERVED_63[12]; __I uint32_t CH8_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4D0 */ uint8_t RESERVED_64[12]; __I uint32_t CH8_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4E0 */ uint8_t RESERVED_65[12]; __I uint32_t CH9_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x4F0 */ uint8_t RESERVED_66[12]; __IO uint32_t CH9_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x500 */ uint8_t RESERVED_67[12]; __I uint32_t CH9_CMD; /**< APBH DMA Channel n Command Register, offset: 0x510 */ uint8_t RESERVED_68[12]; __I uint32_t CH9_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x520 */ uint8_t RESERVED_69[12]; __IO uint32_t CH9_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x530 */ uint8_t RESERVED_70[12]; __I uint32_t CH9_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x540 */ uint8_t RESERVED_71[12]; __I uint32_t CH9_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x550 */ uint8_t RESERVED_72[12]; __I uint32_t CH10_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x560 */ uint8_t RESERVED_73[12]; __IO uint32_t CH10_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x570 */ uint8_t RESERVED_74[12]; __I uint32_t CH10_CMD; /**< APBH DMA Channel n Command Register, offset: 0x580 */ uint8_t RESERVED_75[12]; __I uint32_t CH10_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x590 */ uint8_t RESERVED_76[12]; __IO uint32_t CH10_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x5A0 */ uint8_t RESERVED_77[12]; __I uint32_t CH10_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5B0 */ uint8_t RESERVED_78[12]; __I uint32_t CH10_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5C0 */ uint8_t RESERVED_79[12]; __I uint32_t CH11_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x5D0 */ uint8_t RESERVED_80[12]; __IO uint32_t CH11_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x5E0 */ uint8_t RESERVED_81[12]; __I uint32_t CH11_CMD; /**< APBH DMA Channel n Command Register, offset: 0x5F0 */ uint8_t RESERVED_82[12]; __I uint32_t CH11_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x600 */ uint8_t RESERVED_83[12]; __IO uint32_t CH11_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x610 */ uint8_t RESERVED_84[12]; __I uint32_t CH11_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x620 */ uint8_t RESERVED_85[12]; __I uint32_t CH11_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x630 */ uint8_t RESERVED_86[12]; __I uint32_t CH12_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x640 */ uint8_t RESERVED_87[12]; __IO uint32_t CH12_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x650 */ uint8_t RESERVED_88[12]; __I uint32_t CH12_CMD; /**< APBH DMA Channel n Command Register, offset: 0x660 */ uint8_t RESERVED_89[12]; __I uint32_t CH12_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x670 */ uint8_t RESERVED_90[12]; __IO uint32_t CH12_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x680 */ uint8_t RESERVED_91[12]; __I uint32_t CH12_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x690 */ uint8_t RESERVED_92[12]; __I uint32_t CH12_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x6A0 */ uint8_t RESERVED_93[12]; __I uint32_t CH13_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x6B0 */ uint8_t RESERVED_94[12]; __IO uint32_t CH13_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x6C0 */ uint8_t RESERVED_95[12]; __I uint32_t CH13_CMD; /**< APBH DMA Channel n Command Register, offset: 0x6D0 */ uint8_t RESERVED_96[12]; __I uint32_t CH13_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x6E0 */ uint8_t RESERVED_97[12]; __IO uint32_t CH13_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x6F0 */ uint8_t RESERVED_98[12]; __I uint32_t CH13_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x700 */ uint8_t RESERVED_99[12]; __I uint32_t CH13_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x710 */ uint8_t RESERVED_100[12]; __I uint32_t CH14_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x720 */ uint8_t RESERVED_101[12]; __IO uint32_t CH14_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x730 */ uint8_t RESERVED_102[12]; __I uint32_t CH14_CMD; /**< APBH DMA Channel n Command Register, offset: 0x740 */ uint8_t RESERVED_103[12]; __I uint32_t CH14_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x750 */ uint8_t RESERVED_104[12]; __IO uint32_t CH14_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x760 */ uint8_t RESERVED_105[12]; __I uint32_t CH14_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x770 */ uint8_t RESERVED_106[12]; __I uint32_t CH14_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x780 */ uint8_t RESERVED_107[12]; __I uint32_t CH15_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x790 */ uint8_t RESERVED_108[12]; __IO uint32_t CH15_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x7A0 */ uint8_t RESERVED_109[12]; __I uint32_t CH15_CMD; /**< APBH DMA Channel n Command Register, offset: 0x7B0 */ uint8_t RESERVED_110[12]; __I uint32_t CH15_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x7C0 */ uint8_t RESERVED_111[12]; __IO uint32_t CH15_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x7D0 */ uint8_t RESERVED_112[12]; __I uint32_t CH15_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7E0 */ uint8_t RESERVED_113[12]; __I uint32_t CH15_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7F0 */ uint8_t RESERVED_114[12]; __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */ } APBH_Type; /* ---------------------------------------------------------------------------- -- APBH Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup APBH_Register_Masks APBH Register Masks * @{ */ /*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */ /*! @{ */ #define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU) #define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U) #define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK) #define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U) #define APBH_CTRL0_APB_BURST_EN_SHIFT (28U) #define APBH_CTRL0_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK) #define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U) #define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U) #define APBH_CTRL0_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK) #define APBH_CTRL0_CLKGATE_MASK (0x40000000U) #define APBH_CTRL0_CLKGATE_SHIFT (30U) #define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK) #define APBH_CTRL0_SFTRST_MASK (0x80000000U) #define APBH_CTRL0_SFTRST_SHIFT (31U) #define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK) /*! @} */ /*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */ /*! @{ */ #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U) #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U) #define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U) #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U) #define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U) #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U) #define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U) #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U) #define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U) #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U) #define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U) #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U) #define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U) #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U) #define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U) #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U) #define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U) #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U) #define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U) #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U) #define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U) #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U) #define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U) #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U) #define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U) #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U) #define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U) #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U) #define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U) #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U) #define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U) #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U) #define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK) /*! @} */ /*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */ /*! @{ */ #define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U) #define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U) #define APBH_CTRL2_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK) #define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U) #define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U) #define APBH_CTRL2_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK) #define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U) #define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U) #define APBH_CTRL2_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK) #define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U) #define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U) #define APBH_CTRL2_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK) #define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U) #define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U) #define APBH_CTRL2_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK) #define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U) #define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U) #define APBH_CTRL2_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK) #define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U) #define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U) #define APBH_CTRL2_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK) #define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U) #define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U) #define APBH_CTRL2_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK) #define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U) #define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U) #define APBH_CTRL2_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK) #define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U) #define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U) #define APBH_CTRL2_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK) #define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U) #define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U) #define APBH_CTRL2_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK) #define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U) #define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U) #define APBH_CTRL2_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK) #define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U) #define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U) #define APBH_CTRL2_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK) #define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U) #define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U) #define APBH_CTRL2_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK) #define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U) #define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U) #define APBH_CTRL2_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK) #define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U) #define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U) #define APBH_CTRL2_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK) #define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U) #define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U) /*! CH0_ERROR_STATUS - CH0_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK) #define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U) #define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U) /*! CH1_ERROR_STATUS - CH1_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK) #define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U) #define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U) /*! CH2_ERROR_STATUS - CH2_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK) #define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U) #define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U) /*! CH3_ERROR_STATUS - CH3_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK) #define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U) #define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U) /*! CH4_ERROR_STATUS - CH4_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK) #define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U) #define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U) /*! CH5_ERROR_STATUS - CH5_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK) #define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U) #define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U) /*! CH6_ERROR_STATUS - CH6_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK) #define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U) #define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U) /*! CH7_ERROR_STATUS - CH7_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK) #define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U) #define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U) /*! CH8_ERROR_STATUS - CH8_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK) #define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U) #define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U) /*! CH9_ERROR_STATUS - CH9_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK) #define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U) #define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U) /*! CH10_ERROR_STATUS - CH10_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK) #define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U) #define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U) /*! CH11_ERROR_STATUS - CH11_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK) #define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U) #define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U) /*! CH12_ERROR_STATUS - CH12_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK) #define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U) #define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U) /*! CH13_ERROR_STATUS - CH13_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK) #define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U) #define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U) /*! CH14_ERROR_STATUS - CH14_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK) #define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U) #define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U) /*! CH15_ERROR_STATUS - CH15_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK) /*! @} */ /*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */ /*! @{ */ #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU) #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U) #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK) #define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U) #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U) #define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK) /*! @} */ /*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */ /*! @{ */ #define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U) #define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U) #define APBH_DMA_BURST_SIZE_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK) #define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU) #define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U) #define APBH_DMA_BURST_SIZE_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK) #define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U) #define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U) #define APBH_DMA_BURST_SIZE_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK) #define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U) #define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U) #define APBH_DMA_BURST_SIZE_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK) #define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U) #define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U) #define APBH_DMA_BURST_SIZE_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK) #define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U) #define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U) #define APBH_DMA_BURST_SIZE_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK) #define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U) #define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U) #define APBH_DMA_BURST_SIZE_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK) #define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U) #define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U) #define APBH_DMA_BURST_SIZE_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK) #define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U) #define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U) #define APBH_DMA_BURST_SIZE_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK) /*! @} */ /*! @name DEBUG - AHB to APBH DMA Debug Register */ /*! @{ */ #define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U) #define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U) #define APBH_DEBUG_GPMI_ONE_FIFO(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK) /*! @} */ /*! @name CH0_CURCMDAR - APBH DMA Channel n Current Command Address Register */ /*! @{ */ #define APBH_CH0_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH0_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_CURCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH0_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ /*! @{ */ #define APBH_CH0_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH0_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_NXTCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH0_CMD - APBH DMA Channel n Command Register */ /*! @{ */ #define APBH_CH0_CMD_COMMAND_MASK (0x3U) #define APBH_CH0_CMD_COMMAND_SHIFT (0U) /*! COMMAND - COMMAND * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. */ #define APBH_CH0_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_COMMAND_SHIFT)) & APBH_CH0_CMD_COMMAND_MASK) #define APBH_CH0_CMD_CHAIN_MASK (0x4U) #define APBH_CH0_CMD_CHAIN_SHIFT (2U) #define APBH_CH0_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CHAIN_SHIFT)) & APBH_CH0_CMD_CHAIN_MASK) #define APBH_CH0_CMD_IRQONCMPLT_MASK (0x8U) #define APBH_CH0_CMD_IRQONCMPLT_SHIFT (3U) #define APBH_CH0_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_IRQONCMPLT_SHIFT)) & APBH_CH0_CMD_IRQONCMPLT_MASK) #define APBH_CH0_CMD_NANDLOCK_MASK (0x10U) #define APBH_CH0_CMD_NANDLOCK_SHIFT (4U) #define APBH_CH0_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDLOCK_SHIFT)) & APBH_CH0_CMD_NANDLOCK_MASK) #define APBH_CH0_CMD_NANDWAIT4READY_MASK (0x20U) #define APBH_CH0_CMD_NANDWAIT4READY_SHIFT (5U) #define APBH_CH0_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH0_CMD_NANDWAIT4READY_MASK) #define APBH_CH0_CMD_SEMAPHORE_MASK (0x40U) #define APBH_CH0_CMD_SEMAPHORE_SHIFT (6U) #define APBH_CH0_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_SEMAPHORE_SHIFT)) & APBH_CH0_CMD_SEMAPHORE_MASK) #define APBH_CH0_CMD_WAIT4ENDCMD_MASK (0x80U) #define APBH_CH0_CMD_WAIT4ENDCMD_SHIFT (7U) #define APBH_CH0_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH0_CMD_WAIT4ENDCMD_MASK) #define APBH_CH0_CMD_HALTONTERMINATE_MASK (0x100U) #define APBH_CH0_CMD_HALTONTERMINATE_SHIFT (8U) #define APBH_CH0_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH0_CMD_HALTONTERMINATE_MASK) #define APBH_CH0_CMD_CMDWORDS_MASK (0xF000U) #define APBH_CH0_CMD_CMDWORDS_SHIFT (12U) #define APBH_CH0_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CMDWORDS_SHIFT)) & APBH_CH0_CMD_CMDWORDS_MASK) #define APBH_CH0_CMD_XFER_COUNT_MASK (0xFFFF0000U) #define APBH_CH0_CMD_XFER_COUNT_SHIFT (16U) #define APBH_CH0_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_XFER_COUNT_SHIFT)) & APBH_CH0_CMD_XFER_COUNT_MASK) /*! @} */ /*! @name CH0_BAR - APBH DMA Channel n Buffer Address Register */ /*! @{ */ #define APBH_CH0_BAR_ADDRESS_MASK (0xFFFFFFFFU) #define APBH_CH0_BAR_ADDRESS_SHIFT (0U) #define APBH_CH0_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_BAR_ADDRESS_SHIFT)) & APBH_CH0_BAR_ADDRESS_MASK) /*! @} */ /*! @name CH0_SEMA - APBH DMA Channel n Semaphore Register */ /*! @{ */ #define APBH_CH0_SEMA_INCREMENT_SEMA_MASK (0xFFU) #define APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT (0U) #define APBH_CH0_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH0_SEMA_INCREMENT_SEMA_MASK) #define APBH_CH0_SEMA_PHORE_MASK (0xFF0000U) #define APBH_CH0_SEMA_PHORE_SHIFT (16U) #define APBH_CH0_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_PHORE_SHIFT)) & APBH_CH0_SEMA_PHORE_MASK) /*! @} */ /*! @name CH0_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH0_DEBUG1_STATEMACHINE_MASK (0x1FU) #define APBH_CH0_DEBUG1_STATEMACHINE_SHIFT (0U) /*! STATEMACHINE - STATEMACHINE * 0b00000..This is the idle state of the DMA state machine. * 0b00001..State in which the DMA is waiting to receive the first word of a command. * 0b00010..State in which the DMA is waiting to receive the third word of a command. * 0b00011..State in which the DMA is waiting to receive the second word of a command. * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. */ #define APBH_CH0_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH0_DEBUG1_STATEMACHINE_MASK) #define APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) #define APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT (20U) #define APBH_CH0_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK) #define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) #define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) #define APBH_CH0_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK) #define APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) #define APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT (22U) #define APBH_CH0_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK) #define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) #define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) #define APBH_CH0_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK) #define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) #define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) #define APBH_CH0_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK) #define APBH_CH0_DEBUG1_READY_MASK (0x4000000U) #define APBH_CH0_DEBUG1_READY_SHIFT (26U) #define APBH_CH0_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_READY_SHIFT)) & APBH_CH0_DEBUG1_READY_MASK) #define APBH_CH0_DEBUG1_END_MASK (0x10000000U) #define APBH_CH0_DEBUG1_END_SHIFT (28U) #define APBH_CH0_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_END_SHIFT)) & APBH_CH0_DEBUG1_END_MASK) #define APBH_CH0_DEBUG1_KICK_MASK (0x20000000U) #define APBH_CH0_DEBUG1_KICK_SHIFT (29U) #define APBH_CH0_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_KICK_SHIFT)) & APBH_CH0_DEBUG1_KICK_MASK) #define APBH_CH0_DEBUG1_BURST_MASK (0x40000000U) #define APBH_CH0_DEBUG1_BURST_SHIFT (30U) #define APBH_CH0_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_BURST_SHIFT)) & APBH_CH0_DEBUG1_BURST_MASK) #define APBH_CH0_DEBUG1_REQ_MASK (0x80000000U) #define APBH_CH0_DEBUG1_REQ_SHIFT (31U) #define APBH_CH0_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_REQ_SHIFT)) & APBH_CH0_DEBUG1_REQ_MASK) /*! @} */ /*! @name CH0_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH0_DEBUG2_AHB_BYTES_MASK (0xFFFFU) #define APBH_CH0_DEBUG2_AHB_BYTES_SHIFT (0U) #define APBH_CH0_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_AHB_BYTES_MASK) #define APBH_CH0_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) #define APBH_CH0_DEBUG2_APB_BYTES_SHIFT (16U) #define APBH_CH0_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_APB_BYTES_MASK) /*! @} */ /*! @name CH1_CURCMDAR - APBH DMA Channel n Current Command Address Register */ /*! @{ */ #define APBH_CH1_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH1_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_CURCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH1_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ /*! @{ */ #define APBH_CH1_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH1_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_NXTCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH1_CMD - APBH DMA Channel n Command Register */ /*! @{ */ #define APBH_CH1_CMD_COMMAND_MASK (0x3U) #define APBH_CH1_CMD_COMMAND_SHIFT (0U) /*! COMMAND - COMMAND * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. */ #define APBH_CH1_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_COMMAND_SHIFT)) & APBH_CH1_CMD_COMMAND_MASK) #define APBH_CH1_CMD_CHAIN_MASK (0x4U) #define APBH_CH1_CMD_CHAIN_SHIFT (2U) #define APBH_CH1_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CHAIN_SHIFT)) & APBH_CH1_CMD_CHAIN_MASK) #define APBH_CH1_CMD_IRQONCMPLT_MASK (0x8U) #define APBH_CH1_CMD_IRQONCMPLT_SHIFT (3U) #define APBH_CH1_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_IRQONCMPLT_SHIFT)) & APBH_CH1_CMD_IRQONCMPLT_MASK) #define APBH_CH1_CMD_NANDLOCK_MASK (0x10U) #define APBH_CH1_CMD_NANDLOCK_SHIFT (4U) #define APBH_CH1_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDLOCK_SHIFT)) & APBH_CH1_CMD_NANDLOCK_MASK) #define APBH_CH1_CMD_NANDWAIT4READY_MASK (0x20U) #define APBH_CH1_CMD_NANDWAIT4READY_SHIFT (5U) #define APBH_CH1_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH1_CMD_NANDWAIT4READY_MASK) #define APBH_CH1_CMD_SEMAPHORE_MASK (0x40U) #define APBH_CH1_CMD_SEMAPHORE_SHIFT (6U) #define APBH_CH1_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_SEMAPHORE_SHIFT)) & APBH_CH1_CMD_SEMAPHORE_MASK) #define APBH_CH1_CMD_WAIT4ENDCMD_MASK (0x80U) #define APBH_CH1_CMD_WAIT4ENDCMD_SHIFT (7U) #define APBH_CH1_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH1_CMD_WAIT4ENDCMD_MASK) #define APBH_CH1_CMD_HALTONTERMINATE_MASK (0x100U) #define APBH_CH1_CMD_HALTONTERMINATE_SHIFT (8U) #define APBH_CH1_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH1_CMD_HALTONTERMINATE_MASK) #define APBH_CH1_CMD_CMDWORDS_MASK (0xF000U) #define APBH_CH1_CMD_CMDWORDS_SHIFT (12U) #define APBH_CH1_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CMDWORDS_SHIFT)) & APBH_CH1_CMD_CMDWORDS_MASK) #define APBH_CH1_CMD_XFER_COUNT_MASK (0xFFFF0000U) #define APBH_CH1_CMD_XFER_COUNT_SHIFT (16U) #define APBH_CH1_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_XFER_COUNT_SHIFT)) & APBH_CH1_CMD_XFER_COUNT_MASK) /*! @} */ /*! @name CH1_BAR - APBH DMA Channel n Buffer Address Register */ /*! @{ */ #define APBH_CH1_BAR_ADDRESS_MASK (0xFFFFFFFFU) #define APBH_CH1_BAR_ADDRESS_SHIFT (0U) #define APBH_CH1_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_BAR_ADDRESS_SHIFT)) & APBH_CH1_BAR_ADDRESS_MASK) /*! @} */ /*! @name CH1_SEMA - APBH DMA Channel n Semaphore Register */ /*! @{ */ #define APBH_CH1_SEMA_INCREMENT_SEMA_MASK (0xFFU) #define APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT (0U) #define APBH_CH1_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH1_SEMA_INCREMENT_SEMA_MASK) #define APBH_CH1_SEMA_PHORE_MASK (0xFF0000U) #define APBH_CH1_SEMA_PHORE_SHIFT (16U) #define APBH_CH1_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_PHORE_SHIFT)) & APBH_CH1_SEMA_PHORE_MASK) /*! @} */ /*! @name CH1_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH1_DEBUG1_STATEMACHINE_MASK (0x1FU) #define APBH_CH1_DEBUG1_STATEMACHINE_SHIFT (0U) /*! STATEMACHINE - STATEMACHINE * 0b00000..This is the idle state of the DMA state machine. * 0b00001..State in which the DMA is waiting to receive the first word of a command. * 0b00010..State in which the DMA is waiting to receive the third word of a command. * 0b00011..State in which the DMA is waiting to receive the second word of a command. * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. */ #define APBH_CH1_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH1_DEBUG1_STATEMACHINE_MASK) #define APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) #define APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT (20U) #define APBH_CH1_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK) #define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) #define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) #define APBH_CH1_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK) #define APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) #define APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT (22U) #define APBH_CH1_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK) #define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) #define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) #define APBH_CH1_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK) #define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) #define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) #define APBH_CH1_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK) #define APBH_CH1_DEBUG1_READY_MASK (0x4000000U) #define APBH_CH1_DEBUG1_READY_SHIFT (26U) #define APBH_CH1_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_READY_SHIFT)) & APBH_CH1_DEBUG1_READY_MASK) #define APBH_CH1_DEBUG1_END_MASK (0x10000000U) #define APBH_CH1_DEBUG1_END_SHIFT (28U) #define APBH_CH1_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_END_SHIFT)) & APBH_CH1_DEBUG1_END_MASK) #define APBH_CH1_DEBUG1_KICK_MASK (0x20000000U) #define APBH_CH1_DEBUG1_KICK_SHIFT (29U) #define APBH_CH1_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_KICK_SHIFT)) & APBH_CH1_DEBUG1_KICK_MASK) #define APBH_CH1_DEBUG1_BURST_MASK (0x40000000U) #define APBH_CH1_DEBUG1_BURST_SHIFT (30U) #define APBH_CH1_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_BURST_SHIFT)) & APBH_CH1_DEBUG1_BURST_MASK) #define APBH_CH1_DEBUG1_REQ_MASK (0x80000000U) #define APBH_CH1_DEBUG1_REQ_SHIFT (31U) #define APBH_CH1_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_REQ_SHIFT)) & APBH_CH1_DEBUG1_REQ_MASK) /*! @} */ /*! @name CH1_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH1_DEBUG2_AHB_BYTES_MASK (0xFFFFU) #define APBH_CH1_DEBUG2_AHB_BYTES_SHIFT (0U) #define APBH_CH1_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_AHB_BYTES_MASK) #define APBH_CH1_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) #define APBH_CH1_DEBUG2_APB_BYTES_SHIFT (16U) #define APBH_CH1_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_APB_BYTES_MASK) /*! @} */ /*! @name CH2_CURCMDAR - APBH DMA Channel n Current Command Address Register */ /*! @{ */ #define APBH_CH2_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH2_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_CURCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH2_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ /*! @{ */ #define APBH_CH2_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH2_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_NXTCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH2_CMD - APBH DMA Channel n Command Register */ /*! @{ */ #define APBH_CH2_CMD_COMMAND_MASK (0x3U) #define APBH_CH2_CMD_COMMAND_SHIFT (0U) /*! COMMAND - COMMAND * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. */ #define APBH_CH2_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_COMMAND_SHIFT)) & APBH_CH2_CMD_COMMAND_MASK) #define APBH_CH2_CMD_CHAIN_MASK (0x4U) #define APBH_CH2_CMD_CHAIN_SHIFT (2U) #define APBH_CH2_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CHAIN_SHIFT)) & APBH_CH2_CMD_CHAIN_MASK) #define APBH_CH2_CMD_IRQONCMPLT_MASK (0x8U) #define APBH_CH2_CMD_IRQONCMPLT_SHIFT (3U) #define APBH_CH2_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_IRQONCMPLT_SHIFT)) & APBH_CH2_CMD_IRQONCMPLT_MASK) #define APBH_CH2_CMD_NANDLOCK_MASK (0x10U) #define APBH_CH2_CMD_NANDLOCK_SHIFT (4U) #define APBH_CH2_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDLOCK_SHIFT)) & APBH_CH2_CMD_NANDLOCK_MASK) #define APBH_CH2_CMD_NANDWAIT4READY_MASK (0x20U) #define APBH_CH2_CMD_NANDWAIT4READY_SHIFT (5U) #define APBH_CH2_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH2_CMD_NANDWAIT4READY_MASK) #define APBH_CH2_CMD_SEMAPHORE_MASK (0x40U) #define APBH_CH2_CMD_SEMAPHORE_SHIFT (6U) #define APBH_CH2_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_SEMAPHORE_SHIFT)) & APBH_CH2_CMD_SEMAPHORE_MASK) #define APBH_CH2_CMD_WAIT4ENDCMD_MASK (0x80U) #define APBH_CH2_CMD_WAIT4ENDCMD_SHIFT (7U) #define APBH_CH2_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH2_CMD_WAIT4ENDCMD_MASK) #define APBH_CH2_CMD_HALTONTERMINATE_MASK (0x100U) #define APBH_CH2_CMD_HALTONTERMINATE_SHIFT (8U) #define APBH_CH2_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH2_CMD_HALTONTERMINATE_MASK) #define APBH_CH2_CMD_CMDWORDS_MASK (0xF000U) #define APBH_CH2_CMD_CMDWORDS_SHIFT (12U) #define APBH_CH2_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CMDWORDS_SHIFT)) & APBH_CH2_CMD_CMDWORDS_MASK) #define APBH_CH2_CMD_XFER_COUNT_MASK (0xFFFF0000U) #define APBH_CH2_CMD_XFER_COUNT_SHIFT (16U) #define APBH_CH2_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_XFER_COUNT_SHIFT)) & APBH_CH2_CMD_XFER_COUNT_MASK) /*! @} */ /*! @name CH2_BAR - APBH DMA Channel n Buffer Address Register */ /*! @{ */ #define APBH_CH2_BAR_ADDRESS_MASK (0xFFFFFFFFU) #define APBH_CH2_BAR_ADDRESS_SHIFT (0U) #define APBH_CH2_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_BAR_ADDRESS_SHIFT)) & APBH_CH2_BAR_ADDRESS_MASK) /*! @} */ /*! @name CH2_SEMA - APBH DMA Channel n Semaphore Register */ /*! @{ */ #define APBH_CH2_SEMA_INCREMENT_SEMA_MASK (0xFFU) #define APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT (0U) #define APBH_CH2_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH2_SEMA_INCREMENT_SEMA_MASK) #define APBH_CH2_SEMA_PHORE_MASK (0xFF0000U) #define APBH_CH2_SEMA_PHORE_SHIFT (16U) #define APBH_CH2_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_PHORE_SHIFT)) & APBH_CH2_SEMA_PHORE_MASK) /*! @} */ /*! @name CH2_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH2_DEBUG1_STATEMACHINE_MASK (0x1FU) #define APBH_CH2_DEBUG1_STATEMACHINE_SHIFT (0U) /*! STATEMACHINE - STATEMACHINE * 0b00000..This is the idle state of the DMA state machine. * 0b00001..State in which the DMA is waiting to receive the first word of a command. * 0b00010..State in which the DMA is waiting to receive the third word of a command. * 0b00011..State in which the DMA is waiting to receive the second word of a command. * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. */ #define APBH_CH2_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH2_DEBUG1_STATEMACHINE_MASK) #define APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) #define APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT (20U) #define APBH_CH2_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK) #define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) #define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) #define APBH_CH2_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK) #define APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) #define APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT (22U) #define APBH_CH2_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK) #define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) #define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) #define APBH_CH2_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK) #define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) #define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) #define APBH_CH2_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK) #define APBH_CH2_DEBUG1_READY_MASK (0x4000000U) #define APBH_CH2_DEBUG1_READY_SHIFT (26U) #define APBH_CH2_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_READY_SHIFT)) & APBH_CH2_DEBUG1_READY_MASK) #define APBH_CH2_DEBUG1_END_MASK (0x10000000U) #define APBH_CH2_DEBUG1_END_SHIFT (28U) #define APBH_CH2_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_END_SHIFT)) & APBH_CH2_DEBUG1_END_MASK) #define APBH_CH2_DEBUG1_KICK_MASK (0x20000000U) #define APBH_CH2_DEBUG1_KICK_SHIFT (29U) #define APBH_CH2_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_KICK_SHIFT)) & APBH_CH2_DEBUG1_KICK_MASK) #define APBH_CH2_DEBUG1_BURST_MASK (0x40000000U) #define APBH_CH2_DEBUG1_BURST_SHIFT (30U) #define APBH_CH2_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_BURST_SHIFT)) & APBH_CH2_DEBUG1_BURST_MASK) #define APBH_CH2_DEBUG1_REQ_MASK (0x80000000U) #define APBH_CH2_DEBUG1_REQ_SHIFT (31U) #define APBH_CH2_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_REQ_SHIFT)) & APBH_CH2_DEBUG1_REQ_MASK) /*! @} */ /*! @name CH2_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH2_DEBUG2_AHB_BYTES_MASK (0xFFFFU) #define APBH_CH2_DEBUG2_AHB_BYTES_SHIFT (0U) #define APBH_CH2_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_AHB_BYTES_MASK) #define APBH_CH2_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) #define APBH_CH2_DEBUG2_APB_BYTES_SHIFT (16U) #define APBH_CH2_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_APB_BYTES_MASK) /*! @} */ /*! @name CH3_CURCMDAR - APBH DMA Channel n Current Command Address Register */ /*! @{ */ #define APBH_CH3_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH3_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_CURCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH3_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ /*! @{ */ #define APBH_CH3_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH3_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_NXTCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH3_CMD - APBH DMA Channel n Command Register */ /*! @{ */ #define APBH_CH3_CMD_COMMAND_MASK (0x3U) #define APBH_CH3_CMD_COMMAND_SHIFT (0U) /*! COMMAND - COMMAND * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. */ #define APBH_CH3_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_COMMAND_SHIFT)) & APBH_CH3_CMD_COMMAND_MASK) #define APBH_CH3_CMD_CHAIN_MASK (0x4U) #define APBH_CH3_CMD_CHAIN_SHIFT (2U) #define APBH_CH3_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CHAIN_SHIFT)) & APBH_CH3_CMD_CHAIN_MASK) #define APBH_CH3_CMD_IRQONCMPLT_MASK (0x8U) #define APBH_CH3_CMD_IRQONCMPLT_SHIFT (3U) #define APBH_CH3_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_IRQONCMPLT_SHIFT)) & APBH_CH3_CMD_IRQONCMPLT_MASK) #define APBH_CH3_CMD_NANDLOCK_MASK (0x10U) #define APBH_CH3_CMD_NANDLOCK_SHIFT (4U) #define APBH_CH3_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDLOCK_SHIFT)) & APBH_CH3_CMD_NANDLOCK_MASK) #define APBH_CH3_CMD_NANDWAIT4READY_MASK (0x20U) #define APBH_CH3_CMD_NANDWAIT4READY_SHIFT (5U) #define APBH_CH3_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH3_CMD_NANDWAIT4READY_MASK) #define APBH_CH3_CMD_SEMAPHORE_MASK (0x40U) #define APBH_CH3_CMD_SEMAPHORE_SHIFT (6U) #define APBH_CH3_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_SEMAPHORE_SHIFT)) & APBH_CH3_CMD_SEMAPHORE_MASK) #define APBH_CH3_CMD_WAIT4ENDCMD_MASK (0x80U) #define APBH_CH3_CMD_WAIT4ENDCMD_SHIFT (7U) #define APBH_CH3_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH3_CMD_WAIT4ENDCMD_MASK) #define APBH_CH3_CMD_HALTONTERMINATE_MASK (0x100U) #define APBH_CH3_CMD_HALTONTERMINATE_SHIFT (8U) #define APBH_CH3_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH3_CMD_HALTONTERMINATE_MASK) #define APBH_CH3_CMD_CMDWORDS_MASK (0xF000U) #define APBH_CH3_CMD_CMDWORDS_SHIFT (12U) #define APBH_CH3_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CMDWORDS_SHIFT)) & APBH_CH3_CMD_CMDWORDS_MASK) #define APBH_CH3_CMD_XFER_COUNT_MASK (0xFFFF0000U) #define APBH_CH3_CMD_XFER_COUNT_SHIFT (16U) #define APBH_CH3_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_XFER_COUNT_SHIFT)) & APBH_CH3_CMD_XFER_COUNT_MASK) /*! @} */ /*! @name CH3_BAR - APBH DMA Channel n Buffer Address Register */ /*! @{ */ #define APBH_CH3_BAR_ADDRESS_MASK (0xFFFFFFFFU) #define APBH_CH3_BAR_ADDRESS_SHIFT (0U) #define APBH_CH3_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_BAR_ADDRESS_SHIFT)) & APBH_CH3_BAR_ADDRESS_MASK) /*! @} */ /*! @name CH3_SEMA - APBH DMA Channel n Semaphore Register */ /*! @{ */ #define APBH_CH3_SEMA_INCREMENT_SEMA_MASK (0xFFU) #define APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT (0U) #define APBH_CH3_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH3_SEMA_INCREMENT_SEMA_MASK) #define APBH_CH3_SEMA_PHORE_MASK (0xFF0000U) #define APBH_CH3_SEMA_PHORE_SHIFT (16U) #define APBH_CH3_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_PHORE_SHIFT)) & APBH_CH3_SEMA_PHORE_MASK) /*! @} */ /*! @name CH3_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH3_DEBUG1_STATEMACHINE_MASK (0x1FU) #define APBH_CH3_DEBUG1_STATEMACHINE_SHIFT (0U) /*! STATEMACHINE - STATEMACHINE * 0b00000..This is the idle state of the DMA state machine. * 0b00001..State in which the DMA is waiting to receive the first word of a command. * 0b00010..State in which the DMA is waiting to receive the third word of a command. * 0b00011..State in which the DMA is waiting to receive the second word of a command. * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. */ #define APBH_CH3_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH3_DEBUG1_STATEMACHINE_MASK) #define APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) #define APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT (20U) #define APBH_CH3_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK) #define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) #define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) #define APBH_CH3_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK) #define APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) #define APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT (22U) #define APBH_CH3_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK) #define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) #define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) #define APBH_CH3_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK) #define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) #define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) #define APBH_CH3_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK) #define APBH_CH3_DEBUG1_READY_MASK (0x4000000U) #define APBH_CH3_DEBUG1_READY_SHIFT (26U) #define APBH_CH3_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_READY_SHIFT)) & APBH_CH3_DEBUG1_READY_MASK) #define APBH_CH3_DEBUG1_END_MASK (0x10000000U) #define APBH_CH3_DEBUG1_END_SHIFT (28U) #define APBH_CH3_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_END_SHIFT)) & APBH_CH3_DEBUG1_END_MASK) #define APBH_CH3_DEBUG1_KICK_MASK (0x20000000U) #define APBH_CH3_DEBUG1_KICK_SHIFT (29U) #define APBH_CH3_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_KICK_SHIFT)) & APBH_CH3_DEBUG1_KICK_MASK) #define APBH_CH3_DEBUG1_BURST_MASK (0x40000000U) #define APBH_CH3_DEBUG1_BURST_SHIFT (30U) #define APBH_CH3_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_BURST_SHIFT)) & APBH_CH3_DEBUG1_BURST_MASK) #define APBH_CH3_DEBUG1_REQ_MASK (0x80000000U) #define APBH_CH3_DEBUG1_REQ_SHIFT (31U) #define APBH_CH3_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_REQ_SHIFT)) & APBH_CH3_DEBUG1_REQ_MASK) /*! @} */ /*! @name CH3_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH3_DEBUG2_AHB_BYTES_MASK (0xFFFFU) #define APBH_CH3_DEBUG2_AHB_BYTES_SHIFT (0U) #define APBH_CH3_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_AHB_BYTES_MASK) #define APBH_CH3_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) #define APBH_CH3_DEBUG2_APB_BYTES_SHIFT (16U) #define APBH_CH3_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_APB_BYTES_MASK) /*! @} */ /*! @name CH4_CURCMDAR - APBH DMA Channel n Current Command Address Register */ /*! @{ */ #define APBH_CH4_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH4_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_CURCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH4_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ /*! @{ */ #define APBH_CH4_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH4_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_NXTCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH4_CMD - APBH DMA Channel n Command Register */ /*! @{ */ #define APBH_CH4_CMD_COMMAND_MASK (0x3U) #define APBH_CH4_CMD_COMMAND_SHIFT (0U) /*! COMMAND - COMMAND * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. */ #define APBH_CH4_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_COMMAND_SHIFT)) & APBH_CH4_CMD_COMMAND_MASK) #define APBH_CH4_CMD_CHAIN_MASK (0x4U) #define APBH_CH4_CMD_CHAIN_SHIFT (2U) #define APBH_CH4_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CHAIN_SHIFT)) & APBH_CH4_CMD_CHAIN_MASK) #define APBH_CH4_CMD_IRQONCMPLT_MASK (0x8U) #define APBH_CH4_CMD_IRQONCMPLT_SHIFT (3U) #define APBH_CH4_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_IRQONCMPLT_SHIFT)) & APBH_CH4_CMD_IRQONCMPLT_MASK) #define APBH_CH4_CMD_NANDLOCK_MASK (0x10U) #define APBH_CH4_CMD_NANDLOCK_SHIFT (4U) #define APBH_CH4_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDLOCK_SHIFT)) & APBH_CH4_CMD_NANDLOCK_MASK) #define APBH_CH4_CMD_NANDWAIT4READY_MASK (0x20U) #define APBH_CH4_CMD_NANDWAIT4READY_SHIFT (5U) #define APBH_CH4_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH4_CMD_NANDWAIT4READY_MASK) #define APBH_CH4_CMD_SEMAPHORE_MASK (0x40U) #define APBH_CH4_CMD_SEMAPHORE_SHIFT (6U) #define APBH_CH4_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_SEMAPHORE_SHIFT)) & APBH_CH4_CMD_SEMAPHORE_MASK) #define APBH_CH4_CMD_WAIT4ENDCMD_MASK (0x80U) #define APBH_CH4_CMD_WAIT4ENDCMD_SHIFT (7U) #define APBH_CH4_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH4_CMD_WAIT4ENDCMD_MASK) #define APBH_CH4_CMD_HALTONTERMINATE_MASK (0x100U) #define APBH_CH4_CMD_HALTONTERMINATE_SHIFT (8U) #define APBH_CH4_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH4_CMD_HALTONTERMINATE_MASK) #define APBH_CH4_CMD_CMDWORDS_MASK (0xF000U) #define APBH_CH4_CMD_CMDWORDS_SHIFT (12U) #define APBH_CH4_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CMDWORDS_SHIFT)) & APBH_CH4_CMD_CMDWORDS_MASK) #define APBH_CH4_CMD_XFER_COUNT_MASK (0xFFFF0000U) #define APBH_CH4_CMD_XFER_COUNT_SHIFT (16U) #define APBH_CH4_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_XFER_COUNT_SHIFT)) & APBH_CH4_CMD_XFER_COUNT_MASK) /*! @} */ /*! @name CH4_BAR - APBH DMA Channel n Buffer Address Register */ /*! @{ */ #define APBH_CH4_BAR_ADDRESS_MASK (0xFFFFFFFFU) #define APBH_CH4_BAR_ADDRESS_SHIFT (0U) #define APBH_CH4_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_BAR_ADDRESS_SHIFT)) & APBH_CH4_BAR_ADDRESS_MASK) /*! @} */ /*! @name CH4_SEMA - APBH DMA Channel n Semaphore Register */ /*! @{ */ #define APBH_CH4_SEMA_INCREMENT_SEMA_MASK (0xFFU) #define APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT (0U) #define APBH_CH4_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH4_SEMA_INCREMENT_SEMA_MASK) #define APBH_CH4_SEMA_PHORE_MASK (0xFF0000U) #define APBH_CH4_SEMA_PHORE_SHIFT (16U) #define APBH_CH4_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_PHORE_SHIFT)) & APBH_CH4_SEMA_PHORE_MASK) /*! @} */ /*! @name CH4_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH4_DEBUG1_STATEMACHINE_MASK (0x1FU) #define APBH_CH4_DEBUG1_STATEMACHINE_SHIFT (0U) /*! STATEMACHINE - STATEMACHINE * 0b00000..This is the idle state of the DMA state machine. * 0b00001..State in which the DMA is waiting to receive the first word of a command. * 0b00010..State in which the DMA is waiting to receive the third word of a command. * 0b00011..State in which the DMA is waiting to receive the second word of a command. * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. */ #define APBH_CH4_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH4_DEBUG1_STATEMACHINE_MASK) #define APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) #define APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT (20U) #define APBH_CH4_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK) #define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) #define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) #define APBH_CH4_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK) #define APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) #define APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT (22U) #define APBH_CH4_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK) #define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) #define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) #define APBH_CH4_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK) #define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) #define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) #define APBH_CH4_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK) #define APBH_CH4_DEBUG1_READY_MASK (0x4000000U) #define APBH_CH4_DEBUG1_READY_SHIFT (26U) #define APBH_CH4_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_READY_SHIFT)) & APBH_CH4_DEBUG1_READY_MASK) #define APBH_CH4_DEBUG1_END_MASK (0x10000000U) #define APBH_CH4_DEBUG1_END_SHIFT (28U) #define APBH_CH4_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_END_SHIFT)) & APBH_CH4_DEBUG1_END_MASK) #define APBH_CH4_DEBUG1_KICK_MASK (0x20000000U) #define APBH_CH4_DEBUG1_KICK_SHIFT (29U) #define APBH_CH4_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_KICK_SHIFT)) & APBH_CH4_DEBUG1_KICK_MASK) #define APBH_CH4_DEBUG1_BURST_MASK (0x40000000U) #define APBH_CH4_DEBUG1_BURST_SHIFT (30U) #define APBH_CH4_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_BURST_SHIFT)) & APBH_CH4_DEBUG1_BURST_MASK) #define APBH_CH4_DEBUG1_REQ_MASK (0x80000000U) #define APBH_CH4_DEBUG1_REQ_SHIFT (31U) #define APBH_CH4_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_REQ_SHIFT)) & APBH_CH4_DEBUG1_REQ_MASK) /*! @} */ /*! @name CH4_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH4_DEBUG2_AHB_BYTES_MASK (0xFFFFU) #define APBH_CH4_DEBUG2_AHB_BYTES_SHIFT (0U) #define APBH_CH4_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_AHB_BYTES_MASK) #define APBH_CH4_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) #define APBH_CH4_DEBUG2_APB_BYTES_SHIFT (16U) #define APBH_CH4_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_APB_BYTES_MASK) /*! @} */ /*! @name CH5_CURCMDAR - APBH DMA Channel n Current Command Address Register */ /*! @{ */ #define APBH_CH5_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH5_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_CURCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH5_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ /*! @{ */ #define APBH_CH5_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH5_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_NXTCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH5_CMD - APBH DMA Channel n Command Register */ /*! @{ */ #define APBH_CH5_CMD_COMMAND_MASK (0x3U) #define APBH_CH5_CMD_COMMAND_SHIFT (0U) /*! COMMAND - COMMAND * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. */ #define APBH_CH5_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_COMMAND_SHIFT)) & APBH_CH5_CMD_COMMAND_MASK) #define APBH_CH5_CMD_CHAIN_MASK (0x4U) #define APBH_CH5_CMD_CHAIN_SHIFT (2U) #define APBH_CH5_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CHAIN_SHIFT)) & APBH_CH5_CMD_CHAIN_MASK) #define APBH_CH5_CMD_IRQONCMPLT_MASK (0x8U) #define APBH_CH5_CMD_IRQONCMPLT_SHIFT (3U) #define APBH_CH5_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_IRQONCMPLT_SHIFT)) & APBH_CH5_CMD_IRQONCMPLT_MASK) #define APBH_CH5_CMD_NANDLOCK_MASK (0x10U) #define APBH_CH5_CMD_NANDLOCK_SHIFT (4U) #define APBH_CH5_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK) #define APBH_CH5_CMD_NANDWAIT4READY_MASK (0x20U) #define APBH_CH5_CMD_NANDWAIT4READY_SHIFT (5U) #define APBH_CH5_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH5_CMD_NANDWAIT4READY_MASK) #define APBH_CH5_CMD_SEMAPHORE_MASK (0x40U) #define APBH_CH5_CMD_SEMAPHORE_SHIFT (6U) #define APBH_CH5_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_SEMAPHORE_SHIFT)) & APBH_CH5_CMD_SEMAPHORE_MASK) #define APBH_CH5_CMD_WAIT4ENDCMD_MASK (0x80U) #define APBH_CH5_CMD_WAIT4ENDCMD_SHIFT (7U) #define APBH_CH5_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH5_CMD_WAIT4ENDCMD_MASK) #define APBH_CH5_CMD_HALTONTERMINATE_MASK (0x100U) #define APBH_CH5_CMD_HALTONTERMINATE_SHIFT (8U) #define APBH_CH5_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH5_CMD_HALTONTERMINATE_MASK) #define APBH_CH5_CMD_CMDWORDS_MASK (0xF000U) #define APBH_CH5_CMD_CMDWORDS_SHIFT (12U) #define APBH_CH5_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CMDWORDS_SHIFT)) & APBH_CH5_CMD_CMDWORDS_MASK) #define APBH_CH5_CMD_XFER_COUNT_MASK (0xFFFF0000U) #define APBH_CH5_CMD_XFER_COUNT_SHIFT (16U) #define APBH_CH5_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_XFER_COUNT_SHIFT)) & APBH_CH5_CMD_XFER_COUNT_MASK) /*! @} */ /*! @name CH5_BAR - APBH DMA Channel n Buffer Address Register */ /*! @{ */ #define APBH_CH5_BAR_ADDRESS_MASK (0xFFFFFFFFU) #define APBH_CH5_BAR_ADDRESS_SHIFT (0U) #define APBH_CH5_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_BAR_ADDRESS_SHIFT)) & APBH_CH5_BAR_ADDRESS_MASK) /*! @} */ /*! @name CH5_SEMA - APBH DMA Channel n Semaphore Register */ /*! @{ */ #define APBH_CH5_SEMA_INCREMENT_SEMA_MASK (0xFFU) #define APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT (0U) #define APBH_CH5_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH5_SEMA_INCREMENT_SEMA_MASK) #define APBH_CH5_SEMA_PHORE_MASK (0xFF0000U) #define APBH_CH5_SEMA_PHORE_SHIFT (16U) #define APBH_CH5_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_PHORE_SHIFT)) & APBH_CH5_SEMA_PHORE_MASK) /*! @} */ /*! @name CH5_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH5_DEBUG1_STATEMACHINE_MASK (0x1FU) #define APBH_CH5_DEBUG1_STATEMACHINE_SHIFT (0U) /*! STATEMACHINE - STATEMACHINE * 0b00000..This is the idle state of the DMA state machine. * 0b00001..State in which the DMA is waiting to receive the first word of a command. * 0b00010..State in which the DMA is waiting to receive the third word of a command. * 0b00011..State in which the DMA is waiting to receive the second word of a command. * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. */ #define APBH_CH5_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH5_DEBUG1_STATEMACHINE_MASK) #define APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) #define APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT (20U) #define APBH_CH5_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK) #define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) #define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) #define APBH_CH5_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK) #define APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) #define APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT (22U) #define APBH_CH5_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK) #define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) #define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) #define APBH_CH5_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK) #define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) #define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) #define APBH_CH5_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK) #define APBH_CH5_DEBUG1_READY_MASK (0x4000000U) #define APBH_CH5_DEBUG1_READY_SHIFT (26U) #define APBH_CH5_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_READY_SHIFT)) & APBH_CH5_DEBUG1_READY_MASK) #define APBH_CH5_DEBUG1_END_MASK (0x10000000U) #define APBH_CH5_DEBUG1_END_SHIFT (28U) #define APBH_CH5_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_END_SHIFT)) & APBH_CH5_DEBUG1_END_MASK) #define APBH_CH5_DEBUG1_KICK_MASK (0x20000000U) #define APBH_CH5_DEBUG1_KICK_SHIFT (29U) #define APBH_CH5_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_KICK_SHIFT)) & APBH_CH5_DEBUG1_KICK_MASK) #define APBH_CH5_DEBUG1_BURST_MASK (0x40000000U) #define APBH_CH5_DEBUG1_BURST_SHIFT (30U) #define APBH_CH5_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_BURST_SHIFT)) & APBH_CH5_DEBUG1_BURST_MASK) #define APBH_CH5_DEBUG1_REQ_MASK (0x80000000U) #define APBH_CH5_DEBUG1_REQ_SHIFT (31U) #define APBH_CH5_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_REQ_SHIFT)) & APBH_CH5_DEBUG1_REQ_MASK) /*! @} */ /*! @name CH5_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH5_DEBUG2_AHB_BYTES_MASK (0xFFFFU) #define APBH_CH5_DEBUG2_AHB_BYTES_SHIFT (0U) #define APBH_CH5_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_AHB_BYTES_MASK) #define APBH_CH5_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) #define APBH_CH5_DEBUG2_APB_BYTES_SHIFT (16U) #define APBH_CH5_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_APB_BYTES_MASK) /*! @} */ /*! @name CH6_CURCMDAR - APBH DMA Channel n Current Command Address Register */ /*! @{ */ #define APBH_CH6_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH6_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_CURCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH6_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ /*! @{ */ #define APBH_CH6_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH6_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_NXTCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH6_CMD - APBH DMA Channel n Command Register */ /*! @{ */ #define APBH_CH6_CMD_COMMAND_MASK (0x3U) #define APBH_CH6_CMD_COMMAND_SHIFT (0U) /*! COMMAND - COMMAND * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. */ #define APBH_CH6_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_COMMAND_SHIFT)) & APBH_CH6_CMD_COMMAND_MASK) #define APBH_CH6_CMD_CHAIN_MASK (0x4U) #define APBH_CH6_CMD_CHAIN_SHIFT (2U) #define APBH_CH6_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CHAIN_SHIFT)) & APBH_CH6_CMD_CHAIN_MASK) #define APBH_CH6_CMD_IRQONCMPLT_MASK (0x8U) #define APBH_CH6_CMD_IRQONCMPLT_SHIFT (3U) #define APBH_CH6_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_IRQONCMPLT_SHIFT)) & APBH_CH6_CMD_IRQONCMPLT_MASK) #define APBH_CH6_CMD_NANDLOCK_MASK (0x10U) #define APBH_CH6_CMD_NANDLOCK_SHIFT (4U) #define APBH_CH6_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDLOCK_SHIFT)) & APBH_CH6_CMD_NANDLOCK_MASK) #define APBH_CH6_CMD_NANDWAIT4READY_MASK (0x20U) #define APBH_CH6_CMD_NANDWAIT4READY_SHIFT (5U) #define APBH_CH6_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH6_CMD_NANDWAIT4READY_MASK) #define APBH_CH6_CMD_SEMAPHORE_MASK (0x40U) #define APBH_CH6_CMD_SEMAPHORE_SHIFT (6U) #define APBH_CH6_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_SEMAPHORE_SHIFT)) & APBH_CH6_CMD_SEMAPHORE_MASK) #define APBH_CH6_CMD_WAIT4ENDCMD_MASK (0x80U) #define APBH_CH6_CMD_WAIT4ENDCMD_SHIFT (7U) #define APBH_CH6_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH6_CMD_WAIT4ENDCMD_MASK) #define APBH_CH6_CMD_HALTONTERMINATE_MASK (0x100U) #define APBH_CH6_CMD_HALTONTERMINATE_SHIFT (8U) #define APBH_CH6_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH6_CMD_HALTONTERMINATE_MASK) #define APBH_CH6_CMD_CMDWORDS_MASK (0xF000U) #define APBH_CH6_CMD_CMDWORDS_SHIFT (12U) #define APBH_CH6_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CMDWORDS_SHIFT)) & APBH_CH6_CMD_CMDWORDS_MASK) #define APBH_CH6_CMD_XFER_COUNT_MASK (0xFFFF0000U) #define APBH_CH6_CMD_XFER_COUNT_SHIFT (16U) #define APBH_CH6_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_XFER_COUNT_SHIFT)) & APBH_CH6_CMD_XFER_COUNT_MASK) /*! @} */ /*! @name CH6_BAR - APBH DMA Channel n Buffer Address Register */ /*! @{ */ #define APBH_CH6_BAR_ADDRESS_MASK (0xFFFFFFFFU) #define APBH_CH6_BAR_ADDRESS_SHIFT (0U) #define APBH_CH6_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_BAR_ADDRESS_SHIFT)) & APBH_CH6_BAR_ADDRESS_MASK) /*! @} */ /*! @name CH6_SEMA - APBH DMA Channel n Semaphore Register */ /*! @{ */ #define APBH_CH6_SEMA_INCREMENT_SEMA_MASK (0xFFU) #define APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT (0U) #define APBH_CH6_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH6_SEMA_INCREMENT_SEMA_MASK) #define APBH_CH6_SEMA_PHORE_MASK (0xFF0000U) #define APBH_CH6_SEMA_PHORE_SHIFT (16U) #define APBH_CH6_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_PHORE_SHIFT)) & APBH_CH6_SEMA_PHORE_MASK) /*! @} */ /*! @name CH6_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH6_DEBUG1_STATEMACHINE_MASK (0x1FU) #define APBH_CH6_DEBUG1_STATEMACHINE_SHIFT (0U) /*! STATEMACHINE - STATEMACHINE * 0b00000..This is the idle state of the DMA state machine. * 0b00001..State in which the DMA is waiting to receive the first word of a command. * 0b00010..State in which the DMA is waiting to receive the third word of a command. * 0b00011..State in which the DMA is waiting to receive the second word of a command. * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. */ #define APBH_CH6_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH6_DEBUG1_STATEMACHINE_MASK) #define APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) #define APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT (20U) #define APBH_CH6_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK) #define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) #define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) #define APBH_CH6_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK) #define APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) #define APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT (22U) #define APBH_CH6_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK) #define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) #define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) #define APBH_CH6_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK) #define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) #define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) #define APBH_CH6_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK) #define APBH_CH6_DEBUG1_READY_MASK (0x4000000U) #define APBH_CH6_DEBUG1_READY_SHIFT (26U) #define APBH_CH6_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_READY_SHIFT)) & APBH_CH6_DEBUG1_READY_MASK) #define APBH_CH6_DEBUG1_END_MASK (0x10000000U) #define APBH_CH6_DEBUG1_END_SHIFT (28U) #define APBH_CH6_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_END_SHIFT)) & APBH_CH6_DEBUG1_END_MASK) #define APBH_CH6_DEBUG1_KICK_MASK (0x20000000U) #define APBH_CH6_DEBUG1_KICK_SHIFT (29U) #define APBH_CH6_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_KICK_SHIFT)) & APBH_CH6_DEBUG1_KICK_MASK) #define APBH_CH6_DEBUG1_BURST_MASK (0x40000000U) #define APBH_CH6_DEBUG1_BURST_SHIFT (30U) #define APBH_CH6_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_BURST_SHIFT)) & APBH_CH6_DEBUG1_BURST_MASK) #define APBH_CH6_DEBUG1_REQ_MASK (0x80000000U) #define APBH_CH6_DEBUG1_REQ_SHIFT (31U) #define APBH_CH6_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_REQ_SHIFT)) & APBH_CH6_DEBUG1_REQ_MASK) /*! @} */ /*! @name CH6_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH6_DEBUG2_AHB_BYTES_MASK (0xFFFFU) #define APBH_CH6_DEBUG2_AHB_BYTES_SHIFT (0U) #define APBH_CH6_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_AHB_BYTES_MASK) #define APBH_CH6_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) #define APBH_CH6_DEBUG2_APB_BYTES_SHIFT (16U) #define APBH_CH6_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_APB_BYTES_MASK) /*! @} */ /*! @name CH7_CURCMDAR - APBH DMA Channel n Current Command Address Register */ /*! @{ */ #define APBH_CH7_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH7_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_CURCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH7_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ /*! @{ */ #define APBH_CH7_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH7_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_NXTCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH7_CMD - APBH DMA Channel n Command Register */ /*! @{ */ #define APBH_CH7_CMD_COMMAND_MASK (0x3U) #define APBH_CH7_CMD_COMMAND_SHIFT (0U) /*! COMMAND - COMMAND * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. */ #define APBH_CH7_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_COMMAND_SHIFT)) & APBH_CH7_CMD_COMMAND_MASK) #define APBH_CH7_CMD_CHAIN_MASK (0x4U) #define APBH_CH7_CMD_CHAIN_SHIFT (2U) #define APBH_CH7_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CHAIN_SHIFT)) & APBH_CH7_CMD_CHAIN_MASK) #define APBH_CH7_CMD_IRQONCMPLT_MASK (0x8U) #define APBH_CH7_CMD_IRQONCMPLT_SHIFT (3U) #define APBH_CH7_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_IRQONCMPLT_SHIFT)) & APBH_CH7_CMD_IRQONCMPLT_MASK) #define APBH_CH7_CMD_NANDLOCK_MASK (0x10U) #define APBH_CH7_CMD_NANDLOCK_SHIFT (4U) #define APBH_CH7_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_NANDLOCK_SHIFT)) & APBH_CH7_CMD_NANDLOCK_MASK) #define APBH_CH7_CMD_NANDWAIT4READY_MASK (0x20U) #define APBH_CH7_CMD_NANDWAIT4READY_SHIFT (5U) #define APBH_CH7_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH7_CMD_NANDWAIT4READY_MASK) #define APBH_CH7_CMD_SEMAPHORE_MASK (0x40U) #define APBH_CH7_CMD_SEMAPHORE_SHIFT (6U) #define APBH_CH7_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_SEMAPHORE_SHIFT)) & APBH_CH7_CMD_SEMAPHORE_MASK) #define APBH_CH7_CMD_WAIT4ENDCMD_MASK (0x80U) #define APBH_CH7_CMD_WAIT4ENDCMD_SHIFT (7U) #define APBH_CH7_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH7_CMD_WAIT4ENDCMD_MASK) #define APBH_CH7_CMD_HALTONTERMINATE_MASK (0x100U) #define APBH_CH7_CMD_HALTONTERMINATE_SHIFT (8U) #define APBH_CH7_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH7_CMD_HALTONTERMINATE_MASK) #define APBH_CH7_CMD_CMDWORDS_MASK (0xF000U) #define APBH_CH7_CMD_CMDWORDS_SHIFT (12U) #define APBH_CH7_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CMDWORDS_SHIFT)) & APBH_CH7_CMD_CMDWORDS_MASK) #define APBH_CH7_CMD_XFER_COUNT_MASK (0xFFFF0000U) #define APBH_CH7_CMD_XFER_COUNT_SHIFT (16U) #define APBH_CH7_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_XFER_COUNT_SHIFT)) & APBH_CH7_CMD_XFER_COUNT_MASK) /*! @} */ /*! @name CH7_BAR - APBH DMA Channel n Buffer Address Register */ /*! @{ */ #define APBH_CH7_BAR_ADDRESS_MASK (0xFFFFFFFFU) #define APBH_CH7_BAR_ADDRESS_SHIFT (0U) #define APBH_CH7_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_BAR_ADDRESS_SHIFT)) & APBH_CH7_BAR_ADDRESS_MASK) /*! @} */ /*! @name CH7_SEMA - APBH DMA Channel n Semaphore Register */ /*! @{ */ #define APBH_CH7_SEMA_INCREMENT_SEMA_MASK (0xFFU) #define APBH_CH7_SEMA_INCREMENT_SEMA_SHIFT (0U) #define APBH_CH7_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH7_SEMA_INCREMENT_SEMA_MASK) #define APBH_CH7_SEMA_PHORE_MASK (0xFF0000U) #define APBH_CH7_SEMA_PHORE_SHIFT (16U) #define APBH_CH7_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_SEMA_PHORE_SHIFT)) & APBH_CH7_SEMA_PHORE_MASK) /*! @} */ /*! @name CH7_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH7_DEBUG1_STATEMACHINE_MASK (0x1FU) #define APBH_CH7_DEBUG1_STATEMACHINE_SHIFT (0U) /*! STATEMACHINE - STATEMACHINE * 0b00000..This is the idle state of the DMA state machine. * 0b00001..State in which the DMA is waiting to receive the first word of a command. * 0b00010..State in which the DMA is waiting to receive the third word of a command. * 0b00011..State in which the DMA is waiting to receive the second word of a command. * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. */ #define APBH_CH7_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH7_DEBUG1_STATEMACHINE_MASK) #define APBH_CH7_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) #define APBH_CH7_DEBUG1_WR_FIFO_FULL_SHIFT (20U) #define APBH_CH7_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH7_DEBUG1_WR_FIFO_FULL_MASK) #define APBH_CH7_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) #define APBH_CH7_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) #define APBH_CH7_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH7_DEBUG1_WR_FIFO_EMPTY_MASK) #define APBH_CH7_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) #define APBH_CH7_DEBUG1_RD_FIFO_FULL_SHIFT (22U) #define APBH_CH7_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH7_DEBUG1_RD_FIFO_FULL_MASK) #define APBH_CH7_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) #define APBH_CH7_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) #define APBH_CH7_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH7_DEBUG1_RD_FIFO_EMPTY_MASK) #define APBH_CH7_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) #define APBH_CH7_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) #define APBH_CH7_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH7_DEBUG1_NEXTCMDADDRVALID_MASK) #define APBH_CH7_DEBUG1_READY_MASK (0x4000000U) #define APBH_CH7_DEBUG1_READY_SHIFT (26U) #define APBH_CH7_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_READY_SHIFT)) & APBH_CH7_DEBUG1_READY_MASK) #define APBH_CH7_DEBUG1_END_MASK (0x10000000U) #define APBH_CH7_DEBUG1_END_SHIFT (28U) #define APBH_CH7_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_END_SHIFT)) & APBH_CH7_DEBUG1_END_MASK) #define APBH_CH7_DEBUG1_KICK_MASK (0x20000000U) #define APBH_CH7_DEBUG1_KICK_SHIFT (29U) #define APBH_CH7_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_KICK_SHIFT)) & APBH_CH7_DEBUG1_KICK_MASK) #define APBH_CH7_DEBUG1_BURST_MASK (0x40000000U) #define APBH_CH7_DEBUG1_BURST_SHIFT (30U) #define APBH_CH7_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_BURST_SHIFT)) & APBH_CH7_DEBUG1_BURST_MASK) #define APBH_CH7_DEBUG1_REQ_MASK (0x80000000U) #define APBH_CH7_DEBUG1_REQ_SHIFT (31U) #define APBH_CH7_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_REQ_SHIFT)) & APBH_CH7_DEBUG1_REQ_MASK) /*! @} */ /*! @name CH7_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH7_DEBUG2_AHB_BYTES_MASK (0xFFFFU) #define APBH_CH7_DEBUG2_AHB_BYTES_SHIFT (0U) #define APBH_CH7_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH7_DEBUG2_AHB_BYTES_MASK) #define APBH_CH7_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) #define APBH_CH7_DEBUG2_APB_BYTES_SHIFT (16U) #define APBH_CH7_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH7_DEBUG2_APB_BYTES_MASK) /*! @} */ /*! @name CH8_CURCMDAR - APBH DMA Channel n Current Command Address Register */ /*! @{ */ #define APBH_CH8_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH8_CURCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH8_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH8_CURCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH8_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ /*! @{ */ #define APBH_CH8_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH8_NXTCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH8_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH8_NXTCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH8_CMD - APBH DMA Channel n Command Register */ /*! @{ */ #define APBH_CH8_CMD_COMMAND_MASK (0x3U) #define APBH_CH8_CMD_COMMAND_SHIFT (0U) /*! COMMAND - COMMAND * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. */ #define APBH_CH8_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_COMMAND_SHIFT)) & APBH_CH8_CMD_COMMAND_MASK) #define APBH_CH8_CMD_CHAIN_MASK (0x4U) #define APBH_CH8_CMD_CHAIN_SHIFT (2U) #define APBH_CH8_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_CHAIN_SHIFT)) & APBH_CH8_CMD_CHAIN_MASK) #define APBH_CH8_CMD_IRQONCMPLT_MASK (0x8U) #define APBH_CH8_CMD_IRQONCMPLT_SHIFT (3U) #define APBH_CH8_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_IRQONCMPLT_SHIFT)) & APBH_CH8_CMD_IRQONCMPLT_MASK) #define APBH_CH8_CMD_NANDLOCK_MASK (0x10U) #define APBH_CH8_CMD_NANDLOCK_SHIFT (4U) #define APBH_CH8_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_NANDLOCK_SHIFT)) & APBH_CH8_CMD_NANDLOCK_MASK) #define APBH_CH8_CMD_NANDWAIT4READY_MASK (0x20U) #define APBH_CH8_CMD_NANDWAIT4READY_SHIFT (5U) #define APBH_CH8_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH8_CMD_NANDWAIT4READY_MASK) #define APBH_CH8_CMD_SEMAPHORE_MASK (0x40U) #define APBH_CH8_CMD_SEMAPHORE_SHIFT (6U) #define APBH_CH8_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_SEMAPHORE_SHIFT)) & APBH_CH8_CMD_SEMAPHORE_MASK) #define APBH_CH8_CMD_WAIT4ENDCMD_MASK (0x80U) #define APBH_CH8_CMD_WAIT4ENDCMD_SHIFT (7U) #define APBH_CH8_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH8_CMD_WAIT4ENDCMD_MASK) #define APBH_CH8_CMD_HALTONTERMINATE_MASK (0x100U) #define APBH_CH8_CMD_HALTONTERMINATE_SHIFT (8U) #define APBH_CH8_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH8_CMD_HALTONTERMINATE_MASK) #define APBH_CH8_CMD_CMDWORDS_MASK (0xF000U) #define APBH_CH8_CMD_CMDWORDS_SHIFT (12U) #define APBH_CH8_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_CMDWORDS_SHIFT)) & APBH_CH8_CMD_CMDWORDS_MASK) #define APBH_CH8_CMD_XFER_COUNT_MASK (0xFFFF0000U) #define APBH_CH8_CMD_XFER_COUNT_SHIFT (16U) #define APBH_CH8_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_XFER_COUNT_SHIFT)) & APBH_CH8_CMD_XFER_COUNT_MASK) /*! @} */ /*! @name CH8_BAR - APBH DMA Channel n Buffer Address Register */ /*! @{ */ #define APBH_CH8_BAR_ADDRESS_MASK (0xFFFFFFFFU) #define APBH_CH8_BAR_ADDRESS_SHIFT (0U) #define APBH_CH8_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_BAR_ADDRESS_SHIFT)) & APBH_CH8_BAR_ADDRESS_MASK) /*! @} */ /*! @name CH8_SEMA - APBH DMA Channel n Semaphore Register */ /*! @{ */ #define APBH_CH8_SEMA_INCREMENT_SEMA_MASK (0xFFU) #define APBH_CH8_SEMA_INCREMENT_SEMA_SHIFT (0U) #define APBH_CH8_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH8_SEMA_INCREMENT_SEMA_MASK) #define APBH_CH8_SEMA_PHORE_MASK (0xFF0000U) #define APBH_CH8_SEMA_PHORE_SHIFT (16U) #define APBH_CH8_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_SEMA_PHORE_SHIFT)) & APBH_CH8_SEMA_PHORE_MASK) /*! @} */ /*! @name CH8_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH8_DEBUG1_STATEMACHINE_MASK (0x1FU) #define APBH_CH8_DEBUG1_STATEMACHINE_SHIFT (0U) /*! STATEMACHINE - STATEMACHINE * 0b00000..This is the idle state of the DMA state machine. * 0b00001..State in which the DMA is waiting to receive the first word of a command. * 0b00010..State in which the DMA is waiting to receive the third word of a command. * 0b00011..State in which the DMA is waiting to receive the second word of a command. * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. */ #define APBH_CH8_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH8_DEBUG1_STATEMACHINE_MASK) #define APBH_CH8_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) #define APBH_CH8_DEBUG1_WR_FIFO_FULL_SHIFT (20U) #define APBH_CH8_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH8_DEBUG1_WR_FIFO_FULL_MASK) #define APBH_CH8_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) #define APBH_CH8_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) #define APBH_CH8_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH8_DEBUG1_WR_FIFO_EMPTY_MASK) #define APBH_CH8_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) #define APBH_CH8_DEBUG1_RD_FIFO_FULL_SHIFT (22U) #define APBH_CH8_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH8_DEBUG1_RD_FIFO_FULL_MASK) #define APBH_CH8_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) #define APBH_CH8_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) #define APBH_CH8_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH8_DEBUG1_RD_FIFO_EMPTY_MASK) #define APBH_CH8_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) #define APBH_CH8_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) #define APBH_CH8_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH8_DEBUG1_NEXTCMDADDRVALID_MASK) #define APBH_CH8_DEBUG1_READY_MASK (0x4000000U) #define APBH_CH8_DEBUG1_READY_SHIFT (26U) #define APBH_CH8_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_READY_SHIFT)) & APBH_CH8_DEBUG1_READY_MASK) #define APBH_CH8_DEBUG1_END_MASK (0x10000000U) #define APBH_CH8_DEBUG1_END_SHIFT (28U) #define APBH_CH8_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_END_SHIFT)) & APBH_CH8_DEBUG1_END_MASK) #define APBH_CH8_DEBUG1_KICK_MASK (0x20000000U) #define APBH_CH8_DEBUG1_KICK_SHIFT (29U) #define APBH_CH8_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_KICK_SHIFT)) & APBH_CH8_DEBUG1_KICK_MASK) #define APBH_CH8_DEBUG1_BURST_MASK (0x40000000U) #define APBH_CH8_DEBUG1_BURST_SHIFT (30U) #define APBH_CH8_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_BURST_SHIFT)) & APBH_CH8_DEBUG1_BURST_MASK) #define APBH_CH8_DEBUG1_REQ_MASK (0x80000000U) #define APBH_CH8_DEBUG1_REQ_SHIFT (31U) #define APBH_CH8_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_REQ_SHIFT)) & APBH_CH8_DEBUG1_REQ_MASK) /*! @} */ /*! @name CH8_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH8_DEBUG2_AHB_BYTES_MASK (0xFFFFU) #define APBH_CH8_DEBUG2_AHB_BYTES_SHIFT (0U) #define APBH_CH8_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH8_DEBUG2_AHB_BYTES_MASK) #define APBH_CH8_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) #define APBH_CH8_DEBUG2_APB_BYTES_SHIFT (16U) #define APBH_CH8_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH8_DEBUG2_APB_BYTES_MASK) /*! @} */ /*! @name CH9_CURCMDAR - APBH DMA Channel n Current Command Address Register */ /*! @{ */ #define APBH_CH9_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH9_CURCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH9_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH9_CURCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH9_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ /*! @{ */ #define APBH_CH9_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH9_NXTCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH9_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH9_NXTCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH9_CMD - APBH DMA Channel n Command Register */ /*! @{ */ #define APBH_CH9_CMD_COMMAND_MASK (0x3U) #define APBH_CH9_CMD_COMMAND_SHIFT (0U) /*! COMMAND - COMMAND * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. */ #define APBH_CH9_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_COMMAND_SHIFT)) & APBH_CH9_CMD_COMMAND_MASK) #define APBH_CH9_CMD_CHAIN_MASK (0x4U) #define APBH_CH9_CMD_CHAIN_SHIFT (2U) #define APBH_CH9_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_CHAIN_SHIFT)) & APBH_CH9_CMD_CHAIN_MASK) #define APBH_CH9_CMD_IRQONCMPLT_MASK (0x8U) #define APBH_CH9_CMD_IRQONCMPLT_SHIFT (3U) #define APBH_CH9_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_IRQONCMPLT_SHIFT)) & APBH_CH9_CMD_IRQONCMPLT_MASK) #define APBH_CH9_CMD_NANDLOCK_MASK (0x10U) #define APBH_CH9_CMD_NANDLOCK_SHIFT (4U) #define APBH_CH9_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_NANDLOCK_SHIFT)) & APBH_CH9_CMD_NANDLOCK_MASK) #define APBH_CH9_CMD_NANDWAIT4READY_MASK (0x20U) #define APBH_CH9_CMD_NANDWAIT4READY_SHIFT (5U) #define APBH_CH9_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH9_CMD_NANDWAIT4READY_MASK) #define APBH_CH9_CMD_SEMAPHORE_MASK (0x40U) #define APBH_CH9_CMD_SEMAPHORE_SHIFT (6U) #define APBH_CH9_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_SEMAPHORE_SHIFT)) & APBH_CH9_CMD_SEMAPHORE_MASK) #define APBH_CH9_CMD_WAIT4ENDCMD_MASK (0x80U) #define APBH_CH9_CMD_WAIT4ENDCMD_SHIFT (7U) #define APBH_CH9_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH9_CMD_WAIT4ENDCMD_MASK) #define APBH_CH9_CMD_HALTONTERMINATE_MASK (0x100U) #define APBH_CH9_CMD_HALTONTERMINATE_SHIFT (8U) #define APBH_CH9_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH9_CMD_HALTONTERMINATE_MASK) #define APBH_CH9_CMD_CMDWORDS_MASK (0xF000U) #define APBH_CH9_CMD_CMDWORDS_SHIFT (12U) #define APBH_CH9_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_CMDWORDS_SHIFT)) & APBH_CH9_CMD_CMDWORDS_MASK) #define APBH_CH9_CMD_XFER_COUNT_MASK (0xFFFF0000U) #define APBH_CH9_CMD_XFER_COUNT_SHIFT (16U) #define APBH_CH9_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_XFER_COUNT_SHIFT)) & APBH_CH9_CMD_XFER_COUNT_MASK) /*! @} */ /*! @name CH9_BAR - APBH DMA Channel n Buffer Address Register */ /*! @{ */ #define APBH_CH9_BAR_ADDRESS_MASK (0xFFFFFFFFU) #define APBH_CH9_BAR_ADDRESS_SHIFT (0U) #define APBH_CH9_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_BAR_ADDRESS_SHIFT)) & APBH_CH9_BAR_ADDRESS_MASK) /*! @} */ /*! @name CH9_SEMA - APBH DMA Channel n Semaphore Register */ /*! @{ */ #define APBH_CH9_SEMA_INCREMENT_SEMA_MASK (0xFFU) #define APBH_CH9_SEMA_INCREMENT_SEMA_SHIFT (0U) #define APBH_CH9_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH9_SEMA_INCREMENT_SEMA_MASK) #define APBH_CH9_SEMA_PHORE_MASK (0xFF0000U) #define APBH_CH9_SEMA_PHORE_SHIFT (16U) #define APBH_CH9_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_SEMA_PHORE_SHIFT)) & APBH_CH9_SEMA_PHORE_MASK) /*! @} */ /*! @name CH9_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH9_DEBUG1_STATEMACHINE_MASK (0x1FU) #define APBH_CH9_DEBUG1_STATEMACHINE_SHIFT (0U) /*! STATEMACHINE - STATEMACHINE * 0b00000..This is the idle state of the DMA state machine. * 0b00001..State in which the DMA is waiting to receive the first word of a command. * 0b00010..State in which the DMA is waiting to receive the third word of a command. * 0b00011..State in which the DMA is waiting to receive the second word of a command. * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. */ #define APBH_CH9_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH9_DEBUG1_STATEMACHINE_MASK) #define APBH_CH9_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) #define APBH_CH9_DEBUG1_WR_FIFO_FULL_SHIFT (20U) #define APBH_CH9_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH9_DEBUG1_WR_FIFO_FULL_MASK) #define APBH_CH9_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) #define APBH_CH9_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) #define APBH_CH9_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH9_DEBUG1_WR_FIFO_EMPTY_MASK) #define APBH_CH9_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) #define APBH_CH9_DEBUG1_RD_FIFO_FULL_SHIFT (22U) #define APBH_CH9_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH9_DEBUG1_RD_FIFO_FULL_MASK) #define APBH_CH9_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) #define APBH_CH9_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) #define APBH_CH9_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH9_DEBUG1_RD_FIFO_EMPTY_MASK) #define APBH_CH9_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) #define APBH_CH9_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) #define APBH_CH9_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH9_DEBUG1_NEXTCMDADDRVALID_MASK) #define APBH_CH9_DEBUG1_READY_MASK (0x4000000U) #define APBH_CH9_DEBUG1_READY_SHIFT (26U) #define APBH_CH9_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_READY_SHIFT)) & APBH_CH9_DEBUG1_READY_MASK) #define APBH_CH9_DEBUG1_END_MASK (0x10000000U) #define APBH_CH9_DEBUG1_END_SHIFT (28U) #define APBH_CH9_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_END_SHIFT)) & APBH_CH9_DEBUG1_END_MASK) #define APBH_CH9_DEBUG1_KICK_MASK (0x20000000U) #define APBH_CH9_DEBUG1_KICK_SHIFT (29U) #define APBH_CH9_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_KICK_SHIFT)) & APBH_CH9_DEBUG1_KICK_MASK) #define APBH_CH9_DEBUG1_BURST_MASK (0x40000000U) #define APBH_CH9_DEBUG1_BURST_SHIFT (30U) #define APBH_CH9_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_BURST_SHIFT)) & APBH_CH9_DEBUG1_BURST_MASK) #define APBH_CH9_DEBUG1_REQ_MASK (0x80000000U) #define APBH_CH9_DEBUG1_REQ_SHIFT (31U) #define APBH_CH9_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_REQ_SHIFT)) & APBH_CH9_DEBUG1_REQ_MASK) /*! @} */ /*! @name CH9_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH9_DEBUG2_AHB_BYTES_MASK (0xFFFFU) #define APBH_CH9_DEBUG2_AHB_BYTES_SHIFT (0U) #define APBH_CH9_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH9_DEBUG2_AHB_BYTES_MASK) #define APBH_CH9_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) #define APBH_CH9_DEBUG2_APB_BYTES_SHIFT (16U) #define APBH_CH9_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH9_DEBUG2_APB_BYTES_MASK) /*! @} */ /*! @name CH10_CURCMDAR - APBH DMA Channel n Current Command Address Register */ /*! @{ */ #define APBH_CH10_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH10_CURCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH10_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH10_CURCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH10_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ /*! @{ */ #define APBH_CH10_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH10_NXTCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH10_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH10_NXTCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH10_CMD - APBH DMA Channel n Command Register */ /*! @{ */ #define APBH_CH10_CMD_COMMAND_MASK (0x3U) #define APBH_CH10_CMD_COMMAND_SHIFT (0U) /*! COMMAND - COMMAND * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. */ #define APBH_CH10_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_COMMAND_SHIFT)) & APBH_CH10_CMD_COMMAND_MASK) #define APBH_CH10_CMD_CHAIN_MASK (0x4U) #define APBH_CH10_CMD_CHAIN_SHIFT (2U) #define APBH_CH10_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_CHAIN_SHIFT)) & APBH_CH10_CMD_CHAIN_MASK) #define APBH_CH10_CMD_IRQONCMPLT_MASK (0x8U) #define APBH_CH10_CMD_IRQONCMPLT_SHIFT (3U) #define APBH_CH10_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_IRQONCMPLT_SHIFT)) & APBH_CH10_CMD_IRQONCMPLT_MASK) #define APBH_CH10_CMD_NANDLOCK_MASK (0x10U) #define APBH_CH10_CMD_NANDLOCK_SHIFT (4U) #define APBH_CH10_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_NANDLOCK_SHIFT)) & APBH_CH10_CMD_NANDLOCK_MASK) #define APBH_CH10_CMD_NANDWAIT4READY_MASK (0x20U) #define APBH_CH10_CMD_NANDWAIT4READY_SHIFT (5U) #define APBH_CH10_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH10_CMD_NANDWAIT4READY_MASK) #define APBH_CH10_CMD_SEMAPHORE_MASK (0x40U) #define APBH_CH10_CMD_SEMAPHORE_SHIFT (6U) #define APBH_CH10_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_SEMAPHORE_SHIFT)) & APBH_CH10_CMD_SEMAPHORE_MASK) #define APBH_CH10_CMD_WAIT4ENDCMD_MASK (0x80U) #define APBH_CH10_CMD_WAIT4ENDCMD_SHIFT (7U) #define APBH_CH10_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH10_CMD_WAIT4ENDCMD_MASK) #define APBH_CH10_CMD_HALTONTERMINATE_MASK (0x100U) #define APBH_CH10_CMD_HALTONTERMINATE_SHIFT (8U) #define APBH_CH10_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH10_CMD_HALTONTERMINATE_MASK) #define APBH_CH10_CMD_CMDWORDS_MASK (0xF000U) #define APBH_CH10_CMD_CMDWORDS_SHIFT (12U) #define APBH_CH10_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_CMDWORDS_SHIFT)) & APBH_CH10_CMD_CMDWORDS_MASK) #define APBH_CH10_CMD_XFER_COUNT_MASK (0xFFFF0000U) #define APBH_CH10_CMD_XFER_COUNT_SHIFT (16U) #define APBH_CH10_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_XFER_COUNT_SHIFT)) & APBH_CH10_CMD_XFER_COUNT_MASK) /*! @} */ /*! @name CH10_BAR - APBH DMA Channel n Buffer Address Register */ /*! @{ */ #define APBH_CH10_BAR_ADDRESS_MASK (0xFFFFFFFFU) #define APBH_CH10_BAR_ADDRESS_SHIFT (0U) #define APBH_CH10_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_BAR_ADDRESS_SHIFT)) & APBH_CH10_BAR_ADDRESS_MASK) /*! @} */ /*! @name CH10_SEMA - APBH DMA Channel n Semaphore Register */ /*! @{ */ #define APBH_CH10_SEMA_INCREMENT_SEMA_MASK (0xFFU) #define APBH_CH10_SEMA_INCREMENT_SEMA_SHIFT (0U) #define APBH_CH10_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH10_SEMA_INCREMENT_SEMA_MASK) #define APBH_CH10_SEMA_PHORE_MASK (0xFF0000U) #define APBH_CH10_SEMA_PHORE_SHIFT (16U) #define APBH_CH10_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_SEMA_PHORE_SHIFT)) & APBH_CH10_SEMA_PHORE_MASK) /*! @} */ /*! @name CH10_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH10_DEBUG1_STATEMACHINE_MASK (0x1FU) #define APBH_CH10_DEBUG1_STATEMACHINE_SHIFT (0U) /*! STATEMACHINE - STATEMACHINE * 0b00000..This is the idle state of the DMA state machine. * 0b00001..State in which the DMA is waiting to receive the first word of a command. * 0b00010..State in which the DMA is waiting to receive the third word of a command. * 0b00011..State in which the DMA is waiting to receive the second word of a command. * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. */ #define APBH_CH10_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH10_DEBUG1_STATEMACHINE_MASK) #define APBH_CH10_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) #define APBH_CH10_DEBUG1_WR_FIFO_FULL_SHIFT (20U) #define APBH_CH10_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH10_DEBUG1_WR_FIFO_FULL_MASK) #define APBH_CH10_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) #define APBH_CH10_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) #define APBH_CH10_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH10_DEBUG1_WR_FIFO_EMPTY_MASK) #define APBH_CH10_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) #define APBH_CH10_DEBUG1_RD_FIFO_FULL_SHIFT (22U) #define APBH_CH10_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH10_DEBUG1_RD_FIFO_FULL_MASK) #define APBH_CH10_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) #define APBH_CH10_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) #define APBH_CH10_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH10_DEBUG1_RD_FIFO_EMPTY_MASK) #define APBH_CH10_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) #define APBH_CH10_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) #define APBH_CH10_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH10_DEBUG1_NEXTCMDADDRVALID_MASK) #define APBH_CH10_DEBUG1_READY_MASK (0x4000000U) #define APBH_CH10_DEBUG1_READY_SHIFT (26U) #define APBH_CH10_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_READY_SHIFT)) & APBH_CH10_DEBUG1_READY_MASK) #define APBH_CH10_DEBUG1_END_MASK (0x10000000U) #define APBH_CH10_DEBUG1_END_SHIFT (28U) #define APBH_CH10_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_END_SHIFT)) & APBH_CH10_DEBUG1_END_MASK) #define APBH_CH10_DEBUG1_KICK_MASK (0x20000000U) #define APBH_CH10_DEBUG1_KICK_SHIFT (29U) #define APBH_CH10_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_KICK_SHIFT)) & APBH_CH10_DEBUG1_KICK_MASK) #define APBH_CH10_DEBUG1_BURST_MASK (0x40000000U) #define APBH_CH10_DEBUG1_BURST_SHIFT (30U) #define APBH_CH10_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_BURST_SHIFT)) & APBH_CH10_DEBUG1_BURST_MASK) #define APBH_CH10_DEBUG1_REQ_MASK (0x80000000U) #define APBH_CH10_DEBUG1_REQ_SHIFT (31U) #define APBH_CH10_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_REQ_SHIFT)) & APBH_CH10_DEBUG1_REQ_MASK) /*! @} */ /*! @name CH10_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH10_DEBUG2_AHB_BYTES_MASK (0xFFFFU) #define APBH_CH10_DEBUG2_AHB_BYTES_SHIFT (0U) #define APBH_CH10_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH10_DEBUG2_AHB_BYTES_MASK) #define APBH_CH10_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) #define APBH_CH10_DEBUG2_APB_BYTES_SHIFT (16U) #define APBH_CH10_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH10_DEBUG2_APB_BYTES_MASK) /*! @} */ /*! @name CH11_CURCMDAR - APBH DMA Channel n Current Command Address Register */ /*! @{ */ #define APBH_CH11_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH11_CURCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH11_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH11_CURCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH11_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ /*! @{ */ #define APBH_CH11_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH11_NXTCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH11_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH11_NXTCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH11_CMD - APBH DMA Channel n Command Register */ /*! @{ */ #define APBH_CH11_CMD_COMMAND_MASK (0x3U) #define APBH_CH11_CMD_COMMAND_SHIFT (0U) /*! COMMAND - COMMAND * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. */ #define APBH_CH11_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_COMMAND_SHIFT)) & APBH_CH11_CMD_COMMAND_MASK) #define APBH_CH11_CMD_CHAIN_MASK (0x4U) #define APBH_CH11_CMD_CHAIN_SHIFT (2U) #define APBH_CH11_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_CHAIN_SHIFT)) & APBH_CH11_CMD_CHAIN_MASK) #define APBH_CH11_CMD_IRQONCMPLT_MASK (0x8U) #define APBH_CH11_CMD_IRQONCMPLT_SHIFT (3U) #define APBH_CH11_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_IRQONCMPLT_SHIFT)) & APBH_CH11_CMD_IRQONCMPLT_MASK) #define APBH_CH11_CMD_NANDLOCK_MASK (0x10U) #define APBH_CH11_CMD_NANDLOCK_SHIFT (4U) #define APBH_CH11_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_NANDLOCK_SHIFT)) & APBH_CH11_CMD_NANDLOCK_MASK) #define APBH_CH11_CMD_NANDWAIT4READY_MASK (0x20U) #define APBH_CH11_CMD_NANDWAIT4READY_SHIFT (5U) #define APBH_CH11_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH11_CMD_NANDWAIT4READY_MASK) #define APBH_CH11_CMD_SEMAPHORE_MASK (0x40U) #define APBH_CH11_CMD_SEMAPHORE_SHIFT (6U) #define APBH_CH11_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_SEMAPHORE_SHIFT)) & APBH_CH11_CMD_SEMAPHORE_MASK) #define APBH_CH11_CMD_WAIT4ENDCMD_MASK (0x80U) #define APBH_CH11_CMD_WAIT4ENDCMD_SHIFT (7U) #define APBH_CH11_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH11_CMD_WAIT4ENDCMD_MASK) #define APBH_CH11_CMD_HALTONTERMINATE_MASK (0x100U) #define APBH_CH11_CMD_HALTONTERMINATE_SHIFT (8U) #define APBH_CH11_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH11_CMD_HALTONTERMINATE_MASK) #define APBH_CH11_CMD_CMDWORDS_MASK (0xF000U) #define APBH_CH11_CMD_CMDWORDS_SHIFT (12U) #define APBH_CH11_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_CMDWORDS_SHIFT)) & APBH_CH11_CMD_CMDWORDS_MASK) #define APBH_CH11_CMD_XFER_COUNT_MASK (0xFFFF0000U) #define APBH_CH11_CMD_XFER_COUNT_SHIFT (16U) #define APBH_CH11_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_XFER_COUNT_SHIFT)) & APBH_CH11_CMD_XFER_COUNT_MASK) /*! @} */ /*! @name CH11_BAR - APBH DMA Channel n Buffer Address Register */ /*! @{ */ #define APBH_CH11_BAR_ADDRESS_MASK (0xFFFFFFFFU) #define APBH_CH11_BAR_ADDRESS_SHIFT (0U) #define APBH_CH11_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_BAR_ADDRESS_SHIFT)) & APBH_CH11_BAR_ADDRESS_MASK) /*! @} */ /*! @name CH11_SEMA - APBH DMA Channel n Semaphore Register */ /*! @{ */ #define APBH_CH11_SEMA_INCREMENT_SEMA_MASK (0xFFU) #define APBH_CH11_SEMA_INCREMENT_SEMA_SHIFT (0U) #define APBH_CH11_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH11_SEMA_INCREMENT_SEMA_MASK) #define APBH_CH11_SEMA_PHORE_MASK (0xFF0000U) #define APBH_CH11_SEMA_PHORE_SHIFT (16U) #define APBH_CH11_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_SEMA_PHORE_SHIFT)) & APBH_CH11_SEMA_PHORE_MASK) /*! @} */ /*! @name CH11_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH11_DEBUG1_STATEMACHINE_MASK (0x1FU) #define APBH_CH11_DEBUG1_STATEMACHINE_SHIFT (0U) /*! STATEMACHINE - STATEMACHINE * 0b00000..This is the idle state of the DMA state machine. * 0b00001..State in which the DMA is waiting to receive the first word of a command. * 0b00010..State in which the DMA is waiting to receive the third word of a command. * 0b00011..State in which the DMA is waiting to receive the second word of a command. * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. */ #define APBH_CH11_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH11_DEBUG1_STATEMACHINE_MASK) #define APBH_CH11_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) #define APBH_CH11_DEBUG1_WR_FIFO_FULL_SHIFT (20U) #define APBH_CH11_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH11_DEBUG1_WR_FIFO_FULL_MASK) #define APBH_CH11_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) #define APBH_CH11_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) #define APBH_CH11_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH11_DEBUG1_WR_FIFO_EMPTY_MASK) #define APBH_CH11_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) #define APBH_CH11_DEBUG1_RD_FIFO_FULL_SHIFT (22U) #define APBH_CH11_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH11_DEBUG1_RD_FIFO_FULL_MASK) #define APBH_CH11_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) #define APBH_CH11_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) #define APBH_CH11_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH11_DEBUG1_RD_FIFO_EMPTY_MASK) #define APBH_CH11_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) #define APBH_CH11_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) #define APBH_CH11_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH11_DEBUG1_NEXTCMDADDRVALID_MASK) #define APBH_CH11_DEBUG1_READY_MASK (0x4000000U) #define APBH_CH11_DEBUG1_READY_SHIFT (26U) #define APBH_CH11_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_READY_SHIFT)) & APBH_CH11_DEBUG1_READY_MASK) #define APBH_CH11_DEBUG1_END_MASK (0x10000000U) #define APBH_CH11_DEBUG1_END_SHIFT (28U) #define APBH_CH11_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_END_SHIFT)) & APBH_CH11_DEBUG1_END_MASK) #define APBH_CH11_DEBUG1_KICK_MASK (0x20000000U) #define APBH_CH11_DEBUG1_KICK_SHIFT (29U) #define APBH_CH11_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_KICK_SHIFT)) & APBH_CH11_DEBUG1_KICK_MASK) #define APBH_CH11_DEBUG1_BURST_MASK (0x40000000U) #define APBH_CH11_DEBUG1_BURST_SHIFT (30U) #define APBH_CH11_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_BURST_SHIFT)) & APBH_CH11_DEBUG1_BURST_MASK) #define APBH_CH11_DEBUG1_REQ_MASK (0x80000000U) #define APBH_CH11_DEBUG1_REQ_SHIFT (31U) #define APBH_CH11_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_REQ_SHIFT)) & APBH_CH11_DEBUG1_REQ_MASK) /*! @} */ /*! @name CH11_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH11_DEBUG2_AHB_BYTES_MASK (0xFFFFU) #define APBH_CH11_DEBUG2_AHB_BYTES_SHIFT (0U) #define APBH_CH11_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH11_DEBUG2_AHB_BYTES_MASK) #define APBH_CH11_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) #define APBH_CH11_DEBUG2_APB_BYTES_SHIFT (16U) #define APBH_CH11_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH11_DEBUG2_APB_BYTES_MASK) /*! @} */ /*! @name CH12_CURCMDAR - APBH DMA Channel n Current Command Address Register */ /*! @{ */ #define APBH_CH12_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH12_CURCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH12_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH12_CURCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH12_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ /*! @{ */ #define APBH_CH12_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH12_NXTCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH12_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH12_NXTCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH12_CMD - APBH DMA Channel n Command Register */ /*! @{ */ #define APBH_CH12_CMD_COMMAND_MASK (0x3U) #define APBH_CH12_CMD_COMMAND_SHIFT (0U) /*! COMMAND - COMMAND * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. */ #define APBH_CH12_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_COMMAND_SHIFT)) & APBH_CH12_CMD_COMMAND_MASK) #define APBH_CH12_CMD_CHAIN_MASK (0x4U) #define APBH_CH12_CMD_CHAIN_SHIFT (2U) #define APBH_CH12_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_CHAIN_SHIFT)) & APBH_CH12_CMD_CHAIN_MASK) #define APBH_CH12_CMD_IRQONCMPLT_MASK (0x8U) #define APBH_CH12_CMD_IRQONCMPLT_SHIFT (3U) #define APBH_CH12_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_IRQONCMPLT_SHIFT)) & APBH_CH12_CMD_IRQONCMPLT_MASK) #define APBH_CH12_CMD_NANDLOCK_MASK (0x10U) #define APBH_CH12_CMD_NANDLOCK_SHIFT (4U) #define APBH_CH12_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_NANDLOCK_SHIFT)) & APBH_CH12_CMD_NANDLOCK_MASK) #define APBH_CH12_CMD_NANDWAIT4READY_MASK (0x20U) #define APBH_CH12_CMD_NANDWAIT4READY_SHIFT (5U) #define APBH_CH12_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH12_CMD_NANDWAIT4READY_MASK) #define APBH_CH12_CMD_SEMAPHORE_MASK (0x40U) #define APBH_CH12_CMD_SEMAPHORE_SHIFT (6U) #define APBH_CH12_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_SEMAPHORE_SHIFT)) & APBH_CH12_CMD_SEMAPHORE_MASK) #define APBH_CH12_CMD_WAIT4ENDCMD_MASK (0x80U) #define APBH_CH12_CMD_WAIT4ENDCMD_SHIFT (7U) #define APBH_CH12_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH12_CMD_WAIT4ENDCMD_MASK) #define APBH_CH12_CMD_HALTONTERMINATE_MASK (0x100U) #define APBH_CH12_CMD_HALTONTERMINATE_SHIFT (8U) #define APBH_CH12_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH12_CMD_HALTONTERMINATE_MASK) #define APBH_CH12_CMD_CMDWORDS_MASK (0xF000U) #define APBH_CH12_CMD_CMDWORDS_SHIFT (12U) #define APBH_CH12_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_CMDWORDS_SHIFT)) & APBH_CH12_CMD_CMDWORDS_MASK) #define APBH_CH12_CMD_XFER_COUNT_MASK (0xFFFF0000U) #define APBH_CH12_CMD_XFER_COUNT_SHIFT (16U) #define APBH_CH12_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_XFER_COUNT_SHIFT)) & APBH_CH12_CMD_XFER_COUNT_MASK) /*! @} */ /*! @name CH12_BAR - APBH DMA Channel n Buffer Address Register */ /*! @{ */ #define APBH_CH12_BAR_ADDRESS_MASK (0xFFFFFFFFU) #define APBH_CH12_BAR_ADDRESS_SHIFT (0U) #define APBH_CH12_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_BAR_ADDRESS_SHIFT)) & APBH_CH12_BAR_ADDRESS_MASK) /*! @} */ /*! @name CH12_SEMA - APBH DMA Channel n Semaphore Register */ /*! @{ */ #define APBH_CH12_SEMA_INCREMENT_SEMA_MASK (0xFFU) #define APBH_CH12_SEMA_INCREMENT_SEMA_SHIFT (0U) #define APBH_CH12_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH12_SEMA_INCREMENT_SEMA_MASK) #define APBH_CH12_SEMA_PHORE_MASK (0xFF0000U) #define APBH_CH12_SEMA_PHORE_SHIFT (16U) #define APBH_CH12_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_SEMA_PHORE_SHIFT)) & APBH_CH12_SEMA_PHORE_MASK) /*! @} */ /*! @name CH12_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH12_DEBUG1_STATEMACHINE_MASK (0x1FU) #define APBH_CH12_DEBUG1_STATEMACHINE_SHIFT (0U) /*! STATEMACHINE - STATEMACHINE * 0b00000..This is the idle state of the DMA state machine. * 0b00001..State in which the DMA is waiting to receive the first word of a command. * 0b00010..State in which the DMA is waiting to receive the third word of a command. * 0b00011..State in which the DMA is waiting to receive the second word of a command. * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. */ #define APBH_CH12_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH12_DEBUG1_STATEMACHINE_MASK) #define APBH_CH12_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) #define APBH_CH12_DEBUG1_WR_FIFO_FULL_SHIFT (20U) #define APBH_CH12_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH12_DEBUG1_WR_FIFO_FULL_MASK) #define APBH_CH12_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) #define APBH_CH12_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) #define APBH_CH12_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH12_DEBUG1_WR_FIFO_EMPTY_MASK) #define APBH_CH12_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) #define APBH_CH12_DEBUG1_RD_FIFO_FULL_SHIFT (22U) #define APBH_CH12_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH12_DEBUG1_RD_FIFO_FULL_MASK) #define APBH_CH12_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) #define APBH_CH12_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) #define APBH_CH12_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH12_DEBUG1_RD_FIFO_EMPTY_MASK) #define APBH_CH12_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) #define APBH_CH12_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) #define APBH_CH12_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH12_DEBUG1_NEXTCMDADDRVALID_MASK) #define APBH_CH12_DEBUG1_READY_MASK (0x4000000U) #define APBH_CH12_DEBUG1_READY_SHIFT (26U) #define APBH_CH12_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_READY_SHIFT)) & APBH_CH12_DEBUG1_READY_MASK) #define APBH_CH12_DEBUG1_END_MASK (0x10000000U) #define APBH_CH12_DEBUG1_END_SHIFT (28U) #define APBH_CH12_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_END_SHIFT)) & APBH_CH12_DEBUG1_END_MASK) #define APBH_CH12_DEBUG1_KICK_MASK (0x20000000U) #define APBH_CH12_DEBUG1_KICK_SHIFT (29U) #define APBH_CH12_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_KICK_SHIFT)) & APBH_CH12_DEBUG1_KICK_MASK) #define APBH_CH12_DEBUG1_BURST_MASK (0x40000000U) #define APBH_CH12_DEBUG1_BURST_SHIFT (30U) #define APBH_CH12_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_BURST_SHIFT)) & APBH_CH12_DEBUG1_BURST_MASK) #define APBH_CH12_DEBUG1_REQ_MASK (0x80000000U) #define APBH_CH12_DEBUG1_REQ_SHIFT (31U) #define APBH_CH12_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_REQ_SHIFT)) & APBH_CH12_DEBUG1_REQ_MASK) /*! @} */ /*! @name CH12_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH12_DEBUG2_AHB_BYTES_MASK (0xFFFFU) #define APBH_CH12_DEBUG2_AHB_BYTES_SHIFT (0U) #define APBH_CH12_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH12_DEBUG2_AHB_BYTES_MASK) #define APBH_CH12_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) #define APBH_CH12_DEBUG2_APB_BYTES_SHIFT (16U) #define APBH_CH12_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH12_DEBUG2_APB_BYTES_MASK) /*! @} */ /*! @name CH13_CURCMDAR - APBH DMA Channel n Current Command Address Register */ /*! @{ */ #define APBH_CH13_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH13_CURCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH13_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH13_CURCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH13_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ /*! @{ */ #define APBH_CH13_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH13_NXTCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH13_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH13_NXTCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH13_CMD - APBH DMA Channel n Command Register */ /*! @{ */ #define APBH_CH13_CMD_COMMAND_MASK (0x3U) #define APBH_CH13_CMD_COMMAND_SHIFT (0U) /*! COMMAND - COMMAND * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. */ #define APBH_CH13_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_COMMAND_SHIFT)) & APBH_CH13_CMD_COMMAND_MASK) #define APBH_CH13_CMD_CHAIN_MASK (0x4U) #define APBH_CH13_CMD_CHAIN_SHIFT (2U) #define APBH_CH13_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_CHAIN_SHIFT)) & APBH_CH13_CMD_CHAIN_MASK) #define APBH_CH13_CMD_IRQONCMPLT_MASK (0x8U) #define APBH_CH13_CMD_IRQONCMPLT_SHIFT (3U) #define APBH_CH13_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_IRQONCMPLT_SHIFT)) & APBH_CH13_CMD_IRQONCMPLT_MASK) #define APBH_CH13_CMD_NANDLOCK_MASK (0x10U) #define APBH_CH13_CMD_NANDLOCK_SHIFT (4U) #define APBH_CH13_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_NANDLOCK_SHIFT)) & APBH_CH13_CMD_NANDLOCK_MASK) #define APBH_CH13_CMD_NANDWAIT4READY_MASK (0x20U) #define APBH_CH13_CMD_NANDWAIT4READY_SHIFT (5U) #define APBH_CH13_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH13_CMD_NANDWAIT4READY_MASK) #define APBH_CH13_CMD_SEMAPHORE_MASK (0x40U) #define APBH_CH13_CMD_SEMAPHORE_SHIFT (6U) #define APBH_CH13_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_SEMAPHORE_SHIFT)) & APBH_CH13_CMD_SEMAPHORE_MASK) #define APBH_CH13_CMD_WAIT4ENDCMD_MASK (0x80U) #define APBH_CH13_CMD_WAIT4ENDCMD_SHIFT (7U) #define APBH_CH13_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH13_CMD_WAIT4ENDCMD_MASK) #define APBH_CH13_CMD_HALTONTERMINATE_MASK (0x100U) #define APBH_CH13_CMD_HALTONTERMINATE_SHIFT (8U) #define APBH_CH13_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH13_CMD_HALTONTERMINATE_MASK) #define APBH_CH13_CMD_CMDWORDS_MASK (0xF000U) #define APBH_CH13_CMD_CMDWORDS_SHIFT (12U) #define APBH_CH13_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_CMDWORDS_SHIFT)) & APBH_CH13_CMD_CMDWORDS_MASK) #define APBH_CH13_CMD_XFER_COUNT_MASK (0xFFFF0000U) #define APBH_CH13_CMD_XFER_COUNT_SHIFT (16U) #define APBH_CH13_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_XFER_COUNT_SHIFT)) & APBH_CH13_CMD_XFER_COUNT_MASK) /*! @} */ /*! @name CH13_BAR - APBH DMA Channel n Buffer Address Register */ /*! @{ */ #define APBH_CH13_BAR_ADDRESS_MASK (0xFFFFFFFFU) #define APBH_CH13_BAR_ADDRESS_SHIFT (0U) #define APBH_CH13_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_BAR_ADDRESS_SHIFT)) & APBH_CH13_BAR_ADDRESS_MASK) /*! @} */ /*! @name CH13_SEMA - APBH DMA Channel n Semaphore Register */ /*! @{ */ #define APBH_CH13_SEMA_INCREMENT_SEMA_MASK (0xFFU) #define APBH_CH13_SEMA_INCREMENT_SEMA_SHIFT (0U) #define APBH_CH13_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH13_SEMA_INCREMENT_SEMA_MASK) #define APBH_CH13_SEMA_PHORE_MASK (0xFF0000U) #define APBH_CH13_SEMA_PHORE_SHIFT (16U) #define APBH_CH13_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_SEMA_PHORE_SHIFT)) & APBH_CH13_SEMA_PHORE_MASK) /*! @} */ /*! @name CH13_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH13_DEBUG1_STATEMACHINE_MASK (0x1FU) #define APBH_CH13_DEBUG1_STATEMACHINE_SHIFT (0U) /*! STATEMACHINE - STATEMACHINE * 0b00000..This is the idle state of the DMA state machine. * 0b00001..State in which the DMA is waiting to receive the first word of a command. * 0b00010..State in which the DMA is waiting to receive the third word of a command. * 0b00011..State in which the DMA is waiting to receive the second word of a command. * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. */ #define APBH_CH13_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH13_DEBUG1_STATEMACHINE_MASK) #define APBH_CH13_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) #define APBH_CH13_DEBUG1_WR_FIFO_FULL_SHIFT (20U) #define APBH_CH13_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH13_DEBUG1_WR_FIFO_FULL_MASK) #define APBH_CH13_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) #define APBH_CH13_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) #define APBH_CH13_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH13_DEBUG1_WR_FIFO_EMPTY_MASK) #define APBH_CH13_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) #define APBH_CH13_DEBUG1_RD_FIFO_FULL_SHIFT (22U) #define APBH_CH13_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH13_DEBUG1_RD_FIFO_FULL_MASK) #define APBH_CH13_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) #define APBH_CH13_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) #define APBH_CH13_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH13_DEBUG1_RD_FIFO_EMPTY_MASK) #define APBH_CH13_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) #define APBH_CH13_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) #define APBH_CH13_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH13_DEBUG1_NEXTCMDADDRVALID_MASK) #define APBH_CH13_DEBUG1_READY_MASK (0x4000000U) #define APBH_CH13_DEBUG1_READY_SHIFT (26U) #define APBH_CH13_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_READY_SHIFT)) & APBH_CH13_DEBUG1_READY_MASK) #define APBH_CH13_DEBUG1_END_MASK (0x10000000U) #define APBH_CH13_DEBUG1_END_SHIFT (28U) #define APBH_CH13_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_END_SHIFT)) & APBH_CH13_DEBUG1_END_MASK) #define APBH_CH13_DEBUG1_KICK_MASK (0x20000000U) #define APBH_CH13_DEBUG1_KICK_SHIFT (29U) #define APBH_CH13_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_KICK_SHIFT)) & APBH_CH13_DEBUG1_KICK_MASK) #define APBH_CH13_DEBUG1_BURST_MASK (0x40000000U) #define APBH_CH13_DEBUG1_BURST_SHIFT (30U) #define APBH_CH13_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_BURST_SHIFT)) & APBH_CH13_DEBUG1_BURST_MASK) #define APBH_CH13_DEBUG1_REQ_MASK (0x80000000U) #define APBH_CH13_DEBUG1_REQ_SHIFT (31U) #define APBH_CH13_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_REQ_SHIFT)) & APBH_CH13_DEBUG1_REQ_MASK) /*! @} */ /*! @name CH13_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH13_DEBUG2_AHB_BYTES_MASK (0xFFFFU) #define APBH_CH13_DEBUG2_AHB_BYTES_SHIFT (0U) #define APBH_CH13_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH13_DEBUG2_AHB_BYTES_MASK) #define APBH_CH13_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) #define APBH_CH13_DEBUG2_APB_BYTES_SHIFT (16U) #define APBH_CH13_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH13_DEBUG2_APB_BYTES_MASK) /*! @} */ /*! @name CH14_CURCMDAR - APBH DMA Channel n Current Command Address Register */ /*! @{ */ #define APBH_CH14_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH14_CURCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH14_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH14_CURCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH14_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ /*! @{ */ #define APBH_CH14_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH14_NXTCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH14_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH14_NXTCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH14_CMD - APBH DMA Channel n Command Register */ /*! @{ */ #define APBH_CH14_CMD_COMMAND_MASK (0x3U) #define APBH_CH14_CMD_COMMAND_SHIFT (0U) /*! COMMAND - COMMAND * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. */ #define APBH_CH14_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_COMMAND_SHIFT)) & APBH_CH14_CMD_COMMAND_MASK) #define APBH_CH14_CMD_CHAIN_MASK (0x4U) #define APBH_CH14_CMD_CHAIN_SHIFT (2U) #define APBH_CH14_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_CHAIN_SHIFT)) & APBH_CH14_CMD_CHAIN_MASK) #define APBH_CH14_CMD_IRQONCMPLT_MASK (0x8U) #define APBH_CH14_CMD_IRQONCMPLT_SHIFT (3U) #define APBH_CH14_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_IRQONCMPLT_SHIFT)) & APBH_CH14_CMD_IRQONCMPLT_MASK) #define APBH_CH14_CMD_NANDLOCK_MASK (0x10U) #define APBH_CH14_CMD_NANDLOCK_SHIFT (4U) #define APBH_CH14_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_NANDLOCK_SHIFT)) & APBH_CH14_CMD_NANDLOCK_MASK) #define APBH_CH14_CMD_NANDWAIT4READY_MASK (0x20U) #define APBH_CH14_CMD_NANDWAIT4READY_SHIFT (5U) #define APBH_CH14_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH14_CMD_NANDWAIT4READY_MASK) #define APBH_CH14_CMD_SEMAPHORE_MASK (0x40U) #define APBH_CH14_CMD_SEMAPHORE_SHIFT (6U) #define APBH_CH14_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_SEMAPHORE_SHIFT)) & APBH_CH14_CMD_SEMAPHORE_MASK) #define APBH_CH14_CMD_WAIT4ENDCMD_MASK (0x80U) #define APBH_CH14_CMD_WAIT4ENDCMD_SHIFT (7U) #define APBH_CH14_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH14_CMD_WAIT4ENDCMD_MASK) #define APBH_CH14_CMD_HALTONTERMINATE_MASK (0x100U) #define APBH_CH14_CMD_HALTONTERMINATE_SHIFT (8U) #define APBH_CH14_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH14_CMD_HALTONTERMINATE_MASK) #define APBH_CH14_CMD_CMDWORDS_MASK (0xF000U) #define APBH_CH14_CMD_CMDWORDS_SHIFT (12U) #define APBH_CH14_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_CMDWORDS_SHIFT)) & APBH_CH14_CMD_CMDWORDS_MASK) #define APBH_CH14_CMD_XFER_COUNT_MASK (0xFFFF0000U) #define APBH_CH14_CMD_XFER_COUNT_SHIFT (16U) #define APBH_CH14_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_XFER_COUNT_SHIFT)) & APBH_CH14_CMD_XFER_COUNT_MASK) /*! @} */ /*! @name CH14_BAR - APBH DMA Channel n Buffer Address Register */ /*! @{ */ #define APBH_CH14_BAR_ADDRESS_MASK (0xFFFFFFFFU) #define APBH_CH14_BAR_ADDRESS_SHIFT (0U) #define APBH_CH14_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_BAR_ADDRESS_SHIFT)) & APBH_CH14_BAR_ADDRESS_MASK) /*! @} */ /*! @name CH14_SEMA - APBH DMA Channel n Semaphore Register */ /*! @{ */ #define APBH_CH14_SEMA_INCREMENT_SEMA_MASK (0xFFU) #define APBH_CH14_SEMA_INCREMENT_SEMA_SHIFT (0U) #define APBH_CH14_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH14_SEMA_INCREMENT_SEMA_MASK) #define APBH_CH14_SEMA_PHORE_MASK (0xFF0000U) #define APBH_CH14_SEMA_PHORE_SHIFT (16U) #define APBH_CH14_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_SEMA_PHORE_SHIFT)) & APBH_CH14_SEMA_PHORE_MASK) /*! @} */ /*! @name CH14_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH14_DEBUG1_STATEMACHINE_MASK (0x1FU) #define APBH_CH14_DEBUG1_STATEMACHINE_SHIFT (0U) /*! STATEMACHINE - STATEMACHINE * 0b00000..This is the idle state of the DMA state machine. * 0b00001..State in which the DMA is waiting to receive the first word of a command. * 0b00010..State in which the DMA is waiting to receive the third word of a command. * 0b00011..State in which the DMA is waiting to receive the second word of a command. * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. */ #define APBH_CH14_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH14_DEBUG1_STATEMACHINE_MASK) #define APBH_CH14_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) #define APBH_CH14_DEBUG1_WR_FIFO_FULL_SHIFT (20U) #define APBH_CH14_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH14_DEBUG1_WR_FIFO_FULL_MASK) #define APBH_CH14_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) #define APBH_CH14_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) #define APBH_CH14_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH14_DEBUG1_WR_FIFO_EMPTY_MASK) #define APBH_CH14_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) #define APBH_CH14_DEBUG1_RD_FIFO_FULL_SHIFT (22U) #define APBH_CH14_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH14_DEBUG1_RD_FIFO_FULL_MASK) #define APBH_CH14_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) #define APBH_CH14_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) #define APBH_CH14_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH14_DEBUG1_RD_FIFO_EMPTY_MASK) #define APBH_CH14_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) #define APBH_CH14_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) #define APBH_CH14_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH14_DEBUG1_NEXTCMDADDRVALID_MASK) #define APBH_CH14_DEBUG1_READY_MASK (0x4000000U) #define APBH_CH14_DEBUG1_READY_SHIFT (26U) #define APBH_CH14_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_READY_SHIFT)) & APBH_CH14_DEBUG1_READY_MASK) #define APBH_CH14_DEBUG1_END_MASK (0x10000000U) #define APBH_CH14_DEBUG1_END_SHIFT (28U) #define APBH_CH14_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_END_SHIFT)) & APBH_CH14_DEBUG1_END_MASK) #define APBH_CH14_DEBUG1_KICK_MASK (0x20000000U) #define APBH_CH14_DEBUG1_KICK_SHIFT (29U) #define APBH_CH14_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_KICK_SHIFT)) & APBH_CH14_DEBUG1_KICK_MASK) #define APBH_CH14_DEBUG1_BURST_MASK (0x40000000U) #define APBH_CH14_DEBUG1_BURST_SHIFT (30U) #define APBH_CH14_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_BURST_SHIFT)) & APBH_CH14_DEBUG1_BURST_MASK) #define APBH_CH14_DEBUG1_REQ_MASK (0x80000000U) #define APBH_CH14_DEBUG1_REQ_SHIFT (31U) #define APBH_CH14_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_REQ_SHIFT)) & APBH_CH14_DEBUG1_REQ_MASK) /*! @} */ /*! @name CH14_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH14_DEBUG2_AHB_BYTES_MASK (0xFFFFU) #define APBH_CH14_DEBUG2_AHB_BYTES_SHIFT (0U) #define APBH_CH14_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH14_DEBUG2_AHB_BYTES_MASK) #define APBH_CH14_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) #define APBH_CH14_DEBUG2_APB_BYTES_SHIFT (16U) #define APBH_CH14_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH14_DEBUG2_APB_BYTES_MASK) /*! @} */ /*! @name CH15_CURCMDAR - APBH DMA Channel n Current Command Address Register */ /*! @{ */ #define APBH_CH15_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH15_CURCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH15_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH15_CURCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH15_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ /*! @{ */ #define APBH_CH15_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH15_NXTCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH15_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH15_NXTCMDAR_CMD_ADDR_MASK) /*! @} */ /*! @name CH15_CMD - APBH DMA Channel n Command Register */ /*! @{ */ #define APBH_CH15_CMD_COMMAND_MASK (0x3U) #define APBH_CH15_CMD_COMMAND_SHIFT (0U) /*! COMMAND - COMMAND * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. */ #define APBH_CH15_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_COMMAND_SHIFT)) & APBH_CH15_CMD_COMMAND_MASK) #define APBH_CH15_CMD_CHAIN_MASK (0x4U) #define APBH_CH15_CMD_CHAIN_SHIFT (2U) #define APBH_CH15_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_CHAIN_SHIFT)) & APBH_CH15_CMD_CHAIN_MASK) #define APBH_CH15_CMD_IRQONCMPLT_MASK (0x8U) #define APBH_CH15_CMD_IRQONCMPLT_SHIFT (3U) #define APBH_CH15_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_IRQONCMPLT_SHIFT)) & APBH_CH15_CMD_IRQONCMPLT_MASK) #define APBH_CH15_CMD_NANDLOCK_MASK (0x10U) #define APBH_CH15_CMD_NANDLOCK_SHIFT (4U) #define APBH_CH15_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_NANDLOCK_SHIFT)) & APBH_CH15_CMD_NANDLOCK_MASK) #define APBH_CH15_CMD_NANDWAIT4READY_MASK (0x20U) #define APBH_CH15_CMD_NANDWAIT4READY_SHIFT (5U) #define APBH_CH15_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH15_CMD_NANDWAIT4READY_MASK) #define APBH_CH15_CMD_SEMAPHORE_MASK (0x40U) #define APBH_CH15_CMD_SEMAPHORE_SHIFT (6U) #define APBH_CH15_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_SEMAPHORE_SHIFT)) & APBH_CH15_CMD_SEMAPHORE_MASK) #define APBH_CH15_CMD_WAIT4ENDCMD_MASK (0x80U) #define APBH_CH15_CMD_WAIT4ENDCMD_SHIFT (7U) #define APBH_CH15_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH15_CMD_WAIT4ENDCMD_MASK) #define APBH_CH15_CMD_HALTONTERMINATE_MASK (0x100U) #define APBH_CH15_CMD_HALTONTERMINATE_SHIFT (8U) #define APBH_CH15_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH15_CMD_HALTONTERMINATE_MASK) #define APBH_CH15_CMD_CMDWORDS_MASK (0xF000U) #define APBH_CH15_CMD_CMDWORDS_SHIFT (12U) #define APBH_CH15_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_CMDWORDS_SHIFT)) & APBH_CH15_CMD_CMDWORDS_MASK) #define APBH_CH15_CMD_XFER_COUNT_MASK (0xFFFF0000U) #define APBH_CH15_CMD_XFER_COUNT_SHIFT (16U) #define APBH_CH15_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_XFER_COUNT_SHIFT)) & APBH_CH15_CMD_XFER_COUNT_MASK) /*! @} */ /*! @name CH15_BAR - APBH DMA Channel n Buffer Address Register */ /*! @{ */ #define APBH_CH15_BAR_ADDRESS_MASK (0xFFFFFFFFU) #define APBH_CH15_BAR_ADDRESS_SHIFT (0U) #define APBH_CH15_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_BAR_ADDRESS_SHIFT)) & APBH_CH15_BAR_ADDRESS_MASK) /*! @} */ /*! @name CH15_SEMA - APBH DMA Channel n Semaphore Register */ /*! @{ */ #define APBH_CH15_SEMA_INCREMENT_SEMA_MASK (0xFFU) #define APBH_CH15_SEMA_INCREMENT_SEMA_SHIFT (0U) #define APBH_CH15_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH15_SEMA_INCREMENT_SEMA_MASK) #define APBH_CH15_SEMA_PHORE_MASK (0xFF0000U) #define APBH_CH15_SEMA_PHORE_SHIFT (16U) #define APBH_CH15_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_SEMA_PHORE_SHIFT)) & APBH_CH15_SEMA_PHORE_MASK) /*! @} */ /*! @name CH15_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH15_DEBUG1_STATEMACHINE_MASK (0x1FU) #define APBH_CH15_DEBUG1_STATEMACHINE_SHIFT (0U) /*! STATEMACHINE - STATEMACHINE * 0b00000..This is the idle state of the DMA state machine. * 0b00001..State in which the DMA is waiting to receive the first word of a command. * 0b00010..State in which the DMA is waiting to receive the third word of a command. * 0b00011..State in which the DMA is waiting to receive the second word of a command. * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. */ #define APBH_CH15_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH15_DEBUG1_STATEMACHINE_MASK) #define APBH_CH15_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) #define APBH_CH15_DEBUG1_WR_FIFO_FULL_SHIFT (20U) #define APBH_CH15_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH15_DEBUG1_WR_FIFO_FULL_MASK) #define APBH_CH15_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) #define APBH_CH15_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) #define APBH_CH15_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH15_DEBUG1_WR_FIFO_EMPTY_MASK) #define APBH_CH15_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) #define APBH_CH15_DEBUG1_RD_FIFO_FULL_SHIFT (22U) #define APBH_CH15_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH15_DEBUG1_RD_FIFO_FULL_MASK) #define APBH_CH15_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) #define APBH_CH15_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) #define APBH_CH15_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH15_DEBUG1_RD_FIFO_EMPTY_MASK) #define APBH_CH15_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) #define APBH_CH15_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) #define APBH_CH15_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH15_DEBUG1_NEXTCMDADDRVALID_MASK) #define APBH_CH15_DEBUG1_READY_MASK (0x4000000U) #define APBH_CH15_DEBUG1_READY_SHIFT (26U) #define APBH_CH15_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_READY_SHIFT)) & APBH_CH15_DEBUG1_READY_MASK) #define APBH_CH15_DEBUG1_END_MASK (0x10000000U) #define APBH_CH15_DEBUG1_END_SHIFT (28U) #define APBH_CH15_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_END_SHIFT)) & APBH_CH15_DEBUG1_END_MASK) #define APBH_CH15_DEBUG1_KICK_MASK (0x20000000U) #define APBH_CH15_DEBUG1_KICK_SHIFT (29U) #define APBH_CH15_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_KICK_SHIFT)) & APBH_CH15_DEBUG1_KICK_MASK) #define APBH_CH15_DEBUG1_BURST_MASK (0x40000000U) #define APBH_CH15_DEBUG1_BURST_SHIFT (30U) #define APBH_CH15_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_BURST_SHIFT)) & APBH_CH15_DEBUG1_BURST_MASK) #define APBH_CH15_DEBUG1_REQ_MASK (0x80000000U) #define APBH_CH15_DEBUG1_REQ_SHIFT (31U) #define APBH_CH15_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_REQ_SHIFT)) & APBH_CH15_DEBUG1_REQ_MASK) /*! @} */ /*! @name CH15_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH15_DEBUG2_AHB_BYTES_MASK (0xFFFFU) #define APBH_CH15_DEBUG2_AHB_BYTES_SHIFT (0U) #define APBH_CH15_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH15_DEBUG2_AHB_BYTES_MASK) #define APBH_CH15_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) #define APBH_CH15_DEBUG2_APB_BYTES_SHIFT (16U) #define APBH_CH15_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH15_DEBUG2_APB_BYTES_MASK) /*! @} */ /*! @name VERSION - APBH Bridge Version Register */ /*! @{ */ #define APBH_VERSION_STEP_MASK (0xFFFFU) #define APBH_VERSION_STEP_SHIFT (0U) #define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK) #define APBH_VERSION_MINOR_MASK (0xFF0000U) #define APBH_VERSION_MINOR_SHIFT (16U) #define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK) #define APBH_VERSION_MAJOR_MASK (0xFF000000U) #define APBH_VERSION_MAJOR_SHIFT (24U) #define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK) /*! @} */ /*! * @} */ /* end of group APBH_Register_Masks */ /* APBH - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__APBH base address */ #define CONNECTIVITY__APBH_BASE (0x5B810000u) /** Peripheral CONNECTIVITY__APBH base pointer */ #define CONNECTIVITY__APBH ((APBH_Type *)CONNECTIVITY__APBH_BASE) /** Array initializer of APBH peripheral base addresses */ #define APBH_BASE_ADDRS { CONNECTIVITY__APBH_BASE } /** Array initializer of APBH peripheral base pointers */ #define APBH_BASE_PTRS { CONNECTIVITY__APBH } /** Interrupt vectors for the APBH peripheral type */ #define APBH_IRQS { CONNECTIVITY_APBHDMA_IRQn } /*! * @} */ /* end of group APBH_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ASMC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ASMC_Peripheral_Access_Layer ASMC Peripheral Access Layer * @{ */ /** ASMC - Register Layout Typedef */ typedef struct { __I uint32_t SRS; /**< System Reset Status Register, offset: 0x0 */ uint8_t RESERVED_0[4]; __IO uint32_t PMPROT; /**< Power Mode Protection register, offset: 0x8 */ __IO uint32_t PMCTRL; /**< Power Mode Control register, offset: 0xC */ __IO uint32_t STOPCTRL; /**< Stop Control Register, offset: 0x10 */ __I uint32_t PMSTAT; /**< Power Mode Status register, offset: 0x14 */ } ASMC_Type; /* ---------------------------------------------------------------------------- -- ASMC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ASMC_Register_Masks ASMC Register Masks * @{ */ /*! @name SRS - System Reset Status Register */ #define ASMC_SRS_WAKEUP_MASK (0x1U) #define ASMC_SRS_WAKEUP_SHIFT (0U) #define ASMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WAKEUP_SHIFT)) & ASMC_SRS_WAKEUP_MASK) #define ASMC_SRS_WDOG1_MASK (0x20U) #define ASMC_SRS_WDOG1_SHIFT (5U) #define ASMC_SRS_WDOG1(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WDOG1_SHIFT)) & ASMC_SRS_WDOG1_MASK) #define ASMC_SRS_RES_MASK (0x40U) #define ASMC_SRS_RES_SHIFT (6U) #define ASMC_SRS_RES(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_RES_SHIFT)) & ASMC_SRS_RES_MASK) #define ASMC_SRS_POR_MASK (0x80U) #define ASMC_SRS_POR_SHIFT (7U) #define ASMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_POR_SHIFT)) & ASMC_SRS_POR_MASK) #define ASMC_SRS_LOCKUP_MASK (0x200U) #define ASMC_SRS_LOCKUP_SHIFT (9U) #define ASMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_LOCKUP_SHIFT)) & ASMC_SRS_LOCKUP_MASK) #define ASMC_SRS_SW_MASK (0x400U) #define ASMC_SRS_SW_SHIFT (10U) #define ASMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SW_SHIFT)) & ASMC_SRS_SW_MASK) #define ASMC_SRS_SACKERR_MASK (0x1000U) #define ASMC_SRS_SACKERR_SHIFT (12U) #define ASMC_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SACKERR_SHIFT)) & ASMC_SRS_SACKERR_MASK) /*! @name PMPROT - Power Mode Protection register */ #define ASMC_PMPROT_AVLLS_MASK (0x2U) #define ASMC_PMPROT_AVLLS_SHIFT (1U) #define ASMC_PMPROT_AVLLS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLLS_SHIFT)) & ASMC_PMPROT_AVLLS_MASK) #define ASMC_PMPROT_ALLS_MASK (0x8U) #define ASMC_PMPROT_ALLS_SHIFT (3U) #define ASMC_PMPROT_ALLS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_ALLS_SHIFT)) & ASMC_PMPROT_ALLS_MASK) #define ASMC_PMPROT_AVLP_MASK (0x20U) #define ASMC_PMPROT_AVLP_SHIFT (5U) #define ASMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLP_SHIFT)) & ASMC_PMPROT_AVLP_MASK) /*! @name PMCTRL - Power Mode Control register */ #define ASMC_PMCTRL_STOPM_MASK (0x7U) #define ASMC_PMCTRL_STOPM_SHIFT (0U) #define ASMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_STOPM_SHIFT)) & ASMC_PMCTRL_STOPM_MASK) #define ASMC_PMCTRL_RUNM_MASK (0x60U) #define ASMC_PMCTRL_RUNM_SHIFT (5U) #define ASMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_RUNM_SHIFT)) & ASMC_PMCTRL_RUNM_MASK) /*! @name STOPCTRL - Stop Control Register */ #define ASMC_STOPCTRL_PSTOPO_MASK (0xC0U) #define ASMC_STOPCTRL_PSTOPO_SHIFT (6U) #define ASMC_STOPCTRL_PSTOPO(x) (((uint32_t)(((uint32_t)(x)) << ASMC_STOPCTRL_PSTOPO_SHIFT)) & ASMC_STOPCTRL_PSTOPO_MASK) /*! @name PMSTAT - Power Mode Status register */ #define ASMC_PMSTAT_PMSTAT_MASK (0xFFU) #define ASMC_PMSTAT_PMSTAT_SHIFT (0U) #define ASMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMSTAT_PMSTAT_SHIFT)) & ASMC_PMSTAT_PMSTAT_MASK) /*! * @} */ /* end of group ASMC_Register_Masks */ /* ASMC - Peripheral instance base addresses */ /** Peripheral ASMC base address */ #define BBS_SIM_BASE (0x41410000) /** Peripheral BBS_SIM base pointer */ #define BBS_SIM ((ASMC_Type *)BBS_SIM_BASE) /** Array initializer of BBS_SIM peripheral base addresses */ #define BBS_SIM_BASE_ADDRS {BBS_SIM_BASE} /** Array initializer of BBS_SIM peripheral base pointers */ #define BBS_SIM_BASE_PTRS {BBS_SIM} /*! * @} */ /* end of group ASMC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ASRC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer * @{ */ /** ASRC - Register Layout Typedef */ typedef struct { __IO uint32_t ASRCTR; /**< ASRC Control Register, offset: 0x0 */ __IO uint32_t ASRIER; /**< ASRC Interrupt Enable Register, offset: 0x4 */ uint8_t RESERVED_0[4]; __IO uint32_t ASRCNCR; /**< ASRC Channel Number Configuration Register, offset: 0xC */ __IO uint32_t ASRCFG; /**< ASRC Filter Configuration Status Register, offset: 0x10 */ __IO uint32_t ASRCSR; /**< ASRC Clock Source Register, offset: 0x14 */ __IO uint32_t ASRCDR1; /**< ASRC Clock Divider Register 1, offset: 0x18 */ __IO uint32_t ASRCDR2; /**< ASRC Clock Divider Register 2, offset: 0x1C */ __I uint32_t ASRSTR; /**< ASRC Status Register, offset: 0x20 */ union { /* offset: 0x24 */ __IO uint32_t ASRDCMD; /**< ASRC Debug Command Register, offset: 0x24 */ __I uint32_t ASRRA; /**< Ratio Register Part A, offset: 0x24 */ }; union { /* offset: 0x28 */ __IO uint32_t ASRDINSTH; /**< ASRC Debug Instruction Register High, offset: 0x28 */ __I uint32_t ASRRB; /**< Ratio Register Part B, offset: 0x28 */ }; union { /* offset: 0x2C */ __IO uint32_t ASRDINSTL; /**< ASRC Debug Instruction Register Low, offset: 0x2C */ __I uint32_t ASRRC; /**< Ratio Register Part C, offset: 0x2C */ }; __IO uint32_t ASRMAA; /**< ASRC Memory Access Address Register, offset: 0x30 */ __IO uint32_t ASRMAD; /**< ASRC Memory Access Data Register, offset: 0x34 */ __IO uint32_t ASRDCR; /**< ASRC Debug Control Register, offset: 0x38 */ __IO uint32_t ASRDCR1; /**< ASRC Debug Control Register -1, offset: 0x3C */ __IO uint32_t ASRPM[5]; /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */ __IO uint32_t ASRTFR1; /**< ASRC ASRC Task Queue FIFO Register 1, offset: 0x54 */ __I uint32_t ASRTFR2; /**< ASRC Task queue FIFO Register 2, offset: 0x58 */ __IO uint32_t ASRCCR; /**< ASRC Channel Counter Register, offset: 0x5C */ __O uint32_t ASRDIA; /**< ASRC Data Input Register for Pair x, offset: 0x60 */ __I uint32_t ASRDOA; /**< ASRC Data Output Register for Pair x, offset: 0x64 */ __O uint32_t ASRDIB; /**< ASRC Data Input Register for Pair x, offset: 0x68 */ __I uint32_t ASRDOB; /**< ASRC Data Output Register for Pair x, offset: 0x6C */ __O uint32_t ASRDIC; /**< ASRC Data Input Register for Pair x, offset: 0x70 */ __I uint32_t ASRDOC; /**< ASRC Data Output Register for Pair x, offset: 0x74 */ uint8_t RESERVED_1[8]; __IO uint32_t ASRIDRHA; /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */ __IO uint32_t ASRIDRLA; /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */ __IO uint32_t ASRIDRHB; /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */ __IO uint32_t ASRIDRLB; /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */ __IO uint32_t ASRIDRHC; /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */ __IO uint32_t ASRIDRLC; /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */ __IO uint32_t ASR76K; /**< ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98 */ __IO uint32_t ASR56K; /**< ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C */ __IO uint32_t ASRMCRA; /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */ __I uint32_t ASRFSTA; /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */ __IO uint32_t ASRMCRB; /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */ __I uint32_t ASRFSTB; /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */ __IO uint32_t ASRMCRC; /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */ __I uint32_t ASRFSTC; /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */ uint8_t RESERVED_2[8]; __IO uint32_t ASRMCR1[3]; /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */ } ASRC_Type; /* ---------------------------------------------------------------------------- -- ASRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ASRC_Register_Masks ASRC Register Masks * @{ */ /*! @name ASRCTR - ASRC Control Register */ /*! @{ */ #define ASRC_ASRCTR_ASRCEN_MASK (0x1U) #define ASRC_ASRCTR_ASRCEN_SHIFT (0U) #define ASRC_ASRCTR_ASRCEN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK) #define ASRC_ASRCTR_ASREA_MASK (0x2U) #define ASRC_ASRCTR_ASREA_SHIFT (1U) #define ASRC_ASRCTR_ASREA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK) #define ASRC_ASRCTR_ASREB_MASK (0x4U) #define ASRC_ASRCTR_ASREB_SHIFT (2U) #define ASRC_ASRCTR_ASREB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK) #define ASRC_ASRCTR_ASREC_MASK (0x8U) #define ASRC_ASRCTR_ASREC_SHIFT (3U) #define ASRC_ASRCTR_ASREC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK) #define ASRC_ASRCTR_SRST_MASK (0x10U) #define ASRC_ASRCTR_SRST_SHIFT (4U) #define ASRC_ASRCTR_SRST(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK) #define ASRC_ASRCTR_WINDA_MASK (0x80U) #define ASRC_ASRCTR_WINDA_SHIFT (7U) #define ASRC_ASRCTR_WINDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_WINDA_SHIFT)) & ASRC_ASRCTR_WINDA_MASK) #define ASRC_ASRCTR_WINDB_MASK (0x100U) #define ASRC_ASRCTR_WINDB_SHIFT (8U) #define ASRC_ASRCTR_WINDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_WINDB_SHIFT)) & ASRC_ASRCTR_WINDB_MASK) #define ASRC_ASRCTR_WINDC_MASK (0x200U) #define ASRC_ASRCTR_WINDC_SHIFT (9U) #define ASRC_ASRCTR_WINDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_WINDC_SHIFT)) & ASRC_ASRCTR_WINDC_MASK) #define ASRC_ASRCTR_SHIRA_MASK (0x400U) #define ASRC_ASRCTR_SHIRA_SHIFT (10U) #define ASRC_ASRCTR_SHIRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SHIRA_SHIFT)) & ASRC_ASRCTR_SHIRA_MASK) #define ASRC_ASRCTR_SHIRB_MASK (0x800U) #define ASRC_ASRCTR_SHIRB_SHIFT (11U) #define ASRC_ASRCTR_SHIRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SHIRB_SHIFT)) & ASRC_ASRCTR_SHIRB_MASK) #define ASRC_ASRCTR_SHIRC_MASK (0x1000U) #define ASRC_ASRCTR_SHIRC_SHIFT (12U) #define ASRC_ASRCTR_SHIRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SHIRC_SHIFT)) & ASRC_ASRCTR_SHIRC_MASK) #define ASRC_ASRCTR_IDRA_MASK (0x2000U) #define ASRC_ASRCTR_IDRA_SHIFT (13U) #define ASRC_ASRCTR_IDRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK) #define ASRC_ASRCTR_USRA_MASK (0x4000U) #define ASRC_ASRCTR_USRA_SHIFT (14U) #define ASRC_ASRCTR_USRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK) #define ASRC_ASRCTR_IDRB_MASK (0x8000U) #define ASRC_ASRCTR_IDRB_SHIFT (15U) #define ASRC_ASRCTR_IDRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK) #define ASRC_ASRCTR_USRB_MASK (0x10000U) #define ASRC_ASRCTR_USRB_SHIFT (16U) #define ASRC_ASRCTR_USRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK) #define ASRC_ASRCTR_IDRC_MASK (0x20000U) #define ASRC_ASRCTR_IDRC_SHIFT (17U) #define ASRC_ASRCTR_IDRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK) #define ASRC_ASRCTR_USRC_MASK (0x40000U) #define ASRC_ASRCTR_USRC_SHIFT (18U) #define ASRC_ASRCTR_USRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK) #define ASRC_ASRCTR_SD1R0_MASK (0x80000U) #define ASRC_ASRCTR_SD1R0_SHIFT (19U) #define ASRC_ASRCTR_SD1R0(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SD1R0_SHIFT)) & ASRC_ASRCTR_SD1R0_MASK) #define ASRC_ASRCTR_ATSA_MASK (0x100000U) #define ASRC_ASRCTR_ATSA_SHIFT (20U) #define ASRC_ASRCTR_ATSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK) #define ASRC_ASRCTR_ATSB_MASK (0x200000U) #define ASRC_ASRCTR_ATSB_SHIFT (21U) #define ASRC_ASRCTR_ATSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK) #define ASRC_ASRCTR_ATSC_MASK (0x400000U) #define ASRC_ASRCTR_ATSC_SHIFT (22U) #define ASRC_ASRCTR_ATSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK) #define ASRC_ASRCTR_ASDBG_MASK (0x800000U) #define ASRC_ASRCTR_ASDBG_SHIFT (23U) #define ASRC_ASRCTR_ASDBG(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASDBG_SHIFT)) & ASRC_ASRCTR_ASDBG_MASK) /*! @} */ /*! @name ASRIER - ASRC Interrupt Enable Register */ /*! @{ */ #define ASRC_ASRIER_ADIEA_MASK (0x1U) #define ASRC_ASRIER_ADIEA_SHIFT (0U) /*! ADIEA - ADIEA * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_ADIEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK) #define ASRC_ASRIER_ADIEB_MASK (0x2U) #define ASRC_ASRIER_ADIEB_SHIFT (1U) /*! ADIEB - ADIEB * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_ADIEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK) #define ASRC_ASRIER_ADIEC_MASK (0x4U) #define ASRC_ASRIER_ADIEC_SHIFT (2U) /*! ADIEC - ADIEC * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_ADIEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK) #define ASRC_ASRIER_ADOEA_MASK (0x8U) #define ASRC_ASRIER_ADOEA_SHIFT (3U) /*! ADOEA - ADOEA * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_ADOEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK) #define ASRC_ASRIER_ADOEB_MASK (0x10U) #define ASRC_ASRIER_ADOEB_SHIFT (4U) /*! ADOEB - ADOEB * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_ADOEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK) #define ASRC_ASRIER_ADOEC_MASK (0x20U) #define ASRC_ASRIER_ADOEC_SHIFT (5U) /*! ADOEC - ADOEC * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_ADOEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK) #define ASRC_ASRIER_AOLIE_MASK (0x40U) #define ASRC_ASRIER_AOLIE_SHIFT (6U) /*! AOLIE - AOLIE * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_AOLIE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK) #define ASRC_ASRIER_AFPWE_MASK (0x80U) #define ASRC_ASRIER_AFPWE_SHIFT (7U) /*! AFPWE - AFPWE * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_AFPWE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK) /*! @} */ /*! @name ASRCNCR - ASRC Channel Number Configuration Register */ /*! @{ */ #define ASRC_ASRCNCR_ANCA_MASK (0xFU) #define ASRC_ASRCNCR_ANCA_SHIFT (0U) /*! ANCA - ANCA * 0b0000..0 channels in A (Pair A is disabled) * 0b0001..1 channel in A * 0b0010..2 channels in A * 0b0011..3 channels in A * 0b0100..4 channels in A * 0b0101..5 channels in A * 0b0110..6 channels in A * 0b0111..7 channels in A * 0b1000..8 channels in A * 0b1001..9 channels in A * 0b1010..10 channels in A * 0b1011-0b1111..Should not be used. */ #define ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK) #define ASRC_ASRCNCR_ANCB_MASK (0xF0U) #define ASRC_ASRCNCR_ANCB_SHIFT (4U) /*! ANCB - ANCB * 0b0000..0 channels in B (Pair B is disabled) * 0b0001..1 channel in B * 0b0010..2 channels in B * 0b0011..3 channels in B * 0b0100..4 channels in B * 0b0101..5 channels in B * 0b0110..6 channels in B * 0b0111..7 channels in B * 0b1000..8 channels in B * 0b1001..9 channels in B * 0b1010..10 channels in B * 0b1011-0b1111..Should not be used. */ #define ASRC_ASRCNCR_ANCB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK) #define ASRC_ASRCNCR_ANCC_MASK (0xF00U) #define ASRC_ASRCNCR_ANCC_SHIFT (8U) /*! ANCC - ANCC * 0b0000..0 channels in C (Pair C is disabled) * 0b0001..1 channel in C * 0b0010..2 channels in C * 0b0011..3 channels in C * 0b0100..4 channels in C * 0b0101..5 channels in C * 0b0110..6 channels in C * 0b0111..7 channels in C * 0b1000..8 channels in C * 0b1001..9 channels in C * 0b1010..10 channels in C * 0b1011-0b1111..Should not be used. */ #define ASRC_ASRCNCR_ANCC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK) /*! @} */ /*! @name ASRCFG - ASRC Filter Configuration Status Register */ /*! @{ */ #define ASRC_ASRCFG_HFA_MASK (0x3U) #define ASRC_ASRCFG_HFA_SHIFT (0U) /*! HFA - HFA * 0b00..Select half-band pre-filter. This mode can have less MIPS but at the cost of about -50dB THD+N near Nyquist frequency (the range covers from 20/24*Nyquist frequency to the Nyquist frequency). * 0b01..Select a general type pre-filter with normalized bandwidth chosen as 0.468 * 0b10..Select a general type pre-filter with normalized bandwidth chosen as 0.416 * 0b11..Select a general type pre-filter with normalized bandwidth chosen as 0.292 */ #define ASRC_ASRCFG_HFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_HFA_SHIFT)) & ASRC_ASRCFG_HFA_MASK) #define ASRC_ASRCFG_HFB_MASK (0xCU) #define ASRC_ASRCFG_HFB_SHIFT (2U) /*! HFB - HFB * 0b00..Select half-band pre-filter. This mode can have less MIPS but at the cost of about -50dB THD+N near Nyquist frequency (the range covers from 20/24*Nyquist frequency to the Nyquist frequency). * 0b01..Select a general type pre-filter with normalized bandwidth chosen as 0.468 * 0b10..Select a general type pre-filter with normalized bandwidth chosen as 0.416 * 0b11..Select a general type pre-filter with normalized bandwidth chosen as 0.292 */ #define ASRC_ASRCFG_HFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_HFB_SHIFT)) & ASRC_ASRCFG_HFB_MASK) #define ASRC_ASRCFG_HFC_MASK (0x30U) #define ASRC_ASRCFG_HFC_SHIFT (4U) /*! HFC - HFC * 0b00..Select half-band pre-filter. This mode can have less MIPS but at the cost of about -50dB THD+N near Nyquist frequency (the range covers from 20/24*Nyquist frequency to the Nyquist frequency). * 0b01..Select a general type pre-filter with normalized bandwidth chosen as 0.468 * 0b10..Select a general type pre-filter with normalized bandwidth chosen as 0.416 * 0b11..Select a general type pre-filter with normalized bandwidth chosen as 0.292 */ #define ASRC_ASRCFG_HFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_HFC_SHIFT)) & ASRC_ASRCFG_HFC_MASK) #define ASRC_ASRCFG_PREMODA_MASK (0xC0U) #define ASRC_ASRCFG_PREMODA_SHIFT (6U) #define ASRC_ASRCFG_PREMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK) #define ASRC_ASRCFG_POSTMODA_MASK (0x300U) #define ASRC_ASRCFG_POSTMODA_SHIFT (8U) #define ASRC_ASRCFG_POSTMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK) #define ASRC_ASRCFG_PREMODB_MASK (0xC00U) #define ASRC_ASRCFG_PREMODB_SHIFT (10U) #define ASRC_ASRCFG_PREMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK) #define ASRC_ASRCFG_POSTMODB_MASK (0x3000U) #define ASRC_ASRCFG_POSTMODB_SHIFT (12U) #define ASRC_ASRCFG_POSTMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK) #define ASRC_ASRCFG_PREMODC_MASK (0xC000U) #define ASRC_ASRCFG_PREMODC_SHIFT (14U) #define ASRC_ASRCFG_PREMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK) #define ASRC_ASRCFG_POSTMODC_MASK (0x30000U) #define ASRC_ASRCFG_POSTMODC_SHIFT (16U) /*! POSTMODC - POSTMODC * 0b00..Select Upsampling-by-2 as defined in Signal Processing Flow. * 0b01..Select Direct-Connection as defined in Signal Processing Flow. * 0b10..Select Downsampling-by-2 as defined in Signal Processing Flow. */ #define ASRC_ASRCFG_POSTMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK) #define ASRC_ASRCFG_NDPRA_MASK (0x40000U) #define ASRC_ASRCFG_NDPRA_SHIFT (18U) /*! NDPRA - NDPRA * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM. * 0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM. */ #define ASRC_ASRCFG_NDPRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK) #define ASRC_ASRCFG_NDPRB_MASK (0x80000U) #define ASRC_ASRCFG_NDPRB_SHIFT (19U) /*! NDPRB - NDPRB * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM. * 0b1..Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM. */ #define ASRC_ASRCFG_NDPRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK) #define ASRC_ASRCFG_NDPRC_MASK (0x100000U) #define ASRC_ASRCFG_NDPRC_SHIFT (20U) /*! NDPRC - NDPRC * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM. * 0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM. */ #define ASRC_ASRCFG_NDPRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK) #define ASRC_ASRCFG_INIRQA_MASK (0x200000U) #define ASRC_ASRCFG_INIRQA_SHIFT (21U) #define ASRC_ASRCFG_INIRQA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK) #define ASRC_ASRCFG_INIRQB_MASK (0x400000U) #define ASRC_ASRCFG_INIRQB_SHIFT (22U) #define ASRC_ASRCFG_INIRQB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK) #define ASRC_ASRCFG_INIRQC_MASK (0x800000U) #define ASRC_ASRCFG_INIRQC_SHIFT (23U) #define ASRC_ASRCFG_INIRQC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK) /*! @} */ /*! @name ASRCSR - ASRC Clock Source Register */ /*! @{ */ #define ASRC_ASRCSR_AICSA_MASK (0xFU) #define ASRC_ASRCSR_AICSA_SHIFT (0U) /*! AICSA - AICSA * 0b0000..bit clock 0 * 0b0001..bit clock 1 * 0b0010..bit clock 2 * 0b0011..bit clock 3 * 0b0100..bit clock 4 * 0b0101..bit clock 5 * 0b0110..bit clock 6 * 0b0111..bit clock 7 * 0b1000..bit clock 8 * 0b1001..bit clock 9 * 0b1010..bit clock A * 0b1011..bit clock B * 0b1100..bit clock C * 0b1101..bit clock D * 0b1110..bit clock E * 0b1111..clock disabled, connected to zero */ #define ASRC_ASRCSR_AICSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK) #define ASRC_ASRCSR_AICSB_MASK (0xF0U) #define ASRC_ASRCSR_AICSB_SHIFT (4U) /*! AICSB - AICSB * 0b0000..bit clock 0 * 0b0001..bit clock 1 * 0b0010..bit clock 2 * 0b0011..bit clock 3 * 0b0100..bit clock 4 * 0b0101..bit clock 5 * 0b0110..bit clock 6 * 0b0111..bit clock 7 * 0b1000..bit clock 8 * 0b1001..bit clock 9 * 0b1010..bit clock A * 0b1011..bit clock B * 0b1100..bit clock C * 0b1101..bit clock D * 0b1110..bit clock E * 0b1111..clock disabled, connected to zero */ #define ASRC_ASRCSR_AICSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK) #define ASRC_ASRCSR_AICSC_MASK (0xF00U) #define ASRC_ASRCSR_AICSC_SHIFT (8U) /*! AICSC - AICSC * 0b0000..bit clock 0 * 0b0001..bit clock 1 * 0b0010..bit clock 2 * 0b0011..bit clock 3 * 0b0100..bit clock 4 * 0b0101..bit clock 5 * 0b0110..bit clock 6 * 0b0111..bit clock 7 * 0b1000..bit clock 8 * 0b1001..bit clock 9 * 0b1010..bit clock A * 0b1011..bit clock B * 0b1100..bit clock C * 0b1101..bit clock D * 0b1110..bit clock E * 0b1111..clock disabled, connected to zero */ #define ASRC_ASRCSR_AICSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK) #define ASRC_ASRCSR_AOCSA_MASK (0xF000U) #define ASRC_ASRCSR_AOCSA_SHIFT (12U) /*! AOCSA - AOCSA * 0b0000..bit clock 0 * 0b0001..bit clock 1 * 0b0010..bit clock 2 * 0b0011..bit clock 3 * 0b0100..bit clock 4 * 0b0101..bit clock 5 * 0b0110..bit clock 6 * 0b0111..bit clock 7 * 0b1000..bit clock 8 * 0b1001..bit clock 9 * 0b1010..bit clock A * 0b1011..bit clock B * 0b1100..bit clock C * 0b1101..bit clock D * 0b1110..bit clock E * 0b1111..clock disabled, connected to zero */ #define ASRC_ASRCSR_AOCSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK) #define ASRC_ASRCSR_AOCSB_MASK (0xF0000U) #define ASRC_ASRCSR_AOCSB_SHIFT (16U) /*! AOCSB - AOCSB * 0b0000..bit clock 0 * 0b0001..bit clock 1 * 0b0010..bit clock 2 * 0b0011..bit clock 3 * 0b0100..bit clock 4 * 0b0101..bit clock 5 * 0b0110..bit clock 6 * 0b0111..bit clock 7 * 0b1000..bit clock 8 * 0b1001..bit clock 9 * 0b1010..bit clock A * 0b1011..bit clock B * 0b1100..bit clock C * 0b1101..bit clock D * 0b1110..bit clock E * 0b1111..clock disabled, connected to zero */ #define ASRC_ASRCSR_AOCSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK) #define ASRC_ASRCSR_AOCSC_MASK (0xF00000U) #define ASRC_ASRCSR_AOCSC_SHIFT (20U) /*! AOCSC - AOCSC * 0b0000..bit clock 0 * 0b0001..bit clock 1 * 0b0010..bit clock 2 * 0b0011..bit clock 3 * 0b0100..bit clock 4 * 0b0101..bit clock 5 * 0b0110..bit clock 6 * 0b0111..bit clock 7 * 0b1000..bit clock 8 * 0b1001..bit clock 9 * 0b1010..bit clock A * 0b1011..bit clock B * 0b1100..bit clock C * 0b1101..bit clock D * 0b1110..bit clock E * 0b1111..clock disabled, connected to zero */ #define ASRC_ASRCSR_AOCSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK) /*! @} */ /*! @name ASRCDR1 - ASRC Clock Divider Register 1 */ /*! @{ */ #define ASRC_ASRCDR1_AICPA_MASK (0x7U) #define ASRC_ASRCDR1_AICPA_SHIFT (0U) #define ASRC_ASRCDR1_AICPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK) #define ASRC_ASRCDR1_AICDA_MASK (0x38U) #define ASRC_ASRCDR1_AICDA_SHIFT (3U) #define ASRC_ASRCDR1_AICDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK) #define ASRC_ASRCDR1_AICPB_MASK (0x1C0U) #define ASRC_ASRCDR1_AICPB_SHIFT (6U) #define ASRC_ASRCDR1_AICPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK) #define ASRC_ASRCDR1_AICDB_MASK (0xE00U) #define ASRC_ASRCDR1_AICDB_SHIFT (9U) #define ASRC_ASRCDR1_AICDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK) #define ASRC_ASRCDR1_AOCPA_MASK (0x7000U) #define ASRC_ASRCDR1_AOCPA_SHIFT (12U) #define ASRC_ASRCDR1_AOCPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK) #define ASRC_ASRCDR1_AOCDA_MASK (0x38000U) #define ASRC_ASRCDR1_AOCDA_SHIFT (15U) #define ASRC_ASRCDR1_AOCDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK) #define ASRC_ASRCDR1_AOCPB_MASK (0x1C0000U) #define ASRC_ASRCDR1_AOCPB_SHIFT (18U) #define ASRC_ASRCDR1_AOCPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK) #define ASRC_ASRCDR1_AOCDB_MASK (0xE00000U) #define ASRC_ASRCDR1_AOCDB_SHIFT (21U) #define ASRC_ASRCDR1_AOCDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK) /*! @} */ /*! @name ASRCDR2 - ASRC Clock Divider Register 2 */ /*! @{ */ #define ASRC_ASRCDR2_AICPC_MASK (0x7U) #define ASRC_ASRCDR2_AICPC_SHIFT (0U) #define ASRC_ASRCDR2_AICPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK) #define ASRC_ASRCDR2_AICDC_MASK (0x38U) #define ASRC_ASRCDR2_AICDC_SHIFT (3U) #define ASRC_ASRCDR2_AICDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK) #define ASRC_ASRCDR2_AOCPC_MASK (0x1C0U) #define ASRC_ASRCDR2_AOCPC_SHIFT (6U) #define ASRC_ASRCDR2_AOCPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK) #define ASRC_ASRCDR2_AOCDC_MASK (0xE00U) #define ASRC_ASRCDR2_AOCDC_SHIFT (9U) #define ASRC_ASRCDR2_AOCDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK) /*! @} */ /*! @name ASRSTR - ASRC Status Register */ /*! @{ */ #define ASRC_ASRSTR_AIDEA_MASK (0x1U) #define ASRC_ASRSTR_AIDEA_SHIFT (0U) #define ASRC_ASRSTR_AIDEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK) #define ASRC_ASRSTR_AIDEB_MASK (0x2U) #define ASRC_ASRSTR_AIDEB_SHIFT (1U) #define ASRC_ASRSTR_AIDEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK) #define ASRC_ASRSTR_AIDEC_MASK (0x4U) #define ASRC_ASRSTR_AIDEC_SHIFT (2U) #define ASRC_ASRSTR_AIDEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK) #define ASRC_ASRSTR_AODFA_MASK (0x8U) #define ASRC_ASRSTR_AODFA_SHIFT (3U) #define ASRC_ASRSTR_AODFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK) #define ASRC_ASRSTR_AODFB_MASK (0x10U) #define ASRC_ASRSTR_AODFB_SHIFT (4U) #define ASRC_ASRSTR_AODFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK) #define ASRC_ASRSTR_AODFC_MASK (0x20U) #define ASRC_ASRSTR_AODFC_SHIFT (5U) #define ASRC_ASRSTR_AODFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK) #define ASRC_ASRSTR_AOLE_MASK (0x40U) #define ASRC_ASRSTR_AOLE_SHIFT (6U) #define ASRC_ASRSTR_AOLE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK) #define ASRC_ASRSTR_FPWT_MASK (0x80U) #define ASRC_ASRSTR_FPWT_SHIFT (7U) #define ASRC_ASRSTR_FPWT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK) #define ASRC_ASRSTR_AIDUA_MASK (0x100U) #define ASRC_ASRSTR_AIDUA_SHIFT (8U) #define ASRC_ASRSTR_AIDUA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK) #define ASRC_ASRSTR_AIDUB_MASK (0x200U) #define ASRC_ASRSTR_AIDUB_SHIFT (9U) #define ASRC_ASRSTR_AIDUB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK) #define ASRC_ASRSTR_AIDUC_MASK (0x400U) #define ASRC_ASRSTR_AIDUC_SHIFT (10U) #define ASRC_ASRSTR_AIDUC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK) #define ASRC_ASRSTR_AODOA_MASK (0x800U) #define ASRC_ASRSTR_AODOA_SHIFT (11U) #define ASRC_ASRSTR_AODOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK) #define ASRC_ASRSTR_AODOB_MASK (0x1000U) #define ASRC_ASRSTR_AODOB_SHIFT (12U) #define ASRC_ASRSTR_AODOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK) #define ASRC_ASRSTR_AODOC_MASK (0x2000U) #define ASRC_ASRSTR_AODOC_SHIFT (13U) #define ASRC_ASRSTR_AODOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK) #define ASRC_ASRSTR_AIOLA_MASK (0x4000U) #define ASRC_ASRSTR_AIOLA_SHIFT (14U) #define ASRC_ASRSTR_AIOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK) #define ASRC_ASRSTR_AIOLB_MASK (0x8000U) #define ASRC_ASRSTR_AIOLB_SHIFT (15U) #define ASRC_ASRSTR_AIOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK) #define ASRC_ASRSTR_AIOLC_MASK (0x10000U) #define ASRC_ASRSTR_AIOLC_SHIFT (16U) #define ASRC_ASRSTR_AIOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK) #define ASRC_ASRSTR_AOOLA_MASK (0x20000U) #define ASRC_ASRSTR_AOOLA_SHIFT (17U) #define ASRC_ASRSTR_AOOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK) #define ASRC_ASRSTR_AOOLB_MASK (0x40000U) #define ASRC_ASRSTR_AOOLB_SHIFT (18U) #define ASRC_ASRSTR_AOOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK) #define ASRC_ASRSTR_AOOLC_MASK (0x80000U) #define ASRC_ASRSTR_AOOLC_SHIFT (19U) #define ASRC_ASRSTR_AOOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK) #define ASRC_ASRSTR_ATQOL_MASK (0x100000U) #define ASRC_ASRSTR_ATQOL_SHIFT (20U) #define ASRC_ASRSTR_ATQOL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK) #define ASRC_ASRSTR_DSLCNT_MASK (0x200000U) #define ASRC_ASRSTR_DSLCNT_SHIFT (21U) #define ASRC_ASRSTR_DSLCNT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK) /*! @} */ /*! @name ASRDCMD - ASRC Debug Command Register */ /*! @{ */ #define ASRC_ASRDCMD_PMAB_OR_BKPTAB_MASK (0x1FFU) #define ASRC_ASRDCMD_PMAB_OR_BKPTAB_SHIFT (0U) #define ASRC_ASRDCMD_PMAB_OR_BKPTAB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCMD_PMAB_OR_BKPTAB_SHIFT)) & ASRC_ASRDCMD_PMAB_OR_BKPTAB_MASK) #define ASRC_ASRDCMD_BKPACT_MASK (0x40000U) #define ASRC_ASRDCMD_BKPACT_SHIFT (18U) #define ASRC_ASRDCMD_BKPACT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCMD_BKPACT_SHIFT)) & ASRC_ASRDCMD_BKPACT_MASK) #define ASRC_ASRDCMD_DBGCMD_MASK (0x380000U) #define ASRC_ASRDCMD_DBGCMD_SHIFT (19U) /*! DBGCMD - DBGCMD * 0b000..NOP. No debug operation. * 0b001..GO. This command changes the FP mode from interactive debug mode to normal execution mode. This command is only active when FP is in interactive debug mode. * 0b010..STEP. This command advances the FP mode one instruction further. This command is only active when FP is in interactive debug mode. * 0b011..SET_BREAKPOINT. Set the breakpoint. * 0b100..MANUAL INSTRUCTION. This command forces the FP to put the manual instruction into pipeline for execution in the next running cycle. This command is only active when FP is in interactive debug mode. * 0b101..FORCE_BREAKPOINT. Force the FP into the interactive debug mode. * 0b111..REMOVE_BREAKPOINT. Remove the breakpoint. */ #define ASRC_ASRDCMD_DBGCMD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCMD_DBGCMD_SHIFT)) & ASRC_ASRDCMD_DBGCMD_MASK) #define ASRC_ASRDCMD_SDCMD_MASK (0x400000U) #define ASRC_ASRDCMD_SDCMD_SHIFT (22U) #define ASRC_ASRDCMD_SDCMD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCMD_SDCMD_SHIFT)) & ASRC_ASRDCMD_SDCMD_MASK) #define ASRC_ASRDCMD_INTACT_MASK (0x800000U) #define ASRC_ASRDCMD_INTACT_SHIFT (23U) #define ASRC_ASRDCMD_INTACT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCMD_INTACT_SHIFT)) & ASRC_ASRDCMD_INTACT_MASK) /*! @} */ /*! @name ASRRA - Ratio Register Part A */ /*! @{ */ #define ASRC_ASRRA_ASRRA_MASK (0xFFFFFFU) #define ASRC_ASRRA_ASRRA_SHIFT (0U) #define ASRC_ASRRA_ASRRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRRA_ASRRA_SHIFT)) & ASRC_ASRRA_ASRRA_MASK) /*! @} */ /*! @name ASRDINSTH - ASRC Debug Instruction Register High */ /*! @{ */ #define ASRC_ASRDINSTH_ASRDINSTH_MASK (0xFFFFFFU) #define ASRC_ASRDINSTH_ASRDINSTH_SHIFT (0U) #define ASRC_ASRDINSTH_ASRDINSTH(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDINSTH_ASRDINSTH_SHIFT)) & ASRC_ASRDINSTH_ASRDINSTH_MASK) /*! @} */ /*! @name ASRRB - Ratio Register Part B */ /*! @{ */ #define ASRC_ASRRB_ASRRC_H_MASK (0x3FU) #define ASRC_ASRRB_ASRRC_H_SHIFT (0U) #define ASRC_ASRRB_ASRRC_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRRB_ASRRC_H_SHIFT)) & ASRC_ASRRB_ASRRC_H_MASK) #define ASRC_ASRRB_IPSFT_MASK (0x3F00U) #define ASRC_ASRRB_IPSFT_SHIFT (8U) #define ASRC_ASRRB_IPSFT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRRB_IPSFT_SHIFT)) & ASRC_ASRRB_IPSFT_MASK) #define ASRC_ASRRB_ASRRA_H_MASK (0x3F0000U) #define ASRC_ASRRB_ASRRA_H_SHIFT (16U) #define ASRC_ASRRB_ASRRA_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRRB_ASRRA_H_SHIFT)) & ASRC_ASRRB_ASRRA_H_MASK) /*! @} */ /*! @name ASRDINSTL - ASRC Debug Instruction Register Low */ /*! @{ */ #define ASRC_ASRDINSTL_ASRDINSTL_MASK (0xFFFFFFU) #define ASRC_ASRDINSTL_ASRDINSTL_SHIFT (0U) #define ASRC_ASRDINSTL_ASRDINSTL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDINSTL_ASRDINSTL_SHIFT)) & ASRC_ASRDINSTL_ASRDINSTL_MASK) /*! @} */ /*! @name ASRRC - Ratio Register Part C */ /*! @{ */ #define ASRC_ASRRC_ASRRC_MASK (0xFFFFFFU) #define ASRC_ASRRC_ASRRC_SHIFT (0U) #define ASRC_ASRRC_ASRRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRRC_ASRRC_SHIFT)) & ASRC_ASRRC_ASRRC_MASK) /*! @} */ /*! @name ASRMAA - ASRC Memory Access Address Register */ /*! @{ */ #define ASRC_ASRMAA_ADDR_MASK (0x1FFFU) #define ASRC_ASRMAA_ADDR_SHIFT (0U) #define ASRC_ASRMAA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMAA_ADDR_SHIFT)) & ASRC_ASRMAA_ADDR_MASK) #define ASRC_ASRMAA_MEMOPT_MASK (0xC00000U) #define ASRC_ASRMAA_MEMOPT_SHIFT (22U) #define ASRC_ASRMAA_MEMOPT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMAA_MEMOPT_SHIFT)) & ASRC_ASRMAA_MEMOPT_MASK) /*! @} */ /*! @name ASRMAD - ASRC Memory Access Data Register */ /*! @{ */ #define ASRC_ASRMAD_DATA_MASK (0xFFFFFFU) #define ASRC_ASRMAD_DATA_SHIFT (0U) #define ASRC_ASRMAD_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMAD_DATA_SHIFT)) & ASRC_ASRMAD_DATA_MASK) /*! @} */ /*! @name ASRDCR - ASRC Debug Control Register */ /*! @{ */ #define ASRC_ASRDCR_DSL_TKO_H_MASK (0x3FU) #define ASRC_ASRDCR_DSL_TKO_H_SHIFT (0U) #define ASRC_ASRDCR_DSL_TKO_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_DSL_TKO_H_SHIFT)) & ASRC_ASRDCR_DSL_TKO_H_MASK) #define ASRC_ASRDCR_OUTCLK_MASK (0x100U) #define ASRC_ASRDCR_OUTCLK_SHIFT (8U) #define ASRC_ASRDCR_OUTCLK(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_OUTCLK_SHIFT)) & ASRC_ASRDCR_OUTCLK_MASK) #define ASRC_ASRDCR_INCLK_MASK (0x200U) #define ASRC_ASRDCR_INCLK_SHIFT (9U) #define ASRC_ASRDCR_INCLK(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_INCLK_SHIFT)) & ASRC_ASRDCR_INCLK_MASK) #define ASRC_ASRDCR_CPAIR_MASK (0xC00U) #define ASRC_ASRDCR_CPAIR_SHIFT (10U) #define ASRC_ASRDCR_CPAIR(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_CPAIR_SHIFT)) & ASRC_ASRDCR_CPAIR_MASK) #define ASRC_ASRDCR_PFWPT_MASK (0x1F000U) #define ASRC_ASRDCR_PFWPT_SHIFT (12U) #define ASRC_ASRDCR_PFWPT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_PFWPT_SHIFT)) & ASRC_ASRDCR_PFWPT_MASK) #define ASRC_ASRDCR_TSKQE_MASK (0x20000U) #define ASRC_ASRDCR_TSKQE_SHIFT (17U) #define ASRC_ASRDCR_TSKQE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_TSKQE_SHIFT)) & ASRC_ASRDCR_TSKQE_MASK) #define ASRC_ASRDCR_SFFOA_MASK (0x40000U) #define ASRC_ASRDCR_SFFOA_SHIFT (18U) #define ASRC_ASRDCR_SFFOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_SFFOA_SHIFT)) & ASRC_ASRDCR_SFFOA_MASK) #define ASRC_ASRDCR_SFFOB_MASK (0x80000U) #define ASRC_ASRDCR_SFFOB_SHIFT (19U) #define ASRC_ASRDCR_SFFOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_SFFOB_SHIFT)) & ASRC_ASRDCR_SFFOB_MASK) #define ASRC_ASRDCR_SFFOC_MASK (0x100000U) #define ASRC_ASRDCR_SFFOC_SHIFT (20U) #define ASRC_ASRDCR_SFFOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_SFFOC_SHIFT)) & ASRC_ASRDCR_SFFOC_MASK) #define ASRC_ASRDCR_CNTCLRA_MASK (0x200000U) #define ASRC_ASRDCR_CNTCLRA_SHIFT (21U) #define ASRC_ASRDCR_CNTCLRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_CNTCLRA_SHIFT)) & ASRC_ASRDCR_CNTCLRA_MASK) #define ASRC_ASRDCR_CNTCLRB_MASK (0x400000U) #define ASRC_ASRDCR_CNTCLRB_SHIFT (22U) #define ASRC_ASRDCR_CNTCLRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_CNTCLRB_SHIFT)) & ASRC_ASRDCR_CNTCLRB_MASK) #define ASRC_ASRDCR_CNTCLRC_MASK (0x800000U) #define ASRC_ASRDCR_CNTCLRC_SHIFT (23U) #define ASRC_ASRDCR_CNTCLRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_CNTCLRC_SHIFT)) & ASRC_ASRDCR_CNTCLRC_MASK) /*! @} */ /*! @name ASRDCR1 - ASRC Debug Control Register -1 */ /*! @{ */ #define ASRC_ASRDCR1_DSL_TKO_L_MASK (0xFFFFFFU) #define ASRC_ASRDCR1_DSL_TKO_L_SHIFT (0U) #define ASRC_ASRDCR1_DSL_TKO_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR1_DSL_TKO_L_SHIFT)) & ASRC_ASRDCR1_DSL_TKO_L_MASK) /*! @} */ /*! @name ASRPM - ASRC Parameter Register n */ /*! @{ */ #define ASRC_ASRPM_PARAMETER_VALUE_MASK (0xFFFFFFU) #define ASRC_ASRPM_PARAMETER_VALUE_SHIFT (0U) #define ASRC_ASRPM_PARAMETER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPM_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPM_PARAMETER_VALUE_MASK) /*! @} */ /* The count of ASRC_ASRPM */ #define ASRC_ASRPM_COUNT (5U) /*! @name ASRTFR1 - ASRC ASRC Task Queue FIFO Register 1 */ /*! @{ */ #define ASRC_ASRTFR1_TF_BASE_MASK (0x1FC0U) #define ASRC_ASRTFR1_TF_BASE_SHIFT (6U) #define ASRC_ASRTFR1_TF_BASE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK) #define ASRC_ASRTFR1_TF_FILL_MASK (0xFE000U) #define ASRC_ASRTFR1_TF_FILL_SHIFT (13U) #define ASRC_ASRTFR1_TF_FILL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK) /*! @} */ /*! @name ASRTFR2 - ASRC Task queue FIFO Register 2 */ /*! @{ */ #define ASRC_ASRTFR2_TF_WR_PTR_MASK (0x3FU) #define ASRC_ASRTFR2_TF_WR_PTR_SHIFT (0U) #define ASRC_ASRTFR2_TF_WR_PTR(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR2_TF_WR_PTR_SHIFT)) & ASRC_ASRTFR2_TF_WR_PTR_MASK) #define ASRC_ASRTFR2_TF_RD_PTR_MASK (0xFC0U) #define ASRC_ASRTFR2_TF_RD_PTR_SHIFT (6U) #define ASRC_ASRTFR2_TF_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR2_TF_RD_PTR_SHIFT)) & ASRC_ASRTFR2_TF_RD_PTR_MASK) #define ASRC_ASRTFR2_DSLA_FIFO_PT_MASK (0xF000U) #define ASRC_ASRTFR2_DSLA_FIFO_PT_SHIFT (12U) #define ASRC_ASRTFR2_DSLA_FIFO_PT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR2_DSLA_FIFO_PT_SHIFT)) & ASRC_ASRTFR2_DSLA_FIFO_PT_MASK) #define ASRC_ASRTFR2_DSLB_FIFO_PT_MASK (0xF0000U) #define ASRC_ASRTFR2_DSLB_FIFO_PT_SHIFT (16U) #define ASRC_ASRTFR2_DSLB_FIFO_PT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR2_DSLB_FIFO_PT_SHIFT)) & ASRC_ASRTFR2_DSLB_FIFO_PT_MASK) #define ASRC_ASRTFR2_DSLC_FIFO_PT_MASK (0xF00000U) #define ASRC_ASRTFR2_DSLC_FIFO_PT_SHIFT (20U) #define ASRC_ASRTFR2_DSLC_FIFO_PT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR2_DSLC_FIFO_PT_SHIFT)) & ASRC_ASRTFR2_DSLC_FIFO_PT_MASK) /*! @} */ /*! @name ASRCCR - ASRC Channel Counter Register */ /*! @{ */ #define ASRC_ASRCCR_ACIA_MASK (0xFU) #define ASRC_ASRCCR_ACIA_SHIFT (0U) #define ASRC_ASRCCR_ACIA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK) #define ASRC_ASRCCR_ACIB_MASK (0xF0U) #define ASRC_ASRCCR_ACIB_SHIFT (4U) #define ASRC_ASRCCR_ACIB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK) #define ASRC_ASRCCR_ACIC_MASK (0xF00U) #define ASRC_ASRCCR_ACIC_SHIFT (8U) #define ASRC_ASRCCR_ACIC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK) #define ASRC_ASRCCR_ACOA_MASK (0xF000U) #define ASRC_ASRCCR_ACOA_SHIFT (12U) #define ASRC_ASRCCR_ACOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK) #define ASRC_ASRCCR_ACOB_MASK (0xF0000U) #define ASRC_ASRCCR_ACOB_SHIFT (16U) #define ASRC_ASRCCR_ACOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK) #define ASRC_ASRCCR_ACOC_MASK (0xF00000U) #define ASRC_ASRCCR_ACOC_SHIFT (20U) #define ASRC_ASRCCR_ACOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK) /*! @} */ /*! @name ASRDIA - ASRC Data Input Register for Pair x */ /*! @{ */ #define ASRC_ASRDIA_DATA_MASK (0xFFFFFFU) #define ASRC_ASRDIA_DATA_SHIFT (0U) #define ASRC_ASRDIA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK) /*! @} */ /*! @name ASRDOA - ASRC Data Output Register for Pair x */ /*! @{ */ #define ASRC_ASRDOA_DATA_MASK (0xFFFFFFU) #define ASRC_ASRDOA_DATA_SHIFT (0U) #define ASRC_ASRDOA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK) /*! @} */ /*! @name ASRDIB - ASRC Data Input Register for Pair x */ /*! @{ */ #define ASRC_ASRDIB_DATA_MASK (0xFFFFFFU) #define ASRC_ASRDIB_DATA_SHIFT (0U) #define ASRC_ASRDIB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK) /*! @} */ /*! @name ASRDOB - ASRC Data Output Register for Pair x */ /*! @{ */ #define ASRC_ASRDOB_DATA_MASK (0xFFFFFFU) #define ASRC_ASRDOB_DATA_SHIFT (0U) #define ASRC_ASRDOB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK) /*! @} */ /*! @name ASRDIC - ASRC Data Input Register for Pair x */ /*! @{ */ #define ASRC_ASRDIC_DATA_MASK (0xFFFFFFU) #define ASRC_ASRDIC_DATA_SHIFT (0U) #define ASRC_ASRDIC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK) /*! @} */ /*! @name ASRDOC - ASRC Data Output Register for Pair x */ /*! @{ */ #define ASRC_ASRDOC_DATA_MASK (0xFFFFFFU) #define ASRC_ASRDOC_DATA_SHIFT (0U) #define ASRC_ASRDOC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK) /*! @} */ /*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */ /*! @{ */ #define ASRC_ASRIDRHA_IDRATIOA_H_MASK (0xFFU) #define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT (0U) #define ASRC_ASRIDRHA_IDRATIOA_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK) /*! @} */ /*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */ /*! @{ */ #define ASRC_ASRIDRLA_IDRATIOA_L_MASK (0xFFFFFFU) #define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT (0U) #define ASRC_ASRIDRLA_IDRATIOA_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK) /*! @} */ /*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */ /*! @{ */ #define ASRC_ASRIDRHB_IDRATIOB_H_MASK (0xFFU) #define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT (0U) #define ASRC_ASRIDRHB_IDRATIOB_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK) /*! @} */ /*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */ /*! @{ */ #define ASRC_ASRIDRLB_IDRATIOB_L_MASK (0xFFFFFFU) #define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT (0U) #define ASRC_ASRIDRLB_IDRATIOB_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK) /*! @} */ /*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */ /*! @{ */ #define ASRC_ASRIDRHC_IDRATIOC_H_MASK (0xFFU) #define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT (0U) #define ASRC_ASRIDRHC_IDRATIOC_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK) /*! @} */ /*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */ /*! @{ */ #define ASRC_ASRIDRLC_IDRATIOC_L_MASK (0xFFFFFFU) #define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT (0U) #define ASRC_ASRIDRLC_IDRATIOC_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK) /*! @} */ /*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */ /*! @{ */ #define ASRC_ASR76K_ASR76K_MASK (0x1FFFFU) #define ASRC_ASR76K_ASR76K_SHIFT (0U) #define ASRC_ASR76K_ASR76K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK) /*! @} */ /*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */ /*! @{ */ #define ASRC_ASR56K_ASR56K_MASK (0x1FFFFU) #define ASRC_ASR56K_ASR56K_SHIFT (0U) #define ASRC_ASR56K_ASR56K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK) /*! @} */ /*! @name ASRMCRA - ASRC Misc Control Register for Pair A */ /*! @{ */ #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK (0x3FU) #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT (0U) #define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK) #define ASRC_ASRMCRA_RSYNOFA_MASK (0x400U) #define ASRC_ASRMCRA_RSYNOFA_SHIFT (10U) #define ASRC_ASRMCRA_RSYNOFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK) #define ASRC_ASRMCRA_RSYNIFA_MASK (0x800U) #define ASRC_ASRMCRA_RSYNIFA_SHIFT (11U) #define ASRC_ASRMCRA_RSYNIFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK) #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK (0x3F000U) #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT (12U) #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK) #define ASRC_ASRMCRA_BYPASSPOLYA_MASK (0x100000U) #define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT (20U) /*! BYPASSPOLYA - BYPASSPOLYA * 0b1..Bypass polyphase filtering. * 0b0..Don't bypass polyphase filtering. */ #define ASRC_ASRMCRA_BYPASSPOLYA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK) #define ASRC_ASRMCRA_BUFSTALLA_MASK (0x200000U) #define ASRC_ASRMCRA_BUFSTALLA_SHIFT (21U) /*! BUFSTALLA - BUFSTALLA * 0b1..Stall Pair A conversion in case of near empty/full FIFO conditions. * 0b0..Don't stall Pair A conversion even in case of near empty/full FIFO conditions. */ #define ASRC_ASRMCRA_BUFSTALLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK) #define ASRC_ASRMCRA_EXTTHRSHA_MASK (0x400000U) #define ASRC_ASRMCRA_EXTTHRSHA_SHIFT (22U) /*! EXTTHRSHA - EXTTHRSHA * 0b1..Use external defined thresholds. * 0b0..Use default thresholds. */ #define ASRC_ASRMCRA_EXTTHRSHA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK) #define ASRC_ASRMCRA_ZEROBUFA_MASK (0x800000U) #define ASRC_ASRMCRA_ZEROBUFA_SHIFT (23U) /*! ZEROBUFA - ZEROBUFA * 0b1..Don't zeroize the buffer * 0b0..Zeroize the buffer */ #define ASRC_ASRMCRA_ZEROBUFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK) /*! @} */ /*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */ /*! @{ */ #define ASRC_ASRFSTA_INFIFO_FILLA_MASK (0x7FU) #define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT (0U) #define ASRC_ASRFSTA_INFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK) #define ASRC_ASRFSTA_IAEA_MASK (0x800U) #define ASRC_ASRFSTA_IAEA_SHIFT (11U) #define ASRC_ASRFSTA_IAEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK) #define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK (0x7F000U) #define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT (12U) #define ASRC_ASRFSTA_OUTFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK) #define ASRC_ASRFSTA_OAFA_MASK (0x800000U) #define ASRC_ASRFSTA_OAFA_SHIFT (23U) #define ASRC_ASRFSTA_OAFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK) /*! @} */ /*! @name ASRMCRB - ASRC Misc Control Register for Pair B */ /*! @{ */ #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK (0x3FU) #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT (0U) #define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK) #define ASRC_ASRMCRB_RSYNOFB_MASK (0x400U) #define ASRC_ASRMCRB_RSYNOFB_SHIFT (10U) #define ASRC_ASRMCRB_RSYNOFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK) #define ASRC_ASRMCRB_RSYNIFB_MASK (0x800U) #define ASRC_ASRMCRB_RSYNIFB_SHIFT (11U) #define ASRC_ASRMCRB_RSYNIFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK) #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK (0x3F000U) #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT (12U) #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK) #define ASRC_ASRMCRB_BYPASSPOLYB_MASK (0x100000U) #define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT (20U) /*! BYPASSPOLYB - BYPASSPOLYB * 0b1..Bypass polyphase filtering. * 0b0..Don't bypass polyphase filtering. */ #define ASRC_ASRMCRB_BYPASSPOLYB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK) #define ASRC_ASRMCRB_BUFSTALLB_MASK (0x200000U) #define ASRC_ASRMCRB_BUFSTALLB_SHIFT (21U) /*! BUFSTALLB - BUFSTALLB * 0b1..Stall Pair B conversion in case of near empty/full FIFO conditions. * 0b0..Don't stall Pair B conversion even in case of near empty/full FIFO conditions. */ #define ASRC_ASRMCRB_BUFSTALLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK) #define ASRC_ASRMCRB_EXTTHRSHB_MASK (0x400000U) #define ASRC_ASRMCRB_EXTTHRSHB_SHIFT (22U) /*! EXTTHRSHB - EXTTHRSHB * 0b1..Use external defined thresholds. * 0b0..Use default thresholds. */ #define ASRC_ASRMCRB_EXTTHRSHB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK) #define ASRC_ASRMCRB_ZEROBUFB_MASK (0x800000U) #define ASRC_ASRMCRB_ZEROBUFB_SHIFT (23U) /*! ZEROBUFB - ZEROBUFB * 0b1..Don't zeroize the buffer * 0b0..Zeroize the buffer */ #define ASRC_ASRMCRB_ZEROBUFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK) /*! @} */ /*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */ /*! @{ */ #define ASRC_ASRFSTB_INFIFO_FILLB_MASK (0x7FU) #define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT (0U) #define ASRC_ASRFSTB_INFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK) #define ASRC_ASRFSTB_IAEB_MASK (0x800U) #define ASRC_ASRFSTB_IAEB_SHIFT (11U) #define ASRC_ASRFSTB_IAEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK) #define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK (0x7F000U) #define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT (12U) #define ASRC_ASRFSTB_OUTFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK) #define ASRC_ASRFSTB_OAFB_MASK (0x800000U) #define ASRC_ASRFSTB_OAFB_SHIFT (23U) #define ASRC_ASRFSTB_OAFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK) /*! @} */ /*! @name ASRMCRC - ASRC Misc Control Register for Pair C */ /*! @{ */ #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK (0x3FU) #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT (0U) #define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK) #define ASRC_ASRMCRC_RSYNOFC_MASK (0x400U) #define ASRC_ASRMCRC_RSYNOFC_SHIFT (10U) #define ASRC_ASRMCRC_RSYNOFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK) #define ASRC_ASRMCRC_RSYNIFC_MASK (0x800U) #define ASRC_ASRMCRC_RSYNIFC_SHIFT (11U) #define ASRC_ASRMCRC_RSYNIFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK) #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK (0x3F000U) #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT (12U) #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK) #define ASRC_ASRMCRC_BYPASSPOLYC_MASK (0x100000U) #define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT (20U) /*! BYPASSPOLYC - BYPASSPOLYC * 0b1..Bypass polyphase filtering. * 0b0..Don't bypass polyphase filtering. */ #define ASRC_ASRMCRC_BYPASSPOLYC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK) #define ASRC_ASRMCRC_BUFSTALLC_MASK (0x200000U) #define ASRC_ASRMCRC_BUFSTALLC_SHIFT (21U) /*! BUFSTALLC - BUFSTALLC * 0b1..Stall Pair C conversion in case of near empty/full FIFO conditions. * 0b0..Don't stall Pair C conversion even in case of near empty/full FIFO conditions. */ #define ASRC_ASRMCRC_BUFSTALLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK) #define ASRC_ASRMCRC_EXTTHRSHC_MASK (0x400000U) #define ASRC_ASRMCRC_EXTTHRSHC_SHIFT (22U) /*! EXTTHRSHC - EXTTHRSHC * 0b1..Use external defined thresholds. * 0b0..Use default thresholds. */ #define ASRC_ASRMCRC_EXTTHRSHC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK) #define ASRC_ASRMCRC_ZEROBUFC_MASK (0x800000U) #define ASRC_ASRMCRC_ZEROBUFC_SHIFT (23U) /*! ZEROBUFC - ZEROBUFC * 0b1..Don't zeroize the buffer * 0b0..Zeroize the buffer */ #define ASRC_ASRMCRC_ZEROBUFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK) /*! @} */ /*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */ /*! @{ */ #define ASRC_ASRFSTC_INFIFO_FILLC_MASK (0x7FU) #define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT (0U) #define ASRC_ASRFSTC_INFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK) #define ASRC_ASRFSTC_IAEC_MASK (0x800U) #define ASRC_ASRFSTC_IAEC_SHIFT (11U) #define ASRC_ASRFSTC_IAEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK) #define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK (0x7F000U) #define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT (12U) #define ASRC_ASRFSTC_OUTFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK) #define ASRC_ASRFSTC_OAFC_MASK (0x800000U) #define ASRC_ASRFSTC_OAFC_SHIFT (23U) #define ASRC_ASRFSTC_OAFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK) /*! @} */ /*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */ /*! @{ */ #define ASRC_ASRMCR1_OW16_MASK (0x1U) #define ASRC_ASRMCR1_OW16_SHIFT (0U) /*! OW16 - OW16 * 0b1..16-bit output data * 0b0..24-bit output data. */ #define ASRC_ASRMCR1_OW16(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK) #define ASRC_ASRMCR1_OSGN_MASK (0x2U) #define ASRC_ASRMCR1_OSGN_SHIFT (1U) /*! OSGN - OSGN * 0b1..Sign extension. * 0b0..No sign extension. */ #define ASRC_ASRMCR1_OSGN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK) #define ASRC_ASRMCR1_OMSB_MASK (0x4U) #define ASRC_ASRMCR1_OMSB_SHIFT (2U) /*! OMSB - OMSB * 0b1..MSB aligned. * 0b0..LSB aligned. */ #define ASRC_ASRMCR1_OMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK) #define ASRC_ASRMCR1_IMSB_MASK (0x100U) #define ASRC_ASRMCR1_IMSB_SHIFT (8U) /*! IMSB - IMSB * 0b1..MSB aligned. * 0b0..LSB aligned. */ #define ASRC_ASRMCR1_IMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK) #define ASRC_ASRMCR1_IWD_MASK (0xE00U) #define ASRC_ASRMCR1_IWD_SHIFT (9U) #define ASRC_ASRMCR1_IWD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK) /*! @} */ /* The count of ASRC_ASRMCR1 */ #define ASRC_ASRMCR1_COUNT (3U) /*! * @} */ /* end of group ASRC_Register_Masks */ /* ASRC - Peripheral instance base addresses */ /** Peripheral AUDIO__ASRC0 base address */ #define AUDIO__ASRC0_BASE (0x59000000u) /** Peripheral AUDIO__ASRC0 base pointer */ #define AUDIO__ASRC0 ((ASRC_Type *)AUDIO__ASRC0_BASE) /** Peripheral AUDIO__ASRC1 base address */ #define AUDIO__ASRC1_BASE (0x59800000u) /** Peripheral AUDIO__ASRC1 base pointer */ #define AUDIO__ASRC1 ((ASRC_Type *)AUDIO__ASRC1_BASE) /** Array initializer of ASRC peripheral base addresses */ #define ASRC_BASE_ADDRS { AUDIO__ASRC0_BASE, AUDIO__ASRC1_BASE } /** Array initializer of ASRC peripheral base pointers */ #define ASRC_BASE_PTRS { AUDIO__ASRC0, AUDIO__ASRC1 } /*! * @} */ /* end of group ASRC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_ACM_REGS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_ACM_REGS_Peripheral_Access_Layer AUDIO_LPCG_ACM_REGS Peripheral Access Layer * @{ */ /** AUDIO_LPCG_ACM_REGS - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_ACM_REGS_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_ACM_REGS_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_ACM_REGS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_ACM_REGS_Register_Masks AUDIO_LPCG_ACM_REGS Register Masks * @{ */ /*! @name LPCG_LPCG_ACM_REGS_0 - na */ /*! @{ */ #define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN_MASK (0x1U) #define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN_SHIFT (0U) #define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN_SHIFT)) & AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN_MASK) #define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN_MASK (0x2U) #define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN_SHIFT (1U) #define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN_MASK) #define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_2_2_MASK) #define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP_MASK (0x8U) #define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP_SHIFT (3U) #define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP_MASK) #define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_4_31_MASK (0xFFFFFFF0U) #define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_4_31_SHIFT (4U) #define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_4_31_SHIFT)) & AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_ACM_REGS_Register_Masks */ /* AUDIO_LPCG_ACM_REGS - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_ACM_REGS base address */ #define AUDIO__LPCG_ACM_REGS_BASE (0x59C60000u) /** Peripheral AUDIO__LPCG_ACM_REGS base pointer */ #define AUDIO__LPCG_ACM_REGS ((AUDIO_LPCG_ACM_REGS_Type *)AUDIO__LPCG_ACM_REGS_BASE) /** Array initializer of AUDIO_LPCG_ACM_REGS peripheral base addresses */ #define AUDIO_LPCG_ACM_REGS_BASE_ADDRS { AUDIO__LPCG_ACM_REGS_BASE } /** Array initializer of AUDIO_LPCG_ACM_REGS peripheral base pointers */ #define AUDIO_LPCG_ACM_REGS_BASE_PTRS { AUDIO__LPCG_ACM_REGS } /*! * @} */ /* end of group AUDIO_LPCG_ACM_REGS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_AMIX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_AMIX_Peripheral_Access_Layer AUDIO_LPCG_AMIX Peripheral Access Layer * @{ */ /** AUDIO_LPCG_AMIX - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_AMIX_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_AMIX_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_AMIX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_AMIX_Register_Masks AUDIO_LPCG_AMIX Register Masks * @{ */ /*! @name LPCG_LPCG_AMIX_0 - na */ /*! @{ */ #define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0_MASK) #define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN_MASK (0x2U) #define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN_SHIFT (1U) #define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN_MASK) #define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2_MASK) #define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP_MASK (0x8U) #define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP_SHIFT (3U) #define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP_MASK) #define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31_MASK (0xFFFFFFF0U) #define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31_SHIFT (4U) #define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31_SHIFT)) & AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_AMIX_Register_Masks */ /* AUDIO_LPCG_AMIX - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_AMIX base address */ #define AUDIO__LPCG_AMIX_BASE (0x59C40000u) /** Peripheral AUDIO__LPCG_AMIX base pointer */ #define AUDIO__LPCG_AMIX ((AUDIO_LPCG_AMIX_Type *)AUDIO__LPCG_AMIX_BASE) /** Array initializer of AUDIO_LPCG_AMIX peripheral base addresses */ #define AUDIO_LPCG_AMIX_BASE_ADDRS { AUDIO__LPCG_AMIX_BASE } /** Array initializer of AUDIO_LPCG_AMIX peripheral base pointers */ #define AUDIO_LPCG_AMIX_BASE_PTRS { AUDIO__LPCG_AMIX } /*! * @} */ /* end of group AUDIO_LPCG_AMIX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_ASRC0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_ASRC0_Peripheral_Access_Layer AUDIO_LPCG_ASRC0 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_ASRC0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_ASRC0_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_ASRC0_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_ASRC0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_ASRC0_Register_Masks AUDIO_LPCG_ASRC0 Register Masks * @{ */ /*! @name LPCG_LPCG_ASRC0_0 - na */ /*! @{ */ #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_0_MASK) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN_MASK (0x2U) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN_SHIFT (1U) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN_MASK) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_2_2_MASK) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP_MASK (0x8U) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP_SHIFT (3U) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP_MASK) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_4_8_MASK (0x1F0U) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_4_8_SHIFT (4U) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_4_8(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_4_8_SHIFT)) & AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_4_8_MASK) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_SWEN_MASK (0x200U) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_SWEN_SHIFT (9U) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_SWEN_MASK) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_10_10_MASK (0x400U) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_10_10_SHIFT (10U) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_10_10_MASK) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_STOP_MASK (0x800U) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_STOP_SHIFT (11U) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_STOP_MASK) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_12_31_MASK (0xFFFFF000U) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_12_31_SHIFT (12U) #define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_12_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_12_31_SHIFT)) & AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_12_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_ASRC0_Register_Masks */ /* AUDIO_LPCG_ASRC0 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_ASRC0 base address */ #define AUDIO__LPCG_ASRC0_BASE (0x59400000u) /** Peripheral AUDIO__LPCG_ASRC0 base pointer */ #define AUDIO__LPCG_ASRC0 ((AUDIO_LPCG_ASRC0_Type *)AUDIO__LPCG_ASRC0_BASE) /** Array initializer of AUDIO_LPCG_ASRC0 peripheral base addresses */ #define AUDIO_LPCG_ASRC0_BASE_ADDRS { AUDIO__LPCG_ASRC0_BASE } /** Array initializer of AUDIO_LPCG_ASRC0 peripheral base pointers */ #define AUDIO_LPCG_ASRC0_BASE_PTRS { AUDIO__LPCG_ASRC0 } /*! * @} */ /* end of group AUDIO_LPCG_ASRC0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_ASRC1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_ASRC1_Peripheral_Access_Layer AUDIO_LPCG_ASRC1 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_ASRC1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_ASRC1_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_ASRC1_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_ASRC1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_ASRC1_Register_Masks AUDIO_LPCG_ASRC1 Register Masks * @{ */ /*! @name LPCG_LPCG_ASRC1_0 - na */ /*! @{ */ #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_0_MASK) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN_MASK (0x2U) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN_SHIFT (1U) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN_MASK) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_2_2_MASK) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP_MASK (0x8U) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP_SHIFT (3U) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP_MASK) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_4_8_MASK (0x1F0U) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_4_8_SHIFT (4U) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_4_8(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_4_8_SHIFT)) & AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_4_8_MASK) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_SWEN_MASK (0x200U) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_SWEN_SHIFT (9U) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_SWEN_MASK) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_10_10_MASK (0x400U) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_10_10_SHIFT (10U) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_10_10_MASK) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_STOP_MASK (0x800U) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_STOP_SHIFT (11U) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_STOP_MASK) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_12_31_MASK (0xFFFFF000U) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_12_31_SHIFT (12U) #define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_12_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_12_31_SHIFT)) & AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_12_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_ASRC1_Register_Masks */ /* AUDIO_LPCG_ASRC1 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_ASRC1 base address */ #define AUDIO__LPCG_ASRC1_BASE (0x59C00000u) /** Peripheral AUDIO__LPCG_ASRC1 base pointer */ #define AUDIO__LPCG_ASRC1 ((AUDIO_LPCG_ASRC1_Type *)AUDIO__LPCG_ASRC1_BASE) /** Array initializer of AUDIO_LPCG_ASRC1 peripheral base addresses */ #define AUDIO_LPCG_ASRC1_BASE_ADDRS { AUDIO__LPCG_ASRC1_BASE } /** Array initializer of AUDIO_LPCG_ASRC1 peripheral base pointers */ #define AUDIO_LPCG_ASRC1_BASE_PTRS { AUDIO__LPCG_ASRC1 } /*! * @} */ /* end of group AUDIO_LPCG_ASRC1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_AUD_PLL_DIV_CLK0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_AUD_PLL_DIV_CLK0_Peripheral_Access_Layer AUDIO_LPCG_AUD_PLL_DIV_CLK0 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_AUD_PLL_DIV_CLK0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_AUD_PLL_DIV_CLK0_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_AUD_PLL_DIV_CLK0_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_AUD_PLL_DIV_CLK0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_AUD_PLL_DIV_CLK0_Register_Masks AUDIO_LPCG_AUD_PLL_DIV_CLK0 Register Masks * @{ */ /*! @name LPCG_LPCG_AUD_PLL_DIV_CLK0_0 - na */ /*! @{ */ #define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0_MASK) #define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN_MASK (0x2U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN_SHIFT (1U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN_MASK) #define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2_MASK) #define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP_MASK (0x8U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP_SHIFT (3U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP_MASK) #define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31_MASK (0xFFFFFFF0U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31_SHIFT (4U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_AUD_PLL_DIV_CLK0_Register_Masks */ /* AUDIO_LPCG_AUD_PLL_DIV_CLK0 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK0 base address */ #define AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK0_BASE (0x59D20000u) /** Peripheral AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK0 base pointer */ #define AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK0 ((AUDIO_LPCG_AUD_PLL_DIV_CLK0_Type *)AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK0_BASE) /** Array initializer of AUDIO_LPCG_AUD_PLL_DIV_CLK0 peripheral base addresses */ #define AUDIO_LPCG_AUD_PLL_DIV_CLK0_BASE_ADDRS { AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK0_BASE } /** Array initializer of AUDIO_LPCG_AUD_PLL_DIV_CLK0 peripheral base pointers */ #define AUDIO_LPCG_AUD_PLL_DIV_CLK0_BASE_PTRS { AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK0 } /*! * @} */ /* end of group AUDIO_LPCG_AUD_PLL_DIV_CLK0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_AUD_PLL_DIV_CLK1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_AUD_PLL_DIV_CLK1_Peripheral_Access_Layer AUDIO_LPCG_AUD_PLL_DIV_CLK1 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_AUD_PLL_DIV_CLK1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_AUD_PLL_DIV_CLK1_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_AUD_PLL_DIV_CLK1_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_AUD_PLL_DIV_CLK1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_AUD_PLL_DIV_CLK1_Register_Masks AUDIO_LPCG_AUD_PLL_DIV_CLK1 Register Masks * @{ */ /*! @name LPCG_LPCG_AUD_PLL_DIV_CLK1_0 - na */ /*! @{ */ #define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0_MASK) #define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN_MASK (0x2U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN_SHIFT (1U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN_MASK) #define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2_MASK) #define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP_MASK (0x8U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP_SHIFT (3U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP_MASK) #define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31_MASK (0xFFFFFFF0U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31_SHIFT (4U) #define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_AUD_PLL_DIV_CLK1_Register_Masks */ /* AUDIO_LPCG_AUD_PLL_DIV_CLK1 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK1 base address */ #define AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK1_BASE (0x59D30000u) /** Peripheral AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK1 base pointer */ #define AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK1 ((AUDIO_LPCG_AUD_PLL_DIV_CLK1_Type *)AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK1_BASE) /** Array initializer of AUDIO_LPCG_AUD_PLL_DIV_CLK1 peripheral base addresses */ #define AUDIO_LPCG_AUD_PLL_DIV_CLK1_BASE_ADDRS { AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK1_BASE } /** Array initializer of AUDIO_LPCG_AUD_PLL_DIV_CLK1 peripheral base pointers */ #define AUDIO_LPCG_AUD_PLL_DIV_CLK1_BASE_PTRS { AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK1 } /*! * @} */ /* end of group AUDIO_LPCG_AUD_PLL_DIV_CLK1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_AUD_REC_CLK0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_AUD_REC_CLK0_Peripheral_Access_Layer AUDIO_LPCG_AUD_REC_CLK0 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_AUD_REC_CLK0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_AUD_REC_CLK0_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_AUD_REC_CLK0_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_AUD_REC_CLK0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_AUD_REC_CLK0_Register_Masks AUDIO_LPCG_AUD_REC_CLK0 Register Masks * @{ */ /*! @name LPCG_LPCG_AUD_REC_CLK0_0 - na */ /*! @{ */ #define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0_MASK) #define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN_MASK (0x2U) #define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN_SHIFT (1U) #define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN_MASK) #define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2_MASK) #define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP_MASK (0x8U) #define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP_SHIFT (3U) #define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP_MASK) #define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31_MASK (0xFFFFFFF0U) #define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31_SHIFT (4U) #define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_AUD_REC_CLK0_Register_Masks */ /* AUDIO_LPCG_AUD_REC_CLK0 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_ACM_AUD_REC_CLK0 base address */ #define AUDIO__LPCG_ACM_AUD_REC_CLK0_BASE (0x59D00000u) /** Peripheral AUDIO__LPCG_ACM_AUD_REC_CLK0 base pointer */ #define AUDIO__LPCG_ACM_AUD_REC_CLK0 ((AUDIO_LPCG_AUD_REC_CLK0_Type *)AUDIO__LPCG_ACM_AUD_REC_CLK0_BASE) /** Array initializer of AUDIO_LPCG_AUD_REC_CLK0 peripheral base addresses */ #define AUDIO_LPCG_AUD_REC_CLK0_BASE_ADDRS { AUDIO__LPCG_ACM_AUD_REC_CLK0_BASE } /** Array initializer of AUDIO_LPCG_AUD_REC_CLK0 peripheral base pointers */ #define AUDIO_LPCG_AUD_REC_CLK0_BASE_PTRS { AUDIO__LPCG_ACM_AUD_REC_CLK0 } /*! * @} */ /* end of group AUDIO_LPCG_AUD_REC_CLK0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_AUD_REC_CLK1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_AUD_REC_CLK1_Peripheral_Access_Layer AUDIO_LPCG_AUD_REC_CLK1 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_AUD_REC_CLK1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_AUD_REC_CLK1_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_AUD_REC_CLK1_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_AUD_REC_CLK1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_AUD_REC_CLK1_Register_Masks AUDIO_LPCG_AUD_REC_CLK1 Register Masks * @{ */ /*! @name LPCG_LPCG_AUD_REC_CLK1_0 - na */ /*! @{ */ #define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0_MASK) #define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN_MASK (0x2U) #define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN_SHIFT (1U) #define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN_MASK) #define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2_MASK) #define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP_MASK (0x8U) #define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP_SHIFT (3U) #define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP_MASK) #define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31_MASK (0xFFFFFFF0U) #define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31_SHIFT (4U) #define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_AUD_REC_CLK1_Register_Masks */ /* AUDIO_LPCG_AUD_REC_CLK1 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_ACM_AUD_REC_CLK1 base address */ #define AUDIO__LPCG_ACM_AUD_REC_CLK1_BASE (0x59D10000u) /** Peripheral AUDIO__LPCG_ACM_AUD_REC_CLK1 base pointer */ #define AUDIO__LPCG_ACM_AUD_REC_CLK1 ((AUDIO_LPCG_AUD_REC_CLK1_Type *)AUDIO__LPCG_ACM_AUD_REC_CLK1_BASE) /** Array initializer of AUDIO_LPCG_AUD_REC_CLK1 peripheral base addresses */ #define AUDIO_LPCG_AUD_REC_CLK1_BASE_ADDRS { AUDIO__LPCG_ACM_AUD_REC_CLK1_BASE } /** Array initializer of AUDIO_LPCG_AUD_REC_CLK1 peripheral base pointers */ #define AUDIO_LPCG_AUD_REC_CLK1_BASE_PTRS { AUDIO__LPCG_ACM_AUD_REC_CLK1 } /*! * @} */ /* end of group AUDIO_LPCG_AUD_REC_CLK1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_EDMA0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_EDMA0_Peripheral_Access_Layer AUDIO_LPCG_EDMA0 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_EDMA0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_EDMA0_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_EDMA0_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_EDMA0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_EDMA0_Register_Masks AUDIO_LPCG_EDMA0 Register Masks * @{ */ /*! @name LPCG_LPCG_EDMA0_0 - na */ /*! @{ */ #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0_MASK) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN_MASK (0x2U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN_SHIFT (1U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN_MASK) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2_MASK) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP_MASK (0x8U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP_SHIFT (3U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP_MASK) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16_MASK (0x1FFF0U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16_SHIFT (4U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16_MASK) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN_MASK (0x20000U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN_SHIFT (17U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN_MASK) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18_MASK) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP_MASK (0x80000U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP_SHIFT (19U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP_MASK) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_24_MASK (0x1F00000U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_24_SHIFT (20U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_24(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_24_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_24_MASK) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_SWEN_MASK (0x2000000U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_SWEN_SHIFT (25U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_SWEN_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_SWEN_MASK) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_26_26_MASK (0x4000000U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_26_26_SHIFT (26U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_26_26_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_26_26_MASK) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_STOP_MASK (0x8000000U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_STOP_SHIFT (27U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_STOP_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_STOP_MASK) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_28_31_MASK (0xF0000000U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_28_31_SHIFT (28U) #define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_28_31_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_28_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_EDMA0_Register_Masks */ /* AUDIO_LPCG_EDMA0 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_EDMA0 base address */ #define AUDIO__LPCG_EDMA0_BASE (0x595F0000u) /** Peripheral AUDIO__LPCG_EDMA0 base pointer */ #define AUDIO__LPCG_EDMA0 ((AUDIO_LPCG_EDMA0_Type *)AUDIO__LPCG_EDMA0_BASE) /** Array initializer of AUDIO_LPCG_EDMA0 peripheral base addresses */ #define AUDIO_LPCG_EDMA0_BASE_ADDRS { AUDIO__LPCG_EDMA0_BASE } /** Array initializer of AUDIO_LPCG_EDMA0 peripheral base pointers */ #define AUDIO_LPCG_EDMA0_BASE_PTRS { AUDIO__LPCG_EDMA0 } /*! * @} */ /* end of group AUDIO_LPCG_EDMA0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_EDMA1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_EDMA1_Peripheral_Access_Layer AUDIO_LPCG_EDMA1 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_EDMA1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_EDMA1_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_EDMA1_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_EDMA1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_EDMA1_Register_Masks AUDIO_LPCG_EDMA1 Register Masks * @{ */ /*! @name LPCG_LPCG_EDMA1_0 - na */ /*! @{ */ #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0_MASK) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN_MASK (0x2U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN_SHIFT (1U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN_MASK) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2_MASK) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP_MASK (0x8U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP_SHIFT (3U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP_MASK) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16_MASK (0x1FFF0U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16_SHIFT (4U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16_MASK) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN_MASK (0x20000U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN_SHIFT (17U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN_MASK) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18_MASK) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP_MASK (0x80000U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP_SHIFT (19U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP_MASK) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_24_MASK (0x1F00000U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_24_SHIFT (20U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_24(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_24_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_24_MASK) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_SWEN_MASK (0x2000000U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_SWEN_SHIFT (25U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_SWEN_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_SWEN_MASK) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_26_26_MASK (0x4000000U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_26_26_SHIFT (26U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_26_26_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_26_26_MASK) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_STOP_MASK (0x8000000U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_STOP_SHIFT (27U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_STOP_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_STOP_MASK) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_28_31_MASK (0xF0000000U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_28_31_SHIFT (28U) #define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_28_31_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_28_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_EDMA1_Register_Masks */ /* AUDIO_LPCG_EDMA1 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_EDMA1 base address */ #define AUDIO__LPCG_EDMA1_BASE (0x59DF0000u) /** Peripheral AUDIO__LPCG_EDMA1 base pointer */ #define AUDIO__LPCG_EDMA1 ((AUDIO_LPCG_EDMA1_Type *)AUDIO__LPCG_EDMA1_BASE) /** Array initializer of AUDIO_LPCG_EDMA1 peripheral base addresses */ #define AUDIO_LPCG_EDMA1_BASE_ADDRS { AUDIO__LPCG_EDMA1_BASE } /** Array initializer of AUDIO_LPCG_EDMA1 peripheral base pointers */ #define AUDIO_LPCG_EDMA1_BASE_PTRS { AUDIO__LPCG_EDMA1 } /*! * @} */ /* end of group AUDIO_LPCG_EDMA1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_ESAI0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_ESAI0_Peripheral_Access_Layer AUDIO_LPCG_ESAI0 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_ESAI0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_ESAI0_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_ESAI0_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_ESAI0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_ESAI0_Register_Masks AUDIO_LPCG_ESAI0 Register Masks * @{ */ /*! @name LPCG_LPCG_ESAI0_0 - na */ /*! @{ */ #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN_MASK (0x1U) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN_SHIFT (0U) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN_MASK) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN_MASK (0x2U) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN_SHIFT (1U) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN_MASK) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2_MASK) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP_MASK (0x8U) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP_SHIFT (3U) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP_MASK) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_16_MASK (0x1FFF0U) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_16_SHIFT (4U) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_16_MASK) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN_MASK (0x20000U) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN_SHIFT (17U) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN_SHIFT)) & AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN_MASK) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18_MASK) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP_MASK (0x80000U) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP_SHIFT (19U) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP_SHIFT)) & AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP_MASK) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31_MASK (0xFFF00000U) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31_SHIFT (20U) #define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_ESAI0_Register_Masks */ /* AUDIO_LPCG_ESAI0 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_ESAI0 base address */ #define AUDIO__LPCG_ESAI0_BASE (0x59410000u) /** Peripheral AUDIO__LPCG_ESAI0 base pointer */ #define AUDIO__LPCG_ESAI0 ((AUDIO_LPCG_ESAI0_Type *)AUDIO__LPCG_ESAI0_BASE) /** Array initializer of AUDIO_LPCG_ESAI0 peripheral base addresses */ #define AUDIO_LPCG_ESAI0_BASE_ADDRS { AUDIO__LPCG_ESAI0_BASE } /** Array initializer of AUDIO_LPCG_ESAI0 peripheral base pointers */ #define AUDIO_LPCG_ESAI0_BASE_PTRS { AUDIO__LPCG_ESAI0 } /*! * @} */ /* end of group AUDIO_LPCG_ESAI0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_ESAI1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_ESAI1_Peripheral_Access_Layer AUDIO_LPCG_ESAI1 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_ESAI1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_ESAI1_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_ESAI1_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_ESAI1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_ESAI1_Register_Masks AUDIO_LPCG_ESAI1 Register Masks * @{ */ /*! @name LPCG_LPCG_ESAI1_0 - na */ /*! @{ */ #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_HWEN_MASK (0x1U) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_HWEN_SHIFT (0U) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_HWEN_MASK) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_SWEN_MASK (0x2U) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_SWEN_SHIFT (1U) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_SWEN_MASK) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_2_2_MASK) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_STOP_MASK (0x8U) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_STOP_SHIFT (3U) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_STOP_MASK) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_4_16_MASK (0x1FFF0U) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_4_16_SHIFT (4U) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_4_16_MASK) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_SWEN_MASK (0x20000U) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_SWEN_SHIFT (17U) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_SWEN_SHIFT)) & AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_SWEN_MASK) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_18_18_MASK) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_STOP_MASK (0x80000U) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_STOP_SHIFT (19U) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_STOP_SHIFT)) & AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_STOP_MASK) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_20_31_MASK (0xFFF00000U) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_20_31_SHIFT (20U) #define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_ESAI1_Register_Masks */ /* AUDIO_LPCG_ESAI1 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_ESAI1 base address */ #define AUDIO__LPCG_ESAI1_BASE (0x59C10000u) /** Peripheral AUDIO__LPCG_ESAI1 base pointer */ #define AUDIO__LPCG_ESAI1 ((AUDIO_LPCG_ESAI1_Type *)AUDIO__LPCG_ESAI1_BASE) /** Array initializer of AUDIO_LPCG_ESAI1 peripheral base addresses */ #define AUDIO_LPCG_ESAI1_BASE_ADDRS { AUDIO__LPCG_ESAI1_BASE } /** Array initializer of AUDIO_LPCG_ESAI1 peripheral base pointers */ #define AUDIO_LPCG_ESAI1_BASE_PTRS { AUDIO__LPCG_ESAI1 } /*! * @} */ /* end of group AUDIO_LPCG_ESAI1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_GPT0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_GPT0_Peripheral_Access_Layer AUDIO_LPCG_GPT0 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_GPT0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_GPT0_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_GPT0_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_GPT0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_GPT0_Register_Masks AUDIO_LPCG_GPT0 Register Masks * @{ */ /*! @name LPCG_LPCG_GPT0_0 - na */ /*! @{ */ #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_HWEN_MASK (0x1U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_HWEN_SHIFT (0U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_HWEN_MASK) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_SWEN_MASK (0x2U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_SWEN_SHIFT (1U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_SWEN_MASK) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2_MASK) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_STOP_MASK (0x8U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_STOP_SHIFT (3U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_STOP_MASK) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_16_MASK (0x1FFF0U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_16_SHIFT (4U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_16_MASK) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN_MASK (0x20000U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN_SHIFT (17U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN_MASK) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18_MASK) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP_MASK (0x80000U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP_SHIFT (19U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP_MASK) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_20_MASK (0x100000U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_20_SHIFT (20U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_20_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_20_MASK) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_SWEN_MASK (0x200000U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_SWEN_SHIFT (21U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_SWEN_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_SWEN_MASK) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_22_22_MASK (0x400000U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_22_22_SHIFT (22U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_22_22_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_22_22_MASK) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_STOP_MASK (0x800000U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_STOP_SHIFT (23U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_STOP_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_STOP_MASK) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_24_31_MASK (0xFF000000U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_24_31_SHIFT (24U) #define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_24_31_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_GPT0_Register_Masks */ /* AUDIO_LPCG_GPT0 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_GPT0 base address */ #define AUDIO__LPCG_GPT0_BASE (0x594B0000u) /** Peripheral AUDIO__LPCG_GPT0 base pointer */ #define AUDIO__LPCG_GPT0 ((AUDIO_LPCG_GPT0_Type *)AUDIO__LPCG_GPT0_BASE) /** Array initializer of AUDIO_LPCG_GPT0 peripheral base addresses */ #define AUDIO_LPCG_GPT0_BASE_ADDRS { AUDIO__LPCG_GPT0_BASE } /** Array initializer of AUDIO_LPCG_GPT0 peripheral base pointers */ #define AUDIO_LPCG_GPT0_BASE_PTRS { AUDIO__LPCG_GPT0 } /*! * @} */ /* end of group AUDIO_LPCG_GPT0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_GPT1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_GPT1_Peripheral_Access_Layer AUDIO_LPCG_GPT1 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_GPT1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_GPT1_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_GPT1_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_GPT1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_GPT1_Register_Masks AUDIO_LPCG_GPT1 Register Masks * @{ */ /*! @name LPCG_LPCG_GPT1_0 - na */ /*! @{ */ #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_HWEN_MASK (0x1U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_HWEN_SHIFT (0U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_HWEN_MASK) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_SWEN_MASK (0x2U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_SWEN_SHIFT (1U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_SWEN_MASK) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2_MASK) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_STOP_MASK (0x8U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_STOP_SHIFT (3U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_STOP_MASK) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_16_MASK (0x1FFF0U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_16_SHIFT (4U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_16_MASK) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN_MASK (0x20000U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN_SHIFT (17U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN_MASK) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18_MASK) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP_MASK (0x80000U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP_SHIFT (19U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP_MASK) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_20_MASK (0x100000U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_20_SHIFT (20U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_20_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_20_MASK) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_SWEN_MASK (0x200000U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_SWEN_SHIFT (21U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_SWEN_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_SWEN_MASK) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_22_22_MASK (0x400000U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_22_22_SHIFT (22U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_22_22_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_22_22_MASK) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_STOP_MASK (0x800000U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_STOP_SHIFT (23U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_STOP_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_STOP_MASK) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_24_31_MASK (0xFF000000U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_24_31_SHIFT (24U) #define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_24_31_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_GPT1_Register_Masks */ /* AUDIO_LPCG_GPT1 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_GPT1 base address */ #define AUDIO__LPCG_GPT1_BASE (0x594C0000u) /** Peripheral AUDIO__LPCG_GPT1 base pointer */ #define AUDIO__LPCG_GPT1 ((AUDIO_LPCG_GPT1_Type *)AUDIO__LPCG_GPT1_BASE) /** Array initializer of AUDIO_LPCG_GPT1 peripheral base addresses */ #define AUDIO_LPCG_GPT1_BASE_ADDRS { AUDIO__LPCG_GPT1_BASE } /** Array initializer of AUDIO_LPCG_GPT1 peripheral base pointers */ #define AUDIO_LPCG_GPT1_BASE_PTRS { AUDIO__LPCG_GPT1 } /*! * @} */ /* end of group AUDIO_LPCG_GPT1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_GPT2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_GPT2_Peripheral_Access_Layer AUDIO_LPCG_GPT2 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_GPT2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_GPT2_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_GPT2_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_GPT2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_GPT2_Register_Masks AUDIO_LPCG_GPT2 Register Masks * @{ */ /*! @name LPCG_LPCG_GPT2_0 - na */ /*! @{ */ #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_HWEN_MASK (0x1U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_HWEN_SHIFT (0U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_HWEN_MASK) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_SWEN_MASK (0x2U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_SWEN_SHIFT (1U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_SWEN_MASK) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2_MASK) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_STOP_MASK (0x8U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_STOP_SHIFT (3U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_STOP_MASK) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_16_MASK (0x1FFF0U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_16_SHIFT (4U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_16_MASK) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN_MASK (0x20000U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN_SHIFT (17U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN_MASK) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18_MASK) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP_MASK (0x80000U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP_SHIFT (19U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP_MASK) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_20_MASK (0x100000U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_20_SHIFT (20U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_20_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_20_MASK) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_SWEN_MASK (0x200000U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_SWEN_SHIFT (21U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_SWEN_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_SWEN_MASK) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_22_22_MASK (0x400000U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_22_22_SHIFT (22U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_22_22_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_22_22_MASK) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_STOP_MASK (0x800000U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_STOP_SHIFT (23U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_STOP_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_STOP_MASK) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_24_31_MASK (0xFF000000U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_24_31_SHIFT (24U) #define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_24_31_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_GPT2_Register_Masks */ /* AUDIO_LPCG_GPT2 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_GPT2 base address */ #define AUDIO__LPCG_GPT2_BASE (0x594D0000u) /** Peripheral AUDIO__LPCG_GPT2 base pointer */ #define AUDIO__LPCG_GPT2 ((AUDIO_LPCG_GPT2_Type *)AUDIO__LPCG_GPT2_BASE) /** Array initializer of AUDIO_LPCG_GPT2 peripheral base addresses */ #define AUDIO_LPCG_GPT2_BASE_ADDRS { AUDIO__LPCG_GPT2_BASE } /** Array initializer of AUDIO_LPCG_GPT2 peripheral base pointers */ #define AUDIO_LPCG_GPT2_BASE_PTRS { AUDIO__LPCG_GPT2 } /*! * @} */ /* end of group AUDIO_LPCG_GPT2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_GPT3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_GPT3_Peripheral_Access_Layer AUDIO_LPCG_GPT3 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_GPT3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_GPT3_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_GPT3_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_GPT3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_GPT3_Register_Masks AUDIO_LPCG_GPT3 Register Masks * @{ */ /*! @name LPCG_LPCG_GPT3_0 - na */ /*! @{ */ #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_HWEN_MASK (0x1U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_HWEN_SHIFT (0U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_HWEN_MASK) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_SWEN_MASK (0x2U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_SWEN_SHIFT (1U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_SWEN_MASK) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2_MASK) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_STOP_MASK (0x8U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_STOP_SHIFT (3U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_STOP_MASK) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_16_MASK (0x1FFF0U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_16_SHIFT (4U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_16_MASK) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN_MASK (0x20000U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN_SHIFT (17U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN_MASK) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18_MASK) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP_MASK (0x80000U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP_SHIFT (19U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP_MASK) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_20_MASK (0x100000U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_20_SHIFT (20U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_20_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_20_MASK) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_SWEN_MASK (0x200000U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_SWEN_SHIFT (21U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_SWEN_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_SWEN_MASK) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_22_22_MASK (0x400000U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_22_22_SHIFT (22U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_22_22_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_22_22_MASK) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_STOP_MASK (0x800000U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_STOP_SHIFT (23U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_STOP_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_STOP_MASK) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_24_31_MASK (0xFF000000U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_24_31_SHIFT (24U) #define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_24_31_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_GPT3_Register_Masks */ /* AUDIO_LPCG_GPT3 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_GPT3 base address */ #define AUDIO__LPCG_GPT3_BASE (0x594E0000u) /** Peripheral AUDIO__LPCG_GPT3 base pointer */ #define AUDIO__LPCG_GPT3 ((AUDIO_LPCG_GPT3_Type *)AUDIO__LPCG_GPT3_BASE) /** Array initializer of AUDIO_LPCG_GPT3 peripheral base addresses */ #define AUDIO_LPCG_GPT3_BASE_ADDRS { AUDIO__LPCG_GPT3_BASE } /** Array initializer of AUDIO_LPCG_GPT3 peripheral base pointers */ #define AUDIO_LPCG_GPT3_BASE_PTRS { AUDIO__LPCG_GPT3 } /*! * @} */ /* end of group AUDIO_LPCG_GPT3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_GPT4 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_GPT4_Peripheral_Access_Layer AUDIO_LPCG_GPT4 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_GPT4 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_GPT4_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_GPT4_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_GPT4 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_GPT4_Register_Masks AUDIO_LPCG_GPT4 Register Masks * @{ */ /*! @name LPCG_LPCG_GPT4_0 - na */ /*! @{ */ #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_HWEN_MASK (0x1U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_HWEN_SHIFT (0U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_HWEN_MASK) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_SWEN_MASK (0x2U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_SWEN_SHIFT (1U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_SWEN_MASK) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2_MASK) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_STOP_MASK (0x8U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_STOP_SHIFT (3U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_STOP_MASK) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_16_MASK (0x1FFF0U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_16_SHIFT (4U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_16_MASK) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN_MASK (0x20000U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN_SHIFT (17U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN_MASK) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18_MASK) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP_MASK (0x80000U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP_SHIFT (19U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP_MASK) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_20_MASK (0x100000U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_20_SHIFT (20U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_20_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_20_MASK) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_SWEN_MASK (0x200000U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_SWEN_SHIFT (21U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_SWEN_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_SWEN_MASK) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_22_22_MASK (0x400000U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_22_22_SHIFT (22U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_22_22_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_22_22_MASK) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_STOP_MASK (0x800000U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_STOP_SHIFT (23U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_STOP_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_STOP_MASK) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_24_31_MASK (0xFF000000U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_24_31_SHIFT (24U) #define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_24_31_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_GPT4_Register_Masks */ /* AUDIO_LPCG_GPT4 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_GPT4 base address */ #define AUDIO__LPCG_GPT4_BASE (0x594F0000u) /** Peripheral AUDIO__LPCG_GPT4 base pointer */ #define AUDIO__LPCG_GPT4 ((AUDIO_LPCG_GPT4_Type *)AUDIO__LPCG_GPT4_BASE) /** Array initializer of AUDIO_LPCG_GPT4 peripheral base addresses */ #define AUDIO_LPCG_GPT4_BASE_ADDRS { AUDIO__LPCG_GPT4_BASE } /** Array initializer of AUDIO_LPCG_GPT4 peripheral base pointers */ #define AUDIO_LPCG_GPT4_BASE_PTRS { AUDIO__LPCG_GPT4 } /*! * @} */ /* end of group AUDIO_LPCG_GPT4_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_GPT5 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_GPT5_Peripheral_Access_Layer AUDIO_LPCG_GPT5 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_GPT5 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_GPT5_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_GPT5_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_GPT5 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_GPT5_Register_Masks AUDIO_LPCG_GPT5 Register Masks * @{ */ /*! @name LPCG_LPCG_GPT5_0 - na */ /*! @{ */ #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_HWEN_MASK (0x1U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_HWEN_SHIFT (0U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_HWEN_MASK) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_SWEN_MASK (0x2U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_SWEN_SHIFT (1U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_SWEN_MASK) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2_MASK) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_STOP_MASK (0x8U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_STOP_SHIFT (3U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_STOP_MASK) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_16_MASK (0x1FFF0U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_16_SHIFT (4U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_16_MASK) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN_MASK (0x20000U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN_SHIFT (17U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN_MASK) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18_MASK) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP_MASK (0x80000U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP_SHIFT (19U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP_MASK) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_20_MASK (0x100000U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_20_SHIFT (20U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_20_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_20_MASK) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_SWEN_MASK (0x200000U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_SWEN_SHIFT (21U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_SWEN_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_SWEN_MASK) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_22_22_MASK (0x400000U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_22_22_SHIFT (22U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_22_22_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_22_22_MASK) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_STOP_MASK (0x800000U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_STOP_SHIFT (23U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_STOP_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_STOP_MASK) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_24_31_MASK (0xFF000000U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_24_31_SHIFT (24U) #define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_24_31_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_GPT5_Register_Masks */ /* AUDIO_LPCG_GPT5 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_GPT5 base address */ #define AUDIO__LPCG_GPT5_BASE (0x59500000u) /** Peripheral AUDIO__LPCG_GPT5 base pointer */ #define AUDIO__LPCG_GPT5 ((AUDIO_LPCG_GPT5_Type *)AUDIO__LPCG_GPT5_BASE) /** Array initializer of AUDIO_LPCG_GPT5 peripheral base addresses */ #define AUDIO_LPCG_GPT5_BASE_ADDRS { AUDIO__LPCG_GPT5_BASE } /** Array initializer of AUDIO_LPCG_GPT5 peripheral base pointers */ #define AUDIO_LPCG_GPT5_BASE_PTRS { AUDIO__LPCG_GPT5 } /*! * @} */ /* end of group AUDIO_LPCG_GPT5_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_MCLKOUT0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_MCLKOUT0_Peripheral_Access_Layer AUDIO_LPCG_MCLKOUT0 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_MCLKOUT0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_MCLKOUT0_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_MCLKOUT0_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_MCLKOUT0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_MCLKOUT0_Register_Masks AUDIO_LPCG_MCLKOUT0 Register Masks * @{ */ /*! @name LPCG_LPCG_MCLKOUT0_0 - na */ /*! @{ */ #define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0_MASK) #define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN_MASK (0x2U) #define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN_SHIFT (1U) #define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN_SHIFT)) & AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN_MASK) #define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2_MASK) #define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP_MASK (0x8U) #define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP_SHIFT (3U) #define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP_SHIFT)) & AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP_MASK) #define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31_MASK (0xFFFFFFF0U) #define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31_SHIFT (4U) #define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31_SHIFT)) & AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_MCLKOUT0_Register_Masks */ /* AUDIO_LPCG_MCLKOUT0 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_MCLKOUT0 base address */ #define AUDIO__LPCG_MCLKOUT0_BASE (0x59D50000u) /** Peripheral AUDIO__LPCG_MCLKOUT0 base pointer */ #define AUDIO__LPCG_MCLKOUT0 ((AUDIO_LPCG_MCLKOUT0_Type *)AUDIO__LPCG_MCLKOUT0_BASE) /** Array initializer of AUDIO_LPCG_MCLKOUT0 peripheral base addresses */ #define AUDIO_LPCG_MCLKOUT0_BASE_ADDRS { AUDIO__LPCG_MCLKOUT0_BASE } /** Array initializer of AUDIO_LPCG_MCLKOUT0 peripheral base pointers */ #define AUDIO_LPCG_MCLKOUT0_BASE_PTRS { AUDIO__LPCG_MCLKOUT0 } /*! * @} */ /* end of group AUDIO_LPCG_MCLKOUT0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_MCLKOUT1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_MCLKOUT1_Peripheral_Access_Layer AUDIO_LPCG_MCLKOUT1 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_MCLKOUT1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_MCLKOUT1_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_MCLKOUT1_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_MCLKOUT1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_MCLKOUT1_Register_Masks AUDIO_LPCG_MCLKOUT1 Register Masks * @{ */ /*! @name LPCG_LPCG_MCLKOUT1_0 - na */ /*! @{ */ #define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0_MASK) #define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN_MASK (0x2U) #define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN_SHIFT (1U) #define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN_SHIFT)) & AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN_MASK) #define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2_MASK) #define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP_MASK (0x8U) #define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP_SHIFT (3U) #define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP_SHIFT)) & AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP_MASK) #define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31_MASK (0xFFFFFFF0U) #define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31_SHIFT (4U) #define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31_SHIFT)) & AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_MCLKOUT1_Register_Masks */ /* AUDIO_LPCG_MCLKOUT1 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_MCLKOUT1 base address */ #define AUDIO__LPCG_MCLKOUT1_BASE (0x59D60000u) /** Peripheral AUDIO__LPCG_MCLKOUT1 base pointer */ #define AUDIO__LPCG_MCLKOUT1 ((AUDIO_LPCG_MCLKOUT1_Type *)AUDIO__LPCG_MCLKOUT1_BASE) /** Array initializer of AUDIO_LPCG_MCLKOUT1 peripheral base addresses */ #define AUDIO_LPCG_MCLKOUT1_BASE_ADDRS { AUDIO__LPCG_MCLKOUT1_BASE } /** Array initializer of AUDIO_LPCG_MCLKOUT1 peripheral base pointers */ #define AUDIO_LPCG_MCLKOUT1_BASE_PTRS { AUDIO__LPCG_MCLKOUT1 } /*! * @} */ /* end of group AUDIO_LPCG_MCLKOUT1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_MQS_REGS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_MQS_REGS_Peripheral_Access_Layer AUDIO_LPCG_MQS_REGS Peripheral Access Layer * @{ */ /** AUDIO_LPCG_MQS_REGS - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_MQS_REGS_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_MQS_REGS_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_MQS_REGS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_MQS_REGS_Register_Masks AUDIO_LPCG_MQS_REGS Register Masks * @{ */ /*! @name LPCG_LPCG_MQS_REGS_0 - na */ /*! @{ */ #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN_MASK (0x1U) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN_SHIFT (0U) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN_SHIFT)) & AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN_MASK) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN_MASK (0x2U) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN_SHIFT (1U) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN_MASK) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2_MASK) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP_MASK (0x8U) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP_SHIFT (3U) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP_MASK) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_16_MASK (0x1FFF0U) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_16_SHIFT (4U) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_16_MASK) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN_MASK (0x20000U) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN_SHIFT (17U) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN_SHIFT)) & AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN_MASK) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18_MASK) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP_MASK (0x80000U) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP_SHIFT (19U) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP_SHIFT)) & AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP_MASK) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31_MASK (0xFFF00000U) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31_SHIFT (20U) #define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_MQS_REGS_Register_Masks */ /* AUDIO_LPCG_MQS_REGS - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_MQS_REGS base address */ #define AUDIO__LPCG_MQS_REGS_BASE (0x59C50000u) /** Peripheral AUDIO__LPCG_MQS_REGS base pointer */ #define AUDIO__LPCG_MQS_REGS ((AUDIO_LPCG_MQS_REGS_Type *)AUDIO__LPCG_MQS_REGS_BASE) /** Array initializer of AUDIO_LPCG_MQS_REGS peripheral base addresses */ #define AUDIO_LPCG_MQS_REGS_BASE_ADDRS { AUDIO__LPCG_MQS_REGS_BASE } /** Array initializer of AUDIO_LPCG_MQS_REGS peripheral base pointers */ #define AUDIO_LPCG_MQS_REGS_BASE_PTRS { AUDIO__LPCG_MQS_REGS } /*! * @} */ /* end of group AUDIO_LPCG_MQS_REGS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SAI0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SAI0_Peripheral_Access_Layer AUDIO_LPCG_SAI0 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_SAI0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SAI0_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_SAI0_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SAI0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SAI0_Register_Masks AUDIO_LPCG_SAI0 Register Masks * @{ */ /*! @name LPCG_LPCG_SAI0_0 - na */ /*! @{ */ #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0_MASK) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN_MASK (0x2U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN_SHIFT (1U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN_MASK) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2_MASK) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP_MASK (0x8U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP_SHIFT (3U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP_MASK) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_7_MASK (0xF0U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_7_SHIFT (4U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_7(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_7_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_7_MASK) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN_MASK (0x100U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN_SHIFT (8U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN_MASK) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_SWEN_MASK (0x200U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_SWEN_SHIFT (9U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_SWEN_MASK) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_10_10_MASK (0x400U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_10_10_SHIFT (10U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_10_10_MASK) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_STOP_MASK (0x800U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_STOP_SHIFT (11U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_STOP_MASK) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_12_16_MASK (0x1F000U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_12_16_SHIFT (12U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_12_16_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_12_16_MASK) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN_MASK (0x20000U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN_SHIFT (17U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN_MASK) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18_MASK) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP_MASK (0x80000U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP_SHIFT (19U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP_MASK) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31_MASK (0xFFF00000U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31_SHIFT (20U) #define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_SAI0_Register_Masks */ /* AUDIO_LPCG_SAI0 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_SAI0 base address */ #define AUDIO__LPCG_SAI0_BASE (0x59440000u) /** Peripheral AUDIO__LPCG_SAI0 base pointer */ #define AUDIO__LPCG_SAI0 ((AUDIO_LPCG_SAI0_Type *)AUDIO__LPCG_SAI0_BASE) /** Array initializer of AUDIO_LPCG_SAI0 peripheral base addresses */ #define AUDIO_LPCG_SAI0_BASE_ADDRS { AUDIO__LPCG_SAI0_BASE } /** Array initializer of AUDIO_LPCG_SAI0 peripheral base pointers */ #define AUDIO_LPCG_SAI0_BASE_PTRS { AUDIO__LPCG_SAI0 } /*! * @} */ /* end of group AUDIO_LPCG_SAI0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SAI1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SAI1_Peripheral_Access_Layer AUDIO_LPCG_SAI1 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_SAI1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SAI1_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_SAI1_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SAI1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SAI1_Register_Masks AUDIO_LPCG_SAI1 Register Masks * @{ */ /*! @name LPCG_LPCG_SAI1_0 - na */ /*! @{ */ #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0_MASK) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN_MASK (0x2U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN_SHIFT (1U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN_MASK) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2_MASK) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP_MASK (0x8U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP_SHIFT (3U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP_MASK) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_7_MASK (0xF0U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_7_SHIFT (4U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_7(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_7_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_7_MASK) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN_MASK (0x100U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN_SHIFT (8U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN_MASK) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_SWEN_MASK (0x200U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_SWEN_SHIFT (9U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_SWEN_MASK) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_10_10_MASK (0x400U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_10_10_SHIFT (10U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_10_10_MASK) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_STOP_MASK (0x800U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_STOP_SHIFT (11U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_STOP_MASK) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_12_16_MASK (0x1F000U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_12_16_SHIFT (12U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_12_16_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_12_16_MASK) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN_MASK (0x20000U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN_SHIFT (17U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN_MASK) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18_MASK) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP_MASK (0x80000U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP_SHIFT (19U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP_MASK) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31_MASK (0xFFF00000U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31_SHIFT (20U) #define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_SAI1_Register_Masks */ /* AUDIO_LPCG_SAI1 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_SAI1 base address */ #define AUDIO__LPCG_SAI1_BASE (0x59450000u) /** Peripheral AUDIO__LPCG_SAI1 base pointer */ #define AUDIO__LPCG_SAI1 ((AUDIO_LPCG_SAI1_Type *)AUDIO__LPCG_SAI1_BASE) /** Array initializer of AUDIO_LPCG_SAI1 peripheral base addresses */ #define AUDIO_LPCG_SAI1_BASE_ADDRS { AUDIO__LPCG_SAI1_BASE } /** Array initializer of AUDIO_LPCG_SAI1 peripheral base pointers */ #define AUDIO_LPCG_SAI1_BASE_PTRS { AUDIO__LPCG_SAI1 } /*! * @} */ /* end of group AUDIO_LPCG_SAI1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SAI2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SAI2_Peripheral_Access_Layer AUDIO_LPCG_SAI2 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_SAI2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SAI2_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_SAI2_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SAI2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SAI2_Register_Masks AUDIO_LPCG_SAI2 Register Masks * @{ */ /*! @name LPCG_LPCG_SAI2_0 - na */ /*! @{ */ #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0_MASK) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN_MASK (0x2U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN_SHIFT (1U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN_MASK) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2_MASK) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP_MASK (0x8U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP_SHIFT (3U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP_MASK) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_7_MASK (0xF0U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_7_SHIFT (4U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_7(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_7_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_7_MASK) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN_MASK (0x100U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN_SHIFT (8U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN_MASK) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_SWEN_MASK (0x200U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_SWEN_SHIFT (9U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_SWEN_MASK) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_10_10_MASK (0x400U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_10_10_SHIFT (10U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_10_10_MASK) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_STOP_MASK (0x800U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_STOP_SHIFT (11U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_STOP_MASK) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_12_16_MASK (0x1F000U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_12_16_SHIFT (12U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_12_16_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_12_16_MASK) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN_MASK (0x20000U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN_SHIFT (17U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN_MASK) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18_MASK) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP_MASK (0x80000U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP_SHIFT (19U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP_MASK) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31_MASK (0xFFF00000U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31_SHIFT (20U) #define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_SAI2_Register_Masks */ /* AUDIO_LPCG_SAI2 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_SAI2 base address */ #define AUDIO__LPCG_SAI2_BASE (0x59460000u) /** Peripheral AUDIO__LPCG_SAI2 base pointer */ #define AUDIO__LPCG_SAI2 ((AUDIO_LPCG_SAI2_Type *)AUDIO__LPCG_SAI2_BASE) /** Array initializer of AUDIO_LPCG_SAI2 peripheral base addresses */ #define AUDIO_LPCG_SAI2_BASE_ADDRS { AUDIO__LPCG_SAI2_BASE } /** Array initializer of AUDIO_LPCG_SAI2 peripheral base pointers */ #define AUDIO_LPCG_SAI2_BASE_PTRS { AUDIO__LPCG_SAI2 } /*! * @} */ /* end of group AUDIO_LPCG_SAI2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SAI3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SAI3_Peripheral_Access_Layer AUDIO_LPCG_SAI3 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_SAI3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SAI3_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_SAI3_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SAI3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SAI3_Register_Masks AUDIO_LPCG_SAI3 Register Masks * @{ */ /*! @name LPCG_LPCG_SAI3_0 - na */ /*! @{ */ #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0_MASK) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN_MASK (0x2U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN_SHIFT (1U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN_MASK) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2_MASK) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP_MASK (0x8U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP_SHIFT (3U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP_MASK) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_7_MASK (0xF0U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_7_SHIFT (4U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_7(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_7_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_7_MASK) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN_MASK (0x100U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN_SHIFT (8U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN_MASK) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_SWEN_MASK (0x200U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_SWEN_SHIFT (9U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_SWEN_MASK) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_10_10_MASK (0x400U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_10_10_SHIFT (10U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_10_10_MASK) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_STOP_MASK (0x800U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_STOP_SHIFT (11U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_STOP_MASK) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_12_16_MASK (0x1F000U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_12_16_SHIFT (12U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_12_16_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_12_16_MASK) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN_MASK (0x20000U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN_SHIFT (17U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN_MASK) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18_MASK) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP_MASK (0x80000U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP_SHIFT (19U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP_MASK) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31_MASK (0xFFF00000U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31_SHIFT (20U) #define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_SAI3_Register_Masks */ /* AUDIO_LPCG_SAI3 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_SAI3 base address */ #define AUDIO__LPCG_SAI3_BASE (0x59470000u) /** Peripheral AUDIO__LPCG_SAI3 base pointer */ #define AUDIO__LPCG_SAI3 ((AUDIO_LPCG_SAI3_Type *)AUDIO__LPCG_SAI3_BASE) /** Array initializer of AUDIO_LPCG_SAI3 peripheral base addresses */ #define AUDIO_LPCG_SAI3_BASE_ADDRS { AUDIO__LPCG_SAI3_BASE } /** Array initializer of AUDIO_LPCG_SAI3 peripheral base pointers */ #define AUDIO_LPCG_SAI3_BASE_PTRS { AUDIO__LPCG_SAI3 } /*! * @} */ /* end of group AUDIO_LPCG_SAI3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SAI6 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SAI6_Peripheral_Access_Layer AUDIO_LPCG_SAI6 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_SAI6 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SAI6_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_SAI6_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SAI6 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SAI6_Register_Masks AUDIO_LPCG_SAI6 Register Masks * @{ */ /*! @name LPCG_LPCG_SAI6_0 - na */ /*! @{ */ #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_0_0_MASK) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_SWEN_MASK (0x2U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_SWEN_SHIFT (1U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_SWEN_MASK) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_2_2_MASK) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_STOP_MASK (0x8U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_STOP_SHIFT (3U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_STOP_MASK) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_4_7_MASK (0xF0U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_4_7_SHIFT (4U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_4_7(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_4_7_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_4_7_MASK) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_HWEN_MASK (0x100U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_HWEN_SHIFT (8U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_HWEN_MASK) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_SWEN_MASK (0x200U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_SWEN_SHIFT (9U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_SWEN_MASK) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_10_10_MASK (0x400U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_10_10_SHIFT (10U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_10_10_MASK) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_STOP_MASK (0x800U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_STOP_SHIFT (11U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_STOP_MASK) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_12_16_MASK (0x1F000U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_12_16_SHIFT (12U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_12_16_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_12_16_MASK) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_SWEN_MASK (0x20000U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_SWEN_SHIFT (17U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_SWEN_MASK) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_18_18_MASK) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_STOP_MASK (0x80000U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_STOP_SHIFT (19U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_STOP_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_STOP_MASK) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_20_31_MASK (0xFFF00000U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_20_31_SHIFT (20U) #define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_SAI6_Register_Masks */ /* AUDIO_LPCG_SAI6 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_SAI6 base address */ #define AUDIO__LPCG_SAI6_BASE (0x59C20000u) /** Peripheral AUDIO__LPCG_SAI6 base pointer */ #define AUDIO__LPCG_SAI6 ((AUDIO_LPCG_SAI6_Type *)AUDIO__LPCG_SAI6_BASE) /** Array initializer of AUDIO_LPCG_SAI6 peripheral base addresses */ #define AUDIO_LPCG_SAI6_BASE_ADDRS { AUDIO__LPCG_SAI6_BASE } /** Array initializer of AUDIO_LPCG_SAI6 peripheral base pointers */ #define AUDIO_LPCG_SAI6_BASE_PTRS { AUDIO__LPCG_SAI6 } /*! * @} */ /* end of group AUDIO_LPCG_SAI6_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SAI7 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SAI7_Peripheral_Access_Layer AUDIO_LPCG_SAI7 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_SAI7 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SAI7_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_SAI7_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SAI7 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SAI7_Register_Masks AUDIO_LPCG_SAI7 Register Masks * @{ */ /*! @name LPCG_LPCG_SAI7_0 - na */ /*! @{ */ #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_0_0_MASK) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_SWEN_MASK (0x2U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_SWEN_SHIFT (1U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_SWEN_MASK) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_2_2_MASK) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_STOP_MASK (0x8U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_STOP_SHIFT (3U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_STOP_MASK) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_4_7_MASK (0xF0U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_4_7_SHIFT (4U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_4_7(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_4_7_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_4_7_MASK) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_HWEN_MASK (0x100U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_HWEN_SHIFT (8U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_HWEN_MASK) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_SWEN_MASK (0x200U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_SWEN_SHIFT (9U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_SWEN_MASK) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_10_10_MASK (0x400U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_10_10_SHIFT (10U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_10_10_MASK) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_STOP_MASK (0x800U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_STOP_SHIFT (11U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_STOP_MASK) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_12_16_MASK (0x1F000U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_12_16_SHIFT (12U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_12_16_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_12_16_MASK) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_SWEN_MASK (0x20000U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_SWEN_SHIFT (17U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_SWEN_MASK) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_18_18_MASK) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_STOP_MASK (0x80000U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_STOP_SHIFT (19U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_STOP_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_STOP_MASK) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_20_31_MASK (0xFFF00000U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_20_31_SHIFT (20U) #define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_SAI7_Register_Masks */ /* AUDIO_LPCG_SAI7 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_SAI7 base address */ #define AUDIO__LPCG_SAI7_BASE (0x59C30000u) /** Peripheral AUDIO__LPCG_SAI7 base pointer */ #define AUDIO__LPCG_SAI7 ((AUDIO_LPCG_SAI7_Type *)AUDIO__LPCG_SAI7_BASE) /** Array initializer of AUDIO_LPCG_SAI7 peripheral base addresses */ #define AUDIO_LPCG_SAI7_BASE_ADDRS { AUDIO__LPCG_SAI7_BASE } /** Array initializer of AUDIO_LPCG_SAI7 peripheral base pointers */ #define AUDIO_LPCG_SAI7_BASE_PTRS { AUDIO__LPCG_SAI7 } /*! * @} */ /* end of group AUDIO_LPCG_SAI7_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SAI_HDMIRX0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SAI_HDMIRX0_Peripheral_Access_Layer AUDIO_LPCG_SAI_HDMIRX0 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_SAI_HDMIRX0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SAI_HDMIRX0_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_SAI_HDMIRX0_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SAI_HDMIRX0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SAI_HDMIRX0_Register_Masks AUDIO_LPCG_SAI_HDMIRX0 Register Masks * @{ */ /*! @name LPCG_LPCG_SAI_HDMIRX0_0 - na */ /*! @{ */ #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_0_0_MASK) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_SWEN_MASK (0x2U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_SWEN_SHIFT (1U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_SWEN_MASK) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_2_2_MASK) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_STOP_MASK (0x8U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_STOP_SHIFT (3U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_STOP_MASK) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_4_7_MASK (0xF0U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_4_7_SHIFT (4U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_4_7(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_4_7_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_4_7_MASK) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_HWEN_MASK (0x100U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_HWEN_SHIFT (8U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_HWEN_MASK) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_SWEN_MASK (0x200U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_SWEN_SHIFT (9U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_SWEN_MASK) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_10_10_MASK (0x400U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_10_10_SHIFT (10U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_10_10_MASK) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_STOP_MASK (0x800U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_STOP_SHIFT (11U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_STOP_MASK) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_12_16_MASK (0x1F000U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_12_16_SHIFT (12U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_12_16_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_12_16_MASK) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_SWEN_MASK (0x20000U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_SWEN_SHIFT (17U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_SWEN_MASK) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_18_18_MASK) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_STOP_MASK (0x80000U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_STOP_SHIFT (19U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_STOP_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_STOP_MASK) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_20_31_MASK (0xFFF00000U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_20_31_SHIFT (20U) #define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_SAI_HDMIRX0_Register_Masks */ /* AUDIO_LPCG_SAI_HDMIRX0 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_SAI_HDMIRX0 base address */ #define AUDIO__LPCG_SAI_HDMIRX0_BASE (0x59480000u) /** Peripheral AUDIO__LPCG_SAI_HDMIRX0 base pointer */ #define AUDIO__LPCG_SAI_HDMIRX0 ((AUDIO_LPCG_SAI_HDMIRX0_Type *)AUDIO__LPCG_SAI_HDMIRX0_BASE) /** Array initializer of AUDIO_LPCG_SAI_HDMIRX0 peripheral base addresses */ #define AUDIO_LPCG_SAI_HDMIRX0_BASE_ADDRS { AUDIO__LPCG_SAI_HDMIRX0_BASE } /** Array initializer of AUDIO_LPCG_SAI_HDMIRX0 peripheral base pointers */ #define AUDIO_LPCG_SAI_HDMIRX0_BASE_PTRS { AUDIO__LPCG_SAI_HDMIRX0 } /*! * @} */ /* end of group AUDIO_LPCG_SAI_HDMIRX0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SAI_HDMITX0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SAI_HDMITX0_Peripheral_Access_Layer AUDIO_LPCG_SAI_HDMITX0 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_SAI_HDMITX0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SAI_HDMITX0_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_SAI_HDMITX0_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SAI_HDMITX0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SAI_HDMITX0_Register_Masks AUDIO_LPCG_SAI_HDMITX0 Register Masks * @{ */ /*! @name LPCG_LPCG_SAI_HDMITX0_0 - na */ /*! @{ */ #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_0_0_MASK (0x1U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_0_0_SHIFT (0U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_0_0_MASK) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_SWEN_MASK (0x2U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_SWEN_SHIFT (1U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_SWEN_MASK) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_2_2_MASK) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_STOP_MASK (0x8U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_STOP_SHIFT (3U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_STOP_MASK) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_4_7_MASK (0xF0U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_4_7_SHIFT (4U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_4_7(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_4_7_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_4_7_MASK) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_HWEN_MASK (0x100U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_HWEN_SHIFT (8U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_HWEN_MASK) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_SWEN_MASK (0x200U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_SWEN_SHIFT (9U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_SWEN_MASK) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_10_10_MASK (0x400U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_10_10_SHIFT (10U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_10_10_MASK) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_STOP_MASK (0x800U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_STOP_SHIFT (11U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_STOP_MASK) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_12_16_MASK (0x1F000U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_12_16_SHIFT (12U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_12_16_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_12_16_MASK) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_SWEN_MASK (0x20000U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_SWEN_SHIFT (17U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_SWEN_MASK) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_18_18_MASK) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_STOP_MASK (0x80000U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_STOP_SHIFT (19U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_STOP_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_STOP_MASK) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_20_31_MASK (0xFFF00000U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_20_31_SHIFT (20U) #define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_SAI_HDMITX0_Register_Masks */ /* AUDIO_LPCG_SAI_HDMITX0 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_SAI_HDMITX0 base address */ #define AUDIO__LPCG_SAI_HDMITX0_BASE (0x59490000u) /** Peripheral AUDIO__LPCG_SAI_HDMITX0 base pointer */ #define AUDIO__LPCG_SAI_HDMITX0 ((AUDIO_LPCG_SAI_HDMITX0_Type *)AUDIO__LPCG_SAI_HDMITX0_BASE) /** Array initializer of AUDIO_LPCG_SAI_HDMITX0 peripheral base addresses */ #define AUDIO_LPCG_SAI_HDMITX0_BASE_ADDRS { AUDIO__LPCG_SAI_HDMITX0_BASE } /** Array initializer of AUDIO_LPCG_SAI_HDMITX0 peripheral base pointers */ #define AUDIO_LPCG_SAI_HDMITX0_BASE_PTRS { AUDIO__LPCG_SAI_HDMITX0 } /*! * @} */ /* end of group AUDIO_LPCG_SAI_HDMITX0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SPDIF0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SPDIF0_Peripheral_Access_Layer AUDIO_LPCG_SPDIF0 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_SPDIF0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SPDIF0_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_SPDIF0_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SPDIF0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SPDIF0_Register_Masks AUDIO_LPCG_SPDIF0 Register Masks * @{ */ /*! @name LPCG_LPCG_SPDIF0_0 - na */ /*! @{ */ #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN_MASK (0x1U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN_SHIFT (0U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN_MASK) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN_MASK (0x2U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN_SHIFT (1U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN_MASK) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2_MASK) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP_MASK (0x8U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP_SHIFT (3U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP_MASK) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_16_MASK (0x1FFF0U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_16_SHIFT (4U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_16_MASK) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_SWEN_MASK (0x20000U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_SWEN_SHIFT (17U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_SWEN_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_SWEN_MASK) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18_MASK) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_STOP_MASK (0x80000U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_STOP_SHIFT (19U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_STOP_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_STOP_MASK) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_20_MASK (0x100000U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_20_SHIFT (20U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_20_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_20_MASK) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN_MASK (0x200000U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN_SHIFT (21U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN_MASK) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_22_22_MASK (0x400000U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_22_22_SHIFT (22U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_22_22_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_22_22_MASK) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP_MASK (0x800000U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP_SHIFT (23U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP_MASK) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_24_31_MASK (0xFF000000U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_24_31_SHIFT (24U) #define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_24_31_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_SPDIF0_Register_Masks */ /* AUDIO_LPCG_SPDIF0 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_SPDIF0 base address */ #define AUDIO__LPCG_SPDIF0_BASE (0x59420000u) /** Peripheral AUDIO__LPCG_SPDIF0 base pointer */ #define AUDIO__LPCG_SPDIF0 ((AUDIO_LPCG_SPDIF0_Type *)AUDIO__LPCG_SPDIF0_BASE) /** Array initializer of AUDIO_LPCG_SPDIF0 peripheral base addresses */ #define AUDIO_LPCG_SPDIF0_BASE_ADDRS { AUDIO__LPCG_SPDIF0_BASE } /** Array initializer of AUDIO_LPCG_SPDIF0 peripheral base pointers */ #define AUDIO_LPCG_SPDIF0_BASE_PTRS { AUDIO__LPCG_SPDIF0 } /*! * @} */ /* end of group AUDIO_LPCG_SPDIF0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SPDIF1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SPDIF1_Peripheral_Access_Layer AUDIO_LPCG_SPDIF1 Peripheral Access Layer * @{ */ /** AUDIO_LPCG_SPDIF1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SPDIF1_0; /**< na, offset: 0x0 */ } AUDIO_LPCG_SPDIF1_Type; /* ---------------------------------------------------------------------------- -- AUDIO_LPCG_SPDIF1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUDIO_LPCG_SPDIF1_Register_Masks AUDIO_LPCG_SPDIF1 Register Masks * @{ */ /*! @name LPCG_LPCG_SPDIF1_0 - na */ /*! @{ */ #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_HWEN_MASK (0x1U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_HWEN_SHIFT (0U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_HWEN_MASK) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_SWEN_MASK (0x2U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_SWEN_SHIFT (1U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_SWEN_MASK) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_2_2_MASK (0x4U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_2_2_SHIFT (2U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_2_2_MASK) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_STOP_MASK (0x8U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_STOP_SHIFT (3U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_STOP_MASK) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_4_16_MASK (0x1FFF0U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_4_16_SHIFT (4U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_4_16_MASK) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_SWEN_MASK (0x20000U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_SWEN_SHIFT (17U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_SWEN_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_SWEN_MASK) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_18_18_MASK (0x40000U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_18_18_SHIFT (18U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_18_18_MASK) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_STOP_MASK (0x80000U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_STOP_SHIFT (19U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_STOP_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_STOP_MASK) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_20_20_MASK (0x100000U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_20_20_SHIFT (20U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_20_20_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_20_20_MASK) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_SWEN_MASK (0x200000U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_SWEN_SHIFT (21U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_SWEN_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_SWEN_MASK) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_22_22_MASK (0x400000U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_22_22_SHIFT (22U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_22_22_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_22_22_MASK) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_STOP_MASK (0x800000U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_STOP_SHIFT (23U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_STOP_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_STOP_MASK) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_24_31_MASK (0xFF000000U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_24_31_SHIFT (24U) #define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_24_31_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group AUDIO_LPCG_SPDIF1_Register_Masks */ /* AUDIO_LPCG_SPDIF1 - Peripheral instance base addresses */ /** Peripheral AUDIO__LPCG_SPDIF1 base address */ #define AUDIO__LPCG_SPDIF1_BASE (0x59430000u) /** Peripheral AUDIO__LPCG_SPDIF1 base pointer */ #define AUDIO__LPCG_SPDIF1 ((AUDIO_LPCG_SPDIF1_Type *)AUDIO__LPCG_SPDIF1_BASE) /** Array initializer of AUDIO_LPCG_SPDIF1 peripheral base addresses */ #define AUDIO_LPCG_SPDIF1_BASE_ADDRS { AUDIO__LPCG_SPDIF1_BASE } /** Array initializer of AUDIO_LPCG_SPDIF1 peripheral base pointers */ #define AUDIO_LPCG_SPDIF1_BASE_PTRS { AUDIO__LPCG_SPDIF1 } /*! * @} */ /* end of group AUDIO_LPCG_SPDIF1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- BCH Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer * @{ */ /** BCH - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0 */ __IO uint32_t RW; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */ __IO uint32_t SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */ __IO uint32_t CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */ __IO uint32_t TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */ } CTRL; struct { /* offset: 0x10 */ __I uint32_t RW; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */ __I uint32_t SET; /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */ __I uint32_t CLR; /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */ __I uint32_t TOG; /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */ } STATUS0; struct { /* offset: 0x20 */ __IO uint32_t RW; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */ __IO uint32_t SET; /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */ __IO uint32_t CLR; /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */ __IO uint32_t TOG; /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */ } MODE; struct { /* offset: 0x30 */ __IO uint32_t RW; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */ __IO uint32_t SET; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */ __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */ __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */ } ENCODEPTR; struct { /* offset: 0x40 */ __IO uint32_t RW; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */ __IO uint32_t SET; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */ __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */ __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */ } DATAPTR; struct { /* offset: 0x50 */ __IO uint32_t RW; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */ __IO uint32_t SET; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */ __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */ __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */ } METAPTR; uint8_t RESERVED_0[16]; struct { /* offset: 0x70 */ __IO uint32_t RW; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */ __IO uint32_t SET; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */ __IO uint32_t CLR; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */ __IO uint32_t TOG; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */ } LAYOUTSELECT; struct { /* offset: 0x80 */ __IO uint32_t RW; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */ __IO uint32_t SET; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */ __IO uint32_t CLR; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */ __IO uint32_t TOG; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */ } FLASH0LAYOUT0; struct { /* offset: 0x90 */ __IO uint32_t RW; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */ __IO uint32_t SET; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */ __IO uint32_t CLR; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */ __IO uint32_t TOG; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */ } FLASH0LAYOUT1; struct { /* offset: 0xA0 */ __IO uint32_t RW; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */ __IO uint32_t SET; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */ __IO uint32_t CLR; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */ __IO uint32_t TOG; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */ } FLASH1LAYOUT0; struct { /* offset: 0xB0 */ __IO uint32_t RW; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */ __IO uint32_t SET; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */ __IO uint32_t CLR; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */ __IO uint32_t TOG; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */ } FLASH1LAYOUT1; struct { /* offset: 0xC0 */ __IO uint32_t RW; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */ __IO uint32_t SET; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */ __IO uint32_t CLR; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */ __IO uint32_t TOG; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */ } FLASH2LAYOUT0; struct { /* offset: 0xD0 */ __IO uint32_t RW; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */ __IO uint32_t SET; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */ __IO uint32_t CLR; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */ __IO uint32_t TOG; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */ } FLASH2LAYOUT1; struct { /* offset: 0xE0 */ __IO uint32_t RW; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */ __IO uint32_t SET; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */ __IO uint32_t CLR; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */ __IO uint32_t TOG; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */ } FLASH3LAYOUT0; struct { /* offset: 0xF0 */ __IO uint32_t RW; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */ __IO uint32_t SET; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */ __IO uint32_t CLR; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */ __IO uint32_t TOG; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */ } FLASH3LAYOUT1; struct { /* offset: 0x100 */ __IO uint32_t RW; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */ __IO uint32_t SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */ __IO uint32_t CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */ __IO uint32_t TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */ } DEBUG0; struct { /* offset: 0x110 */ __I uint32_t RW; /**< KES Debug Read Register, offset: 0x110 */ __I uint32_t SET; /**< KES Debug Read Register, offset: 0x114 */ __I uint32_t CLR; /**< KES Debug Read Register, offset: 0x118 */ __I uint32_t TOG; /**< KES Debug Read Register, offset: 0x11C */ } DBGKESREAD; struct { /* offset: 0x120 */ __I uint32_t RW; /**< Chien Search Debug Read Register, offset: 0x120 */ __I uint32_t SET; /**< Chien Search Debug Read Register, offset: 0x124 */ __I uint32_t CLR; /**< Chien Search Debug Read Register, offset: 0x128 */ __I uint32_t TOG; /**< Chien Search Debug Read Register, offset: 0x12C */ } DBGCSFEREAD; struct { /* offset: 0x130 */ __I uint32_t RW; /**< Syndrome Generator Debug Read Register, offset: 0x130 */ __I uint32_t SET; /**< Syndrome Generator Debug Read Register, offset: 0x134 */ __I uint32_t CLR; /**< Syndrome Generator Debug Read Register, offset: 0x138 */ __I uint32_t TOG; /**< Syndrome Generator Debug Read Register, offset: 0x13C */ } DBGSYNDGENREAD; struct { /* offset: 0x140 */ __I uint32_t RW; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */ __I uint32_t SET; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */ __I uint32_t CLR; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */ __I uint32_t TOG; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */ } DBGAHBMREAD; struct { /* offset: 0x150 */ __I uint32_t RW; /**< Block Name Register, offset: 0x150 */ __I uint32_t SET; /**< Block Name Register, offset: 0x154 */ __I uint32_t CLR; /**< Block Name Register, offset: 0x158 */ __I uint32_t TOG; /**< Block Name Register, offset: 0x15C */ } BLOCKNAME; struct { /* offset: 0x160 */ __I uint32_t RW; /**< BCH Version Register, offset: 0x160 */ __I uint32_t SET; /**< BCH Version Register, offset: 0x164 */ __I uint32_t CLR; /**< BCH Version Register, offset: 0x168 */ __I uint32_t TOG; /**< BCH Version Register, offset: 0x16C */ } VERSION; struct { /* offset: 0x170 */ __IO uint32_t RW; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */ __IO uint32_t SET; /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */ __IO uint32_t CLR; /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */ __IO uint32_t TOG; /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */ } DEBUG1; } BCH_Type; /* ---------------------------------------------------------------------------- -- BCH Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup BCH_Register_Masks BCH Register Masks * @{ */ /*! @name CTRL - Hardware BCH ECC Accelerator Control Register */ /*! @{ */ #define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U) #define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U) #define BCH_CTRL_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK) #define BCH_CTRL_RSVD0_MASK (0x2U) #define BCH_CTRL_RSVD0_SHIFT (1U) #define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK) #define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U) #define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U) #define BCH_CTRL_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK) #define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U) #define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U) #define BCH_CTRL_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK) #define BCH_CTRL_RSVD1_MASK (0xF0U) #define BCH_CTRL_RSVD1_SHIFT (4U) #define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK) #define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U) #define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U) #define BCH_CTRL_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK) #define BCH_CTRL_RSVD2_MASK (0x200U) #define BCH_CTRL_RSVD2_SHIFT (9U) #define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK) #define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U) #define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U) #define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK) #define BCH_CTRL_RSVD3_MASK (0xF800U) #define BCH_CTRL_RSVD3_SHIFT (11U) #define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK) #define BCH_CTRL_M2M_ENABLE_MASK (0x10000U) #define BCH_CTRL_M2M_ENABLE_SHIFT (16U) #define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK) #define BCH_CTRL_M2M_ENCODE_MASK (0x20000U) #define BCH_CTRL_M2M_ENCODE_SHIFT (17U) #define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK) #define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U) #define BCH_CTRL_M2M_LAYOUT_SHIFT (18U) #define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK) #define BCH_CTRL_RSVD4_MASK (0x300000U) #define BCH_CTRL_RSVD4_SHIFT (20U) #define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK) #define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U) #define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U) #define BCH_CTRL_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK) #define BCH_CTRL_RSVD5_MASK (0x3F800000U) #define BCH_CTRL_RSVD5_SHIFT (23U) #define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK) #define BCH_CTRL_CLKGATE_MASK (0x40000000U) #define BCH_CTRL_CLKGATE_SHIFT (30U) /*! CLKGATE - CLKGATE * 0b0..Allow BCH to operate normally. * 0b1..Do not clock BCH gates in order to minimize power consumption. */ #define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK) #define BCH_CTRL_SFTRST_MASK (0x80000000U) #define BCH_CTRL_SFTRST_SHIFT (31U) /*! SFTRST - SFTRST * 0b0..Allow BCH to operate normally. * 0b1..Hold BCH in reset. */ #define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK) /*! @} */ /*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */ /*! @{ */ #define BCH_STATUS0_RSVD0_MASK (0x3U) #define BCH_STATUS0_RSVD0_SHIFT (0U) #define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK) #define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U) #define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U) #define BCH_STATUS0_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK) #define BCH_STATUS0_CORRECTED_MASK (0x8U) #define BCH_STATUS0_CORRECTED_SHIFT (3U) #define BCH_STATUS0_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK) #define BCH_STATUS0_ALLONES_MASK (0x10U) #define BCH_STATUS0_ALLONES_SHIFT (4U) #define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK) #define BCH_STATUS0_RSVD1_MASK (0xE0U) #define BCH_STATUS0_RSVD1_SHIFT (5U) #define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK) #define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U) #define BCH_STATUS0_STATUS_BLK0_SHIFT (8U) /*! STATUS_BLK0 - STATUS_BLK0 * 0b00000000..No errors found on block. * 0b00000001..One error found on block. * 0b00000010..One errors found on block. * 0b00000011..One errors found on block. * 0b00000100..One errors found on block. * 0b11111110..Block exhibited uncorrectable errors. * 0b11111111..Page is erased. */ #define BCH_STATUS0_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK) #define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U) #define BCH_STATUS0_COMPLETED_CE_SHIFT (16U) #define BCH_STATUS0_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK) #define BCH_STATUS0_HANDLE_MASK (0xFFF00000U) #define BCH_STATUS0_HANDLE_SHIFT (20U) #define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK) /*! @} */ /*! @name MODE - Hardware ECC Accelerator Mode Register */ /*! @{ */ #define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU) #define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U) #define BCH_MODE_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK) #define BCH_MODE_RSVD_MASK (0xFFFFFF00U) #define BCH_MODE_RSVD_SHIFT (8U) #define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK) /*! @} */ /*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */ /*! @{ */ #define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU) #define BCH_ENCODEPTR_ADDR_SHIFT (0U) #define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK) /*! @} */ /*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */ /*! @{ */ #define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU) #define BCH_DATAPTR_ADDR_SHIFT (0U) #define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK) /*! @} */ /*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */ /*! @{ */ #define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU) #define BCH_METAPTR_ADDR_SHIFT (0U) #define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK) /*! @} */ /*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */ /*! @{ */ #define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U) #define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U) #define BCH_LAYOUTSELECT_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK) #define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU) #define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U) #define BCH_LAYOUTSELECT_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK) #define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U) #define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U) #define BCH_LAYOUTSELECT_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK) #define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U) #define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U) #define BCH_LAYOUTSELECT_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK) #define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U) #define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U) #define BCH_LAYOUTSELECT_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK) #define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U) #define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U) #define BCH_LAYOUTSELECT_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK) #define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U) #define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U) #define BCH_LAYOUTSELECT_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK) #define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U) #define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U) #define BCH_LAYOUTSELECT_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK) #define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U) #define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U) #define BCH_LAYOUTSELECT_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK) #define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U) #define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U) #define BCH_LAYOUTSELECT_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK) #define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U) #define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U) #define BCH_LAYOUTSELECT_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK) #define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U) #define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U) #define BCH_LAYOUTSELECT_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK) #define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U) #define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U) #define BCH_LAYOUTSELECT_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK) #define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U) #define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U) #define BCH_LAYOUTSELECT_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK) #define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U) #define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U) #define BCH_LAYOUTSELECT_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK) #define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U) #define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U) #define BCH_LAYOUTSELECT_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK) /*! @} */ /*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */ /*! @{ */ #define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0xFFFU) #define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U) #define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK) #define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF000U) #define BCH_FLASH0LAYOUT0_ECC0_SHIFT (12U) /*! ECC0 - ECC0 * 0b0000..No ECC to be performed * 0b0001..ECC 2 to be performed * 0b0010..ECC 4 to be performed * 0b0011..ECC 6 to be performed * 0b0100..ECC 8 to be performed * 0b0101..ECC 10 to be performed * 0b0110..ECC 12 to be performed * 0b0111..ECC 14 to be performed * 0b1000..ECC 16 to be performed * 0b1001..ECC 18 to be performed * 0b1010..ECC 20 to be performed */ #define BCH_FLASH0LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK) #define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U) #define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U) #define BCH_FLASH0LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK) #define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U) #define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U) #define BCH_FLASH0LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK) /*! @} */ /*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */ /*! @{ */ #define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0xFFFU) #define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U) #define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK) #define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF000U) #define BCH_FLASH0LAYOUT1_ECCN_SHIFT (12U) /*! ECCN - ECCN * 0b0000..No ECC to be performed * 0b0001..ECC 2 to be performed * 0b0010..ECC 4 to be performed * 0b0011..ECC 6 to be performed * 0b0100..ECC 8 to be performed * 0b0101..ECC 10 to be performed * 0b0110..ECC 12 to be performed * 0b0111..ECC 14 to be performed * 0b1000..ECC 16 to be performed * 0b1001..ECC 18 to be performed * 0b1010..ECC 20 to be performed */ #define BCH_FLASH0LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK) #define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) #define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U) #define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK) /*! @} */ /*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */ /*! @{ */ #define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0xFFFU) #define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U) #define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK) #define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF000U) #define BCH_FLASH1LAYOUT0_ECC0_SHIFT (12U) /*! ECC0 - ECC0 * 0b0000..No ECC to be performed * 0b0001..ECC 2 to be performed * 0b0010..ECC 4 to be performed * 0b0011..ECC 6 to be performed * 0b0100..ECC 8 to be performed * 0b0101..ECC 10 to be performed * 0b0110..ECC 12 to be performed * 0b0111..ECC 14 to be performed * 0b1000..ECC 16 to be performed * 0b1001..ECC 18 to be performed * 0b1010..ECC 20 to be performed */ #define BCH_FLASH1LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK) #define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U) #define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U) #define BCH_FLASH1LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK) #define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U) #define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U) #define BCH_FLASH1LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK) /*! @} */ /*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */ /*! @{ */ #define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0xFFFU) #define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U) #define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK) #define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF000U) #define BCH_FLASH1LAYOUT1_ECCN_SHIFT (12U) /*! ECCN - ECCN * 0b0000..No ECC to be performed * 0b0001..ECC 2 to be performed * 0b0010..ECC 4 to be performed * 0b0011..ECC 6 to be performed * 0b0100..ECC 8 to be performed * 0b0101..ECC 10 to be performed * 0b0110..ECC 12 to be performed * 0b0111..ECC 14 to be performed * 0b1000..ECC 16 to be performed * 0b1001..ECC 18 to be performed * 0b1010..ECC 20 to be performed */ #define BCH_FLASH1LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK) #define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) #define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U) #define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK) /*! @} */ /*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */ /*! @{ */ #define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0xFFFU) #define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U) #define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK) #define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF000U) #define BCH_FLASH2LAYOUT0_ECC0_SHIFT (12U) /*! ECC0 - ECC0 * 0b0000..No ECC to be performed * 0b0001..ECC 2 to be performed * 0b0010..ECC 4 to be performed * 0b0011..ECC 6 to be performed * 0b0100..ECC 8 to be performed * 0b0101..ECC 10 to be performed * 0b0110..ECC 12 to be performed * 0b0111..ECC 14 to be performed * 0b1000..ECC 16 to be performed * 0b1001..ECC 18 to be performed * 0b1010..ECC 20 to be performed */ #define BCH_FLASH2LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK) #define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U) #define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U) #define BCH_FLASH2LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK) #define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U) #define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U) #define BCH_FLASH2LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK) /*! @} */ /*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */ /*! @{ */ #define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0xFFFU) #define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U) #define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK) #define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF000U) #define BCH_FLASH2LAYOUT1_ECCN_SHIFT (12U) /*! ECCN - ECCN * 0b0000..No ECC to be performed * 0b0001..ECC 2 to be performed * 0b0010..ECC 4 to be performed * 0b0011..ECC 6 to be performed * 0b0100..ECC 8 to be performed * 0b0101..ECC 10 to be performed * 0b0110..ECC 12 to be performed * 0b0111..ECC 14 to be performed * 0b1000..ECC 16 to be performed * 0b1001..ECC 18 to be performed * 0b1010..ECC 20 to be performed */ #define BCH_FLASH2LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK) #define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) #define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U) #define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK) /*! @} */ /*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */ /*! @{ */ #define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0xFFFU) #define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U) #define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK) #define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF000U) #define BCH_FLASH3LAYOUT0_ECC0_SHIFT (12U) /*! ECC0 - ECC0 * 0b0000..No ECC to be performed * 0b0001..ECC 2 to be performed * 0b0010..ECC 4 to be performed * 0b0011..ECC 6 to be performed * 0b0100..ECC 8 to be performed * 0b0101..ECC 10 to be performed * 0b0110..ECC 12 to be performed * 0b0111..ECC 14 to be performed * 0b1000..ECC 16 to be performed * 0b1001..ECC 18 to be performed * 0b1010..ECC 20 to be performed */ #define BCH_FLASH3LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK) #define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U) #define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U) #define BCH_FLASH3LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK) #define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U) #define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U) #define BCH_FLASH3LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK) /*! @} */ /*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */ /*! @{ */ #define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0xFFFU) #define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U) #define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK) #define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF000U) #define BCH_FLASH3LAYOUT1_ECCN_SHIFT (12U) /*! ECCN - ECCN * 0b0000..No ECC to be performed * 0b0001..ECC 2 to be performed * 0b0010..ECC 4 to be performed * 0b0011..ECC 6 to be performed * 0b0100..ECC 8 to be performed * 0b0101..ECC 10 to be performed * 0b0110..ECC 12 to be performed * 0b0111..ECC 14 to be performed * 0b1000..ECC 16 to be performed * 0b1001..ECC 18 to be performed * 0b1010..ECC 20 to be performed */ #define BCH_FLASH3LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK) #define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) #define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U) #define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK) /*! @} */ /*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */ /*! @{ */ #define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU) #define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U) #define BCH_DEBUG0_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK) #define BCH_DEBUG0_RSVD0_MASK (0xC0U) #define BCH_DEBUG0_RSVD0_SHIFT (6U) #define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK) #define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK (0x100U) #define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT (8U) /*! BM_KES_TEST_BYPASS - BM_KES_TEST_BYPASS * 0b0..Bus master address generator for SYND_GEN writes operates normally. * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. */ #define BCH_DEBUG0_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK) #define BCH_DEBUG0_KES_DEBUG_STALL_MASK (0x200U) #define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT (9U) /*! KES_DEBUG_STALL - KES_DEBUG_STALL * 0b0..KES FSM proceeds to next block supplied by bus master. * 0b1..KES FSM waits after current equations are solved and the search engine is started. */ #define BCH_DEBUG0_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK) #define BCH_DEBUG0_KES_DEBUG_STEP_MASK (0x400U) #define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT (10U) #define BCH_DEBUG0_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK) #define BCH_DEBUG0_KES_STANDALONE_MASK (0x800U) #define BCH_DEBUG0_KES_STANDALONE_SHIFT (11U) /*! KES_STANDALONE - KES_STANDALONE * 0b0..Bus master address generator for SYND_GEN writes operates normally. * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. */ #define BCH_DEBUG0_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK) #define BCH_DEBUG0_KES_DEBUG_KICK_MASK (0x1000U) #define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT (12U) #define BCH_DEBUG0_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK) #define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK (0x2000U) #define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT (13U) /*! KES_DEBUG_MODE4K - KES_DEBUG_MODE4K * 0b1..Mode is set for 4K NAND pages. * 0b1..Mode is set for 2K NAND pages. */ #define BCH_DEBUG0_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK) #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) /*! KES_DEBUG_PAYLOAD_FLAG - KES_DEBUG_PAYLOAD_FLAG * 0b1..Payload is set for 512 bytes data block. * 0b1..Payload is set for 65 or 19 bytes auxiliary block. */ #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK) #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT (15U) #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK) #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) /*! KES_DEBUG_SYNDROME_SYMBOL - KES_DEBUG_SYNDROME_SYMBOL * 0b000000000..Bus master address generator for SYND_GEN writes operates normally. * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block. */ #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK) #define BCH_DEBUG0_ROM_BIST_COMPLETE_MASK (0x2000000U) #define BCH_DEBUG0_ROM_BIST_COMPLETE_SHIFT (25U) #define BCH_DEBUG0_ROM_BIST_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_ROM_BIST_COMPLETE_SHIFT)) & BCH_DEBUG0_ROM_BIST_COMPLETE_MASK) #define BCH_DEBUG0_ROM_BIST_ENABLE_MASK (0x4000000U) #define BCH_DEBUG0_ROM_BIST_ENABLE_SHIFT (26U) #define BCH_DEBUG0_ROM_BIST_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_ROM_BIST_ENABLE_SHIFT)) & BCH_DEBUG0_ROM_BIST_ENABLE_MASK) #define BCH_DEBUG0_RSVD1_MASK (0xF8000000U) #define BCH_DEBUG0_RSVD1_SHIFT (27U) #define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK) /*! @} */ /*! @name DBGKESREAD - KES Debug Read Register */ /*! @{ */ #define BCH_DBGKESREAD_VALUES_MASK (0xFFFFFFFFU) #define BCH_DBGKESREAD_VALUES_SHIFT (0U) #define BCH_DBGKESREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK) /*! @} */ /*! @name DBGCSFEREAD - Chien Search Debug Read Register */ /*! @{ */ #define BCH_DBGCSFEREAD_VALUES_MASK (0xFFFFFFFFU) #define BCH_DBGCSFEREAD_VALUES_SHIFT (0U) #define BCH_DBGCSFEREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK) /*! @} */ /*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */ /*! @{ */ #define BCH_DBGSYNDGENREAD_VALUES_MASK (0xFFFFFFFFU) #define BCH_DBGSYNDGENREAD_VALUES_SHIFT (0U) #define BCH_DBGSYNDGENREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK) /*! @} */ /*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */ /*! @{ */ #define BCH_DBGAHBMREAD_VALUES_MASK (0xFFFFFFFFU) #define BCH_DBGAHBMREAD_VALUES_SHIFT (0U) #define BCH_DBGAHBMREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK) /*! @} */ /*! @name BLOCKNAME - Block Name Register */ /*! @{ */ #define BCH_BLOCKNAME_NAME_MASK (0xFFFFFFFFU) #define BCH_BLOCKNAME_NAME_SHIFT (0U) #define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK) /*! @} */ /*! @name VERSION - BCH Version Register */ /*! @{ */ #define BCH_VERSION_STEP_MASK (0xFFFFU) #define BCH_VERSION_STEP_SHIFT (0U) #define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK) #define BCH_VERSION_MINOR_MASK (0xFF0000U) #define BCH_VERSION_MINOR_SHIFT (16U) #define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK) #define BCH_VERSION_MAJOR_MASK (0xFF000000U) #define BCH_VERSION_MAJOR_SHIFT (24U) #define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK) /*! @} */ /*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */ /*! @{ */ #define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK (0x1FFU) #define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT (0U) #define BCH_DEBUG1_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK) #define BCH_DEBUG1_RSVD_MASK (0x7FFFFE00U) #define BCH_DEBUG1_RSVD_SHIFT (9U) #define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK) #define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK (0x80000000U) #define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT (31U) /*! DEBUG1_PREERASECHK - DEBUG1_PREERASECHK * 0b0..Turn off pre-erase check * 0b1..Turn on pre-erase check */ #define BCH_DEBUG1_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK) /*! @} */ /*! * @} */ /* end of group BCH_Register_Masks */ /* BCH - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__BCH base address */ #define CONNECTIVITY__BCH_BASE (0x5B814000u) /** Peripheral CONNECTIVITY__BCH base pointer */ #define CONNECTIVITY__BCH ((BCH_Type *)CONNECTIVITY__BCH_BASE) /** Array initializer of BCH peripheral base addresses */ #define BCH_BASE_ADDRS { CONNECTIVITY__BCH_BASE } /** Array initializer of BCH peripheral base pointers */ #define BCH_BASE_PTRS { CONNECTIVITY__BCH } /*! * @} */ /* end of group BCH_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CAN Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer * @{ */ /** CAN - Register Layout Typedef */ typedef struct { __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */ __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */ __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */ __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */ __IO uint32_t IMASK2; /**< Interrupt Masks 2 register, offset: 0x24 */ __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */ __IO uint32_t IFLAG2; /**< Interrupt Flags 2 register, offset: 0x2C */ __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */ __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */ __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */ uint8_t RESERVED_1[8]; __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */ __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ __IO uint32_t CBT; /**< CAN Bit Timing Register, offset: 0x50 */ uint8_t RESERVED_2[4]; __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */ __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */ uint8_t RESERVED_3[32]; struct { /* offset: 0x80, array step: 0x10 */ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ } MB[64]; uint8_t RESERVED_4[1024]; __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ uint8_t RESERVED_5[640]; __IO uint32_t FDCTRL; /**< CAN FD Control Register, offset: 0xC00 */ __IO uint32_t FDCBT; /**< CAN FD Bit Timing Register, offset: 0xC04 */ __I uint32_t FDCRC; /**< CAN FD CRC Register, offset: 0xC08 */ } CAN_Type; /* ---------------------------------------------------------------------------- -- CAN Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAN_Register_Masks CAN Register Masks * @{ */ /*! @name MCR - Module Configuration Register */ /*! @{ */ #define CAN_MCR_MAXMB_MASK (0x7FU) #define CAN_MCR_MAXMB_SHIFT (0U) #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) #define CAN_MCR_IDAM_MASK (0x300U) #define CAN_MCR_IDAM_SHIFT (8U) /*! IDAM - ID Acceptance Mode * 0b00..Format A: One full ID (standard and extended) per ID Filter Table element. * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. * 0b10..Format C: Four partial 8-bit Standard IDs per ID Filter Table element. * 0b11..Format D: All frames rejected. */ #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) #define CAN_MCR_FDEN_MASK (0x800U) #define CAN_MCR_FDEN_SHIFT (11U) /*! FDEN - CAN FD operation enable * 0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. * 0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format. */ #define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) #define CAN_MCR_AEN_MASK (0x1000U) #define CAN_MCR_AEN_SHIFT (12U) /*! AEN - Abort Enable * 0b0..Abort disabled. * 0b1..Abort enabled. */ #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) #define CAN_MCR_LPRIOEN_MASK (0x2000U) #define CAN_MCR_LPRIOEN_SHIFT (13U) /*! LPRIOEN - Local Priority Enable * 0b0..Local Priority disabled. * 0b1..Local Priority enabled. */ #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) #define CAN_MCR_DMA_MASK (0x8000U) #define CAN_MCR_DMA_SHIFT (15U) /*! DMA - DMA Enable * 0b0..DMA feature for RX FIFO disabled. * 0b1..DMA feature for RX FIFO enabled. */ #define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) #define CAN_MCR_IRMQ_MASK (0x10000U) #define CAN_MCR_IRMQ_SHIFT (16U) /*! IRMQ - Individual Rx Masking And Queue Enable * 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. * 0b1..Individual Rx masking and queue feature are enabled. */ #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) #define CAN_MCR_SRXDIS_MASK (0x20000U) #define CAN_MCR_SRXDIS_SHIFT (17U) /*! SRXDIS - Self Reception Disable * 0b0..Self reception enabled. * 0b1..Self reception disabled. */ #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) #define CAN_MCR_DOZE_MASK (0x40000U) #define CAN_MCR_DOZE_SHIFT (18U) /*! DOZE - Doze Mode Enable * 0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested. * 0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested. */ #define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK) #define CAN_MCR_WAKSRC_MASK (0x80000U) #define CAN_MCR_WAKSRC_SHIFT (19U) /*! WAKSRC - Wake Up Source * 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. * 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. */ #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) #define CAN_MCR_LPMACK_MASK (0x100000U) #define CAN_MCR_LPMACK_SHIFT (20U) /*! LPMACK - Low-Power Mode Acknowledge * 0b0..FlexCAN is not in a low-power mode. * 0b1..FlexCAN is in a low-power mode. */ #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) #define CAN_MCR_WRNEN_MASK (0x200000U) #define CAN_MCR_WRNEN_SHIFT (21U) /*! WRNEN - Warning Interrupt Enable * 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. * 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. */ #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) #define CAN_MCR_SLFWAK_MASK (0x400000U) #define CAN_MCR_SLFWAK_SHIFT (22U) /*! SLFWAK - Self Wake Up * 0b0..FlexCAN Self Wake Up feature is disabled. * 0b1..FlexCAN Self Wake Up feature is enabled. */ #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) #define CAN_MCR_FRZACK_MASK (0x1000000U) #define CAN_MCR_FRZACK_SHIFT (24U) /*! FRZACK - Freeze Mode Acknowledge * 0b0..FlexCAN not in Freeze mode, prescaler running. * 0b1..FlexCAN in Freeze mode, prescaler stopped. */ #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) #define CAN_MCR_SOFTRST_MASK (0x2000000U) #define CAN_MCR_SOFTRST_SHIFT (25U) /*! SOFTRST - Soft Reset * 0b0..No reset request. * 0b1..Resets the registers affected by soft reset. */ #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) #define CAN_MCR_WAKMSK_MASK (0x4000000U) #define CAN_MCR_WAKMSK_SHIFT (26U) /*! WAKMSK - Wake Up Interrupt Mask * 0b0..Wake Up Interrupt is disabled. * 0b1..Wake Up Interrupt is enabled. */ #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) #define CAN_MCR_NOTRDY_MASK (0x8000000U) #define CAN_MCR_NOTRDY_SHIFT (27U) /*! NOTRDY - FlexCAN Not Ready * 0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. */ #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) #define CAN_MCR_HALT_MASK (0x10000000U) #define CAN_MCR_HALT_SHIFT (28U) /*! HALT - Halt FlexCAN * 0b0..No Freeze mode request. * 0b1..Enters Freeze mode if the FRZ bit is asserted. */ #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) #define CAN_MCR_RFEN_MASK (0x20000000U) #define CAN_MCR_RFEN_SHIFT (29U) /*! RFEN - Rx FIFO Enable * 0b0..Rx FIFO not enabled. * 0b1..Rx FIFO enabled. */ #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) #define CAN_MCR_FRZ_MASK (0x40000000U) #define CAN_MCR_FRZ_SHIFT (30U) /*! FRZ - Freeze Enable * 0b0..Not enabled to enter Freeze mode. * 0b1..Enabled to enter Freeze mode. */ #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) #define CAN_MCR_MDIS_MASK (0x80000000U) #define CAN_MCR_MDIS_SHIFT (31U) /*! MDIS - Module Disable * 0b0..Enable the FlexCAN module. * 0b1..Disable the FlexCAN module. */ #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) /*! @} */ /*! @name CTRL1 - Control 1 register */ /*! @{ */ #define CAN_CTRL1_PROPSEG_MASK (0x7U) #define CAN_CTRL1_PROPSEG_SHIFT (0U) #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) #define CAN_CTRL1_LOM_MASK (0x8U) #define CAN_CTRL1_LOM_SHIFT (3U) /*! LOM - Listen-Only Mode * 0b0..Listen-Only mode is deactivated. * 0b1..FlexCAN module operates in Listen-Only mode. */ #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) #define CAN_CTRL1_LBUF_MASK (0x10U) #define CAN_CTRL1_LBUF_SHIFT (4U) /*! LBUF - Lowest Buffer Transmitted First * 0b0..Buffer with highest priority is transmitted first. * 0b1..Lowest number buffer is transmitted first. */ #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) #define CAN_CTRL1_TSYN_MASK (0x20U) #define CAN_CTRL1_TSYN_SHIFT (5U) /*! TSYN - Timer Sync * 0b0..Timer Sync feature disabled * 0b1..Timer Sync feature enabled */ #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) #define CAN_CTRL1_BOFFREC_MASK (0x40U) #define CAN_CTRL1_BOFFREC_SHIFT (6U) /*! BOFFREC - Bus Off Recovery * 0b0..Automatic recovering from Bus Off state enabled. * 0b1..Automatic recovering from Bus Off state disabled. */ #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) #define CAN_CTRL1_SMP_MASK (0x80U) #define CAN_CTRL1_SMP_SHIFT (7U) /*! SMP - CAN Bit Sampling * 0b0..Just one sample is used to determine the bit value. * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used. */ #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) #define CAN_CTRL1_RWRNMSK_MASK (0x400U) #define CAN_CTRL1_RWRNMSK_SHIFT (10U) /*! RWRNMSK - Rx Warning Interrupt Mask * 0b0..Rx Warning Interrupt disabled. * 0b1..Rx Warning Interrupt enabled. */ #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) #define CAN_CTRL1_TWRNMSK_MASK (0x800U) #define CAN_CTRL1_TWRNMSK_SHIFT (11U) /*! TWRNMSK - Tx Warning Interrupt Mask * 0b0..Tx Warning Interrupt disabled. * 0b1..Tx Warning Interrupt enabled. */ #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) #define CAN_CTRL1_LPB_MASK (0x1000U) #define CAN_CTRL1_LPB_SHIFT (12U) /*! LPB - Loop Back Mode * 0b0..Loop Back disabled. * 0b1..Loop Back enabled. */ #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) #define CAN_CTRL1_ERRMSK_MASK (0x4000U) #define CAN_CTRL1_ERRMSK_SHIFT (14U) /*! ERRMSK - Error Interrupt Mask * 0b0..Error interrupt disabled. * 0b1..Error interrupt enabled. */ #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) #define CAN_CTRL1_BOFFMSK_SHIFT (15U) /*! BOFFMSK - Bus Off Interrupt Mask * 0b0..Bus Off interrupt disabled. * 0b1..Bus Off interrupt enabled. */ #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) #define CAN_CTRL1_PSEG2_MASK (0x70000U) #define CAN_CTRL1_PSEG2_SHIFT (16U) #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) #define CAN_CTRL1_PSEG1_MASK (0x380000U) #define CAN_CTRL1_PSEG1_SHIFT (19U) #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) #define CAN_CTRL1_RJW_MASK (0xC00000U) #define CAN_CTRL1_RJW_SHIFT (22U) #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) #define CAN_CTRL1_PRESDIV_SHIFT (24U) #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) /*! @} */ /*! @name TIMER - Free Running Timer */ /*! @{ */ #define CAN_TIMER_TIMER_MASK (0xFFFFU) #define CAN_TIMER_TIMER_SHIFT (0U) #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) /*! @} */ /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ /*! @{ */ #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) #define CAN_RXMGMASK_MG_SHIFT (0U) #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) /*! @} */ /*! @name RX14MASK - Rx 14 Mask register */ /*! @{ */ #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) #define CAN_RX14MASK_RX14M_SHIFT (0U) #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) /*! @} */ /*! @name RX15MASK - Rx 15 Mask register */ /*! @{ */ #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) #define CAN_RX15MASK_RX15M_SHIFT (0U) #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) /*! @} */ /*! @name ECR - Error Counter */ /*! @{ */ #define CAN_ECR_TXERRCNT_MASK (0xFFU) #define CAN_ECR_TXERRCNT_SHIFT (0U) #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) #define CAN_ECR_RXERRCNT_MASK (0xFF00U) #define CAN_ECR_RXERRCNT_SHIFT (8U) #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) #define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) #define CAN_ECR_TXERRCNT_FAST_SHIFT (16U) #define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) #define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) #define CAN_ECR_RXERRCNT_FAST_SHIFT (24U) #define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK) /*! @} */ /*! @name ESR1 - Error and Status 1 register */ /*! @{ */ #define CAN_ESR1_WAKINT_MASK (0x1U) #define CAN_ESR1_WAKINT_SHIFT (0U) /*! WAKINT - Wake-Up Interrupt * 0b0..No such occurrence. * 0b1..Indicates a recessive to dominant transition was received on the CAN bus. */ #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) #define CAN_ESR1_ERRINT_MASK (0x2U) #define CAN_ESR1_ERRINT_SHIFT (1U) /*! ERRINT - Error Interrupt * 0b0..No such occurrence. * 0b1..Indicates setting of any Error Bit in the Error and Status Register. */ #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) #define CAN_ESR1_BOFFINT_MASK (0x4U) #define CAN_ESR1_BOFFINT_SHIFT (2U) /*! BOFFINT - Bus Off Interrupt * 0b0..No such occurrence. * 0b1..FlexCAN module entered Bus Off state. */ #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) #define CAN_ESR1_RX_MASK (0x8U) #define CAN_ESR1_RX_SHIFT (3U) /*! RX - FlexCAN In Reception * 0b0..FlexCAN is not receiving a message. * 0b1..FlexCAN is receiving a message. */ #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) #define CAN_ESR1_FLTCONF_MASK (0x30U) #define CAN_ESR1_FLTCONF_SHIFT (4U) /*! FLTCONF - Fault Confinement State * 0b00..Error Active * 0b01..Error Passive * 0b1x..Bus Off */ #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) #define CAN_ESR1_TX_MASK (0x40U) #define CAN_ESR1_TX_SHIFT (6U) /*! TX - FlexCAN In Transmission * 0b0..FlexCAN is not transmitting a message. * 0b1..FlexCAN is transmitting a message. */ #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) #define CAN_ESR1_IDLE_MASK (0x80U) #define CAN_ESR1_IDLE_SHIFT (7U) /*! IDLE - IDLE * 0b0..No such occurrence. * 0b1..CAN bus is now IDLE. */ #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) #define CAN_ESR1_RXWRN_MASK (0x100U) #define CAN_ESR1_RXWRN_SHIFT (8U) /*! RXWRN - Rx Error Warning * 0b0..No such occurrence. * 0b1..RXERRCNT is greater than or equal to 96. */ #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) #define CAN_ESR1_TXWRN_MASK (0x200U) #define CAN_ESR1_TXWRN_SHIFT (9U) /*! TXWRN - TX Error Warning * 0b0..No such occurrence. * 0b1..TXERRCNT is greater than or equal to 96. */ #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) #define CAN_ESR1_STFERR_MASK (0x400U) #define CAN_ESR1_STFERR_SHIFT (10U) /*! STFERR - Stuffing Error * 0b0..No such occurrence. * 0b1..A Stuffing Error occurred since last read of this register. */ #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) #define CAN_ESR1_FRMERR_MASK (0x800U) #define CAN_ESR1_FRMERR_SHIFT (11U) /*! FRMERR - Form Error * 0b0..No such occurrence. * 0b1..A Form Error occurred since last read of this register. */ #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) #define CAN_ESR1_CRCERR_MASK (0x1000U) #define CAN_ESR1_CRCERR_SHIFT (12U) /*! CRCERR - Cyclic Redundancy Check Error * 0b0..No such occurrence. * 0b1..A CRC error occurred since last read of this register. */ #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) #define CAN_ESR1_ACKERR_MASK (0x2000U) #define CAN_ESR1_ACKERR_SHIFT (13U) /*! ACKERR - Acknowledge Error * 0b0..No such occurrence. * 0b1..An ACK error occurred since last read of this register. */ #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) #define CAN_ESR1_BIT0ERR_MASK (0x4000U) #define CAN_ESR1_BIT0ERR_SHIFT (14U) /*! BIT0ERR - Bit0 Error * 0b0..No such occurrence. * 0b1..At least one bit sent as dominant is received as recessive. */ #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) #define CAN_ESR1_BIT1ERR_MASK (0x8000U) #define CAN_ESR1_BIT1ERR_SHIFT (15U) /*! BIT1ERR - Bit1 Error * 0b0..No such occurrence. * 0b1..At least one bit sent as recessive is received as dominant. */ #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) #define CAN_ESR1_RWRNINT_MASK (0x10000U) #define CAN_ESR1_RWRNINT_SHIFT (16U) /*! RWRNINT - Rx Warning Interrupt Flag * 0b0..No such occurrence. * 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96. */ #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) #define CAN_ESR1_TWRNINT_MASK (0x20000U) #define CAN_ESR1_TWRNINT_SHIFT (17U) /*! TWRNINT - Tx Warning Interrupt Flag * 0b0..No such occurrence. * 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96. */ #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) #define CAN_ESR1_SYNCH_MASK (0x40000U) #define CAN_ESR1_SYNCH_SHIFT (18U) /*! SYNCH - CAN Synchronization Status * 0b0..FlexCAN is not synchronized to the CAN bus. * 0b1..FlexCAN is synchronized to the CAN bus. */ #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) #define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) #define CAN_ESR1_BOFFDONEINT_SHIFT (19U) /*! BOFFDONEINT - Bus Off Done Interrupt * 0b0..No such occurrence. * 0b1..FlexCAN module has completed Bus Off process. */ #define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) #define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) #define CAN_ESR1_ERRINT_FAST_SHIFT (20U) /*! ERRINT_FAST - Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set. */ #define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) #define CAN_ESR1_ERROVR_MASK (0x200000U) #define CAN_ESR1_ERROVR_SHIFT (21U) /*! ERROVR - Error Overrun bit * 0b0..Overrun has not occurred. * 0b1..Overrun has occurred. */ #define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) #define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) #define CAN_ESR1_STFERR_FAST_SHIFT (26U) /*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..A Stuffing Error occurred since last read of this register. */ #define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) #define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) #define CAN_ESR1_FRMERR_FAST_SHIFT (27U) /*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..A Form Error occurred since last read of this register. */ #define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) #define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) #define CAN_ESR1_CRCERR_FAST_SHIFT (28U) /*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..A CRC error occurred since last read of this register. */ #define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) #define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) #define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) /*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..At least one bit sent as dominant is received as recessive. */ #define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) #define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) #define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) /*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..At least one bit sent as recessive is received as dominant. */ #define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK) /*! @} */ /*! @name IMASK2 - Interrupt Masks 2 register */ /*! @{ */ #define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU) #define CAN_IMASK2_BUF63TO32M_SHIFT (0U) #define CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK) /*! @} */ /*! @name IMASK1 - Interrupt Masks 1 register */ /*! @{ */ #define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) #define CAN_IMASK1_BUF31TO0M_SHIFT (0U) #define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) /*! @} */ /*! @name IFLAG2 - Interrupt Flags 2 register */ /*! @{ */ #define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU) #define CAN_IFLAG2_BUF63TO32I_SHIFT (0U) #define CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK) /*! @} */ /*! @name IFLAG1 - Interrupt Flags 1 register */ /*! @{ */ #define CAN_IFLAG1_BUF0I_MASK (0x1U) #define CAN_IFLAG1_BUF0I_SHIFT (0U) /*! BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when CAN_MCR[RFEN]=0. * 0b1..The corresponding buffer has successfully completed transmission or reception when CAN_MCR[RFEN]=0. */ #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) #define CAN_IFLAG1_BUF5I_MASK (0x20U) #define CAN_IFLAG1_BUF5I_SHIFT (5U) /*! BUF5I - Buffer MB5 Interrupt Or "Frames available in Rx FIFO" * 0b0..No occurrence of MB5 completing transmission/reception when CAN_MCR[RFEN]=0, or of frame(s) available in the FIFO, when CAN_MCR[RFEN]=1 * 0b1..MB5 completed transmission/reception when CAN_MCR[RFEN]=0, or frame(s) available in the Rx FIFO when CAN_MCR[RFEN]=1. It generates a DMA request in case of CAN_MCR[RFEN] and CAN_MCR[DMA] are enabled. */ #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) #define CAN_IFLAG1_BUF6I_MASK (0x40U) #define CAN_IFLAG1_BUF6I_SHIFT (6U) /*! BUF6I - Buffer MB6 Interrupt Or "Rx FIFO Warning" * 0b0..No occurrence of MB6 completing transmission/reception when CAN_MCR[RFEN]=0, or of Rx FIFO almost full when CAN_MCR[RFEN]=1 * 0b1..MB6 completed transmission/reception when CAN_MCR[RFEN]=0, or Rx FIFO almost full when CAN_MCR[RFEN]=1 */ #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) #define CAN_IFLAG1_BUF7I_MASK (0x80U) #define CAN_IFLAG1_BUF7I_SHIFT (7U) /*! BUF7I - Buffer MB7 Interrupt Or "Rx FIFO Overflow" * 0b0..No occurrence of MB7 completing transmission/reception when CAN_MCR[RFEN]=0, or of Rx FIFO overflow when CAN_MCR[RFEN]=1 * 0b1..MB7 completed transmission/reception when CAN_MCR[RFEN]=0, or Rx FIFO overflow when CAN_MCR[RFEN]=1 */ #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) /*! @} */ /*! @name CTRL2 - Control 2 register */ /*! @{ */ #define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) #define CAN_CTRL2_ISOCANFDEN_SHIFT (12U) /*! ISOCANFDEN - ISO CAN FD Enable * 0b0..FlexCAN operates using the non-ISO CAN FD protocol. * 0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1). */ #define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) #define CAN_CTRL2_EACEN_MASK (0x10000U) #define CAN_CTRL2_EACEN_SHIFT (16U) /*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. */ #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) #define CAN_CTRL2_RRS_MASK (0x20000U) #define CAN_CTRL2_RRS_SHIFT (17U) /*! RRS - Remote Request Storing * 0b0..Remote Response Frame is generated. * 0b1..Remote Request Frame is stored. */ #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) #define CAN_CTRL2_MRP_MASK (0x40000U) #define CAN_CTRL2_MRP_SHIFT (18U) /*! MRP - Mailboxes Reception Priority * 0b0..Matching starts from Rx FIFO and continues on Mailboxes. * 0b1..Matching starts from Mailboxes and continues on Rx FIFO. */ #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) #define CAN_CTRL2_TASD_MASK (0xF80000U) #define CAN_CTRL2_TASD_SHIFT (19U) #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) #define CAN_CTRL2_RFFN_MASK (0xF000000U) #define CAN_CTRL2_RFFN_SHIFT (24U) #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) #define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) #define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) /*! BOFFDONEMSK - Bus Off Done Interrupt Mask * 0b0..Bus Off Done interrupt disabled. * 0b1..Bus Off Done interrupt enabled. */ #define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) #define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) #define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) /*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames * 0b0..ERRINT_FAST Error interrupt disabled. * 0b1..ERRINT_FAST Error interrupt enabled. */ #define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK) /*! @} */ /*! @name ESR2 - Error and Status 2 register */ /*! @{ */ #define CAN_ESR2_IMB_MASK (0x2000U) #define CAN_ESR2_IMB_SHIFT (13U) /*! IMB - Inactive Mailbox * 0b0..If CAN_ESR2[VPS] is asserted, the CAN_ESR2[LPTM] is not an inactive Mailbox. * 0b1..If CAN_ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. */ #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) #define CAN_ESR2_VPS_MASK (0x4000U) #define CAN_ESR2_VPS_SHIFT (14U) /*! VPS - Valid Priority Status * 0b0..Contents of IMB and LPTM are invalid. * 0b1..Contents of IMB and LPTM are valid. */ #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) #define CAN_ESR2_LPTM_MASK (0x7F0000U) #define CAN_ESR2_LPTM_SHIFT (16U) #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) /*! @} */ /*! @name CRCR - CRC Register */ /*! @{ */ #define CAN_CRCR_TXCRC_MASK (0x7FFFU) #define CAN_CRCR_TXCRC_SHIFT (0U) #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) #define CAN_CRCR_MBCRC_MASK (0x7F0000U) #define CAN_CRCR_MBCRC_SHIFT (16U) #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) /*! @} */ /*! @name RXFGMASK - Rx FIFO Global Mask register */ /*! @{ */ #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) #define CAN_RXFGMASK_FGM_SHIFT (0U) #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) /*! @} */ /*! @name RXFIR - Rx FIFO Information Register */ /*! @{ */ #define CAN_RXFIR_IDHIT_MASK (0x1FFU) #define CAN_RXFIR_IDHIT_SHIFT (0U) #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) /*! @} */ /*! @name CBT - CAN Bit Timing Register */ /*! @{ */ #define CAN_CBT_EPSEG2_MASK (0x1FU) #define CAN_CBT_EPSEG2_SHIFT (0U) #define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) #define CAN_CBT_EPSEG1_MASK (0x3E0U) #define CAN_CBT_EPSEG1_SHIFT (5U) #define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) #define CAN_CBT_EPROPSEG_MASK (0xFC00U) #define CAN_CBT_EPROPSEG_SHIFT (10U) #define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) #define CAN_CBT_ERJW_MASK (0xF0000U) #define CAN_CBT_ERJW_SHIFT (16U) #define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) #define CAN_CBT_EPRESDIV_MASK (0x7FE00000U) #define CAN_CBT_EPRESDIV_SHIFT (21U) #define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) #define CAN_CBT_BTF_MASK (0x80000000U) #define CAN_CBT_BTF_SHIFT (31U) /*! BTF - Bit Timing Format Enable * 0b0..Extended bit time definitions disabled. * 0b1..Extended bit time definitions enabled. */ #define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) /*! @} */ /*! @name DBG1 - Debug 1 register */ /*! @{ */ #define CAN_DBG1_CFSM_MASK (0x7FU) #define CAN_DBG1_CFSM_SHIFT (0U) #define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK) #define CAN_DBG1_CBN_MASK (0x3FF0000U) #define CAN_DBG1_CBN_SHIFT (16U) #define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK) /*! @} */ /*! @name DBG2 - Debug 2 register */ /*! @{ */ #define CAN_DBG2_RMP_MASK (0x7FU) #define CAN_DBG2_RMP_SHIFT (0U) #define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK) #define CAN_DBG2_MPP_MASK (0x80U) #define CAN_DBG2_MPP_SHIFT (7U) /*! MPP - Matching Process in Progress * 0b0..No matching process ongoing * 0b1..Matching process is in progress. */ #define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK) #define CAN_DBG2_TAP_MASK (0x7F00U) #define CAN_DBG2_TAP_SHIFT (8U) #define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK) #define CAN_DBG2_APP_MASK (0x8000U) #define CAN_DBG2_APP_SHIFT (15U) /*! APP - Arbitration Process in Progress * 0b0..No arbitration process ongoing * 0b1..Arbitration process is in progress. */ #define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK) /*! @} */ /*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */ /*! @{ */ #define CAN_CS_TIME_STAMP_MASK (0xFFFFU) #define CAN_CS_TIME_STAMP_SHIFT (0U) #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) #define CAN_CS_DLC_MASK (0xF0000U) #define CAN_CS_DLC_SHIFT (16U) #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) #define CAN_CS_RTR_MASK (0x100000U) #define CAN_CS_RTR_SHIFT (20U) #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) #define CAN_CS_IDE_MASK (0x200000U) #define CAN_CS_IDE_SHIFT (21U) #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) #define CAN_CS_SRR_MASK (0x400000U) #define CAN_CS_SRR_SHIFT (22U) #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) #define CAN_CS_CODE_MASK (0xF000000U) #define CAN_CS_CODE_SHIFT (24U) #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) #define CAN_CS_ESI_MASK (0x20000000U) #define CAN_CS_ESI_SHIFT (29U) #define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK) #define CAN_CS_BRS_MASK (0x40000000U) #define CAN_CS_BRS_SHIFT (30U) #define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK) #define CAN_CS_EDL_MASK (0x80000000U) #define CAN_CS_EDL_SHIFT (31U) #define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK) /*! @} */ /* The count of CAN_CS */ #define CAN_CS_COUNT (64U) /*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */ /*! @{ */ #define CAN_ID_EXT_MASK (0x3FFFFU) #define CAN_ID_EXT_SHIFT (0U) #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) #define CAN_ID_STD_MASK (0x1FFC0000U) #define CAN_ID_STD_SHIFT (18U) #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) #define CAN_ID_PRIO_MASK (0xE0000000U) #define CAN_ID_PRIO_SHIFT (29U) #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) /*! @} */ /* The count of CAN_ID */ #define CAN_ID_COUNT (64U) /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */ /*! @{ */ #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) /*! @} */ /* The count of CAN_WORD0 */ #define CAN_WORD0_COUNT (64U) /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */ /*! @{ */ #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) /*! @} */ /* The count of CAN_WORD1 */ #define CAN_WORD1_COUNT (64U) /*! @name RXIMR - Rx Individual Mask Registers */ /*! @{ */ #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) #define CAN_RXIMR_MI_SHIFT (0U) #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) /*! @} */ /* The count of CAN_RXIMR */ #define CAN_RXIMR_COUNT (64U) /*! @name FDCTRL - CAN FD Control Register */ /*! @{ */ #define CAN_FDCTRL_TDCVAL_MASK (0x3FU) #define CAN_FDCTRL_TDCVAL_SHIFT (0U) #define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK) #define CAN_FDCTRL_TDCOFF_MASK (0x1F00U) #define CAN_FDCTRL_TDCOFF_SHIFT (8U) #define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK) #define CAN_FDCTRL_TDCFAIL_MASK (0x4000U) #define CAN_FDCTRL_TDCFAIL_SHIFT (14U) /*! TDCFAIL - Transceiver Delay Compensation Fail * 0b0..Measured loop delay is in range. * 0b1..Measured loop delay is out of range. */ #define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) #define CAN_FDCTRL_TDCEN_MASK (0x8000U) #define CAN_FDCTRL_TDCEN_SHIFT (15U) /*! TDCEN - Transceiver Delay Compensation Enable * 0b0..TDC is disabled * 0b1..TDC is enabled */ #define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) #define CAN_FDCTRL_MBDSR0_MASK (0x30000U) #define CAN_FDCTRL_MBDSR0_SHIFT (16U) /*! MBDSR0 - Message Buffer Data Size for Region 0 * 0b00..Selects 8 bytes per Message Buffer. * 0b01..Selects 16 bytes per Message Buffer. * 0b10..Selects 32 bytes per Message Buffer. * 0b11..Selects 64 bytes per Message Buffer. */ #define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) #define CAN_FDCTRL_MBDSR1_MASK (0x180000U) #define CAN_FDCTRL_MBDSR1_SHIFT (19U) /*! MBDSR1 - Message Buffer Data Size for Region 1 * 0b00..Selects 8 bytes per Message Buffer. * 0b01..Selects 16 bytes per Message Buffer. * 0b10..Selects 32 bytes per Message Buffer. * 0b11..Selects 64 bytes per Message Buffer. */ #define CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK) #define CAN_FDCTRL_FDRATE_MASK (0x80000000U) #define CAN_FDCTRL_FDRATE_SHIFT (31U) /*! FDRATE - Bit Rate Switch Enable * 0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect. * 0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive. */ #define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK) /*! @} */ /*! @name FDCBT - CAN FD Bit Timing Register */ /*! @{ */ #define CAN_FDCBT_FPSEG2_MASK (0x7U) #define CAN_FDCBT_FPSEG2_SHIFT (0U) #define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK) #define CAN_FDCBT_FPSEG1_MASK (0xE0U) #define CAN_FDCBT_FPSEG1_SHIFT (5U) #define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK) #define CAN_FDCBT_FPROPSEG_MASK (0x7C00U) #define CAN_FDCBT_FPROPSEG_SHIFT (10U) #define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK) #define CAN_FDCBT_FRJW_MASK (0x30000U) #define CAN_FDCBT_FRJW_SHIFT (16U) #define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK) #define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) #define CAN_FDCBT_FPRESDIV_SHIFT (20U) #define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) /*! @} */ /*! @name FDCRC - CAN FD CRC Register */ /*! @{ */ #define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) #define CAN_FDCRC_FD_TXCRC_SHIFT (0U) #define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK) #define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) #define CAN_FDCRC_FD_MBCRC_SHIFT (24U) #define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) /*! @} */ /*! * @} */ /* end of group CAN_Register_Masks */ /* CAN - Peripheral instance base addresses */ /** Peripheral DMA__CAN0 base address */ #define DMA__CAN0_BASE (0x5A8D0000u) /** Peripheral DMA__CAN0 base pointer */ #define DMA__CAN0 ((CAN_Type *)DMA__CAN0_BASE) /** Peripheral DMA__CAN1 base address */ #define DMA__CAN1_BASE (0x5A8E0000u) /** Peripheral DMA__CAN1 base pointer */ #define DMA__CAN1 ((CAN_Type *)DMA__CAN1_BASE) /** Peripheral DMA__CAN2 base address */ #define DMA__CAN2_BASE (0x5A8F0000u) /** Peripheral DMA__CAN2 base pointer */ #define DMA__CAN2 ((CAN_Type *)DMA__CAN2_BASE) /** Array initializer of CAN peripheral base addresses */ #define CAN_BASE_ADDRS { DMA__CAN0_BASE, DMA__CAN1_BASE, DMA__CAN2_BASE } /** Array initializer of CAN peripheral base pointers */ #define CAN_BASE_PTRS { DMA__CAN0, DMA__CAN1, DMA__CAN2 } /** Interrupt vectors for the CAN peripheral type */ #define CAN_Rx_Warning_IRQS { DMA_FLEXCAN0_INT_IRQn, DMA_FLEXCAN1_INT_IRQn, DMA_FLEXCAN2_INT_IRQn } #define CAN_Tx_Warning_IRQS { DMA_FLEXCAN0_INT_IRQn, DMA_FLEXCAN1_INT_IRQn, DMA_FLEXCAN2_INT_IRQn } #define CAN_Wake_Up_IRQS { DMA_FLEXCAN0_INT_IRQn, DMA_FLEXCAN1_INT_IRQn, DMA_FLEXCAN2_INT_IRQn } #define CAN_Error_IRQS { DMA_FLEXCAN0_INT_IRQn, DMA_FLEXCAN1_INT_IRQn, DMA_FLEXCAN2_INT_IRQn } #define CAN_Bus_Off_IRQS { DMA_FLEXCAN0_INT_IRQn, DMA_FLEXCAN1_INT_IRQn, DMA_FLEXCAN2_INT_IRQn } #define CAN_ORed_Message_buffer_IRQS { DMA_FLEXCAN0_INT_IRQn, DMA_FLEXCAN1_INT_IRQn, DMA_FLEXCAN2_INT_IRQn } /*! * @} */ /* end of group CAN_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CM4_LPCG_LPI2C Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_LPI2C_Peripheral_Access_Layer CM4_LPCG_LPI2C Peripheral Access Layer * @{ */ /** CM4_LPCG_LPI2C - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPI2C_0; /**< na, offset: 0x0 */ } CM4_LPCG_LPI2C_Type; /* ---------------------------------------------------------------------------- -- CM4_LPCG_LPI2C Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_LPI2C_Register_Masks CM4_LPCG_LPI2C Register Masks * @{ */ /*! @name LPCG_LPI2C_0 - na */ /*! @{ */ #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK (0x4U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT (2U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK (0x10U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT (4U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK (0x20U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT (5U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK (0x40U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT (6U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK (0x80U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT (7U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK (0xFFFFFF00U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT (8U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK) /*! @} */ /*! * @} */ /* end of group CM4_LPCG_LPI2C_Register_Masks */ /* CM4_LPCG_LPI2C - Peripheral instance base addresses */ /** Peripheral CM4_0__LPCG_LPI2C base address */ #define CM4_0__LPCG_LPI2C_BASE (0x37630000u) /** Peripheral CM4_0__LPCG_LPI2C base pointer */ #define CM4_0__LPCG_LPI2C ((CM4_LPCG_LPI2C_Type *)CM4_0__LPCG_LPI2C_BASE) /** Peripheral CM4_1__LPCG_LPI2C base address */ #define CM4_1__LPCG_LPI2C_BASE (0x41630000u) /** Peripheral CM4_1__LPCG_LPI2C base pointer */ #define CM4_1__LPCG_LPI2C ((CM4_LPCG_LPI2C_Type *)CM4_1__LPCG_LPI2C_BASE) /** Array initializer of CM4_LPCG_LPI2C peripheral base addresses */ #define CM4_LPCG_LPI2C_BASE_ADDRS { CM4_0__LPCG_LPI2C_BASE, CM4_1__LPCG_LPI2C_BASE } /** Array initializer of CM4_LPCG_LPI2C peripheral base pointers */ #define CM4_LPCG_LPI2C_BASE_PTRS { CM4_0__LPCG_LPI2C, CM4_1__LPCG_LPI2C } /*! * @} */ /* end of group CM4_LPCG_LPI2C_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CM4_LPCG_LPIT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_LPIT_Peripheral_Access_Layer CM4_LPCG_LPIT Peripheral Access Layer * @{ */ /** CM4_LPCG_LPIT - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPIT_0; /**< na, offset: 0x0 */ } CM4_LPCG_LPIT_Type; /* ---------------------------------------------------------------------------- -- CM4_LPCG_LPIT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_LPIT_Register_Masks CM4_LPCG_LPIT Register Masks * @{ */ /*! @name LPCG_LPIT_0 - na */ /*! @{ */ #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK (0x1U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT (0U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK (0x2U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT (1U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK (0x4U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT (2U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK (0x8U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT (3U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK (0x10U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT (4U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK (0x20U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT (5U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK (0x40U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT (6U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK (0x80U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT (7U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK (0xFFFFFF00U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT (8U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK) /*! @} */ /*! * @} */ /* end of group CM4_LPCG_LPIT_Register_Masks */ /* CM4_LPCG_LPIT - Peripheral instance base addresses */ /** Peripheral CM4_0__LPCG_LPIT base address */ #define CM4_0__LPCG_LPIT_BASE (0x37610000u) /** Peripheral CM4_0__LPCG_LPIT base pointer */ #define CM4_0__LPCG_LPIT ((CM4_LPCG_LPIT_Type *)CM4_0__LPCG_LPIT_BASE) /** Peripheral CM4_1__LPCG_LPIT base address */ #define CM4_1__LPCG_LPIT_BASE (0x41610000u) /** Peripheral CM4_1__LPCG_LPIT base pointer */ #define CM4_1__LPCG_LPIT ((CM4_LPCG_LPIT_Type *)CM4_1__LPCG_LPIT_BASE) /** Array initializer of CM4_LPCG_LPIT peripheral base addresses */ #define CM4_LPCG_LPIT_BASE_ADDRS { CM4_0__LPCG_LPIT_BASE, CM4_1__LPCG_LPIT_BASE } /** Array initializer of CM4_LPCG_LPIT peripheral base pointers */ #define CM4_LPCG_LPIT_BASE_PTRS { CM4_0__LPCG_LPIT, CM4_1__LPCG_LPIT } /*! * @} */ /* end of group CM4_LPCG_LPIT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CM4_LPCG_LPUART Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_LPUART_Peripheral_Access_Layer CM4_LPCG_LPUART Peripheral Access Layer * @{ */ /** CM4_LPCG_LPUART - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPUART_0; /**< na, offset: 0x0 */ } CM4_LPCG_LPUART_Type; /* ---------------------------------------------------------------------------- -- CM4_LPCG_LPUART Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_LPUART_Register_Masks CM4_LPCG_LPUART Register Masks * @{ */ /*! @name LPCG_LPUART_0 - na */ /*! @{ */ #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK (0x1U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT (0U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK (0x2U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT (1U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK (0x4U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT (2U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK (0x8U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT (3U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK (0x10U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT (4U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK (0x20U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT (5U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK (0x40U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT (6U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK (0x80U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT (7U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK (0xFFFFFF00U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT (8U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK) /*! @} */ /*! * @} */ /* end of group CM4_LPCG_LPUART_Register_Masks */ /* CM4_LPCG_LPUART - Peripheral instance base addresses */ /** Peripheral CM4_0__LPCG_LPUART base address */ #define CM4_0__LPCG_LPUART_BASE (0x37620000u) /** Peripheral CM4_0__LPCG_LPUART base pointer */ #define CM4_0__LPCG_LPUART ((CM4_LPCG_LPUART_Type *)CM4_0__LPCG_LPUART_BASE) /** Peripheral CM4_1__LPCG_LPUART base address */ #define CM4_1__LPCG_LPUART_BASE (0x41620000u) /** Peripheral CM4_1__LPCG_LPUART base pointer */ #define CM4_1__LPCG_LPUART ((CM4_LPCG_LPUART_Type *)CM4_1__LPCG_LPUART_BASE) /** Array initializer of CM4_LPCG_LPUART peripheral base addresses */ #define CM4_LPCG_LPUART_BASE_ADDRS { CM4_0__LPCG_LPUART_BASE, CM4_1__LPCG_LPUART_BASE } /** Array initializer of CM4_LPCG_LPUART peripheral base pointers */ #define CM4_LPCG_LPUART_BASE_PTRS { CM4_0__LPCG_LPUART, CM4_1__LPCG_LPUART } /*! * @} */ /* end of group CM4_LPCG_LPUART_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CM4_LPCG_MMCAU_HCLK Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_MMCAU_HCLK_Peripheral_Access_Layer CM4_LPCG_MMCAU_HCLK Peripheral Access Layer * @{ */ /** CM4_LPCG_MMCAU_HCLK - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MMCAU_HCLK_0; /**< na, offset: 0x0 */ } CM4_LPCG_MMCAU_HCLK_Type; /* ---------------------------------------------------------------------------- -- CM4_LPCG_MMCAU_HCLK Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_MMCAU_HCLK_Register_Masks CM4_LPCG_MMCAU_HCLK Register Masks * @{ */ /*! @name LPCG_MMCAU_HCLK_0 - na */ /*! @{ */ #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK (0x1U) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT (0U) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK (0x2U) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT (1U) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK (0x4U) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT (2U) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK (0x8U) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT (3U) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT (4U) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group CM4_LPCG_MMCAU_HCLK_Register_Masks */ /* CM4_LPCG_MMCAU_HCLK - Peripheral instance base addresses */ /** Peripheral CM4_0__LPCG_MMCAU_HCLK base address */ #define CM4_0__LPCG_MMCAU_HCLK_BASE (0x375F0000u) /** Peripheral CM4_0__LPCG_MMCAU_HCLK base pointer */ #define CM4_0__LPCG_MMCAU_HCLK ((CM4_LPCG_MMCAU_HCLK_Type *)CM4_0__LPCG_MMCAU_HCLK_BASE) /** Peripheral CM4_1__LPCG_MMCAU_HCLK base address */ #define CM4_1__LPCG_MMCAU_HCLK_BASE (0x415F0000u) /** Peripheral CM4_1__LPCG_MMCAU_HCLK base pointer */ #define CM4_1__LPCG_MMCAU_HCLK ((CM4_LPCG_MMCAU_HCLK_Type *)CM4_1__LPCG_MMCAU_HCLK_BASE) /** Array initializer of CM4_LPCG_MMCAU_HCLK peripheral base addresses */ #define CM4_LPCG_MMCAU_HCLK_BASE_ADDRS { CM4_0__LPCG_MMCAU_HCLK_BASE, CM4_1__LPCG_MMCAU_HCLK_BASE } /** Array initializer of CM4_LPCG_MMCAU_HCLK peripheral base pointers */ #define CM4_LPCG_MMCAU_HCLK_BASE_PTRS { CM4_0__LPCG_MMCAU_HCLK, CM4_1__LPCG_MMCAU_HCLK } /*! * @} */ /* end of group CM4_LPCG_MMCAU_HCLK_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CM4_LPCG_TCMC_HCLK Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_TCMC_HCLK_Peripheral_Access_Layer CM4_LPCG_TCMC_HCLK Peripheral Access Layer * @{ */ /** CM4_LPCG_TCMC_HCLK - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_TCMC_HCLK_0; /**< na, offset: 0x0 */ } CM4_LPCG_TCMC_HCLK_Type; /* ---------------------------------------------------------------------------- -- CM4_LPCG_TCMC_HCLK Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_TCMC_HCLK_Register_Masks CM4_LPCG_TCMC_HCLK Register Masks * @{ */ /*! @name LPCG_TCMC_HCLK_0 - na */ /*! @{ */ #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK (0x1U) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT (0U) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK (0x2U) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT (1U) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK (0x4U) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT (2U) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK (0x8U) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT (3U) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT (4U) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group CM4_LPCG_TCMC_HCLK_Register_Masks */ /* CM4_LPCG_TCMC_HCLK - Peripheral instance base addresses */ /** Peripheral CM4_0__LPCG_TCMC_HCLK base address */ #define CM4_0__LPCG_TCMC_HCLK_BASE (0x375E0000u) /** Peripheral CM4_0__LPCG_TCMC_HCLK base pointer */ #define CM4_0__LPCG_TCMC_HCLK ((CM4_LPCG_TCMC_HCLK_Type *)CM4_0__LPCG_TCMC_HCLK_BASE) /** Peripheral CM4_1__LPCG_TCMC_HCLK base address */ #define CM4_1__LPCG_TCMC_HCLK_BASE (0x415E0000u) /** Peripheral CM4_1__LPCG_TCMC_HCLK base pointer */ #define CM4_1__LPCG_TCMC_HCLK ((CM4_LPCG_TCMC_HCLK_Type *)CM4_1__LPCG_TCMC_HCLK_BASE) /** Array initializer of CM4_LPCG_TCMC_HCLK peripheral base addresses */ #define CM4_LPCG_TCMC_HCLK_BASE_ADDRS { CM4_0__LPCG_TCMC_HCLK_BASE, CM4_1__LPCG_TCMC_HCLK_BASE } /** Array initializer of CM4_LPCG_TCMC_HCLK peripheral base pointers */ #define CM4_LPCG_TCMC_HCLK_BASE_PTRS { CM4_0__LPCG_TCMC_HCLK, CM4_1__LPCG_TCMC_HCLK } /*! * @} */ /* end of group CM4_LPCG_TCMC_HCLK_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CM4_LPCG_TPM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_TPM_Peripheral_Access_Layer CM4_LPCG_TPM Peripheral Access Layer * @{ */ /** CM4_LPCG_TPM - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_TPM_0; /**< na, offset: 0x0 */ } CM4_LPCG_TPM_Type; /* ---------------------------------------------------------------------------- -- CM4_LPCG_TPM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_TPM_Register_Masks CM4_LPCG_TPM Register Masks * @{ */ /*! @name LPCG_TPM_0 - na */ /*! @{ */ #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK (0x1U) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT (0U) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK (0x2U) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT (1U) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK (0x4U) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT (2U) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK (0x8U) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT (3U) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK (0x10U) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT (4U) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK (0x20U) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT (5U) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK (0x40U) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT (6U) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK (0x80U) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT (7U) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK (0xFFFFFF00U) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT (8U) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK) /*! @} */ /*! * @} */ /* end of group CM4_LPCG_TPM_Register_Masks */ /* CM4_LPCG_TPM - Peripheral instance base addresses */ /** Peripheral CM4_0__LPCG_TPM base address */ #define CM4_0__LPCG_TPM_BASE (0x37600000u) /** Peripheral CM4_0__LPCG_TPM base pointer */ #define CM4_0__LPCG_TPM ((CM4_LPCG_TPM_Type *)CM4_0__LPCG_TPM_BASE) /** Peripheral CM4_1__LPCG_TPM base address */ #define CM4_1__LPCG_TPM_BASE (0x41600000u) /** Peripheral CM4_1__LPCG_TPM base pointer */ #define CM4_1__LPCG_TPM ((CM4_LPCG_TPM_Type *)CM4_1__LPCG_TPM_BASE) /** Array initializer of CM4_LPCG_TPM peripheral base addresses */ #define CM4_LPCG_TPM_BASE_ADDRS { CM4_0__LPCG_TPM_BASE, CM4_1__LPCG_TPM_BASE } /** Array initializer of CM4_LPCG_TPM peripheral base pointers */ #define CM4_LPCG_TPM_BASE_PTRS { CM4_0__LPCG_TPM, CM4_1__LPCG_TPM } /*! * @} */ /* end of group CM4_LPCG_TPM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_DTC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_DTC_Peripheral_Access_Layer CONNECTIVITY_LPCG_DTC Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_DTC - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_DTCP_0; /**< na, offset: 0x0 */ } CONNECTIVITY_LPCG_DTC_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_DTC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_DTC_Register_Masks CONNECTIVITY_LPCG_DTC Register Masks * @{ */ /*! @name LPCG_LPCG_DTCP_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_0_0_MASK (0x1U) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_0_0_SHIFT (0U) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_0_0_MASK) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_SWEN_AND_dtcp_mem_dtcp_mem_rom_clk_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_SWEN_AND_dtcp_mem_dtcp_mem_rom_clk_SWEN_SHIFT (1U) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_SWEN_AND_dtcp_mem_dtcp_mem_rom_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_SWEN_AND_dtcp_mem_dtcp_mem_rom_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_SWEN_AND_dtcp_mem_dtcp_mem_rom_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_2_2_SHIFT (2U) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_STOP_AND_dtcp_mem_dtcp_mem_rom_clk_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_STOP_AND_dtcp_mem_dtcp_mem_rom_clk_STOP_SHIFT (3U) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_STOP_AND_dtcp_mem_dtcp_mem_rom_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_STOP_AND_dtcp_mem_dtcp_mem_rom_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_STOP_AND_dtcp_mem_dtcp_mem_rom_clk_STOP_MASK) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_4_16_MASK (0x1FFF0U) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_4_16_SHIFT (4U) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_4_16_SHIFT)) & CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_4_16_MASK) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_SWEN_SHIFT (17U) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_18_18_SHIFT (18U) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_STOP_SHIFT (19U) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_STOP_MASK) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_20_31_MASK (0xFFF00000U) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_20_31_SHIFT (20U) #define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_20_31_SHIFT)) & CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_DTC_Register_Masks */ /* CONNECTIVITY_LPCG_DTC - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_DTCP base address */ #define CONNECTIVITY__LPCG_DTCP_BASE (0x5B250000u) /** Peripheral CONNECTIVITY__LPCG_DTCP base pointer */ #define CONNECTIVITY__LPCG_DTCP ((CONNECTIVITY_LPCG_DTC_Type *)CONNECTIVITY__LPCG_DTCP_BASE) /** Array initializer of CONNECTIVITY_LPCG_DTC peripheral base addresses */ #define CONNECTIVITY_LPCG_DTC_BASE_ADDRS { CONNECTIVITY__LPCG_DTCP_BASE } /** Array initializer of CONNECTIVITY_LPCG_DTC peripheral base pointers */ #define CONNECTIVITY_LPCG_DTC_BASE_PTRS { CONNECTIVITY__LPCG_DTCP } /*! * @} */ /* end of group CONNECTIVITY_LPCG_DTC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_EDMA Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_EDMA_Peripheral_Access_Layer CONNECTIVITY_LPCG_EDMA Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_EDMA - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_EDMA_0; /**< na, offset: 0x0 */ } CONNECTIVITY_LPCG_EDMA_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_EDMA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_EDMA_Register_Masks CONNECTIVITY_LPCG_EDMA Register Masks * @{ */ /*! @name LPCG_LPCG_EDMA_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_MASK (0x1U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_SHIFT (0U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_MASK) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_SHIFT (1U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_SHIFT (2U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_SHIFT (3U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_MASK) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_MASK (0x1FFF0U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_SHIFT (4U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_MASK) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_SHIFT (17U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_SHIFT (18U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_SHIFT (19U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_MASK) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_MASK (0xFFF00000U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_SHIFT (20U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_EDMA_Register_Masks */ /* CONNECTIVITY_LPCG_EDMA - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_EDMA base address */ #define CONNECTIVITY__LPCG_EDMA_BASE (0x5B2A0000u) /** Peripheral CONNECTIVITY__LPCG_EDMA base pointer */ #define CONNECTIVITY__LPCG_EDMA ((CONNECTIVITY_LPCG_EDMA_Type *)CONNECTIVITY__LPCG_EDMA_BASE) /** Array initializer of CONNECTIVITY_LPCG_EDMA peripheral base addresses */ #define CONNECTIVITY_LPCG_EDMA_BASE_ADDRS { CONNECTIVITY__LPCG_EDMA_BASE } /** Array initializer of CONNECTIVITY_LPCG_EDMA peripheral base pointers */ #define CONNECTIVITY_LPCG_EDMA_BASE_PTRS { CONNECTIVITY__LPCG_EDMA } /*! * @} */ /* end of group CONNECTIVITY_LPCG_EDMA_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_ENET0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_ENET0_Peripheral_Access_Layer CONNECTIVITY_LPCG_ENET0 Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_ENET0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_ENET1_0; /**< na, offset: 0x0 */ __IO uint32_t LPCG_LPCG_ENET1_4; /**< na, offset: 0x4 */ } CONNECTIVITY_LPCG_ENET0_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_ENET0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_ENET0_Register_Masks CONNECTIVITY_LPCG_ENET0 Register Masks * @{ */ /*! @name LPCG_LPCG_ENET1_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_MASK (0x1U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_SHIFT (0U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_SHIFT (1U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_SHIFT (2U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_SHIFT (3U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_MASK (0x10U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_SHIFT (4U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_MASK (0x20U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_SHIFT (5U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_MASK (0x40U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_SHIFT (6U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_MASK (0x80U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_SHIFT (7U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_MASK (0x100U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_SHIFT (8U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_MASK (0x200U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_SHIFT (9U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_MASK (0x400U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_SHIFT (10U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_MASK (0x800U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_SHIFT (11U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_MASK (0x1000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_SHIFT (12U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_MASK (0x2000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_SHIFT (13U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_MASK (0x4000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_SHIFT (14U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_MASK (0x8000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_SHIFT (15U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_MASK (0x10000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_SHIFT (16U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_SHIFT (17U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_SHIFT (18U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_SHIFT (19U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_MASK (0x100000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_SHIFT (20U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_MASK (0x200000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_SHIFT (21U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_MASK (0x400000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_SHIFT (22U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_MASK (0x800000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_SHIFT (23U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_MASK (0xFF000000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_SHIFT (24U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_MASK) /*! @} */ /*! @name LPCG_LPCG_ENET1_4 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_MASK (0x1U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_SHIFT (0U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_SHIFT (1U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_SHIFT (2U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_SHIFT (3U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_MASK (0xFFFFFFF0U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_SHIFT (4U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_ENET0_Register_Masks */ /* CONNECTIVITY_LPCG_ENET0 - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_ENET0 base address */ #define CONNECTIVITY__LPCG_ENET0_BASE (0x5B230000u) /** Peripheral CONNECTIVITY__LPCG_ENET0 base pointer */ #define CONNECTIVITY__LPCG_ENET0 ((CONNECTIVITY_LPCG_ENET0_Type *)CONNECTIVITY__LPCG_ENET0_BASE) /** Array initializer of CONNECTIVITY_LPCG_ENET0 peripheral base addresses */ #define CONNECTIVITY_LPCG_ENET0_BASE_ADDRS { CONNECTIVITY__LPCG_ENET0_BASE } /** Array initializer of CONNECTIVITY_LPCG_ENET0 peripheral base pointers */ #define CONNECTIVITY_LPCG_ENET0_BASE_PTRS { CONNECTIVITY__LPCG_ENET0 } /*! * @} */ /* end of group CONNECTIVITY_LPCG_ENET0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_ENET1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_ENET1_Peripheral_Access_Layer CONNECTIVITY_LPCG_ENET1 Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_ENET1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_ENET2_0; /**< na, offset: 0x0 */ __IO uint32_t LPCG_LPCG_ENET2_4; /**< na, offset: 0x4 */ } CONNECTIVITY_LPCG_ENET1_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_ENET1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_ENET1_Register_Masks CONNECTIVITY_LPCG_ENET1 Register Masks * @{ */ /*! @name LPCG_LPCG_ENET2_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_MASK (0x1U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_SHIFT (0U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_SHIFT (1U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_SHIFT (2U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_SHIFT (3U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_MASK (0x10U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_SHIFT (4U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_MASK (0x20U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_SHIFT (5U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_MASK (0x40U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_SHIFT (6U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_MASK (0x80U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_SHIFT (7U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_MASK (0x100U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_SHIFT (8U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_MASK (0x200U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_SHIFT (9U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_MASK (0x400U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_SHIFT (10U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_MASK (0x800U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_SHIFT (11U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_MASK (0x1000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_SHIFT (12U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_MASK (0x2000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_SHIFT (13U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_MASK (0x4000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_SHIFT (14U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_MASK (0x8000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_SHIFT (15U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_MASK (0x10000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_SHIFT (16U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_SHIFT (17U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_SHIFT (18U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_SHIFT (19U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_MASK (0x100000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_SHIFT (20U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_MASK (0x200000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_SHIFT (21U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_MASK (0x400000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_SHIFT (22U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_MASK (0x800000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_SHIFT (23U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_MASK (0xFF000000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_SHIFT (24U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_MASK) /*! @} */ /*! @name LPCG_LPCG_ENET2_4 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_MASK (0x1U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_SHIFT (0U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_SHIFT (1U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_SHIFT (2U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_SHIFT (3U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_MASK (0xFFFFFFF0U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_SHIFT (4U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_ENET1_Register_Masks */ /* CONNECTIVITY_LPCG_ENET1 - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_ENET1 base address */ #define CONNECTIVITY__LPCG_ENET1_BASE (0x5B240000u) /** Peripheral CONNECTIVITY__LPCG_ENET1 base pointer */ #define CONNECTIVITY__LPCG_ENET1 ((CONNECTIVITY_LPCG_ENET1_Type *)CONNECTIVITY__LPCG_ENET1_BASE) /** Array initializer of CONNECTIVITY_LPCG_ENET1 peripheral base addresses */ #define CONNECTIVITY_LPCG_ENET1_BASE_ADDRS { CONNECTIVITY__LPCG_ENET1_BASE } /** Array initializer of CONNECTIVITY_LPCG_ENET1 peripheral base pointers */ #define CONNECTIVITY_LPCG_ENET1_BASE_PTRS { CONNECTIVITY__LPCG_ENET1 } /*! * @} */ /* end of group CONNECTIVITY_LPCG_ENET1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_MLB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_MLB_Peripheral_Access_Layer CONNECTIVITY_LPCG_MLB Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_MLB - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_MLB_0; /**< na, offset: 0x0 */ } CONNECTIVITY_LPCG_MLB_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_MLB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_MLB_Register_Masks CONNECTIVITY_LPCG_MLB Register Masks * @{ */ /*! @name LPCG_LPCG_MLB_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_MASK (0x1U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_SHIFT (0U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_SHIFT (1U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_SHIFT (2U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_SHIFT (3U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_MASK (0xFFF0U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_SHIFT (4U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_MASK (0x10000U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_SHIFT (16U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_SHIFT (17U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_SHIFT (18U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_SHIFT (19U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_MASK (0x100000U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_SHIFT (20U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_MASK (0x200000U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_SHIFT (21U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_MASK (0x400000U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_SHIFT (22U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_MASK (0x800000U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_SHIFT (23U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_MASK (0xFF000000U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_SHIFT (24U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_MLB_Register_Masks */ /* CONNECTIVITY_LPCG_MLB - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_MLB base address */ #define CONNECTIVITY__LPCG_MLB_BASE (0x5B260000u) /** Peripheral CONNECTIVITY__LPCG_MLB base pointer */ #define CONNECTIVITY__LPCG_MLB ((CONNECTIVITY_LPCG_MLB_Type *)CONNECTIVITY__LPCG_MLB_BASE) /** Array initializer of CONNECTIVITY_LPCG_MLB peripheral base addresses */ #define CONNECTIVITY_LPCG_MLB_BASE_ADDRS { CONNECTIVITY__LPCG_MLB_BASE } /** Array initializer of CONNECTIVITY_LPCG_MLB peripheral base pointers */ #define CONNECTIVITY_LPCG_MLB_BASE_PTRS { CONNECTIVITY__LPCG_MLB } /*! * @} */ /* end of group CONNECTIVITY_LPCG_MLB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_RAWNAND Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_RAWNAND_Peripheral_Access_Layer CONNECTIVITY_LPCG_RAWNAND Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_RAWNAND - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_RAWNAND_0; /**< na, offset: 0x0 */ __IO uint32_t LPCG_LPCG_RAWNAND_4; /**< na, offset: 0x4 */ } CONNECTIVITY_LPCG_RAWNAND_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_RAWNAND Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_RAWNAND_Register_Masks CONNECTIVITY_LPCG_RAWNAND Register Masks * @{ */ /*! @name LPCG_LPCG_RAWNAND_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_MASK (0x1U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_SHIFT (0U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_SHIFT (1U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_SHIFT (2U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_SHIFT (3U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_MASK (0x10U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_SHIFT (4U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_MASK (0x20U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_SHIFT (5U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_MASK (0x40U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_SHIFT (6U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_MASK (0x80U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_SHIFT (7U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_MASK (0x1FF00U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_SHIFT (8U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_SHIFT (17U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_SHIFT (18U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_SHIFT (19U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_MASK (0x100000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_SHIFT (20U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_MASK (0x200000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_SHIFT (21U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_MASK (0x400000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_SHIFT (22U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_MASK (0x800000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_SHIFT (23U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_MASK (0xFF000000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_SHIFT (24U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_MASK) /*! @} */ /*! @name LPCG_LPCG_RAWNAND_4 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_MASK (0x1FFFFU) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_SHIFT (0U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_SHIFT (17U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_SHIFT (18U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_SHIFT (19U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_MASK (0xFFF00000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_SHIFT (20U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_RAWNAND_Register_Masks */ /* CONNECTIVITY_LPCG_RAWNAND - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_RAWNAND base address */ #define CONNECTIVITY__LPCG_RAWNAND_BASE (0x5B290000u) /** Peripheral CONNECTIVITY__LPCG_RAWNAND base pointer */ #define CONNECTIVITY__LPCG_RAWNAND ((CONNECTIVITY_LPCG_RAWNAND_Type *)CONNECTIVITY__LPCG_RAWNAND_BASE) /** Array initializer of CONNECTIVITY_LPCG_RAWNAND peripheral base addresses */ #define CONNECTIVITY_LPCG_RAWNAND_BASE_ADDRS { CONNECTIVITY__LPCG_RAWNAND_BASE } /** Array initializer of CONNECTIVITY_LPCG_RAWNAND peripheral base pointers */ #define CONNECTIVITY_LPCG_RAWNAND_BASE_PTRS { CONNECTIVITY__LPCG_RAWNAND } /*! * @} */ /* end of group CONNECTIVITY_LPCG_RAWNAND_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_USB2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_USB2_Peripheral_Access_Layer CONNECTIVITY_LPCG_USB2 Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_USB2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_USB2_0; /**< na, offset: 0x0 */ } CONNECTIVITY_LPCG_USB2_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_USB2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_USB2_Register_Masks CONNECTIVITY_LPCG_USB2 Register Masks * @{ */ /*! @name LPCG_LPCG_USB2_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_MASK (0x1FFFFU) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_SHIFT (0U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_SHIFT (17U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_SHIFT (18U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_SHIFT (19U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_MASK (0x100000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_SHIFT (20U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_MASK (0x200000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_SHIFT (21U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_MASK (0x400000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_SHIFT (22U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_MASK (0x800000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_SHIFT (23U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_MASK (0x1000000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_SHIFT (24U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_MASK (0x2000000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_SHIFT (25U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_MASK (0x4000000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_SHIFT (26U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_MASK (0x8000000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_SHIFT (27U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_MASK (0x10000000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_SHIFT (28U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_MASK (0x20000000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_SHIFT (29U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_MASK (0x40000000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_SHIFT (30U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_MASK (0x80000000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_SHIFT (31U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_USB2_Register_Masks */ /* CONNECTIVITY_LPCG_USB2 - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_USB2 base address */ #define CONNECTIVITY__LPCG_USB2_BASE (0x5B270000u) /** Peripheral CONNECTIVITY__LPCG_USB2 base pointer */ #define CONNECTIVITY__LPCG_USB2 ((CONNECTIVITY_LPCG_USB2_Type *)CONNECTIVITY__LPCG_USB2_BASE) /** Array initializer of CONNECTIVITY_LPCG_USB2 peripheral base addresses */ #define CONNECTIVITY_LPCG_USB2_BASE_ADDRS { CONNECTIVITY__LPCG_USB2_BASE } /** Array initializer of CONNECTIVITY_LPCG_USB2 peripheral base pointers */ #define CONNECTIVITY_LPCG_USB2_BASE_PTRS { CONNECTIVITY__LPCG_USB2 } /*! * @} */ /* end of group CONNECTIVITY_LPCG_USB2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_USB3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_USB3_Peripheral_Access_Layer CONNECTIVITY_LPCG_USB3 Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_USB3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_USB3_0; /**< na, offset: 0x0 */ } CONNECTIVITY_LPCG_USB3_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_USB3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_USB3_Register_Masks CONNECTIVITY_LPCG_USB3 Register Masks * @{ */ /*! @name LPCG_LPCG_USB3_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_MASK (0x1U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_SHIFT (0U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_SHIFT (1U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_SHIFT (2U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_SHIFT (3U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_MASK (0x10U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_SHIFT (4U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_MASK (0x20U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_SHIFT (5U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_MASK (0x40U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_SHIFT (6U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_MASK (0x80U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_SHIFT (7U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_MASK (0x1FF00U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_SHIFT (8U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_SHIFT (17U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_SHIFT (18U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_SHIFT (19U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_MASK (0x100000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_SHIFT (20U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_MASK (0x200000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_SHIFT (21U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_MASK (0x400000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_SHIFT (22U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_MASK (0x800000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_SHIFT (23U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_MASK (0x1000000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_SHIFT (24U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_MASK (0x2000000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_SHIFT (25U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_MASK (0x4000000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_SHIFT (26U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_MASK (0x8000000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_SHIFT (27U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_MASK (0x10000000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_SHIFT (28U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_MASK (0x20000000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_SHIFT (29U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_MASK (0x40000000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_SHIFT (30U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_MASK (0x80000000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_SHIFT (31U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_USB3_Register_Masks */ /* CONNECTIVITY_LPCG_USB3 - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_USB3 base address */ #define CONNECTIVITY__LPCG_USB3_BASE (0x5B280000u) /** Peripheral CONNECTIVITY__LPCG_USB3 base pointer */ #define CONNECTIVITY__LPCG_USB3 ((CONNECTIVITY_LPCG_USB3_Type *)CONNECTIVITY__LPCG_USB3_BASE) /** Array initializer of CONNECTIVITY_LPCG_USB3 peripheral base addresses */ #define CONNECTIVITY_LPCG_USB3_BASE_ADDRS { CONNECTIVITY__LPCG_USB3_BASE } /** Array initializer of CONNECTIVITY_LPCG_USB3 peripheral base pointers */ #define CONNECTIVITY_LPCG_USB3_BASE_PTRS { CONNECTIVITY__LPCG_USB3 } /*! * @} */ /* end of group CONNECTIVITY_LPCG_USB3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_USDHC0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_USDHC0_Peripheral_Access_Layer CONNECTIVITY_LPCG_USDHC0 Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_USDHC0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_USDHC1_0; /**< na, offset: 0x0 */ } CONNECTIVITY_LPCG_USDHC0_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_USDHC0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_USDHC0_Register_Masks CONNECTIVITY_LPCG_USDHC0 Register Masks * @{ */ /*! @name LPCG_LPCG_USDHC1_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_MASK (0x1U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_SHIFT (0U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_SHIFT (1U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_SHIFT (2U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_SHIFT (3U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_MASK (0xFFF0U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_SHIFT (4U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_MASK (0x10000U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_SHIFT (16U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_SHIFT (17U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_SHIFT (18U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_SHIFT (19U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_MASK (0x100000U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_SHIFT (20U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_MASK (0x200000U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_SHIFT (21U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_MASK (0x400000U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_SHIFT (22U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_MASK (0x800000U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_SHIFT (23U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_MASK (0xFF000000U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_SHIFT (24U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_USDHC0_Register_Masks */ /* CONNECTIVITY_LPCG_USDHC0 - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_USDHC0 base address */ #define CONNECTIVITY__LPCG_USDHC0_BASE (0x5B200000u) /** Peripheral CONNECTIVITY__LPCG_USDHC0 base pointer */ #define CONNECTIVITY__LPCG_USDHC0 ((CONNECTIVITY_LPCG_USDHC0_Type *)CONNECTIVITY__LPCG_USDHC0_BASE) /** Array initializer of CONNECTIVITY_LPCG_USDHC0 peripheral base addresses */ #define CONNECTIVITY_LPCG_USDHC0_BASE_ADDRS { CONNECTIVITY__LPCG_USDHC0_BASE } /** Array initializer of CONNECTIVITY_LPCG_USDHC0 peripheral base pointers */ #define CONNECTIVITY_LPCG_USDHC0_BASE_PTRS { CONNECTIVITY__LPCG_USDHC0 } /*! * @} */ /* end of group CONNECTIVITY_LPCG_USDHC0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_USDHC1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_USDHC1_Peripheral_Access_Layer CONNECTIVITY_LPCG_USDHC1 Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_USDHC1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_USDHC2_0; /**< na, offset: 0x0 */ } CONNECTIVITY_LPCG_USDHC1_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_USDHC1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_USDHC1_Register_Masks CONNECTIVITY_LPCG_USDHC1 Register Masks * @{ */ /*! @name LPCG_LPCG_USDHC2_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_MASK (0x1U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_SHIFT (0U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_SHIFT (1U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_SHIFT (2U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_SHIFT (3U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_MASK (0xFFF0U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_SHIFT (4U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_MASK (0x10000U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_SHIFT (16U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_SHIFT (17U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_SHIFT (18U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_SHIFT (19U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_MASK (0x100000U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_SHIFT (20U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_MASK (0x200000U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_SHIFT (21U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_MASK (0x400000U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_SHIFT (22U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_MASK (0x800000U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_SHIFT (23U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_MASK (0xFF000000U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_SHIFT (24U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_USDHC1_Register_Masks */ /* CONNECTIVITY_LPCG_USDHC1 - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_USDHC1 base address */ #define CONNECTIVITY__LPCG_USDHC1_BASE (0x5B210000u) /** Peripheral CONNECTIVITY__LPCG_USDHC1 base pointer */ #define CONNECTIVITY__LPCG_USDHC1 ((CONNECTIVITY_LPCG_USDHC1_Type *)CONNECTIVITY__LPCG_USDHC1_BASE) /** Array initializer of CONNECTIVITY_LPCG_USDHC1 peripheral base addresses */ #define CONNECTIVITY_LPCG_USDHC1_BASE_ADDRS { CONNECTIVITY__LPCG_USDHC1_BASE } /** Array initializer of CONNECTIVITY_LPCG_USDHC1 peripheral base pointers */ #define CONNECTIVITY_LPCG_USDHC1_BASE_PTRS { CONNECTIVITY__LPCG_USDHC1 } /*! * @} */ /* end of group CONNECTIVITY_LPCG_USDHC1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_USDHC2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_USDHC2_Peripheral_Access_Layer CONNECTIVITY_LPCG_USDHC2 Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_USDHC2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_USDHC3_0; /**< na, offset: 0x0 */ } CONNECTIVITY_LPCG_USDHC2_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_USDHC2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_USDHC2_Register_Masks CONNECTIVITY_LPCG_USDHC2 Register Masks * @{ */ /*! @name LPCG_LPCG_USDHC3_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_0_0_MASK (0x1U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_0_0_SHIFT (0U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_0_0_MASK) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_SWEN_SHIFT (1U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_SWEN_MASK) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_2_2_SHIFT (2U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_STOP_SHIFT (3U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_STOP_MASK) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_4_15_MASK (0xFFF0U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_4_15_SHIFT (4U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_4_15_MASK) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_HWEN_MASK (0x10000U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_HWEN_SHIFT (16U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_HWEN_MASK) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_SWEN_AND_usdhc3_ipg_clk_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_SWEN_AND_usdhc3_ipg_clk_SWEN_SHIFT (17U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_SWEN_AND_usdhc3_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_SWEN_AND_usdhc3_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_SWEN_AND_usdhc3_ipg_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_18_18_SHIFT (18U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_STOP_AND_usdhc3_ipg_clk_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_STOP_AND_usdhc3_ipg_clk_STOP_SHIFT (19U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_STOP_AND_usdhc3_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_STOP_AND_usdhc3_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_STOP_AND_usdhc3_ipg_clk_STOP_MASK) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_20_20_MASK (0x100000U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_20_20_SHIFT (20U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_20_20_MASK) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_SWEN_MASK (0x200000U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_SWEN_SHIFT (21U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_SWEN_MASK) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_22_22_MASK (0x400000U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_22_22_SHIFT (22U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_22_22_MASK) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_STOP_MASK (0x800000U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_STOP_SHIFT (23U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_STOP_MASK) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_24_31_MASK (0xFF000000U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_24_31_SHIFT (24U) #define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_USDHC2_Register_Masks */ /* CONNECTIVITY_LPCG_USDHC2 - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_USDHC2 base address */ #define CONNECTIVITY__LPCG_USDHC2_BASE (0x5B220000u) /** Peripheral CONNECTIVITY__LPCG_USDHC2 base pointer */ #define CONNECTIVITY__LPCG_USDHC2 ((CONNECTIVITY_LPCG_USDHC2_Type *)CONNECTIVITY__LPCG_USDHC2_BASE) /** Array initializer of CONNECTIVITY_LPCG_USDHC2 peripheral base addresses */ #define CONNECTIVITY_LPCG_USDHC2_BASE_ADDRS { CONNECTIVITY__LPCG_USDHC2_BASE } /** Array initializer of CONNECTIVITY_LPCG_USDHC2 peripheral base pointers */ #define CONNECTIVITY_LPCG_USDHC2_BASE_PTRS { CONNECTIVITY__LPCG_USDHC2 } /*! * @} */ /* end of group CONNECTIVITY_LPCG_USDHC2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DBLOG_LPCG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DBLOG_LPCG_Peripheral_Access_Layer DBLOG_LPCG Peripheral Access Layer * @{ */ /** DBLOG_LPCG - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_DBLOG_IDLE_0; /**< na, offset: 0x0 */ __IO uint32_t LPCG_LPCG_DBLOG_IDLE_4; /**< na, offset: 0x4 */ } DBLOG_LPCG_Type; /* ---------------------------------------------------------------------------- -- DBLOG_LPCG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DBLOG_LPCG_Register_Masks DBLOG_LPCG Register Masks * @{ */ /*! @name LPCG_LPCG_DBLOG_IDLE_0 - na */ /*! @{ */ #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_0_0_MASK (0x1U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_0_0_SHIFT (0U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_0_0_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_0_0_MASK) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_SWEN_MASK (0x2U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_SWEN_SHIFT (1U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_SWEN_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_SWEN_MASK) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_2_2_MASK (0x4U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_2_2_SHIFT (2U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_2_2_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_2_2_MASK) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_STOP_MASK (0x8U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_STOP_SHIFT (3U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_STOP_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_STOP_MASK) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_4_31_MASK (0xFFFFFFF0U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_4_31_SHIFT (4U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_4_31_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_LPCG_DBLOG_IDLE_4 - na */ /*! @{ */ #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_0_4_MASK (0x1FU) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_0_4_SHIFT (0U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_0_4(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_0_4_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_0_4_MASK) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_SWEN_MASK (0x20U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_SWEN_SHIFT (5U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_SWEN_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_SWEN_MASK) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_6_6_MASK (0x40U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_6_6_SHIFT (6U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_6_6_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_6_6_MASK) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_STOP_MASK (0x80U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_STOP_SHIFT (7U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_STOP_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_STOP_MASK) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_8_31_MASK (0xFFFFFF00U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_8_31_SHIFT (8U) #define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_8_31_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_8_31_MASK) /*! @} */ /*! * @} */ /* end of group DBLOG_LPCG_Register_Masks */ /* DBLOG_LPCG - Peripheral instance base addresses */ /** Peripheral DBLOG__LPCG_CLK base address */ #define DBLOG__LPCG_CLK_BASE (0x510F0000u) /** Peripheral DBLOG__LPCG_CLK base pointer */ #define DBLOG__LPCG_CLK ((DBLOG_LPCG_Type *)DBLOG__LPCG_CLK_BASE) /** Array initializer of DBLOG_LPCG peripheral base addresses */ #define DBLOG_LPCG_BASE_ADDRS { DBLOG__LPCG_CLK_BASE } /** Array initializer of DBLOG_LPCG peripheral base pointers */ #define DBLOG_LPCG_BASE_PTRS { DBLOG__LPCG_CLK } /*! * @} */ /* end of group DBLOG_LPCG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DB_LPCG_BN Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DB_LPCG_BN_Peripheral_Access_Layer DB_LPCG_BN Peripheral Access Layer * @{ */ /** DB_LPCG_BN - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_BN_0; /**< na, offset: 0x0 */ } DB_LPCG_BN_Type; /* ---------------------------------------------------------------------------- -- DB_LPCG_BN Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DB_LPCG_BN_Register_Masks DB_LPCG_BN Register Masks * @{ */ /*! @name LPCG_LPCG_BN_0 - na */ /*! @{ */ #define DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_0_0_MASK (0x1U) #define DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_0_0_SHIFT (0U) #define DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_0_0_SHIFT)) & DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_0_0_MASK) #define DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_SWEN_MASK (0x2U) #define DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_SWEN_SHIFT (1U) #define DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_SWEN_SHIFT)) & DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_SWEN_MASK) #define DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_2_2_MASK (0x4U) #define DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_2_2_SHIFT (2U) #define DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_2_2_SHIFT)) & DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_2_2_MASK) #define DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_STOP_MASK (0x8U) #define DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_STOP_SHIFT (3U) #define DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_STOP_SHIFT)) & DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_STOP_MASK) #define DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_4_31_MASK (0xFFFFFFF0U) #define DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_4_31_SHIFT (4U) #define DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_4_31_SHIFT)) & DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group DB_LPCG_BN_Register_Masks */ /* DB_LPCG_BN - Peripheral instance base addresses */ /** Peripheral DB__LPCG_BN_GATED base address */ #define DB__LPCG_BN_GATED_BASE (0x5CEF0000u) /** Peripheral DB__LPCG_BN_GATED base pointer */ #define DB__LPCG_BN_GATED ((DB_LPCG_BN_Type *)DB__LPCG_BN_GATED_BASE) /** Array initializer of DB_LPCG_BN peripheral base addresses */ #define DB_LPCG_BN_BASE_ADDRS { DB__LPCG_BN_GATED_BASE } /** Array initializer of DB_LPCG_BN peripheral base pointers */ #define DB_LPCG_BN_BASE_PTRS { DB__LPCG_BN_GATED } /*! * @} */ /* end of group DB_LPCG_BN_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DB_LPCG_PG0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DB_LPCG_PG0_Peripheral_Access_Layer DB_LPCG_PG0 Peripheral Access Layer * @{ */ /** DB_LPCG_PG0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_PG0_0; /**< na, offset: 0x0 */ } DB_LPCG_PG0_Type; /* ---------------------------------------------------------------------------- -- DB_LPCG_PG0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DB_LPCG_PG0_Register_Masks DB_LPCG_PG0 Register Masks * @{ */ /*! @name LPCG_LPCG_PG0_0 - na */ /*! @{ */ #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_0_0_MASK (0x1U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_0_0_SHIFT (0U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_0_0_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_0_0_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_SWEN_MASK (0x2U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_SWEN_SHIFT (1U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_SWEN_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_SWEN_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_2_2_MASK (0x4U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_2_2_SHIFT (2U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_2_2_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_2_2_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_STOP_MASK (0x8U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_STOP_SHIFT (3U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_STOP_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_STOP_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_4_4_MASK (0x10U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_4_4_SHIFT (4U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_4_4_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_4_4_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_SWEN_MASK (0x20U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_SWEN_SHIFT (5U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_SWEN_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_SWEN_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_6_6_MASK (0x40U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_6_6_SHIFT (6U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_6_6_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_6_6_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_STOP_MASK (0x80U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_STOP_SHIFT (7U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_STOP_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_STOP_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_8_8_MASK (0x100U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_8_8_SHIFT (8U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_8_8_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_8_8_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_SWEN_MASK (0x200U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_SWEN_SHIFT (9U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_SWEN_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_SWEN_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_10_10_MASK (0x400U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_10_10_SHIFT (10U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_10_10_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_10_10_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_STOP_MASK (0x800U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_STOP_SHIFT (11U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_STOP_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_STOP_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_12_12_MASK (0x1000U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_12_12_SHIFT (12U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_12_12_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_12_12_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_SWEN_MASK (0x2000U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_SWEN_SHIFT (13U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_SWEN_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_SWEN_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_14_14_MASK (0x4000U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_14_14_SHIFT (14U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_14_14_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_14_14_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_STOP_MASK (0x8000U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_STOP_SHIFT (15U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_STOP_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_STOP_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_16_16_MASK (0x10000U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_16_16_SHIFT (16U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_16_16(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_16_16_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_16_16_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_SWEN_MASK (0x20000U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_SWEN_SHIFT (17U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_SWEN_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_SWEN_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_18_18_MASK (0x40000U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_18_18_SHIFT (18U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_18_18_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_18_18_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_STOP_MASK (0x80000U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_STOP_SHIFT (19U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_STOP_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_STOP_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_20_20_MASK (0x100000U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_20_20_SHIFT (20U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_20_20_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_20_20_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_SWEN_MASK (0x200000U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_SWEN_SHIFT (21U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_SWEN_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_SWEN_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_22_22_MASK (0x400000U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_22_22_SHIFT (22U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_22_22_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_22_22_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_STOP_MASK (0x800000U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_STOP_SHIFT (23U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_STOP_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_STOP_MASK) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_24_31_MASK (0xFF000000U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_24_31_SHIFT (24U) #define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_24_31_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group DB_LPCG_PG0_Register_Masks */ /* DB_LPCG_PG0 - Peripheral instance base addresses */ /** Peripheral DB__LPCG_PG0 base address */ #define DB__LPCG_PG0_BASE (0x5C8F0000u) /** Peripheral DB__LPCG_PG0 base pointer */ #define DB__LPCG_PG0 ((DB_LPCG_PG0_Type *)DB__LPCG_PG0_BASE) /** Array initializer of DB_LPCG_PG0 peripheral base addresses */ #define DB_LPCG_PG0_BASE_ADDRS { DB__LPCG_PG0_BASE } /** Array initializer of DB_LPCG_PG0 peripheral base pointers */ #define DB_LPCG_PG0_BASE_PTRS { DB__LPCG_PG0 } /*! * @} */ /* end of group DB_LPCG_PG0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DB_LPCG_PG1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DB_LPCG_PG1_Peripheral_Access_Layer DB_LPCG_PG1 Peripheral Access Layer * @{ */ /** DB_LPCG_PG1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_PG1_0; /**< na, offset: 0x0 */ } DB_LPCG_PG1_Type; /* ---------------------------------------------------------------------------- -- DB_LPCG_PG1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DB_LPCG_PG1_Register_Masks DB_LPCG_PG1 Register Masks * @{ */ /*! @name LPCG_LPCG_PG1_0 - na */ /*! @{ */ #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_0_0_MASK (0x1U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_0_0_SHIFT (0U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_0_0_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_0_0_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_SWEN_MASK (0x2U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_SWEN_SHIFT (1U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_SWEN_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_SWEN_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_2_2_MASK (0x4U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_2_2_SHIFT (2U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_2_2_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_2_2_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_STOP_MASK (0x8U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_STOP_SHIFT (3U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_STOP_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_STOP_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_4_4_MASK (0x10U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_4_4_SHIFT (4U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_4_4_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_4_4_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_SWEN_MASK (0x20U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_SWEN_SHIFT (5U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_SWEN_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_SWEN_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_6_6_MASK (0x40U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_6_6_SHIFT (6U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_6_6_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_6_6_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_STOP_MASK (0x80U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_STOP_SHIFT (7U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_STOP_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_STOP_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_8_8_MASK (0x100U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_8_8_SHIFT (8U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_8_8_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_8_8_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_SWEN_MASK (0x200U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_SWEN_SHIFT (9U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_SWEN_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_SWEN_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_10_10_MASK (0x400U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_10_10_SHIFT (10U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_10_10_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_10_10_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_STOP_MASK (0x800U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_STOP_SHIFT (11U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_STOP_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_STOP_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_12_12_MASK (0x1000U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_12_12_SHIFT (12U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_12_12_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_12_12_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_SWEN_MASK (0x2000U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_SWEN_SHIFT (13U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_SWEN_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_SWEN_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_14_14_MASK (0x4000U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_14_14_SHIFT (14U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_14_14_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_14_14_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_STOP_MASK (0x8000U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_STOP_SHIFT (15U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_STOP_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_STOP_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_16_16_MASK (0x10000U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_16_16_SHIFT (16U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_16_16(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_16_16_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_16_16_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_SWEN_MASK (0x20000U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_SWEN_SHIFT (17U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_SWEN_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_SWEN_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_18_18_MASK (0x40000U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_18_18_SHIFT (18U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_18_18_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_18_18_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_STOP_MASK (0x80000U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_STOP_SHIFT (19U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_STOP_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_STOP_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_20_20_MASK (0x100000U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_20_20_SHIFT (20U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_20_20_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_20_20_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_SWEN_MASK (0x200000U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_SWEN_SHIFT (21U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_SWEN_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_SWEN_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_22_22_MASK (0x400000U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_22_22_SHIFT (22U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_22_22_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_22_22_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_STOP_MASK (0x800000U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_STOP_SHIFT (23U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_STOP_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_STOP_MASK) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_24_31_MASK (0xFF000000U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_24_31_SHIFT (24U) #define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_24_31_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group DB_LPCG_PG1_Register_Masks */ /* DB_LPCG_PG1 - Peripheral instance base addresses */ /** Peripheral DB__LPCG_PG1 base address */ #define DB__LPCG_PG1_BASE (0x5C9F0000u) /** Peripheral DB__LPCG_PG1 base pointer */ #define DB__LPCG_PG1 ((DB_LPCG_PG1_Type *)DB__LPCG_PG1_BASE) /** Array initializer of DB_LPCG_PG1 peripheral base addresses */ #define DB_LPCG_PG1_BASE_ADDRS { DB__LPCG_PG1_BASE } /** Array initializer of DB_LPCG_PG1 peripheral base pointers */ #define DB_LPCG_PG1_BASE_PTRS { DB__LPCG_PG1 } /*! * @} */ /* end of group DB_LPCG_PG1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DB_LPCG_PG2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DB_LPCG_PG2_Peripheral_Access_Layer DB_LPCG_PG2 Peripheral Access Layer * @{ */ /** DB_LPCG_PG2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_PG2_0; /**< na, offset: 0x0 */ } DB_LPCG_PG2_Type; /* ---------------------------------------------------------------------------- -- DB_LPCG_PG2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DB_LPCG_PG2_Register_Masks DB_LPCG_PG2 Register Masks * @{ */ /*! @name LPCG_LPCG_PG2_0 - na */ /*! @{ */ #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_0_0_MASK (0x1U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_0_0_SHIFT (0U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_0_0_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_0_0_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_SWEN_MASK (0x2U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_SWEN_SHIFT (1U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_SWEN_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_SWEN_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_2_2_MASK (0x4U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_2_2_SHIFT (2U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_2_2_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_2_2_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_STOP_MASK (0x8U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_STOP_SHIFT (3U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_STOP_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_STOP_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_4_4_MASK (0x10U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_4_4_SHIFT (4U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_4_4_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_4_4_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_SWEN_MASK (0x20U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_SWEN_SHIFT (5U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_SWEN_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_SWEN_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_6_6_MASK (0x40U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_6_6_SHIFT (6U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_6_6_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_6_6_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_STOP_MASK (0x80U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_STOP_SHIFT (7U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_STOP_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_STOP_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_8_8_MASK (0x100U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_8_8_SHIFT (8U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_8_8_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_8_8_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_SWEN_MASK (0x200U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_SWEN_SHIFT (9U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_SWEN_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_SWEN_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_10_10_MASK (0x400U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_10_10_SHIFT (10U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_10_10_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_10_10_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_STOP_MASK (0x800U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_STOP_SHIFT (11U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_STOP_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_STOP_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_12_12_MASK (0x1000U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_12_12_SHIFT (12U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_12_12_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_12_12_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_SWEN_MASK (0x2000U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_SWEN_SHIFT (13U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_SWEN_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_SWEN_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_14_14_MASK (0x4000U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_14_14_SHIFT (14U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_14_14_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_14_14_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_STOP_MASK (0x8000U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_STOP_SHIFT (15U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_STOP_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_STOP_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_16_16_MASK (0x10000U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_16_16_SHIFT (16U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_16_16(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_16_16_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_16_16_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_SWEN_MASK (0x20000U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_SWEN_SHIFT (17U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_SWEN_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_SWEN_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_18_18_MASK (0x40000U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_18_18_SHIFT (18U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_18_18_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_18_18_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_STOP_MASK (0x80000U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_STOP_SHIFT (19U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_STOP_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_STOP_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_20_20_MASK (0x100000U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_20_20_SHIFT (20U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_20_20_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_20_20_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_SWEN_MASK (0x200000U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_SWEN_SHIFT (21U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_SWEN_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_SWEN_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_22_22_MASK (0x400000U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_22_22_SHIFT (22U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_22_22_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_22_22_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_STOP_MASK (0x800000U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_STOP_SHIFT (23U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_STOP_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_STOP_MASK) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_24_31_MASK (0xFF000000U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_24_31_SHIFT (24U) #define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_24_31_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group DB_LPCG_PG2_Register_Masks */ /* DB_LPCG_PG2 - Peripheral instance base addresses */ /** Peripheral DB__LPCG_PG2 base address */ #define DB__LPCG_PG2_BASE (0x5CAF0000u) /** Peripheral DB__LPCG_PG2 base pointer */ #define DB__LPCG_PG2 ((DB_LPCG_PG2_Type *)DB__LPCG_PG2_BASE) /** Array initializer of DB_LPCG_PG2 peripheral base addresses */ #define DB_LPCG_PG2_BASE_ADDRS { DB__LPCG_PG2_BASE } /** Array initializer of DB_LPCG_PG2 peripheral base pointers */ #define DB_LPCG_PG2_BASE_PTRS { DB__LPCG_PG2 } /*! * @} */ /* end of group DB_LPCG_PG2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DB_LPCG_PG3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DB_LPCG_PG3_Peripheral_Access_Layer DB_LPCG_PG3 Peripheral Access Layer * @{ */ /** DB_LPCG_PG3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_PG3_0; /**< na, offset: 0x0 */ } DB_LPCG_PG3_Type; /* ---------------------------------------------------------------------------- -- DB_LPCG_PG3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DB_LPCG_PG3_Register_Masks DB_LPCG_PG3 Register Masks * @{ */ /*! @name LPCG_LPCG_PG3_0 - na */ /*! @{ */ #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_0_0_MASK (0x1U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_0_0_SHIFT (0U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_0_0_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_0_0_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_SWEN_MASK (0x2U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_SWEN_SHIFT (1U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_SWEN_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_SWEN_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_2_2_MASK (0x4U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_2_2_SHIFT (2U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_2_2_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_2_2_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_STOP_MASK (0x8U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_STOP_SHIFT (3U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_STOP_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_STOP_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_4_4_MASK (0x10U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_4_4_SHIFT (4U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_4_4_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_4_4_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_SWEN_MASK (0x20U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_SWEN_SHIFT (5U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_SWEN_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_SWEN_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_6_6_MASK (0x40U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_6_6_SHIFT (6U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_6_6_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_6_6_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_STOP_MASK (0x80U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_STOP_SHIFT (7U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_STOP_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_STOP_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_8_8_MASK (0x100U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_8_8_SHIFT (8U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_8_8_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_8_8_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_SWEN_MASK (0x200U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_SWEN_SHIFT (9U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_SWEN_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_SWEN_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_10_10_MASK (0x400U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_10_10_SHIFT (10U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_10_10_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_10_10_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_STOP_MASK (0x800U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_STOP_SHIFT (11U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_STOP_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_STOP_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_12_12_MASK (0x1000U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_12_12_SHIFT (12U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_12_12_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_12_12_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_SWEN_MASK (0x2000U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_SWEN_SHIFT (13U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_SWEN_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_SWEN_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_14_14_MASK (0x4000U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_14_14_SHIFT (14U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_14_14_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_14_14_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_STOP_MASK (0x8000U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_STOP_SHIFT (15U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_STOP_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_STOP_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_16_16_MASK (0x10000U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_16_16_SHIFT (16U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_16_16(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_16_16_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_16_16_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_SWEN_MASK (0x20000U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_SWEN_SHIFT (17U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_SWEN_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_SWEN_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_18_18_MASK (0x40000U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_18_18_SHIFT (18U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_18_18_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_18_18_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_STOP_MASK (0x80000U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_STOP_SHIFT (19U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_STOP_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_STOP_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_20_20_MASK (0x100000U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_20_20_SHIFT (20U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_20_20_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_20_20_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_SWEN_MASK (0x200000U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_SWEN_SHIFT (21U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_SWEN_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_SWEN_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_22_22_MASK (0x400000U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_22_22_SHIFT (22U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_22_22_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_22_22_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_STOP_MASK (0x800000U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_STOP_SHIFT (23U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_STOP_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_STOP_MASK) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_24_31_MASK (0xFF000000U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_24_31_SHIFT (24U) #define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_24_31_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group DB_LPCG_PG3_Register_Masks */ /* DB_LPCG_PG3 - Peripheral instance base addresses */ /** Peripheral DB__LPCG_PG3 base address */ #define DB__LPCG_PG3_BASE (0x5CBF0000u) /** Peripheral DB__LPCG_PG3 base pointer */ #define DB__LPCG_PG3 ((DB_LPCG_PG3_Type *)DB__LPCG_PG3_BASE) /** Array initializer of DB_LPCG_PG3 peripheral base addresses */ #define DB_LPCG_PG3_BASE_ADDRS { DB__LPCG_PG3_BASE } /** Array initializer of DB_LPCG_PG3 peripheral base pointers */ #define DB_LPCG_PG3_BASE_PTRS { DB__LPCG_PG3 } /*! * @} */ /* end of group DB_LPCG_PG3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DC_LPCG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DC_LPCG_Peripheral_Access_Layer DC_LPCG Peripheral Access Layer * @{ */ /** DC_LPCG - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_DC_LPCG_0; /**< na, offset: 0x0 */ __IO uint32_t LPCG_DC_LPCG_4; /**< na, offset: 0x4 */ __IO uint32_t LPCG_DC_LPCG_8; /**< na, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t LPCG_DC_LPCG_16; /**< na, offset: 0x10 */ __IO uint32_t LPCG_DC_LPCG_20; /**< na, offset: 0x14 */ __IO uint32_t LPCG_DC_LPCG_24; /**< na, offset: 0x18 */ __IO uint32_t LPCG_DC_LPCG_28; /**< na, offset: 0x1C */ __IO uint32_t LPCG_DC_LPCG_32; /**< na, offset: 0x20 */ __IO uint32_t LPCG_DC_LPCG_36; /**< na, offset: 0x24 */ __IO uint32_t LPCG_DC_LPCG_40; /**< na, offset: 0x28 */ __IO uint32_t LPCG_DC_LPCG_44; /**< na, offset: 0x2C */ __IO uint32_t LPCG_DC_LPCG_48; /**< na, offset: 0x30 */ __IO uint32_t LPCG_DC_LPCG_52; /**< na, offset: 0x34 */ __IO uint32_t LPCG_DC_LPCG_56; /**< na, offset: 0x38 */ __IO uint32_t LPCG_DC_LPCG_60; /**< na, offset: 0x3C */ __IO uint32_t LPCG_DC_LPCG_64; /**< na, offset: 0x40 */ __IO uint32_t LPCG_DC_LPCG_68; /**< na, offset: 0x44 */ __IO uint32_t LPCG_DC_LPCG_72; /**< na, offset: 0x48 */ } DC_LPCG_Type; /* ---------------------------------------------------------------------------- -- DC_LPCG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DC_LPCG_Register_Masks DC_LPCG Register Masks * @{ */ /*! @name LPCG_DC_LPCG_0 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_SHIFT (0U) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_SHIFT (1U) #define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_SHIFT (2U) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_SHIFT (3U) #define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_MASK (0x10U) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_SHIFT (4U) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_MASK) #define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_MASK (0x20U) #define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_SHIFT (5U) #define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_MASK (0x40U) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_SHIFT (6U) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_MASK) #define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_MASK (0x80U) #define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_SHIFT (7U) #define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_MASK (0xFFFFFF00U) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_SHIFT (8U) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_4 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_MASK (0xFFFFU) #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_SHIFT (0U) #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_SHIFT (16U) #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_SHIFT (17U) #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_SHIFT (18U) #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_SHIFT (19U) #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_SHIFT (20U) #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_8 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_MASK (0xFFFFU) #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_SHIFT (0U) #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_SHIFT (16U) #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_SHIFT (17U) #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_SHIFT (18U) #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_SHIFT (19U) #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_SHIFT (20U) #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_16 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_MASK (0xFFFFU) #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_SHIFT (0U) #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_SHIFT (16U) #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_SHIFT (17U) #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_SHIFT (18U) #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_SHIFT (19U) #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_SHIFT (20U) #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_20 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_MASK (0xFFFFU) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_SHIFT (0U) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_SHIFT (16U) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_SHIFT (17U) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_SHIFT (18U) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_SHIFT (19U) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_MASK (0x100000U) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_SHIFT (20U) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_MASK) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_MASK (0x200000U) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_SHIFT (21U) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_MASK (0x400000U) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_SHIFT (22U) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_MASK) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_MASK (0x800000U) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_SHIFT (23U) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_MASK (0xFF000000U) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_SHIFT (24U) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_24 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_MASK (0xFFFFU) #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_SHIFT (0U) #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_SHIFT (16U) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_SHIFT (17U) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_SHIFT (18U) #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_SHIFT (19U) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_MASK (0x100000U) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_SHIFT (20U) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_MASK (0x200000U) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_SHIFT (21U) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_MASK (0x400000U) #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_SHIFT (22U) #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_MASK) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_MASK (0x800000U) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_SHIFT (23U) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_MASK (0xFF000000U) #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_SHIFT (24U) #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_28 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_SHIFT (0U) #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_SHIFT (1U) #define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_SHIFT (2U) #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_SHIFT (3U) #define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_MASK (0xFFFFFFF0U) #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_SHIFT (4U) #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_32 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_SHIFT (0U) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_SHIFT (1U) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_SHIFT (2U) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_SHIFT (3U) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_MASK (0xFFF0U) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_SHIFT (4U) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_SHIFT (16U) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_SHIFT (17U) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_SHIFT (18U) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_SHIFT (19U) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_SHIFT (20U) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_36 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_SHIFT (0U) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_SHIFT (1U) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_SHIFT (2U) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_SHIFT (3U) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_MASK (0xFFF0U) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_SHIFT (4U) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_SHIFT (16U) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_SHIFT (17U) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_SHIFT (18U) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_SHIFT (19U) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_SHIFT (20U) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_40 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_SHIFT (0U) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_SHIFT (1U) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_SHIFT (2U) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_SHIFT (3U) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_MASK (0xFFF0U) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_SHIFT (4U) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_SHIFT (16U) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_SHIFT (17U) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_SHIFT (18U) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_SHIFT (19U) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_SHIFT (20U) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_44 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_MASK (0xFFFFU) #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_SHIFT (0U) #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_SHIFT (16U) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_SHIFT (17U) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_SHIFT (18U) #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_SHIFT (19U) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_MASK (0x100000U) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_SHIFT (20U) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_MASK (0x200000U) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_SHIFT (21U) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_MASK (0x400000U) #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_SHIFT (22U) #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_MASK) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_MASK (0x800000U) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_SHIFT (23U) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_MASK (0xFF000000U) #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_SHIFT (24U) #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_48 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_SHIFT (0U) #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_SHIFT (1U) #define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_SHIFT (2U) #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_SHIFT (3U) #define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_MASK (0xFFFFFFF0U) #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_SHIFT (4U) #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_52 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_SHIFT (0U) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_SHIFT (1U) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_SHIFT (2U) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_SHIFT (3U) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_MASK (0xFFF0U) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_SHIFT (4U) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_SHIFT (16U) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_SHIFT (17U) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_SHIFT (18U) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_SHIFT (19U) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_SHIFT (20U) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_56 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_SHIFT (0U) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_SHIFT (1U) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_SHIFT (2U) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_SHIFT (3U) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_MASK (0xFFF0U) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_SHIFT (4U) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_SHIFT (16U) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_SHIFT (17U) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_SHIFT (18U) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_SHIFT (19U) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_SHIFT (20U) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_60 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_SHIFT (0U) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_SHIFT (1U) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_SHIFT (2U) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_SHIFT (3U) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_MASK (0xFFF0U) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_SHIFT (4U) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_SHIFT (16U) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_SHIFT (17U) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_SHIFT (18U) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_SHIFT (19U) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_SHIFT (20U) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_64 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_SHIFT (0U) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_SHIFT (1U) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_SHIFT (2U) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_SHIFT (3U) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_MASK (0xFFF0U) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_SHIFT (4U) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_SHIFT (16U) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_SHIFT (17U) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_SHIFT (18U) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_SHIFT (19U) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_SHIFT (20U) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_68 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_SHIFT (0U) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_SHIFT (1U) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_SHIFT (2U) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_SHIFT (3U) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_MASK (0xFFF0U) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_SHIFT (4U) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_SHIFT (16U) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_SHIFT (17U) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_SHIFT (18U) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_SHIFT (19U) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_SHIFT (20U) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_72 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_SHIFT (0U) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_SHIFT (1U) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_SHIFT (2U) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_SHIFT (3U) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_MASK (0xFFF0U) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_SHIFT (4U) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_SHIFT (16U) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_SHIFT (17U) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_SHIFT (18U) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_SHIFT (19U) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_SHIFT (20U) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DC_LPCG_Register_Masks */ /* DC_LPCG - Peripheral instance base addresses */ /** Peripheral DC_0__LPCG_DSP0_CLK base address */ #define DC_0__LPCG_DSP0_CLK_BASE (0x56010000u) /** Peripheral DC_0__LPCG_DSP0_CLK base pointer */ #define DC_0__LPCG_DSP0_CLK ((DC_LPCG_Type *)DC_0__LPCG_DSP0_CLK_BASE) /** Peripheral DC_1__LPCG_DSP0_CLK base address */ #define DC_1__LPCG_DSP0_CLK_BASE (0x57010000u) /** Peripheral DC_1__LPCG_DSP0_CLK base pointer */ #define DC_1__LPCG_DSP0_CLK ((DC_LPCG_Type *)DC_1__LPCG_DSP0_CLK_BASE) /** Array initializer of DC_LPCG peripheral base addresses */ #define DC_LPCG_BASE_ADDRS { DC_0__LPCG_DSP0_CLK_BASE, DC_1__LPCG_DSP0_CLK_BASE } /** Array initializer of DC_LPCG peripheral base pointers */ #define DC_LPCG_BASE_PTRS { DC_0__LPCG_DSP0_CLK, DC_1__LPCG_DSP0_CLK } /*! * @} */ /* end of group DC_LPCG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DI_HDMI_LPCG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DI_HDMI_LPCG_Peripheral_Access_Layer DI_HDMI_LPCG Peripheral Access Layer * @{ */ /** DI_HDMI_LPCG - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_DI_HDMI_LPCG_0; /**< na, offset: 0x0 */ __IO uint32_t LPCG_DI_HDMI_LPCG_4; /**< na, offset: 0x4 */ __IO uint32_t LPCG_DI_HDMI_LPCG_8; /**< na, offset: 0x8 */ __IO uint32_t LPCG_DI_HDMI_LPCG_12; /**< na, offset: 0xC */ __IO uint32_t LPCG_DI_HDMI_LPCG_16; /**< na, offset: 0x10 */ __IO uint32_t LPCG_DI_HDMI_LPCG_20; /**< na, offset: 0x14 */ __IO uint32_t LPCG_DI_HDMI_LPCG_24; /**< na, offset: 0x18 */ __IO uint32_t LPCG_DI_HDMI_LPCG_28; /**< na, offset: 0x1C */ __IO uint32_t LPCG_DI_HDMI_LPCG_32; /**< na, offset: 0x20 */ __IO uint32_t LPCG_DI_HDMI_LPCG_36; /**< na, offset: 0x24 */ __IO uint32_t LPCG_DI_HDMI_LPCG_40; /**< na, offset: 0x28 */ __IO uint32_t LPCG_DI_HDMI_LPCG_44; /**< na, offset: 0x2C */ } DI_HDMI_LPCG_Type; /* ---------------------------------------------------------------------------- -- DI_HDMI_LPCG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DI_HDMI_LPCG_Register_Masks DI_HDMI_LPCG Register Masks * @{ */ /*! @name LPCG_DI_HDMI_LPCG_0 - na */ /*! @{ */ #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_div_clk_HWEN_MASK (0x1U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_div_clk_HWEN_SHIFT (0U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_div_clk_HWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_div_clk_HWEN_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_SWEN_AND_hdp_i2c_lpi2c_div_clk_SWEN_MASK (0x2U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_SWEN_AND_hdp_i2c_lpi2c_div_clk_SWEN_SHIFT (1U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_SWEN_AND_hdp_i2c_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_SWEN_AND_hdp_i2c_lpi2c_div_clk_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_SWEN_AND_hdp_i2c_lpi2c_div_clk_SWEN_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_2_2_MASK (0x4U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_2_2_SHIFT (2U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_2_2_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_2_2_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_STOP_AND_hdp_i2c_lpi2c_div_clk_STOP_MASK (0x8U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_STOP_AND_hdp_i2c_lpi2c_div_clk_STOP_SHIFT (3U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_STOP_AND_hdp_i2c_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_STOP_AND_hdp_i2c_lpi2c_div_clk_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_STOP_AND_hdp_i2c_lpi2c_div_clk_STOP_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_4_15_MASK (0xFFF0U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_4_15_SHIFT (4U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_4_15_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_4_15_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_s_HWEN_MASK (0x10000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_s_HWEN_SHIFT (16U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_s_HWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_s_HWEN_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_SWEN_AND_hdp_i2c_ipg_clk_s_SWEN_MASK (0x20000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_SWEN_AND_hdp_i2c_ipg_clk_s_SWEN_SHIFT (17U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_SWEN_AND_hdp_i2c_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_SWEN_AND_hdp_i2c_ipg_clk_s_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_SWEN_AND_hdp_i2c_ipg_clk_s_SWEN_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_18_18_MASK (0x40000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_18_18_SHIFT (18U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_18_18_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_18_18_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_STOP_AND_hdp_i2c_ipg_clk_s_STOP_MASK (0x80000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_STOP_AND_hdp_i2c_ipg_clk_s_STOP_SHIFT (19U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_STOP_AND_hdp_i2c_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_STOP_AND_hdp_i2c_ipg_clk_s_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_STOP_AND_hdp_i2c_ipg_clk_s_STOP_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_20_31_MASK (0xFFF00000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_20_31_SHIFT (20U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_20_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DI_HDMI_LPCG_4 - na */ /*! @{ */ #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_0_16_MASK (0x1FFFFU) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_0_16_SHIFT (0U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_0_16_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_0_16_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_SWEN_MASK (0x20000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_SWEN_SHIFT (17U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_SWEN_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_18_18_MASK (0x40000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_18_18_SHIFT (18U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_18_18_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_18_18_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_STOP_MASK (0x80000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_STOP_SHIFT (19U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_STOP_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_20_31_MASK (0xFFF00000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_20_31_SHIFT (20U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_20_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DI_HDMI_LPCG_8 - na */ /*! @{ */ #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_0_15_MASK (0xFFFFU) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_0_15_SHIFT (0U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_0_15_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_0_15_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_HWEN_AND_hdp_pwm_ipg_clk_s_HWEN_MASK (0x10000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_HWEN_AND_hdp_pwm_ipg_clk_s_HWEN_SHIFT (16U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_HWEN_AND_hdp_pwm_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_HWEN_AND_hdp_pwm_ipg_clk_s_HWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_HWEN_AND_hdp_pwm_ipg_clk_s_HWEN_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_SWEN_AND_hdp_pwm_ipg_clk_s_SWEN_AND_hdp_pwm_ipg_clk_highfreq_SWEN_AND_hdp_pwm_ipg_clk_32k_SWEN_MASK (0x20000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_SWEN_AND_hdp_pwm_ipg_clk_s_SWEN_AND_hdp_pwm_ipg_clk_highfreq_SWEN_AND_hdp_pwm_ipg_clk_32k_SWEN_SHIFT (17U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_SWEN_AND_hdp_pwm_ipg_clk_s_SWEN_AND_hdp_pwm_ipg_clk_highfreq_SWEN_AND_hdp_pwm_ipg_clk_32k_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_SWEN_AND_hdp_pwm_ipg_clk_s_SWEN_AND_hdp_pwm_ipg_clk_highfreq_SWEN_AND_hdp_pwm_ipg_clk_32k_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_SWEN_AND_hdp_pwm_ipg_clk_s_SWEN_AND_hdp_pwm_ipg_clk_highfreq_SWEN_AND_hdp_pwm_ipg_clk_32k_SWEN_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_18_18_MASK (0x40000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_18_18_SHIFT (18U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_18_18_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_18_18_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_STOP_AND_hdp_pwm_ipg_clk_s_STOP_AND_hdp_pwm_ipg_clk_highfreq_STOP_AND_hdp_pwm_ipg_clk_32k_STOP_MASK (0x80000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_STOP_AND_hdp_pwm_ipg_clk_s_STOP_AND_hdp_pwm_ipg_clk_highfreq_STOP_AND_hdp_pwm_ipg_clk_32k_STOP_SHIFT (19U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_STOP_AND_hdp_pwm_ipg_clk_s_STOP_AND_hdp_pwm_ipg_clk_highfreq_STOP_AND_hdp_pwm_ipg_clk_32k_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_STOP_AND_hdp_pwm_ipg_clk_s_STOP_AND_hdp_pwm_ipg_clk_highfreq_STOP_AND_hdp_pwm_ipg_clk_32k_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_STOP_AND_hdp_pwm_ipg_clk_s_STOP_AND_hdp_pwm_ipg_clk_highfreq_STOP_AND_hdp_pwm_ipg_clk_32k_STOP_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_20_31_MASK (0xFFF00000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_20_31_SHIFT (20U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_20_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DI_HDMI_LPCG_12 - na */ /*! @{ */ #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_0_0_MASK (0x1U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_0_0_SHIFT (0U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_0_0_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_0_0_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_SWEN_MASK (0x2U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_SWEN_SHIFT (1U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_SWEN_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_2_2_MASK (0x4U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_2_2_SHIFT (2U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_2_2_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_2_2_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_STOP_MASK (0x8U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_STOP_SHIFT (3U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_STOP_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_4_31_SHIFT (4U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_4_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DI_HDMI_LPCG_16 - na */ /*! @{ */ #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_0_15_MASK (0xFFFFU) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_0_15_SHIFT (0U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_0_15_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_0_15_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_HWEN_MASK (0x10000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_HWEN_SHIFT (16U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_HWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_HWEN_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_SWEN_MASK (0x20000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_SWEN_SHIFT (17U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_SWEN_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_18_18_MASK (0x40000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_18_18_SHIFT (18U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_18_18_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_18_18_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_STOP_MASK (0x80000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_STOP_SHIFT (19U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_STOP_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_20_31_MASK (0xFFF00000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_20_31_SHIFT (20U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_20_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DI_HDMI_LPCG_20 - na */ /*! @{ */ #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_0_0_MASK (0x1U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_0_0_SHIFT (0U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_0_0_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_0_0_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_SWEN_MASK (0x2U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_SWEN_SHIFT (1U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_SWEN_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_2_2_MASK (0x4U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_2_2_SHIFT (2U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_2_2_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_2_2_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_STOP_MASK (0x8U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_STOP_SHIFT (3U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_STOP_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_4_31_SHIFT (4U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_4_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DI_HDMI_LPCG_24 - na */ /*! @{ */ #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_0_0_MASK (0x1U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_0_0_SHIFT (0U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_0_0_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_0_0_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_SWEN_AND_pixel_link_slv_even_ingress_clk_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_SWEN_AND_ss_di_hdmi_pxl_mux_double_clk_SWEN_AND_hdp_ctrl_phy_source_core_clk_SWEN_MASK (0x2U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_SWEN_AND_pixel_link_slv_even_ingress_clk_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_SWEN_AND_ss_di_hdmi_pxl_mux_double_clk_SWEN_AND_hdp_ctrl_phy_source_core_clk_SWEN_SHIFT (1U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_SWEN_AND_pixel_link_slv_even_ingress_clk_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_SWEN_AND_ss_di_hdmi_pxl_mux_double_clk_SWEN_AND_hdp_ctrl_phy_source_core_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_SWEN_AND_pixel_link_slv_even_ingress_clk_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_SWEN_AND_ss_di_hdmi_pxl_mux_double_clk_SWEN_AND_hdp_ctrl_phy_source_core_clk_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_SWEN_AND_pixel_link_slv_even_ingress_clk_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_SWEN_AND_ss_di_hdmi_pxl_mux_double_clk_SWEN_AND_hdp_ctrl_phy_source_core_clk_SWEN_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_2_2_MASK (0x4U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_2_2_SHIFT (2U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_2_2_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_2_2_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_STOP_AND_pixel_link_slv_even_ingress_clk_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_STOP_AND_ss_di_hdmi_pxl_mux_double_clk_STOP_AND_hdp_ctrl_phy_source_core_clk_STOP_MASK (0x8U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_STOP_AND_pixel_link_slv_even_ingress_clk_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_STOP_AND_ss_di_hdmi_pxl_mux_double_clk_STOP_AND_hdp_ctrl_phy_source_core_clk_STOP_SHIFT (3U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_STOP_AND_pixel_link_slv_even_ingress_clk_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_STOP_AND_ss_di_hdmi_pxl_mux_double_clk_STOP_AND_hdp_ctrl_phy_source_core_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_STOP_AND_pixel_link_slv_even_ingress_clk_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_STOP_AND_ss_di_hdmi_pxl_mux_double_clk_STOP_AND_hdp_ctrl_phy_source_core_clk_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_STOP_AND_pixel_link_slv_even_ingress_clk_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_STOP_AND_ss_di_hdmi_pxl_mux_double_clk_STOP_AND_hdp_ctrl_phy_source_core_clk_STOP_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_4_31_SHIFT (4U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_4_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DI_HDMI_LPCG_28 - na */ /*! @{ */ #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_0_0_MASK (0x1U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_0_0_SHIFT (0U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_0_0_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_0_0_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_SWEN_MASK (0x2U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_SWEN_SHIFT (1U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_SWEN_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_2_2_MASK (0x4U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_2_2_SHIFT (2U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_2_2_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_2_2_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_STOP_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_STOP_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_STOP_MASK (0x8U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_STOP_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_STOP_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_STOP_SHIFT (3U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_STOP_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_STOP_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_STOP_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_STOP_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_STOP_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_STOP_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_STOP_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_4_16_MASK (0x1FFF0U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_4_16_SHIFT (4U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_4_16_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_4_16_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_SWEN_AND_hdp_ctrl_phy_source_sclk_SWEN_AND_hdp_ctrl_phy_source_cclk_SWEN_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_SWEN_AND_hdp_ctrl_phy_source_ref_clk_in_SWEN_MASK (0x20000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_SWEN_AND_hdp_ctrl_phy_source_sclk_SWEN_AND_hdp_ctrl_phy_source_cclk_SWEN_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_SWEN_AND_hdp_ctrl_phy_source_ref_clk_in_SWEN_SHIFT (17U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_SWEN_AND_hdp_ctrl_phy_source_sclk_SWEN_AND_hdp_ctrl_phy_source_cclk_SWEN_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_SWEN_AND_hdp_ctrl_phy_source_ref_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_SWEN_AND_hdp_ctrl_phy_source_sclk_SWEN_AND_hdp_ctrl_phy_source_cclk_SWEN_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_SWEN_AND_hdp_ctrl_phy_source_ref_clk_in_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_SWEN_AND_hdp_ctrl_phy_source_sclk_SWEN_AND_hdp_ctrl_phy_source_cclk_SWEN_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_SWEN_AND_hdp_ctrl_phy_source_ref_clk_in_SWEN_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_18_18_MASK (0x40000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_18_18_SHIFT (18U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_18_18_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_18_18_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_STOP_AND_hdp_ctrl_phy_source_sclk_STOP_AND_hdp_ctrl_phy_source_cclk_STOP_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_STOP_AND_hdp_ctrl_phy_source_ref_clk_in_STOP_MASK (0x80000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_STOP_AND_hdp_ctrl_phy_source_sclk_STOP_AND_hdp_ctrl_phy_source_cclk_STOP_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_STOP_AND_hdp_ctrl_phy_source_ref_clk_in_STOP_SHIFT (19U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_STOP_AND_hdp_ctrl_phy_source_sclk_STOP_AND_hdp_ctrl_phy_source_cclk_STOP_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_STOP_AND_hdp_ctrl_phy_source_ref_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_STOP_AND_hdp_ctrl_phy_source_sclk_STOP_AND_hdp_ctrl_phy_source_cclk_STOP_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_STOP_AND_hdp_ctrl_phy_source_ref_clk_in_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_STOP_AND_hdp_ctrl_phy_source_sclk_STOP_AND_hdp_ctrl_phy_source_cclk_STOP_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_STOP_AND_hdp_ctrl_phy_source_ref_clk_in_STOP_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_20_31_MASK (0xFFF00000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_20_31_SHIFT (20U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_20_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DI_HDMI_LPCG_32 - na */ /*! @{ */ #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_0_16_MASK (0x1FFFFU) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_0_16_SHIFT (0U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_0_16_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_0_16_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_SWEN_MASK (0x20000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_SWEN_SHIFT (17U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_SWEN_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_18_18_MASK (0x40000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_18_18_SHIFT (18U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_18_18_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_18_18_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_STOP_MASK (0x80000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_STOP_SHIFT (19U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_STOP_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_20_31_MASK (0xFFF00000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_20_31_SHIFT (20U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_20_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DI_HDMI_LPCG_36 - na */ /*! @{ */ #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_0_16_MASK (0x1FFFFU) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_0_16_SHIFT (0U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_0_16_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_0_16_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_SWEN_MASK (0x20000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_SWEN_SHIFT (17U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_SWEN_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_18_18_MASK (0x40000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_18_18_SHIFT (18U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_18_18_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_18_18_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_STOP_MASK (0x80000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_STOP_SHIFT (19U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_STOP_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_20_31_MASK (0xFFF00000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_20_31_SHIFT (20U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_20_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DI_HDMI_LPCG_40 - na */ /*! @{ */ #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_0_16_MASK (0x1FFFFU) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_0_16_SHIFT (0U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_0_16_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_0_16_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_SWEN_MASK (0x20000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_SWEN_SHIFT (17U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_SWEN_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_18_18_MASK (0x40000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_18_18_SHIFT (18U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_18_18_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_18_18_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_STOP_MASK (0x80000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_STOP_SHIFT (19U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_STOP_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_20_31_MASK (0xFFF00000U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_20_31_SHIFT (20U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_20_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DI_HDMI_LPCG_44 - na */ /*! @{ */ #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_0_0_MASK (0x1U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_0_0_SHIFT (0U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_0_0_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_0_0_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_SWEN_AND_bist_dca_ipg_clk_SWEN_AND_ipsyncs_bist_ipg_slave_clk_SWEN_MASK (0x2U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_SWEN_AND_bist_dca_ipg_clk_SWEN_AND_ipsyncs_bist_ipg_slave_clk_SWEN_SHIFT (1U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_SWEN_AND_bist_dca_ipg_clk_SWEN_AND_ipsyncs_bist_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_SWEN_AND_bist_dca_ipg_clk_SWEN_AND_ipsyncs_bist_ipg_slave_clk_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_SWEN_AND_bist_dca_ipg_clk_SWEN_AND_ipsyncs_bist_ipg_slave_clk_SWEN_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_2_2_MASK (0x4U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_2_2_SHIFT (2U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_2_2_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_2_2_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_STOP_AND_bist_dca_ipg_clk_STOP_AND_ipsyncs_bist_ipg_slave_clk_STOP_MASK (0x8U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_STOP_AND_bist_dca_ipg_clk_STOP_AND_ipsyncs_bist_ipg_slave_clk_STOP_SHIFT (3U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_STOP_AND_bist_dca_ipg_clk_STOP_AND_ipsyncs_bist_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_STOP_AND_bist_dca_ipg_clk_STOP_AND_ipsyncs_bist_ipg_slave_clk_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_STOP_AND_bist_dca_ipg_clk_STOP_AND_ipsyncs_bist_ipg_slave_clk_STOP_MASK) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_4_31_SHIFT (4U) #define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_4_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group DI_HDMI_LPCG_Register_Masks */ /* DI_HDMI_LPCG - Peripheral instance base addresses */ /** Peripheral DI_HDMI__LPCG_CLK base address */ #define DI_HDMI__LPCG_CLK_BASE (0x56263000u) /** Peripheral DI_HDMI__LPCG_CLK base pointer */ #define DI_HDMI__LPCG_CLK ((DI_HDMI_LPCG_Type *)DI_HDMI__LPCG_CLK_BASE) /** Array initializer of DI_HDMI_LPCG peripheral base addresses */ #define DI_HDMI_LPCG_BASE_ADDRS { DI_HDMI__LPCG_CLK_BASE } /** Array initializer of DI_HDMI_LPCG peripheral base pointers */ #define DI_HDMI_LPCG_BASE_PTRS { DI_HDMI__LPCG_CLK } /*! * @} */ /* end of group DI_HDMI_LPCG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DI_LVDS_LPCG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DI_LVDS_LPCG_Peripheral_Access_Layer DI_LVDS_LPCG Peripheral Access Layer * @{ */ /** DI_LVDS_LPCG - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_DI_LVDS_LPCG_0; /**< na, offset: 0x0 */ __IO uint32_t LPCG_DI_LVDS_LPCG_4; /**< na, offset: 0x4 */ __IO uint32_t LPCG_DI_LVDS_LPCG_8; /**< na, offset: 0x8 */ __IO uint32_t LPCG_DI_LVDS_LPCG_12; /**< na, offset: 0xC */ __IO uint32_t LPCG_DI_LVDS_LPCG_16; /**< na, offset: 0x10 */ __IO uint32_t LPCG_DI_LVDS_LPCG_20; /**< na, offset: 0x14 */ } DI_LVDS_LPCG_Type; /* ---------------------------------------------------------------------------- -- DI_LVDS_LPCG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DI_LVDS_LPCG_Register_Masks DI_LVDS_LPCG Register Masks * @{ */ /*! @name LPCG_DI_LVDS_LPCG_0 - na */ /*! @{ */ #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_0_16_MASK (0x1FFFFU) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_0_16_SHIFT (0U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_0_16_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_0_16_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_SWEN_MASK (0x20000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_SWEN_SHIFT (17U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_SWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_18_18_MASK (0x40000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_18_18_SHIFT (18U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_18_18_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_18_18_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_STOP_MASK (0x80000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_STOP_SHIFT (19U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_STOP_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_20_31_MASK (0xFFF00000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_20_31_SHIFT (20U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_20_31_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DI_LVDS_LPCG_4 - na */ /*! @{ */ #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_0_16_MASK (0x1FFFFU) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_0_16_SHIFT (0U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_0_16_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_0_16_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_SWEN_MASK (0x20000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_SWEN_SHIFT (17U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_SWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_18_18_MASK (0x40000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_18_18_SHIFT (18U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_18_18_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_18_18_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_STOP_MASK (0x80000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_STOP_SHIFT (19U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_STOP_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_20_31_MASK (0xFFF00000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_20_31_SHIFT (20U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_20_31_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DI_LVDS_LPCG_8 - na */ /*! @{ */ #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_0_15_MASK (0xFFFFU) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_0_15_SHIFT (0U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_0_15_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_0_15_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN_MASK (0x10000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN_SHIFT (16U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN_MASK (0x20000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN_SHIFT (17U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_18_18_MASK (0x40000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_18_18_SHIFT (18U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_18_18_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_18_18_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP_MASK (0x80000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP_SHIFT (19U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_20_31_MASK (0xFFF00000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_20_31_SHIFT (20U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_20_31_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DI_LVDS_LPCG_12 - na */ /*! @{ */ #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_0_0_MASK (0x1U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_0_0_SHIFT (0U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_0_0_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_0_0_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN_MASK (0x2U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN_SHIFT (1U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_2_2_MASK (0x4U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_2_2_SHIFT (2U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_2_2_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_2_2_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP_MASK (0x8U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP_SHIFT (3U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_4_4_MASK (0x10U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_4_4_SHIFT (4U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_4_4_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_4_4_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_MASK (0x20U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_SHIFT (5U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_6_6_MASK (0x40U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_6_6_SHIFT (6U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_6_6_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_6_6_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_MASK (0x80U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_SHIFT (7U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_8_15_MASK (0xFF00U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_8_15_SHIFT (8U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_8_15(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_8_15_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_8_15_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_MASK (0x10000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_SHIFT (16U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK (0x20000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT (17U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_18_18_MASK (0x40000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_18_18_SHIFT (18U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_18_18_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_18_18_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK (0x80000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT (19U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_MASK (0x100000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_SHIFT (20U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_MASK (0x200000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_SHIFT (21U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_22_22_MASK (0x400000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_22_22_SHIFT (22U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_22_22_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_22_22_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_MASK (0x800000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_SHIFT (23U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_HWEN_MASK (0x1000000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_HWEN_SHIFT (24U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_HWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_HWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_MASK (0x2000000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_SHIFT (25U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_26_26_MASK (0x4000000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_26_26_SHIFT (26U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_26_26_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_26_26_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_MASK (0x8000000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_SHIFT (27U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_28_31_MASK (0xF0000000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_28_31_SHIFT (28U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_28_31_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_28_31_MASK) /*! @} */ /*! @name LPCG_DI_LVDS_LPCG_16 - na */ /*! @{ */ #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_MASK (0x1U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_SHIFT (0U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_MASK (0x2U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_SHIFT (1U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_2_2_MASK (0x4U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_2_2_SHIFT (2U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_2_2_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_2_2_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_MASK (0x8U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_SHIFT (3U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_4_15_MASK (0xFFF0U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_4_15_SHIFT (4U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_4_15_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_4_15_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN_MASK (0x10000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN_SHIFT (16U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_MASK (0x20000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_SHIFT (17U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_18_18_MASK (0x40000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_18_18_SHIFT (18U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_18_18_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_18_18_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_MASK (0x80000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_SHIFT (19U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_20_31_MASK (0xFFF00000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_20_31_SHIFT (20U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_20_31_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DI_LVDS_LPCG_20 - na */ /*! @{ */ #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_2_2_MASK (0x4U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_2_2_SHIFT (2U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_2_2_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_2_2_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_4_15_MASK (0xFFF0U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_4_15_SHIFT (4U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_4_15_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_4_15_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN_MASK (0x10000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN_SHIFT (16U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_MASK (0x20000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_SHIFT (17U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_18_18_MASK (0x40000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_18_18_SHIFT (18U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_18_18_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_18_18_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_MASK (0x80000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_SHIFT (19U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_MASK) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_20_31_MASK (0xFFF00000U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_20_31_SHIFT (20U) #define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_20_31_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DI_LVDS_LPCG_Register_Masks */ /* DI_LVDS_LPCG - Peripheral instance base addresses */ /** Peripheral DI_LVDS_0__LPCG_CLK base address */ #define DI_LVDS_0__LPCG_CLK_BASE (0x56243000u) /** Peripheral DI_LVDS_0__LPCG_CLK base pointer */ #define DI_LVDS_0__LPCG_CLK ((DI_LVDS_LPCG_Type *)DI_LVDS_0__LPCG_CLK_BASE) /** Peripheral DI_LVDS_1__LPCG_CLK base address */ #define DI_LVDS_1__LPCG_CLK_BASE (0x57243000u) /** Peripheral DI_LVDS_1__LPCG_CLK base pointer */ #define DI_LVDS_1__LPCG_CLK ((DI_LVDS_LPCG_Type *)DI_LVDS_1__LPCG_CLK_BASE) /** Array initializer of DI_LVDS_LPCG peripheral base addresses */ #define DI_LVDS_LPCG_BASE_ADDRS { DI_LVDS_0__LPCG_CLK_BASE, DI_LVDS_1__LPCG_CLK_BASE } /** Array initializer of DI_LVDS_LPCG peripheral base pointers */ #define DI_LVDS_LPCG_BASE_PTRS { DI_LVDS_0__LPCG_CLK, DI_LVDS_1__LPCG_CLK } /*! * @} */ /* end of group DI_LVDS_LPCG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DI_MIPI_LPCG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DI_MIPI_LPCG_Peripheral_Access_Layer DI_MIPI_LPCG Peripheral Access Layer * @{ */ /** DI_MIPI_LPCG - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_DI_MIPI_LPCG_0; /**< na, offset: 0x0 */ __IO uint32_t LPCG_DI_MIPI_LPCG_4; /**< na, offset: 0x4 */ __IO uint32_t LPCG_DI_MIPI_LPCG_8; /**< na, offset: 0x8 */ __IO uint32_t LPCG_DI_MIPI_LPCG_12; /**< na, offset: 0xC */ __IO uint32_t LPCG_DI_MIPI_LPCG_16; /**< na, offset: 0x10 */ __IO uint32_t LPCG_DI_MIPI_LPCG_20; /**< na, offset: 0x14 */ __IO uint32_t LPCG_DI_MIPI_LPCG_24; /**< na, offset: 0x18 */ __IO uint32_t LPCG_DI_MIPI_LPCG_28; /**< na, offset: 0x1C */ __IO uint32_t LPCG_DI_MIPI_LPCG_32; /**< na, offset: 0x20 */ __IO uint32_t LPCG_DI_MIPI_LPCG_36; /**< na, offset: 0x24 */ __IO uint32_t LPCG_DI_MIPI_LPCG_40; /**< na, offset: 0x28 */ __IO uint32_t LPCG_DI_MIPI_LPCG_44; /**< na, offset: 0x2C */ __IO uint32_t LPCG_DI_MIPI_LPCG_48; /**< na, offset: 0x30 */ __IO uint32_t LPCG_DI_MIPI_LPCG_52; /**< na, offset: 0x34 */ __IO uint32_t LPCG_DI_MIPI_LPCG_56; /**< na, offset: 0x38 */ __IO uint32_t LPCG_DI_MIPI_LPCG_60; /**< na, offset: 0x3C */ } DI_MIPI_LPCG_Type; /* ---------------------------------------------------------------------------- -- DI_MIPI_LPCG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DI_MIPI_LPCG_Register_Masks DI_MIPI_LPCG Register Masks * @{ */ /*! @name LPCG_DI_MIPI_LPCG_0 - na */ /*! @{ */ #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_0_0_MASK (0x1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_0_0_SHIFT (0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_0_0_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_0_0_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_SWEN_MASK (0x2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_SWEN_SHIFT (1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_SWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_2_2_MASK (0x4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_2_2_SHIFT (2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_2_2_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_STOP_MASK (0x8U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_STOP_SHIFT (3U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_STOP_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_4_31_SHIFT (4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_LPCG_4 - na */ /*! @{ */ #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_HWEN_MASK (0x1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_HWEN_SHIFT (0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_HWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_HWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_SWEN_MASK (0x2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_SWEN_SHIFT (1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_SWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_2_2_MASK (0x4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_2_2_SHIFT (2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_2_2_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_STOP_MASK (0x8U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_STOP_SHIFT (3U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_STOP_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_4_31_SHIFT (4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_LPCG_8 - na */ /*! @{ */ #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_HWEN_MASK (0x1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_HWEN_SHIFT (0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_HWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_HWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_SWEN_MASK (0x2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_SWEN_SHIFT (1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_SWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_2_2_MASK (0x4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_2_2_SHIFT (2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_2_2_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_STOP_MASK (0x8U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_STOP_SHIFT (3U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_STOP_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_4_31_SHIFT (4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_LPCG_12 - na */ /*! @{ */ #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_HWEN_MASK (0x1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_HWEN_SHIFT (0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_HWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_HWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_SWEN_MASK (0x2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_SWEN_SHIFT (1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_SWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_2_2_MASK (0x4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_2_2_SHIFT (2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_2_2_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_STOP_MASK (0x8U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_STOP_SHIFT (3U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_STOP_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_4_31_SHIFT (4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_LPCG_16 - na */ /*! @{ */ #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_0_0_MASK (0x1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_0_0_SHIFT (0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_0_0_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_0_0_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_MASK (0x2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_SHIFT (1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_2_2_MASK (0x4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_2_2_SHIFT (2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_2_2_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_STOP_MASK (0x8U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_STOP_SHIFT (3U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_STOP_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_4_31_SHIFT (4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_LPCG_20 - na */ /*! @{ */ #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_0_0_MASK (0x1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_0_0_SHIFT (0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_0_0_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_0_0_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_SWEN_MASK (0x2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_SWEN_SHIFT (1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_SWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_2_2_MASK (0x4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_2_2_SHIFT (2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_2_2_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_STOP_MASK (0x8U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_STOP_SHIFT (3U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_STOP_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_4_31_SHIFT (4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_LPCG_24 - na */ /*! @{ */ #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_HWEN_MASK (0x1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_HWEN_SHIFT (0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_HWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_HWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_SWEN_MASK (0x2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_SWEN_SHIFT (1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_SWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_2_2_MASK (0x4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_2_2_SHIFT (2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_2_2_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_STOP_MASK (0x8U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_STOP_SHIFT (3U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_STOP_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_4_31_SHIFT (4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_LPCG_28 - na */ /*! @{ */ #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_0_0_MASK (0x1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_0_0_SHIFT (0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_0_0_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_0_0_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_SWEN_MASK (0x2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_SWEN_SHIFT (1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_SWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_2_2_MASK (0x4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_2_2_SHIFT (2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_2_2_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_STOP_MASK (0x8U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_STOP_SHIFT (3U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_STOP_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_4_31_SHIFT (4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_LPCG_32 - na */ /*! @{ */ #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_HWEN_MASK (0x1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_HWEN_SHIFT (0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_HWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_HWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_SWEN_MASK (0x2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_SWEN_SHIFT (1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_SWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_2_2_MASK (0x4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_2_2_SHIFT (2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_2_2_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_STOP_MASK (0x8U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_STOP_SHIFT (3U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_STOP_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_4_31_SHIFT (4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_LPCG_36 - na */ /*! @{ */ #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_0_0_MASK (0x1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_0_0_SHIFT (0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_0_0_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_0_0_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_SWEN_MASK (0x2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_SWEN_SHIFT (1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_SWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_2_2_MASK (0x4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_2_2_SHIFT (2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_2_2_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_STOP_MASK (0x8U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_STOP_SHIFT (3U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_STOP_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_4_31_SHIFT (4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_LPCG_40 - na */ /*! @{ */ #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_HWEN_MASK (0x1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_HWEN_SHIFT (0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_HWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_HWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_SWEN_MASK (0x2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_SWEN_SHIFT (1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_SWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_2_2_MASK (0x4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_2_2_SHIFT (2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_2_2_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_STOP_MASK (0x8U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_STOP_SHIFT (3U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_STOP_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_4_31_SHIFT (4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_LPCG_44 - na */ /*! @{ */ #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_0_0_MASK (0x1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_0_0_SHIFT (0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_0_0_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_0_0_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_SWEN_MASK (0x2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_SWEN_SHIFT (1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_SWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_2_2_MASK (0x4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_2_2_SHIFT (2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_2_2_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_STOP_MASK (0x8U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_STOP_SHIFT (3U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_STOP_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_4_31_SHIFT (4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_LPCG_48 - na */ /*! @{ */ #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_HWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_SWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_2_2_MASK (0x4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_2_2_SHIFT (2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_2_2_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_STOP_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_4_31_SHIFT (4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_LPCG_52 - na */ /*! @{ */ #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_0_0_MASK (0x1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_0_0_SHIFT (0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_0_0_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_0_0_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_SWEN_MASK (0x2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_SWEN_SHIFT (1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_SWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_2_2_MASK (0x4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_2_2_SHIFT (2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_2_2_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_STOP_MASK (0x8U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_STOP_SHIFT (3U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_STOP_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_4_31_SHIFT (4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_LPCG_56 - na */ /*! @{ */ #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_0_0_MASK (0x1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_0_0_SHIFT (0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_0_0_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_0_0_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_SWEN_MASK (0x2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_SWEN_SHIFT (1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_SWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_2_2_MASK (0x4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_2_2_SHIFT (2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_2_2_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_STOP_MASK (0x8U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_STOP_SHIFT (3U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_STOP_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_4_31_SHIFT (4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_LPCG_60 - na */ /*! @{ */ #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_0_0_MASK (0x1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_0_0_SHIFT (0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_0_0_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_0_0_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_SWEN_MASK (0x2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_SWEN_SHIFT (1U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_SWEN_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_2_2_MASK (0x4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_2_2_SHIFT (2U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_2_2_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_STOP_MASK (0x8U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_STOP_SHIFT (3U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_STOP_MASK) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_4_31_MASK (0xFFFFFFF0U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_4_31_SHIFT (4U) #define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group DI_MIPI_LPCG_Register_Masks */ /* DI_MIPI_LPCG - Peripheral instance base addresses */ /** Peripheral DI_MIPI_0__LPCG_CLK base address */ #define DI_MIPI_0__LPCG_CLK_BASE (0x56223000u) /** Peripheral DI_MIPI_0__LPCG_CLK base pointer */ #define DI_MIPI_0__LPCG_CLK ((DI_MIPI_LPCG_Type *)DI_MIPI_0__LPCG_CLK_BASE) /** Peripheral DI_MIPI_1__LPCG_CLK base address */ #define DI_MIPI_1__LPCG_CLK_BASE (0x57223000u) /** Peripheral DI_MIPI_1__LPCG_CLK base pointer */ #define DI_MIPI_1__LPCG_CLK ((DI_MIPI_LPCG_Type *)DI_MIPI_1__LPCG_CLK_BASE) /** Array initializer of DI_MIPI_LPCG peripheral base addresses */ #define DI_MIPI_LPCG_BASE_ADDRS { DI_MIPI_0__LPCG_CLK_BASE, DI_MIPI_1__LPCG_CLK_BASE } /** Array initializer of DI_MIPI_LPCG peripheral base pointers */ #define DI_MIPI_LPCG_BASE_PTRS { DI_MIPI_0__LPCG_CLK, DI_MIPI_1__LPCG_CLK } /*! * @} */ /* end of group DI_MIPI_LPCG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer * @{ */ /** DMA - Register Layout Typedef */ typedef struct { __IO uint32_t MP_CSR; /**< Management Page Control Register, offset: 0x0 */ __I uint32_t MP_ES; /**< Management Page Error Status Register, offset: 0x4 */ uint8_t RESERVED_0[4]; __I uint32_t MP_HRS; /**< Management Page Hardware Request Status Register, offset: 0xC */ uint8_t RESERVED_1[240]; __IO uint32_t CH_GRPRI[32]; /**< Channel Arbitration Group Register, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_2[65152]; struct { /* offset: 0x10000, array step: 0x10000 */ __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */ __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */ __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */ __IO uint32_t CH_SBR; /**< Channel System Bus Register, array offset: 0x1000C, array step: 0x10000 */ __IO uint32_t CH_PRI; /**< Channel Priority Register, array offset: 0x10010, array step: 0x10000 */ uint8_t RESERVED_0[12]; __IO uint32_t TCD_SADDR; /**< TCD Source Address, array offset: 0x10020, array step: 0x10000 */ __IO uint16_t TCD_SOFF; /**< TCD Signed Source Address Offset, array offset: 0x10024, array step: 0x10000 */ __IO uint16_t TCD_ATTR; /**< TCD Transfer Attributes, array offset: 0x10026, array step: 0x10000 */ union { /* offset: 0x10028, array step: 0x10000 */ __IO uint32_t TCD_NBYTES_MLOFFNO; /**< TCD Transfer Size without Minor Loop Offsets, array offset: 0x10028, array step: 0x10000 */ __IO uint32_t TCD_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x10028, array step: 0x10000 */ }; __IO uint32_t TCD_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x1002C, array step: 0x10000 */ __IO uint32_t TCD_DADDR; /**< TCD Destination Address, array offset: 0x10030, array step: 0x10000 */ __IO uint16_t TCD_DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x10034, array step: 0x10000 */ union { /* offset: 0x10036, array step: 0x10000 */ __IO uint16_t TCD_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x10036, array step: 0x10000 */ __IO uint16_t TCD_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x10036, array step: 0x10000 */ }; __IO uint32_t TCD_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x10038, array step: 0x10000 */ __IO uint16_t TCD_CSR; /**< TCD Control and Status, array offset: 0x1003C, array step: 0x10000 */ union { /* offset: 0x1003E, array step: 0x10000 */ __IO uint16_t TCD_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1003E, array step: 0x10000 */ __IO uint16_t TCD_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1003E, array step: 0x10000 */ }; uint8_t RESERVED_1[65472]; } CH[32]; } DMA_Type; /* ---------------------------------------------------------------------------- -- DMA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Register_Masks DMA Register Masks * @{ */ /*! @name MP_CSR - Management Page Control Register */ /*! @{ */ #define DMA_MP_CSR_EBW_MASK (0x1U) #define DMA_MP_CSR_EBW_SHIFT (0U) /*! EBW - Enable Buffered Writes * 0b0..Buffered writes on the system bus are disabled. * 0b1..Buffered writes on the system bus are enabled. */ #define DMA_MP_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EBW_SHIFT)) & DMA_MP_CSR_EBW_MASK) #define DMA_MP_CSR_EDBG_MASK (0x2U) #define DMA_MP_CSR_EDBG_SHIFT (1U) /*! EDBG - Enable Debug * 0b0..Debug mode is disabled. * 0b1..Debug mode is enabled. */ #define DMA_MP_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK) #define DMA_MP_CSR_ERCA_MASK (0x4U) #define DMA_MP_CSR_ERCA_SHIFT (2U) /*! ERCA - Enable Round Robin Channel Arbitration * 0b0..Round robin channel arbitration is disabled. * 0b1..Round robin channel arbitration is enabled. */ #define DMA_MP_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK) #define DMA_MP_CSR_HAE_MASK (0x10U) #define DMA_MP_CSR_HAE_SHIFT (4U) /*! HAE - Halt After Error * 0b0..Normal operation * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. */ #define DMA_MP_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK) #define DMA_MP_CSR_HALT_MASK (0x20U) #define DMA_MP_CSR_HALT_SHIFT (5U) /*! HALT - Halt DMA Operations * 0b0..Normal operation * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. */ #define DMA_MP_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK) #define DMA_MP_CSR_GCLC_MASK (0x40U) #define DMA_MP_CSR_GCLC_SHIFT (6U) /*! GCLC - Global Channel Linking Control * 0b0..Channel linking is disabled for all channels. * 0b1..Channel linking is available and controlled by each channel's link settings. */ #define DMA_MP_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK) #define DMA_MP_CSR_GMRC_MASK (0x80U) #define DMA_MP_CSR_GMRC_SHIFT (7U) /*! GMRC - Global Master ID Replication Control * 0b0..Master ID replication is disabled for all channels. * 0b1..Master ID replication is available and is controlled by each channel's CHn_SBR[EMI] setting. */ #define DMA_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK) #define DMA_MP_CSR_ECX_MASK (0x100U) #define DMA_MP_CSR_ECX_SHIFT (8U) /*! ECX - Cancel Transfer with Error * 0b0..Normal operation * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. */ #define DMA_MP_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK) #define DMA_MP_CSR_CX_MASK (0x200U) #define DMA_MP_CSR_CX_SHIFT (9U) /*! CX - Cancel Transfer * 0b0..Normal operation * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. */ #define DMA_MP_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK) #define DMA_MP_CSR_ACTIVE_ID_MASK (0x1F000000U) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define DMA_MP_CSR_ACTIVE_ID_SHIFT (24U) #define DMA_MP_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define DMA_MP_CSR_ACTIVE_MASK (0x80000000U) #define DMA_MP_CSR_ACTIVE_SHIFT (31U) /*! ACTIVE - DMA Active Status * 0b0..eDMA is idle. * 0b1..eDMA is executing a channel. */ #define DMA_MP_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK) /*! @} */ /*! @name MP_ES - Management Page Error Status Register */ /*! @{ */ #define DMA_MP_ES_DBE_MASK (0x1U) #define DMA_MP_ES_DBE_SHIFT (0U) /*! DBE - Destination Bus Error * 0b0..No destination bus error * 0b1..The last recorded error was a bus error on a destination write */ #define DMA_MP_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK) #define DMA_MP_ES_SBE_MASK (0x2U) #define DMA_MP_ES_SBE_SHIFT (1U) /*! SBE - Source Bus Error * 0b0..No source bus error * 0b1..The last recorded error was a bus error on a source read */ #define DMA_MP_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK) #define DMA_MP_ES_SGE_MASK (0x4U) #define DMA_MP_ES_SGE_SHIFT (2U) /*! SGE - Scatter/Gather Configuration Error * 0b0..No scatter/gather configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. */ #define DMA_MP_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK) #define DMA_MP_ES_NCE_MASK (0x8U) #define DMA_MP_ES_NCE_SHIFT (3U) /*! NCE - NBYTES/CITER Configuration Error * 0b0..No NBYTES/CITER configuration error * 0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error */ #define DMA_MP_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK) #define DMA_MP_ES_DOE_MASK (0x10U) #define DMA_MP_ES_DOE_SHIFT (4U) /*! DOE - Destination Offset Error * 0b0..No destination offset configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. */ #define DMA_MP_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK) #define DMA_MP_ES_DAE_MASK (0x20U) #define DMA_MP_ES_DAE_SHIFT (5U) /*! DAE - Destination Address Error * 0b0..No destination address configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. */ #define DMA_MP_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK) #define DMA_MP_ES_SOE_MASK (0x40U) #define DMA_MP_ES_SOE_SHIFT (6U) /*! SOE - Source Offset Error * 0b0..No source offset configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. */ #define DMA_MP_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK) #define DMA_MP_ES_SAE_MASK (0x80U) #define DMA_MP_ES_SAE_SHIFT (7U) /*! SAE - Source Address Error * 0b0..No source address configuration error. * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. */ #define DMA_MP_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK) #define DMA_MP_ES_ECX_MASK (0x100U) #define DMA_MP_ES_ECX_SHIFT (8U) /*! ECX - Transfer Canceled * 0b0..No canceled transfers * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input */ #define DMA_MP_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK) #define DMA_MP_ES_ERRCHN_MASK (0x1F000000U) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define DMA_MP_ES_ERRCHN_SHIFT (24U) #define DMA_MP_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define DMA_MP_ES_VLD_MASK (0x80000000U) #define DMA_MP_ES_VLD_SHIFT (31U) /*! VLD - Valid * 0b0..No ERR bits are set. * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared. */ #define DMA_MP_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK) /*! @} */ /*! @name MP_HRS - Management Page Hardware Request Status Register */ /*! @{ */ #define DMA_MP_HRS_HRS_MASK (0xFFFFFFFFU) #define DMA_MP_HRS_HRS_SHIFT (0U) /*! HRS - Hardware Request Status * 0b00000000000000000000000000000000..A hardware service request for the channel is not present * 0b00000000000000000000000000000001..A hardware service request for channel 0 is present */ #define DMA_MP_HRS_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK) /*! @} */ /*! @name CH_GRPRI - Channel Arbitration Group Register */ /*! @{ */ #define DMA_CH_GRPRI_GRPRI_MASK (0x1FU) #define DMA_CH_GRPRI_GRPRI_SHIFT (0U) #define DMA_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK) /*! @} */ /* The count of DMA_CH_GRPRI */ #define DMA_CH_GRPRI_COUNT (32U) /*! @name CH_CSR - Channel Control and Status */ /*! @{ */ #define DMA_CH_CSR_ERQ_MASK (0x1U) #define DMA_CH_CSR_ERQ_SHIFT (0U) /*! ERQ - Enable DMA Request * 0b0..The DMA hardware request signal for the corresponding channel is disabled. * 0b1..The DMA hardware request signal for the corresponding channel is enabled. */ #define DMA_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK) #define DMA_CH_CSR_EARQ_MASK (0x2U) #define DMA_CH_CSR_EARQ_SHIFT (1U) /*! EARQ - Enable Asynchronous DMA Request in stop mode for channel * 0b0..Disable asynchronous DMA request for the channel. * 0b1..Enable asynchronous DMA request for the channel. */ #define DMA_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK) #define DMA_CH_CSR_EEI_MASK (0x4U) #define DMA_CH_CSR_EEI_SHIFT (2U) /*! EEI - Enable Error Interrupt * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK) #define DMA_CH_CSR_DONE_MASK (0x40000000U) #define DMA_CH_CSR_DONE_SHIFT (30U) #define DMA_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK) #define DMA_CH_CSR_ACTIVE_MASK (0x80000000U) #define DMA_CH_CSR_ACTIVE_SHIFT (31U) #define DMA_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK) /*! @} */ /* The count of DMA_CH_CSR */ #define DMA_CH_CSR_COUNT (32U) /*! @name CH_ES - Channel Error Status */ /*! @{ */ #define DMA_CH_ES_DBE_MASK (0x1U) #define DMA_CH_ES_DBE_SHIFT (0U) /*! DBE - Destination Bus Error * 0b0..No destination bus error * 0b1..The last recorded error was a bus error on a destination write */ #define DMA_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK) #define DMA_CH_ES_SBE_MASK (0x2U) #define DMA_CH_ES_SBE_SHIFT (1U) /*! SBE - Source Bus Error * 0b0..No source bus error * 0b1..The last recorded error was a bus error on a source read */ #define DMA_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK) #define DMA_CH_ES_SGE_MASK (0x4U) #define DMA_CH_ES_SGE_SHIFT (2U) /*! SGE - Scatter/Gather Configuration Error * 0b0..No scatter/gather configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. */ #define DMA_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK) #define DMA_CH_ES_NCE_MASK (0x8U) #define DMA_CH_ES_NCE_SHIFT (3U) /*! NCE - NBYTES/CITER Configuration Error * 0b0..No NBYTES/CITER configuration error */ #define DMA_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK) #define DMA_CH_ES_DOE_MASK (0x10U) #define DMA_CH_ES_DOE_SHIFT (4U) /*! DOE - Destination Offset Error * 0b0..No destination offset configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. */ #define DMA_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK) #define DMA_CH_ES_DAE_MASK (0x20U) #define DMA_CH_ES_DAE_SHIFT (5U) /*! DAE - Destination Address Error * 0b0..No destination address configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. */ #define DMA_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK) #define DMA_CH_ES_SOE_MASK (0x40U) #define DMA_CH_ES_SOE_SHIFT (6U) /*! SOE - Source Offset Error * 0b0..No source offset configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. */ #define DMA_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK) #define DMA_CH_ES_SAE_MASK (0x80U) #define DMA_CH_ES_SAE_SHIFT (7U) /*! SAE - Source Address Error * 0b0..No source address configuration error. * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. */ #define DMA_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK) #define DMA_CH_ES_ERR_MASK (0x80000000U) #define DMA_CH_ES_ERR_SHIFT (31U) /*! ERR - Error In Channel * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK) /*! @} */ /* The count of DMA_CH_ES */ #define DMA_CH_ES_COUNT (32U) /*! @name CH_INT - Channel Interrupt Status */ /*! @{ */ #define DMA_CH_INT_INT_MASK (0x1U) #define DMA_CH_INT_INT_SHIFT (0U) /*! INT - Interrupt Request * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK) /*! @} */ /* The count of DMA_CH_INT */ #define DMA_CH_INT_COUNT (32U) /*! @name CH_SBR - Channel System Bus Register */ /*! @{ */ #define DMA_CH_SBR_MID_MASK (0x1FU) #define DMA_CH_SBR_MID_SHIFT (0U) #define DMA_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK) #define DMA_CH_SBR_PAL_MASK (0x8000U) #define DMA_CH_SBR_PAL_SHIFT (15U) /*! PAL - Privileged Access Level * 0b0..User protection level for DMA transfers * 0b1..Privileged protection level for DMA transfers */ #define DMA_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK) #define DMA_CH_SBR_ATTR_MASK (0x7E0000U) #define DMA_CH_SBR_ATTR_SHIFT (17U) #define DMA_CH_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_ATTR_SHIFT)) & DMA_CH_SBR_ATTR_MASK) /*! @} */ /* The count of DMA_CH_SBR */ #define DMA_CH_SBR_COUNT (32U) /*! @name CH_PRI - Channel Priority Register */ /*! @{ */ #define DMA_CH_PRI_APL_MASK (0x7U) #define DMA_CH_PRI_APL_SHIFT (0U) #define DMA_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK) #define DMA_CH_PRI_DPA_MASK (0x40000000U) #define DMA_CH_PRI_DPA_SHIFT (30U) /*! DPA - Disable Preempt Ability. * 0b0..The channel can suspend a lower priority channel. * 0b1..The channel cannot suspend any other channel, regardless of channel priority. */ #define DMA_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK) #define DMA_CH_PRI_ECP_MASK (0x80000000U) #define DMA_CH_PRI_ECP_SHIFT (31U) /*! ECP - Enable Channel Preemption. * 0b0..The channel cannot be suspended by a higher priority channel's service request. * 0b1..The channel can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK) /*! @} */ /* The count of DMA_CH_PRI */ #define DMA_CH_PRI_COUNT (32U) /*! @name TCD_SADDR - TCD Source Address */ /*! @{ */ #define DMA_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) #define DMA_TCD_SADDR_SADDR_SHIFT (0U) #define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK) /*! @} */ /* The count of DMA_TCD_SADDR */ #define DMA_TCD_SADDR_COUNT (32U) /*! @name TCD_SOFF - TCD Signed Source Address Offset */ /*! @{ */ #define DMA_TCD_SOFF_SOFF_MASK (0xFFFFU) #define DMA_TCD_SOFF_SOFF_SHIFT (0U) #define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK) /*! @} */ /* The count of DMA_TCD_SOFF */ #define DMA_TCD_SOFF_COUNT (32U) /*! @name TCD_ATTR - TCD Transfer Attributes */ /*! @{ */ #define DMA_TCD_ATTR_DSIZE_MASK (0x7U) #define DMA_TCD_ATTR_DSIZE_SHIFT (0U) #define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK) #define DMA_TCD_ATTR_DMOD_MASK (0xF8U) #define DMA_TCD_ATTR_DMOD_SHIFT (3U) #define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK) #define DMA_TCD_ATTR_SSIZE_MASK (0x700U) #define DMA_TCD_ATTR_SSIZE_SHIFT (8U) /*! SSIZE - Source data transfer size * 0b000..8-bit * 0b001..16-bit * 0b010..32-bit * 0b011..64-bit * 0b100..16-byte * 0b101..32-byte * 0b110..64-byte * 0b111..Reserved */ #define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK) #define DMA_TCD_ATTR_SMOD_MASK (0xF800U) #define DMA_TCD_ATTR_SMOD_SHIFT (11U) /*! SMOD - Source address modulo * 0b00000..Source address modulo feature is disabled * 0b00001..Source address modulo feature is enabled for any non-zero value [1-31] */ #define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK) /*! @} */ /* The count of DMA_TCD_ATTR */ #define DMA_TCD_ATTR_COUNT (32U) /*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size without Minor Loop Offsets */ /*! @{ */ #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK) #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) /*! DMLOE - Destination Minor Loop Offset Enable * 0b0..The minor loop offset is not applied to the DADDR * 0b1..The minor loop offset is applied to the DADDR */ #define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK) #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) /*! SMLOE - Source Minor Loop Offset Enable * 0b0..The minor loop offset is not applied to the SADDR * 0b1..The minor loop offset is applied to the SADDR */ #define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK) /*! @} */ /* The count of DMA_TCD_NBYTES_MLOFFNO */ #define DMA_TCD_NBYTES_MLOFFNO_COUNT (32U) /*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ /*! @{ */ #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK) #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK) #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) /*! DMLOE - Destination Minor Loop Offset Enable * 0b0..The minor loop offset is not applied to the DADDR * 0b1..The minor loop offset is applied to the DADDR */ #define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK) #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) /*! SMLOE - Source Minor Loop Offset Enable * 0b0..The minor loop offset is not applied to the SADDR * 0b1..The minor loop offset is applied to the SADDR */ #define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK) /*! @} */ /* The count of DMA_TCD_NBYTES_MLOFFYES */ #define DMA_TCD_NBYTES_MLOFFYES_COUNT (32U) /*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ /*! @{ */ #define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) #define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U) #define DMA_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK) /*! @} */ /* The count of DMA_TCD_SLAST_SDA */ #define DMA_TCD_SLAST_SDA_COUNT (32U) /*! @name TCD_DADDR - TCD Destination Address */ /*! @{ */ #define DMA_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) #define DMA_TCD_DADDR_DADDR_SHIFT (0U) #define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK) /*! @} */ /* The count of DMA_TCD_DADDR */ #define DMA_TCD_DADDR_COUNT (32U) /*! @name TCD_DOFF - TCD Signed Destination Address Offset */ /*! @{ */ #define DMA_TCD_DOFF_DOFF_MASK (0xFFFFU) #define DMA_TCD_DOFF_DOFF_SHIFT (0U) #define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK) /*! @} */ /* The count of DMA_TCD_DOFF */ #define DMA_TCD_DOFF_COUNT (32U) /*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ /*! @{ */ #define DMA_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) #define DMA_TCD_CITER_ELINKNO_CITER_SHIFT (0U) #define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK) #define DMA_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) /*! ELINK - Enable channel-to-channel linking on minor-loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ #define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK) /*! @} */ /* The count of DMA_TCD_CITER_ELINKNO */ #define DMA_TCD_CITER_ELINKNO_COUNT (32U) /*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ /*! @{ */ #define DMA_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) #define DMA_TCD_CITER_ELINKYES_CITER_SHIFT (0U) #define DMA_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK) #define DMA_TCD_CITER_ELINKYES_LINKCH_MASK (0x3E00U) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) #define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define DMA_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) /*! ELINK - Enable channel-to-channel linking on minor-loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ #define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK) /*! @} */ /* The count of DMA_TCD_CITER_ELINKYES */ #define DMA_TCD_CITER_ELINKYES_COUNT (32U) /*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ /*! @{ */ #define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) #define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U) #define DMA_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK) /*! @} */ /* The count of DMA_TCD_DLAST_SGA */ #define DMA_TCD_DLAST_SGA_COUNT (32U) /*! @name TCD_CSR - TCD Control and Status */ /*! @{ */ #define DMA_TCD_CSR_START_MASK (0x1U) #define DMA_TCD_CSR_START_SHIFT (0U) /*! START - Channel Start * 0b0..The channel is not explicitly started. * 0b1..The channel is explicitly started via a software initiated service request. */ #define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK) #define DMA_TCD_CSR_INTMAJOR_MASK (0x2U) #define DMA_TCD_CSR_INTMAJOR_SHIFT (1U) /*! INTMAJOR - Enable an interrupt when major iteration count completes. * 0b0..The end-of-major loop interrupt is disabled. * 0b1..The end-of-major loop interrupt is enabled. */ #define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK) #define DMA_TCD_CSR_INTHALF_MASK (0x4U) #define DMA_TCD_CSR_INTHALF_SHIFT (2U) /*! INTHALF - Enable an interrupt when major counter is half complete. * 0b0..The half-point interrupt is disabled. * 0b1..The half-point interrupt is enabled. */ #define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK) #define DMA_TCD_CSR_DREQ_MASK (0x8U) #define DMA_TCD_CSR_DREQ_SHIFT (3U) /*! DREQ - Disable request * 0b0..No operation * 0b1..Clear the ERQ bit upon major loop completion, thus disabling hardware service requests. */ #define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK) #define DMA_TCD_CSR_ESG_MASK (0x10U) #define DMA_TCD_CSR_ESG_SHIFT (4U) /*! ESG - Enable Scatter/Gather processing * 0b0..The current channel's TCD is normal format. * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. */ #define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK) #define DMA_TCD_CSR_MAJORELINK_MASK (0x20U) #define DMA_TCD_CSR_MAJORELINK_SHIFT (5U) /*! MAJORELINK - Enable channel-to-channel linking on major loop complete * 0b0..The channel-to-channel linking is disabled. * 0b1..The channel-to-channel linking is enabled. */ #define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK) #define DMA_TCD_CSR_EEOP_MASK (0x40U) #define DMA_TCD_CSR_EEOP_SHIFT (6U) /*! EEOP - Enable end-of-packet processing * 0b0..The end-of-packet operation is disabled. * 0b1..The end-of-packet hardware input signal is enabled. */ #define DMA_TCD_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK) #define DMA_TCD_CSR_ESDA_MASK (0x80U) #define DMA_TCD_CSR_ESDA_SHIFT (7U) /*! ESDA - Enable store destination address * 0b0..The store destination address to system memory operation is disabled. * 0b1..The store destination address to system memory operation is enabled. */ #define DMA_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK) #define DMA_TCD_CSR_MAJORLINKCH_MASK (0x1F00U) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define DMA_TCD_CSR_MAJORLINKCH_SHIFT (8U) #define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define DMA_TCD_CSR_BWC_MASK (0xC000U) #define DMA_TCD_CSR_BWC_SHIFT (14U) /*! BWC - Bandwidth Control * 0b00..No eDMA engine stalls. * 0b01..Reserved * 0b10..eDMA engine stalls for 4 cycles after each R/W. * 0b11..eDMA engine stalls for 8 cycles after each R/W. */ #define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK) /*! @} */ /* The count of DMA_TCD_CSR */ #define DMA_TCD_CSR_COUNT (32U) /*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ /*! @{ */ #define DMA_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) #define DMA_TCD_BITER_ELINKNO_BITER_SHIFT (0U) #define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK) #define DMA_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) /*! ELINK - Enables channel-to-channel linking on minor loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ #define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK) /*! @} */ /* The count of DMA_TCD_BITER_ELINKNO */ #define DMA_TCD_BITER_ELINKNO_COUNT (32U) /*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ /*! @{ */ #define DMA_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) #define DMA_TCD_BITER_ELINKYES_BITER_SHIFT (0U) #define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK) #define DMA_TCD_BITER_ELINKYES_LINKCH_MASK (0x3E00U) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) #define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define DMA_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) /*! ELINK - Enables channel-to-channel linking on minor loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ #define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK) /*! @} */ /* The count of DMA_TCD_BITER_ELINKYES */ #define DMA_TCD_BITER_ELINKYES_COUNT (32U) /*! * @} */ /* end of group DMA_Register_Masks */ /* DMA - Peripheral instance base addresses */ /** Peripheral AUDIO__EDMA0 base address */ #define AUDIO__EDMA0_BASE (0x591F0000u) /** Peripheral AUDIO__EDMA0 base pointer */ #define AUDIO__EDMA0 ((DMA_Type *)AUDIO__EDMA0_BASE) /** Peripheral AUDIO__EDMA1 base address */ #define AUDIO__EDMA1_BASE (0x599F0000u) /** Peripheral AUDIO__EDMA1 base pointer */ #define AUDIO__EDMA1 ((DMA_Type *)AUDIO__EDMA1_BASE) /** Peripheral CONNECTIVITY__EDMA base address */ #define CONNECTIVITY__EDMA_BASE (0x5B070000u) /** Peripheral CONNECTIVITY__EDMA base pointer */ #define CONNECTIVITY__EDMA ((DMA_Type *)CONNECTIVITY__EDMA_BASE) /** Peripheral DMA__EDMA0 base address */ #define DMA__EDMA0_BASE (0x5A1F0000u) /** Peripheral DMA__EDMA0 base pointer */ #define DMA__EDMA0 ((DMA_Type *)DMA__EDMA0_BASE) /** Peripheral DMA__EDMA1 base address */ #define DMA__EDMA1_BASE (0x5A9F0000u) /** Peripheral DMA__EDMA1 base pointer */ #define DMA__EDMA1 ((DMA_Type *)DMA__EDMA1_BASE) /** Array initializer of DMA peripheral base addresses */ #define DMA_BASE_ADDRS { AUDIO__EDMA0_BASE, AUDIO__EDMA1_BASE, CONNECTIVITY__EDMA_BASE, DMA__EDMA0_BASE, DMA__EDMA1_BASE } /** Array initializer of DMA peripheral base pointers */ #define DMA_BASE_PTRS { AUDIO__EDMA0, AUDIO__EDMA1, CONNECTIVITY__EDMA, DMA__EDMA0, DMA__EDMA1 } /** Interrupt vectors for the DMA peripheral type */ #define DMA_IRQS { { AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn }, \ { AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn }, \ { CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn }, \ { DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn }, \ { DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn } } #define DMA_ERROR_IRQS { AUDIO_EDMA0_ERR_INT_IRQn, AUDIO_EDMA1_ERR_INT_IRQn, CONNECTIVITY_DMA_ERR_INT_IRQn, DMA_EDMA0_ERR_INT_IRQn, DMA_EDMA1_ERR_INT_IRQn } /*! * @} */ /* end of group DMA_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DPR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DPR_Peripheral_Access_Layer DPR Peripheral Access Layer * @{ */ /** DPR - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0 */ __IO uint32_t RW; /**< System Control 0, offset: 0x0 */ __IO uint32_t SET; /**< System Control 0, offset: 0x4 */ __IO uint32_t CLR; /**< System Control 0, offset: 0x8 */ __IO uint32_t TOG; /**< System Control 0, offset: 0xC */ } SYSTEM_CTRL0; uint8_t RESERVED_0[16]; struct { /* offset: 0x20 */ __IO uint32_t RW; /**< Interrupt Mask, offset: 0x20 */ __IO uint32_t SET; /**< Interrupt Mask, offset: 0x24 */ __IO uint32_t CLR; /**< Interrupt Mask, offset: 0x28 */ __IO uint32_t TOG; /**< Interrupt Mask, offset: 0x2C */ } IRQ_MASK; struct { /* offset: 0x30 */ __I uint32_t RW; /**< Status Register of Masked IRQ, offset: 0x30 */ __I uint32_t SET; /**< Status Register of Masked IRQ, offset: 0x34 */ __I uint32_t CLR; /**< Status Register of Masked IRQ, offset: 0x38 */ __I uint32_t TOG; /**< Status Register of Masked IRQ, offset: 0x3C */ } IRQ_MASK_STATUS; struct { /* offset: 0x40 */ __IO uint32_t RW; /**< Status of Non-Masked IRQ, offset: 0x40 */ __IO uint32_t SET; /**< Status of Non-Masked IRQ, offset: 0x44 */ __IO uint32_t CLR; /**< Status of Non-Masked IRQ, offset: 0x48 */ __IO uint32_t TOG; /**< Status of Non-Masked IRQ, offset: 0x4C */ } IRQ_NONMASK_STATUS; struct { /* offset: 0x50 */ __IO uint32_t RW; /**< Mode Control 0, offset: 0x50 */ __IO uint32_t SET; /**< Mode Control 0, offset: 0x54 */ __IO uint32_t CLR; /**< Mode Control 0, offset: 0x58 */ __IO uint32_t TOG; /**< Mode Control 0, offset: 0x5C */ } MODE_CTRL0; uint8_t RESERVED_1[16]; struct { /* offset: 0x70 */ __IO uint32_t RW; /**< Frame Control 0, offset: 0x70 */ __IO uint32_t SET; /**< Frame Control 0, offset: 0x74 */ __IO uint32_t CLR; /**< Frame Control 0, offset: 0x78 */ __IO uint32_t TOG; /**< Frame Control 0, offset: 0x7C */ } FRAME_CTRL0; uint8_t RESERVED_2[16]; struct { /* offset: 0x90 */ __IO uint32_t RW; /**< Frame 1-Plane Control 0, offset: 0x90 */ __IO uint32_t SET; /**< Frame 1-Plane Control 0, offset: 0x94 */ __IO uint32_t CLR; /**< Frame 1-Plane Control 0, offset: 0x98 */ __IO uint32_t TOG; /**< Frame 1-Plane Control 0, offset: 0x9C */ } FRAME_1P_CTRL0; struct { /* offset: 0xA0 */ __IO uint32_t RW; /**< Frame 1-Plane Pix X Control, offset: 0xA0 */ __IO uint32_t SET; /**< Frame 1-Plane Pix X Control, offset: 0xA4 */ __IO uint32_t CLR; /**< Frame 1-Plane Pix X Control, offset: 0xA8 */ __IO uint32_t TOG; /**< Frame 1-Plane Pix X Control, offset: 0xAC */ } FRAME_1P_PIX_X_CTRL; struct { /* offset: 0xB0 */ __IO uint32_t RW; /**< Frame 1-Plane Pix Y Control, offset: 0xB0 */ __IO uint32_t SET; /**< Frame 1-Plane Pix Y Control, offset: 0xB4 */ __IO uint32_t CLR; /**< Frame 1-Plane Pix Y Control, offset: 0xB8 */ __IO uint32_t TOG; /**< Frame 1-Plane Pix Y Control, offset: 0xBC */ } FRAME_1P_PIX_Y_CTRL; struct { /* offset: 0xC0 */ __IO uint32_t RW; /**< Frame 1-Plane Base Address Control 0, offset: 0xC0 */ __IO uint32_t SET; /**< Frame 1-Plane Base Address Control 0, offset: 0xC4 */ __IO uint32_t CLR; /**< Frame 1-Plane Base Address Control 0, offset: 0xC8 */ __IO uint32_t TOG; /**< Frame 1-Plane Base Address Control 0, offset: 0xCC */ } FRAME_1P_BASE_ADDR_CTRL0; uint8_t RESERVED_3[16]; struct { /* offset: 0xE0 */ __IO uint32_t RW; /**< Frame 2-Plane Control 0, offset: 0xE0 */ __IO uint32_t SET; /**< Frame 2-Plane Control 0, offset: 0xE4 */ __IO uint32_t CLR; /**< Frame 2-Plane Control 0, offset: 0xE8 */ __IO uint32_t TOG; /**< Frame 2-Plane Control 0, offset: 0xEC */ } FRAME_2P_CTRL0; struct { /* offset: 0xF0 */ __IO uint32_t RW; /**< Frame Pixel X Upper Left Coordinate Control, offset: 0xF0 */ __IO uint32_t SET; /**< Frame Pixel X Upper Left Coordinate Control, offset: 0xF4 */ __IO uint32_t CLR; /**< Frame Pixel X Upper Left Coordinate Control, offset: 0xF8 */ __IO uint32_t TOG; /**< Frame Pixel X Upper Left Coordinate Control, offset: 0xFC */ } FRAME_PIX_X_ULC_CTRL; struct { /* offset: 0x100 */ __IO uint32_t RW; /**< Frame Pixel Y Upper Left Coordinate Control, offset: 0x100 */ __IO uint32_t SET; /**< Frame Pixel Y Upper Left Coordinate Control, offset: 0x104 */ __IO uint32_t CLR; /**< Frame Pixel Y Upper Left Coordinate Control, offset: 0x108 */ __IO uint32_t TOG; /**< Frame Pixel Y Upper Left Coordinate Control, offset: 0x10C */ } FRAME_PIX_Y_ULC_CTRL; struct { /* offset: 0x110 */ __IO uint32_t RW; /**< Frame 2-Plane Base Address Control 0, offset: 0x110 */ __IO uint32_t SET; /**< Frame 2-Plane Base Address Control 0, offset: 0x114 */ __IO uint32_t CLR; /**< Frame 2-Plane Base Address Control 0, offset: 0x118 */ __IO uint32_t TOG; /**< Frame 2-Plane Base Address Control 0, offset: 0x11C */ } FRAME_2P_BASE_ADDR_CTRL0; uint8_t RESERVED_4[16]; struct { /* offset: 0x130 */ __IO uint32_t RW; /**< Status Control 0, offset: 0x130 */ __IO uint32_t SET; /**< Status Control 0, offset: 0x134 */ __IO uint32_t CLR; /**< Status Control 0, offset: 0x138 */ __IO uint32_t TOG; /**< Status Control 0, offset: 0x13C */ } STATUS_CTRL0; struct { /* offset: 0x140 */ __I uint32_t RW; /**< Status Control 1, offset: 0x140 */ __I uint32_t SET; /**< Status Control 1, offset: 0x144 */ __I uint32_t CLR; /**< Status Control 1, offset: 0x148 */ __I uint32_t TOG; /**< Status Control 1, offset: 0x14C */ } STATUS_CTRL1; uint8_t RESERVED_5[176]; struct { /* offset: 0x200 */ __IO uint32_t RW; /**< RTRAM Control 0, offset: 0x200 */ __IO uint32_t SET; /**< RTRAM Control 0, offset: 0x204 */ __IO uint32_t CLR; /**< RTRAM Control 0, offset: 0x208 */ __IO uint32_t TOG; /**< RTRAM Control 0, offset: 0x20C */ } RTRAM_CTRL0; } DPR_Type; /* ---------------------------------------------------------------------------- -- DPR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DPR_Register_Masks DPR Register Masks * @{ */ /*! @name SYSTEM_CTRL0 - System Control 0 */ /*! @{ */ #define DPR_SYSTEM_CTRL0_RUN_EN_MASK (0x1U) #define DPR_SYSTEM_CTRL0_RUN_EN_SHIFT (0U) /*! RUN_EN - Run Enable */ #define DPR_SYSTEM_CTRL0_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_RUN_EN_SHIFT)) & DPR_SYSTEM_CTRL0_RUN_EN_MASK) #define DPR_SYSTEM_CTRL0_SOFT_RESET_MASK (0x2U) #define DPR_SYSTEM_CTRL0_SOFT_RESET_SHIFT (1U) /*! SOFT_RESET - Soft Reset */ #define DPR_SYSTEM_CTRL0_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SOFT_RESET_SHIFT)) & DPR_SYSTEM_CTRL0_SOFT_RESET_MASK) #define DPR_SYSTEM_CTRL0_REPEAT_EN_MASK (0x4U) #define DPR_SYSTEM_CTRL0_REPEAT_EN_SHIFT (2U) /*! REPEAT_EN - Repeat Enable */ #define DPR_SYSTEM_CTRL0_REPEAT_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_REPEAT_EN_SHIFT)) & DPR_SYSTEM_CTRL0_REPEAT_EN_MASK) #define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_MASK (0x8U) #define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_SHIFT (3U) /*! SHADOW_LOAD_EN - Shadow Load Enable */ #define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_SHIFT)) & DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_MASK) #define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_MASK (0x10U) #define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_SHIFT (4U) /*! SW_SHADOW_LOAD_SEL - Software Shadow Load Select */ #define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_SHIFT)) & DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_MASK) #define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_MASK (0x10000U) #define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_SHIFT (16U) /*! BCMD2AXI_MSTR_ID_CTRL - Buscmd To AXI Master ID Control */ #define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_SHIFT)) & DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_MASK) /*! @} */ /*! @name IRQ_MASK - Interrupt Mask */ /*! @{ */ #define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_MASK (0x1U) #define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_SHIFT (0U) /*! IRQ_DPR_CTRL_DONE - DPR Control Done IRQ Mask */ #define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_MASK) #define DPR_IRQ_MASK_IRQ_DPR_RUN_MASK (0x2U) #define DPR_IRQ_MASK_IRQ_DPR_RUN_SHIFT (1U) /*! IRQ_DPR_RUN - DPR Run IRQ Mask */ #define DPR_IRQ_MASK_IRQ_DPR_RUN(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_RUN_MASK) #define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_MASK (0x4U) #define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_SHIFT (2U) /*! IRQ_DPR_SHADOW_LOADED_MASK - DPR Shadow Loaded IRQ Mask */ #define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_MASK) #define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_MASK (0x8U) #define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_SHIFT (3U) /*! IRQ_AXI_READ_ERROR - AXI Read Error IRQ Mask */ #define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_MASK) #define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U) #define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U) /*! DPR2RTR_YRGB_FIFO_OVFL - DPR to RTRAM YRGB Fifo Overflow IRQ Mask */ #define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_MASK) #define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U) #define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U) /*! DPR2RTR_UV_FIFO_OVFL - DPR to RTRAM UV Fifo Overflow IRQ Mask */ #define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_MASK) #define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U) #define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U) /*! DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR - DPR to RTRAM Fifo load YRGB buffer ready IRQ error Mask */ #define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK) #define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U) #define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U) /*! DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR - DPR to RTRAM Fifo load UV buffer ready IRQ error Mask */ #define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK) /*! @} */ /*! @name IRQ_MASK_STATUS - Status Register of Masked IRQ */ /*! @{ */ #define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_MASK (0x1U) #define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT (0U) /*! IRQ_DPR_CTRL_DONE - DPR Control Done Masked IRQ */ #define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_MASK) #define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_MASK (0x2U) #define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_SHIFT (1U) /*! IRQ_DPR_RUN - DPR Run Masked IRQ */ #define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_MASK) #define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_MASK (0x4U) #define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_SHIFT (2U) /*! IRQ_DPR_SHADOW_LOADED - DPR Shadow Loaded Masked IRQ */ #define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_MASK) #define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_MASK (0x8U) #define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT (3U) /*! IRQ_AXI_READ_ERROR - AXI Read Error Masked IRQ */ #define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_MASK) #define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U) #define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U) /*! DPR2RTR_YRGB_FIFO_OVFL - DPR to RTRAM YRGB Fifo Overflow Masked IRQ */ #define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK) #define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U) #define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U) /*! DPR2RTR_UV_FIFO_OVFL - DPR to RTRAM UV Fifo Overflow Masked IRQ */ #define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK) #define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U) #define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U) /*! DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR - DPR to RTRAM Fifo load YRGB buffer error Masked IRQ */ #define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK) #define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U) #define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U) /*! DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR - DPR to RTRAM Fifo load UV buffer error Masked IRQ */ #define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK) /*! @} */ /*! @name IRQ_NONMASK_STATUS - Status of Non-Masked IRQ */ /*! @{ */ #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_MASK (0x1U) #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT (0U) /*! IRQ_DPR_CTRL_DONE - DPR Control Done Non-Masked IRQ */ #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_MASK) #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_MASK (0x2U) #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_SHIFT (1U) /*! IRQ_DPR_RUN - DPR Run Non-Masked IRQ */ #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_MASK) #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_MASK (0x4U) #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_SHIFT (2U) /*! IRQ_DPR_SHADOW_LOADED_NMSTAT - DPR Shadow Loaded Non-Masked IRQ */ #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_MASK) #define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_MASK (0x8U) #define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT (3U) /*! IRQ_AXI_READ_ERROR - AXI Read Error Non-Masked IRQ */ #define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_MASK) #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U) #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U) /*! DPR2RTR_YRGB_FIFO_OVFL - DPR to RTRAM YRGB Fifo Overflow Non-Masked IRQ */ #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK) #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U) #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U) /*! DPR2RTR_UV_FIFO_OVFL - DPR to RTRAM UV Fifo Overflow Non-Masked IRQ */ #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK) #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U) #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U) /*! DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR - DPR to RTRAM Fifo load YRGB buffer ready error Non-Masked IRQ */ #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK) #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U) #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U) /*! DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR - DPR to RTRAM Fifo load UV buffer ready error Non-Masked IRQ */ #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK) /*! @} */ /*! @name MODE_CTRL0 - Mode Control 0 */ /*! @{ */ #define DPR_MODE_CTRL0_RTR_3BUF_EN_MASK (0x1U) #define DPR_MODE_CTRL0_RTR_3BUF_EN_SHIFT (0U) /*! RTR_3BUF_EN - RTRAM Buffer Implementation */ #define DPR_MODE_CTRL0_RTR_3BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_RTR_3BUF_EN_SHIFT)) & DPR_MODE_CTRL0_RTR_3BUF_EN_MASK) #define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_MASK (0x2U) #define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_SHIFT (1U) /*! RTR_4LINE_BUF_EN - RTRAM Lines Per Buffer */ #define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_SHIFT)) & DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_MASK) #define DPR_MODE_CTRL0_TILE_TYPE_MASK (0xCU) #define DPR_MODE_CTRL0_TILE_TYPE_SHIFT (2U) /*! TILE_TYPE - Tile Type */ #define DPR_MODE_CTRL0_TILE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_TILE_TYPE_SHIFT)) & DPR_MODE_CTRL0_TILE_TYPE_MASK) #define DPR_MODE_CTRL0_YUV_EN_MASK (0x10U) #define DPR_MODE_CTRL0_YUV_EN_SHIFT (4U) /*! YUV_EN - YUV Enable */ #define DPR_MODE_CTRL0_YUV_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_YUV_EN_SHIFT)) & DPR_MODE_CTRL0_YUV_EN_MASK) #define DPR_MODE_CTRL0_COMP_2PLANE_EN_MASK (0x20U) #define DPR_MODE_CTRL0_COMP_2PLANE_EN_SHIFT (5U) /*! COMP_2PLANE_EN - Component 2-Plane Enable */ #define DPR_MODE_CTRL0_COMP_2PLANE_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_COMP_2PLANE_EN_SHIFT)) & DPR_MODE_CTRL0_COMP_2PLANE_EN_MASK) #define DPR_MODE_CTRL0_PIX_SIZE_MASK (0xC0U) #define DPR_MODE_CTRL0_PIX_SIZE_SHIFT (6U) /*! PIX_SIZE - Pixel Size */ #define DPR_MODE_CTRL0_PIX_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_SIZE_SHIFT)) & DPR_MODE_CTRL0_PIX_SIZE_MASK) #define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_MASK (0x100U) #define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_SHIFT (8U) /*! PIX_LUMA_UV_SWAP - Pixel luma/UV position Swap */ #define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_SHIFT)) & DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_MASK) #define DPR_MODE_CTRL0_PIX_UV_SWAP_MASK (0x200U) #define DPR_MODE_CTRL0_PIX_UV_SWAP_SHIFT (9U) /*! PIX_UV_SWAP - Pixel UV Swap */ #define DPR_MODE_CTRL0_PIX_UV_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_UV_SWAP_SHIFT)) & DPR_MODE_CTRL0_PIX_UV_SWAP_MASK) #define DPR_MODE_CTRL0_B_COMP_SEL_MASK (0xC00U) #define DPR_MODE_CTRL0_B_COMP_SEL_SHIFT (10U) /*! B_COMP_SEL - B Component Select */ #define DPR_MODE_CTRL0_B_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_B_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_B_COMP_SEL_MASK) #define DPR_MODE_CTRL0_G_COMP_SEL_MASK (0x3000U) #define DPR_MODE_CTRL0_G_COMP_SEL_SHIFT (12U) /*! G_COMP_SEL - G Component Select */ #define DPR_MODE_CTRL0_G_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_G_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_G_COMP_SEL_MASK) #define DPR_MODE_CTRL0_R_COMP_SEL_MASK (0xC000U) #define DPR_MODE_CTRL0_R_COMP_SEL_SHIFT (14U) /*! R_COMP_SEL - R Component Select */ #define DPR_MODE_CTRL0_R_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_R_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_R_COMP_SEL_MASK) #define DPR_MODE_CTRL0_A_COMP_SEL_MASK (0x30000U) #define DPR_MODE_CTRL0_A_COMP_SEL_SHIFT (16U) /*! A_COMP_SEL - A Component Select */ #define DPR_MODE_CTRL0_A_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_A_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_A_COMP_SEL_MASK) /*! @} */ /*! @name FRAME_CTRL0 - Frame Control 0 */ /*! @{ */ #define DPR_FRAME_CTRL0_HFLIP_EN_MASK (0x1U) #define DPR_FRAME_CTRL0_HFLIP_EN_SHIFT (0U) /*! HFLIP_EN - Horizontal Flip Enable */ #define DPR_FRAME_CTRL0_HFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_HFLIP_EN_SHIFT)) & DPR_FRAME_CTRL0_HFLIP_EN_MASK) #define DPR_FRAME_CTRL0_VFLIP_EN_MASK (0x2U) #define DPR_FRAME_CTRL0_VFLIP_EN_SHIFT (1U) /*! VFLIP_EN - Vertical Flip Enable */ #define DPR_FRAME_CTRL0_VFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_VFLIP_EN_SHIFT)) & DPR_FRAME_CTRL0_VFLIP_EN_MASK) #define DPR_FRAME_CTRL0_ROT_ENC_MASK (0xCU) #define DPR_FRAME_CTRL0_ROT_ENC_SHIFT (2U) /*! ROT_ENC - Encoded Rotation */ #define DPR_FRAME_CTRL0_ROT_ENC(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_ROT_ENC_SHIFT)) & DPR_FRAME_CTRL0_ROT_ENC_MASK) #define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_MASK (0x10U) #define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_SHIFT (4U) /*! ROT_FLIP_ORDER_EN - Rotation Flip Order */ #define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_SHIFT)) & DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_MASK) #define DPR_FRAME_CTRL0_PITCH_MASK (0xFFFF0000U) #define DPR_FRAME_CTRL0_PITCH_SHIFT (16U) /*! PITCH - Image Pitch */ #define DPR_FRAME_CTRL0_PITCH(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_PITCH_SHIFT)) & DPR_FRAME_CTRL0_PITCH_MASK) /*! @} */ /*! @name FRAME_1P_CTRL0 - Frame 1-Plane Control 0 */ /*! @{ */ #define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_MASK (0x7U) #define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_SHIFT (0U) /*! MAX_BYTES_PREQ - Max Bytes Per Request */ #define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_SHIFT)) & DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_MASK) /*! @} */ /*! @name FRAME_1P_PIX_X_CTRL - Frame 1-Plane Pix X Control */ /*! @{ */ #define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK (0xFFFFU) #define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT (0U) /*! NUM_X_PIX_WIDE - Number of Pixels Wide in X-direction */ #define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT)) & DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK) /*! @} */ /*! @name FRAME_1P_PIX_Y_CTRL - Frame 1-Plane Pix Y Control */ /*! @{ */ #define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK (0xFFFFU) #define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT (0U) /*! NUM_Y_PIX_HIGH - Number of Pixels High in Y-direction */ #define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT)) & DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK) /*! @} */ /*! @name FRAME_1P_BASE_ADDR_CTRL0 - Frame 1-Plane Base Address Control 0 */ /*! @{ */ #define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_MASK (0xFFFFFFFFU) #define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT (0U) /*! BASE_ADDR - Base Address */ #define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT)) & DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_MASK) /*! @} */ /*! @name FRAME_2P_CTRL0 - Frame 2-Plane Control 0 */ /*! @{ */ #define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_MASK (0x7U) #define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_SHIFT (0U) /*! MAX_BYTES_PREQ - Max Bytes Per Request */ #define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_SHIFT)) & DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_MASK) /*! @} */ /*! @name FRAME_PIX_X_ULC_CTRL - Frame Pixel X Upper Left Coordinate Control */ /*! @{ */ #define DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X_MASK (0xFFFFU) #define DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X_SHIFT (0U) /*! CROP_ULC_X - Starting Coordinate of Cropped Image X (1-Plane or 2-Plane Luma) */ #define DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X_SHIFT)) & DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X_MASK) /*! @} */ /*! @name FRAME_PIX_Y_ULC_CTRL - Frame Pixel Y Upper Left Coordinate Control */ /*! @{ */ #define DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y_MASK (0xFFFFU) #define DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y_SHIFT (0U) /*! CROP_ULC_y - Starting Coordinate of Cropped Image X (1-Plane or 2-Plane Luma) */ #define DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y_SHIFT)) & DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y_MASK) /*! @} */ /*! @name FRAME_2P_BASE_ADDR_CTRL0 - Frame 2-Plane Base Address Control 0 */ /*! @{ */ #define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_MASK (0xFFFFFFFFU) #define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT (0U) /*! BASE_ADDR - Base Address */ #define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT)) & DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_MASK) /*! @} */ /*! @name STATUS_CTRL0 - Status Control 0 */ /*! @{ */ #define DPR_STATUS_CTRL0_STATUS_MUX_SEL_MASK (0x7U) #define DPR_STATUS_CTRL0_STATUS_MUX_SEL_SHIFT (0U) /*! STATUS_MUX_SEL - Status Mux Select */ #define DPR_STATUS_CTRL0_STATUS_MUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_STATUS_CTRL0_STATUS_MUX_SEL_SHIFT)) & DPR_STATUS_CTRL0_STATUS_MUX_SEL_MASK) #define DPR_STATUS_CTRL0_STATUS_SRC_SEL_MASK (0x70000U) #define DPR_STATUS_CTRL0_STATUS_SRC_SEL_SHIFT (16U) /*! STATUS_SRC_SEL - Status Source Select */ #define DPR_STATUS_CTRL0_STATUS_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_STATUS_CTRL0_STATUS_SRC_SEL_SHIFT)) & DPR_STATUS_CTRL0_STATUS_SRC_SEL_MASK) /*! @} */ /*! @name STATUS_CTRL1 - Status Control 1 */ /*! @{ */ #define DPR_STATUS_CTRL1_STATUS_MASK (0xFFFFFFFFU) #define DPR_STATUS_CTRL1_STATUS_SHIFT (0U) /*! STATUS - Status Register */ #define DPR_STATUS_CTRL1_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DPR_STATUS_CTRL1_STATUS_SHIFT)) & DPR_STATUS_CTRL1_STATUS_MASK) /*! @} */ /*! @name RTRAM_CTRL0 - RTRAM Control 0 */ /*! @{ */ #define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_MASK (0x1U) #define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_SHIFT (0U) /*! NUM_ROWS_ACTIVE - Number of Rows Active */ #define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_SHIFT)) & DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_MASK) #define DPR_RTRAM_CTRL0_THRES_HIGH_MASK (0xEU) #define DPR_RTRAM_CTRL0_THRES_HIGH_SHIFT (1U) /*! THRES_HIGH - Threshold High */ #define DPR_RTRAM_CTRL0_THRES_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_THRES_HIGH_SHIFT)) & DPR_RTRAM_CTRL0_THRES_HIGH_MASK) #define DPR_RTRAM_CTRL0_THRES_LOW_MASK (0x70U) #define DPR_RTRAM_CTRL0_THRES_LOW_SHIFT (4U) /*! THRES_LOW - Threshold Low */ #define DPR_RTRAM_CTRL0_THRES_LOW(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_THRES_LOW_SHIFT)) & DPR_RTRAM_CTRL0_THRES_LOW_MASK) #define DPR_RTRAM_CTRL0_ABORT_SEL_MASK (0x80U) #define DPR_RTRAM_CTRL0_ABORT_SEL_SHIFT (7U) /*! ABORT_SEL - Abort Select */ #define DPR_RTRAM_CTRL0_ABORT_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_ABORT_SEL_SHIFT)) & DPR_RTRAM_CTRL0_ABORT_SEL_MASK) /*! @} */ /*! * @} */ /* end of group DPR_Register_Masks */ /* DPR - Peripheral instance base addresses */ /** Peripheral DC_0__DPR0 base address */ #define DC_0__DPR0_BASE (0x560D0000u) /** Peripheral DC_0__DPR0 base pointer */ #define DC_0__DPR0 ((DPR_Type *)DC_0__DPR0_BASE) /** Peripheral DC_0__DPR1 base address */ #define DC_0__DPR1_BASE (0x56100000u) /** Peripheral DC_0__DPR1 base pointer */ #define DC_0__DPR1 ((DPR_Type *)DC_0__DPR1_BASE) /** Peripheral DC_1__DPR0 base address */ #define DC_1__DPR0_BASE (0x570D0000u) /** Peripheral DC_1__DPR0 base pointer */ #define DC_1__DPR0 ((DPR_Type *)DC_1__DPR0_BASE) /** Peripheral DC_1__DPR1 base address */ #define DC_1__DPR1_BASE (0x57100000u) /** Peripheral DC_1__DPR1 base pointer */ #define DC_1__DPR1 ((DPR_Type *)DC_1__DPR1_BASE) /** Array initializer of DPR peripheral base addresses */ #define DPR_BASE_ADDRS { DC_0__DPR0_BASE, DC_0__DPR1_BASE, DC_1__DPR0_BASE, DC_1__DPR1_BASE } /** Array initializer of DPR peripheral base pointers */ #define DPR_BASE_PTRS { DC_0__DPR0, DC_0__DPR1, DC_1__DPR0, DC_1__DPR1 } /* Backward compatibility */ /** Peripheral DC_0__DPR0_CH0 base address */ #define DC_0__DPR0_CH0_BASE DC_0__DPR0_BASE /** Peripheral DC_0__DPR0_CH0 base pointer */ #define DC_0__DPR0_CH0 ((DPR_Type *)DC_0__DPR0_CH0_BASE) /** Peripheral DC_0__DPR0_CH1 base address */ #define DC_0__DPR0_CH1_BASE (0x560E0000u) /** Peripheral DC_0__DPR0_CH1 base pointer */ #define DC_0__DPR0_CH1 ((DPR_Type *)DC_0__DPR0_CH1_BASE) /** Peripheral DC_0__DPR0_CH2 base address */ #define DC_0__DPR0_CH2_BASE (0x560F0000u) /** Peripheral DC_0__DPR0_CH2 base pointer */ #define DC_0__DPR0_CH2 ((DPR_Type *)DC_0__DPR0_CH2_BASE) /** Peripheral DC_0__DPR1_CH0 base address */ #define DC_0__DPR1_CH0_BASE DC_0__DPR1_BASE /** Peripheral DC_0__DPR1_CH0 base pointer */ #define DC_0__DPR1_CH0 ((DPR_Type *)DC_0__DPR1_CH0_BASE) /** Peripheral DC_0__DPR1_CH1 base address */ #define DC_0__DPR1_CH1_BASE (0x56110000u) /** Peripheral DC_0__DPR1_CH1 base pointer */ #define DC_0__DPR1_CH1 ((DPR_Type *)DC_0__DPR1_CH1_BASE) /** Peripheral DC_0__DPR1_CH2 base address */ #define DC_0__DPR1_CH2_BASE (0x56120000u) /** Peripheral DC_0__DPR1_CH2 base pointer */ #define DC_0__DPR1_CH2 ((DPR_Type *)DC_0__DPR1_CH2_BASE) /** Peripheral DC_1__DPR0_CH0 base address */ #define DC_1__DPR0_CH0_BASE DC_1__DPR0_BASE /** Peripheral DC_1__DPR0_CH0 base pointer */ #define DC_1__DPR0_CH0 ((DPR_Type *)DC_1__DPR0_CH0_BASE) /** Peripheral DC_1__DPR0_CH1 base address */ #define DC_1__DPR0_CH1_BASE (0x570E0000u) /** Peripheral DC_1__DPR0_CH1 base pointer */ #define DC_1__DPR0_CH1 ((DPR_Type *)DC_1__DPR0_CH1_BASE) /** Peripheral DC_1__DPR0_CH2 base address */ #define DC_1__DPR0_CH2_BASE (0x570F0000u) /** Peripheral DC_1__DPR0_CH2 base pointer */ #define DC_1__DPR0_CH2 ((DPR_Type *)DC_1__DPR0_CH2_BASE) /** Peripheral DC_1__DPR1_CH0 base address */ #define DC_1__DPR1_CH0_BASE DC_1__DPR1_BASE /** Peripheral DC_1__DPR1_CH0 base pointer */ #define DC_1__DPR1_CH0 ((DPR_Type *)DC_1__DPR1_CH0_BASE) /** Peripheral DC_1__DPR1_CH1 base address */ #define DC_1__DPR1_CH1_BASE (0x57110000u) /** Peripheral DC_1__DPR1_CH1 base pointer */ #define DC_1__DPR1_CH1 ((DPR_Type *)DC_1__DPR1_CH1_BASE) /** Peripheral DC_1__DPR1_CH2 base address */ #define DC_1__DPR1_CH2_BASE (0x57120000u) /** Peripheral DC_1__DPR1_CH2 base pointer */ #define DC_1__DPR1_CH2 ((DPR_Type *)DC_1__DPR1_CH2_BASE) /** Array initializer of DPR peripheral base addresses */ #define DPR_CH_BASE_ADDRS { DC_0__DPR0_CH0_BASE, DC_0__DPR0_CH1_BASE, DC_0__DPR0_CH2_BASE, DC_0__DPR1_CH0_BASE, DC_0__DPR1_CH1_BASE, DC_0__DPR1_CH2_BASE, \ DC_1__DPR0_CH0_BASE, DC_1__DPR0_CH1_BASE, DC_1__DPR0_CH2_BASE, DC_1__DPR1_CH0_BASE, DC_1__DPR1_CH1_BASE, DC_1__DPR1_CH2_BASE } /** Array initializer of DPR peripheral base pointers */ #define DPR_CH_BASE_PTRS { DC_0__DPR0_CH0, DC_0__DPR0_CH1, DC_0__DPR0_CH2, DC_0__DPR1_CH0, DC_0__DPR1_CH1, DC_0__DPR1_CH2, \ DC_1__DPR0_CH0, DC_1__DPR0_CH1, DC_1__DPR0_CH2, DC_1__DPR1_CH0, DC_1__DPR1_CH1, DC_1__DPR1_CH2 } /*! * @} */ /* end of group DPR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_ADC0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_ADC0_Peripheral_Access_Layer DMA_LPCG_ADC0 Peripheral Access Layer * @{ */ /** DMA_LPCG_ADC0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_ANAMIX_ADC0_0; /**< na, offset: 0x0 */ } DMA_LPCG_ADC0_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_ADC0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_ADC0_Register_Masks DMA_LPCG_ADC0 Register Masks * @{ */ /*! @name LPCG_ANAMIX_ADC0_0 - na */ /*! @{ */ #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_0_0_MASK (0x1U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_0_0_SHIFT (0U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_0_0_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_0_0_MASK) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_SWEN_MASK (0x2U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_SWEN_SHIFT (1U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_SWEN_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_SWEN_MASK) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_2_2_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_2_2_MASK) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_STOP_MASK (0x8U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_STOP_SHIFT (3U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_STOP_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_STOP_MASK) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_4_15_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_4_15_MASK) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_s_adc0_HWEN_MASK (0x10000U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_s_adc0_HWEN_SHIFT (16U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_s_adc0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_s_adc0_HWEN_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_s_adc0_HWEN_MASK) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN_MASK (0x20000U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN_SHIFT (17U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN_MASK) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_18_18_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_18_18_MASK) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP_MASK (0x80000U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP_SHIFT (19U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP_MASK) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_20_31_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_ADC0_Register_Masks */ /* DMA_LPCG_ADC0 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_ADC0 base address */ #define DMA__LPCG_ADC0_BASE (0x5AC80000u) /** Peripheral DMA__LPCG_ADC0 base pointer */ #define DMA__LPCG_ADC0 ((DMA_LPCG_ADC0_Type *)DMA__LPCG_ADC0_BASE) /** Array initializer of DMA_LPCG_ADC0 peripheral base addresses */ #define DMA_LPCG_ADC0_BASE_ADDRS { DMA__LPCG_ADC0_BASE } /** Array initializer of DMA_LPCG_ADC0 peripheral base pointers */ #define DMA_LPCG_ADC0_BASE_PTRS { DMA__LPCG_ADC0 } /*! * @} */ /* end of group DMA_LPCG_ADC0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_ADC1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_ADC1_Peripheral_Access_Layer DMA_LPCG_ADC1 Peripheral Access Layer * @{ */ /** DMA_LPCG_ADC1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_ANAMIX_ADC1_0; /**< na, offset: 0x0 */ } DMA_LPCG_ADC1_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_ADC1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_ADC1_Register_Masks DMA_LPCG_ADC1 Register Masks * @{ */ /*! @name LPCG_ANAMIX_ADC1_0 - na */ /*! @{ */ #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_0_0_MASK (0x1U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_0_0_SHIFT (0U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_0_0_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_0_0_MASK) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_SWEN_MASK (0x2U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_SWEN_SHIFT (1U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_SWEN_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_SWEN_MASK) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_2_2_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_2_2_MASK) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_STOP_MASK (0x8U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_STOP_SHIFT (3U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_STOP_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_STOP_MASK) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_4_15_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_4_15_MASK) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_s_adc1_HWEN_MASK (0x10000U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_s_adc1_HWEN_SHIFT (16U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_s_adc1_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_s_adc1_HWEN_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_s_adc1_HWEN_MASK) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_SWEN_AND_anamix_ipg_clk_s_adc1_SWEN_MASK (0x20000U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_SWEN_AND_anamix_ipg_clk_s_adc1_SWEN_SHIFT (17U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_SWEN_AND_anamix_ipg_clk_s_adc1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_SWEN_AND_anamix_ipg_clk_s_adc1_SWEN_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_SWEN_AND_anamix_ipg_clk_s_adc1_SWEN_MASK) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_18_18_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_18_18_MASK) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_STOP_AND_anamix_ipg_clk_s_adc1_STOP_MASK (0x80000U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_STOP_AND_anamix_ipg_clk_s_adc1_STOP_SHIFT (19U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_STOP_AND_anamix_ipg_clk_s_adc1_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_STOP_AND_anamix_ipg_clk_s_adc1_STOP_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_STOP_AND_anamix_ipg_clk_s_adc1_STOP_MASK) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_20_31_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_ADC1_Register_Masks */ /* DMA_LPCG_ADC1 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_ADC1 base address */ #define DMA__LPCG_ADC1_BASE (0x5AC90000u) /** Peripheral DMA__LPCG_ADC1 base pointer */ #define DMA__LPCG_ADC1 ((DMA_LPCG_ADC1_Type *)DMA__LPCG_ADC1_BASE) /** Array initializer of DMA_LPCG_ADC1 peripheral base addresses */ #define DMA_LPCG_ADC1_BASE_ADDRS { DMA__LPCG_ADC1_BASE } /** Array initializer of DMA_LPCG_ADC1 peripheral base pointers */ #define DMA_LPCG_ADC1_BASE_PTRS { DMA__LPCG_ADC1 } /*! * @} */ /* end of group DMA_LPCG_ADC1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_CAN0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_CAN0_Peripheral_Access_Layer DMA_LPCG_CAN0 Peripheral Access Layer * @{ */ /** DMA_LPCG_CAN0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_CAN0_0; /**< na, offset: 0x0 */ } DMA_LPCG_CAN0_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_CAN0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_CAN0_Register_Masks DMA_LPCG_CAN0 Register Masks * @{ */ /*! @name LPCG_CAN0_0 - na */ /*! @{ */ #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN_MASK (0x1U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN_SHIFT (0U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN_MASK) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_SWEN_AND_can0_ipg_clk_pe_nogate_SWEN_MASK (0x2U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_SWEN_AND_can0_ipg_clk_pe_nogate_SWEN_SHIFT (1U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_SWEN_AND_can0_ipg_clk_pe_nogate_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_SWEN_AND_can0_ipg_clk_pe_nogate_SWEN_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_SWEN_AND_can0_ipg_clk_pe_nogate_SWEN_MASK) #define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_2_2_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_2_2_MASK) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_STOP_AND_can0_ipg_clk_pe_nogate_STOP_MASK (0x8U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_STOP_AND_can0_ipg_clk_pe_nogate_STOP_SHIFT (3U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_STOP_AND_can0_ipg_clk_pe_nogate_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_STOP_AND_can0_ipg_clk_pe_nogate_STOP_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_STOP_AND_can0_ipg_clk_pe_nogate_STOP_MASK) #define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_4_15_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_4_15_MASK) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_18_18_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_18_18_MASK) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP_MASK) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN_MASK (0x100000U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN_SHIFT (20U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN_MASK) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN_MASK (0x200000U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN_SHIFT (21U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN_MASK) #define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_22_22_MASK (0x400000U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_22_22_SHIFT (22U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_22_22_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_22_22_MASK) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_STOP_MASK (0x800000U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_STOP_SHIFT (23U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_STOP_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_STOP_MASK) #define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_24_31_MASK (0xFF000000U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_24_31_SHIFT (24U) #define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_24_31_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_CAN0_Register_Masks */ /* DMA_LPCG_CAN0 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_CAN0 base address */ #define DMA__LPCG_CAN0_BASE (0x5ACD0000u) /** Peripheral DMA__LPCG_CAN0 base pointer */ #define DMA__LPCG_CAN0 ((DMA_LPCG_CAN0_Type *)DMA__LPCG_CAN0_BASE) /** Array initializer of DMA_LPCG_CAN0 peripheral base addresses */ #define DMA_LPCG_CAN0_BASE_ADDRS { DMA__LPCG_CAN0_BASE } /** Array initializer of DMA_LPCG_CAN0 peripheral base pointers */ #define DMA_LPCG_CAN0_BASE_PTRS { DMA__LPCG_CAN0 } /*! * @} */ /* end of group DMA_LPCG_CAN0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_CAN1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_CAN1_Peripheral_Access_Layer DMA_LPCG_CAN1 Peripheral Access Layer * @{ */ /** DMA_LPCG_CAN1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_CAN1_0; /**< na, offset: 0x0 */ } DMA_LPCG_CAN1_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_CAN1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_CAN1_Register_Masks DMA_LPCG_CAN1 Register Masks * @{ */ /*! @name LPCG_CAN1_0 - na */ /*! @{ */ #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN_MASK (0x1U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN_SHIFT (0U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN_MASK) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_SWEN_AND_can1_ipg_clk_pe_nogate_SWEN_MASK (0x2U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_SWEN_AND_can1_ipg_clk_pe_nogate_SWEN_SHIFT (1U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_SWEN_AND_can1_ipg_clk_pe_nogate_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_SWEN_AND_can1_ipg_clk_pe_nogate_SWEN_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_SWEN_AND_can1_ipg_clk_pe_nogate_SWEN_MASK) #define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_2_2_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_2_2_MASK) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_STOP_AND_can1_ipg_clk_pe_nogate_STOP_MASK (0x8U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_STOP_AND_can1_ipg_clk_pe_nogate_STOP_SHIFT (3U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_STOP_AND_can1_ipg_clk_pe_nogate_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_STOP_AND_can1_ipg_clk_pe_nogate_STOP_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_STOP_AND_can1_ipg_clk_pe_nogate_STOP_MASK) #define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_4_15_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_4_15_MASK) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_18_18_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_18_18_MASK) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP_MASK) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN_MASK (0x100000U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN_SHIFT (20U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN_MASK) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN_MASK (0x200000U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN_SHIFT (21U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN_MASK) #define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_22_22_MASK (0x400000U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_22_22_SHIFT (22U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_22_22_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_22_22_MASK) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_STOP_MASK (0x800000U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_STOP_SHIFT (23U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_STOP_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_STOP_MASK) #define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_24_31_MASK (0xFF000000U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_24_31_SHIFT (24U) #define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_24_31_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_CAN1_Register_Masks */ /* DMA_LPCG_CAN1 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_CAN1 base address */ #define DMA__LPCG_CAN1_BASE (0x5ACE0000u) /** Peripheral DMA__LPCG_CAN1 base pointer */ #define DMA__LPCG_CAN1 ((DMA_LPCG_CAN1_Type *)DMA__LPCG_CAN1_BASE) /** Array initializer of DMA_LPCG_CAN1 peripheral base addresses */ #define DMA_LPCG_CAN1_BASE_ADDRS { DMA__LPCG_CAN1_BASE } /** Array initializer of DMA_LPCG_CAN1 peripheral base pointers */ #define DMA_LPCG_CAN1_BASE_PTRS { DMA__LPCG_CAN1 } /*! * @} */ /* end of group DMA_LPCG_CAN1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_CAN2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_CAN2_Peripheral_Access_Layer DMA_LPCG_CAN2 Peripheral Access Layer * @{ */ /** DMA_LPCG_CAN2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_CAN2_0; /**< na, offset: 0x0 */ } DMA_LPCG_CAN2_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_CAN2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_CAN2_Register_Masks DMA_LPCG_CAN2 Register Masks * @{ */ /*! @name LPCG_CAN2_0 - na */ /*! @{ */ #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN_MASK (0x1U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN_SHIFT (0U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN_MASK) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_SWEN_AND_can2_ipg_clk_pe_nogate_SWEN_MASK (0x2U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_SWEN_AND_can2_ipg_clk_pe_nogate_SWEN_SHIFT (1U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_SWEN_AND_can2_ipg_clk_pe_nogate_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_SWEN_AND_can2_ipg_clk_pe_nogate_SWEN_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_SWEN_AND_can2_ipg_clk_pe_nogate_SWEN_MASK) #define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_2_2_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_2_2_MASK) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_STOP_AND_can2_ipg_clk_pe_nogate_STOP_MASK (0x8U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_STOP_AND_can2_ipg_clk_pe_nogate_STOP_SHIFT (3U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_STOP_AND_can2_ipg_clk_pe_nogate_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_STOP_AND_can2_ipg_clk_pe_nogate_STOP_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_STOP_AND_can2_ipg_clk_pe_nogate_STOP_MASK) #define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_4_15_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_4_15_MASK) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_18_18_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_18_18_MASK) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP_MASK) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN_MASK (0x100000U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN_SHIFT (20U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN_MASK) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN_MASK (0x200000U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN_SHIFT (21U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN_MASK) #define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_22_22_MASK (0x400000U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_22_22_SHIFT (22U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_22_22_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_22_22_MASK) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_STOP_MASK (0x800000U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_STOP_SHIFT (23U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_STOP_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_STOP_MASK) #define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_24_31_MASK (0xFF000000U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_24_31_SHIFT (24U) #define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_24_31_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_CAN2_Register_Masks */ /* DMA_LPCG_CAN2 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_CAN2 base address */ #define DMA__LPCG_CAN2_BASE (0x5ACF0000u) /** Peripheral DMA__LPCG_CAN2 base pointer */ #define DMA__LPCG_CAN2 ((DMA_LPCG_CAN2_Type *)DMA__LPCG_CAN2_BASE) /** Array initializer of DMA_LPCG_CAN2 peripheral base addresses */ #define DMA_LPCG_CAN2_BASE_ADDRS { DMA__LPCG_CAN2_BASE } /** Array initializer of DMA_LPCG_CAN2 peripheral base pointers */ #define DMA_LPCG_CAN2_BASE_PTRS { DMA__LPCG_CAN2 } /*! * @} */ /* end of group DMA_LPCG_CAN2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_EMV_SIM0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_EMV_SIM0_Peripheral_Access_Layer DMA_LPCG_EMV_SIM0 Peripheral Access Layer * @{ */ /** DMA_LPCG_EMV_SIM0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_EMV_SIM0_0; /**< na, offset: 0x0 */ } DMA_LPCG_EMV_SIM0_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_EMV_SIM0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_EMV_SIM0_Register_Masks DMA_LPCG_EMV_SIM0 Register Masks * @{ */ /*! @name LPCG_EMV_SIM0_0 - na */ /*! @{ */ #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_HWEN_MASK (0x1U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_HWEN_SHIFT (0U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_HWEN_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_HWEN_MASK) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_SWEN_AND_emv_sim0_ipg_ungated_sim_clk_SWEN_MASK (0x2U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_SWEN_AND_emv_sim0_ipg_ungated_sim_clk_SWEN_SHIFT (1U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_SWEN_AND_emv_sim0_ipg_ungated_sim_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_SWEN_AND_emv_sim0_ipg_ungated_sim_clk_SWEN_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_SWEN_AND_emv_sim0_ipg_ungated_sim_clk_SWEN_MASK) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_2_2_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_2_2_MASK) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_STOP_AND_emv_sim0_ipg_ungated_sim_clk_STOP_MASK (0x8U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_STOP_AND_emv_sim0_ipg_ungated_sim_clk_STOP_SHIFT (3U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_STOP_AND_emv_sim0_ipg_ungated_sim_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_STOP_AND_emv_sim0_ipg_ungated_sim_clk_STOP_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_STOP_AND_emv_sim0_ipg_ungated_sim_clk_STOP_MASK) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_4_15_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_4_15_MASK) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_SWEN_AND_emv_sim0_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_SWEN_AND_emv_sim0_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_SWEN_AND_emv_sim0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_SWEN_AND_emv_sim0_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_SWEN_AND_emv_sim0_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_18_18_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_18_18_MASK) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_STOP_AND_emv_sim0_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_STOP_AND_emv_sim0_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_STOP_AND_emv_sim0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_STOP_AND_emv_sim0_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_STOP_AND_emv_sim0_ipg_clk_s_STOP_MASK) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_20_31_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_EMV_SIM0_Register_Masks */ /* DMA_LPCG_EMV_SIM0 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_EMV_SIM0 base address */ #define DMA__LPCG_EMV_SIM0_BASE (0x5A4D0000u) /** Peripheral DMA__LPCG_EMV_SIM0 base pointer */ #define DMA__LPCG_EMV_SIM0 ((DMA_LPCG_EMV_SIM0_Type *)DMA__LPCG_EMV_SIM0_BASE) /** Array initializer of DMA_LPCG_EMV_SIM0 peripheral base addresses */ #define DMA_LPCG_EMV_SIM0_BASE_ADDRS { DMA__LPCG_EMV_SIM0_BASE } /** Array initializer of DMA_LPCG_EMV_SIM0 peripheral base pointers */ #define DMA_LPCG_EMV_SIM0_BASE_PTRS { DMA__LPCG_EMV_SIM0 } /*! * @} */ /* end of group DMA_LPCG_EMV_SIM0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_EMV_SIM1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_EMV_SIM1_Peripheral_Access_Layer DMA_LPCG_EMV_SIM1 Peripheral Access Layer * @{ */ /** DMA_LPCG_EMV_SIM1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_EMV_SIM1_0; /**< na, offset: 0x0 */ } DMA_LPCG_EMV_SIM1_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_EMV_SIM1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_EMV_SIM1_Register_Masks DMA_LPCG_EMV_SIM1 Register Masks * @{ */ /*! @name LPCG_EMV_SIM1_0 - na */ /*! @{ */ #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_HWEN_MASK (0x1U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_HWEN_SHIFT (0U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_HWEN_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_HWEN_MASK) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_SWEN_AND_emv_sim1_ipg_ungated_sim_clk_SWEN_MASK (0x2U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_SWEN_AND_emv_sim1_ipg_ungated_sim_clk_SWEN_SHIFT (1U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_SWEN_AND_emv_sim1_ipg_ungated_sim_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_SWEN_AND_emv_sim1_ipg_ungated_sim_clk_SWEN_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_SWEN_AND_emv_sim1_ipg_ungated_sim_clk_SWEN_MASK) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_2_2_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_2_2_MASK) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_STOP_AND_emv_sim1_ipg_ungated_sim_clk_STOP_MASK (0x8U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_STOP_AND_emv_sim1_ipg_ungated_sim_clk_STOP_SHIFT (3U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_STOP_AND_emv_sim1_ipg_ungated_sim_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_STOP_AND_emv_sim1_ipg_ungated_sim_clk_STOP_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_STOP_AND_emv_sim1_ipg_ungated_sim_clk_STOP_MASK) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_4_15_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_4_15_MASK) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_SWEN_AND_emv_sim1_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_SWEN_AND_emv_sim1_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_SWEN_AND_emv_sim1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_SWEN_AND_emv_sim1_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_SWEN_AND_emv_sim1_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_18_18_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_18_18_MASK) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_STOP_AND_emv_sim1_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_STOP_AND_emv_sim1_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_STOP_AND_emv_sim1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_STOP_AND_emv_sim1_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_STOP_AND_emv_sim1_ipg_clk_s_STOP_MASK) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_20_31_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_EMV_SIM1_Register_Masks */ /* DMA_LPCG_EMV_SIM1 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_EMV_SIM1 base address */ #define DMA__LPCG_EMV_SIM1_BASE (0x5A4E0000u) /** Peripheral DMA__LPCG_EMV_SIM1 base pointer */ #define DMA__LPCG_EMV_SIM1 ((DMA_LPCG_EMV_SIM1_Type *)DMA__LPCG_EMV_SIM1_BASE) /** Array initializer of DMA_LPCG_EMV_SIM1 peripheral base addresses */ #define DMA_LPCG_EMV_SIM1_BASE_ADDRS { DMA__LPCG_EMV_SIM1_BASE } /** Array initializer of DMA_LPCG_EMV_SIM1 peripheral base pointers */ #define DMA_LPCG_EMV_SIM1_BASE_PTRS { DMA__LPCG_EMV_SIM1 } /*! * @} */ /* end of group DMA_LPCG_EMV_SIM1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_FTM0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_FTM0_Peripheral_Access_Layer DMA_LPCG_FTM0 Peripheral Access Layer * @{ */ /** DMA_LPCG_FTM0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_FTM0_0; /**< na, offset: 0x0 */ } DMA_LPCG_FTM0_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_FTM0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_FTM0_Register_Masks DMA_LPCG_FTM0 Register Masks * @{ */ /*! @name LPCG_FTM0_0 - na */ /*! @{ */ #define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN_MASK (0x1U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN_SHIFT (0U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN_MASK) #define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN_MASK (0x2U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN_SHIFT (1U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN_MASK) #define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_2_2_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_2_2_MASK) #define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP_MASK (0x8U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP_SHIFT (3U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP_MASK) #define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_4_15_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_4_15_MASK) #define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_18_18_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_18_18_MASK) #define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP_MASK) #define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_20_31_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_FTM0_Register_Masks */ /* DMA_LPCG_FTM0 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_FTM0 base address */ #define DMA__LPCG_FTM0_BASE (0x5ACA0000u) /** Peripheral DMA__LPCG_FTM0 base pointer */ #define DMA__LPCG_FTM0 ((DMA_LPCG_FTM0_Type *)DMA__LPCG_FTM0_BASE) /** Array initializer of DMA_LPCG_FTM0 peripheral base addresses */ #define DMA_LPCG_FTM0_BASE_ADDRS { DMA__LPCG_FTM0_BASE } /** Array initializer of DMA_LPCG_FTM0 peripheral base pointers */ #define DMA_LPCG_FTM0_BASE_PTRS { DMA__LPCG_FTM0 } /*! * @} */ /* end of group DMA_LPCG_FTM0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_FTM1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_FTM1_Peripheral_Access_Layer DMA_LPCG_FTM1 Peripheral Access Layer * @{ */ /** DMA_LPCG_FTM1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_FTM1_0; /**< na, offset: 0x0 */ } DMA_LPCG_FTM1_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_FTM1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_FTM1_Register_Masks DMA_LPCG_FTM1 Register Masks * @{ */ /*! @name LPCG_FTM1_0 - na */ /*! @{ */ #define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN_MASK (0x1U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN_SHIFT (0U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN_MASK) #define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN_MASK (0x2U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN_SHIFT (1U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN_MASK) #define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_2_2_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_2_2_MASK) #define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP_MASK (0x8U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP_SHIFT (3U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP_MASK) #define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_4_15_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_4_15_MASK) #define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_18_18_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_18_18_MASK) #define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP_MASK) #define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_20_31_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_FTM1_Register_Masks */ /* DMA_LPCG_FTM1 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_FTM1 base address */ #define DMA__LPCG_FTM1_BASE (0x5ACB0000u) /** Peripheral DMA__LPCG_FTM1 base pointer */ #define DMA__LPCG_FTM1 ((DMA_LPCG_FTM1_Type *)DMA__LPCG_FTM1_BASE) /** Array initializer of DMA_LPCG_FTM1 peripheral base addresses */ #define DMA_LPCG_FTM1_BASE_ADDRS { DMA__LPCG_FTM1_BASE } /** Array initializer of DMA_LPCG_FTM1 peripheral base pointers */ #define DMA_LPCG_FTM1_BASE_PTRS { DMA__LPCG_FTM1 } /*! * @} */ /* end of group DMA_LPCG_FTM1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPI2C0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPI2C0_Peripheral_Access_Layer DMA_LPCG_LPI2C0 Peripheral Access Layer * @{ */ /** DMA_LPCG_LPI2C0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPI2C0_0; /**< na, offset: 0x0 */ } DMA_LPCG_LPI2C0_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPI2C0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPI2C0_Register_Masks DMA_LPCG_LPI2C0 Register Masks * @{ */ /*! @name LPCG_LPI2C0_0 - na */ /*! @{ */ #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_div_clk_HWEN_MASK (0x1U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_div_clk_HWEN_SHIFT (0U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_div_clk_HWEN_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_div_clk_HWEN_MASK) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_MASK (0x2U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_SHIFT (1U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_MASK) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_2_2_MASK) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_MASK (0x8U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_SHIFT (3U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_MASK) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_4_15_MASK) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_18_18_MASK) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_MASK) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_LPI2C0_Register_Masks */ /* DMA_LPCG_LPI2C0 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_LPI2C0 base address */ #define DMA__LPCG_LPI2C0_BASE (0x5AC00000u) /** Peripheral DMA__LPCG_LPI2C0 base pointer */ #define DMA__LPCG_LPI2C0 ((DMA_LPCG_LPI2C0_Type *)DMA__LPCG_LPI2C0_BASE) /** Array initializer of DMA_LPCG_LPI2C0 peripheral base addresses */ #define DMA_LPCG_LPI2C0_BASE_ADDRS { DMA__LPCG_LPI2C0_BASE } /** Array initializer of DMA_LPCG_LPI2C0 peripheral base pointers */ #define DMA_LPCG_LPI2C0_BASE_PTRS { DMA__LPCG_LPI2C0 } /*! * @} */ /* end of group DMA_LPCG_LPI2C0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPI2C1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPI2C1_Peripheral_Access_Layer DMA_LPCG_LPI2C1 Peripheral Access Layer * @{ */ /** DMA_LPCG_LPI2C1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPI2C1_0; /**< na, offset: 0x0 */ } DMA_LPCG_LPI2C1_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPI2C1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPI2C1_Register_Masks DMA_LPCG_LPI2C1 Register Masks * @{ */ /*! @name LPCG_LPI2C1_0 - na */ /*! @{ */ #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_div_clk_HWEN_MASK) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_2_2_MASK) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_4_15_MASK) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_18_18_MASK) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_MASK) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_LPI2C1_Register_Masks */ /* DMA_LPCG_LPI2C1 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_LPI2C1 base address */ #define DMA__LPCG_LPI2C1_BASE (0x5AC10000u) /** Peripheral DMA__LPCG_LPI2C1 base pointer */ #define DMA__LPCG_LPI2C1 ((DMA_LPCG_LPI2C1_Type *)DMA__LPCG_LPI2C1_BASE) /** Array initializer of DMA_LPCG_LPI2C1 peripheral base addresses */ #define DMA_LPCG_LPI2C1_BASE_ADDRS { DMA__LPCG_LPI2C1_BASE } /** Array initializer of DMA_LPCG_LPI2C1 peripheral base pointers */ #define DMA_LPCG_LPI2C1_BASE_PTRS { DMA__LPCG_LPI2C1 } /*! * @} */ /* end of group DMA_LPCG_LPI2C1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPI2C2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPI2C2_Peripheral_Access_Layer DMA_LPCG_LPI2C2 Peripheral Access Layer * @{ */ /** DMA_LPCG_LPI2C2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPI2C2_0; /**< na, offset: 0x0 */ } DMA_LPCG_LPI2C2_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPI2C2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPI2C2_Register_Masks DMA_LPCG_LPI2C2 Register Masks * @{ */ /*! @name LPCG_LPI2C2_0 - na */ /*! @{ */ #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_div_clk_HWEN_MASK (0x1U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_div_clk_HWEN_SHIFT (0U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_div_clk_HWEN_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_div_clk_HWEN_MASK) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_SWEN_AND_lpi2c2_lpi2c_div_clk_SWEN_MASK (0x2U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_SWEN_AND_lpi2c2_lpi2c_div_clk_SWEN_SHIFT (1U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_SWEN_AND_lpi2c2_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_SWEN_AND_lpi2c2_lpi2c_div_clk_SWEN_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_SWEN_AND_lpi2c2_lpi2c_div_clk_SWEN_MASK) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_2_2_MASK) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_STOP_AND_lpi2c2_lpi2c_div_clk_STOP_MASK (0x8U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_STOP_AND_lpi2c2_lpi2c_div_clk_STOP_SHIFT (3U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_STOP_AND_lpi2c2_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_STOP_AND_lpi2c2_lpi2c_div_clk_STOP_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_STOP_AND_lpi2c2_lpi2c_div_clk_STOP_MASK) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_4_15_MASK) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_SWEN_AND_lpi2c2_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_SWEN_AND_lpi2c2_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_SWEN_AND_lpi2c2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_SWEN_AND_lpi2c2_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_SWEN_AND_lpi2c2_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_18_18_MASK) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_STOP_AND_lpi2c2_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_STOP_AND_lpi2c2_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_STOP_AND_lpi2c2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_STOP_AND_lpi2c2_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_STOP_AND_lpi2c2_ipg_clk_s_STOP_MASK) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_LPI2C2_Register_Masks */ /* DMA_LPCG_LPI2C2 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_LPI2C2 base address */ #define DMA__LPCG_LPI2C2_BASE (0x5AC20000u) /** Peripheral DMA__LPCG_LPI2C2 base pointer */ #define DMA__LPCG_LPI2C2 ((DMA_LPCG_LPI2C2_Type *)DMA__LPCG_LPI2C2_BASE) /** Array initializer of DMA_LPCG_LPI2C2 peripheral base addresses */ #define DMA_LPCG_LPI2C2_BASE_ADDRS { DMA__LPCG_LPI2C2_BASE } /** Array initializer of DMA_LPCG_LPI2C2 peripheral base pointers */ #define DMA_LPCG_LPI2C2_BASE_PTRS { DMA__LPCG_LPI2C2 } /*! * @} */ /* end of group DMA_LPCG_LPI2C2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPI2C3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPI2C3_Peripheral_Access_Layer DMA_LPCG_LPI2C3 Peripheral Access Layer * @{ */ /** DMA_LPCG_LPI2C3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPI2C3_0; /**< na, offset: 0x0 */ } DMA_LPCG_LPI2C3_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPI2C3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPI2C3_Register_Masks DMA_LPCG_LPI2C3 Register Masks * @{ */ /*! @name LPCG_LPI2C3_0 - na */ /*! @{ */ #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_div_clk_HWEN_MASK (0x1U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_div_clk_HWEN_SHIFT (0U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_div_clk_HWEN_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_div_clk_HWEN_MASK) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_SWEN_AND_lpi2c3_lpi2c_div_clk_SWEN_MASK (0x2U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_SWEN_AND_lpi2c3_lpi2c_div_clk_SWEN_SHIFT (1U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_SWEN_AND_lpi2c3_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_SWEN_AND_lpi2c3_lpi2c_div_clk_SWEN_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_SWEN_AND_lpi2c3_lpi2c_div_clk_SWEN_MASK) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_2_2_MASK) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_STOP_AND_lpi2c3_lpi2c_div_clk_STOP_MASK (0x8U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_STOP_AND_lpi2c3_lpi2c_div_clk_STOP_SHIFT (3U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_STOP_AND_lpi2c3_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_STOP_AND_lpi2c3_lpi2c_div_clk_STOP_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_STOP_AND_lpi2c3_lpi2c_div_clk_STOP_MASK) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_4_15_MASK) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_SWEN_AND_lpi2c3_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_SWEN_AND_lpi2c3_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_SWEN_AND_lpi2c3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_SWEN_AND_lpi2c3_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_SWEN_AND_lpi2c3_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_18_18_MASK) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_STOP_AND_lpi2c3_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_STOP_AND_lpi2c3_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_STOP_AND_lpi2c3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_STOP_AND_lpi2c3_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_STOP_AND_lpi2c3_ipg_clk_s_STOP_MASK) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_LPI2C3_Register_Masks */ /* DMA_LPCG_LPI2C3 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_LPI2C3 base address */ #define DMA__LPCG_LPI2C3_BASE (0x5AC30000u) /** Peripheral DMA__LPCG_LPI2C3 base pointer */ #define DMA__LPCG_LPI2C3 ((DMA_LPCG_LPI2C3_Type *)DMA__LPCG_LPI2C3_BASE) /** Array initializer of DMA_LPCG_LPI2C3 peripheral base addresses */ #define DMA_LPCG_LPI2C3_BASE_ADDRS { DMA__LPCG_LPI2C3_BASE } /** Array initializer of DMA_LPCG_LPI2C3 peripheral base pointers */ #define DMA_LPCG_LPI2C3_BASE_PTRS { DMA__LPCG_LPI2C3 } /*! * @} */ /* end of group DMA_LPCG_LPI2C3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPI2C4 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPI2C4_Peripheral_Access_Layer DMA_LPCG_LPI2C4 Peripheral Access Layer * @{ */ /** DMA_LPCG_LPI2C4 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPI2C4_0; /**< na, offset: 0x0 */ } DMA_LPCG_LPI2C4_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPI2C4 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPI2C4_Register_Masks DMA_LPCG_LPI2C4 Register Masks * @{ */ /*! @name LPCG_LPI2C4_0 - na */ /*! @{ */ #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_div_clk_HWEN_MASK (0x1U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_div_clk_HWEN_SHIFT (0U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_div_clk_HWEN_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_div_clk_HWEN_MASK) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_SWEN_AND_lpi2c4_lpi2c_div_clk_SWEN_MASK (0x2U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_SWEN_AND_lpi2c4_lpi2c_div_clk_SWEN_SHIFT (1U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_SWEN_AND_lpi2c4_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_SWEN_AND_lpi2c4_lpi2c_div_clk_SWEN_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_SWEN_AND_lpi2c4_lpi2c_div_clk_SWEN_MASK) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_2_2_MASK) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_STOP_AND_lpi2c4_lpi2c_div_clk_STOP_MASK (0x8U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_STOP_AND_lpi2c4_lpi2c_div_clk_STOP_SHIFT (3U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_STOP_AND_lpi2c4_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_STOP_AND_lpi2c4_lpi2c_div_clk_STOP_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_STOP_AND_lpi2c4_lpi2c_div_clk_STOP_MASK) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_4_15_MASK) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_SWEN_AND_lpi2c4_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_SWEN_AND_lpi2c4_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_SWEN_AND_lpi2c4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_SWEN_AND_lpi2c4_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_SWEN_AND_lpi2c4_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_18_18_MASK) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_STOP_AND_lpi2c4_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_STOP_AND_lpi2c4_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_STOP_AND_lpi2c4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_STOP_AND_lpi2c4_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_STOP_AND_lpi2c4_ipg_clk_s_STOP_MASK) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_LPI2C4_Register_Masks */ /* DMA_LPCG_LPI2C4 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_LPI2C4 base address */ #define DMA__LPCG_LPI2C4_BASE (0x5AC40000u) /** Peripheral DMA__LPCG_LPI2C4 base pointer */ #define DMA__LPCG_LPI2C4 ((DMA_LPCG_LPI2C4_Type *)DMA__LPCG_LPI2C4_BASE) /** Array initializer of DMA_LPCG_LPI2C4 peripheral base addresses */ #define DMA_LPCG_LPI2C4_BASE_ADDRS { DMA__LPCG_LPI2C4_BASE } /** Array initializer of DMA_LPCG_LPI2C4 peripheral base pointers */ #define DMA_LPCG_LPI2C4_BASE_PTRS { DMA__LPCG_LPI2C4 } /*! * @} */ /* end of group DMA_LPCG_LPI2C4_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPSPI0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPSPI0_Peripheral_Access_Layer DMA_LPCG_LPSPI0 Peripheral Access Layer * @{ */ /** DMA_LPCG_LPSPI0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPSPI0_0; /**< na, offset: 0x0 */ } DMA_LPCG_LPSPI0_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPSPI0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPSPI0_Register_Masks DMA_LPCG_LPSPI0 Register Masks * @{ */ /*! @name LPCG_LPSPI0_0 - na */ /*! @{ */ #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_div_clk_HWEN_MASK (0x1U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_div_clk_HWEN_SHIFT (0U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_div_clk_HWEN_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_div_clk_HWEN_MASK) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_SWEN_AND_lpspi0_lpspi_div_clk_SWEN_MASK (0x2U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_SWEN_AND_lpspi0_lpspi_div_clk_SWEN_SHIFT (1U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_SWEN_AND_lpspi0_lpspi_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_SWEN_AND_lpspi0_lpspi_div_clk_SWEN_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_SWEN_AND_lpspi0_lpspi_div_clk_SWEN_MASK) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_2_2_MASK) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_STOP_AND_lpspi0_lpspi_div_clk_STOP_MASK (0x8U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_STOP_AND_lpspi0_lpspi_div_clk_STOP_SHIFT (3U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_STOP_AND_lpspi0_lpspi_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_STOP_AND_lpspi0_lpspi_div_clk_STOP_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_STOP_AND_lpspi0_lpspi_div_clk_STOP_MASK) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_4_15_MASK) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_SWEN_AND_lpspi0_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_SWEN_AND_lpspi0_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_SWEN_AND_lpspi0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_SWEN_AND_lpspi0_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_SWEN_AND_lpspi0_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_18_18_MASK) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_STOP_AND_lpspi0_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_STOP_AND_lpspi0_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_STOP_AND_lpspi0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_STOP_AND_lpspi0_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_STOP_AND_lpspi0_ipg_clk_s_STOP_MASK) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_LPSPI0_Register_Masks */ /* DMA_LPCG_LPSPI0 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_LPSPI0 base address */ #define DMA__LPCG_LPSPI0_BASE (0x5A400000u) /** Peripheral DMA__LPCG_LPSPI0 base pointer */ #define DMA__LPCG_LPSPI0 ((DMA_LPCG_LPSPI0_Type *)DMA__LPCG_LPSPI0_BASE) /** Array initializer of DMA_LPCG_LPSPI0 peripheral base addresses */ #define DMA_LPCG_LPSPI0_BASE_ADDRS { DMA__LPCG_LPSPI0_BASE } /** Array initializer of DMA_LPCG_LPSPI0 peripheral base pointers */ #define DMA_LPCG_LPSPI0_BASE_PTRS { DMA__LPCG_LPSPI0 } /*! * @} */ /* end of group DMA_LPCG_LPSPI0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPSPI1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPSPI1_Peripheral_Access_Layer DMA_LPCG_LPSPI1 Peripheral Access Layer * @{ */ /** DMA_LPCG_LPSPI1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPSPI1_0; /**< na, offset: 0x0 */ } DMA_LPCG_LPSPI1_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPSPI1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPSPI1_Register_Masks DMA_LPCG_LPSPI1 Register Masks * @{ */ /*! @name LPCG_LPSPI1_0 - na */ /*! @{ */ #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_div_clk_HWEN_MASK (0x1U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_div_clk_HWEN_SHIFT (0U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_div_clk_HWEN_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_div_clk_HWEN_MASK) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_SWEN_AND_lpspi1_lpspi_div_clk_SWEN_MASK (0x2U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_SWEN_AND_lpspi1_lpspi_div_clk_SWEN_SHIFT (1U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_SWEN_AND_lpspi1_lpspi_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_SWEN_AND_lpspi1_lpspi_div_clk_SWEN_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_SWEN_AND_lpspi1_lpspi_div_clk_SWEN_MASK) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_2_2_MASK) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_STOP_AND_lpspi1_lpspi_div_clk_STOP_MASK (0x8U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_STOP_AND_lpspi1_lpspi_div_clk_STOP_SHIFT (3U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_STOP_AND_lpspi1_lpspi_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_STOP_AND_lpspi1_lpspi_div_clk_STOP_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_STOP_AND_lpspi1_lpspi_div_clk_STOP_MASK) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_4_15_MASK) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_SWEN_AND_lpspi1_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_SWEN_AND_lpspi1_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_SWEN_AND_lpspi1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_SWEN_AND_lpspi1_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_SWEN_AND_lpspi1_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_18_18_MASK) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_STOP_AND_lpspi1_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_STOP_AND_lpspi1_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_STOP_AND_lpspi1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_STOP_AND_lpspi1_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_STOP_AND_lpspi1_ipg_clk_s_STOP_MASK) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_LPSPI1_Register_Masks */ /* DMA_LPCG_LPSPI1 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_LPSPI1 base address */ #define DMA__LPCG_LPSPI1_BASE (0x5A410000u) /** Peripheral DMA__LPCG_LPSPI1 base pointer */ #define DMA__LPCG_LPSPI1 ((DMA_LPCG_LPSPI1_Type *)DMA__LPCG_LPSPI1_BASE) /** Array initializer of DMA_LPCG_LPSPI1 peripheral base addresses */ #define DMA_LPCG_LPSPI1_BASE_ADDRS { DMA__LPCG_LPSPI1_BASE } /** Array initializer of DMA_LPCG_LPSPI1 peripheral base pointers */ #define DMA_LPCG_LPSPI1_BASE_PTRS { DMA__LPCG_LPSPI1 } /*! * @} */ /* end of group DMA_LPCG_LPSPI1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPSPI2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPSPI2_Peripheral_Access_Layer DMA_LPCG_LPSPI2 Peripheral Access Layer * @{ */ /** DMA_LPCG_LPSPI2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPSPI2_0; /**< na, offset: 0x0 */ } DMA_LPCG_LPSPI2_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPSPI2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPSPI2_Register_Masks DMA_LPCG_LPSPI2 Register Masks * @{ */ /*! @name LPCG_LPSPI2_0 - na */ /*! @{ */ #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_div_clk_HWEN_MASK (0x1U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_div_clk_HWEN_SHIFT (0U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_div_clk_HWEN_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_div_clk_HWEN_MASK) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_SWEN_AND_lpspi2_lpspi_div_clk_SWEN_MASK (0x2U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_SWEN_AND_lpspi2_lpspi_div_clk_SWEN_SHIFT (1U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_SWEN_AND_lpspi2_lpspi_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_SWEN_AND_lpspi2_lpspi_div_clk_SWEN_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_SWEN_AND_lpspi2_lpspi_div_clk_SWEN_MASK) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_2_2_MASK) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_STOP_AND_lpspi2_lpspi_div_clk_STOP_MASK (0x8U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_STOP_AND_lpspi2_lpspi_div_clk_STOP_SHIFT (3U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_STOP_AND_lpspi2_lpspi_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_STOP_AND_lpspi2_lpspi_div_clk_STOP_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_STOP_AND_lpspi2_lpspi_div_clk_STOP_MASK) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_4_15_MASK) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_SWEN_AND_lpspi2_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_SWEN_AND_lpspi2_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_SWEN_AND_lpspi2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_SWEN_AND_lpspi2_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_SWEN_AND_lpspi2_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_18_18_MASK) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_STOP_AND_lpspi2_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_STOP_AND_lpspi2_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_STOP_AND_lpspi2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_STOP_AND_lpspi2_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_STOP_AND_lpspi2_ipg_clk_s_STOP_MASK) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_LPSPI2_Register_Masks */ /* DMA_LPCG_LPSPI2 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_LPSPI2 base address */ #define DMA__LPCG_LPSPI2_BASE (0x5A420000u) /** Peripheral DMA__LPCG_LPSPI2 base pointer */ #define DMA__LPCG_LPSPI2 ((DMA_LPCG_LPSPI2_Type *)DMA__LPCG_LPSPI2_BASE) /** Array initializer of DMA_LPCG_LPSPI2 peripheral base addresses */ #define DMA_LPCG_LPSPI2_BASE_ADDRS { DMA__LPCG_LPSPI2_BASE } /** Array initializer of DMA_LPCG_LPSPI2 peripheral base pointers */ #define DMA_LPCG_LPSPI2_BASE_PTRS { DMA__LPCG_LPSPI2 } /*! * @} */ /* end of group DMA_LPCG_LPSPI2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPSPI3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPSPI3_Peripheral_Access_Layer DMA_LPCG_LPSPI3 Peripheral Access Layer * @{ */ /** DMA_LPCG_LPSPI3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPSPI3_0; /**< na, offset: 0x0 */ } DMA_LPCG_LPSPI3_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPSPI3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPSPI3_Register_Masks DMA_LPCG_LPSPI3 Register Masks * @{ */ /*! @name LPCG_LPSPI3_0 - na */ /*! @{ */ #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_div_clk_HWEN_MASK (0x1U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_div_clk_HWEN_SHIFT (0U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_div_clk_HWEN_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_div_clk_HWEN_MASK) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_SWEN_AND_lpspi3_lpspi_div_clk_SWEN_MASK (0x2U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_SWEN_AND_lpspi3_lpspi_div_clk_SWEN_SHIFT (1U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_SWEN_AND_lpspi3_lpspi_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_SWEN_AND_lpspi3_lpspi_div_clk_SWEN_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_SWEN_AND_lpspi3_lpspi_div_clk_SWEN_MASK) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_2_2_MASK) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_STOP_AND_lpspi3_lpspi_div_clk_STOP_MASK (0x8U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_STOP_AND_lpspi3_lpspi_div_clk_STOP_SHIFT (3U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_STOP_AND_lpspi3_lpspi_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_STOP_AND_lpspi3_lpspi_div_clk_STOP_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_STOP_AND_lpspi3_lpspi_div_clk_STOP_MASK) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_4_15_MASK) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_SWEN_AND_lpspi3_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_SWEN_AND_lpspi3_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_SWEN_AND_lpspi3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_SWEN_AND_lpspi3_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_SWEN_AND_lpspi3_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_18_18_MASK) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_STOP_AND_lpspi3_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_STOP_AND_lpspi3_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_STOP_AND_lpspi3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_STOP_AND_lpspi3_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_STOP_AND_lpspi3_ipg_clk_s_STOP_MASK) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_LPSPI3_Register_Masks */ /* DMA_LPCG_LPSPI3 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_LPSPI3 base address */ #define DMA__LPCG_LPSPI3_BASE (0x5A430000u) /** Peripheral DMA__LPCG_LPSPI3 base pointer */ #define DMA__LPCG_LPSPI3 ((DMA_LPCG_LPSPI3_Type *)DMA__LPCG_LPSPI3_BASE) /** Array initializer of DMA_LPCG_LPSPI3 peripheral base addresses */ #define DMA_LPCG_LPSPI3_BASE_ADDRS { DMA__LPCG_LPSPI3_BASE } /** Array initializer of DMA_LPCG_LPSPI3 peripheral base pointers */ #define DMA_LPCG_LPSPI3_BASE_PTRS { DMA__LPCG_LPSPI3 } /*! * @} */ /* end of group DMA_LPCG_LPSPI3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPUART0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPUART0_Peripheral_Access_Layer DMA_LPCG_LPUART0 Peripheral Access Layer * @{ */ /** DMA_LPCG_LPUART0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPUART0_0; /**< na, offset: 0x0 */ } DMA_LPCG_LPUART0_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPUART0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPUART0_Register_Masks DMA_LPCG_LPUART0 Register Masks * @{ */ /*! @name LPCG_LPUART0_0 - na */ /*! @{ */ #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_gated_clk_HWEN_MASK (0x1U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_gated_clk_HWEN_SHIFT (0U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_gated_clk_HWEN_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_gated_clk_HWEN_MASK) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_SWEN_AND_lpuart0_lpuart_baud_gated_clk_SWEN_MASK (0x2U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_SWEN_AND_lpuart0_lpuart_baud_gated_clk_SWEN_SHIFT (1U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_SWEN_AND_lpuart0_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_SWEN_AND_lpuart0_lpuart_baud_gated_clk_SWEN_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_SWEN_AND_lpuart0_lpuart_baud_gated_clk_SWEN_MASK) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_2_2_MASK) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_STOP_AND_lpuart0_lpuart_baud_gated_clk_STOP_MASK (0x8U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_STOP_AND_lpuart0_lpuart_baud_gated_clk_STOP_SHIFT (3U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_STOP_AND_lpuart0_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_STOP_AND_lpuart0_lpuart_baud_gated_clk_STOP_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_STOP_AND_lpuart0_lpuart_baud_gated_clk_STOP_MASK) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_4_15_MASK) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_SWEN_AND_lpuart0_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_SWEN_AND_lpuart0_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_SWEN_AND_lpuart0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_SWEN_AND_lpuart0_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_SWEN_AND_lpuart0_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_18_18_MASK) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_STOP_AND_lpuart0_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_STOP_AND_lpuart0_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_STOP_AND_lpuart0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_STOP_AND_lpuart0_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_STOP_AND_lpuart0_ipg_clk_s_STOP_MASK) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_LPUART0_Register_Masks */ /* DMA_LPCG_LPUART0 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_LPUART0 base address */ #define DMA__LPCG_LPUART0_BASE (0x5A460000u) /** Peripheral DMA__LPCG_LPUART0 base pointer */ #define DMA__LPCG_LPUART0 ((DMA_LPCG_LPUART0_Type *)DMA__LPCG_LPUART0_BASE) /** Array initializer of DMA_LPCG_LPUART0 peripheral base addresses */ #define DMA_LPCG_LPUART0_BASE_ADDRS { DMA__LPCG_LPUART0_BASE } /** Array initializer of DMA_LPCG_LPUART0 peripheral base pointers */ #define DMA_LPCG_LPUART0_BASE_PTRS { DMA__LPCG_LPUART0 } /*! * @} */ /* end of group DMA_LPCG_LPUART0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPUART1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPUART1_Peripheral_Access_Layer DMA_LPCG_LPUART1 Peripheral Access Layer * @{ */ /** DMA_LPCG_LPUART1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPUART1_0; /**< na, offset: 0x0 */ } DMA_LPCG_LPUART1_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPUART1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPUART1_Register_Masks DMA_LPCG_LPUART1 Register Masks * @{ */ /*! @name LPCG_LPUART1_0 - na */ /*! @{ */ #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK (0x1U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT (0U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK (0x2U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT (1U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_2_2_MASK) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK (0x8U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT (3U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_4_15_MASK) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_SWEN_AND_lpuart1_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_SWEN_AND_lpuart1_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_SWEN_AND_lpuart1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_SWEN_AND_lpuart1_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_SWEN_AND_lpuart1_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_18_18_MASK) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_STOP_AND_lpuart1_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_STOP_AND_lpuart1_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_STOP_AND_lpuart1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_STOP_AND_lpuart1_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_STOP_AND_lpuart1_ipg_clk_s_STOP_MASK) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_LPUART1_Register_Masks */ /* DMA_LPCG_LPUART1 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_LPUART1 base address */ #define DMA__LPCG_LPUART1_BASE (0x5A470000u) /** Peripheral DMA__LPCG_LPUART1 base pointer */ #define DMA__LPCG_LPUART1 ((DMA_LPCG_LPUART1_Type *)DMA__LPCG_LPUART1_BASE) /** Array initializer of DMA_LPCG_LPUART1 peripheral base addresses */ #define DMA_LPCG_LPUART1_BASE_ADDRS { DMA__LPCG_LPUART1_BASE } /** Array initializer of DMA_LPCG_LPUART1 peripheral base pointers */ #define DMA_LPCG_LPUART1_BASE_PTRS { DMA__LPCG_LPUART1 } /*! * @} */ /* end of group DMA_LPCG_LPUART1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPUART2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPUART2_Peripheral_Access_Layer DMA_LPCG_LPUART2 Peripheral Access Layer * @{ */ /** DMA_LPCG_LPUART2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPUART2_0; /**< na, offset: 0x0 */ } DMA_LPCG_LPUART2_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPUART2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPUART2_Register_Masks DMA_LPCG_LPUART2 Register Masks * @{ */ /*! @name LPCG_LPUART2_0 - na */ /*! @{ */ #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_gated_clk_HWEN_MASK (0x1U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_gated_clk_HWEN_SHIFT (0U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_gated_clk_HWEN_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_gated_clk_HWEN_MASK) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_SWEN_AND_lpuart2_lpuart_baud_gated_clk_SWEN_MASK (0x2U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_SWEN_AND_lpuart2_lpuart_baud_gated_clk_SWEN_SHIFT (1U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_SWEN_AND_lpuart2_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_SWEN_AND_lpuart2_lpuart_baud_gated_clk_SWEN_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_SWEN_AND_lpuart2_lpuart_baud_gated_clk_SWEN_MASK) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_2_2_MASK) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_STOP_AND_lpuart2_lpuart_baud_gated_clk_STOP_MASK (0x8U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_STOP_AND_lpuart2_lpuart_baud_gated_clk_STOP_SHIFT (3U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_STOP_AND_lpuart2_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_STOP_AND_lpuart2_lpuart_baud_gated_clk_STOP_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_STOP_AND_lpuart2_lpuart_baud_gated_clk_STOP_MASK) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_4_15_MASK) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_SWEN_AND_lpuart2_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_SWEN_AND_lpuart2_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_SWEN_AND_lpuart2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_SWEN_AND_lpuart2_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_SWEN_AND_lpuart2_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_18_18_MASK) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_STOP_AND_lpuart2_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_STOP_AND_lpuart2_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_STOP_AND_lpuart2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_STOP_AND_lpuart2_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_STOP_AND_lpuart2_ipg_clk_s_STOP_MASK) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_LPUART2_Register_Masks */ /* DMA_LPCG_LPUART2 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_LPUART2 base address */ #define DMA__LPCG_LPUART2_BASE (0x5A480000u) /** Peripheral DMA__LPCG_LPUART2 base pointer */ #define DMA__LPCG_LPUART2 ((DMA_LPCG_LPUART2_Type *)DMA__LPCG_LPUART2_BASE) /** Array initializer of DMA_LPCG_LPUART2 peripheral base addresses */ #define DMA_LPCG_LPUART2_BASE_ADDRS { DMA__LPCG_LPUART2_BASE } /** Array initializer of DMA_LPCG_LPUART2 peripheral base pointers */ #define DMA_LPCG_LPUART2_BASE_PTRS { DMA__LPCG_LPUART2 } /*! * @} */ /* end of group DMA_LPCG_LPUART2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPUART3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPUART3_Peripheral_Access_Layer DMA_LPCG_LPUART3 Peripheral Access Layer * @{ */ /** DMA_LPCG_LPUART3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPUART3_0; /**< na, offset: 0x0 */ } DMA_LPCG_LPUART3_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPUART3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPUART3_Register_Masks DMA_LPCG_LPUART3 Register Masks * @{ */ /*! @name LPCG_LPUART3_0 - na */ /*! @{ */ #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_gated_clk_HWEN_MASK (0x1U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_gated_clk_HWEN_SHIFT (0U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_gated_clk_HWEN_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_gated_clk_HWEN_MASK) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_SWEN_AND_lpuart3_lpuart_baud_gated_clk_SWEN_MASK (0x2U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_SWEN_AND_lpuart3_lpuart_baud_gated_clk_SWEN_SHIFT (1U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_SWEN_AND_lpuart3_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_SWEN_AND_lpuart3_lpuart_baud_gated_clk_SWEN_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_SWEN_AND_lpuart3_lpuart_baud_gated_clk_SWEN_MASK) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_2_2_MASK) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_STOP_AND_lpuart3_lpuart_baud_gated_clk_STOP_MASK (0x8U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_STOP_AND_lpuart3_lpuart_baud_gated_clk_STOP_SHIFT (3U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_STOP_AND_lpuart3_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_STOP_AND_lpuart3_lpuart_baud_gated_clk_STOP_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_STOP_AND_lpuart3_lpuart_baud_gated_clk_STOP_MASK) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_4_15_MASK) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_SWEN_AND_lpuart3_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_SWEN_AND_lpuart3_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_SWEN_AND_lpuart3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_SWEN_AND_lpuart3_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_SWEN_AND_lpuart3_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_18_18_MASK) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_STOP_AND_lpuart3_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_STOP_AND_lpuart3_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_STOP_AND_lpuart3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_STOP_AND_lpuart3_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_STOP_AND_lpuart3_ipg_clk_s_STOP_MASK) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_LPUART3_Register_Masks */ /* DMA_LPCG_LPUART3 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_LPUART3 base address */ #define DMA__LPCG_LPUART3_BASE (0x5A490000u) /** Peripheral DMA__LPCG_LPUART3 base pointer */ #define DMA__LPCG_LPUART3 ((DMA_LPCG_LPUART3_Type *)DMA__LPCG_LPUART3_BASE) /** Array initializer of DMA_LPCG_LPUART3 peripheral base addresses */ #define DMA_LPCG_LPUART3_BASE_ADDRS { DMA__LPCG_LPUART3_BASE } /** Array initializer of DMA_LPCG_LPUART3 peripheral base pointers */ #define DMA_LPCG_LPUART3_BASE_PTRS { DMA__LPCG_LPUART3 } /*! * @} */ /* end of group DMA_LPCG_LPUART3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPUART4 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPUART4_Peripheral_Access_Layer DMA_LPCG_LPUART4 Peripheral Access Layer * @{ */ /** DMA_LPCG_LPUART4 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPUART4_0; /**< na, offset: 0x0 */ } DMA_LPCG_LPUART4_Type; /* ---------------------------------------------------------------------------- -- DMA_LPCG_LPUART4 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_LPCG_LPUART4_Register_Masks DMA_LPCG_LPUART4 Register Masks * @{ */ /*! @name LPCG_LPUART4_0 - na */ /*! @{ */ #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_gated_clk_HWEN_MASK (0x1U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_gated_clk_HWEN_SHIFT (0U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_gated_clk_HWEN_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_gated_clk_HWEN_MASK) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_SWEN_AND_lpuart4_lpuart_baud_gated_clk_SWEN_MASK (0x2U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_SWEN_AND_lpuart4_lpuart_baud_gated_clk_SWEN_SHIFT (1U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_SWEN_AND_lpuart4_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_SWEN_AND_lpuart4_lpuart_baud_gated_clk_SWEN_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_SWEN_AND_lpuart4_lpuart_baud_gated_clk_SWEN_MASK) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_2_2_MASK (0x4U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_2_2_SHIFT (2U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_2_2_MASK) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_STOP_AND_lpuart4_lpuart_baud_gated_clk_STOP_MASK (0x8U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_STOP_AND_lpuart4_lpuart_baud_gated_clk_STOP_SHIFT (3U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_STOP_AND_lpuart4_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_STOP_AND_lpuart4_lpuart_baud_gated_clk_STOP_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_STOP_AND_lpuart4_lpuart_baud_gated_clk_STOP_MASK) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_4_15_MASK (0xFFF0U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_4_15_SHIFT (4U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_4_15_MASK) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_s_HWEN_MASK (0x10000U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_s_HWEN_SHIFT (16U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_s_HWEN_MASK) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_SWEN_AND_lpuart4_ipg_clk_s_SWEN_MASK (0x20000U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_SWEN_AND_lpuart4_ipg_clk_s_SWEN_SHIFT (17U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_SWEN_AND_lpuart4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_SWEN_AND_lpuart4_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_SWEN_AND_lpuart4_ipg_clk_s_SWEN_MASK) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_18_18_MASK (0x40000U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_18_18_SHIFT (18U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_18_18_MASK) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_STOP_AND_lpuart4_ipg_clk_s_STOP_MASK (0x80000U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_STOP_AND_lpuart4_ipg_clk_s_STOP_SHIFT (19U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_STOP_AND_lpuart4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_STOP_AND_lpuart4_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_STOP_AND_lpuart4_ipg_clk_s_STOP_MASK) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_20_31_MASK (0xFFF00000U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_20_31_SHIFT (20U) #define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DMA_LPCG_LPUART4_Register_Masks */ /* DMA_LPCG_LPUART4 - Peripheral instance base addresses */ /** Peripheral DMA__LPCG_LPUART4 base address */ #define DMA__LPCG_LPUART4_BASE (0x5A4A0000u) /** Peripheral DMA__LPCG_LPUART4 base pointer */ #define DMA__LPCG_LPUART4 ((DMA_LPCG_LPUART4_Type *)DMA__LPCG_LPUART4_BASE) /** Array initializer of DMA_LPCG_LPUART4 peripheral base addresses */ #define DMA_LPCG_LPUART4_BASE_ADDRS { DMA__LPCG_LPUART4_BASE } /** Array initializer of DMA_LPCG_LPUART4 peripheral base pointers */ #define DMA_LPCG_LPUART4_BASE_PTRS { DMA__LPCG_LPUART4 } /*! * @} */ /* end of group DMA_LPCG_LPUART4_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DRC_LPCG_0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DRC_LPCG_0_Peripheral_Access_Layer DRC_LPCG_0 Peripheral Access Layer * @{ */ /** DRC_LPCG_0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_0_0; /**< na, offset: 0x0 */ } DRC_LPCG_0_Type; /* ---------------------------------------------------------------------------- -- DRC_LPCG_0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DRC_LPCG_0_Register_Masks DRC_LPCG_0 Register Masks * @{ */ /*! @name LPCG_LPCG_0_0 - na */ /*! @{ */ #define DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0_MASK (0x1U) #define DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0_SHIFT (0U) #define DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0_SHIFT)) & DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0_MASK) #define DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN_MASK (0x2U) #define DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN_SHIFT (1U) #define DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN_SHIFT)) & DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN_MASK) #define DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2_MASK (0x4U) #define DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2_SHIFT (2U) #define DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2_SHIFT)) & DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2_MASK) #define DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP_MASK (0x8U) #define DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP_SHIFT (3U) #define DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP_SHIFT)) & DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP_MASK) #define DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31_MASK (0xFFFFFFF0U) #define DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31_SHIFT (4U) #define DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31_SHIFT)) & DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group DRC_LPCG_0_Register_Masks */ /* DRC_LPCG_0 - Peripheral instance base addresses */ /** Peripheral DRC_0__LPCG_SSI_PORT0_CLK base address */ #define DRC_0__LPCG_SSI_PORT0_CLK_BASE (0x5C0C0000u) /** Peripheral DRC_0__LPCG_SSI_PORT0_CLK base pointer */ #define DRC_0__LPCG_SSI_PORT0_CLK ((DRC_LPCG_0_Type *)DRC_0__LPCG_SSI_PORT0_CLK_BASE) /** Peripheral DRC_1__LPCG_SSI_PORT0_CLK base address */ #define DRC_1__LPCG_SSI_PORT0_CLK_BASE (0x5C1C0000u) /** Peripheral DRC_1__LPCG_SSI_PORT0_CLK base pointer */ #define DRC_1__LPCG_SSI_PORT0_CLK ((DRC_LPCG_0_Type *)DRC_1__LPCG_SSI_PORT0_CLK_BASE) /** Array initializer of DRC_LPCG_0 peripheral base addresses */ #define DRC_LPCG_0_BASE_ADDRS { DRC_0__LPCG_SSI_PORT0_CLK_BASE, DRC_1__LPCG_SSI_PORT0_CLK_BASE } /** Array initializer of DRC_LPCG_0 peripheral base pointers */ #define DRC_LPCG_0_BASE_PTRS { DRC_0__LPCG_SSI_PORT0_CLK, DRC_1__LPCG_SSI_PORT0_CLK } /*! * @} */ /* end of group DRC_LPCG_0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DRC_LPCG_1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DRC_LPCG_1_Peripheral_Access_Layer DRC_LPCG_1 Peripheral Access Layer * @{ */ /** DRC_LPCG_1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_1_0; /**< na, offset: 0x0 */ } DRC_LPCG_1_Type; /* ---------------------------------------------------------------------------- -- DRC_LPCG_1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DRC_LPCG_1_Register_Masks DRC_LPCG_1 Register Masks * @{ */ /*! @name LPCG_LPCG_1_0 - na */ /*! @{ */ #define DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0_MASK (0x1U) #define DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0_SHIFT (0U) #define DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0_SHIFT)) & DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0_MASK) #define DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN_MASK (0x2U) #define DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN_SHIFT (1U) #define DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN_SHIFT)) & DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN_MASK) #define DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2_MASK (0x4U) #define DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2_SHIFT (2U) #define DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2_SHIFT)) & DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2_MASK) #define DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP_MASK (0x8U) #define DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP_SHIFT (3U) #define DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP_SHIFT)) & DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP_MASK) #define DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31_MASK (0xFFFFFFF0U) #define DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31_SHIFT (4U) #define DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31_SHIFT)) & DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group DRC_LPCG_1_Register_Masks */ /* DRC_LPCG_1 - Peripheral instance base addresses */ /** Peripheral DRC_0__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK base address */ #define DRC_0__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK_BASE (0x5C0D0000u) /** Peripheral DRC_0__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK base pointer */ #define DRC_0__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK ((DRC_LPCG_1_Type *)DRC_0__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK_BASE) /** Peripheral DRC_1__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK base address */ #define DRC_1__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK_BASE (0x5C1D0000u) /** Peripheral DRC_1__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK base pointer */ #define DRC_1__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK ((DRC_LPCG_1_Type *)DRC_1__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK_BASE) /** Array initializer of DRC_LPCG_1 peripheral base addresses */ #define DRC_LPCG_1_BASE_ADDRS { DRC_0__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK_BASE, DRC_1__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK_BASE } /** Array initializer of DRC_LPCG_1 peripheral base pointers */ #define DRC_LPCG_1_BASE_PTRS { DRC_0__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK, DRC_1__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK } /*! * @} */ /* end of group DRC_LPCG_1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DRC_LPCG_2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DRC_LPCG_2_Peripheral_Access_Layer DRC_LPCG_2 Peripheral Access Layer * @{ */ /** DRC_LPCG_2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_2_0; /**< na, offset: 0x0 */ } DRC_LPCG_2_Type; /* ---------------------------------------------------------------------------- -- DRC_LPCG_2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DRC_LPCG_2_Register_Masks DRC_LPCG_2 Register Masks * @{ */ /*! @name LPCG_LPCG_2_0 - na */ /*! @{ */ #define DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_0_0_MASK (0x1U) #define DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_0_0_SHIFT (0U) #define DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_0_0_SHIFT)) & DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_0_0_MASK) #define DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_SWEN_MASK (0x2U) #define DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_SWEN_SHIFT (1U) #define DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_SWEN_SHIFT)) & DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_SWEN_MASK) #define DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_2_2_MASK (0x4U) #define DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_2_2_SHIFT (2U) #define DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_2_2_SHIFT)) & DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_2_2_MASK) #define DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_STOP_MASK (0x8U) #define DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_STOP_SHIFT (3U) #define DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_STOP(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_STOP_SHIFT)) & DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_STOP_MASK) #define DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_4_31_MASK (0xFFFFFFF0U) #define DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_4_31_SHIFT (4U) #define DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_4_31_SHIFT)) & DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group DRC_LPCG_2_Register_Masks */ /* DRC_LPCG_2 - Peripheral instance base addresses */ /** Peripheral DRC_0__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1 base address */ #define DRC_0__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1_BASE (0x5C0E0000u) /** Peripheral DRC_0__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1 base pointer */ #define DRC_0__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1 ((DRC_LPCG_2_Type *)DRC_0__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1_BASE) /** Peripheral DRC_1__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1 base address */ #define DRC_1__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1_BASE (0x5C1E0000u) /** Peripheral DRC_1__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1 base pointer */ #define DRC_1__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1 ((DRC_LPCG_2_Type *)DRC_1__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1_BASE) /** Array initializer of DRC_LPCG_2 peripheral base addresses */ #define DRC_LPCG_2_BASE_ADDRS { DRC_0__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1_BASE, DRC_1__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1_BASE } /** Array initializer of DRC_LPCG_2 peripheral base pointers */ #define DRC_LPCG_2_BASE_PTRS { DRC_0__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1, DRC_1__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1 } /*! * @} */ /* end of group DRC_LPCG_2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DRC_LPCG_3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DRC_LPCG_3_Peripheral_Access_Layer DRC_LPCG_3 Peripheral Access Layer * @{ */ /** DRC_LPCG_3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_3_0; /**< na, offset: 0x0 */ __IO uint32_t LPCG_LPCG_3_4; /**< na, offset: 0x4 */ } DRC_LPCG_3_Type; /* ---------------------------------------------------------------------------- -- DRC_LPCG_3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DRC_LPCG_3_Register_Masks DRC_LPCG_3 Register Masks * @{ */ /*! @name LPCG_LPCG_3_0 - na */ /*! @{ */ #define DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0_MASK (0x1U) #define DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0_SHIFT (0U) #define DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0_MASK) #define DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN_MASK (0x2U) #define DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN_SHIFT (1U) #define DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN_MASK) #define DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2_MASK (0x4U) #define DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2_SHIFT (2U) #define DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2_MASK) #define DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP_MASK (0x8U) #define DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP_SHIFT (3U) #define DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP_MASK) #define DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31_MASK (0xFFFFFFF0U) #define DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31_SHIFT (4U) #define DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_LPCG_3_4 - na */ /*! @{ */ #define DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0_MASK (0x1U) #define DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0_SHIFT (0U) #define DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0_MASK) #define DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN_MASK (0x2U) #define DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN_SHIFT (1U) #define DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN_MASK) #define DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2_MASK (0x4U) #define DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2_SHIFT (2U) #define DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2_MASK) #define DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP_MASK (0x8U) #define DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP_SHIFT (3U) #define DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP_MASK) #define DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31_MASK (0xFFFFFFF0U) #define DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31_SHIFT (4U) #define DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group DRC_LPCG_3_Register_Masks */ /* DRC_LPCG_3 - Peripheral instance base addresses */ /** Peripheral DRC_0__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 base address */ #define DRC_0__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_BASE (0x5C0F0000u) /** Peripheral DRC_0__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 base pointer */ #define DRC_0__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 ((DRC_LPCG_3_Type *)DRC_0__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_BASE) /** Peripheral DRC_1__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 base address */ #define DRC_1__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_BASE (0x5C1F0000u) /** Peripheral DRC_1__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 base pointer */ #define DRC_1__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 ((DRC_LPCG_3_Type *)DRC_1__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_BASE) /** Array initializer of DRC_LPCG_3 peripheral base addresses */ #define DRC_LPCG_3_BASE_ADDRS { DRC_0__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_BASE, DRC_1__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_BASE } /** Array initializer of DRC_LPCG_3 peripheral base pointers */ #define DRC_LPCG_3_BASE_PTRS { DRC_0__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0, DRC_1__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 } /*! * @} */ /* end of group DRC_LPCG_3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DTCP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DTCP_Peripheral_Access_Layer DTCP Peripheral Access Layer * @{ */ /** DTCP - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[1024]; __IO uint16_t DTCP_INT_MASK; /**< Initial mask, offset: 0x400 */ __IO uint16_t DTCP_INT_FLAG; /**< Initial Flag, offset: 0x402 */ __IO uint16_t DTCP_STATE; /**< Initial State, offset: 0x404 */ uint8_t RESERVED_1[2]; __IO uint16_t DTCP_REQ_MASK; /**< Request Mask, offset: 0x408 */ } DTCP_Type; /* ---------------------------------------------------------------------------- -- DTCP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DTCP_Register_Masks DTCP Register Masks * @{ */ /*! @name DTCP_INT_MASK - Initial mask */ /*! @{ */ #define DTCP_DTCP_INT_MASK_CHN0_INT_MASK_MASK (0x1U) #define DTCP_DTCP_INT_MASK_CHN0_INT_MASK_SHIFT (0U) /*! CHN0_INT_MASK - Channel 0 Interrupt Mask * 0b0..DTCP generates interrupt when channel 0 #8 or #9 service finish. * 0b1..DTCP does not generate service interrupt for channel 0. */ #define DTCP_DTCP_INT_MASK_CHN0_INT_MASK(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_MASK_CHN0_INT_MASK_SHIFT)) & DTCP_DTCP_INT_MASK_CHN0_INT_MASK_MASK) #define DTCP_DTCP_INT_MASK_CHN1_INT_MASK_MASK (0x2U) #define DTCP_DTCP_INT_MASK_CHN1_INT_MASK_SHIFT (1U) /*! CHN1_INT_MASK - Channel 1 Interrupt Mask * 0b0..DTCP generates interrupt when channel 1 #8 or #9 service finish. * 0b1..DTCP does not generate service interrupt for channel 1. */ #define DTCP_DTCP_INT_MASK_CHN1_INT_MASK(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_MASK_CHN1_INT_MASK_SHIFT)) & DTCP_DTCP_INT_MASK_CHN1_INT_MASK_MASK) #define DTCP_DTCP_INT_MASK_CHN2_INT_MASK_MASK (0x4U) #define DTCP_DTCP_INT_MASK_CHN2_INT_MASK_SHIFT (2U) /*! CHN2_INT_MASK - Channel 2 Interrupt Mask * 0b0..DTCP generates interrupt when channel 2 #8 or #9 service finish. * 0b1..DTCP does not generate service interrupt for channel 2. */ #define DTCP_DTCP_INT_MASK_CHN2_INT_MASK(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_MASK_CHN2_INT_MASK_SHIFT)) & DTCP_DTCP_INT_MASK_CHN2_INT_MASK_MASK) #define DTCP_DTCP_INT_MASK_CHN3_INT_MASK_MASK (0x8U) #define DTCP_DTCP_INT_MASK_CHN3_INT_MASK_SHIFT (3U) /*! CHN3_INT_MASK - Channel 3 Interrupt Mask * 0b0..DTCP generates interrupt when channel 3 #8 or #9 service finish. * 0b1..DTCP does not generate service interrupt for channel 3. */ #define DTCP_DTCP_INT_MASK_CHN3_INT_MASK(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_MASK_CHN3_INT_MASK_SHIFT)) & DTCP_DTCP_INT_MASK_CHN3_INT_MASK_MASK) #define DTCP_DTCP_INT_MASK_CHN4_INT_MASK_MASK (0x10U) #define DTCP_DTCP_INT_MASK_CHN4_INT_MASK_SHIFT (4U) /*! CHN4_INT_MASK - Channel 4 Interrupt Mask * 0b0..DTCP generates interrupt when channel 4 #8 or #9 service finish. * 0b1..DTCP does not generate service interrupt for channel 4. */ #define DTCP_DTCP_INT_MASK_CHN4_INT_MASK(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_MASK_CHN4_INT_MASK_SHIFT)) & DTCP_DTCP_INT_MASK_CHN4_INT_MASK_MASK) #define DTCP_DTCP_INT_MASK_CHN5_INT_MASK_MASK (0x20U) #define DTCP_DTCP_INT_MASK_CHN5_INT_MASK_SHIFT (5U) /*! CHN5_INT_MASK - Channel 5 Interrupt Mask * 0b0..DTCP generates interrupt when channel 5 #8 or #9 service finish. * 0b1..DTCP does not generate service interrupt for channel 5. */ #define DTCP_DTCP_INT_MASK_CHN5_INT_MASK(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_MASK_CHN5_INT_MASK_SHIFT)) & DTCP_DTCP_INT_MASK_CHN5_INT_MASK_MASK) #define DTCP_DTCP_INT_MASK_CHN6_INT_MASK_MASK (0x40U) #define DTCP_DTCP_INT_MASK_CHN6_INT_MASK_SHIFT (6U) /*! CHN6_INT_MASK - Channel 6 Interrupt Mask * 0b0..DTCP generates interrupt when channel 6 #8 or #9 service finish. * 0b1..DTCP does not generate service interrupt for channel 6. */ #define DTCP_DTCP_INT_MASK_CHN6_INT_MASK(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_MASK_CHN6_INT_MASK_SHIFT)) & DTCP_DTCP_INT_MASK_CHN6_INT_MASK_MASK) #define DTCP_DTCP_INT_MASK_CHN7_INT_MASK_MASK (0x80U) #define DTCP_DTCP_INT_MASK_CHN7_INT_MASK_SHIFT (7U) /*! CHN7_INT_MASK - Channel 6 Interrupt Mask * 0b0..DTCP generates interrupt when channel 7 #8 or #9 service finish. * 0b1..DTCP does not generate service interrupt for channel 7. */ #define DTCP_DTCP_INT_MASK_CHN7_INT_MASK(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_MASK_CHN7_INT_MASK_SHIFT)) & DTCP_DTCP_INT_MASK_CHN7_INT_MASK_MASK) #define DTCP_DTCP_INT_MASK_CHN8_INT_MASK_MASK (0x100U) #define DTCP_DTCP_INT_MASK_CHN8_INT_MASK_SHIFT (8U) /*! CHN8_INT_MASK - Channel 8 Interrupt Mask * 0b0..DTCP generates interrupt when AKE service finish. * 0b1..DTCP does not generate service interrupt for SKE service. */ #define DTCP_DTCP_INT_MASK_CHN8_INT_MASK(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_MASK_CHN8_INT_MASK_SHIFT)) & DTCP_DTCP_INT_MASK_CHN8_INT_MASK_MASK) /*! @} */ /*! @name DTCP_INT_FLAG - Initial Flag */ /*! @{ */ #define DTCP_DTCP_INT_FLAG_CHN0_INT_FLAG_MASK (0x1U) #define DTCP_DTCP_INT_FLAG_CHN0_INT_FLAG_SHIFT (0U) /*! CHN0_INT_FLAG - Channel 0 Interrupt Flag * 0b1..DTCP channel 0 #8 or #9 service finish. */ #define DTCP_DTCP_INT_FLAG_CHN0_INT_FLAG(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_FLAG_CHN0_INT_FLAG_SHIFT)) & DTCP_DTCP_INT_FLAG_CHN0_INT_FLAG_MASK) #define DTCP_DTCP_INT_FLAG_CHN1_INT_FLAG_MASK (0x2U) #define DTCP_DTCP_INT_FLAG_CHN1_INT_FLAG_SHIFT (1U) /*! CHN1_INT_FLAG - Channel 1 Interrupt Flag * 0b1..DTCP channel 1 #8 or #9 service finish. */ #define DTCP_DTCP_INT_FLAG_CHN1_INT_FLAG(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_FLAG_CHN1_INT_FLAG_SHIFT)) & DTCP_DTCP_INT_FLAG_CHN1_INT_FLAG_MASK) #define DTCP_DTCP_INT_FLAG_CHN2_INT_FLAG_MASK (0x4U) #define DTCP_DTCP_INT_FLAG_CHN2_INT_FLAG_SHIFT (2U) /*! CHN2_INT_FLAG - Channel 2 Interrupt FLAG * 0b1..DTCP channel 2 #8 or #9 service finish. */ #define DTCP_DTCP_INT_FLAG_CHN2_INT_FLAG(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_FLAG_CHN2_INT_FLAG_SHIFT)) & DTCP_DTCP_INT_FLAG_CHN2_INT_FLAG_MASK) #define DTCP_DTCP_INT_FLAG_CHN3_INT_FLAG_MASK (0x8U) #define DTCP_DTCP_INT_FLAG_CHN3_INT_FLAG_SHIFT (3U) /*! CHN3_INT_FLAG - Channel 3 Interrupt Flag * 0b1..DTCP channel 3 #8 or #9 service finish. */ #define DTCP_DTCP_INT_FLAG_CHN3_INT_FLAG(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_FLAG_CHN3_INT_FLAG_SHIFT)) & DTCP_DTCP_INT_FLAG_CHN3_INT_FLAG_MASK) #define DTCP_DTCP_INT_FLAG_CHN4_INT_FLAG_MASK (0x10U) #define DTCP_DTCP_INT_FLAG_CHN4_INT_FLAG_SHIFT (4U) /*! CHN4_INT_FLAG - Channel 4 Interrupt Flag * 0b1..DTCP channel 4 #8 or #9 service finish. */ #define DTCP_DTCP_INT_FLAG_CHN4_INT_FLAG(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_FLAG_CHN4_INT_FLAG_SHIFT)) & DTCP_DTCP_INT_FLAG_CHN4_INT_FLAG_MASK) #define DTCP_DTCP_INT_FLAG_CHN5_INT_FLAG_MASK (0x20U) #define DTCP_DTCP_INT_FLAG_CHN5_INT_FLAG_SHIFT (5U) /*! CHN5_INT_FLAG - Channel 5 Interrupt Flag * 0b1..DTCP channel 5 #8 or #9 service finish. */ #define DTCP_DTCP_INT_FLAG_CHN5_INT_FLAG(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_FLAG_CHN5_INT_FLAG_SHIFT)) & DTCP_DTCP_INT_FLAG_CHN5_INT_FLAG_MASK) #define DTCP_DTCP_INT_FLAG_CHN6_INT_FLAG_MASK (0x40U) #define DTCP_DTCP_INT_FLAG_CHN6_INT_FLAG_SHIFT (6U) /*! CHN6_INT_FLAG - Channel 6 Interrupt Flag * 0b1..DTCP channel 6 #8 or #9 service finish. */ #define DTCP_DTCP_INT_FLAG_CHN6_INT_FLAG(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_FLAG_CHN6_INT_FLAG_SHIFT)) & DTCP_DTCP_INT_FLAG_CHN6_INT_FLAG_MASK) #define DTCP_DTCP_INT_FLAG_CHN7_INT_FLAG_MASK (0x80U) #define DTCP_DTCP_INT_FLAG_CHN7_INT_FLAG_SHIFT (7U) /*! CHN7_INT_FLAG - Channel 6 Interrupt Flag * 0b1..DTCP channel 7 #8 or #9 service finish. */ #define DTCP_DTCP_INT_FLAG_CHN7_INT_FLAG(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_FLAG_CHN7_INT_FLAG_SHIFT)) & DTCP_DTCP_INT_FLAG_CHN7_INT_FLAG_MASK) #define DTCP_DTCP_INT_FLAG_CHN8_INT_FLAG_MASK (0x100U) #define DTCP_DTCP_INT_FLAG_CHN8_INT_FLAG_SHIFT (8U) /*! CHN8_INT_FLAG - Channel 8 Interrupt Flag * 0b1..AKE service finish. */ #define DTCP_DTCP_INT_FLAG_CHN8_INT_FLAG(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_FLAG_CHN8_INT_FLAG_SHIFT)) & DTCP_DTCP_INT_FLAG_CHN8_INT_FLAG_MASK) /*! @} */ /*! @name DTCP_STATE - Initial State */ /*! @{ */ #define DTCP_DTCP_STATE_BUFF_MT_MASK (0xFFU) #define DTCP_DTCP_STATE_BUFF_MT_SHIFT (0U) #define DTCP_DTCP_STATE_BUFF_MT(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_STATE_BUFF_MT_SHIFT)) & DTCP_DTCP_STATE_BUFF_MT_MASK) #define DTCP_DTCP_STATE_CUR_CHN_MASK (0x700U) #define DTCP_DTCP_STATE_CUR_CHN_SHIFT (8U) #define DTCP_DTCP_STATE_CUR_CHN(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_STATE_CUR_CHN_SHIFT)) & DTCP_DTCP_STATE_CUR_CHN_MASK) /*! @} */ /*! @name DTCP_REQ_MASK - Request Mask */ /*! @{ */ #define DTCP_DTCP_REQ_MASK_CHN0_DMA_REQ_MASK_MASK (0x1U) #define DTCP_DTCP_REQ_MASK_CHN0_DMA_REQ_MASK_SHIFT (0U) /*! CHN0_DMA_REQ_MASK - Channel 0 DMA Request Mask * 0b0..DTCP generates DMA request when channel 0 #8 or #9 service finish. * 0b1..DTCP does not generate DMA request interrupt for channel 0. */ #define DTCP_DTCP_REQ_MASK_CHN0_DMA_REQ_MASK(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_REQ_MASK_CHN0_DMA_REQ_MASK_SHIFT)) & DTCP_DTCP_REQ_MASK_CHN0_DMA_REQ_MASK_MASK) #define DTCP_DTCP_REQ_MASK_CHN1_DMA_REQ_MASK_MASK (0x2U) #define DTCP_DTCP_REQ_MASK_CHN1_DMA_REQ_MASK_SHIFT (1U) /*! CHN1_DMA_REQ_MASK - Channel 1 DMA Request Mask * 0b0..DTCP generates DMA request when channel 1 #8 or #9 service finish. * 0b1..DTCP does not generate DMA request for channel 1. */ #define DTCP_DTCP_REQ_MASK_CHN1_DMA_REQ_MASK(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_REQ_MASK_CHN1_DMA_REQ_MASK_SHIFT)) & DTCP_DTCP_REQ_MASK_CHN1_DMA_REQ_MASK_MASK) #define DTCP_DTCP_REQ_MASK_CHN2_DMA_REQ_MASK_MASK (0x4U) #define DTCP_DTCP_REQ_MASK_CHN2_DMA_REQ_MASK_SHIFT (2U) /*! CHN2_DMA_REQ_MASK - Channel 2 DMA Request Mask * 0b0..DTCP generates DMA request when channel 2 #8 or #9 service finish. * 0b1..DTCP does not generate DMA request for channel 2. */ #define DTCP_DTCP_REQ_MASK_CHN2_DMA_REQ_MASK(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_REQ_MASK_CHN2_DMA_REQ_MASK_SHIFT)) & DTCP_DTCP_REQ_MASK_CHN2_DMA_REQ_MASK_MASK) #define DTCP_DTCP_REQ_MASK_CHN3_DMA_REQ_MASK_MASK (0x8U) #define DTCP_DTCP_REQ_MASK_CHN3_DMA_REQ_MASK_SHIFT (3U) /*! CHN3_DMA_REQ_MASK - Channel 3 DMA Request Mask * 0b0..DTCP generates DMA request when channel 3 #8 or #9 service finish. * 0b1..DTCP does not generate DMA request for channel 3. */ #define DTCP_DTCP_REQ_MASK_CHN3_DMA_REQ_MASK(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_REQ_MASK_CHN3_DMA_REQ_MASK_SHIFT)) & DTCP_DTCP_REQ_MASK_CHN3_DMA_REQ_MASK_MASK) #define DTCP_DTCP_REQ_MASK_CHN4_DMA_REQ_MASK_MASK (0x10U) #define DTCP_DTCP_REQ_MASK_CHN4_DMA_REQ_MASK_SHIFT (4U) /*! CHN4_DMA_REQ_MASK - Channel 4 DMA Request Mask * 0b0..DTCP generates DMA request when channel 4 #8 or #9 service finish. * 0b1..DTCP does not generate DMA request for channel 4. */ #define DTCP_DTCP_REQ_MASK_CHN4_DMA_REQ_MASK(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_REQ_MASK_CHN4_DMA_REQ_MASK_SHIFT)) & DTCP_DTCP_REQ_MASK_CHN4_DMA_REQ_MASK_MASK) #define DTCP_DTCP_REQ_MASK_CHN5_DMA_REQ_MASK_MASK (0x20U) #define DTCP_DTCP_REQ_MASK_CHN5_DMA_REQ_MASK_SHIFT (5U) /*! CHN5_DMA_REQ_MASK - Channel 5 DMA Request Mask * 0b0..DTCP generates DMA request when channel 5 #8 or #9 service finish. * 0b1..DTCP does not generate DMA request for channel 5. */ #define DTCP_DTCP_REQ_MASK_CHN5_DMA_REQ_MASK(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_REQ_MASK_CHN5_DMA_REQ_MASK_SHIFT)) & DTCP_DTCP_REQ_MASK_CHN5_DMA_REQ_MASK_MASK) #define DTCP_DTCP_REQ_MASK_CHN6_DMA_REQ_MASK_MASK (0x40U) #define DTCP_DTCP_REQ_MASK_CHN6_DMA_REQ_MASK_SHIFT (6U) /*! CHN6_DMA_REQ_MASK - Channel 6 DMA Request Mask * 0b0..DTCP generates DMA request when channel 6 #8 or #9 service finish. * 0b1..DTCP does not generate DMA request for channel 6. */ #define DTCP_DTCP_REQ_MASK_CHN6_DMA_REQ_MASK(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_REQ_MASK_CHN6_DMA_REQ_MASK_SHIFT)) & DTCP_DTCP_REQ_MASK_CHN6_DMA_REQ_MASK_MASK) #define DTCP_DTCP_REQ_MASK_CHN7_DMA_REQ_MASK_MASK (0x80U) #define DTCP_DTCP_REQ_MASK_CHN7_DMA_REQ_MASK_SHIFT (7U) /*! CHN7_DMA_REQ_MASK - Channel 6 DMA Request Mask * 0b0..DTCP generates DMA request when channel 7 #8 or #9 service finish. * 0b1..DTCP does not generate DMA request for channel 7. */ #define DTCP_DTCP_REQ_MASK_CHN7_DMA_REQ_MASK(x) (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_REQ_MASK_CHN7_DMA_REQ_MASK_SHIFT)) & DTCP_DTCP_REQ_MASK_CHN7_DMA_REQ_MASK_MASK) /*! @} */ /*! * @} */ /* end of group DTCP_Register_Masks */ /* DTCP - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__DTCP base address */ #define CONNECTIVITY__DTCP_BASE (0x5B800000u) /** Peripheral CONNECTIVITY__DTCP base pointer */ #define CONNECTIVITY__DTCP ((DTCP_Type *)CONNECTIVITY__DTCP_BASE) /** Array initializer of DTCP peripheral base addresses */ #define DTCP_BASE_ADDRS { CONNECTIVITY__DTCP_BASE } /** Array initializer of DTCP peripheral base pointers */ #define DTCP_BASE_PTRS { CONNECTIVITY__DTCP } /** Interrupt vectors for the DTCP peripheral type */ #define DTCP_IRQS { CONNECTIVITY_DTCP_INT_IRQn } /*! * @} */ /* end of group DTCP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- EMVSIM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer * @{ */ /** EMVSIM - Register Layout Typedef */ typedef struct { __I uint32_t VER_ID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __IO uint32_t CLKCFG; /**< Clock Configuration Register, offset: 0x8 */ __IO uint32_t DIVISOR; /**< Baud Rate Divisor Register, offset: 0xC */ __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */ __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ __IO uint32_t TX_THD; /**< Transmitter Threshold Register, offset: 0x1C */ __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ __IO uint32_t TX_STATUS; /**< Transmitter Status Register, offset: 0x24 */ __IO uint32_t PCSR; /**< Port Control and Status Register, offset: 0x28 */ __I uint32_t RX_BUF; /**< Receive Data Read Buffer, offset: 0x2C */ __O uint32_t TX_BUF; /**< Transmit Data Buffer, offset: 0x30 */ __IO uint32_t TX_GETU; /**< Transmitter Guard ETU Value Register, offset: 0x34 */ __IO uint32_t CWT_VAL; /**< Character Wait Time Value Register, offset: 0x38 */ __IO uint32_t BWT_VAL; /**< Block Wait Time Value Register, offset: 0x3C */ __IO uint32_t BGT_VAL; /**< Block Guard Time Value Register, offset: 0x40 */ __IO uint32_t GPCNT0_VAL; /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */ __IO uint32_t GPCNT1_VAL; /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */ } EMVSIM_Type; /* ---------------------------------------------------------------------------- -- EMVSIM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks * @{ */ /*! @name VER_ID - Version ID Register */ /*! @{ */ #define EMVSIM_VER_ID_VER_MASK (0xFFFFFFFFU) #define EMVSIM_VER_ID_VER_SHIFT (0U) #define EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK (0xFFU) #define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT (0U) #define EMVSIM_PARAM_RX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK) #define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK (0xFF00U) #define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT (8U) #define EMVSIM_PARAM_TX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK) /*! @} */ /*! @name CLKCFG - Clock Configuration Register */ /*! @{ */ #define EMVSIM_CLKCFG_CLK_PRSC_MASK (0xFFU) #define EMVSIM_CLKCFG_CLK_PRSC_SHIFT (0U) /*! CLK_PRSC - Clock Prescaler Value * 0b00000010..Divide by 2 */ #define EMVSIM_CLKCFG_CLK_PRSC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK) #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK (0x300U) #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT (8U) /*! GPCNT1_CLK_SEL - General Purpose Counter 1 Clock Select * 0b00..Disabled / Reset (default) * 0b01..Card Clock * 0b10..Receive Clock * 0b11..ETU Clock (transmit clock) */ #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK) #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK (0xC00U) #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT (10U) /*! GPCNT0_CLK_SEL - General Purpose Counter 0 Clock Select * 0b00..Disabled / Reset (default) * 0b01..Card Clock * 0b10..Receive Clock * 0b11..ETU Clock (transmit clock) */ #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK) /*! @} */ /*! @name DIVISOR - Baud Rate Divisor Register */ /*! @{ */ #define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK (0x1FFU) #define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT (0U) /*! DIVISOR_VALUE - Divisor (F/D) Value * 0b000000000-0b000000100..Invalid. As per ISO 7816 specification, minimum value of F/D is 5 * 0b101110100..Divisor value for F = 372 and D = 1 (default) */ #define EMVSIM_DIVISOR_DIVISOR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK) /*! @} */ /*! @name CTRL - Control Register */ /*! @{ */ #define EMVSIM_CTRL_IC_MASK (0x1U) #define EMVSIM_CTRL_IC_SHIFT (0U) /*! IC - Inverse Convention * 0b0..Direction convention transfers enabled (default) * 0b1..Inverse convention transfers enabled */ #define EMVSIM_CTRL_IC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK) #define EMVSIM_CTRL_ICM_MASK (0x2U) #define EMVSIM_CTRL_ICM_SHIFT (1U) /*! ICM - Initial Character Mode * 0b0..Initial Character Mode disabled * 0b1..Initial Character Mode enabled (default) */ #define EMVSIM_CTRL_ICM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK) #define EMVSIM_CTRL_ANACK_MASK (0x4U) #define EMVSIM_CTRL_ANACK_SHIFT (2U) /*! ANACK - Auto NACK Enable * 0b0..NACK generation on errors disabled * 0b1..NACK generation on errors enabled (default) */ #define EMVSIM_CTRL_ANACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK) #define EMVSIM_CTRL_ONACK_MASK (0x8U) #define EMVSIM_CTRL_ONACK_SHIFT (3U) /*! ONACK - Overrun NACK Enable * 0b0..NACK generation on overrun is disabled (default) * 0b1..NACK generation on overrun is enabled */ #define EMVSIM_CTRL_ONACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK) #define EMVSIM_CTRL_FLSH_RX_MASK (0x100U) #define EMVSIM_CTRL_FLSH_RX_SHIFT (8U) /*! FLSH_RX - Flush Receiver Bit * 0b0..EMV SIM Receiver normal operation (default) * 0b1..EMV SIM Receiver held in Reset */ #define EMVSIM_CTRL_FLSH_RX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK) #define EMVSIM_CTRL_FLSH_TX_MASK (0x200U) #define EMVSIM_CTRL_FLSH_TX_SHIFT (9U) /*! FLSH_TX - Flush Transmitter Bit * 0b0..EMV SIM Transmitter normal operation (default) * 0b1..EMV SIM Transmitter held in Reset */ #define EMVSIM_CTRL_FLSH_TX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK) #define EMVSIM_CTRL_SW_RST_MASK (0x400U) #define EMVSIM_CTRL_SW_RST_SHIFT (10U) /*! SW_RST - Software Reset Bit * 0b0..EMV SIM Normal operation (default) * 0b1..EMV SIM held in Reset */ #define EMVSIM_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK) #define EMVSIM_CTRL_KILL_CLOCKS_MASK (0x800U) #define EMVSIM_CTRL_KILL_CLOCKS_SHIFT (11U) /*! KILL_CLOCKS - Kill all internal clocks * 0b0..EMV SIM input clock enabled (default) * 0b1..EMV SIM input clock is disabled */ #define EMVSIM_CTRL_KILL_CLOCKS(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK) #define EMVSIM_CTRL_DOZE_EN_MASK (0x1000U) #define EMVSIM_CTRL_DOZE_EN_SHIFT (12U) /*! DOZE_EN - Doze Enable * 0b0..DOZE instruction will gate all internal EMV SIM clocks as well as the Smart Card clock when the transmit FIFO is empty (default) * 0b1..DOZE instruction has no effect on EMV SIM module */ #define EMVSIM_CTRL_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK) #define EMVSIM_CTRL_STOP_EN_MASK (0x2000U) #define EMVSIM_CTRL_STOP_EN_SHIFT (13U) /*! STOP_EN - STOP Enable * 0b0..STOP instruction shuts down all EMV SIM clocks (default) * 0b1..STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card) */ #define EMVSIM_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK) #define EMVSIM_CTRL_RCV_EN_MASK (0x10000U) #define EMVSIM_CTRL_RCV_EN_SHIFT (16U) /*! RCV_EN - Receiver Enable * 0b0..EMV SIM Receiver disabled (default) * 0b1..EMV SIM Receiver enabled */ #define EMVSIM_CTRL_RCV_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK) #define EMVSIM_CTRL_XMT_EN_MASK (0x20000U) #define EMVSIM_CTRL_XMT_EN_SHIFT (17U) /*! XMT_EN - Transmitter Enable * 0b0..EMV SIM Transmitter disabled (default) * 0b1..EMV SIM Transmitter enabled */ #define EMVSIM_CTRL_XMT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK) #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) #define EMVSIM_CTRL_RCVR_11_SHIFT (18U) /*! RCVR_11 - Receiver 11 ETU Mode Enable * 0b0..Receiver configured for 12 ETU operation mode (default) * 0b1..Receiver configured for 11 ETU operation mode */ #define EMVSIM_CTRL_RCVR_11(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK) #define EMVSIM_CTRL_RX_DMA_EN_MASK (0x80000U) #define EMVSIM_CTRL_RX_DMA_EN_SHIFT (19U) /*! RX_DMA_EN - Receive DMA Enable * 0b0..No DMA Read Request asserted for Receiver (default) * 0b1..DMA Read Request asserted for Receiver */ #define EMVSIM_CTRL_RX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK) #define EMVSIM_CTRL_TX_DMA_EN_MASK (0x100000U) #define EMVSIM_CTRL_TX_DMA_EN_SHIFT (20U) /*! TX_DMA_EN - Transmit DMA Enable * 0b0..No DMA Write Request asserted for Transmitter (default) * 0b1..DMA Write Request asserted for Transmitter */ #define EMVSIM_CTRL_TX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK) #define EMVSIM_CTRL_INV_CRC_VAL_MASK (0x1000000U) #define EMVSIM_CTRL_INV_CRC_VAL_SHIFT (24U) /*! INV_CRC_VAL - Invert bits in the CRC Output Value * 0b0..Bits in CRC Output value will not be inverted. * 0b1..Bits in CRC Output value will be inverted. (default) */ #define EMVSIM_CTRL_INV_CRC_VAL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK) #define EMVSIM_CTRL_CRC_OUT_FLIP_MASK (0x2000000U) #define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT (25U) /*! CRC_OUT_FLIP - CRC Output Value Bit Reversal or Flip * 0b0..Bits within the CRC output bytes will not be reversed i.e. 15:0 will remain 15:0 (default) * 0b1..Bits within the CRC output bytes will be reversed i.e. 15:0 will become {8:15,0:7} */ #define EMVSIM_CTRL_CRC_OUT_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK) #define EMVSIM_CTRL_CRC_IN_FLIP_MASK (0x4000000U) #define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT (26U) /*! CRC_IN_FLIP - CRC Input Byte's Bit Reversal or Flip Control * 0b0..Bits in the input byte will not be reversed (i.e. 7:0 will remain 7:0) before the CRC calculation (default) * 0b1..Bits in the input byte will be reversed (i.e. 7:0 will become 0:7) before CRC calculation */ #define EMVSIM_CTRL_CRC_IN_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK) #define EMVSIM_CTRL_CWT_EN_MASK (0x8000000U) #define EMVSIM_CTRL_CWT_EN_SHIFT (27U) /*! CWT_EN - Character Wait Time Counter Enable * 0b0..Character Wait time Counter is disabled (default) * 0b1..Character Wait time counter is enabled */ #define EMVSIM_CTRL_CWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK) #define EMVSIM_CTRL_LRC_EN_MASK (0x10000000U) #define EMVSIM_CTRL_LRC_EN_SHIFT (28U) /*! LRC_EN - LRC Enable * 0b0..8-bit Linear Redundancy Checking disabled (default) * 0b1..8-bit Linear Redundancy Checking enabled */ #define EMVSIM_CTRL_LRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK) #define EMVSIM_CTRL_CRC_EN_MASK (0x20000000U) #define EMVSIM_CTRL_CRC_EN_SHIFT (29U) /*! CRC_EN - CRC Enable * 0b0..16-bit Cyclic Redundancy Checking disabled (default) * 0b1..16-bit Cyclic Redundancy Checking enabled */ #define EMVSIM_CTRL_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK) #define EMVSIM_CTRL_XMT_CRC_LRC_MASK (0x40000000U) #define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT (30U) /*! XMT_CRC_LRC - Transmit CRC or LRC Enable * 0b0..No CRC or LRC value is transmitted (default) * 0b1..Transmit LRC or CRC info when FIFO empties (whichever is enabled) */ #define EMVSIM_CTRL_XMT_CRC_LRC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK) #define EMVSIM_CTRL_BWT_EN_MASK (0x80000000U) #define EMVSIM_CTRL_BWT_EN_SHIFT (31U) /*! BWT_EN - Block Wait Time Counter Enable * 0b0..Disable BWT, BGT Counters (default) * 0b1..Enable BWT, BGT Counters */ #define EMVSIM_CTRL_BWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK) /*! @} */ /*! @name INT_MASK - Interrupt Mask Register */ /*! @{ */ #define EMVSIM_INT_MASK_RDT_IM_MASK (0x1U) #define EMVSIM_INT_MASK_RDT_IM_SHIFT (0U) /*! RDT_IM - Receive Data Threshold Interrupt Mask * 0b0..RDTF interrupt enabled * 0b1..RDTF interrupt masked (default) */ #define EMVSIM_INT_MASK_RDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK) #define EMVSIM_INT_MASK_TC_IM_MASK (0x2U) #define EMVSIM_INT_MASK_TC_IM_SHIFT (1U) /*! TC_IM - Transmit Complete Interrupt Mask * 0b0..TCF interrupt enabled * 0b1..TCF interrupt masked (default) */ #define EMVSIM_INT_MASK_TC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK) #define EMVSIM_INT_MASK_RFO_IM_MASK (0x4U) #define EMVSIM_INT_MASK_RFO_IM_SHIFT (2U) /*! RFO_IM - Receive FIFO Overflow Interrupt Mask * 0b0..RFO interrupt enabled * 0b1..RFO interrupt masked (default) */ #define EMVSIM_INT_MASK_RFO_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK) #define EMVSIM_INT_MASK_ETC_IM_MASK (0x8U) #define EMVSIM_INT_MASK_ETC_IM_SHIFT (3U) /*! ETC_IM - Early Transmit Complete Interrupt Mask * 0b0..ETC interrupt enabled * 0b1..ETC interrupt masked (default) */ #define EMVSIM_INT_MASK_ETC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK) #define EMVSIM_INT_MASK_TFE_IM_MASK (0x10U) #define EMVSIM_INT_MASK_TFE_IM_SHIFT (4U) /*! TFE_IM - Transmit FIFO Empty Interrupt Mask * 0b0..TFE interrupt enabled * 0b1..TFE interrupt masked (default) */ #define EMVSIM_INT_MASK_TFE_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK) #define EMVSIM_INT_MASK_TNACK_IM_MASK (0x20U) #define EMVSIM_INT_MASK_TNACK_IM_SHIFT (5U) /*! TNACK_IM - Transmit NACK Threshold Interrupt Mask * 0b0..TNTE interrupt enabled * 0b1..TNTE interrupt masked (default) */ #define EMVSIM_INT_MASK_TNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK) #define EMVSIM_INT_MASK_TFF_IM_MASK (0x40U) #define EMVSIM_INT_MASK_TFF_IM_SHIFT (6U) /*! TFF_IM - Transmit FIFO Full Interrupt Mask * 0b0..TFF interrupt enabled * 0b1..TFF interrupt masked (default) */ #define EMVSIM_INT_MASK_TFF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK) #define EMVSIM_INT_MASK_TDT_IM_MASK (0x80U) #define EMVSIM_INT_MASK_TDT_IM_SHIFT (7U) /*! TDT_IM - Transmit Data Threshold Interrupt Mask * 0b0..TDTF interrupt enabled * 0b1..TDTF interrupt masked (default) */ #define EMVSIM_INT_MASK_TDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK) #define EMVSIM_INT_MASK_GPCNT0_IM_MASK (0x100U) #define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT (8U) /*! GPCNT0_IM - General Purpose Timer 0 Timeout Interrupt Mask * 0b0..GPCNT0_TO interrupt enabled * 0b1..GPCNT0_TO interrupt masked (default) */ #define EMVSIM_INT_MASK_GPCNT0_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK) #define EMVSIM_INT_MASK_CWT_ERR_IM_MASK (0x200U) #define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT (9U) /*! CWT_ERR_IM - Character Wait Time Error Interrupt Mask * 0b0..CWT_ERR interrupt enabled * 0b1..CWT_ERR interrupt masked (default) */ #define EMVSIM_INT_MASK_CWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK) #define EMVSIM_INT_MASK_RNACK_IM_MASK (0x400U) #define EMVSIM_INT_MASK_RNACK_IM_SHIFT (10U) /*! RNACK_IM - Receiver NACK Threshold Interrupt Mask * 0b0..RTE interrupt enabled * 0b1..RTE interrupt masked (default) */ #define EMVSIM_INT_MASK_RNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK) #define EMVSIM_INT_MASK_BWT_ERR_IM_MASK (0x800U) #define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT (11U) /*! BWT_ERR_IM - Block Wait Time Error Interrupt Mask * 0b0..BWT_ERR interrupt enabled * 0b1..BWT_ERR interrupt masked (default) */ #define EMVSIM_INT_MASK_BWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK) #define EMVSIM_INT_MASK_BGT_ERR_IM_MASK (0x1000U) #define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT (12U) /*! BGT_ERR_IM - Block Guard Time Error Interrupt * 0b0..BGT_ERR interrupt enabled * 0b1..BGT_ERR interrupt masked (default) */ #define EMVSIM_INT_MASK_BGT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK) #define EMVSIM_INT_MASK_GPCNT1_IM_MASK (0x2000U) #define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT (13U) /*! GPCNT1_IM - General Purpose Counter 1 Timeout Interrupt Mask * 0b0..GPCNT1_TO interrupt enabled * 0b1..GPCNT1_TO interrupt masked (default) */ #define EMVSIM_INT_MASK_GPCNT1_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK) #define EMVSIM_INT_MASK_RX_DATA_IM_MASK (0x4000U) #define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT (14U) /*! RX_DATA_IM - Receive Data Interrupt Mask * 0b0..RX_DATA interrupt enabled * 0b1..RX_DATA interrupt masked (default) */ #define EMVSIM_INT_MASK_RX_DATA_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK) #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) #define EMVSIM_INT_MASK_PEF_IM_SHIFT (15U) /*! PEF_IM - Parity Error Interrupt Mask * 0b0..PEF interrupt enabled * 0b1..PEF interrupt masked (default) */ #define EMVSIM_INT_MASK_PEF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK) /*! @} */ /*! @name RX_THD - Receiver Threshold Register */ /*! @{ */ #define EMVSIM_RX_THD_RDT_MASK (0xFU) #define EMVSIM_RX_THD_RDT_SHIFT (0U) #define EMVSIM_RX_THD_RDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK) #define EMVSIM_RX_THD_RNCK_THD_MASK (0xF00U) #define EMVSIM_RX_THD_RNCK_THD_SHIFT (8U) /*! RNCK_THD - Receiver NACK Threshold Value * 0b0000..Zero Threshold. RTE will not be set */ #define EMVSIM_RX_THD_RNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK) /*! @} */ /*! @name TX_THD - Transmitter Threshold Register */ /*! @{ */ #define EMVSIM_TX_THD_TDT_MASK (0xFU) #define EMVSIM_TX_THD_TDT_SHIFT (0U) #define EMVSIM_TX_THD_TDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK) #define EMVSIM_TX_THD_TNCK_THD_MASK (0xF00U) #define EMVSIM_TX_THD_TNCK_THD_SHIFT (8U) /*! TNCK_THD - Transmitter NACK Threshold Value * 0b0000..TNTE will never be set; retransmission after NACK reception is disabled. * 0b0001..TNTE will be set after 1 nack is received; 0 retransmissions occurs. * 0b0010..TNTE will be set after 2 nacks are received; at most 1 retransmission occurs. * 0b0011..TNTE will be set after 3 nacks are received; at most 2 retransmissions occurs. * 0b1111..TNTE will be set after 15 nacks are received; at most 14 retransmissions occurs. */ #define EMVSIM_TX_THD_TNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK) /*! @} */ /*! @name RX_STATUS - Receive Status Register */ /*! @{ */ #define EMVSIM_RX_STATUS_RFO_MASK (0x1U) #define EMVSIM_RX_STATUS_RFO_SHIFT (0U) /*! RFO - Receive FIFO Overflow Flag * 0b0..No overrun error has occurred (default) * 0b1..A byte was received when the received FIFO was already full */ #define EMVSIM_RX_STATUS_RFO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK) #define EMVSIM_RX_STATUS_RX_DATA_MASK (0x10U) #define EMVSIM_RX_STATUS_RX_DATA_SHIFT (4U) /*! RX_DATA - Receive Data Interrupt Flag * 0b0..No new byte is received * 0b1..New byte is received ans stored in Receive FIFO */ #define EMVSIM_RX_STATUS_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK) #define EMVSIM_RX_STATUS_RDTF_MASK (0x20U) #define EMVSIM_RX_STATUS_RDTF_SHIFT (5U) /*! RDTF - Receive Data Threshold Interrupt Flag * 0b0..Number of unread bytes in receive FIFO less than the value set by RDT[3:0] (default). * 0b1..Number of unread bytes in receive FIFO greater or than equal to value set by RDT[3:0]. */ #define EMVSIM_RX_STATUS_RDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK) #define EMVSIM_RX_STATUS_LRC_OK_MASK (0x40U) #define EMVSIM_RX_STATUS_LRC_OK_SHIFT (6U) /*! LRC_OK - LRC Check OK Flag * 0b0..Current LRC value does not match remainder. * 0b1..Current calculated LRC value matches the expected result (i.e. zero). */ #define EMVSIM_RX_STATUS_LRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK) #define EMVSIM_RX_STATUS_CRC_OK_MASK (0x80U) #define EMVSIM_RX_STATUS_CRC_OK_SHIFT (7U) /*! CRC_OK - CRC Check OK Flag * 0b0..Current CRC value does not match remainder. * 0b1..Current calculated CRC value matches the expected result. */ #define EMVSIM_RX_STATUS_CRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK) #define EMVSIM_RX_STATUS_CWT_ERR_MASK (0x100U) #define EMVSIM_RX_STATUS_CWT_ERR_SHIFT (8U) /*! CWT_ERR - Character Wait Time Error Flag * 0b0..No CWT violation has occurred (default). * 0b1..Time between two consecutive characters has exceeded the value in CHAR_WAIT. */ #define EMVSIM_RX_STATUS_CWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK) #define EMVSIM_RX_STATUS_RTE_MASK (0x200U) #define EMVSIM_RX_STATUS_RTE_SHIFT (9U) /*! RTE - Received NACK Threshold Error Flag * 0b0..Number of NACKs generated by the receiver is less than the value programmed in RTH[3:0] * 0b1..Number of NACKs generated by the receiver is equal to the value programmed in RTH[3:0] */ #define EMVSIM_RX_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK) #define EMVSIM_RX_STATUS_BWT_ERR_MASK (0x400U) #define EMVSIM_RX_STATUS_BWT_ERR_SHIFT (10U) /*! BWT_ERR - Block Wait Time Error Flag * 0b0..Block wait time not exceeded * 0b1..Block wait time was exceeded */ #define EMVSIM_RX_STATUS_BWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK) #define EMVSIM_RX_STATUS_BGT_ERR_MASK (0x800U) #define EMVSIM_RX_STATUS_BGT_ERR_SHIFT (11U) /*! BGT_ERR - Block Guard Time Error Flag * 0b0..Block guard time was sufficient * 0b1..Block guard time was too small */ #define EMVSIM_RX_STATUS_BGT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK) #define EMVSIM_RX_STATUS_PEF_MASK (0x1000U) #define EMVSIM_RX_STATUS_PEF_SHIFT (12U) /*! PEF - Parity Error Flag * 0b0..No parity error detected * 0b1..Parity error detected */ #define EMVSIM_RX_STATUS_PEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK) #define EMVSIM_RX_STATUS_FEF_MASK (0x2000U) #define EMVSIM_RX_STATUS_FEF_SHIFT (13U) /*! FEF - Frame Error Flag * 0b0..No frame error detected * 0b1..Frame error detected */ #define EMVSIM_RX_STATUS_FEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK) #define EMVSIM_RX_STATUS_RX_WPTR_MASK (0xF0000U) #define EMVSIM_RX_STATUS_RX_WPTR_SHIFT (16U) #define EMVSIM_RX_STATUS_RX_WPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK) #define EMVSIM_RX_STATUS_RX_CNT_MASK (0xF000000U) #define EMVSIM_RX_STATUS_RX_CNT_SHIFT (24U) /*! RX_CNT - Receive FIFO Byte Count * 0b0000..FIFO is emtpy */ #define EMVSIM_RX_STATUS_RX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK) /*! @} */ /*! @name TX_STATUS - Transmitter Status Register */ /*! @{ */ #define EMVSIM_TX_STATUS_TNTE_MASK (0x1U) #define EMVSIM_TX_STATUS_TNTE_SHIFT (0U) /*! TNTE - Transmit NACK Threshold Error Flag * 0b0..Transmit NACK threshold has not been reached (default) * 0b1..Transmit NACK threshold reached; transmitter frozen */ #define EMVSIM_TX_STATUS_TNTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK) #define EMVSIM_TX_STATUS_TFE_MASK (0x8U) #define EMVSIM_TX_STATUS_TFE_SHIFT (3U) /*! TFE - Transmit FIFO Empty Flag * 0b0..Transmit FIFO is not empty * 0b1..Transmit FIFO is empty (default) */ #define EMVSIM_TX_STATUS_TFE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK) #define EMVSIM_TX_STATUS_ETCF_MASK (0x10U) #define EMVSIM_TX_STATUS_ETCF_SHIFT (4U) /*! ETCF - Early Transmit Complete Flag * 0b0..Transmit pending or in progress * 0b1..Transmit complete (default) */ #define EMVSIM_TX_STATUS_ETCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK) #define EMVSIM_TX_STATUS_TCF_MASK (0x20U) #define EMVSIM_TX_STATUS_TCF_SHIFT (5U) /*! TCF - Transmit Complete Flag * 0b0..Transmit pending or in progress * 0b1..Transmit complete (default) */ #define EMVSIM_TX_STATUS_TCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK) #define EMVSIM_TX_STATUS_TFF_MASK (0x40U) #define EMVSIM_TX_STATUS_TFF_SHIFT (6U) /*! TFF - Transmit FIFO Full Flag * 0b1..A Transmit FIFO Full condition has occurred */ #define EMVSIM_TX_STATUS_TFF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK) #define EMVSIM_TX_STATUS_TDTF_MASK (0x80U) #define EMVSIM_TX_STATUS_TDTF_SHIFT (7U) /*! TDTF - Transmit Data Threshold Flag * 0b0..Number of bytes in FIFO is greater than TDT[3:0], or bit has been cleared * 0b1..Number of bytes in FIFO is less than or equal to TDT[3:0] (default) */ #define EMVSIM_TX_STATUS_TDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK) #define EMVSIM_TX_STATUS_GPCNT0_TO_MASK (0x100U) #define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT (8U) /*! GPCNT0_TO - General Purpose Counter 0 Timeout Flag * 0b0..GPCNT0_VAL time not reached, or bit has been cleared. (default) * 0b1..General Purpose counter has reached the GPCNT0_VAL value */ #define EMVSIM_TX_STATUS_GPCNT0_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK) #define EMVSIM_TX_STATUS_GPCNT1_TO_MASK (0x200U) #define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT (9U) /*! GPCNT1_TO - General Purpose Counter 1 Timeout Flag * 0b0..GPCNT1_VAL time not reached, or bit has been cleared. (default) * 0b1..General Purpose counter has reached the GPCNT1_VAL value */ #define EMVSIM_TX_STATUS_GPCNT1_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK) #define EMVSIM_TX_STATUS_TX_RPTR_MASK (0xF0000U) #define EMVSIM_TX_STATUS_TX_RPTR_SHIFT (16U) #define EMVSIM_TX_STATUS_TX_RPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK) #define EMVSIM_TX_STATUS_TX_CNT_MASK (0xF000000U) #define EMVSIM_TX_STATUS_TX_CNT_SHIFT (24U) /*! TX_CNT - Transmit FIFO Byte Count * 0b0000..FIFO is emtpy */ #define EMVSIM_TX_STATUS_TX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK) /*! @} */ /*! @name PCSR - Port Control and Status Register */ /*! @{ */ #define EMVSIM_PCSR_SAPD_MASK (0x1U) #define EMVSIM_PCSR_SAPD_SHIFT (0U) /*! SAPD - Auto Power Down Enable * 0b0..Auto power down disabled (default) * 0b1..Auto power down enabled */ #define EMVSIM_PCSR_SAPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK) #define EMVSIM_PCSR_SVCC_EN_MASK (0x2U) #define EMVSIM_PCSR_SVCC_EN_SHIFT (1U) /*! SVCC_EN - Vcc Enable for Smart Card * 0b0..Smart Card Voltage disabled (default) * 0b1..Smart Card Voltage enabled */ #define EMVSIM_PCSR_SVCC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK) #define EMVSIM_PCSR_VCCENP_MASK (0x4U) #define EMVSIM_PCSR_VCCENP_SHIFT (2U) /*! VCCENP - VCC Enable Polarity Control * 0b0..VCC_EN is active high. Polarity of SVCC_EN is unchanged. * 0b1..VCC_EN is active low. Polarity of SVCC_EN is inverted. */ #define EMVSIM_PCSR_VCCENP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK) #define EMVSIM_PCSR_SRST_MASK (0x8U) #define EMVSIM_PCSR_SRST_SHIFT (3U) /*! SRST - Reset to Smart Card * 0b0..Smart Card Reset is asserted (default) * 0b1..Smart Card Reset is de-asserted */ #define EMVSIM_PCSR_SRST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK) #define EMVSIM_PCSR_SCEN_MASK (0x10U) #define EMVSIM_PCSR_SCEN_SHIFT (4U) /*! SCEN - Clock Enable for Smart Card * 0b0..Smart Card Clock Disabled * 0b1..Smart Card Clock Enabled */ #define EMVSIM_PCSR_SCEN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK) #define EMVSIM_PCSR_SCSP_MASK (0x20U) #define EMVSIM_PCSR_SCSP_SHIFT (5U) /*! SCSP - Smart Card Clock Stop Polarity * 0b0..Clock is logic 0 when stopped by SCEN * 0b1..Clock is logic 1 when stopped by SCEN */ #define EMVSIM_PCSR_SCSP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK) #define EMVSIM_PCSR_SPD_MASK (0x80U) #define EMVSIM_PCSR_SPD_SHIFT (7U) /*! SPD - Auto Power Down Control * 0b0..No effect (default) * 0b1..Start Auto Powerdown or Power Down is in progress */ #define EMVSIM_PCSR_SPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK) #define EMVSIM_PCSR_SPDIM_MASK (0x1000000U) #define EMVSIM_PCSR_SPDIM_SHIFT (24U) /*! SPDIM - Smart Card Presence Detect Interrupt Mask * 0b0..SIM presence detect interrupt is enabled * 0b1..SIM presence detect interrupt is masked (default) */ #define EMVSIM_PCSR_SPDIM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK) #define EMVSIM_PCSR_SPDIF_MASK (0x2000000U) #define EMVSIM_PCSR_SPDIF_SHIFT (25U) /*! SPDIF - Smart Card Presence Detect Interrupt Flag * 0b0..No insertion or removal of Smart Card detected on Port (default) * 0b1..Insertion or removal of Smart Card detected on Port */ #define EMVSIM_PCSR_SPDIF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK) #define EMVSIM_PCSR_SPDP_MASK (0x4000000U) #define EMVSIM_PCSR_SPDP_SHIFT (26U) /*! SPDP - Smart Card Presence Detect Pin Status * 0b0..SIM Presence Detect pin is logic low * 0b1..SIM Presence Detectpin is logic high */ #define EMVSIM_PCSR_SPDP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK) #define EMVSIM_PCSR_SPDES_MASK (0x8000000U) #define EMVSIM_PCSR_SPDES_SHIFT (27U) /*! SPDES - SIM Presence Detect Edge Select * 0b0..Falling edge on the pin (default) * 0b1..Rising edge on the pin */ #define EMVSIM_PCSR_SPDES(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK) /*! @} */ /*! @name RX_BUF - Receive Data Read Buffer */ /*! @{ */ #define EMVSIM_RX_BUF_RX_BYTE_MASK (0xFFU) #define EMVSIM_RX_BUF_RX_BYTE_SHIFT (0U) #define EMVSIM_RX_BUF_RX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK) /*! @} */ /*! @name TX_BUF - Transmit Data Buffer */ /*! @{ */ #define EMVSIM_TX_BUF_TX_BYTE_MASK (0xFFU) #define EMVSIM_TX_BUF_TX_BYTE_SHIFT (0U) #define EMVSIM_TX_BUF_TX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK) /*! @} */ /*! @name TX_GETU - Transmitter Guard ETU Value Register */ /*! @{ */ #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) #define EMVSIM_TX_GETU_GETU_SHIFT (0U) /*! GETU - Transmitter Guard Time Value in ETU * 0b00000000..no additional ETUs inserted (default) * 0b00000001..1 additional ETU inserted * 0b11111110..254 additional ETUs inserted * 0b11111111..Subtracts one ETU by reducing the number of STOP bits from two to one */ #define EMVSIM_TX_GETU_GETU(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK) /*! @} */ /*! @name CWT_VAL - Character Wait Time Value Register */ /*! @{ */ #define EMVSIM_CWT_VAL_CWT_MASK (0xFFFFU) #define EMVSIM_CWT_VAL_CWT_SHIFT (0U) #define EMVSIM_CWT_VAL_CWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK) /*! @} */ /*! @name BWT_VAL - Block Wait Time Value Register */ /*! @{ */ #define EMVSIM_BWT_VAL_BWT_MASK (0xFFFFFFFFU) #define EMVSIM_BWT_VAL_BWT_SHIFT (0U) #define EMVSIM_BWT_VAL_BWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK) /*! @} */ /*! @name BGT_VAL - Block Guard Time Value Register */ /*! @{ */ #define EMVSIM_BGT_VAL_BGT_MASK (0xFFFFU) #define EMVSIM_BGT_VAL_BGT_SHIFT (0U) #define EMVSIM_BGT_VAL_BGT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK) /*! @} */ /*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */ /*! @{ */ #define EMVSIM_GPCNT0_VAL_GPCNT0_MASK (0xFFFFU) #define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT (0U) #define EMVSIM_GPCNT0_VAL_GPCNT0(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK) /*! @} */ /*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */ /*! @{ */ #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) #define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT (0U) #define EMVSIM_GPCNT1_VAL_GPCNT1(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK) /*! @} */ /*! * @} */ /* end of group EMVSIM_Register_Masks */ /* EMVSIM - Peripheral instance base addresses */ /** Peripheral DMA__EMV_SIM0 base address */ #define DMA__EMV_SIM0_BASE (0x5A0D0000u) /** Peripheral DMA__EMV_SIM0 base pointer */ #define DMA__EMV_SIM0 ((EMVSIM_Type *)DMA__EMV_SIM0_BASE) /** Peripheral DMA__EMV_SIM1 base address */ #define DMA__EMV_SIM1_BASE (0x5A0E0000u) /** Peripheral DMA__EMV_SIM1 base pointer */ #define DMA__EMV_SIM1 ((EMVSIM_Type *)DMA__EMV_SIM1_BASE) /** Array initializer of EMVSIM peripheral base addresses */ #define EMVSIM_BASE_ADDRS { DMA__EMV_SIM0_BASE, DMA__EMV_SIM1_BASE } /** Array initializer of EMVSIM peripheral base pointers */ #define EMVSIM_BASE_PTRS { DMA__EMV_SIM0, DMA__EMV_SIM1 } /** Interrupt vectors for the EMVSIM peripheral type */ #define EMVSIM_IRQS { DMA_SIM0_INT_IRQn, DMA_SIM1_INT_IRQn } /*! * @} */ /* end of group EMVSIM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ENET Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer * @{ */ /** ENET - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t EIR; /**< offset: 0x4 */ __IO uint32_t EIMR; /**< offset: 0x8 */ uint8_t RESERVED_1[4]; __IO uint32_t RDAR; /**< offset: 0x10 */ __IO uint32_t TDAR; /**< offset: 0x14 */ uint8_t RESERVED_2[12]; __IO uint32_t ECR; /**< offset: 0x24 */ uint8_t RESERVED_3[24]; __IO uint32_t MMFR; /**< offset: 0x40 */ __IO uint32_t MSCR; /**< offset: 0x44 */ uint8_t RESERVED_4[28]; __IO uint32_t MIBC; /**< offset: 0x64 */ uint8_t RESERVED_5[28]; __IO uint32_t RCR; /**< offset: 0x84 */ uint8_t RESERVED_6[60]; __IO uint32_t TCR; /**< offset: 0xC4 */ uint8_t RESERVED_7[28]; __IO uint32_t PALR; /**< offset: 0xE4 */ __IO uint32_t PAUR; /**< offset: 0xE8 */ __IO uint32_t OPD; /**< offset: 0xEC */ __IO uint32_t TXIC[3]; /**< offset: 0xF0 */ uint8_t RESERVED_8[4]; __IO uint32_t RXIC[3]; /**< offset: 0x100 */ uint8_t RESERVED_9[12]; __IO uint32_t IAUR; /**< offset: 0x118 */ __IO uint32_t IALR; /**< offset: 0x11C */ __IO uint32_t GAUR; /**< offset: 0x120 */ __IO uint32_t GALR; /**< offset: 0x124 */ uint8_t RESERVED_10[28]; __IO uint32_t TFWR; /**< offset: 0x144 */ uint8_t RESERVED_11[24]; __IO uint32_t RDSR1; /**< offset: 0x160 */ __IO uint32_t TDSR1; /**< offset: 0x164 */ __IO uint32_t MRBR1; /**< offset: 0x168 */ __IO uint32_t RDSR2; /**< offset: 0x16C */ __IO uint32_t TDSR2; /**< offset: 0x170 */ __IO uint32_t MRBR2; /**< offset: 0x174 */ uint8_t RESERVED_12[8]; __IO uint32_t RDSR; /**< offset: 0x180 */ __IO uint32_t TDSR; /**< offset: 0x184 */ __IO uint32_t MRBR; /**< offset: 0x188 */ uint8_t RESERVED_13[4]; __IO uint32_t RSFL; /**< offset: 0x190 */ __IO uint32_t RSEM; /**< offset: 0x194 */ __IO uint32_t RAEM; /**< offset: 0x198 */ __IO uint32_t RAFL; /**< offset: 0x19C */ __IO uint32_t TSEM; /**< offset: 0x1A0 */ __IO uint32_t TAEM; /**< offset: 0x1A4 */ __IO uint32_t TAFL; /**< offset: 0x1A8 */ __IO uint32_t TIPG; /**< offset: 0x1AC */ __IO uint32_t FTRL; /**< offset: 0x1B0 */ uint8_t RESERVED_14[12]; __IO uint32_t TACC; /**< offset: 0x1C0 */ __IO uint32_t RACC; /**< offset: 0x1C4 */ __IO uint32_t RCMR[2]; /**< offset: 0x1C8 */ uint8_t RESERVED_15[8]; __IO uint32_t DMACFG[2]; /**< offset: 0x1D8 */ __IO uint32_t RDAR1; /**< offset: 0x1E0 */ __IO uint32_t TDAR1; /**< offset: 0x1E4 */ __IO uint32_t RDAR2; /**< offset: 0x1E8 */ __IO uint32_t TDAR2; /**< offset: 0x1EC */ __IO uint32_t QOS; /**< offset: 0x1F0 */ uint8_t RESERVED_16[12]; __I uint32_t RMON_T_DROP; /**< offset: 0x200 */ __I uint32_t RMON_T_PACKETS; /**< offset: 0x204 */ __I uint32_t RMON_T_BC_PKT; /**< offset: 0x208 */ __I uint32_t RMON_T_MC_PKT; /**< offset: 0x20C */ __I uint32_t RMON_T_CRC_ALIGN; /**< offset: 0x210 */ __I uint32_t RMON_T_UNDERSIZE; /**< offset: 0x214 */ __I uint32_t RMON_T_OVERSIZE; /**< offset: 0x218 */ __I uint32_t RMON_T_FRAG; /**< offset: 0x21C */ __I uint32_t RMON_T_JAB; /**< offset: 0x220 */ __I uint32_t RMON_T_COL; /**< offset: 0x224 */ __I uint32_t RMON_T_P64; /**< offset: 0x228 */ __I uint32_t RMON_T_P65TO127; /**< offset: 0x22C */ __I uint32_t RMON_T_P128TO255; /**< offset: 0x230 */ __I uint32_t RMON_T_P256TO511; /**< offset: 0x234 */ __I uint32_t RMON_T_P512TO1023; /**< offset: 0x238 */ __I uint32_t RMON_T_P1024TO2047; /**< offset: 0x23C */ __I uint32_t RMON_T_P_GTE2048; /**< offset: 0x240 */ __I uint32_t RMON_T_OCTETS; /**< offset: 0x244 */ __I uint32_t IEEE_T_DROP; /**< offset: 0x248 */ __I uint32_t IEEE_T_FRAME_OK; /**< offset: 0x24C */ __I uint32_t IEEE_T_1COL; /**< offset: 0x250 */ __I uint32_t IEEE_T_MCOL; /**< offset: 0x254 */ __I uint32_t IEEE_T_DEF; /**< offset: 0x258 */ __I uint32_t IEEE_T_LCOL; /**< offset: 0x25C */ __I uint32_t IEEE_T_EXCOL; /**< offset: 0x260 */ __I uint32_t IEEE_T_MACERR; /**< offset: 0x264 */ __I uint32_t IEEE_T_CSERR; /**< offset: 0x268 */ __I uint32_t IEEE_T_SQE; /**< offset: 0x26C */ __I uint32_t IEEE_T_FDXFC; /**< offset: 0x270 */ __I uint32_t IEEE_T_OCTETS_OK; /**< offset: 0x274 */ uint8_t RESERVED_17[12]; __I uint32_t RMON_R_PACKETS; /**< offset: 0x284 */ __I uint32_t RMON_R_BC_PKT; /**< offset: 0x288 */ __I uint32_t RMON_R_MC_PKT; /**< offset: 0x28C */ __I uint32_t RMON_R_CRC_ALIGN; /**< offset: 0x290 */ __I uint32_t RMON_R_UNDERSIZE; /**< offset: 0x294 */ __I uint32_t RMON_R_OVERSIZE; /**< offset: 0x298 */ __I uint32_t RMON_R_FRAG; /**< offset: 0x29C */ __I uint32_t RMON_R_JAB; /**< offset: 0x2A0 */ __I uint32_t RMON_R_RESVD_0; /**< offset: 0x2A4 */ __I uint32_t RMON_R_P64; /**< offset: 0x2A8 */ __I uint32_t RMON_R_P65TO127; /**< offset: 0x2AC */ __I uint32_t RMON_R_P128TO255; /**< offset: 0x2B0 */ __I uint32_t RMON_R_P256TO511; /**< offset: 0x2B4 */ __I uint32_t RMON_R_P512TO1023; /**< offset: 0x2B8 */ __I uint32_t RMON_R_P1024TO2047; /**< offset: 0x2BC */ __I uint32_t RMON_R_P_GTE2048; /**< offset: 0x2C0 */ __I uint32_t RMON_R_OCTETS; /**< offset: 0x2C4 */ __I uint32_t IEEE_R_DROP; /**< offset: 0x2C8 */ __I uint32_t IEEE_R_FRAME_OK; /**< offset: 0x2CC */ __I uint32_t IEEE_R_CRC; /**< offset: 0x2D0 */ __I uint32_t IEEE_R_ALIGN; /**< offset: 0x2D4 */ __I uint32_t IEEE_R_MACERR; /**< offset: 0x2D8 */ __I uint32_t IEEE_R_FDXFC; /**< offset: 0x2DC */ __I uint32_t IEEE_R_OCTETS_OK; /**< offset: 0x2E0 */ uint8_t RESERVED_18[284]; __IO uint32_t ATCR; /**< offset: 0x400 */ __IO uint32_t ATVR; /**< offset: 0x404 */ __IO uint32_t ATOFF; /**< offset: 0x408 */ __IO uint32_t ATPER; /**< offset: 0x40C */ __IO uint32_t ATCOR; /**< offset: 0x410 */ __IO uint32_t ATINC; /**< offset: 0x414 */ __I uint32_t ATSTMP; /**< offset: 0x418 */ uint8_t RESERVED_19[356]; __IO uint32_t MDATA; /**< offset: 0x580 */ __IO uint32_t MMASK; /**< offset: 0x584 */ __IO uint32_t MCONFIG; /**< offset: 0x588 */ __IO uint32_t MENTRYRW; /**< offset: 0x58C */ __IO uint32_t RXPCTL; /**< offset: 0x590 */ __IO uint32_t MAXFRMOFF; /**< offset: 0x594 */ __I uint32_t RXPARST; /**< offset: 0x598 */ uint8_t RESERVED_20[4]; __I uint32_t PARSDSCD; /**< offset: 0x5A0 */ struct { /**< offset: 0x5A4 */ __I uint32_t PRSACPT; __I uint32_t PRSRJCT; } PRS[3]; uint8_t RESERVED_21[72]; __IO uint32_t TGSR; /**< offset: 0x604 */ struct { /**< offset: 0x608 */ __IO uint32_t TCSR; __IO uint32_t TCCR; } CHANNEL[4]; } ENET_Type; /* ---------------------------------------------------------------------------- -- ENET Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_Register_Masks ENET Register Masks * @{ */ /* EIR Bit Fields */ #define ENET_EIR_RXB1_MASK 0x1u #define ENET_EIR_RXB1_SHIFT 0 #define ENET_EIR_RXF1_MASK 0x2u #define ENET_EIR_RXF1_SHIFT 1 #define ENET_EIR_TXB1_MASK 0x4u #define ENET_EIR_TXB1_SHIFT 2 #define ENET_EIR_TXF1_MASK 0x8u #define ENET_EIR_TXF1_SHIFT 3 #define ENET_EIR_RXB2_MASK 0x10u #define ENET_EIR_RXB2_SHIFT 4 #define ENET_EIR_RXF2_MASK 0x20u #define ENET_EIR_RXF2_SHIFT 5 #define ENET_EIR_TXB2_MASK 0x40u #define ENET_EIR_TXB2_SHIFT 6 #define ENET_EIR_TXF2_MASK 0x80u #define ENET_EIR_TXF2_SHIFT 7 #define ENET_EIR_RXFLUSH_0_MASK 0x1000u #define ENET_EIR_RXFLUSH_0_SHIFT 12 #define ENET_EIR_RXFLUSH_1_MASK 0x2000u #define ENET_EIR_RXFLUSH_1_SHIFT 13 #define ENET_EIR_RXFLUSH_2_MASK 0x4000u #define ENET_EIR_RXFLUSH_2_SHIFT 14 #define ENET_EIR_TS_TIMER_MASK 0x8000u #define ENET_EIR_TS_TIMER_SHIFT 15 #define ENET_EIR_TS_AVAIL_MASK 0x10000u #define ENET_EIR_TS_AVAIL_SHIFT 16 #define ENET_EIR_WAKEUP_MASK 0x20000u #define ENET_EIR_WAKEUP_SHIFT 17 #define ENET_EIR_PLR_MASK 0x40000u #define ENET_EIR_PLR_SHIFT 18 #define ENET_EIR_UN_MASK 0x80000u #define ENET_EIR_UN_SHIFT 19 #define ENET_EIR_RL_MASK 0x100000u #define ENET_EIR_RL_SHIFT 20 #define ENET_EIR_LC_MASK 0x200000u #define ENET_EIR_LC_SHIFT 21 #define ENET_EIR_EBERR_MASK 0x400000u #define ENET_EIR_EBERR_SHIFT 22 #define ENET_EIR_MII_MASK 0x800000u #define ENET_EIR_MII_SHIFT 23 #define ENET_EIR_RXB_MASK 0x1000000u #define ENET_EIR_RXB_SHIFT 24 #define ENET_EIR_RXF_MASK 0x2000000u #define ENET_EIR_RXF_SHIFT 25 #define ENET_EIR_TXB_MASK 0x4000000u #define ENET_EIR_TXB_SHIFT 26 #define ENET_EIR_TXF_MASK 0x8000000u #define ENET_EIR_TXF_SHIFT 27 #define ENET_EIR_GRA_MASK 0x10000000u #define ENET_EIR_GRA_SHIFT 28 #define ENET_EIR_BABT_MASK 0x20000000u #define ENET_EIR_BABT_SHIFT 29 #define ENET_EIR_BABR_MASK 0x40000000u #define ENET_EIR_BABR_SHIFT 30 /* EIMR Bit Fields */ #define ENET_EIMR_RXB1_MASK 0x1u #define ENET_EIMR_RXB1_SHIFT 0 #define ENET_EIMR_RXF1_MASK 0x2u #define ENET_EIMR_RXF1_SHIFT 1 #define ENET_EIMR_TXB1_MASK 0x4u #define ENET_EIMR_TXB1_SHIFT 2 #define ENET_EIMR_TXF1_MASK 0x8u #define ENET_EIMR_TXF1_SHIFT 3 #define ENET_EIMR_RXB2_MASK 0x10u #define ENET_EIMR_RXB2_SHIFT 4 #define ENET_EIMR_RXF2_MASK 0x20u #define ENET_EIMR_RXF2_SHIFT 5 #define ENET_EIMR_TXB2_MASK 0x40u #define ENET_EIMR_TXB2_SHIFT 6 #define ENET_EIMR_TXF2_MASK 0x80u #define ENET_EIMR_TXF2_SHIFT 7 #define ENET_EIMR_RXFLUSH_0_MASK 0x1000u #define ENET_EIMR_RXFLUSH_0_SHIFT 12 #define ENET_EIMR_RXFLUSH_1_MASK 0x2000u #define ENET_EIMR_RXFLUSH_1_SHIFT 13 #define ENET_EIMR_RXFLUSH_2_MASK 0x4000u #define ENET_EIMR_RXFLUSH_2_SHIFT 14 #define ENET_EIMR_TS_TIMER_MASK 0x8000u #define ENET_EIMR_TS_TIMER_SHIFT 15 #define ENET_EIMR_TS_AVAIL_MASK 0x10000u #define ENET_EIMR_TS_AVAIL_SHIFT 16 #define ENET_EIMR_WAKEUP_MASK 0x20000u #define ENET_EIMR_WAKEUP_SHIFT 17 #define ENET_EIMR_PLR_MASK 0x40000u #define ENET_EIMR_PLR_SHIFT 18 #define ENET_EIMR_UN_MASK 0x80000u #define ENET_EIMR_UN_SHIFT 19 #define ENET_EIMR_RL_MASK 0x100000u #define ENET_EIMR_RL_SHIFT 20 #define ENET_EIMR_LC_MASK 0x200000u #define ENET_EIMR_LC_SHIFT 21 #define ENET_EIMR_EBERR_MASK 0x400000u #define ENET_EIMR_EBERR_SHIFT 22 #define ENET_EIMR_MII_MASK 0x800000u #define ENET_EIMR_MII_SHIFT 23 #define ENET_EIMR_RXB_MASK 0x1000000u #define ENET_EIMR_RXB_SHIFT 24 #define ENET_EIMR_RXF_MASK 0x2000000u #define ENET_EIMR_RXF_SHIFT 25 #define ENET_EIMR_TXB_MASK 0x4000000u #define ENET_EIMR_TXB_SHIFT 26 #define ENET_EIMR_TXF_MASK 0x8000000u #define ENET_EIMR_TXF_SHIFT 27 #define ENET_EIMR_GRA_MASK 0x10000000u #define ENET_EIMR_GRA_SHIFT 28 #define ENET_EIMR_BABT_MASK 0x20000000u #define ENET_EIMR_BABT_SHIFT 29 #define ENET_EIMR_BABR_MASK 0x40000000u #define ENET_EIMR_BABR_SHIFT 30 /* RDAR Bit Fields */ #define ENET_RDAR_RDAR_MASK 0x1000000u #define ENET_RDAR_RDAR_SHIFT 24 /* TDAR Bit Fields */ #define ENET_TDAR_TDAR_MASK 0x1000000u #define ENET_TDAR_TDAR_SHIFT 24 /* ECR Bit Fields */ #define ENET_ECR_RESET_MASK 0x1u #define ENET_ECR_RESET_SHIFT 0 #define ENET_ECR_ETHEREN_MASK 0x2u #define ENET_ECR_ETHEREN_SHIFT 1 #define ENET_ECR_MAGICEN_MASK 0x4u #define ENET_ECR_MAGICEN_SHIFT 2 #define ENET_ECR_SLEEP_MASK 0x8u #define ENET_ECR_SLEEP_SHIFT 3 #define ENET_ECR_EN1588_MASK 0x10u #define ENET_ECR_EN1588_SHIFT 4 #define ENET_ECR_SPEED_MASK 0x20u #define ENET_ECR_SPEED_SHIFT 5 #define ENET_ECR_DBGEN_MASK 0x40u #define ENET_ECR_DBGEN_SHIFT 6 #define ENET_ECR_DBSWP_MASK 0x100u #define ENET_ECR_DBSWP_SHIFT 8 #define ENET_ECR_SVLANEN_MASK 0x200u #define ENET_ECR_SVLANEN_SHIFT 9 #define ENET_ECR_VLANUSE2ND_MASK 0x400u #define ENET_ECR_VLANUSE2ND_SHIFT 10 #define ENET_ECR_SVLANDBL_MASK 0x800u #define ENET_ECR_SVLANDBL_SHIFT 11 #define ENET_ECR_TXC_DLY_MASK 0x10000u #define ENET_ECR_TXC_DLY_SHIFT 16 #define ENET_ECR_RXC_DLY_MASK 0x20000u #define ENET_ECR_RXC_DLY_SHIFT 17 /* MMFR Bit Fields */ #define ENET_MMFR_DATA_MASK 0xFFFFu #define ENET_MMFR_DATA_SHIFT 0 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<