/* ** ################################################################### ** Processors: MIMX8MN4CVTIZ ** MIMX8MN4DVTJZ ** ** Compilers: GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** ** Reference manual: MX8MNRM, Rev.A, 04/2019 ** Version: rev. 2.0, 2019-09-23 ** Build: b190830 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8MN4_cm7 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. ** Copyright 2016-2019 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2019-04-22) ** Initial version. ** - rev. 2.0 (2019-09-23) ** Rev.B Header RFP ** ** ################################################################### */ /*! * @file MIMX8MN4_cm7.h * @version 2.0 * @date 2019-09-23 * @brief CMSIS Peripheral Access Layer for MIMX8MN4_cm7 * * CMSIS Peripheral Access Layer for MIMX8MN4_cm7 */ #ifndef _MIMX8MN4_CM7_H_ #define _MIMX8MN4_CM7_H_ /**< Symbol preventing repeated inclusion */ /** Memory map major version (memory maps with equal major version number are * compatible) */ #define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U /* ---------------------------------------------------------------------------- -- Interrupt vector numbers ---------------------------------------------------------------------------- */ /*! * @addtogroup Interrupt_vector_numbers Interrupt vector numbers * @{ */ /** Interrupt Number Definitions */ #define NUMBER_OF_INT_VECTORS 144 /**< Number of interrupts in the Vector table */ typedef enum IRQn { /* Auxiliary constants */ NotAvail_IRQn = -128, /**< Not available device specific interrupt */ /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */ BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */ UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */ SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */ DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */ PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */ SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */ /* Device specific interrupts */ GPR_IRQ_IRQn = 0, /**< GPR Interrupt. Used to notify cores on exception condition while boot. */ DAP_IRQn = 1, /**< DAP Interrupt */ SDMA1_IRQn = 2, /**< AND of all 48 SDMA1 interrupts (events) from all the channels */ GPU3D_IRQn = 3, /**< GPU3D Interrupt */ SNVS_IRQn = 4, /**< ON-OFF button press shorter than 5 seconds (pulse event) */ LCDIF_IRQn = 5, /**< LCDIF Interrupt */ SPDIF1_IRQn = 6, /**< SPDIF1 RZX/TX Interrupt */ Reserved23_IRQn = 7, /**< Reserved Interrupt */ Reserved24_IRQn = 8, /**< Reserved Interrupt */ QOS_IRQn = 9, /**< QOS interrupt */ WDOG3_IRQn = 10, /**< Watchdog Timer reset */ HS_CP1_IRQn = 11, /**< HS Interrupt Request */ APBHDMA_IRQn = 12, /**< GPMI operation channel 0-3 description complete interrupt */ Reserved29_IRQn = 13, /**< Reserved */ BCH_IRQn = 14, /**< BCH operation complete interrupt */ GPMI_IRQn = 15, /**< GPMI operation TIMEOUT ERROR interrupt */ ISI_CH0_IRQn = 16, /**< ISI Camera Channel 0 Interrupt */ MIPI_CSI1_IRQn = 17, /**< MIPI CSI Interrupt */ MIPI_DSI_IRQn = 18, /**< MIPI DSI Interrupt */ SNVS_Consolidated_IRQn = 19, /**< SRTC Consolidated Interrupt. Non TZ. */ SNVS_Security_IRQn = 20, /**< SRTC Security Interrupt. TZ. */ CSU_IRQn = 21, /**< CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted. */ USDHC1_IRQn = 22, /**< uSDHC1 Enhanced SDHC Interrupt Request */ USDHC2_IRQn = 23, /**< uSDHC2 Enhanced SDHC Interrupt Request */ USDHC3_IRQn = 24, /**< uSDHC3 Enhanced SDHC Interrupt Request */ Reserved41_IRQn = 25, /**< Reserved Interrupt */ UART1_IRQn = 26, /**< UART-1 ORed interrupt */ UART2_IRQn = 27, /**< UART-2 ORed interrupt */ UART3_IRQn = 28, /**< UART-3 ORed interrupt */ UART4_IRQn = 29, /**< UART-4 ORed interrupt */ Reserved46_IRQn = 30, /**< Reserved Interrupt */ ECSPI1_IRQn = 31, /**< ECSPI1 interrupt request line to the core. */ ECSPI2_IRQn = 32, /**< ECSPI2 interrupt request line to the core. */ ECSPI3_IRQn = 33, /**< ECSPI3 interrupt request line to the core. */ SDMA3_IRQn = 34, /**< AND of all 48 SDMA3 interrupts (events) from all the channels */ I2C1_IRQn = 35, /**< I2C-1 Interrupt */ I2C2_IRQn = 36, /**< I2C-2 Interrupt */ I2C3_IRQn = 37, /**< I2C-3 Interrupt */ I2C4_IRQn = 38, /**< I2C-4 Interrupt */ RDC_IRQn = 39, /**< RDC interrupt */ USB1_IRQn = 40, /**< USB1 Interrupt */ Reserved57_IRQn = 41, /**< Reserved Interrupt */ ISI_CH1_IRQn = 42, /**< ISI Camera Channel 1 Interrupt */ ISI_CH2_IRQn = 43, /**< ISI Camera Channel 2 Interrupt */ PDM_HWVAD_EVENT_IRQn = 44, /**< Digital Microphone interface voice activity detector event interrupt */ PDM_HWVAD_ERROR_IRQn = 45, /**< Digital Microphone interface voice activity detector error interrupt */ GPT6_IRQn = 46, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */ SCTR_IRQ0_IRQn = 47, /**< System Counter Interrupt 0 */ SCTR_IRQ1_IRQn = 48, /**< System Counter Interrupt 1 */ TEMPMON_LOW_IRQn = 49, /**< TempSensor (Temperature low alarm). */ I2S3_IRQn = 50, /**< SAI3 Receive / Transmit Interrupt */ GPT5_IRQn = 51, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */ GPT4_IRQn = 52, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */ GPT3_IRQn = 53, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */ GPT2_IRQn = 54, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */ GPT1_IRQn = 55, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */ GPIO1_INT7_IRQn = 56, /**< Active HIGH Interrupt from INT7 from GPIO */ GPIO1_INT6_IRQn = 57, /**< Active HIGH Interrupt from INT6 from GPIO */ GPIO1_INT5_IRQn = 58, /**< Active HIGH Interrupt from INT5 from GPIO */ GPIO1_INT4_IRQn = 59, /**< Active HIGH Interrupt from INT4 from GPIO */ GPIO1_INT3_IRQn = 60, /**< Active HIGH Interrupt from INT3 from GPIO */ GPIO1_INT2_IRQn = 61, /**< Active HIGH Interrupt from INT2 from GPIO */ GPIO1_INT1_IRQn = 62, /**< Active HIGH Interrupt from INT1 from GPIO */ GPIO1_INT0_IRQn = 63, /**< Active HIGH Interrupt from INT0 from GPIO */ GPIO1_Combined_0_15_IRQn = 64, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */ GPIO1_Combined_16_31_IRQn = 65, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */ GPIO2_Combined_0_15_IRQn = 66, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */ GPIO2_Combined_16_31_IRQn = 67, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */ GPIO3_Combined_0_15_IRQn = 68, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */ GPIO3_Combined_16_31_IRQn = 69, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */ GPIO4_Combined_0_15_IRQn = 70, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */ GPIO4_Combined_16_31_IRQn = 71, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */ GPIO5_Combined_0_15_IRQn = 72, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */ GPIO5_Combined_16_31_IRQn = 73, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */ Reserved90_IRQn = 74, /**< Reserved interrupt */ Reserved91_IRQn = 75, /**< Reserved interrupt */ Reserved92_IRQn = 76, /**< Reserved interrupt */ Reserved93_IRQn = 77, /**< Reserved interrupt */ WDOG1_IRQn = 78, /**< Watchdog Timer reset */ WDOG2_IRQn = 79, /**< Watchdog Timer reset */ Reserved96_IRQn = 80, /**< Reserved interrupt */ PWM1_IRQn = 81, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */ PWM2_IRQn = 82, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */ PWM3_IRQn = 83, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */ PWM4_IRQn = 84, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */ CCM_IRQ1_IRQn = 85, /**< CCM Interrupt Request 1 */ CCM_IRQ2_IRQn = 86, /**< CCM Interrupt Request 2 */ GPC_IRQn = 87, /**< GPC Interrupt Request 1 */ MU_A53_IRQn = 88, /**< Interrupt to A53 */ SRC_IRQn = 89, /**< SRC interrupt request */ I2S56_IRQn = 90, /**< SAI5/6 Receive / Transmit Interrupt */ RTIC_IRQn = 91, /**< RTIC Interrupt */ CPU_PerformanceUnit_IRQn = 92, /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n] */ CPU_CTI_Trigger_IRQn = 93, /**< CTI trigger outputs (internal: nCTIIRQ[n] */ SRC_Combined_IRQn = 94, /**< Combined CPU wdog interrupts (4x) out of SRC. */ Reserved111_IRQn = 95, /**< Reserved Interrupt */ I2S2_IRQn = 96, /**< SAI2 Receive / Transmit Interrupt */ MU_M7_IRQn = 97, /**< Interrupt to M7 */ DDR_PerformanceMonitor_IRQn = 98, /**< ddr Interrupt for performance monitor */ DDR_IRQn = 99, /**< ddr Interrupt */ Reserved116_IRQn = 100, /**< Reserved interrupt */ CPU_Error_AXI_IRQn = 101, /**< CPU Error indicator for AXI transaction with a write response error condition */ CPU_Error_L2RAM_IRQn = 102, /**< CPU Error indicator for L2 RAM double-bit ECC error */ SDMA2_IRQn = 103, /**< AND of all 48 SDMA2 interrupts (events) from all the channels */ SJC_IRQn = 104, /**< Interrupt triggered by SJC register */ CAAM_IRQ0_IRQn = 105, /**< CAAM interrupt queue for JQ */ CAAM_IRQ1_IRQn = 106, /**< CAAM interrupt queue for JQ */ QSPI_IRQn = 107, /**< QSPI Interrupt */ TZASC_IRQn = 108, /**< TZASC (PL380) interrupt */ PDM_EVENT_IRQn = 109, /**< Digital Microphone interface interrupt */ PDM_ERROR_IRQn = 110, /**< Digital Microphone interface error interrupt */ I2S7_IRQn = 111, /**< SAI7 Receive / Transmit Interrupt */ PERFMON1_IRQn = 112, /**< General Interrupt */ PERFMON2_IRQn = 113, /**< General Interrupt */ CAAM_IRQ2_IRQn = 114, /**< CAAM interrupt queue for JQ */ CAAM_ERROR_IRQn = 115, /**< Recoverable error interrupt */ HS_CP0_IRQn = 116, /**< HS Interrupt Request */ CM7_CTI_IRQn = 117, /**< CTI trigger outputs from CM7 platform */ ENET_MAC0_Rx_Tx_Done1_IRQn = 118, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ ENET_MAC0_Rx_Tx_Done2_IRQn = 119, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ ENET_IRQn = 120, /**< MAC 0 IRQ */ ENET_1588_IRQn = 121, /**< MAC 0 1588 Timer Interrupt - synchronous */ ASRC_IRQn = 122, /**< ASRC Interrupt */ Reserved139_IRQn = 123, /**< Reserved Interrupt */ Reserved140_IRQn = 124, /**< Reserved Interrupt */ Reserved141_IRQn = 125, /**< Reserved Interrupt */ ISI_CH3_IRQn = 126, /**< ISI Camera Channel 3 Interrupt */ Reserved143_IRQn = 127 /**< Reserved Interrupt */ } IRQn_Type; /*! * @} */ /* end of group Interrupt_vector_numbers */ /* ---------------------------------------------------------------------------- -- Cortex M7 Core Configuration ---------------------------------------------------------------------------- */ /*! * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration * @{ */ #define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ #define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */ #define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */ #define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */ #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ #include "core_cm7.h" /* Core Peripheral Access Layer */ #include "system_MIMX8MN4_cm7.h" /* Device specific configuration file */ /*! * @} */ /* end of group Cortex_Core_Configuration */ /* ---------------------------------------------------------------------------- -- Mapping Information ---------------------------------------------------------------------------- */ /*! * @addtogroup Mapping_Information Mapping Information * @{ */ /** Mapping Information */ /*! * @addtogroup iomuxc_pads * @{ */ /******************************************************************************* * Definitions *******************************************************************************/ /*! * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD * * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections. */ typedef enum _iomuxc_sw_mux_ctl_pad { kIOMUXC_SW_MUX_CTL_PAD_BOOT_MODE2 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_BOOT_MODE3 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ENET_MDC = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ENET_MDIO = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ENET_TD3 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ENET_TD2 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ENET_TD1 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ENET_TD0 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ENET_TXC = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ENET_RXC = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ENET_RD0 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ENET_RD1 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ENET_RD2 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ENET_RD3 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD1_CLK = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD1_CMD = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA4 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA5 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA6 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA7 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD1_STROBE = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD2_CD_B = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD2_CLK = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD2_CMD = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SD2_WP = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_ALE = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_CLE = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_DQS = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_RE_B = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_READY_B = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_WE_B = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_NAND_WP_B = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXC = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXC = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0 = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXC = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI2_MCLK = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXC = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXD = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXC = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXD = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SPDIF_TX = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SPDIF_RX = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 = 124U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_I2C1_SCL = 125U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_I2C1_SDA = 126U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_I2C2_SCL = 127U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_I2C2_SDA = 128U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_I2C3_SCL = 129U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_I2C3_SDA = 130U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_I2C4_SCL = 131U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_I2C4_SDA = 132U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_UART1_RXD = 133U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_UART1_TXD = 134U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_UART2_RXD = 135U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_UART2_TXD = 136U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_UART3_RXD = 137U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_UART3_TXD = 138U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_UART4_RXD = 139U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC_SW_MUX_CTL_PAD_UART4_TXD = 140U, /**< IOMUXC SW_MUX_CTL_PAD index */ } iomuxc_sw_mux_ctl_pad_t; /*! * @addtogroup iomuxc_pads * @{ */ /******************************************************************************* * Definitions *******************************************************************************/ /*! * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD * * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections. */ typedef enum _iomuxc_sw_pad_ctl_pad { kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE2 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE3 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_JTAG_MOD = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDI = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_JTAG_TMS = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_JTAG_TCK = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDO = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ENET_MDC = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ENET_MDIO = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ENET_TD3 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ENET_TD2 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ENET_TD1 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ENET_TD0 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ENET_TX_CTL = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ENET_TXC = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ENET_RX_CTL = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ENET_RXC = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ENET_RD0 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ENET_RD1 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ENET_RD2 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ENET_RD3 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD1_CLK = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD1_CMD = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA4 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA5 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA6 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA7 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD1_STROBE = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD2_CD_B = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD2_CLK = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD2_CMD = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SD2_WP = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_ALE = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_CE2_B = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_CE3_B = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_CLE = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_DQS = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_RE_B = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_READY_B = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_WE_B = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_NAND_WP_B = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXFS = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXC = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD0 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD1 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD2 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD3 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI5_MCLK = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXFS = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXC = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXD0 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXFS = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXC = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXD0 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI2_MCLK = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXFS = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXC = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXD = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXFS = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXC = 124U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXD = 125U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SAI3_MCLK = 126U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SPDIF_TX = 127U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SPDIF_RX = 128U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_SPDIF_EXT_CLK = 129U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK = 130U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI = 131U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO = 132U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0 = 133U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK = 134U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI = 135U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO = 136U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0 = 137U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_I2C1_SCL = 138U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_I2C1_SDA = 139U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_I2C2_SCL = 140U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_I2C2_SDA = 141U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_I2C3_SCL = 142U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_I2C3_SDA = 143U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_I2C4_SCL = 144U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_I2C4_SDA = 145U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_UART1_RXD = 146U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_UART1_TXD = 147U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_UART2_RXD = 148U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_UART2_TXD = 149U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_UART3_RXD = 150U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_UART3_TXD = 151U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_UART4_RXD = 152U, /**< IOMUXC SW_PAD_CTL_PAD index */ kIOMUXC_SW_PAD_CTL_PAD_UART4_TXD = 153U, /**< IOMUXC SW_PAD_CTL_PAD index */ } iomuxc_sw_pad_ctl_pad_t; /* @} */ /*! * @brief Enumeration for the IOMUXC select input * * Defines the enumeration for the IOMUXC select input collections. */ typedef enum _iomuxc_select_input { kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 0U, /**< IOMUXC select input index */ kIOMUXC_ENET1_MDIO_SELECT_INPUT = 1U, /**< IOMUXC select input index */ kIOMUXC_SAI5_RX_BCLK_SELECT_INPUT = 5U, /**< IOMUXC select input index */ kIOMUXC_SAI5_RX_DATA0_SELECT_INPUT = 6U, /**< IOMUXC select input index */ kIOMUXC_SAI5_RX_DATA1_SELECT_INPUT = 7U, /**< IOMUXC select input index */ kIOMUXC_SAI5_RX_DATA2_SELECT_INPUT = 8U, /**< IOMUXC select input index */ kIOMUXC_SAI5_RX_DATA3_SELECT_INPUT = 9U, /**< IOMUXC select input index */ kIOMUXC_SAI5_RX_SYNC_SELECT_INPUT = 10U, /**< IOMUXC select input index */ kIOMUXC_SAI5_TX_BCLK_SELECT_INPUT = 11U, /**< IOMUXC select input index */ kIOMUXC_SAI5_TX_SYNC_SELECT_INPUT = 12U, /**< IOMUXC select input index */ kIOMUXC_UART1_RTS_B_SELECT_INPUT = 13U, /**< IOMUXC select input index */ kIOMUXC_UART1_RX_SELECT_INPUT = 14U, /**< IOMUXC select input index */ kIOMUXC_UART2_RTS_B_SELECT_INPUT = 15U, /**< IOMUXC select input index */ kIOMUXC_UART2_RX_SELECT_INPUT = 16U, /**< IOMUXC select input index */ kIOMUXC_UART3_RTS_B_SELECT_INPUT = 17U, /**< IOMUXC select input index */ kIOMUXC_UART3_RX_SELECT_INPUT = 18U, /**< IOMUXC select input index */ kIOMUXC_UART4_RTS_B_SELECT_INPUT = 19U, /**< IOMUXC select input index */ kIOMUXC_UART4_RX_SELECT_INPUT = 20U, /**< IOMUXC select input index */ kIOMUXC_PDM_BIT_STREAM0_SELECT_INPUT = 30U, /**< IOMUXC select input index */ kIOMUXC_PDM_BIT_STREAM1_SELECT_INPUT = 31U, /**< IOMUXC select input index */ kIOMUXC_PDM_BIT_STREAM2_SELECT_INPUT = 32U, /**< IOMUXC select input index */ kIOMUXC_PDM_BIT_STREAM3_SELECT_INPUT = 33U, /**< IOMUXC select input index */ kIOMUXC_USDHC3_DATA7_SELECT_INPUT = 36U, /**< IOMUXC select input index */ kIOMUXC_USDHC3_DATA5_SELECT_INPUT = 37U, /**< IOMUXC select input index */ kIOMUXC_ENET1_RGMII_RD1_SELECT_INPUT = 38U, /**< IOMUXC select input index */ kIOMUXC_USDHC3_DATA4_SELECT_INPUT = 39U, /**< IOMUXC select input index */ kIOMUXC_I2C1_SCL_SELECT_INPUT = 40U, /**< IOMUXC select input index */ kIOMUXC_I2C2_SDA_SELECT_INPUT = 41U, /**< IOMUXC select input index */ kIOMUXC_ECSPI1_SS0_SELECT_INPUT = 42U, /**< IOMUXC select input index */ kIOMUXC_SPDIF1_EXT_CLK_SELECT_INPUT = 43U, /**< IOMUXC select input index */ kIOMUXC_I2C1_SDA_SELECT_INPUT = 44U, /**< IOMUXC select input index */ kIOMUXC_ECSPI2_SS0_SELECT_INPUT = 45U, /**< IOMUXC select input index */ kIOMUXC_ENET1_RGMII_RX_CTL_SELECT_INPUT = 46U, /**< IOMUXC select input index */ kIOMUXC_ECSPI2_MISO_SELECT_INPUT = 47U, /**< IOMUXC select input index */ kIOMUXC_ENET1_RGMII_RD0_SELECT_INPUT = 48U, /**< IOMUXC select input index */ kIOMUXC_ECSPI2_SCLK_SELECT_INPUT = 49U, /**< IOMUXC select input index */ kIOMUXC_USDHC3_DATA6_SELECT_INPUT = 50U, /**< IOMUXC select input index */ kIOMUXC_I2C3_SCL_SELECT_INPUT = 51U, /**< IOMUXC select input index */ kIOMUXC_I2C4_SDA_SELECT_INPUT = 52U, /**< IOMUXC select input index */ kIOMUXC_ECSPI2_MOSI_SELECT_INPUT = 53U, /**< IOMUXC select input index */ kIOMUXC_SAI5_MCLK_SELECT_INPUT = 54U, /**< IOMUXC select input index */ kIOMUXC_USDHC3_CD_B_SELECT_INPUT = 55U, /**< IOMUXC select input index */ kIOMUXC_USDHC3_STROBE_SELECT_INPUT = 56U, /**< IOMUXC select input index */ kIOMUXC_USDHC3_CLK_SELECT_INPUT = 57U, /**< IOMUXC select input index */ kIOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT = 58U, /**< IOMUXC select input index */ kIOMUXC_ECSPI1_MOSI_SELECT_INPUT = 59U, /**< IOMUXC select input index */ kIOMUXC_SAI2_RX_DATA1_SELECT_INPUT = 60U, /**< IOMUXC select input index */ kIOMUXC_USDHC3_DATA1_SELECT_INPUT = 61U, /**< IOMUXC select input index */ kIOMUXC_USDHC3_DATA0_SELECT_INPUT = 62U, /**< IOMUXC select input index */ kIOMUXC_USDHC3_WP_SELECT_INPUT = 63U, /**< IOMUXC select input index */ kIOMUXC_I2C3_SDA_SELECT_INPUT = 64U, /**< IOMUXC select input index */ kIOMUXC_SAI3_MCLK_SELECT_INPUT = 65U, /**< IOMUXC select input index */ kIOMUXC_ECSPI1_MISO_SELECT_INPUT = 66U, /**< IOMUXC select input index */ kIOMUXC_ENET1_RX_ER_SELECT_INPUT = 67U, /**< IOMUXC select input index */ kIOMUXC_SPDIF1_IN_SELECT_INPUT = 68U, /**< IOMUXC select input index */ kIOMUXC_I2C2_SCL_SELECT_INPUT = 69U, /**< IOMUXC select input index */ kIOMUXC_I2C4_SCL_SELECT_INPUT = 70U, /**< IOMUXC select input index */ kIOMUXC_ECSPI1_SCLK_SELECT_INPUT = 71U, /**< IOMUXC select input index */ kIOMUXC_USDHC3_CMD_SELECT_INPUT = 72U, /**< IOMUXC select input index */ kIOMUXC_USDHC3_DATA3_SELECT_INPUT = 73U, /**< IOMUXC select input index */ kIOMUXC_USDHC3_DATA2_SELECT_INPUT = 74U, /**< IOMUXC select input index */ kIOMUXC_GPT1_CLK_SELECT_INPUT = 75U, /**< IOMUXC select input index */ kIOMUXC_GPT1_CAPTURE2_SELECT_INPUT = 76U, /**< IOMUXC select input index */ kIOMUXC_GPT1_CAPTURE1_SELECT_INPUT = 77U, /**< IOMUXC select input index */ } iomuxc_select_input_t; /*! * @addtogroup rdc_mapping * @{ */ /******************************************************************************* * Definitions ******************************************************************************/ /*! * @brief Structure for the RDC mapping * * Defines the structure for the RDC resource collections. */ typedef enum _rdc_master { kRDC_Master_A53 = 0U, /**< ARM Cortex-A53 RDC Master */ kRDC_Master_M7 = 1U, /**< ARM Cortex-M7 RDC Master */ kRDC_Reserved0 = 2U, /**< Reserved */ kRDC_Master_SDMA3_PERIPH = 3U, /**< SDMA3 PERIPHERAL RDC Master */ kRDC_Reserved1 = 4U, /**< Reserved */ kRDC_Master_LCDIF = 5U, /**< LCDIF RDC Master */ kRDC_Master_ISI = 6U, /**< ISI PORT RDC Master */ kRDC_Master_SDMA3_BURST = 7U, /**< SDMA3 BURST RDC Master */ kRDC_Master_Coresight = 8U, /**< CORESIGHT RDC Master */ kRDC_Master_DAP = 9U, /**< DAP RDC Master */ kRDC_Master_CAAM = 10U, /**< CAAM RDC Master */ kRDC_Master_SDMA1_PERIPH = 11U, /**< SDMA1 PERIPHERAL RDC Master */ kRDC_Master_SDMA1_BURST = 12U, /**< SDMA1 BURST RDC Master */ kRDC_Master_APBHDMA = 13U, /**< APBH DMA RDC Master */ kRDC_Master_RAWNAND = 14U, /**< RAW NAND RDC Master */ kRDC_Master_USDHC1 = 15U, /**< USDHC1 RDC Master */ kRDC_Master_USDHC2 = 16U, /**< USDHC2 RDC Master */ kRDC_Master_USDHC3 = 17U, /**< USDHC3 RDC Master */ kRDC_Master_GPU = 18U, /**< GPU RDC Master */ kRDC_Master_USB1 = 19U, /**< USB1 RDC Master */ kRDC_Reserved2 = 20U, /**< Reserved */ kRDC_Master_TESTPORT = 21U, /**< TESTPORT RDC Master */ kRDC_Master_ENET1TX = 22U, /**< ENET1 TX RDC Master */ kRDC_Master_ENET1RX = 23U, /**< ENET1 RX RDC Master */ kRDC_Master_SDMA2_PERIPH = 24U, /**< SDMA2 PERIPH RDC Master */ kRDC_Master_SDMA2_BURST = 24U, /**< SDMA2 BURST RDC Master */ kRDC_Master_SDMA2_SPBA2 = 24U, /**< SDMA2 to SPBA2 RDC Master */ kRDC_Master_SDMA3_SPBA2 = 25U, /**< SDMA3 to SPBA2 RDC Master */ kRDC_Master_SDMA1_SPBA1 = 26U, /**< SDMA1 to SPBA1 RDC Master */ } rdc_master_t; typedef enum _rdc_mem { kRDC_Mem_MRC0_0 = 0U, /**< DRAM. Region resolution 4KB. */ kRDC_Mem_MRC0_1 = 1U, kRDC_Mem_MRC0_2 = 2U, kRDC_Mem_MRC0_3 = 3U, kRDC_Mem_MRC0_4 = 4U, kRDC_Mem_MRC0_5 = 5U, kRDC_Mem_MRC0_6 = 6U, kRDC_Mem_MRC0_7 = 7U, kRDC_Mem_MRC1_0 = 8U, /**< QSPI. Region resolution 4KB. */ kRDC_Mem_MRC1_1 = 9U, kRDC_Mem_MRC1_2 = 10U, kRDC_Mem_MRC1_3 = 11U, kRDC_Mem_MRC1_4 = 12U, kRDC_Mem_MRC1_5 = 13U, kRDC_Mem_MRC1_6 = 14U, kRDC_Mem_MRC1_7 = 15U, kRDC_Mem_MRC2_0 = 16U, /**< OCRAM. Region resolution 128B. */ kRDC_Mem_MRC2_1 = 17U, kRDC_Mem_MRC2_2 = 18U, kRDC_Mem_MRC2_3 = 19U, kRDC_Mem_MRC2_4 = 20U, kRDC_Mem_MRC3_0 = 21U, /**< OCRAM_S. Region resolution 128B. */ kRDC_Mem_MRC3_1 = 22U, kRDC_Mem_MRC3_2 = 23U, kRDC_Mem_MRC3_3 = 24U, kRDC_Mem_MRC3_4 = 25U, kRDC_Mem_MRC4_0 = 26U, /**< TCM. Region resolution 128B. */ kRDC_Mem_MRC4_1 = 27U, kRDC_Mem_MRC4_2 = 28U, kRDC_Mem_MRC4_3 = 29U, kRDC_Mem_MRC4_4 = 30U, kRDC_Mem_MRC5_0 = 31U, /**< GIC. Region resolution 4KB. */ kRDC_Mem_MRC5_1 = 32U, kRDC_Mem_MRC5_2 = 33U, kRDC_Mem_MRC5_3 = 34U, kRDC_Mem_MRC6_0 = 35U, /**< GPU. Region resolution 4KB. */ kRDC_Mem_MRC6_1 = 36U, kRDC_Mem_MRC6_2 = 37U, kRDC_Mem_MRC6_3 = 38U, kRDC_Mem_MRC6_4 = 39U, kRDC_Mem_MRC6_5 = 40U, kRDC_Mem_MRC6_6 = 41U, kRDC_Mem_MRC6_7 = 42U, kRDC_Mem_MRC7_0 = 43U, /**< DEBUG(DAP). Region resolution 4KB. */ kRDC_Mem_MRC7_1 = 44U, kRDC_Mem_MRC7_2 = 45U, kRDC_Mem_MRC7_3 = 46U, kRDC_Mem_MRC8_0 = 47U, /**< DDRC(REG). Region resolution 4KB. */ kRDC_Mem_MRC8_1 = 48U, kRDC_Mem_MRC8_2 = 49U, kRDC_Mem_MRC8_3 = 50U, kRDC_Mem_MRC8_4 = 51U, } rdc_mem_t; typedef enum _rdc_periph { kRDC_Periph_GPIO1 = 0U, /**< GPIO1 RDC Peripheral */ kRDC_Periph_GPIO2 = 1U, /**< GPIO2 RDC Peripheral */ kRDC_Periph_GPIO3 = 2U, /**< GPIO3 RDC Peripheral */ kRDC_Periph_GPIO4 = 3U, /**< GPIO4 RDC Peripheral */ kRDC_Periph_GPIO5 = 4U, /**< GPIO5 RDC Peripheral */ kRDC_Periph_ANA_TSENSOR = 6U, /**< ANA_TSENSOR RDC Peripheral */ kRDC_Periph_ANA_OSC = 7U, /**< ANA_OSC RDC Peripheral */ kRDC_Periph_WDOG1 = 8U, /**< WDOG1 RDC Peripheral */ kRDC_Periph_WDOG2 = 9U, /**< WDOG2 RDC Peripheral */ kRDC_Periph_WDOG3 = 10U, /**< WDOG3 RDC Peripheral */ kRDC_Periph_SDMA3 = 11U, /**< SDMA3 RDC Peripheral */ kRDC_Periph_SDMA2 = 12U, /**< SDMA2 RDC Peripheral */ kRDC_Periph_GPT1 = 13U, /**< GPT1 RDC Peripheral */ kRDC_Periph_GPT2 = 14U, /**< GPT2 RDC Peripheral */ kRDC_Periph_GPT3 = 15U, /**< GPT3 RDC Peripheral */ kRDC_Periph_ROMCP = 17U, /**< ROMCP RDC Peripheral */ kRDC_Periph_IOMUXC = 19U, /**< IOMUXC RDC Peripheral */ kRDC_Periph_IOMUXC_GPR = 20U, /**< IOMUXC_GPR RDC Peripheral */ kRDC_Periph_OCOTP_CTRL = 21U, /**< OCOTP_CTRL RDC Peripheral */ kRDC_Periph_ANA_PLL = 22U, /**< ANA_PLL RDC Peripheral */ kRDC_Periph_SNVS_HP = 23U, /**< SNVS_HP GPR RDC Peripheral */ kRDC_Periph_CCM = 24U, /**< CCM RDC Peripheral */ kRDC_Periph_SRC = 25U, /**< SRC RDC Peripheral */ kRDC_Periph_GPC = 26U, /**< GPC RDC Peripheral */ kRDC_Periph_SEMAPHORE1 = 27U, /**< SEMAPHORE1 RDC Peripheral */ kRDC_Periph_SEMAPHORE2 = 28U, /**< SEMAPHORE2 RDC Peripheral */ kRDC_Periph_RDC = 29U, /**< RDC RDC Peripheral */ kRDC_Periph_CSU = 30U, /**< CSU RDC Peripheral */ kRDC_Periph_LCDIF = 32U, /**< LCDIF RDC Peripheral */ kRDC_Periph_MIPI_DSI = 33U, /**< MIPI_DSI RDC Peripheral */ kRDC_Periph_ISI = 34U, /**< ISI RDC Peripheral */ kRDC_Periph_MIPI_CSI = 35U, /**< MIPI_CSI RDC Peripheral */ kRDC_Periph_USB1 = 36U, /**< USB1 RDC Peripheral */ kRDC_Periph_PWM1 = 38U, /**< PWM1 RDC Peripheral */ kRDC_Periph_PWM2 = 39U, /**< PWM2 RDC Peripheral */ kRDC_Periph_PWM3 = 40U, /**< PWM3 RDC Peripheral */ kRDC_Periph_PWM4 = 41U, /**< PWM4 RDC Peripheral */ kRDC_Periph_SYS_COUNTER_RD = 42U, /**< System counter read RDC Peripheral */ kRDC_Periph_SYS_COUNTER_CMP = 43U, /**< System counter compare RDC Peripheral */ kRDC_Periph_SYS_COUNTER_CTRL = 44U, /**< System counter control RDC Peripheral */ kRDC_Periph_GPT6 = 46U, /**< GPT6 RDC Peripheral */ kRDC_Periph_GPT5 = 47U, /**< GPT5 RDC Peripheral */ kRDC_Periph_GPT4 = 48U, /**< GPT4 RDC Peripheral */ kRDC_Periph_TZASC = 56U, /**< TZASC RDC Peripheral */ kRDC_Periph_PERFMON1 = 60U, /**< PERFMON1 RDC Peripheral */ kRDC_Periph_PERFMON2 = 61U, /**< PERFMON2 RDC Peripheral */ kRDC_Periph_PLATFORM_CTRL = 62U, /**< PLATFORM_CTRL RDC Peripheral */ kRDC_Periph_QOSC = 63U, /**< QOSC RDC Peripheral */ kRDC_Periph_I2C1 = 66U, /**< I2C1 RDC Peripheral */ kRDC_Periph_I2C2 = 67U, /**< I2C2 RDC Peripheral */ kRDC_Periph_I2C3 = 68U, /**< I2C3 RDC Peripheral */ kRDC_Periph_I2C4 = 69U, /**< I2C4 RDC Peripheral */ kRDC_Periph_UART4 = 70U, /**< UART4 RDC Peripheral */ kRDC_Periph_MU_A = 74U, /**< MU_A RDC Peripheral */ kRDC_Periph_MU_B = 75U, /**< MU_B RDC Peripheral */ kRDC_Periph_SEMAPHORE_HS = 76U, /**< SEMAPHORE_HS RDC Peripheral */ kRDC_Periph_SAI2 = 79U, /**< SAI2 RDC Peripheral */ kRDC_Periph_SAI3 = 80U, /**< SAI3 RDC Peripheral */ kRDC_Periph_SAI5 = 82U, /**< SAI5 RDC Peripheral */ kRDC_Periph_SAI6 = 83U, /**< SAI6 RDC Peripheral */ kRDC_Periph_USDHC1 = 84U, /**< USDHC1 RDC Peripheral */ kRDC_Periph_USDHC2 = 85U, /**< USDHC2 RDC Peripheral */ kRDC_Periph_USDHC3 = 86U, /**< USDHC3 RDC Peripheral */ kRDC_Periph_SAI7 = 87U, /**< SAI7 RDC Peripheral */ kRDC_Periph_SPBA2 = 90U, /**< SPBA2 RDC Peripheral */ kRDC_Periph_QSPI = 91U, /**< QSPI RDC Peripheral */ kRDC_Periph_SDMA1 = 93U, /**< SDMA1 RDC Peripheral */ kRDC_Periph_ENET1 = 94U, /**< ENET1 RDC Peripheral */ kRDC_Periph_SPDIF1 = 97U, /**< SPDIF1 RDC Peripheral */ kRDC_Periph_ECSPI1 = 98U, /**< ECSPI1 RDC Peripheral */ kRDC_Periph_ECSPI2 = 99U, /**< ECSPI2 RDC Peripheral */ kRDC_Periph_ECSPI3 = 100U, /**< ECSPI3 RDC Peripheral */ kRDC_Periph_MICFIL = 101U, /**< MICFIL RDC Peripheral */ kRDC_Periph_UART1 = 102U, /**< UART1 RDC Peripheral */ kRDC_Periph_UART3 = 104U, /**< UART3 RDC Peripheral */ kRDC_Periph_UART2 = 105U, /**< UART2 RDC Peripheral */ kRDC_Periph_ASRC = 107U, /**< ASRC RDC Peripheral */ kRDC_Periph_SPBA1 = 111U, /**< SPBA1 RDC Peripheral */ kRDC_Periph_CAAM = 114U, /**< CAAM RDC Peripheral */ } rdc_periph_t; /* @} */ /*! * @} */ /* end of group Mapping_Information */ /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup Peripheral_access_layer Device Peripheral Access Layer * @{ */ /* ** Start of section using anonymous unions */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #else #pragma push #pragma anon_unions #endif #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language = extended #else #error Not supported compiler type #endif /* ---------------------------------------------------------------------------- -- AIPSTZ Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer * @{ */ /** AIPSTZ - Register Layout Typedef */ typedef struct { __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ uint8_t RESERVED_0[60]; __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */ __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */ __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */ __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */ __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */ } AIPSTZ_Type; /* ---------------------------------------------------------------------------- -- AIPSTZ Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks * @{ */ /*! @name MPR - Master Priviledge Registers */ /*! @{ */ #define AIPSTZ_MPR_MPROT5_MASK (0xF00U) #define AIPSTZ_MPR_MPROT5_SHIFT (8U) /*! MPROT5 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses. * 0bxx1x..This master is trusted for write accesses. * 0bx0xx..This master is not trusted for read accesses. * 0bx1xx..This master is trusted for read accesses. * 0b1xxx..Write accesses from this master are allowed to be buffered */ #define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) #define AIPSTZ_MPR_MPROT3_MASK (0xF0000U) #define AIPSTZ_MPR_MPROT3_SHIFT (16U) /*! MPROT3 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses. * 0bxx1x..This master is trusted for write accesses. * 0bx0xx..This master is not trusted for read accesses. * 0bx1xx..This master is trusted for read accesses. * 0b1xxx..Write accesses from this master are allowed to be buffered */ #define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) #define AIPSTZ_MPR_MPROT2_MASK (0xF00000U) #define AIPSTZ_MPR_MPROT2_SHIFT (20U) /*! MPROT2 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses. * 0bxx1x..This master is trusted for write accesses. * 0bx0xx..This master is not trusted for read accesses. * 0bx1xx..This master is trusted for read accesses. * 0b1xxx..Write accesses from this master are allowed to be buffered */ #define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) #define AIPSTZ_MPR_MPROT1_MASK (0xF000000U) #define AIPSTZ_MPR_MPROT1_SHIFT (24U) /*! MPROT1 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses. * 0bxx1x..This master is trusted for write accesses. * 0bx0xx..This master is not trusted for read accesses. * 0bx1xx..This master is trusted for read accesses. * 0b1xxx..Write accesses from this master are allowed to be buffered */ #define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) #define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) #define AIPSTZ_MPR_MPROT0_SHIFT (28U) /*! MPROT0 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses. * 0bxx1x..This master is trusted for write accesses. * 0bx0xx..This master is not trusted for read accesses. * 0bx1xx..This master is trusted for read accesses. * 0b1xxx..Write accesses from this master are allowed to be buffered */ #define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) /*! @} */ /*! @name OPACR - Off-Platform Peripheral Access Control Registers */ /*! @{ */ #define AIPSTZ_OPACR_OPAC7_MASK (0xFU) #define AIPSTZ_OPACR_OPAC7_SHIFT (0U) /*! OPAC7 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) #define AIPSTZ_OPACR_OPAC6_MASK (0xF0U) #define AIPSTZ_OPACR_OPAC6_SHIFT (4U) /*! OPAC6 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK) #define AIPSTZ_OPACR_OPAC5_MASK (0xF00U) #define AIPSTZ_OPACR_OPAC5_SHIFT (8U) /*! OPAC5 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK) #define AIPSTZ_OPACR_OPAC4_MASK (0xF000U) #define AIPSTZ_OPACR_OPAC4_SHIFT (12U) /*! OPAC4 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK) #define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U) #define AIPSTZ_OPACR_OPAC3_SHIFT (16U) /*! OPAC3 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK) #define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U) #define AIPSTZ_OPACR_OPAC2_SHIFT (20U) /*! OPAC2 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK) #define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U) #define AIPSTZ_OPACR_OPAC1_SHIFT (24U) /*! OPAC1 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK) #define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) #define AIPSTZ_OPACR_OPAC0_SHIFT (28U) /*! OPAC0 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) /*! @} */ /*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */ /*! @{ */ #define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) #define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) /*! OPAC15 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR1_OPAC15(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) #define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U) #define AIPSTZ_OPACR1_OPAC14_SHIFT (4U) /*! OPAC14 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR1_OPAC14(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK) #define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U) #define AIPSTZ_OPACR1_OPAC13_SHIFT (8U) /*! OPAC13 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR1_OPAC13(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK) #define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U) #define AIPSTZ_OPACR1_OPAC12_SHIFT (12U) /*! OPAC12 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR1_OPAC12(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK) #define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U) #define AIPSTZ_OPACR1_OPAC11_SHIFT (16U) /*! OPAC11 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR1_OPAC11(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK) #define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U) #define AIPSTZ_OPACR1_OPAC10_SHIFT (20U) /*! OPAC10 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR1_OPAC10(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK) #define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U) #define AIPSTZ_OPACR1_OPAC9_SHIFT (24U) /*! OPAC9 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK) #define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) #define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) /*! OPAC8 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) /*! @} */ /*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */ /*! @{ */ #define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) #define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) /*! OPAC23 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR2_OPAC23(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) #define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U) #define AIPSTZ_OPACR2_OPAC22_SHIFT (4U) /*! OPAC22 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR2_OPAC22(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK) #define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U) #define AIPSTZ_OPACR2_OPAC21_SHIFT (8U) /*! OPAC21 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR2_OPAC21(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK) #define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U) #define AIPSTZ_OPACR2_OPAC20_SHIFT (12U) /*! OPAC20 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR2_OPAC20(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK) #define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U) #define AIPSTZ_OPACR2_OPAC19_SHIFT (16U) /*! OPAC19 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR2_OPAC19(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK) #define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U) #define AIPSTZ_OPACR2_OPAC18_SHIFT (20U) /*! OPAC18 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR2_OPAC18(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK) #define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U) #define AIPSTZ_OPACR2_OPAC17_SHIFT (24U) /*! OPAC17 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR2_OPAC17(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK) #define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) #define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) /*! OPAC16 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR2_OPAC16(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) /*! @} */ /*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */ /*! @{ */ #define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) #define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) /*! OPAC31 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR3_OPAC31(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) #define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U) #define AIPSTZ_OPACR3_OPAC30_SHIFT (4U) /*! OPAC30 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR3_OPAC30(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK) #define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U) #define AIPSTZ_OPACR3_OPAC29_SHIFT (8U) /*! OPAC29 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR3_OPAC29(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK) #define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U) #define AIPSTZ_OPACR3_OPAC28_SHIFT (12U) /*! OPAC28 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR3_OPAC28(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK) #define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U) #define AIPSTZ_OPACR3_OPAC27_SHIFT (16U) /*! OPAC27 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR3_OPAC27(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK) #define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U) #define AIPSTZ_OPACR3_OPAC26_SHIFT (20U) /*! OPAC26 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR3_OPAC26(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK) #define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U) #define AIPSTZ_OPACR3_OPAC25_SHIFT (24U) /*! OPAC25 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR3_OPAC25(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK) #define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) #define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) /*! OPAC24 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR3_OPAC24(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) /*! @} */ /*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */ /*! @{ */ #define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) #define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) /*! OPAC33 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR4_OPAC33(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) #define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) #define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) /*! OPAC32 * 0bxxx0..Accesses from an untrusted master are allowed. * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. * 0bxx0x..This peripheral allows write accesses. * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an * error response and no peripheral access is initiated on the IPS bus. * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must * be set. If not, the access is terminated with an error response and no peripheral access is initiated * on the IPS bus. * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. */ #define AIPSTZ_OPACR4_OPAC32(x) \ (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) /*! @} */ /*! * @} */ /* end of group AIPSTZ_Register_Masks */ /* AIPSTZ - Peripheral instance base addresses */ /** Peripheral AIPSTZ base address */ #define AIPSTZ_BASE (0x301F0000u) /** Peripheral AIPSTZ base pointer */ #define AIPSTZ ((AIPSTZ_Type *)AIPSTZ_BASE) /** Array initializer of AIPSTZ peripheral base addresses */ #define AIPSTZ_BASE_ADDRS \ { \ AIPSTZ_BASE \ } /** Array initializer of AIPSTZ peripheral base pointers */ #define AIPSTZ_BASE_PTRS \ { \ AIPSTZ \ } /*! * @} */ /* end of group AIPSTZ_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- APBH Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer * @{ */ /** APBH - Register Layout Typedef */ typedef struct { __IO uint32_t CTRL0; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */ __IO uint32_t CTRL0_SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */ __IO uint32_t CTRL0_CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */ __IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */ __IO uint32_t CTRL1; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */ __IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */ __IO uint32_t CTRL1_CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */ __IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */ __IO uint32_t CTRL2; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */ __IO uint32_t CTRL2_SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */ __IO uint32_t CTRL2_CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */ __IO uint32_t CTRL2_TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */ __IO uint32_t CHANNEL_CTRL; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */ __IO uint32_t CHANNEL_CTRL_SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */ __IO uint32_t CHANNEL_CTRL_CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */ __IO uint32_t CHANNEL_CTRL_TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */ __I uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */ uint8_t RESERVED_0[12]; __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */ uint8_t RESERVED_1[12]; __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */ uint8_t RESERVED_2[156]; struct { /* offset: 0x100, array step: 0x70 */ __I uint32_t CH_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, array offset: 0x100, array step: 0x70 */ uint8_t RESERVED_0[12]; __IO uint32_t CH_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, array offset: 0x110, array step: 0x70 */ uint8_t RESERVED_1[12]; __I uint32_t CH_CMD; /**< APBH DMA Channel n Command Register, array offset: 0x120, array step: 0x70 */ uint8_t RESERVED_2[12]; __I uint32_t CH_BAR; /**< APBH DMA Channel n Buffer Address Register, array offset: 0x130, array step: 0x70 */ uint8_t RESERVED_3[12]; __IO uint32_t CH_SEMA; /**< APBH DMA Channel n Semaphore Register, array offset: 0x140, array step: 0x70 */ uint8_t RESERVED_4[12]; __I uint32_t CH_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x150, array step: 0x70 */ uint8_t RESERVED_5[12]; __I uint32_t CH_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */ uint8_t RESERVED_6[12]; } CH_CFGn[16]; __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */ } APBH_Type; /* ---------------------------------------------------------------------------- -- APBH Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup APBH_Register_Masks APBH Register Masks * @{ */ /*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */ /*! @{ */ #define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU) #define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U) /*! CLKGATE_CHANNEL * 0b0000000000000001..NAND0 * 0b0000000000000010..NAND1 * 0b0000000000000100..NAND2 * 0b0000000000001000..NAND3 * 0b0000000000010000..NAND4 * 0b0000000000100000..NAND5 * 0b0000000001000000..NAND6 * 0b0000000010000000..NAND7 * 0b0000000100000000..SSP */ #define APBH_CTRL0_CLKGATE_CHANNEL(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK) #define APBH_CTRL0_RSVD0_MASK (0xFFF0000U) #define APBH_CTRL0_RSVD0_SHIFT (16U) #define APBH_CTRL0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_RSVD0_SHIFT)) & APBH_CTRL0_RSVD0_MASK) #define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U) #define APBH_CTRL0_APB_BURST_EN_SHIFT (28U) #define APBH_CTRL0_APB_BURST_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK) #define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U) #define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U) #define APBH_CTRL0_AHB_BURST8_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK) #define APBH_CTRL0_CLKGATE_MASK (0x40000000U) #define APBH_CTRL0_CLKGATE_SHIFT (30U) #define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK) #define APBH_CTRL0_SFTRST_MASK (0x80000000U) #define APBH_CTRL0_SFTRST_SHIFT (31U) #define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK) /*! @} */ /*! @name CTRL0_SET - AHB to APBH Bridge Control and Status Register 0 */ /*! @{ */ #define APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK (0xFFFFU) #define APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT (0U) /*! CLKGATE_CHANNEL * 0b0000000000000001..NAND0 * 0b0000000000000010..NAND1 * 0b0000000000000100..NAND2 * 0b0000000000001000..NAND3 * 0b0000000000010000..NAND4 * 0b0000000000100000..NAND5 * 0b0000000001000000..NAND6 * 0b0000000010000000..NAND7 * 0b0000000100000000..SSP */ #define APBH_CTRL0_SET_CLKGATE_CHANNEL(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK) #define APBH_CTRL0_SET_RSVD0_MASK (0xFFF0000U) #define APBH_CTRL0_SET_RSVD0_SHIFT (16U) #define APBH_CTRL0_SET_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_RSVD0_SHIFT)) & APBH_CTRL0_SET_RSVD0_MASK) #define APBH_CTRL0_SET_APB_BURST_EN_MASK (0x10000000U) #define APBH_CTRL0_SET_APB_BURST_EN_SHIFT (28U) #define APBH_CTRL0_SET_APB_BURST_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_APB_BURST_EN_SHIFT)) & APBH_CTRL0_SET_APB_BURST_EN_MASK) #define APBH_CTRL0_SET_AHB_BURST8_EN_MASK (0x20000000U) #define APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT (29U) #define APBH_CTRL0_SET_AHB_BURST8_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_SET_AHB_BURST8_EN_MASK) #define APBH_CTRL0_SET_CLKGATE_MASK (0x40000000U) #define APBH_CTRL0_SET_CLKGATE_SHIFT (30U) #define APBH_CTRL0_SET_CLKGATE(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_SHIFT)) & APBH_CTRL0_SET_CLKGATE_MASK) #define APBH_CTRL0_SET_SFTRST_MASK (0x80000000U) #define APBH_CTRL0_SET_SFTRST_SHIFT (31U) #define APBH_CTRL0_SET_SFTRST(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_SFTRST_SHIFT)) & APBH_CTRL0_SET_SFTRST_MASK) /*! @} */ /*! @name CTRL0_CLR - AHB to APBH Bridge Control and Status Register 0 */ /*! @{ */ #define APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK (0xFFFFU) #define APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT (0U) /*! CLKGATE_CHANNEL * 0b0000000000000001..NAND0 * 0b0000000000000010..NAND1 * 0b0000000000000100..NAND2 * 0b0000000000001000..NAND3 * 0b0000000000010000..NAND4 * 0b0000000000100000..NAND5 * 0b0000000001000000..NAND6 * 0b0000000010000000..NAND7 * 0b0000000100000000..SSP */ #define APBH_CTRL0_CLR_CLKGATE_CHANNEL(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK) #define APBH_CTRL0_CLR_RSVD0_MASK (0xFFF0000U) #define APBH_CTRL0_CLR_RSVD0_SHIFT (16U) #define APBH_CTRL0_CLR_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_RSVD0_SHIFT)) & APBH_CTRL0_CLR_RSVD0_MASK) #define APBH_CTRL0_CLR_APB_BURST_EN_MASK (0x10000000U) #define APBH_CTRL0_CLR_APB_BURST_EN_SHIFT (28U) #define APBH_CTRL0_CLR_APB_BURST_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_APB_BURST_EN_SHIFT)) & APBH_CTRL0_CLR_APB_BURST_EN_MASK) #define APBH_CTRL0_CLR_AHB_BURST8_EN_MASK (0x20000000U) #define APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT (29U) #define APBH_CTRL0_CLR_AHB_BURST8_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_CLR_AHB_BURST8_EN_MASK) #define APBH_CTRL0_CLR_CLKGATE_MASK (0x40000000U) #define APBH_CTRL0_CLR_CLKGATE_SHIFT (30U) #define APBH_CTRL0_CLR_CLKGATE(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_MASK) #define APBH_CTRL0_CLR_SFTRST_MASK (0x80000000U) #define APBH_CTRL0_CLR_SFTRST_SHIFT (31U) #define APBH_CTRL0_CLR_SFTRST(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_SFTRST_SHIFT)) & APBH_CTRL0_CLR_SFTRST_MASK) /*! @} */ /*! @name CTRL0_TOG - AHB to APBH Bridge Control and Status Register 0 */ /*! @{ */ #define APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK (0xFFFFU) #define APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT (0U) /*! CLKGATE_CHANNEL * 0b0000000000000001..NAND0 * 0b0000000000000010..NAND1 * 0b0000000000000100..NAND2 * 0b0000000000001000..NAND3 * 0b0000000000010000..NAND4 * 0b0000000000100000..NAND5 * 0b0000000001000000..NAND6 * 0b0000000010000000..NAND7 * 0b0000000100000000..SSP */ #define APBH_CTRL0_TOG_CLKGATE_CHANNEL(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK) #define APBH_CTRL0_TOG_RSVD0_MASK (0xFFF0000U) #define APBH_CTRL0_TOG_RSVD0_SHIFT (16U) #define APBH_CTRL0_TOG_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_RSVD0_SHIFT)) & APBH_CTRL0_TOG_RSVD0_MASK) #define APBH_CTRL0_TOG_APB_BURST_EN_MASK (0x10000000U) #define APBH_CTRL0_TOG_APB_BURST_EN_SHIFT (28U) #define APBH_CTRL0_TOG_APB_BURST_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_APB_BURST_EN_SHIFT)) & APBH_CTRL0_TOG_APB_BURST_EN_MASK) #define APBH_CTRL0_TOG_AHB_BURST8_EN_MASK (0x20000000U) #define APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT (29U) #define APBH_CTRL0_TOG_AHB_BURST8_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_TOG_AHB_BURST8_EN_MASK) #define APBH_CTRL0_TOG_CLKGATE_MASK (0x40000000U) #define APBH_CTRL0_TOG_CLKGATE_SHIFT (30U) #define APBH_CTRL0_TOG_CLKGATE(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_MASK) #define APBH_CTRL0_TOG_SFTRST_MASK (0x80000000U) #define APBH_CTRL0_TOG_SFTRST_SHIFT (31U) #define APBH_CTRL0_TOG_SFTRST(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_SFTRST_SHIFT)) & APBH_CTRL0_TOG_SFTRST_MASK) /*! @} */ /*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */ /*! @{ */ #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U) #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U) #define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U) #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U) #define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U) #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U) #define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U) #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U) #define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U) #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U) #define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U) #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U) #define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U) #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U) #define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U) #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U) #define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U) #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U) #define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U) #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U) #define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U) #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U) #define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U) #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U) #define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U) #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U) #define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U) #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U) #define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U) #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U) #define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U) #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U) #define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK) /*! @} */ /*! @name CTRL1_SET - AHB to APBH Bridge Control and Status Register 1 */ /*! @{ */ #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK (0x1U) #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT (0U) #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK (0x2U) #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT (1U) #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK (0x4U) #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT (2U) #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK (0x8U) #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT (3U) #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK (0x10U) #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT (4U) #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK (0x20U) #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT (5U) #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK (0x40U) #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT (6U) #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK (0x80U) #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT (7U) #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK (0x100U) #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT (8U) #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK (0x200U) #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT (9U) #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK (0x400U) #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT (10U) #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK (0x800U) #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT (11U) #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK (0x1000U) #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT (12U) #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK (0x2000U) #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT (13U) #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK (0x4000U) #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT (14U) #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK (0x8000U) #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT (15U) #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK) /*! @} */ /*! @name CTRL1_CLR - AHB to APBH Bridge Control and Status Register 1 */ /*! @{ */ #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK (0x1U) #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT (0U) #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK (0x2U) #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT (1U) #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK (0x4U) #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT (2U) #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK (0x8U) #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT (3U) #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK (0x10U) #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT (4U) #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK (0x20U) #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT (5U) #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK (0x40U) #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT (6U) #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK (0x80U) #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT (7U) #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK (0x100U) #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT (8U) #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK (0x200U) #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT (9U) #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK (0x400U) #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT (10U) #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK (0x800U) #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT (11U) #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK (0x1000U) #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT (12U) #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK (0x2000U) #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT (13U) #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK (0x4000U) #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT (14U) #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK (0x8000U) #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT (15U) #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK) /*! @} */ /*! @name CTRL1_TOG - AHB to APBH Bridge Control and Status Register 1 */ /*! @{ */ #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK (0x1U) #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT (0U) #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK (0x2U) #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT (1U) #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK (0x4U) #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT (2U) #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK (0x8U) #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT (3U) #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK (0x10U) #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT (4U) #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK (0x20U) #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT (5U) #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK (0x40U) #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT (6U) #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK (0x80U) #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT (7U) #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK (0x100U) #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT (8U) #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK (0x200U) #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT (9U) #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK (0x400U) #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT (10U) #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK (0x800U) #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT (11U) #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK (0x1000U) #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT (12U) #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK (0x2000U) #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT (13U) #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK (0x4000U) #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT (14U) #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK (0x8000U) #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT (15U) #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & \ APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK) /*! @} */ /*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */ /*! @{ */ #define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U) #define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U) #define APBH_CTRL2_CH0_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK) #define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U) #define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U) #define APBH_CTRL2_CH1_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK) #define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U) #define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U) #define APBH_CTRL2_CH2_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK) #define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U) #define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U) #define APBH_CTRL2_CH3_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK) #define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U) #define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U) #define APBH_CTRL2_CH4_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK) #define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U) #define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U) #define APBH_CTRL2_CH5_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK) #define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U) #define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U) #define APBH_CTRL2_CH6_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK) #define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U) #define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U) #define APBH_CTRL2_CH7_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK) #define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U) #define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U) #define APBH_CTRL2_CH8_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK) #define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U) #define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U) #define APBH_CTRL2_CH9_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK) #define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U) #define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U) #define APBH_CTRL2_CH10_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK) #define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U) #define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U) #define APBH_CTRL2_CH11_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK) #define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U) #define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U) #define APBH_CTRL2_CH12_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK) #define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U) #define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U) #define APBH_CTRL2_CH13_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK) #define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U) #define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U) #define APBH_CTRL2_CH14_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK) #define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U) #define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U) #define APBH_CTRL2_CH15_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK) #define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U) #define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U) /*! CH0_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH0_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK) #define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U) #define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U) /*! CH1_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH1_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK) #define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U) #define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U) /*! CH2_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH2_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK) #define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U) #define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U) /*! CH3_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH3_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK) #define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U) #define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U) /*! CH4_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH4_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK) #define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U) #define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U) /*! CH5_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH5_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK) #define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U) #define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U) /*! CH6_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH6_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK) #define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U) #define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U) /*! CH7_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH7_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK) #define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U) #define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U) /*! CH8_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH8_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK) #define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U) #define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U) /*! CH9_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH9_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK) #define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U) #define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U) /*! CH10_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH10_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK) #define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U) #define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U) /*! CH11_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH11_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK) #define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U) #define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U) /*! CH12_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH12_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK) #define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U) #define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U) /*! CH13_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH13_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK) #define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U) #define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U) /*! CH14_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH14_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK) #define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U) #define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U) /*! CH15_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH15_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK) /*! @} */ /*! @name CTRL2_SET - AHB to APBH Bridge Control and Status Register 2 */ /*! @{ */ #define APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK (0x1U) #define APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT (0U) #define APBH_CTRL2_SET_CH0_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK) #define APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK (0x2U) #define APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT (1U) #define APBH_CTRL2_SET_CH1_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK) #define APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK (0x4U) #define APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT (2U) #define APBH_CTRL2_SET_CH2_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK) #define APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK (0x8U) #define APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT (3U) #define APBH_CTRL2_SET_CH3_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK) #define APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK (0x10U) #define APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT (4U) #define APBH_CTRL2_SET_CH4_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK) #define APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK (0x20U) #define APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT (5U) #define APBH_CTRL2_SET_CH5_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK) #define APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK (0x40U) #define APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT (6U) #define APBH_CTRL2_SET_CH6_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK) #define APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK (0x80U) #define APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT (7U) #define APBH_CTRL2_SET_CH7_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK) #define APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK (0x100U) #define APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT (8U) #define APBH_CTRL2_SET_CH8_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK) #define APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK (0x200U) #define APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT (9U) #define APBH_CTRL2_SET_CH9_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK) #define APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK (0x400U) #define APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT (10U) #define APBH_CTRL2_SET_CH10_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK) #define APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK (0x800U) #define APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT (11U) #define APBH_CTRL2_SET_CH11_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK) #define APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK (0x1000U) #define APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT (12U) #define APBH_CTRL2_SET_CH12_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK) #define APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK (0x2000U) #define APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT (13U) #define APBH_CTRL2_SET_CH13_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK) #define APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK (0x4000U) #define APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT (14U) #define APBH_CTRL2_SET_CH14_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK) #define APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK (0x8000U) #define APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT (15U) #define APBH_CTRL2_SET_CH15_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK) #define APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK (0x10000U) #define APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT (16U) /*! CH0_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_SET_CH0_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK) #define APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK (0x20000U) #define APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT (17U) /*! CH1_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_SET_CH1_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK) #define APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK (0x40000U) #define APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT (18U) /*! CH2_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_SET_CH2_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK) #define APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK (0x80000U) #define APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT (19U) /*! CH3_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_SET_CH3_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK) #define APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK (0x100000U) #define APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT (20U) /*! CH4_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_SET_CH4_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK) #define APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK (0x200000U) #define APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT (21U) /*! CH5_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_SET_CH5_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK) #define APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK (0x400000U) #define APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT (22U) /*! CH6_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_SET_CH6_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK) #define APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK (0x800000U) #define APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT (23U) /*! CH7_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_SET_CH7_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK) #define APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK (0x1000000U) #define APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT (24U) /*! CH8_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_SET_CH8_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK) #define APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK (0x2000000U) #define APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT (25U) /*! CH9_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_SET_CH9_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK) #define APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK (0x4000000U) #define APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT (26U) /*! CH10_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_SET_CH10_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK) #define APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK (0x8000000U) #define APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT (27U) /*! CH11_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_SET_CH11_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK) #define APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK (0x10000000U) #define APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT (28U) /*! CH12_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_SET_CH12_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK) #define APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK (0x20000000U) #define APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT (29U) /*! CH13_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_SET_CH13_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK) #define APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK (0x40000000U) #define APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT (30U) /*! CH14_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_SET_CH14_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK) #define APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK (0x80000000U) #define APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT (31U) /*! CH15_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_SET_CH15_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK) /*! @} */ /*! @name CTRL2_CLR - AHB to APBH Bridge Control and Status Register 2 */ /*! @{ */ #define APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK (0x1U) #define APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT (0U) #define APBH_CTRL2_CLR_CH0_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK) #define APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK (0x2U) #define APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT (1U) #define APBH_CTRL2_CLR_CH1_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK) #define APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK (0x4U) #define APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT (2U) #define APBH_CTRL2_CLR_CH2_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK) #define APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK (0x8U) #define APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT (3U) #define APBH_CTRL2_CLR_CH3_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK) #define APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK (0x10U) #define APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT (4U) #define APBH_CTRL2_CLR_CH4_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK) #define APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK (0x20U) #define APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT (5U) #define APBH_CTRL2_CLR_CH5_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK) #define APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK (0x40U) #define APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT (6U) #define APBH_CTRL2_CLR_CH6_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK) #define APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK (0x80U) #define APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT (7U) #define APBH_CTRL2_CLR_CH7_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK) #define APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK (0x100U) #define APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT (8U) #define APBH_CTRL2_CLR_CH8_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK) #define APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK (0x200U) #define APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT (9U) #define APBH_CTRL2_CLR_CH9_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK) #define APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK (0x400U) #define APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT (10U) #define APBH_CTRL2_CLR_CH10_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK) #define APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK (0x800U) #define APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT (11U) #define APBH_CTRL2_CLR_CH11_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK) #define APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK (0x1000U) #define APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT (12U) #define APBH_CTRL2_CLR_CH12_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK) #define APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK (0x2000U) #define APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT (13U) #define APBH_CTRL2_CLR_CH13_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK) #define APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK (0x4000U) #define APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT (14U) #define APBH_CTRL2_CLR_CH14_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK) #define APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK (0x8000U) #define APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT (15U) #define APBH_CTRL2_CLR_CH15_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK) #define APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK (0x10000U) #define APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT (16U) /*! CH0_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CLR_CH0_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK) #define APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK (0x20000U) #define APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT (17U) /*! CH1_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CLR_CH1_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK) #define APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK (0x40000U) #define APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT (18U) /*! CH2_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CLR_CH2_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK) #define APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK (0x80000U) #define APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT (19U) /*! CH3_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CLR_CH3_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK) #define APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK (0x100000U) #define APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT (20U) /*! CH4_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CLR_CH4_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK) #define APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK (0x200000U) #define APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT (21U) /*! CH5_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CLR_CH5_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK) #define APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK (0x400000U) #define APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT (22U) /*! CH6_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CLR_CH6_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK) #define APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK (0x800000U) #define APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT (23U) /*! CH7_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CLR_CH7_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK) #define APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK (0x1000000U) #define APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT (24U) /*! CH8_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CLR_CH8_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK) #define APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK (0x2000000U) #define APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT (25U) /*! CH9_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CLR_CH9_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK) #define APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK (0x4000000U) #define APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT (26U) /*! CH10_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CLR_CH10_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK) #define APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK (0x8000000U) #define APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT (27U) /*! CH11_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CLR_CH11_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK) #define APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK (0x10000000U) #define APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT (28U) /*! CH12_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CLR_CH12_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK) #define APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK (0x20000000U) #define APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT (29U) /*! CH13_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CLR_CH13_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK) #define APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK (0x40000000U) #define APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT (30U) /*! CH14_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CLR_CH14_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK) #define APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK (0x80000000U) #define APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT (31U) /*! CH15_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CLR_CH15_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK) /*! @} */ /*! @name CTRL2_TOG - AHB to APBH Bridge Control and Status Register 2 */ /*! @{ */ #define APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK (0x1U) #define APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT (0U) #define APBH_CTRL2_TOG_CH0_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK) #define APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK (0x2U) #define APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT (1U) #define APBH_CTRL2_TOG_CH1_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK) #define APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK (0x4U) #define APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT (2U) #define APBH_CTRL2_TOG_CH2_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK) #define APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK (0x8U) #define APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT (3U) #define APBH_CTRL2_TOG_CH3_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK) #define APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK (0x10U) #define APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT (4U) #define APBH_CTRL2_TOG_CH4_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK) #define APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK (0x20U) #define APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT (5U) #define APBH_CTRL2_TOG_CH5_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK) #define APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK (0x40U) #define APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT (6U) #define APBH_CTRL2_TOG_CH6_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK) #define APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK (0x80U) #define APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT (7U) #define APBH_CTRL2_TOG_CH7_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK) #define APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK (0x100U) #define APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT (8U) #define APBH_CTRL2_TOG_CH8_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK) #define APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK (0x200U) #define APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT (9U) #define APBH_CTRL2_TOG_CH9_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK) #define APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK (0x400U) #define APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT (10U) #define APBH_CTRL2_TOG_CH10_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK) #define APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK (0x800U) #define APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT (11U) #define APBH_CTRL2_TOG_CH11_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK) #define APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK (0x1000U) #define APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT (12U) #define APBH_CTRL2_TOG_CH12_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK) #define APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK (0x2000U) #define APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT (13U) #define APBH_CTRL2_TOG_CH13_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK) #define APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK (0x4000U) #define APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT (14U) #define APBH_CTRL2_TOG_CH14_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK) #define APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK (0x8000U) #define APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT (15U) #define APBH_CTRL2_TOG_CH15_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK) #define APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK (0x10000U) #define APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT (16U) /*! CH0_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_TOG_CH0_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK) #define APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK (0x20000U) #define APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT (17U) /*! CH1_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_TOG_CH1_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK) #define APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK (0x40000U) #define APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT (18U) /*! CH2_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_TOG_CH2_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK) #define APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK (0x80000U) #define APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT (19U) /*! CH3_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_TOG_CH3_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK) #define APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK (0x100000U) #define APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT (20U) /*! CH4_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_TOG_CH4_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK) #define APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK (0x200000U) #define APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT (21U) /*! CH5_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_TOG_CH5_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK) #define APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK (0x400000U) #define APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT (22U) /*! CH6_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_TOG_CH6_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK) #define APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK (0x800000U) #define APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT (23U) /*! CH7_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_TOG_CH7_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK) #define APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK (0x1000000U) #define APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT (24U) /*! CH8_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_TOG_CH8_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK) #define APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK (0x2000000U) #define APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT (25U) /*! CH9_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_TOG_CH9_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK) #define APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK (0x4000000U) #define APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT (26U) /*! CH10_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_TOG_CH10_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK) #define APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK (0x8000000U) #define APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT (27U) /*! CH11_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_TOG_CH11_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK) #define APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK (0x10000000U) #define APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT (28U) /*! CH12_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_TOG_CH12_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK) #define APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK (0x20000000U) #define APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT (29U) /*! CH13_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_TOG_CH13_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK) #define APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK (0x40000000U) #define APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT (30U) /*! CH14_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_TOG_CH14_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK) #define APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK (0x80000000U) #define APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT (31U) /*! CH15_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_TOG_CH15_ERROR_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK) /*! @} */ /*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */ /*! @{ */ #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU) #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U) /*! FREEZE_CHANNEL * 0b0000000000000001..NAND0 * 0b0000000000000010..NAND1 * 0b0000000000000100..NAND2 * 0b0000000000001000..NAND3 * 0b0000000000010000..NAND4 * 0b0000000000100000..NAND5 * 0b0000000001000000..NAND6 * 0b0000000010000000..NAND7 * 0b0000000100000000..SSP */ #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK) #define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U) #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U) /*! RESET_CHANNEL * 0b0000000000000001..NAND0 * 0b0000000000000010..NAND1 * 0b0000000000000100..NAND2 * 0b0000000000001000..NAND3 * 0b0000000000010000..NAND4 * 0b0000000000100000..NAND5 * 0b0000000001000000..NAND6 * 0b0000000010000000..NAND7 * 0b0000000100000000..SSP */ #define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK) /*! @} */ /*! @name CHANNEL_CTRL_SET - AHB to APBH Bridge Channel Register */ /*! @{ */ #define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK (0xFFFFU) #define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT (0U) /*! FREEZE_CHANNEL * 0b0000000000000001..NAND0 * 0b0000000000000010..NAND1 * 0b0000000000000100..NAND2 * 0b0000000000001000..NAND3 * 0b0000000000010000..NAND4 * 0b0000000000100000..NAND5 * 0b0000000001000000..NAND6 * 0b0000000010000000..NAND7 * 0b0000000100000000..SSP */ #define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT)) & \ APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK) #define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK (0xFFFF0000U) #define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT (16U) /*! RESET_CHANNEL * 0b0000000000000001..NAND0 * 0b0000000000000010..NAND1 * 0b0000000000000100..NAND2 * 0b0000000000001000..NAND3 * 0b0000000000010000..NAND4 * 0b0000000000100000..NAND5 * 0b0000000001000000..NAND6 * 0b0000000010000000..NAND7 * 0b0000000100000000..SSP */ #define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT)) & \ APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK) /*! @} */ /*! @name CHANNEL_CTRL_CLR - AHB to APBH Bridge Channel Register */ /*! @{ */ #define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK (0xFFFFU) #define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT (0U) /*! FREEZE_CHANNEL * 0b0000000000000001..NAND0 * 0b0000000000000010..NAND1 * 0b0000000000000100..NAND2 * 0b0000000000001000..NAND3 * 0b0000000000010000..NAND4 * 0b0000000000100000..NAND5 * 0b0000000001000000..NAND6 * 0b0000000010000000..NAND7 * 0b0000000100000000..SSP */ #define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT)) & \ APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK) #define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK (0xFFFF0000U) #define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT (16U) /*! RESET_CHANNEL * 0b0000000000000001..NAND0 * 0b0000000000000010..NAND1 * 0b0000000000000100..NAND2 * 0b0000000000001000..NAND3 * 0b0000000000010000..NAND4 * 0b0000000000100000..NAND5 * 0b0000000001000000..NAND6 * 0b0000000010000000..NAND7 * 0b0000000100000000..SSP */ #define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT)) & \ APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK) /*! @} */ /*! @name CHANNEL_CTRL_TOG - AHB to APBH Bridge Channel Register */ /*! @{ */ #define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK (0xFFFFU) #define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT (0U) /*! FREEZE_CHANNEL * 0b0000000000000001..NAND0 * 0b0000000000000010..NAND1 * 0b0000000000000100..NAND2 * 0b0000000000001000..NAND3 * 0b0000000000010000..NAND4 * 0b0000000000100000..NAND5 * 0b0000000001000000..NAND6 * 0b0000000010000000..NAND7 * 0b0000000100000000..SSP */ #define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT)) & \ APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK) #define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK (0xFFFF0000U) #define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT (16U) /*! RESET_CHANNEL * 0b0000000000000001..NAND0 * 0b0000000000000010..NAND1 * 0b0000000000000100..NAND2 * 0b0000000000001000..NAND3 * 0b0000000000010000..NAND4 * 0b0000000000100000..NAND5 * 0b0000000001000000..NAND6 * 0b0000000010000000..NAND7 * 0b0000000100000000..SSP */ #define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT)) & \ APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK) /*! @} */ /*! @name DEVSEL - AHB to APBH DMA Device Assignment Register */ /*! @{ */ #define APBH_DEVSEL_CH0_MASK (0x3U) #define APBH_DEVSEL_CH0_SHIFT (0U) #define APBH_DEVSEL_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH0_SHIFT)) & APBH_DEVSEL_CH0_MASK) #define APBH_DEVSEL_CH1_MASK (0xCU) #define APBH_DEVSEL_CH1_SHIFT (2U) #define APBH_DEVSEL_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH1_SHIFT)) & APBH_DEVSEL_CH1_MASK) #define APBH_DEVSEL_CH2_MASK (0x30U) #define APBH_DEVSEL_CH2_SHIFT (4U) #define APBH_DEVSEL_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH2_SHIFT)) & APBH_DEVSEL_CH2_MASK) #define APBH_DEVSEL_CH3_MASK (0xC0U) #define APBH_DEVSEL_CH3_SHIFT (6U) #define APBH_DEVSEL_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH3_SHIFT)) & APBH_DEVSEL_CH3_MASK) #define APBH_DEVSEL_CH4_MASK (0x300U) #define APBH_DEVSEL_CH4_SHIFT (8U) #define APBH_DEVSEL_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH4_SHIFT)) & APBH_DEVSEL_CH4_MASK) #define APBH_DEVSEL_CH5_MASK (0xC00U) #define APBH_DEVSEL_CH5_SHIFT (10U) #define APBH_DEVSEL_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH5_SHIFT)) & APBH_DEVSEL_CH5_MASK) #define APBH_DEVSEL_CH6_MASK (0x3000U) #define APBH_DEVSEL_CH6_SHIFT (12U) #define APBH_DEVSEL_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH6_SHIFT)) & APBH_DEVSEL_CH6_MASK) #define APBH_DEVSEL_CH7_MASK (0xC000U) #define APBH_DEVSEL_CH7_SHIFT (14U) #define APBH_DEVSEL_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH7_SHIFT)) & APBH_DEVSEL_CH7_MASK) #define APBH_DEVSEL_CH8_MASK (0x30000U) #define APBH_DEVSEL_CH8_SHIFT (16U) #define APBH_DEVSEL_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH8_SHIFT)) & APBH_DEVSEL_CH8_MASK) #define APBH_DEVSEL_CH9_MASK (0xC0000U) #define APBH_DEVSEL_CH9_SHIFT (18U) #define APBH_DEVSEL_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH9_SHIFT)) & APBH_DEVSEL_CH9_MASK) #define APBH_DEVSEL_CH10_MASK (0x300000U) #define APBH_DEVSEL_CH10_SHIFT (20U) #define APBH_DEVSEL_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH10_SHIFT)) & APBH_DEVSEL_CH10_MASK) #define APBH_DEVSEL_CH11_MASK (0xC00000U) #define APBH_DEVSEL_CH11_SHIFT (22U) #define APBH_DEVSEL_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH11_SHIFT)) & APBH_DEVSEL_CH11_MASK) #define APBH_DEVSEL_CH12_MASK (0x3000000U) #define APBH_DEVSEL_CH12_SHIFT (24U) #define APBH_DEVSEL_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH12_SHIFT)) & APBH_DEVSEL_CH12_MASK) #define APBH_DEVSEL_CH13_MASK (0xC000000U) #define APBH_DEVSEL_CH13_SHIFT (26U) #define APBH_DEVSEL_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH13_SHIFT)) & APBH_DEVSEL_CH13_MASK) #define APBH_DEVSEL_CH14_MASK (0x30000000U) #define APBH_DEVSEL_CH14_SHIFT (28U) #define APBH_DEVSEL_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH14_SHIFT)) & APBH_DEVSEL_CH14_MASK) #define APBH_DEVSEL_CH15_MASK (0xC0000000U) #define APBH_DEVSEL_CH15_SHIFT (30U) #define APBH_DEVSEL_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH15_SHIFT)) & APBH_DEVSEL_CH15_MASK) /*! @} */ /*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */ /*! @{ */ #define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U) #define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U) #define APBH_DMA_BURST_SIZE_CH0(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK) #define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU) #define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U) #define APBH_DMA_BURST_SIZE_CH1(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK) #define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U) #define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U) #define APBH_DMA_BURST_SIZE_CH2(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK) #define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U) #define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U) #define APBH_DMA_BURST_SIZE_CH3(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK) #define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U) #define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U) #define APBH_DMA_BURST_SIZE_CH4(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK) #define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U) #define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U) #define APBH_DMA_BURST_SIZE_CH5(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK) #define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U) #define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U) #define APBH_DMA_BURST_SIZE_CH6(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK) #define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U) #define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U) #define APBH_DMA_BURST_SIZE_CH7(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK) #define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U) #define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U) /*! CH8 * 0b00..BURST0 * 0b01..BURST4 * 0b10..BURST8 */ #define APBH_DMA_BURST_SIZE_CH8(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK) #define APBH_DMA_BURST_SIZE_CH9_MASK (0xC0000U) #define APBH_DMA_BURST_SIZE_CH9_SHIFT (18U) #define APBH_DMA_BURST_SIZE_CH9(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH9_SHIFT)) & APBH_DMA_BURST_SIZE_CH9_MASK) #define APBH_DMA_BURST_SIZE_CH10_MASK (0x300000U) #define APBH_DMA_BURST_SIZE_CH10_SHIFT (20U) #define APBH_DMA_BURST_SIZE_CH10(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH10_SHIFT)) & APBH_DMA_BURST_SIZE_CH10_MASK) #define APBH_DMA_BURST_SIZE_CH11_MASK (0xC00000U) #define APBH_DMA_BURST_SIZE_CH11_SHIFT (22U) #define APBH_DMA_BURST_SIZE_CH11(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH11_SHIFT)) & APBH_DMA_BURST_SIZE_CH11_MASK) #define APBH_DMA_BURST_SIZE_CH12_MASK (0x3000000U) #define APBH_DMA_BURST_SIZE_CH12_SHIFT (24U) #define APBH_DMA_BURST_SIZE_CH12(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH12_SHIFT)) & APBH_DMA_BURST_SIZE_CH12_MASK) #define APBH_DMA_BURST_SIZE_CH13_MASK (0xC000000U) #define APBH_DMA_BURST_SIZE_CH13_SHIFT (26U) #define APBH_DMA_BURST_SIZE_CH13(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH13_SHIFT)) & APBH_DMA_BURST_SIZE_CH13_MASK) #define APBH_DMA_BURST_SIZE_CH14_MASK (0x30000000U) #define APBH_DMA_BURST_SIZE_CH14_SHIFT (28U) #define APBH_DMA_BURST_SIZE_CH14(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH14_SHIFT)) & APBH_DMA_BURST_SIZE_CH14_MASK) #define APBH_DMA_BURST_SIZE_CH15_MASK (0xC0000000U) #define APBH_DMA_BURST_SIZE_CH15_SHIFT (30U) #define APBH_DMA_BURST_SIZE_CH15(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH15_SHIFT)) & APBH_DMA_BURST_SIZE_CH15_MASK) /*! @} */ /*! @name DEBUG - AHB to APBH DMA Debug Register */ /*! @{ */ #define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U) #define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U) #define APBH_DEBUG_GPMI_ONE_FIFO(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK) /*! @} */ /*! @name CH_CURCMDAR - APBH DMA Channel n Current Command Address Register */ /*! @{ */ #define APBH_CH_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH_CURCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH_CURCMDAR_CMD_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_CURCMDAR_CMD_ADDR_MASK) /*! @} */ /* The count of APBH_CH_CURCMDAR */ #define APBH_CH_CURCMDAR_COUNT (16U) /*! @name CH_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ /*! @{ */ #define APBH_CH_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT (0U) #define APBH_CH_NXTCMDAR_CMD_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_NXTCMDAR_CMD_ADDR_MASK) /*! @} */ /* The count of APBH_CH_NXTCMDAR */ #define APBH_CH_NXTCMDAR_COUNT (16U) /*! @name CH_CMD - APBH DMA Channel n Command Register */ /*! @{ */ #define APBH_CH_CMD_COMMAND_MASK (0x3U) #define APBH_CH_CMD_COMMAND_SHIFT (0U) /*! COMMAND * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified * number of bytes. 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for * the specified number of bytes. 0b11..Perform any requested PIO word transfers and then perform a conditional branch * to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS * as a chain pointer if the peripheral sense line is false. */ #define APBH_CH_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_COMMAND_SHIFT)) & APBH_CH_CMD_COMMAND_MASK) #define APBH_CH_CMD_CHAIN_MASK (0x4U) #define APBH_CH_CMD_CHAIN_SHIFT (2U) #define APBH_CH_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CHAIN_SHIFT)) & APBH_CH_CMD_CHAIN_MASK) #define APBH_CH_CMD_IRQONCMPLT_MASK (0x8U) #define APBH_CH_CMD_IRQONCMPLT_SHIFT (3U) #define APBH_CH_CMD_IRQONCMPLT(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_IRQONCMPLT_SHIFT)) & APBH_CH_CMD_IRQONCMPLT_MASK) #define APBH_CH_CMD_NANDLOCK_MASK (0x10U) #define APBH_CH_CMD_NANDLOCK_SHIFT (4U) #define APBH_CH_CMD_NANDLOCK(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDLOCK_SHIFT)) & APBH_CH_CMD_NANDLOCK_MASK) #define APBH_CH_CMD_NANDWAIT4READY_MASK (0x20U) #define APBH_CH_CMD_NANDWAIT4READY_SHIFT (5U) #define APBH_CH_CMD_NANDWAIT4READY(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH_CMD_NANDWAIT4READY_MASK) #define APBH_CH_CMD_SEMAPHORE_MASK (0x40U) #define APBH_CH_CMD_SEMAPHORE_SHIFT (6U) #define APBH_CH_CMD_SEMAPHORE(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_SEMAPHORE_SHIFT)) & APBH_CH_CMD_SEMAPHORE_MASK) #define APBH_CH_CMD_WAIT4ENDCMD_MASK (0x80U) #define APBH_CH_CMD_WAIT4ENDCMD_SHIFT (7U) #define APBH_CH_CMD_WAIT4ENDCMD(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH_CMD_WAIT4ENDCMD_MASK) #define APBH_CH_CMD_HALTONTERMINATE_MASK (0x100U) #define APBH_CH_CMD_HALTONTERMINATE_SHIFT (8U) #define APBH_CH_CMD_HALTONTERMINATE(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH_CMD_HALTONTERMINATE_MASK) #define APBH_CH_CMD_CMDWORDS_MASK (0xF000U) #define APBH_CH_CMD_CMDWORDS_SHIFT (12U) #define APBH_CH_CMD_CMDWORDS(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CMDWORDS_SHIFT)) & APBH_CH_CMD_CMDWORDS_MASK) #define APBH_CH_CMD_XFER_COUNT_MASK (0xFFFF0000U) #define APBH_CH_CMD_XFER_COUNT_SHIFT (16U) #define APBH_CH_CMD_XFER_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_XFER_COUNT_SHIFT)) & APBH_CH_CMD_XFER_COUNT_MASK) /*! @} */ /* The count of APBH_CH_CMD */ #define APBH_CH_CMD_COUNT (16U) /*! @name CH_BAR - APBH DMA Channel n Buffer Address Register */ /*! @{ */ #define APBH_CH_BAR_ADDRESS_MASK (0xFFFFFFFFU) #define APBH_CH_BAR_ADDRESS_SHIFT (0U) #define APBH_CH_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_BAR_ADDRESS_SHIFT)) & APBH_CH_BAR_ADDRESS_MASK) /*! @} */ /* The count of APBH_CH_BAR */ #define APBH_CH_BAR_COUNT (16U) /*! @name CH_SEMA - APBH DMA Channel n Semaphore Register */ /*! @{ */ #define APBH_CH_SEMA_INCREMENT_SEMA_MASK (0xFFU) #define APBH_CH_SEMA_INCREMENT_SEMA_SHIFT (0U) #define APBH_CH_SEMA_INCREMENT_SEMA(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH_SEMA_INCREMENT_SEMA_MASK) #define APBH_CH_SEMA_PHORE_MASK (0xFF0000U) #define APBH_CH_SEMA_PHORE_SHIFT (16U) #define APBH_CH_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_PHORE_SHIFT)) & APBH_CH_SEMA_PHORE_MASK) /*! @} */ /* The count of APBH_CH_SEMA */ #define APBH_CH_SEMA_COUNT (16U) /*! @name CH_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH_DEBUG1_STATEMACHINE_MASK (0x1FU) #define APBH_CH_DEBUG1_STATEMACHINE_SHIFT (0U) /*! STATEMACHINE * 0b00000..This is the idle state of the DMA state machine. * 0b00001..State in which the DMA is waiting to receive the first word of a command. * 0b00010..State in which the DMA is waiting to receive the third word of a command. * 0b00011..State in which the DMA is waiting to receive the second word of a command. * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the * PIO words when PIO count is greater than 1. * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on * the APB. 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to * complete. 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter * accepts the request from this channel. 0b01101..During DMA Read transfers, the state machine waits in this state * until the AHB master arbiter accepts the request from this channel. 0b01110..Upon completion of the DMA transfers, * this state checks the value of the Chain bit and branches accordingly. 0b01111..The state machine goes to this state * after the DMA transfers are complete, and determines what step to take next. 0b10100..When a terminate signal is set, * the state machine enters this state until the current AHB transfer is completed. 0b10101..When the Wait for Command * End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write * to the AHB memory space. 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters * this state and effectively halts. A channel reset is required to exit this state 0b11110..If the Chain bit is a 0, * the state machine enters this state and effectively halts. 0b11111..When the NAND Wait for Ready bit is set, the * state machine enters this state until the GPMI device indicates that the external device is ready. */ #define APBH_CH_DEBUG1_STATEMACHINE(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH_DEBUG1_STATEMACHINE_MASK) #define APBH_CH_DEBUG1_RSVD1_MASK (0xFFFE0U) #define APBH_CH_DEBUG1_RSVD1_SHIFT (5U) #define APBH_CH_DEBUG1_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RSVD1_SHIFT)) & APBH_CH_DEBUG1_RSVD1_MASK) #define APBH_CH_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) #define APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT (20U) #define APBH_CH_DEBUG1_WR_FIFO_FULL(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_FULL_MASK) #define APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) #define APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) #define APBH_CH_DEBUG1_WR_FIFO_EMPTY(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK) #define APBH_CH_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) #define APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT (22U) #define APBH_CH_DEBUG1_RD_FIFO_FULL(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_FULL_MASK) #define APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) #define APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) #define APBH_CH_DEBUG1_RD_FIFO_EMPTY(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK) #define APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) #define APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) #define APBH_CH_DEBUG1_NEXTCMDADDRVALID(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK) #define APBH_CH_DEBUG1_LOCK_MASK (0x2000000U) #define APBH_CH_DEBUG1_LOCK_SHIFT (25U) #define APBH_CH_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_LOCK_SHIFT)) & APBH_CH_DEBUG1_LOCK_MASK) #define APBH_CH_DEBUG1_READY_MASK (0x4000000U) #define APBH_CH_DEBUG1_READY_SHIFT (26U) #define APBH_CH_DEBUG1_READY(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_READY_SHIFT)) & APBH_CH_DEBUG1_READY_MASK) #define APBH_CH_DEBUG1_SENSE_MASK (0x8000000U) #define APBH_CH_DEBUG1_SENSE_SHIFT (27U) #define APBH_CH_DEBUG1_SENSE(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_SENSE_SHIFT)) & APBH_CH_DEBUG1_SENSE_MASK) #define APBH_CH_DEBUG1_END_MASK (0x10000000U) #define APBH_CH_DEBUG1_END_SHIFT (28U) #define APBH_CH_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_END_SHIFT)) & APBH_CH_DEBUG1_END_MASK) #define APBH_CH_DEBUG1_KICK_MASK (0x20000000U) #define APBH_CH_DEBUG1_KICK_SHIFT (29U) #define APBH_CH_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_KICK_SHIFT)) & APBH_CH_DEBUG1_KICK_MASK) #define APBH_CH_DEBUG1_BURST_MASK (0x40000000U) #define APBH_CH_DEBUG1_BURST_SHIFT (30U) #define APBH_CH_DEBUG1_BURST(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_BURST_SHIFT)) & APBH_CH_DEBUG1_BURST_MASK) #define APBH_CH_DEBUG1_REQ_MASK (0x80000000U) #define APBH_CH_DEBUG1_REQ_SHIFT (31U) #define APBH_CH_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_REQ_SHIFT)) & APBH_CH_DEBUG1_REQ_MASK) /*! @} */ /* The count of APBH_CH_DEBUG1 */ #define APBH_CH_DEBUG1_COUNT (16U) /*! @name CH_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH_DEBUG2_AHB_BYTES_MASK (0xFFFFU) #define APBH_CH_DEBUG2_AHB_BYTES_SHIFT (0U) #define APBH_CH_DEBUG2_AHB_BYTES(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH_DEBUG2_AHB_BYTES_MASK) #define APBH_CH_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) #define APBH_CH_DEBUG2_APB_BYTES_SHIFT (16U) #define APBH_CH_DEBUG2_APB_BYTES(x) \ (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH_DEBUG2_APB_BYTES_MASK) /*! @} */ /* The count of APBH_CH_DEBUG2 */ #define APBH_CH_DEBUG2_COUNT (16U) /*! @name VERSION - APBH Bridge Version Register */ /*! @{ */ #define APBH_VERSION_STEP_MASK (0xFFFFU) #define APBH_VERSION_STEP_SHIFT (0U) #define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK) #define APBH_VERSION_MINOR_MASK (0xFF0000U) #define APBH_VERSION_MINOR_SHIFT (16U) #define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK) #define APBH_VERSION_MAJOR_MASK (0xFF000000U) #define APBH_VERSION_MAJOR_SHIFT (24U) #define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK) /*! @} */ /*! * @} */ /* end of group APBH_Register_Masks */ /* APBH - Peripheral instance base addresses */ /** Peripheral APBH base address */ #define APBH_BASE (0x33000000u) /** Peripheral APBH base pointer */ #define APBH ((APBH_Type *)APBH_BASE) /** Array initializer of APBH peripheral base addresses */ #define APBH_BASE_ADDRS \ { \ APBH_BASE \ } /** Array initializer of APBH peripheral base pointers */ #define APBH_BASE_PTRS \ { \ APBH \ } /** Interrupt vectors for the APBH peripheral type */ #define APBH_IRQS \ { \ APBHDMA_IRQn \ } /*! * @} */ /* end of group APBH_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ASRC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer * @{ */ /** ASRC - Register Layout Typedef */ typedef struct { __O uint32_t WRFIFO[4]; /**< ASRC Input Write FIFO, array offset: 0x0, array step: 0x4 */ __I uint32_t RDFIFO[4]; /**< ASRC Output Read FIFO, array offset: 0x10, array step: 0x4 */ __IO uint32_t CTX_CTRL[4]; /**< ASRC Context Control, array offset: 0x20, array step: 0x4 */ __IO uint32_t CTX_CTRL_EXT1[4]; /**< ASRC Context Control Extended 1, array offset: 0x30, array step: 0x4 */ __IO uint32_t CTX_CTRL_EXT2[4]; /**< ASRC Context Control Extended 2, array offset: 0x40, array step: 0x4 */ __IO uint32_t CTRL_IN_ACCESS[4]; /**< ASRC Control Input Access, array offset: 0x50, array step: 0x4 */ __IO uint32_t PROC_CTRL_SLOT0_R0[4]; /**< ASRC Datapath Processor Control Slot0 Register0, array offset: 0x60, array step: 0x4 */ __IO uint32_t PROC_CTRL_SLOT0_R1[4]; /**< ASRC Datapath Processor Control Slot0 Register1, array offset: 0x70, array step: 0x4 */ __IO uint32_t PROC_CTRL_SLOT0_R2[4]; /**< ASRC Datapath Processor Control Slot0 Register2, array offset: 0x80, array step: 0x4 */ __IO uint32_t PROC_CTRL_SLOT0_R3[4]; /**< ASRC Datapath Processor Control Slot0 Register3, array offset: 0x90, array step: 0x4 */ __IO uint32_t PROC_CTRL_SLOT1_R0[4]; /**< ASRC Datapath Processor Control Slot1 Register0, array offset: 0xA0, array step: 0x4 */ __IO uint32_t PROC_CTRL_SLOT1_R1[4]; /**< ASRC Datapath Processor Control SLOT1 Register1, array offset: 0xB0, array step: 0x4 */ __IO uint32_t PROC_CTRL_SLOT1_R2[4]; /**< ASRC Datapath Processor Control SLOT1 Register2, array offset: 0xC0, array step: 0x4 */ __IO uint32_t PROC_CTRL_SLOT1_R3[4]; /**< ASRC Datapath Processor Control SLOT1 Register3, array offset: 0xD0, array step: 0x4 */ __IO uint32_t CTX_OUT_CTRL[4]; /**< ASRC Context Output Control, array offset: 0xE0, array step: 0x4 */ __IO uint32_t CTRL_OUT_ACCESS[4]; /**< ASRC Control Output Access, array offset: 0xF0, array step: 0x4 */ __I uint32_t SAMPLE_FIFO_STATUS[4]; /**< ASRC Sample FIFO Status, array offset: 0x100, array step: 0x4 */ struct { /* offset: 0x110, array step: 0x8 */ __IO uint32_t RS_RATIO_LOW; /**< ASRC Resampling Ratio Low, array offset: 0x110, array step: 0x8 */ __IO uint32_t RS_RATIO_HIGH; /**< ASRC Resampling Ratio High, array offset: 0x114, array step: 0x8 */ } RS_RATIO_LOW[4]; __IO uint32_t RS_UPDATE_CTRL[4]; /**< ASRC Resampling Ratio Update Control, array offset: 0x130, array step: 0x4 */ __IO uint32_t RS_UPDATE_RATE[4]; /**< ASRC Resampling Ratio Update Rate, array offset: 0x140, array step: 0x4 */ __IO uint32_t RS_CT_LOW; /**< ASRC Resampling Center Tap Coefficient Low, offset: 0x150 */ __IO uint32_t RS_CT_HIGH; /**< ASRC Resampling Center Tap Coefficient High, offset: 0x154 */ uint8_t RESERVED_0[8]; __IO uint32_t PRE_COEFF_FIFO[4]; /**< ASRC Prefilter Coefficient FIFO, array offset: 0x160, array step: 0x4 */ __O uint32_t CTX_RS_COEFF_MEM; /**< ASRC Context Resampling Coefficient Memory, offset: 0x170 */ __IO uint32_t CTX_RS_COEFF_CTRL; /**< ASRC Context Resampling Coefficient Control, offset: 0x174 */ __IO uint32_t IRQ_CTRL; /**< ASRC Interrupt Control, offset: 0x178 */ __IO uint32_t IRQ_FLAGS; /**< ASRC Interrupt Status Flags, offset: 0x17C */ __IO uint32_t CHANNEL_STATUS_0[4]; /**< ASRC Channel Status 0, array offset: 0x180, array step: 0x4 */ __IO uint32_t CHANNEL_STATUS_1[4]; /**< ASRC Channel Status 1, array offset: 0x190, array step: 0x4 */ __IO uint32_t CHANNEL_STATUS_2[4]; /**< ASRC Channel Status 2, array offset: 0x1A0, array step: 0x4 */ __IO uint32_t CHANNEL_STATUS_3[4]; /**< ASRC Channel Status 3, array offset: 0x1B0, array step: 0x4 */ __IO uint32_t CHANNEL_STATUS_4[4]; /**< ASRC Channel Status 4, array offset: 0x1C0, array step: 0x4 */ __IO uint32_t CHANNEL_STATUS_5[4]; /**< ASRC Channel Status 5, array offset: 0x1D0, array step: 0x4 */ } ASRC_Type; /* ---------------------------------------------------------------------------- -- ASRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ASRC_Register_Masks ASRC Register Masks * @{ */ /*! @name WRFIFO - ASRC Input Write FIFO */ /*! @{ */ #define ASRC_WRFIFO_CTX_WR_DATA_MASK (0xFFFFFFFFU) #define ASRC_WRFIFO_CTX_WR_DATA_SHIFT (0U) #define ASRC_WRFIFO_CTX_WR_DATA(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_WRFIFO_CTX_WR_DATA_SHIFT)) & ASRC_WRFIFO_CTX_WR_DATA_MASK) /*! @} */ /* The count of ASRC_WRFIFO */ #define ASRC_WRFIFO_COUNT (4U) /*! @name RDFIFO - ASRC Output Read FIFO */ /*! @{ */ #define ASRC_RDFIFO_CTX_RD_DATA_MASK (0xFFFFFFFFU) #define ASRC_RDFIFO_CTX_RD_DATA_SHIFT (0U) #define ASRC_RDFIFO_CTX_RD_DATA(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_RDFIFO_CTX_RD_DATA_SHIFT)) & ASRC_RDFIFO_CTX_RD_DATA_MASK) /*! @} */ /* The count of ASRC_RDFIFO */ #define ASRC_RDFIFO_COUNT (4U) /*! @name CTX_CTRL - ASRC Context Control */ /*! @{ */ #define ASRC_CTX_CTRL_NUM_CH_EN_MASK (0x1FU) #define ASRC_CTX_CTRL_NUM_CH_EN_SHIFT (0U) #define ASRC_CTX_CTRL_NUM_CH_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_NUM_CH_EN_SHIFT)) & ASRC_CTX_CTRL_NUM_CH_EN_MASK) #define ASRC_CTX_CTRL_SIGN_IN_MASK (0x40U) #define ASRC_CTX_CTRL_SIGN_IN_SHIFT (6U) /*! SIGN_IN - Input Data Sign * 0b0..Signed Format * 0b1..Unsigned Format */ #define ASRC_CTX_CTRL_SIGN_IN(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_SIGN_IN_SHIFT)) & ASRC_CTX_CTRL_SIGN_IN_MASK) #define ASRC_CTX_CTRL_FLOAT_FMT_MASK (0x80U) #define ASRC_CTX_CTRL_FLOAT_FMT_SHIFT (7U) /*! FLOAT_FMT - Context Input Floating Point Format * 0b0..Integer Format * 0b1..Single Precision Floating Point Format */ #define ASRC_CTX_CTRL_FLOAT_FMT(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_FLOAT_FMT_SHIFT)) & ASRC_CTX_CTRL_FLOAT_FMT_MASK) #define ASRC_CTX_CTRL_BITS_PER_SAMPLE_MASK (0x300U) #define ASRC_CTX_CTRL_BITS_PER_SAMPLE_SHIFT (8U) /*! BITS_PER_SAMPLE - Number of Bits Per Audio Sample * 0b00..16-bits Per Sample * 0b01..20-bits Per Sample * 0b10..24-bits Per Sample * 0b11..32-bits Per Sample */ #define ASRC_CTX_CTRL_BITS_PER_SAMPLE(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_BITS_PER_SAMPLE_SHIFT)) & ASRC_CTX_CTRL_BITS_PER_SAMPLE_MASK) #define ASRC_CTX_CTRL_BIT_REV_MASK (0x400U) #define ASRC_CTX_CTRL_BIT_REV_SHIFT (10U) /*! BIT_REV - Sample Bit Reversal * 0b0..Keep Input Ordering * 0b1..Reverse Bit Ordering */ #define ASRC_CTX_CTRL_BIT_REV(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_BIT_REV_SHIFT)) & ASRC_CTX_CTRL_BIT_REV_MASK) #define ASRC_CTX_CTRL_SAMPLE_POSITION_MASK (0xF800U) #define ASRC_CTX_CTRL_SAMPLE_POSITION_SHIFT (11U) #define ASRC_CTX_CTRL_SAMPLE_POSITION(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_SAMPLE_POSITION_SHIFT)) & ASRC_CTX_CTRL_SAMPLE_POSITION_MASK) #define ASRC_CTX_CTRL_FIFO_WTMK_MASK (0x7F0000U) #define ASRC_CTX_CTRL_FIFO_WTMK_SHIFT (16U) #define ASRC_CTX_CTRL_FIFO_WTMK(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_FIFO_WTMK_SHIFT)) & ASRC_CTX_CTRL_FIFO_WTMK_MASK) #define ASRC_CTX_CTRL_FWMDE_MASK (0x10000000U) #define ASRC_CTX_CTRL_FWMDE_SHIFT (28U) /*! FWMDE - FIFO Watermark DMA Enable * 0b0..Input DMA Requests Not Enabled for This Context * 0b1..Input DMA Requests Enabled for This Context */ #define ASRC_CTX_CTRL_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_FWMDE_SHIFT)) & ASRC_CTX_CTRL_FWMDE_MASK) #define ASRC_CTX_CTRL_RUN_STOP_MASK (0x20000000U) #define ASRC_CTX_CTRL_RUN_STOP_SHIFT (29U) #define ASRC_CTX_CTRL_RUN_STOP(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_RUN_STOP_SHIFT)) & ASRC_CTX_CTRL_RUN_STOP_MASK) #define ASRC_CTX_CTRL_RUN_EN_MASK (0x80000000U) #define ASRC_CTX_CTRL_RUN_EN_SHIFT (31U) #define ASRC_CTX_CTRL_RUN_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_RUN_EN_SHIFT)) & ASRC_CTX_CTRL_RUN_EN_MASK) /*! @} */ /* The count of ASRC_CTX_CTRL */ #define ASRC_CTX_CTRL_COUNT (4U) /*! @name CTX_CTRL_EXT1 - ASRC Context Control Extended 1 */ /*! @{ */ #define ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_MASK (0x3U) #define ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_SHIFT (0U) /*! PF_INIT_MODE - Prefilter Initialization Mode * 0b00..Do not pre-fill any prefilter taps. The first sample written to the ASRC corresponds to the highest index * prefilter filter tap. 0b01..Replicate the first sample to fill the right half of the prefilter. 0b10..Zero fill the * right half of the prefilter. 0b11..N/A */ #define ASRC_CTX_CTRL_EXT1_PF_INIT_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_MASK) #define ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_MASK (0xCU) #define ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_SHIFT (2U) /*! RS_INIT_MODE - Resampler Initialization Mode * 0b00..Do not pre-fill any resampler taps. The first sample output from the prefilter corresponds to the highest * index resampling filter tap. 0b01..Replicate the first prefilter output sample to fill the right half of the * resampler. 0b10..Fill the right half of the re-sampler with zeros. 0b11..N/A */ #define ASRC_CTX_CTRL_EXT1_RS_INIT_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_MASK) #define ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_MASK (0x10U) #define ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_SHIFT (4U) /*! PF_STOP_MODE - Pre-Filter Stop Mode * 0b0..Replicate the last sample input to the ASRC_WRFIFO for the left-half of the pre-filter on RUN_STOP. * 0b1..Zero-Fill the left-half of the pre-filter on RUN_STOP. */ #define ASRC_CTX_CTRL_EXT1_PF_STOP_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_MASK) #define ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_MASK (0x20U) #define ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_SHIFT (5U) /*! RS_STOP_MODE - Resampler Stop Mode * 0b0..Replicate the final prefilter output for the left-half of the resampler on RUN_STOP. * 0b1..Zero-Fill the left-half of the resampler on RUN_STOP. */ #define ASRC_CTX_CTRL_EXT1_RS_STOP_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_MASK) #define ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_MASK (0x40U) #define ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_SHIFT (6U) /*! PF_BYPASS_MODE - Prefilter Bypass Mode * 0b0..Run the prefilter in normal operation. * 0b1..Run the prefilter in bypass mode. */ #define ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_MASK) #define ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_MASK (0x80U) #define ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_SHIFT (7U) /*! RS_BYPASS_MODE - Resampler Bypass Mode * 0b0..Run the resampler in normal operation. * 0b1..Run the resampler in bypass mode. */ #define ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_MASK) #define ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_MASK (0x100U) #define ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_SHIFT (8U) /*! PF_TWO_STAGE_EN - Prefilter Two-Stage Enable * 0b0..The pre-filter will run in single stage mode (ST1 only) * 0b1..The pre-filter will run in two stage mode (ST1 and ST2) */ #define ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_SHIFT)) & \ ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_MASK) #define ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_MASK (0x200U) #define ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_SHIFT (9U) /*! PF_ST1_WB_FLOAT - Prefilter Stage1 Writeback Floating Point * 0b0..The pre-filter stage1 results are stored in 32-bit integer format. * 0b1..The pre-filter stage1 results are stored in 32-bit floating point format. */ #define ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_SHIFT)) & \ ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_MASK) #define ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_MASK (0xFF0000U) #define ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_SHIFT (16U) #define ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_SHIFT)) & \ ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_MASK) #define ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_MASK (0x1000000U) #define ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_SHIFT (24U) #define ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_SHIFT)) & \ ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_MASK) #define ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_MASK (0x2000000U) #define ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_SHIFT (25U) #define ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_SHIFT)) & \ ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_MASK) /*! @} */ /* The count of ASRC_CTX_CTRL_EXT1 */ #define ASRC_CTX_CTRL_EXT1_COUNT (4U) /*! @name CTX_CTRL_EXT2 - ASRC Context Control Extended 2 */ /*! @{ */ #define ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_MASK (0x1FFU) #define ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_SHIFT (0U) #define ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_SHIFT)) & ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_MASK) #define ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_MASK (0x1FF0000U) #define ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_SHIFT (16U) #define ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_SHIFT)) & ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_MASK) /*! @} */ /* The count of ASRC_CTX_CTRL_EXT2 */ #define ASRC_CTX_CTRL_EXT2_COUNT (4U) /*! @name CTRL_IN_ACCESS - ASRC Control Input Access */ /*! @{ */ #define ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_MASK (0x3FU) #define ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_SHIFT (0U) #define ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_SHIFT)) & ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_MASK) #define ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_MASK (0x3F00U) #define ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_SHIFT (8U) #define ASRC_CTRL_IN_ACCESS_GROUP_LENGTH(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_SHIFT)) & ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_MASK) #define ASRC_CTRL_IN_ACCESS_ITERATIONS_MASK (0x3F0000U) #define ASRC_CTRL_IN_ACCESS_ITERATIONS_SHIFT (16U) #define ASRC_CTRL_IN_ACCESS_ITERATIONS(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_IN_ACCESS_ITERATIONS_SHIFT)) & ASRC_CTRL_IN_ACCESS_ITERATIONS_MASK) /*! @} */ /* The count of ASRC_CTRL_IN_ACCESS */ #define ASRC_CTRL_IN_ACCESS_COUNT (4U) /*! @name PROC_CTRL_SLOT0_R0 - ASRC Datapath Processor Control Slot0 Register0 */ /*! @{ */ #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_MASK (0x1U) #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_SHIFT (0U) /*! SLOT0_EN - SLOT0 Enable * 0b0..Context SLOT0 is disabled * 0b1..Context SLOT0 is enabled */ #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_MASK) #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_MASK (0x6U) #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_SHIFT (1U) #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_SHIFT)) & \ ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_MASK) #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_MASK (0x1F00U) #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_SHIFT (8U) /*! SLOT0_NUM_CH - SLOT0 Number of Channels * 0b00000..Context SLOT0 owns 1 of 8 channels * 0b00001..Context SLOT0 owns 2 of 8 channels * 0b00010..Context SLOT0 owns 3 of 8 channels * 0b00011-0b00111..Context SLOT0 owns N of 8 channels */ #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_SHIFT)) & \ ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_MASK) #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_MASK (0x1F0000U) #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_SHIFT (16U) #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_SHIFT)) & \ ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_MASK) #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_MASK (0x1F000000U) #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_SHIFT (24U) #define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_SHIFT)) & \ ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_MASK) /*! @} */ /* The count of ASRC_PROC_CTRL_SLOT0_R0 */ #define ASRC_PROC_CTRL_SLOT0_R0_COUNT (4U) /*! @name PROC_CTRL_SLOT0_R1 - ASRC Datapath Processor Control Slot0 Register1 */ /*! @{ */ #define ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_MASK (0x1FFFU) #define ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_SHIFT (0U) #define ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_SHIFT)) & \ ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_MASK) /*! @} */ /* The count of ASRC_PROC_CTRL_SLOT0_R1 */ #define ASRC_PROC_CTRL_SLOT0_R1_COUNT (4U) /*! @name PROC_CTRL_SLOT0_R2 - ASRC Datapath Processor Control Slot0 Register2 */ /*! @{ */ #define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_MASK (0x1FFFU) #define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_SHIFT (0U) #define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_SHIFT)) & \ ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_MASK) #define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_MASK (0x1FFF0000U) #define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_SHIFT (16U) #define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_SHIFT)) & \ ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_MASK) /*! @} */ /* The count of ASRC_PROC_CTRL_SLOT0_R2 */ #define ASRC_PROC_CTRL_SLOT0_R2_COUNT (4U) /*! @name PROC_CTRL_SLOT0_R3 - ASRC Datapath Processor Control Slot0 Register3 */ /*! @{ */ #define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_MASK (0x1FFFU) #define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_SHIFT (0U) #define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_SHIFT)) & \ ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_MASK) #define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_MASK (0x1FFF0000U) #define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_SHIFT (16U) #define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_SHIFT)) & \ ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_MASK) /*! @} */ /* The count of ASRC_PROC_CTRL_SLOT0_R3 */ #define ASRC_PROC_CTRL_SLOT0_R3_COUNT (4U) /*! @name PROC_CTRL_SLOT1_R0 - ASRC Datapath Processor Control Slot1 Register0 */ /*! @{ */ #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_MASK (0x1U) #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_SHIFT (0U) /*! SLOT1_EN - SLOT1 Enable * 0b0..Context SLOT1 is disabled * 0b1..Context SLOT1 is enabled */ #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_MASK) #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_MASK (0x6U) #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_SHIFT (1U) #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_SHIFT)) & \ ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_MASK) #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_MASK (0x1F00U) #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_SHIFT (8U) /*! SLOT1_NUM_CH - SLOT1 Number of Channels * 0b00000..Context SLOT1 owns 1 of 8 channels * 0b00001..Context SLOT1 owns 2 of 8 channels * 0b00010..Context SLOT1 owns 3 of 8 channels * 0b00011-0b00111..Context SLOT1 owns N of 8 channels */ #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_SHIFT)) & \ ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_MASK) #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_MASK (0x1F0000U) #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_SHIFT (16U) #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_SHIFT)) & \ ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_MASK) #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_MASK (0x1F000000U) #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_SHIFT (24U) #define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_SHIFT)) & \ ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_MASK) /*! @} */ /* The count of ASRC_PROC_CTRL_SLOT1_R0 */ #define ASRC_PROC_CTRL_SLOT1_R0_COUNT (4U) /*! @name PROC_CTRL_SLOT1_R1 - ASRC Datapath Processor Control SLOT1 Register1 */ /*! @{ */ #define ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_MASK (0x1FFFU) #define ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_SHIFT (0U) #define ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_SHIFT)) & \ ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_MASK) /*! @} */ /* The count of ASRC_PROC_CTRL_SLOT1_R1 */ #define ASRC_PROC_CTRL_SLOT1_R1_COUNT (4U) /*! @name PROC_CTRL_SLOT1_R2 - ASRC Datapath Processor Control SLOT1 Register2 */ /*! @{ */ #define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_MASK (0x1FFFU) #define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_SHIFT (0U) #define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_SHIFT)) & \ ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_MASK) #define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_MASK (0x1FFF0000U) #define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_SHIFT (16U) #define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_SHIFT)) & \ ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_MASK) /*! @} */ /* The count of ASRC_PROC_CTRL_SLOT1_R2 */ #define ASRC_PROC_CTRL_SLOT1_R2_COUNT (4U) /*! @name PROC_CTRL_SLOT1_R3 - ASRC Datapath Processor Control SLOT1 Register3 */ /*! @{ */ #define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_MASK (0x1FFFU) #define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_SHIFT (0U) #define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_SHIFT)) & \ ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_MASK) #define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_MASK (0x1FFF0000U) #define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_SHIFT (16U) #define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_SHIFT)) & \ ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_MASK) /*! @} */ /* The count of ASRC_PROC_CTRL_SLOT1_R3 */ #define ASRC_PROC_CTRL_SLOT1_R3_COUNT (4U) /*! @name CTX_OUT_CTRL - ASRC Context Output Control */ /*! @{ */ #define ASRC_CTX_OUT_CTRL_DITHER_EN_MASK (0x1U) #define ASRC_CTX_OUT_CTRL_DITHER_EN_SHIFT (0U) #define ASRC_CTX_OUT_CTRL_DITHER_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_DITHER_EN_SHIFT)) & ASRC_CTX_OUT_CTRL_DITHER_EN_MASK) #define ASRC_CTX_OUT_CTRL_IEC_EN_MASK (0x2U) #define ASRC_CTX_OUT_CTRL_IEC_EN_SHIFT (1U) /*! IEC_EN - IEC60958 Bit-Field Insertion Enable * 0b0..No Data Insertion Enabled. * 0b1..IEC60958 Bit-Field Insertion Enabled. */ #define ASRC_CTX_OUT_CTRL_IEC_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_IEC_EN_SHIFT)) & ASRC_CTX_OUT_CTRL_IEC_EN_MASK) #define ASRC_CTX_OUT_CTRL_IEC_V_DATA_MASK (0x4U) #define ASRC_CTX_OUT_CTRL_IEC_V_DATA_SHIFT (2U) #define ASRC_CTX_OUT_CTRL_IEC_V_DATA(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_IEC_V_DATA_SHIFT)) & ASRC_CTX_OUT_CTRL_IEC_V_DATA_MASK) #define ASRC_CTX_OUT_CTRL_SIGN_OUT_MASK (0x40U) #define ASRC_CTX_OUT_CTRL_SIGN_OUT_SHIFT (6U) /*! SIGN_OUT - Output Data Sign * 0b0..Signed Format * 0b1..Convert to Unsigned */ #define ASRC_CTX_OUT_CTRL_SIGN_OUT(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_SIGN_OUT_SHIFT)) & ASRC_CTX_OUT_CTRL_SIGN_OUT_MASK) #define ASRC_CTX_OUT_CTRL_FLOAT_FMT_MASK (0x80U) #define ASRC_CTX_OUT_CTRL_FLOAT_FMT_SHIFT (7U) /*! FLOAT_FMT - Context Output Floating Point Format * 0b0..Integer Format * 0b1..Single Precision Floating Point Format */ #define ASRC_CTX_OUT_CTRL_FLOAT_FMT(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_FLOAT_FMT_SHIFT)) & ASRC_CTX_OUT_CTRL_FLOAT_FMT_MASK) #define ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_MASK (0x300U) #define ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_SHIFT (8U) /*! BITS_PER_SAMPLE - Number of Bits Per Audio Sample * 0b00..16-bits Per Sample * 0b01..20-bits Per Sample * 0b10..24-bits Per Sample * 0b11..32-bits Per Sample */ #define ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_SHIFT)) & ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_MASK) #define ASRC_CTX_OUT_CTRL_BIT_REV_MASK (0x400U) #define ASRC_CTX_OUT_CTRL_BIT_REV_SHIFT (10U) /*! BIT_REV - Sample Bit-Reversal * 0b0..No change. * 0b1..Bit-reverse sample data. */ #define ASRC_CTX_OUT_CTRL_BIT_REV(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_BIT_REV_SHIFT)) & ASRC_CTX_OUT_CTRL_BIT_REV_MASK) #define ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_MASK (0xF800U) #define ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_SHIFT (11U) #define ASRC_CTX_OUT_CTRL_SAMPLE_POSITION(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_SHIFT)) & ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_MASK) #define ASRC_CTX_OUT_CTRL_FIFO_WTMK_MASK (0x7F0000U) #define ASRC_CTX_OUT_CTRL_FIFO_WTMK_SHIFT (16U) #define ASRC_CTX_OUT_CTRL_FIFO_WTMK(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_FIFO_WTMK_SHIFT)) & ASRC_CTX_OUT_CTRL_FIFO_WTMK_MASK) #define ASRC_CTX_OUT_CTRL_FWMDE_MASK (0x10000000U) #define ASRC_CTX_OUT_CTRL_FWMDE_SHIFT (28U) /*! FWMDE - Output FIFO Watermark DMA Enable * 0b0..Output DMA Requests Not Enabled for This Context * 0b1..Output DMA Requests Enabled for This Context */ #define ASRC_CTX_OUT_CTRL_FWMDE(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_FWMDE_SHIFT)) & ASRC_CTX_OUT_CTRL_FWMDE_MASK) /*! @} */ /* The count of ASRC_CTX_OUT_CTRL */ #define ASRC_CTX_OUT_CTRL_COUNT (4U) /*! @name CTRL_OUT_ACCESS - ASRC Control Output Access */ /*! @{ */ #define ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_MASK (0x3FU) #define ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_SHIFT (0U) #define ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_SHIFT)) & \ ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_MASK) #define ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_MASK (0x3F00U) #define ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_SHIFT (8U) #define ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_SHIFT)) & ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_MASK) #define ASRC_CTRL_OUT_ACCESS_ITERATIONS_MASK (0x3F0000U) #define ASRC_CTRL_OUT_ACCESS_ITERATIONS_SHIFT (16U) #define ASRC_CTRL_OUT_ACCESS_ITERATIONS(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_OUT_ACCESS_ITERATIONS_SHIFT)) & ASRC_CTRL_OUT_ACCESS_ITERATIONS_MASK) /*! @} */ /* The count of ASRC_CTRL_OUT_ACCESS */ #define ASRC_CTRL_OUT_ACCESS_COUNT (4U) /*! @name SAMPLE_FIFO_STATUS - ASRC Sample FIFO Status */ /*! @{ */ #define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_MASK (0x7FU) #define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_SHIFT (0U) #define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_SHIFT)) & \ ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_MASK) #define ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_MASK (0x80U) #define ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_SHIFT (7U) #define ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_SHIFT)) & \ ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_MASK) #define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_MASK (0x7F0000U) #define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_SHIFT (16U) #define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_SHIFT)) & \ ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_MASK) #define ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_MASK (0x800000U) #define ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_SHIFT (23U) #define ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_SHIFT)) & \ ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_MASK) /*! @} */ /* The count of ASRC_SAMPLE_FIFO_STATUS */ #define ASRC_SAMPLE_FIFO_STATUS_COUNT (4U) /*! @name RS_RATIO_LOW - ASRC Resampling Ratio Low */ /*! @{ */ #define ASRC_RS_RATIO_LOW_RS_RATIO_LOW_MASK (0xFFFFFFFFU) #define ASRC_RS_RATIO_LOW_RS_RATIO_LOW_SHIFT (0U) #define ASRC_RS_RATIO_LOW_RS_RATIO_LOW(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_RS_RATIO_LOW_RS_RATIO_LOW_SHIFT)) & ASRC_RS_RATIO_LOW_RS_RATIO_LOW_MASK) /*! @} */ /* The count of ASRC_RS_RATIO_LOW */ #define ASRC_RS_RATIO_LOW_COUNT (4U) /*! @name RS_RATIO_HIGH - ASRC Resampling Ratio High */ /*! @{ */ #define ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_MASK (0xFFFU) #define ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_SHIFT (0U) #define ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_SHIFT)) & ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_MASK) #define ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_MASK (0x80000000U) #define ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_SHIFT (31U) #define ASRC_RS_RATIO_HIGH_RS_RATIO_VLD(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_SHIFT)) & ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_MASK) /*! @} */ /* The count of ASRC_RS_RATIO_HIGH */ #define ASRC_RS_RATIO_HIGH_COUNT (4U) /*! @name RS_UPDATE_CTRL - ASRC Resampling Ratio Update Control */ /*! @{ */ #define ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_MASK (0xFFFFFFFFU) #define ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_SHIFT (0U) #define ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_SHIFT)) & ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_MASK) /*! @} */ /* The count of ASRC_RS_UPDATE_CTRL */ #define ASRC_RS_UPDATE_CTRL_COUNT (4U) /*! @name RS_UPDATE_RATE - ASRC Resampling Ratio Update Rate */ /*! @{ */ #define ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_MASK (0x7FFFFFFFU) #define ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_SHIFT (0U) #define ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_SHIFT)) & \ ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_MASK) /*! @} */ /* The count of ASRC_RS_UPDATE_RATE */ #define ASRC_RS_UPDATE_RATE_COUNT (4U) /*! @name RS_CT_LOW - ASRC Resampling Center Tap Coefficient Low */ /*! @{ */ #define ASRC_RS_CT_LOW_RS_CT_LOW_MASK (0xFFFFFFFFU) #define ASRC_RS_CT_LOW_RS_CT_LOW_SHIFT (0U) #define ASRC_RS_CT_LOW_RS_CT_LOW(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_RS_CT_LOW_RS_CT_LOW_SHIFT)) & ASRC_RS_CT_LOW_RS_CT_LOW_MASK) /*! @} */ /*! @name RS_CT_HIGH - ASRC Resampling Center Tap Coefficient High */ /*! @{ */ #define ASRC_RS_CT_HIGH_RS_CT_HIGH_MASK (0xFFFFFFFFU) #define ASRC_RS_CT_HIGH_RS_CT_HIGH_SHIFT (0U) #define ASRC_RS_CT_HIGH_RS_CT_HIGH(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_RS_CT_HIGH_RS_CT_HIGH_SHIFT)) & ASRC_RS_CT_HIGH_RS_CT_HIGH_MASK) /*! @} */ /*! @name PRE_COEFF_FIFO - ASRC Prefilter Coefficient FIFO */ /*! @{ */ #define ASRC_PRE_COEFF_FIFO_COEFF_DATA_MASK (0xFFFFFFFFU) #define ASRC_PRE_COEFF_FIFO_COEFF_DATA_SHIFT (0U) #define ASRC_PRE_COEFF_FIFO_COEFF_DATA(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_PRE_COEFF_FIFO_COEFF_DATA_SHIFT)) & ASRC_PRE_COEFF_FIFO_COEFF_DATA_MASK) /*! @} */ /* The count of ASRC_PRE_COEFF_FIFO */ #define ASRC_PRE_COEFF_FIFO_COUNT (4U) /*! @name CTX_RS_COEFF_MEM - ASRC Context Resampling Coefficient Memory */ /*! @{ */ #define ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_MASK (0xFFFFFFFFU) #define ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_SHIFT (0U) #define ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_SHIFT)) & \ ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_MASK) /*! @} */ /*! @name CTX_RS_COEFF_CTRL - ASRC Context Resampling Coefficient Control */ /*! @{ */ #define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_MASK (0x1U) #define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_SHIFT (0U) #define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_SHIFT)) & \ ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_MASK) #define ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_MASK (0x6U) #define ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_SHIFT (1U) /*! NUM_RES_TAPS - Number of Resampling Coefficient Taps * 0b00..32-Tap Resampling Filter * 0b01..64-Tap Resampling Filter * 0b10..128-Tap Resampling Filter * 0b11..N/A */ #define ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_SHIFT)) & \ ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_MASK) #define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_MASK (0x7FF0000U) #define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_SHIFT (16U) #define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_SHIFT)) & \ ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_MASK) /*! @} */ /*! @name IRQ_CTRL - ASRC Interrupt Control */ /*! @{ */ #define ASRC_IRQ_CTRL_INFIFO_OVF_MASK_MASK (0xFU) #define ASRC_IRQ_CTRL_INFIFO_OVF_MASK_SHIFT (0U) /*! INFIFO_OVF_MASK - ASRC Input FIFO Overflow Mask * 0b0000..The INFIFO_OVF interrupt is enabled for Context 0 to 3. * 0b0001..The INFIFO_OVF interrupt is disabled for Context 0 and enabled for Context 1 to 3. * 0b0010..The INFIFO_OVF interrupt is disabled for Context 1 and enabled for Context 0, 2, and 3. * 0b0011-0b1110..The INFIFO_OVF interrupt is enabled for any context with a 1'b0 bit field. * 0b1111..The INFIFO_OVF interrupt is disabled for Context 0 to 3. */ #define ASRC_IRQ_CTRL_INFIFO_OVF_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_CTRL_INFIFO_OVF_MASK_SHIFT)) & ASRC_IRQ_CTRL_INFIFO_OVF_MASK_MASK) #define ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_MASK (0xF0U) #define ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_SHIFT (4U) /*! OUTFIFO_EMPTY_RD_MASK - ASRC Output FIFO Empty Read Mask * 0b0000..The OUTFIFO_EMPTY_RD interrupt is enabled for Context 0 to 3. * 0b0001..The OUTFIFO_EMPTY_RD interrupt is disabled for Context 0 and enabled for Context 1 to 3. * 0b0010..The OUTFIFO_EMPTY_RD interrupt is disabled for Context 1 and enabled for Context 0, 2, and 3. * 0b0011-0b1110..The OUTFIFO_EMPTY_RD interrupt is enabled for any context with a 1'b0 bit field. * 0b1111..The OUTFIFO_EMPTY_RD interrupt is disabled for Context 0 to 3. */ #define ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_SHIFT)) & \ ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_MASK) #define ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_MASK (0xF00U) #define ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_SHIFT (8U) /*! RUN_STOP_DONE_MASK - ASRC RUN STOP DONE MASK * 0b0000..The RUN_STOP_DONE interrupt is enabled for Context 0 to 3. * 0b0001..The RUN_STOP_DONE interrupt is disabled for Context 0 and enabled for Context 1 to 3. * 0b0010..The RUN_STOP_DONE interrupt is disabled for Context 1 and enabled for Context 0, 2, and 3. * 0b0011-0b1110..The RUN_STOP_DONE interrupt is enabled for any context with a 1'b0 bit field. * 0b1111..The RUN_STOP_DONE interrupt is disabled for Context 0 to 3. */ #define ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_SHIFT)) & ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_MASK) /*! @} */ /*! @name IRQ_FLAGS - ASRC Interrupt Status Flags */ /*! @{ */ #define ASRC_IRQ_FLAGS_INFIFO_OVF_MASK (0xFU) #define ASRC_IRQ_FLAGS_INFIFO_OVF_SHIFT (0U) /*! INFIFO_OVF - ASRC Input FIFO Overflow Flag * 0b0000..No INFIFO_OVF errors have been recorded. * 0b0001..The ASRC_WRFIFO0 has overflown. * 0b0010..The ASRC_WRFIFO1 has overflown. * 0b0011-0b1110..The ASRC_WRFIFOn has overflown. Where n = any bit position set to 0b1. * 0b1111..ASRC_WRFIFO0, ASRC_WRFIFO1, ASRC_WRFIFO2, and ASRC_WRFIFO3 have overflown. */ #define ASRC_IRQ_FLAGS_INFIFO_OVF(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_FLAGS_INFIFO_OVF_SHIFT)) & ASRC_IRQ_FLAGS_INFIFO_OVF_MASK) #define ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_MASK (0xF0U) #define ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_SHIFT (4U) /*! OUTFIFO_EMPTY_RD - ASRC Output FIFO Empty Read Flag * 0b0000..No reads have been requested from an empty ASRC_RDFIFO. * 0b0001..A read has been requested from ASRC_RDFIFO0 when it was empty. * 0b0010..A read has been requested from ASRC_RDFIFO1 when it was empty. * 0b0011-0b1110..A read has been requested from ASRC_RDFIFOn when it was empty. n = any bit position with a 0b1. * 0b1111..A read has been requested from ASRC_RDFIFO0, ASRC_RDFIFO1, ASRC_RDFIFO2, and ASRC_RDFIFO3 while empty. */ #define ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_SHIFT)) & ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_MASK) #define ASRC_IRQ_FLAGS_RUN_STOP_DONE_MASK (0xF00U) #define ASRC_IRQ_FLAGS_RUN_STOP_DONE_SHIFT (8U) /*! RUN_STOP_DONE - ASRC RUN STOP DONE FLAG * 0b0000..No RUN_STOP operations have been completed. * 0b0001..The RUN_STOP operation for Context 0 has completed. * 0b0010..The RUN_STOP operation for Context 1 has completed. * 0b0011-0b1110..The RUN_STOP operation has completed for any context with a 1'b1 bit field. * 0b1111..The RUN_STOP operation has completed for Context 0 to 3. */ #define ASRC_IRQ_FLAGS_RUN_STOP_DONE(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_FLAGS_RUN_STOP_DONE_SHIFT)) & ASRC_IRQ_FLAGS_RUN_STOP_DONE_MASK) /*! @} */ /*! @name CHANNEL_STATUS_0 - ASRC Channel Status 0 */ /*! @{ */ #define ASRC_CHANNEL_STATUS_0_CHN_STAT_MASK (0xFFFFFFFFU) #define ASRC_CHANNEL_STATUS_0_CHN_STAT_SHIFT (0U) #define ASRC_CHANNEL_STATUS_0_CHN_STAT(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_0_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_0_CHN_STAT_MASK) /*! @} */ /* The count of ASRC_CHANNEL_STATUS_0 */ #define ASRC_CHANNEL_STATUS_0_COUNT (4U) /*! @name CHANNEL_STATUS_1 - ASRC Channel Status 1 */ /*! @{ */ #define ASRC_CHANNEL_STATUS_1_CHN_STAT_MASK (0xFFFFFFFFU) #define ASRC_CHANNEL_STATUS_1_CHN_STAT_SHIFT (0U) #define ASRC_CHANNEL_STATUS_1_CHN_STAT(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_1_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_1_CHN_STAT_MASK) /*! @} */ /* The count of ASRC_CHANNEL_STATUS_1 */ #define ASRC_CHANNEL_STATUS_1_COUNT (4U) /*! @name CHANNEL_STATUS_2 - ASRC Channel Status 2 */ /*! @{ */ #define ASRC_CHANNEL_STATUS_2_CHN_STAT_MASK (0xFFFFFFFFU) #define ASRC_CHANNEL_STATUS_2_CHN_STAT_SHIFT (0U) #define ASRC_CHANNEL_STATUS_2_CHN_STAT(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_2_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_2_CHN_STAT_MASK) /*! @} */ /* The count of ASRC_CHANNEL_STATUS_2 */ #define ASRC_CHANNEL_STATUS_2_COUNT (4U) /*! @name CHANNEL_STATUS_3 - ASRC Channel Status 3 */ /*! @{ */ #define ASRC_CHANNEL_STATUS_3_CHN_STAT_MASK (0xFFFFFFFFU) #define ASRC_CHANNEL_STATUS_3_CHN_STAT_SHIFT (0U) #define ASRC_CHANNEL_STATUS_3_CHN_STAT(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_3_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_3_CHN_STAT_MASK) /*! @} */ /* The count of ASRC_CHANNEL_STATUS_3 */ #define ASRC_CHANNEL_STATUS_3_COUNT (4U) /*! @name CHANNEL_STATUS_4 - ASRC Channel Status 4 */ /*! @{ */ #define ASRC_CHANNEL_STATUS_4_CHN_STAT_MASK (0xFFFFFFFFU) #define ASRC_CHANNEL_STATUS_4_CHN_STAT_SHIFT (0U) #define ASRC_CHANNEL_STATUS_4_CHN_STAT(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_4_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_4_CHN_STAT_MASK) /*! @} */ /* The count of ASRC_CHANNEL_STATUS_4 */ #define ASRC_CHANNEL_STATUS_4_COUNT (4U) /*! @name CHANNEL_STATUS_5 - ASRC Channel Status 5 */ /*! @{ */ #define ASRC_CHANNEL_STATUS_5_CHN_STAT_MASK (0xFFFFFFFFU) #define ASRC_CHANNEL_STATUS_5_CHN_STAT_SHIFT (0U) #define ASRC_CHANNEL_STATUS_5_CHN_STAT(x) \ (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_5_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_5_CHN_STAT_MASK) /*! @} */ /* The count of ASRC_CHANNEL_STATUS_5 */ #define ASRC_CHANNEL_STATUS_5_COUNT (4U) /*! * @} */ /* end of group ASRC_Register_Masks */ /* ASRC - Peripheral instance base addresses */ /** Peripheral ASRC base address */ #define ASRC_BASE (0x300C0000u) /** Peripheral ASRC base pointer */ #define ASRC ((ASRC_Type *)ASRC_BASE) /** Array initializer of ASRC peripheral base addresses */ #define ASRC_BASE_ADDRS \ { \ ASRC_BASE \ } /** Array initializer of ASRC peripheral base pointers */ #define ASRC_BASE_PTRS \ { \ ASRC \ } /*! * @} */ /* end of group ASRC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- BCH Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer * @{ */ /** BCH - Register Layout Typedef */ typedef struct { __IO uint32_t CTRL; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */ __IO uint32_t CTRL_SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */ __IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */ __IO uint32_t CTRL_TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */ __I uint32_t STATUS0; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */ uint8_t RESERVED_0[12]; __IO uint32_t MODE; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */ uint8_t RESERVED_1[12]; __IO uint32_t ENCODEPTR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */ uint8_t RESERVED_2[12]; __IO uint32_t DATAPTR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */ uint8_t RESERVED_3[12]; __IO uint32_t METAPTR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */ uint8_t RESERVED_4[28]; __IO uint32_t LAYOUTSELECT; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */ uint8_t RESERVED_5[12]; __IO uint32_t FLASH0LAYOUT0; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */ uint8_t RESERVED_6[12]; __IO uint32_t FLASH0LAYOUT1; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */ uint8_t RESERVED_7[12]; __IO uint32_t FLASH1LAYOUT0; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */ uint8_t RESERVED_8[12]; __IO uint32_t FLASH1LAYOUT1; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */ uint8_t RESERVED_9[12]; __IO uint32_t FLASH2LAYOUT0; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */ uint8_t RESERVED_10[12]; __IO uint32_t FLASH2LAYOUT1; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */ uint8_t RESERVED_11[12]; __IO uint32_t FLASH3LAYOUT0; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */ uint8_t RESERVED_12[12]; __IO uint32_t FLASH3LAYOUT1; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */ uint8_t RESERVED_13[12]; __IO uint32_t DEBUG0; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */ __IO uint32_t DEBUG0_SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */ __IO uint32_t DEBUG0_CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */ __IO uint32_t DEBUG0_TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */ __I uint32_t DBGKESREAD; /**< KES Debug Read Register, offset: 0x110 */ uint8_t RESERVED_14[12]; __I uint32_t DBGCSFEREAD; /**< Chien Search Debug Read Register, offset: 0x120 */ uint8_t RESERVED_15[12]; __I uint32_t DBGSYNDGENREAD; /**< Syndrome Generator Debug Read Register, offset: 0x130 */ uint8_t RESERVED_16[12]; __I uint32_t DBGAHBMREAD; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */ uint8_t RESERVED_17[12]; __I uint32_t BLOCKNAME; /**< Block Name Register, offset: 0x150 */ uint8_t RESERVED_18[12]; __I uint32_t VERSION; /**< BCH Version Register, offset: 0x160 */ uint8_t RESERVED_19[12]; __IO uint32_t DEBUG1; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */ } BCH_Type; /* ---------------------------------------------------------------------------- -- BCH Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup BCH_Register_Masks BCH Register Masks * @{ */ /*! @name CTRL - Hardware BCH ECC Accelerator Control Register */ /*! @{ */ #define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U) #define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U) #define BCH_CTRL_COMPLETE_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK) #define BCH_CTRL_RSVD0_MASK (0x2U) #define BCH_CTRL_RSVD0_SHIFT (1U) #define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK) #define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U) #define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U) #define BCH_CTRL_DEBUG_STALL_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK) #define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U) #define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U) #define BCH_CTRL_BM_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK) #define BCH_CTRL_RSVD1_MASK (0xF0U) #define BCH_CTRL_RSVD1_SHIFT (4U) #define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK) #define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U) #define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U) #define BCH_CTRL_COMPLETE_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK) #define BCH_CTRL_RSVD2_MASK (0x200U) #define BCH_CTRL_RSVD2_SHIFT (9U) #define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK) #define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U) #define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U) #define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK) #define BCH_CTRL_RSVD3_MASK (0xF800U) #define BCH_CTRL_RSVD3_SHIFT (11U) #define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK) #define BCH_CTRL_M2M_ENABLE_MASK (0x10000U) #define BCH_CTRL_M2M_ENABLE_SHIFT (16U) #define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK) #define BCH_CTRL_M2M_ENCODE_MASK (0x20000U) #define BCH_CTRL_M2M_ENCODE_SHIFT (17U) #define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK) #define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U) #define BCH_CTRL_M2M_LAYOUT_SHIFT (18U) #define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK) #define BCH_CTRL_RSVD4_MASK (0x300000U) #define BCH_CTRL_RSVD4_SHIFT (20U) #define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK) #define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U) #define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U) #define BCH_CTRL_DEBUGSYNDROME(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK) #define BCH_CTRL_RSVD5_MASK (0x3F800000U) #define BCH_CTRL_RSVD5_SHIFT (23U) #define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK) #define BCH_CTRL_CLKGATE_MASK (0x40000000U) #define BCH_CTRL_CLKGATE_SHIFT (30U) /*! CLKGATE * 0b0..Allow BCH to operate normally. * 0b1..Do not clock BCH gates in order to minimize power consumption. */ #define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK) #define BCH_CTRL_SFTRST_MASK (0x80000000U) #define BCH_CTRL_SFTRST_SHIFT (31U) /*! SFTRST * 0b0..Allow BCH to operate normally. * 0b1..Hold BCH in reset. */ #define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK) /*! @} */ /*! @name CTRL_SET - Hardware BCH ECC Accelerator Control Register */ /*! @{ */ #define BCH_CTRL_SET_COMPLETE_IRQ_MASK (0x1U) #define BCH_CTRL_SET_COMPLETE_IRQ_SHIFT (0U) #define BCH_CTRL_SET_COMPLETE_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_MASK) #define BCH_CTRL_SET_RSVD0_MASK (0x2U) #define BCH_CTRL_SET_RSVD0_SHIFT (1U) #define BCH_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD0_SHIFT)) & BCH_CTRL_SET_RSVD0_MASK) #define BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK (0x4U) #define BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT (2U) #define BCH_CTRL_SET_DEBUG_STALL_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK) #define BCH_CTRL_SET_BM_ERROR_IRQ_MASK (0x8U) #define BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT (3U) #define BCH_CTRL_SET_BM_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_SET_BM_ERROR_IRQ_MASK) #define BCH_CTRL_SET_RSVD1_MASK (0xF0U) #define BCH_CTRL_SET_RSVD1_SHIFT (4U) #define BCH_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD1_SHIFT)) & BCH_CTRL_SET_RSVD1_MASK) #define BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK (0x100U) #define BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT (8U) #define BCH_CTRL_SET_COMPLETE_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK) #define BCH_CTRL_SET_RSVD2_MASK (0x200U) #define BCH_CTRL_SET_RSVD2_SHIFT (9U) #define BCH_CTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD2_SHIFT)) & BCH_CTRL_SET_RSVD2_MASK) #define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK (0x400U) #define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT (10U) #define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK) #define BCH_CTRL_SET_RSVD3_MASK (0xF800U) #define BCH_CTRL_SET_RSVD3_SHIFT (11U) #define BCH_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD3_SHIFT)) & BCH_CTRL_SET_RSVD3_MASK) #define BCH_CTRL_SET_M2M_ENABLE_MASK (0x10000U) #define BCH_CTRL_SET_M2M_ENABLE_SHIFT (16U) #define BCH_CTRL_SET_M2M_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENABLE_SHIFT)) & BCH_CTRL_SET_M2M_ENABLE_MASK) #define BCH_CTRL_SET_M2M_ENCODE_MASK (0x20000U) #define BCH_CTRL_SET_M2M_ENCODE_SHIFT (17U) #define BCH_CTRL_SET_M2M_ENCODE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENCODE_SHIFT)) & BCH_CTRL_SET_M2M_ENCODE_MASK) #define BCH_CTRL_SET_M2M_LAYOUT_MASK (0xC0000U) #define BCH_CTRL_SET_M2M_LAYOUT_SHIFT (18U) #define BCH_CTRL_SET_M2M_LAYOUT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_LAYOUT_SHIFT)) & BCH_CTRL_SET_M2M_LAYOUT_MASK) #define BCH_CTRL_SET_RSVD4_MASK (0x300000U) #define BCH_CTRL_SET_RSVD4_SHIFT (20U) #define BCH_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD4_SHIFT)) & BCH_CTRL_SET_RSVD4_MASK) #define BCH_CTRL_SET_DEBUGSYNDROME_MASK (0x400000U) #define BCH_CTRL_SET_DEBUGSYNDROME_SHIFT (22U) #define BCH_CTRL_SET_DEBUGSYNDROME(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_SET_DEBUGSYNDROME_MASK) #define BCH_CTRL_SET_RSVD5_MASK (0x3F800000U) #define BCH_CTRL_SET_RSVD5_SHIFT (23U) #define BCH_CTRL_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD5_SHIFT)) & BCH_CTRL_SET_RSVD5_MASK) #define BCH_CTRL_SET_CLKGATE_MASK (0x40000000U) #define BCH_CTRL_SET_CLKGATE_SHIFT (30U) /*! CLKGATE * 0b0..Allow BCH to operate normally. * 0b1..Do not clock BCH gates in order to minimize power consumption. */ #define BCH_CTRL_SET_CLKGATE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_CLKGATE_SHIFT)) & BCH_CTRL_SET_CLKGATE_MASK) #define BCH_CTRL_SET_SFTRST_MASK (0x80000000U) #define BCH_CTRL_SET_SFTRST_SHIFT (31U) /*! SFTRST * 0b0..Allow BCH to operate normally. * 0b1..Hold BCH in reset. */ #define BCH_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_SFTRST_SHIFT)) & BCH_CTRL_SET_SFTRST_MASK) /*! @} */ /*! @name CTRL_CLR - Hardware BCH ECC Accelerator Control Register */ /*! @{ */ #define BCH_CTRL_CLR_COMPLETE_IRQ_MASK (0x1U) #define BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT (0U) #define BCH_CTRL_CLR_COMPLETE_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_MASK) #define BCH_CTRL_CLR_RSVD0_MASK (0x2U) #define BCH_CTRL_CLR_RSVD0_SHIFT (1U) #define BCH_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD0_SHIFT)) & BCH_CTRL_CLR_RSVD0_MASK) #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK (0x4U) #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT (2U) #define BCH_CTRL_CLR_DEBUG_STALL_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK) #define BCH_CTRL_CLR_BM_ERROR_IRQ_MASK (0x8U) #define BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT (3U) #define BCH_CTRL_CLR_BM_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_CLR_BM_ERROR_IRQ_MASK) #define BCH_CTRL_CLR_RSVD1_MASK (0xF0U) #define BCH_CTRL_CLR_RSVD1_SHIFT (4U) #define BCH_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD1_SHIFT)) & BCH_CTRL_CLR_RSVD1_MASK) #define BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK (0x100U) #define BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT (8U) #define BCH_CTRL_CLR_COMPLETE_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK) #define BCH_CTRL_CLR_RSVD2_MASK (0x200U) #define BCH_CTRL_CLR_RSVD2_SHIFT (9U) #define BCH_CTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD2_SHIFT)) & BCH_CTRL_CLR_RSVD2_MASK) #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK (0x400U) #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT (10U) #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK) #define BCH_CTRL_CLR_RSVD3_MASK (0xF800U) #define BCH_CTRL_CLR_RSVD3_SHIFT (11U) #define BCH_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD3_SHIFT)) & BCH_CTRL_CLR_RSVD3_MASK) #define BCH_CTRL_CLR_M2M_ENABLE_MASK (0x10000U) #define BCH_CTRL_CLR_M2M_ENABLE_SHIFT (16U) #define BCH_CTRL_CLR_M2M_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENABLE_SHIFT)) & BCH_CTRL_CLR_M2M_ENABLE_MASK) #define BCH_CTRL_CLR_M2M_ENCODE_MASK (0x20000U) #define BCH_CTRL_CLR_M2M_ENCODE_SHIFT (17U) #define BCH_CTRL_CLR_M2M_ENCODE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENCODE_SHIFT)) & BCH_CTRL_CLR_M2M_ENCODE_MASK) #define BCH_CTRL_CLR_M2M_LAYOUT_MASK (0xC0000U) #define BCH_CTRL_CLR_M2M_LAYOUT_SHIFT (18U) #define BCH_CTRL_CLR_M2M_LAYOUT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_LAYOUT_SHIFT)) & BCH_CTRL_CLR_M2M_LAYOUT_MASK) #define BCH_CTRL_CLR_RSVD4_MASK (0x300000U) #define BCH_CTRL_CLR_RSVD4_SHIFT (20U) #define BCH_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD4_SHIFT)) & BCH_CTRL_CLR_RSVD4_MASK) #define BCH_CTRL_CLR_DEBUGSYNDROME_MASK (0x400000U) #define BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT (22U) #define BCH_CTRL_CLR_DEBUGSYNDROME(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_CLR_DEBUGSYNDROME_MASK) #define BCH_CTRL_CLR_RSVD5_MASK (0x3F800000U) #define BCH_CTRL_CLR_RSVD5_SHIFT (23U) #define BCH_CTRL_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD5_SHIFT)) & BCH_CTRL_CLR_RSVD5_MASK) #define BCH_CTRL_CLR_CLKGATE_MASK (0x40000000U) #define BCH_CTRL_CLR_CLKGATE_SHIFT (30U) /*! CLKGATE * 0b0..Allow BCH to operate normally. * 0b1..Do not clock BCH gates in order to minimize power consumption. */ #define BCH_CTRL_CLR_CLKGATE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_CLKGATE_SHIFT)) & BCH_CTRL_CLR_CLKGATE_MASK) #define BCH_CTRL_CLR_SFTRST_MASK (0x80000000U) #define BCH_CTRL_CLR_SFTRST_SHIFT (31U) /*! SFTRST * 0b0..Allow BCH to operate normally. * 0b1..Hold BCH in reset. */ #define BCH_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_SFTRST_SHIFT)) & BCH_CTRL_CLR_SFTRST_MASK) /*! @} */ /*! @name CTRL_TOG - Hardware BCH ECC Accelerator Control Register */ /*! @{ */ #define BCH_CTRL_TOG_COMPLETE_IRQ_MASK (0x1U) #define BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT (0U) #define BCH_CTRL_TOG_COMPLETE_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_MASK) #define BCH_CTRL_TOG_RSVD0_MASK (0x2U) #define BCH_CTRL_TOG_RSVD0_SHIFT (1U) #define BCH_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD0_SHIFT)) & BCH_CTRL_TOG_RSVD0_MASK) #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK (0x4U) #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT (2U) #define BCH_CTRL_TOG_DEBUG_STALL_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK) #define BCH_CTRL_TOG_BM_ERROR_IRQ_MASK (0x8U) #define BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT (3U) #define BCH_CTRL_TOG_BM_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_TOG_BM_ERROR_IRQ_MASK) #define BCH_CTRL_TOG_RSVD1_MASK (0xF0U) #define BCH_CTRL_TOG_RSVD1_SHIFT (4U) #define BCH_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD1_SHIFT)) & BCH_CTRL_TOG_RSVD1_MASK) #define BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK (0x100U) #define BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT (8U) #define BCH_CTRL_TOG_COMPLETE_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK) #define BCH_CTRL_TOG_RSVD2_MASK (0x200U) #define BCH_CTRL_TOG_RSVD2_SHIFT (9U) #define BCH_CTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD2_SHIFT)) & BCH_CTRL_TOG_RSVD2_MASK) #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK (0x400U) #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT (10U) #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK) #define BCH_CTRL_TOG_RSVD3_MASK (0xF800U) #define BCH_CTRL_TOG_RSVD3_SHIFT (11U) #define BCH_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD3_SHIFT)) & BCH_CTRL_TOG_RSVD3_MASK) #define BCH_CTRL_TOG_M2M_ENABLE_MASK (0x10000U) #define BCH_CTRL_TOG_M2M_ENABLE_SHIFT (16U) #define BCH_CTRL_TOG_M2M_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENABLE_SHIFT)) & BCH_CTRL_TOG_M2M_ENABLE_MASK) #define BCH_CTRL_TOG_M2M_ENCODE_MASK (0x20000U) #define BCH_CTRL_TOG_M2M_ENCODE_SHIFT (17U) #define BCH_CTRL_TOG_M2M_ENCODE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENCODE_SHIFT)) & BCH_CTRL_TOG_M2M_ENCODE_MASK) #define BCH_CTRL_TOG_M2M_LAYOUT_MASK (0xC0000U) #define BCH_CTRL_TOG_M2M_LAYOUT_SHIFT (18U) #define BCH_CTRL_TOG_M2M_LAYOUT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_LAYOUT_SHIFT)) & BCH_CTRL_TOG_M2M_LAYOUT_MASK) #define BCH_CTRL_TOG_RSVD4_MASK (0x300000U) #define BCH_CTRL_TOG_RSVD4_SHIFT (20U) #define BCH_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD4_SHIFT)) & BCH_CTRL_TOG_RSVD4_MASK) #define BCH_CTRL_TOG_DEBUGSYNDROME_MASK (0x400000U) #define BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT (22U) #define BCH_CTRL_TOG_DEBUGSYNDROME(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_TOG_DEBUGSYNDROME_MASK) #define BCH_CTRL_TOG_RSVD5_MASK (0x3F800000U) #define BCH_CTRL_TOG_RSVD5_SHIFT (23U) #define BCH_CTRL_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD5_SHIFT)) & BCH_CTRL_TOG_RSVD5_MASK) #define BCH_CTRL_TOG_CLKGATE_MASK (0x40000000U) #define BCH_CTRL_TOG_CLKGATE_SHIFT (30U) /*! CLKGATE * 0b0..Allow BCH to operate normally. * 0b1..Do not clock BCH gates in order to minimize power consumption. */ #define BCH_CTRL_TOG_CLKGATE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_CLKGATE_SHIFT)) & BCH_CTRL_TOG_CLKGATE_MASK) #define BCH_CTRL_TOG_SFTRST_MASK (0x80000000U) #define BCH_CTRL_TOG_SFTRST_SHIFT (31U) /*! SFTRST * 0b0..Allow BCH to operate normally. * 0b1..Hold BCH in reset. */ #define BCH_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_SFTRST_SHIFT)) & BCH_CTRL_TOG_SFTRST_MASK) /*! @} */ /*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */ /*! @{ */ #define BCH_STATUS0_RSVD0_MASK (0x3U) #define BCH_STATUS0_RSVD0_SHIFT (0U) #define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK) #define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U) #define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U) #define BCH_STATUS0_UNCORRECTABLE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK) #define BCH_STATUS0_CORRECTED_MASK (0x8U) #define BCH_STATUS0_CORRECTED_SHIFT (3U) #define BCH_STATUS0_CORRECTED(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK) #define BCH_STATUS0_ALLONES_MASK (0x10U) #define BCH_STATUS0_ALLONES_SHIFT (4U) #define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK) #define BCH_STATUS0_RSVD1_MASK (0xE0U) #define BCH_STATUS0_RSVD1_SHIFT (5U) #define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK) #define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U) #define BCH_STATUS0_STATUS_BLK0_SHIFT (8U) /*! STATUS_BLK0 * 0b00000000..No errors found on block. * 0b00000001..One error found on block. * 0b00000010..One errors found on block. * 0b00000011..One errors found on block. * 0b00000100..One errors found on block. * 0b11111110..Block exhibited uncorrectable errors. * 0b11111111..Page is erased. */ #define BCH_STATUS0_STATUS_BLK0(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK) #define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U) #define BCH_STATUS0_COMPLETED_CE_SHIFT (16U) #define BCH_STATUS0_COMPLETED_CE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK) #define BCH_STATUS0_HANDLE_MASK (0xFFF00000U) #define BCH_STATUS0_HANDLE_SHIFT (20U) #define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK) /*! @} */ /*! @name MODE - Hardware ECC Accelerator Mode Register */ /*! @{ */ #define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU) #define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U) #define BCH_MODE_ERASE_THRESHOLD(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK) #define BCH_MODE_RSVD_MASK (0xFFFFFF00U) #define BCH_MODE_RSVD_SHIFT (8U) #define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK) /*! @} */ /*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */ /*! @{ */ #define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU) #define BCH_ENCODEPTR_ADDR_SHIFT (0U) #define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK) /*! @} */ /*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */ /*! @{ */ #define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU) #define BCH_DATAPTR_ADDR_SHIFT (0U) #define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK) /*! @} */ /*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */ /*! @{ */ #define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU) #define BCH_METAPTR_ADDR_SHIFT (0U) #define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK) /*! @} */ /*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */ /*! @{ */ #define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U) #define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U) #define BCH_LAYOUTSELECT_CS0_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK) #define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU) #define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U) #define BCH_LAYOUTSELECT_CS1_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK) #define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U) #define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U) #define BCH_LAYOUTSELECT_CS2_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK) #define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U) #define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U) #define BCH_LAYOUTSELECT_CS3_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK) #define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U) #define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U) #define BCH_LAYOUTSELECT_CS4_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK) #define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U) #define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U) #define BCH_LAYOUTSELECT_CS5_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK) #define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U) #define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U) #define BCH_LAYOUTSELECT_CS6_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK) #define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U) #define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U) #define BCH_LAYOUTSELECT_CS7_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK) #define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U) #define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U) #define BCH_LAYOUTSELECT_CS8_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK) #define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U) #define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U) #define BCH_LAYOUTSELECT_CS9_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK) #define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U) #define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U) #define BCH_LAYOUTSELECT_CS10_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK) #define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U) #define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U) #define BCH_LAYOUTSELECT_CS11_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK) #define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U) #define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U) #define BCH_LAYOUTSELECT_CS12_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK) #define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U) #define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U) #define BCH_LAYOUTSELECT_CS13_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK) #define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U) #define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U) #define BCH_LAYOUTSELECT_CS14_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK) #define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U) #define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U) #define BCH_LAYOUTSELECT_CS15_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK) /*! @} */ /*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */ /*! @{ */ #define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0x3FFU) #define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U) #define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK) #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK (0x400U) #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT (10U) #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK) #define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF800U) #define BCH_FLASH0LAYOUT0_ECC0_SHIFT (11U) /*! ECC0 * 0b00000..No ECC to be performed * 0b00001..ECC 2 to be performed * 0b00010..ECC 4 to be performed * 0b11110..ECC 60 to be performed * 0b11111..ECC 62 to be performed */ #define BCH_FLASH0LAYOUT0_ECC0(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK) #define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U) #define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U) #define BCH_FLASH0LAYOUT0_META_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK) #define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U) #define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U) #define BCH_FLASH0LAYOUT0_NBLOCKS(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK) /*! @} */ /*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */ /*! @{ */ #define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0x3FFU) #define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U) #define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK) #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK (0x400U) #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT (10U) #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK) #define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF800U) #define BCH_FLASH0LAYOUT1_ECCN_SHIFT (11U) /*! ECCN * 0b00000..No ECC to be performed * 0b00001..ECC 2 to be performed * 0b00010..ECC 4 to be performed * 0b11110..ECC 60 to be performed * 0b11111..ECC 62 to be performed */ #define BCH_FLASH0LAYOUT1_ECCN(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK) #define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) #define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U) #define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK) /*! @} */ /*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */ /*! @{ */ #define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0x3FFU) #define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U) #define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK) #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK (0x400U) #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT (10U) #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK) #define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF800U) #define BCH_FLASH1LAYOUT0_ECC0_SHIFT (11U) /*! ECC0 * 0b00000..No ECC to be performed * 0b00001..ECC 2 to be performed * 0b00010..ECC 4 to be performed * 0b11110..ECC 60 to be performed * 0b11111..ECC 62 to be performed */ #define BCH_FLASH1LAYOUT0_ECC0(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK) #define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U) #define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U) #define BCH_FLASH1LAYOUT0_META_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK) #define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U) #define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U) #define BCH_FLASH1LAYOUT0_NBLOCKS(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK) /*! @} */ /*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */ /*! @{ */ #define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0x3FFU) #define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U) #define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK) #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK (0x400U) #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT (10U) #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK) #define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF800U) #define BCH_FLASH1LAYOUT1_ECCN_SHIFT (11U) /*! ECCN * 0b00000..No ECC to be performed * 0b00001..ECC 2 to be performed * 0b00010..ECC 4 to be performed * 0b11110..ECC 60 to be performed * 0b11111..ECC 62 to be performed */ #define BCH_FLASH1LAYOUT1_ECCN(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK) #define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) #define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U) #define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK) /*! @} */ /*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */ /*! @{ */ #define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0x3FFU) #define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U) #define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK) #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK (0x400U) #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT (10U) #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK) #define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF800U) #define BCH_FLASH2LAYOUT0_ECC0_SHIFT (11U) /*! ECC0 * 0b00000..No ECC to be performed * 0b00001..ECC 2 to be performed * 0b00010..ECC 4 to be performed * 0b11110..ECC 60 to be performed * 0b11111..ECC 62 to be performed */ #define BCH_FLASH2LAYOUT0_ECC0(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK) #define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U) #define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U) #define BCH_FLASH2LAYOUT0_META_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK) #define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U) #define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U) #define BCH_FLASH2LAYOUT0_NBLOCKS(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK) /*! @} */ /*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */ /*! @{ */ #define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0x3FFU) #define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U) #define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK) #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK (0x400U) #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT (10U) #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK) #define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF800U) #define BCH_FLASH2LAYOUT1_ECCN_SHIFT (11U) /*! ECCN * 0b00000..No ECC to be performed * 0b00001..ECC 2 to be performed * 0b00010..ECC 4 to be performed * 0b11110..ECC 60 to be performed * 0b11111..ECC 62 to be performed */ #define BCH_FLASH2LAYOUT1_ECCN(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK) #define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) #define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U) #define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK) /*! @} */ /*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */ /*! @{ */ #define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0x3FFU) #define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U) #define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK) #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK (0x400U) #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT (10U) #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK) #define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF800U) #define BCH_FLASH3LAYOUT0_ECC0_SHIFT (11U) /*! ECC0 * 0b00000..No ECC to be performed * 0b00001..ECC 2 to be performed * 0b00010..ECC 4 to be performed * 0b11110..ECC 60 to be performed * 0b11111..ECC 62 to be performed */ #define BCH_FLASH3LAYOUT0_ECC0(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK) #define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U) #define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U) #define BCH_FLASH3LAYOUT0_META_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK) #define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U) #define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U) #define BCH_FLASH3LAYOUT0_NBLOCKS(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK) /*! @} */ /*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */ /*! @{ */ #define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0x3FFU) #define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U) #define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK) #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK (0x400U) #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT (10U) #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK) #define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF800U) #define BCH_FLASH3LAYOUT1_ECCN_SHIFT (11U) /*! ECCN * 0b00000..No ECC to be performed * 0b00001..ECC 2 to be performed * 0b00010..ECC 4 to be performed * 0b11110..ECC 60 to be performed * 0b11111..ECC 62 to be performed */ #define BCH_FLASH3LAYOUT1_ECCN(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK) #define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) #define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U) #define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK) /*! @} */ /*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */ /*! @{ */ #define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU) #define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U) #define BCH_DEBUG0_DEBUG_REG_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK) #define BCH_DEBUG0_RSVD0_MASK (0xC0U) #define BCH_DEBUG0_RSVD0_SHIFT (6U) #define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK) #define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK (0x100U) #define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT (8U) /*! BM_KES_TEST_BYPASS * 0b0..Bus master address generator for SYND_GEN writes operates normally. * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. */ #define BCH_DEBUG0_BM_KES_TEST_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK) #define BCH_DEBUG0_KES_DEBUG_STALL_MASK (0x200U) #define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT (9U) /*! KES_DEBUG_STALL * 0b0..KES FSM proceeds to next block supplied by bus master. * 0b1..KES FSM waits after current equations are solved and the search engine is started. */ #define BCH_DEBUG0_KES_DEBUG_STALL(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK) #define BCH_DEBUG0_KES_DEBUG_STEP_MASK (0x400U) #define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT (10U) #define BCH_DEBUG0_KES_DEBUG_STEP(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK) #define BCH_DEBUG0_KES_STANDALONE_MASK (0x800U) #define BCH_DEBUG0_KES_STANDALONE_SHIFT (11U) /*! KES_STANDALONE * 0b0..Bus master address generator for SYND_GEN writes operates normally. * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. */ #define BCH_DEBUG0_KES_STANDALONE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK) #define BCH_DEBUG0_KES_DEBUG_KICK_MASK (0x1000U) #define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT (12U) #define BCH_DEBUG0_KES_DEBUG_KICK(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK) #define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK (0x2000U) #define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT (13U) /*! KES_DEBUG_MODE4K * 0b1..Mode is set for 4K NAND pages. * 0b1..Mode is set for 2K NAND pages. */ #define BCH_DEBUG0_KES_DEBUG_MODE4K(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK) #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) /*! KES_DEBUG_PAYLOAD_FLAG * 0b1..Payload is set for 512 bytes data block. * 0b1..Payload is set for 65 or 19 bytes auxiliary block. */ #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK) #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT (15U) #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK) #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) /*! KES_DEBUG_SYNDROME_SYMBOL * 0b000000000..Bus master address generator for SYND_GEN writes operates normally. * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block. */ #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & \ BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK) #define BCH_DEBUG0_RSVD1_MASK (0xFE000000U) #define BCH_DEBUG0_RSVD1_SHIFT (25U) #define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK) /*! @} */ /*! @name DEBUG0_SET - Hardware BCH ECC Debug Register0 */ /*! @{ */ #define BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK (0x3FU) #define BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT (0U) #define BCH_DEBUG0_SET_DEBUG_REG_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK) #define BCH_DEBUG0_SET_RSVD0_MASK (0xC0U) #define BCH_DEBUG0_SET_RSVD0_SHIFT (6U) #define BCH_DEBUG0_SET_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD0_SHIFT)) & BCH_DEBUG0_SET_RSVD0_MASK) #define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK (0x100U) #define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT (8U) /*! BM_KES_TEST_BYPASS * 0b0..Bus master address generator for SYND_GEN writes operates normally. * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. */ #define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK) #define BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK (0x200U) #define BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT (9U) /*! KES_DEBUG_STALL * 0b0..KES FSM proceeds to next block supplied by bus master. * 0b1..KES FSM waits after current equations are solved and the search engine is started. */ #define BCH_DEBUG0_SET_KES_DEBUG_STALL(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK) #define BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK (0x400U) #define BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT (10U) #define BCH_DEBUG0_SET_KES_DEBUG_STEP(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK) #define BCH_DEBUG0_SET_KES_STANDALONE_MASK (0x800U) #define BCH_DEBUG0_SET_KES_STANDALONE_SHIFT (11U) /*! KES_STANDALONE * 0b0..Bus master address generator for SYND_GEN writes operates normally. * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. */ #define BCH_DEBUG0_SET_KES_STANDALONE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_SET_KES_STANDALONE_MASK) #define BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK (0x1000U) #define BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT (12U) #define BCH_DEBUG0_SET_KES_DEBUG_KICK(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK) #define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK (0x2000U) #define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT (13U) /*! KES_DEBUG_MODE4K * 0b1..Mode is set for 4K NAND pages. * 0b1..Mode is set for 2K NAND pages. */ #define BCH_DEBUG0_SET_KES_DEBUG_MODE4K(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK) #define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) #define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) /*! KES_DEBUG_PAYLOAD_FLAG * 0b1..Payload is set for 512 bytes data block. * 0b1..Payload is set for 65 or 19 bytes auxiliary block. */ #define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & \ BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK) #define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) #define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT (15U) #define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT)) & \ BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK) #define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) #define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) /*! KES_DEBUG_SYNDROME_SYMBOL * 0b000000000..Bus master address generator for SYND_GEN writes operates normally. * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block. */ #define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & \ BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK) #define BCH_DEBUG0_SET_RSVD1_MASK (0xFE000000U) #define BCH_DEBUG0_SET_RSVD1_SHIFT (25U) #define BCH_DEBUG0_SET_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD1_SHIFT)) & BCH_DEBUG0_SET_RSVD1_MASK) /*! @} */ /*! @name DEBUG0_CLR - Hardware BCH ECC Debug Register0 */ /*! @{ */ #define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK (0x3FU) #define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT (0U) #define BCH_DEBUG0_CLR_DEBUG_REG_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK) #define BCH_DEBUG0_CLR_RSVD0_MASK (0xC0U) #define BCH_DEBUG0_CLR_RSVD0_SHIFT (6U) #define BCH_DEBUG0_CLR_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD0_SHIFT)) & BCH_DEBUG0_CLR_RSVD0_MASK) #define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK (0x100U) #define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT (8U) /*! BM_KES_TEST_BYPASS * 0b0..Bus master address generator for SYND_GEN writes operates normally. * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. */ #define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK) #define BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK (0x200U) #define BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT (9U) /*! KES_DEBUG_STALL * 0b0..KES FSM proceeds to next block supplied by bus master. * 0b1..KES FSM waits after current equations are solved and the search engine is started. */ #define BCH_DEBUG0_CLR_KES_DEBUG_STALL(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK) #define BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK (0x400U) #define BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT (10U) #define BCH_DEBUG0_CLR_KES_DEBUG_STEP(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK) #define BCH_DEBUG0_CLR_KES_STANDALONE_MASK (0x800U) #define BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT (11U) /*! KES_STANDALONE * 0b0..Bus master address generator for SYND_GEN writes operates normally. * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. */ #define BCH_DEBUG0_CLR_KES_STANDALONE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_CLR_KES_STANDALONE_MASK) #define BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK (0x1000U) #define BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT (12U) #define BCH_DEBUG0_CLR_KES_DEBUG_KICK(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK) #define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK (0x2000U) #define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT (13U) /*! KES_DEBUG_MODE4K * 0b1..Mode is set for 4K NAND pages. * 0b1..Mode is set for 2K NAND pages. */ #define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK) #define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) #define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) /*! KES_DEBUG_PAYLOAD_FLAG * 0b1..Payload is set for 512 bytes data block. * 0b1..Payload is set for 65 or 19 bytes auxiliary block. */ #define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & \ BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK) #define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) #define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT (15U) #define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT)) & \ BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK) #define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) #define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) /*! KES_DEBUG_SYNDROME_SYMBOL * 0b000000000..Bus master address generator for SYND_GEN writes operates normally. * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block. */ #define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & \ BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK) #define BCH_DEBUG0_CLR_RSVD1_MASK (0xFE000000U) #define BCH_DEBUG0_CLR_RSVD1_SHIFT (25U) #define BCH_DEBUG0_CLR_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD1_SHIFT)) & BCH_DEBUG0_CLR_RSVD1_MASK) /*! @} */ /*! @name DEBUG0_TOG - Hardware BCH ECC Debug Register0 */ /*! @{ */ #define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK (0x3FU) #define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT (0U) #define BCH_DEBUG0_TOG_DEBUG_REG_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK) #define BCH_DEBUG0_TOG_RSVD0_MASK (0xC0U) #define BCH_DEBUG0_TOG_RSVD0_SHIFT (6U) #define BCH_DEBUG0_TOG_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD0_SHIFT)) & BCH_DEBUG0_TOG_RSVD0_MASK) #define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK (0x100U) #define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT (8U) /*! BM_KES_TEST_BYPASS * 0b0..Bus master address generator for SYND_GEN writes operates normally. * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. */ #define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK) #define BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK (0x200U) #define BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT (9U) /*! KES_DEBUG_STALL * 0b0..KES FSM proceeds to next block supplied by bus master. * 0b1..KES FSM waits after current equations are solved and the search engine is started. */ #define BCH_DEBUG0_TOG_KES_DEBUG_STALL(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK) #define BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK (0x400U) #define BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT (10U) #define BCH_DEBUG0_TOG_KES_DEBUG_STEP(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK) #define BCH_DEBUG0_TOG_KES_STANDALONE_MASK (0x800U) #define BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT (11U) /*! KES_STANDALONE * 0b0..Bus master address generator for SYND_GEN writes operates normally. * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. */ #define BCH_DEBUG0_TOG_KES_STANDALONE(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_TOG_KES_STANDALONE_MASK) #define BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK (0x1000U) #define BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT (12U) #define BCH_DEBUG0_TOG_KES_DEBUG_KICK(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK) #define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK (0x2000U) #define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT (13U) /*! KES_DEBUG_MODE4K * 0b1..Mode is set for 4K NAND pages. * 0b1..Mode is set for 2K NAND pages. */ #define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK) #define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) #define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) /*! KES_DEBUG_PAYLOAD_FLAG * 0b1..Payload is set for 512 bytes data block. * 0b1..Payload is set for 65 or 19 bytes auxiliary block. */ #define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & \ BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK) #define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) #define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT (15U) #define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT)) & \ BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK) #define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) #define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) /*! KES_DEBUG_SYNDROME_SYMBOL * 0b000000000..Bus master address generator for SYND_GEN writes operates normally. * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block. */ #define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & \ BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK) #define BCH_DEBUG0_TOG_RSVD1_MASK (0xFE000000U) #define BCH_DEBUG0_TOG_RSVD1_SHIFT (25U) #define BCH_DEBUG0_TOG_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD1_SHIFT)) & BCH_DEBUG0_TOG_RSVD1_MASK) /*! @} */ /*! @name DBGKESREAD - KES Debug Read Register */ /*! @{ */ #define BCH_DBGKESREAD_VALUES_MASK (0xFFFFFFFFU) #define BCH_DBGKESREAD_VALUES_SHIFT (0U) #define BCH_DBGKESREAD_VALUES(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK) /*! @} */ /*! @name DBGCSFEREAD - Chien Search Debug Read Register */ /*! @{ */ #define BCH_DBGCSFEREAD_VALUES_MASK (0xFFFFFFFFU) #define BCH_DBGCSFEREAD_VALUES_SHIFT (0U) #define BCH_DBGCSFEREAD_VALUES(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK) /*! @} */ /*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */ /*! @{ */ #define BCH_DBGSYNDGENREAD_VALUES_MASK (0xFFFFFFFFU) #define BCH_DBGSYNDGENREAD_VALUES_SHIFT (0U) #define BCH_DBGSYNDGENREAD_VALUES(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK) /*! @} */ /*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */ /*! @{ */ #define BCH_DBGAHBMREAD_VALUES_MASK (0xFFFFFFFFU) #define BCH_DBGAHBMREAD_VALUES_SHIFT (0U) #define BCH_DBGAHBMREAD_VALUES(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK) /*! @} */ /*! @name BLOCKNAME - Block Name Register */ /*! @{ */ #define BCH_BLOCKNAME_NAME_MASK (0xFFFFFFFFU) #define BCH_BLOCKNAME_NAME_SHIFT (0U) #define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK) /*! @} */ /*! @name VERSION - BCH Version Register */ /*! @{ */ #define BCH_VERSION_STEP_MASK (0xFFFFU) #define BCH_VERSION_STEP_SHIFT (0U) #define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK) #define BCH_VERSION_MINOR_MASK (0xFF0000U) #define BCH_VERSION_MINOR_SHIFT (16U) #define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK) #define BCH_VERSION_MAJOR_MASK (0xFF000000U) #define BCH_VERSION_MAJOR_SHIFT (24U) #define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK) /*! @} */ /*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */ /*! @{ */ #define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK (0x1FFU) #define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT (0U) #define BCH_DEBUG1_ERASED_ZERO_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK) #define BCH_DEBUG1_RSVD_MASK (0x7FFFFE00U) #define BCH_DEBUG1_RSVD_SHIFT (9U) #define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK) #define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK (0x80000000U) #define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT (31U) /*! DEBUG1_PREERASECHK * 0b0..Turn off pre-erase check * 0b1..Turn on pre-erase check */ #define BCH_DEBUG1_DEBUG1_PREERASECHK(x) \ (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK) /*! @} */ /*! * @} */ /* end of group BCH_Register_Masks */ /* BCH - Peripheral instance base addresses */ /** Peripheral BCH base address */ #define BCH_BASE (0x33004000u) /** Peripheral BCH base pointer */ #define BCH ((BCH_Type *)BCH_BASE) /** Array initializer of BCH peripheral base addresses */ #define BCH_BASE_ADDRS \ { \ BCH_BASE \ } /** Array initializer of BCH peripheral base pointers */ #define BCH_BASE_PTRS \ { \ BCH \ } /** Interrupt vectors for the BCH peripheral type */ #define BCH_IRQS \ { \ BCH_IRQn \ } /*! * @} */ /* end of group BCH_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CCM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer * @{ */ /** CCM - Register Layout Typedef */ typedef struct { __IO uint32_t GPR0; /**< General Purpose Register, offset: 0x0 */ __IO uint32_t GPR0_SET; /**< General Purpose Register, offset: 0x4 */ __IO uint32_t GPR0_CLR; /**< General Purpose Register, offset: 0x8 */ __IO uint32_t GPR0_TOG; /**< General Purpose Register, offset: 0xC */ uint8_t RESERVED_0[2032]; struct { /* offset: 0x800, array step: 0x10 */ __IO uint32_t PLL_CTRL; /**< CCM PLL Control Register, array offset: 0x800, array step: 0x10 */ __IO uint32_t PLL_CTRL_SET; /**< CCM PLL Control Register, array offset: 0x804, array step: 0x10 */ __IO uint32_t PLL_CTRL_CLR; /**< CCM PLL Control Register, array offset: 0x808, array step: 0x10 */ __IO uint32_t PLL_CTRL_TOG; /**< CCM PLL Control Register, array offset: 0x80C, array step: 0x10 */ } PLL_CTRL[39]; uint8_t RESERVED_1[13712]; struct { /* offset: 0x4000, array step: 0x10 */ __IO uint32_t CCGR; /**< CCM Clock Gating Register, array offset: 0x4000, array step: 0x10 */ __IO uint32_t CCGR_SET; /**< CCM Clock Gating Register, array offset: 0x4004, array step: 0x10 */ __IO uint32_t CCGR_CLR; /**< CCM Clock Gating Register, array offset: 0x4008, array step: 0x10 */ __IO uint32_t CCGR_TOG; /**< CCM Clock Gating Register, array offset: 0x400C, array step: 0x10 */ } CCGR[103]; uint8_t RESERVED_2[14736]; struct { /* offset: 0x8000, array step: 0x80 */ __IO uint32_t TARGET_ROOT; /**< Target Register, array offset: 0x8000, array step: 0x80 */ __IO uint32_t TARGET_ROOT_SET; /**< Target Register, array offset: 0x8004, array step: 0x80 */ __IO uint32_t TARGET_ROOT_CLR; /**< Target Register, array offset: 0x8008, array step: 0x80 */ __IO uint32_t TARGET_ROOT_TOG; /**< Target Register, array offset: 0x800C, array step: 0x80 */ __IO uint32_t MISC; /**< Miscellaneous Register, array offset: 0x8010, array step: 0x80 */ __IO uint32_t MISC_ROOT_SET; /**< Miscellaneous Register, array offset: 0x8014, array step: 0x80 */ __IO uint32_t MISC_ROOT_CLR; /**< Miscellaneous Register, array offset: 0x8018, array step: 0x80 */ __IO uint32_t MISC_ROOT_TOG; /**< Miscellaneous Register, array offset: 0x801C, array step: 0x80 */ __IO uint32_t POST; /**< Post Divider Register, array offset: 0x8020, array step: 0x80 */ __IO uint32_t POST_ROOT_SET; /**< Post Divider Register, array offset: 0x8024, array step: 0x80 */ __IO uint32_t POST_ROOT_CLR; /**< Post Divider Register, array offset: 0x8028, array step: 0x80 */ __IO uint32_t POST_ROOT_TOG; /**< Post Divider Register, array offset: 0x802C, array step: 0x80 */ __IO uint32_t PRE; /**< Pre Divider Register, array offset: 0x8030, array step: 0x80 */ __IO uint32_t PRE_ROOT_SET; /**< Pre Divider Register, array offset: 0x8034, array step: 0x80 */ __IO uint32_t PRE_ROOT_CLR; /**< Pre Divider Register, array offset: 0x8038, array step: 0x80 */ __IO uint32_t PRE_ROOT_TOG; /**< Pre Divider Register, array offset: 0x803C, array step: 0x80 */ uint8_t RESERVED_0[48]; __IO uint32_t ACCESS_CTRL; /**< Access Control Register, array offset: 0x8070, array step: 0x80 */ __IO uint32_t ACCESS_CTRL_ROOT_SET; /**< Access Control Register, array offset: 0x8074, array step: 0x80 */ __IO uint32_t ACCESS_CTRL_ROOT_CLR; /**< Access Control Register, array offset: 0x8078, array step: 0x80 */ __IO uint32_t ACCESS_CTRL_ROOT_TOG; /**< Access Control Register, array offset: 0x807C, array step: 0x80 */ } ROOT[135]; } CCM_Type; /* ---------------------------------------------------------------------------- -- CCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CCM_Register_Masks CCM Register Masks * @{ */ /*! @name GPR0 - General Purpose Register */ /*! @{ */ #define CCM_GPR0_GP0_MASK (0xFFFFFFFFU) #define CCM_GPR0_GP0_SHIFT (0U) #define CCM_GPR0_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_GP0_SHIFT)) & CCM_GPR0_GP0_MASK) /*! @} */ /*! @name GPR0_SET - General Purpose Register */ /*! @{ */ #define CCM_GPR0_SET_GP0_MASK (0xFFFFFFFFU) #define CCM_GPR0_SET_GP0_SHIFT (0U) #define CCM_GPR0_SET_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_SET_GP0_SHIFT)) & CCM_GPR0_SET_GP0_MASK) /*! @} */ /*! @name GPR0_CLR - General Purpose Register */ /*! @{ */ #define CCM_GPR0_CLR_GP0_MASK (0xFFFFFFFFU) #define CCM_GPR0_CLR_GP0_SHIFT (0U) #define CCM_GPR0_CLR_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_CLR_GP0_SHIFT)) & CCM_GPR0_CLR_GP0_MASK) /*! @} */ /*! @name GPR0_TOG - General Purpose Register */ /*! @{ */ #define CCM_GPR0_TOG_GP0_MASK (0xFFFFFFFFU) #define CCM_GPR0_TOG_GP0_SHIFT (0U) #define CCM_GPR0_TOG_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_TOG_GP0_SHIFT)) & CCM_GPR0_TOG_GP0_MASK) /*! @} */ /*! @name PLL_CTRL - CCM PLL Control Register */ /*! @{ */ #define CCM_PLL_CTRL_SETTING0_MASK (0x3U) #define CCM_PLL_CTRL_SETTING0_SHIFT (0U) /*! SETTING0 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_PLL_CTRL_SETTING0(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING0_SHIFT)) & CCM_PLL_CTRL_SETTING0_MASK) #define CCM_PLL_CTRL_SETTING1_MASK (0x30U) #define CCM_PLL_CTRL_SETTING1_SHIFT (4U) /*! SETTING1 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_PLL_CTRL_SETTING1(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING1_SHIFT)) & CCM_PLL_CTRL_SETTING1_MASK) #define CCM_PLL_CTRL_SETTING2_MASK (0x300U) #define CCM_PLL_CTRL_SETTING2_SHIFT (8U) /*! SETTING2 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_PLL_CTRL_SETTING2(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING2_SHIFT)) & CCM_PLL_CTRL_SETTING2_MASK) #define CCM_PLL_CTRL_SETTING3_MASK (0x3000U) #define CCM_PLL_CTRL_SETTING3_SHIFT (12U) /*! SETTING3 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_PLL_CTRL_SETTING3(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING3_SHIFT)) & CCM_PLL_CTRL_SETTING3_MASK) /*! @} */ /* The count of CCM_PLL_CTRL */ #define CCM_PLL_CTRL_COUNT (39U) /*! @name PLL_CTRL_SET - CCM PLL Control Register */ /*! @{ */ #define CCM_PLL_CTRL_SET_SETTING0_MASK (0x3U) #define CCM_PLL_CTRL_SET_SETTING0_SHIFT (0U) /*! SETTING0 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_PLL_CTRL_SET_SETTING0(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING0_SHIFT)) & CCM_PLL_CTRL_SET_SETTING0_MASK) #define CCM_PLL_CTRL_SET_SETTING1_MASK (0x30U) #define CCM_PLL_CTRL_SET_SETTING1_SHIFT (4U) /*! SETTING1 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_PLL_CTRL_SET_SETTING1(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING1_SHIFT)) & CCM_PLL_CTRL_SET_SETTING1_MASK) #define CCM_PLL_CTRL_SET_SETTING2_MASK (0x300U) #define CCM_PLL_CTRL_SET_SETTING2_SHIFT (8U) /*! SETTING2 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_PLL_CTRL_SET_SETTING2(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING2_SHIFT)) & CCM_PLL_CTRL_SET_SETTING2_MASK) #define CCM_PLL_CTRL_SET_SETTING3_MASK (0x3000U) #define CCM_PLL_CTRL_SET_SETTING3_SHIFT (12U) /*! SETTING3 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_PLL_CTRL_SET_SETTING3(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING3_SHIFT)) & CCM_PLL_CTRL_SET_SETTING3_MASK) /*! @} */ /* The count of CCM_PLL_CTRL_SET */ #define CCM_PLL_CTRL_SET_COUNT (39U) /*! @name PLL_CTRL_CLR - CCM PLL Control Register */ /*! @{ */ #define CCM_PLL_CTRL_CLR_SETTING0_MASK (0x3U) #define CCM_PLL_CTRL_CLR_SETTING0_SHIFT (0U) /*! SETTING0 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_PLL_CTRL_CLR_SETTING0(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING0_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING0_MASK) #define CCM_PLL_CTRL_CLR_SETTING1_MASK (0x30U) #define CCM_PLL_CTRL_CLR_SETTING1_SHIFT (4U) /*! SETTING1 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_PLL_CTRL_CLR_SETTING1(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING1_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING1_MASK) #define CCM_PLL_CTRL_CLR_SETTING2_MASK (0x300U) #define CCM_PLL_CTRL_CLR_SETTING2_SHIFT (8U) /*! SETTING2 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_PLL_CTRL_CLR_SETTING2(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING2_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING2_MASK) #define CCM_PLL_CTRL_CLR_SETTING3_MASK (0x3000U) #define CCM_PLL_CTRL_CLR_SETTING3_SHIFT (12U) /*! SETTING3 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_PLL_CTRL_CLR_SETTING3(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING3_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING3_MASK) /*! @} */ /* The count of CCM_PLL_CTRL_CLR */ #define CCM_PLL_CTRL_CLR_COUNT (39U) /*! @name PLL_CTRL_TOG - CCM PLL Control Register */ /*! @{ */ #define CCM_PLL_CTRL_TOG_SETTING0_MASK (0x3U) #define CCM_PLL_CTRL_TOG_SETTING0_SHIFT (0U) /*! SETTING0 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_PLL_CTRL_TOG_SETTING0(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING0_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING0_MASK) #define CCM_PLL_CTRL_TOG_SETTING1_MASK (0x30U) #define CCM_PLL_CTRL_TOG_SETTING1_SHIFT (4U) /*! SETTING1 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_PLL_CTRL_TOG_SETTING1(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING1_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING1_MASK) #define CCM_PLL_CTRL_TOG_SETTING2_MASK (0x300U) #define CCM_PLL_CTRL_TOG_SETTING2_SHIFT (8U) /*! SETTING2 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_PLL_CTRL_TOG_SETTING2(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING2_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING2_MASK) #define CCM_PLL_CTRL_TOG_SETTING3_MASK (0x3000U) #define CCM_PLL_CTRL_TOG_SETTING3_SHIFT (12U) /*! SETTING3 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_PLL_CTRL_TOG_SETTING3(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING3_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING3_MASK) /*! @} */ /* The count of CCM_PLL_CTRL_TOG */ #define CCM_PLL_CTRL_TOG_COUNT (39U) /*! @name CCGR - CCM Clock Gating Register */ /*! @{ */ #define CCM_CCGR_SETTING0_MASK (0x3U) #define CCM_CCGR_SETTING0_SHIFT (0U) /*! SETTING0 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_CCGR_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING0_SHIFT)) & CCM_CCGR_SETTING0_MASK) #define CCM_CCGR_SETTING1_MASK (0x30U) #define CCM_CCGR_SETTING1_SHIFT (4U) /*! SETTING1 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_CCGR_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING1_SHIFT)) & CCM_CCGR_SETTING1_MASK) #define CCM_CCGR_SETTING2_MASK (0x300U) #define CCM_CCGR_SETTING2_SHIFT (8U) /*! SETTING2 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_CCGR_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING2_SHIFT)) & CCM_CCGR_SETTING2_MASK) #define CCM_CCGR_SETTING3_MASK (0x3000U) #define CCM_CCGR_SETTING3_SHIFT (12U) /*! SETTING3 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_CCGR_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING3_SHIFT)) & CCM_CCGR_SETTING3_MASK) /*! @} */ /* The count of CCM_CCGR */ #define CCM_CCGR_COUNT (103U) /*! @name CCGR_SET - CCM Clock Gating Register */ /*! @{ */ #define CCM_CCGR_SET_SETTING0_MASK (0x3U) #define CCM_CCGR_SET_SETTING0_SHIFT (0U) /*! SETTING0 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_CCGR_SET_SETTING0(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING0_SHIFT)) & CCM_CCGR_SET_SETTING0_MASK) #define CCM_CCGR_SET_SETTING1_MASK (0x30U) #define CCM_CCGR_SET_SETTING1_SHIFT (4U) /*! SETTING1 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_CCGR_SET_SETTING1(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING1_SHIFT)) & CCM_CCGR_SET_SETTING1_MASK) #define CCM_CCGR_SET_SETTING2_MASK (0x300U) #define CCM_CCGR_SET_SETTING2_SHIFT (8U) /*! SETTING2 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_CCGR_SET_SETTING2(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING2_SHIFT)) & CCM_CCGR_SET_SETTING2_MASK) #define CCM_CCGR_SET_SETTING3_MASK (0x3000U) #define CCM_CCGR_SET_SETTING3_SHIFT (12U) /*! SETTING3 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_CCGR_SET_SETTING3(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING3_SHIFT)) & CCM_CCGR_SET_SETTING3_MASK) /*! @} */ /* The count of CCM_CCGR_SET */ #define CCM_CCGR_SET_COUNT (103U) /*! @name CCGR_CLR - CCM Clock Gating Register */ /*! @{ */ #define CCM_CCGR_CLR_SETTING0_MASK (0x3U) #define CCM_CCGR_CLR_SETTING0_SHIFT (0U) /*! SETTING0 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_CCGR_CLR_SETTING0(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING0_SHIFT)) & CCM_CCGR_CLR_SETTING0_MASK) #define CCM_CCGR_CLR_SETTING1_MASK (0x30U) #define CCM_CCGR_CLR_SETTING1_SHIFT (4U) /*! SETTING1 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_CCGR_CLR_SETTING1(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING1_SHIFT)) & CCM_CCGR_CLR_SETTING1_MASK) #define CCM_CCGR_CLR_SETTING2_MASK (0x300U) #define CCM_CCGR_CLR_SETTING2_SHIFT (8U) /*! SETTING2 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_CCGR_CLR_SETTING2(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING2_SHIFT)) & CCM_CCGR_CLR_SETTING2_MASK) #define CCM_CCGR_CLR_SETTING3_MASK (0x3000U) #define CCM_CCGR_CLR_SETTING3_SHIFT (12U) /*! SETTING3 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_CCGR_CLR_SETTING3(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING3_SHIFT)) & CCM_CCGR_CLR_SETTING3_MASK) /*! @} */ /* The count of CCM_CCGR_CLR */ #define CCM_CCGR_CLR_COUNT (103U) /*! @name CCGR_TOG - CCM Clock Gating Register */ /*! @{ */ #define CCM_CCGR_TOG_SETTING0_MASK (0x3U) #define CCM_CCGR_TOG_SETTING0_SHIFT (0U) /*! SETTING0 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_CCGR_TOG_SETTING0(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING0_SHIFT)) & CCM_CCGR_TOG_SETTING0_MASK) #define CCM_CCGR_TOG_SETTING1_MASK (0x30U) #define CCM_CCGR_TOG_SETTING1_SHIFT (4U) /*! SETTING1 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_CCGR_TOG_SETTING1(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING1_SHIFT)) & CCM_CCGR_TOG_SETTING1_MASK) #define CCM_CCGR_TOG_SETTING2_MASK (0x300U) #define CCM_CCGR_TOG_SETTING2_SHIFT (8U) /*! SETTING2 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_CCGR_TOG_SETTING2(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING2_SHIFT)) & CCM_CCGR_TOG_SETTING2_MASK) #define CCM_CCGR_TOG_SETTING3_MASK (0x3000U) #define CCM_CCGR_TOG_SETTING3_SHIFT (12U) /*! SETTING3 * 0b00..Domain clocks not needed * 0b01..Domain clocks needed when in RUN * 0b10..Domain clocks needed when in RUN and WAIT * 0b11..Domain clocks needed all the time */ #define CCM_CCGR_TOG_SETTING3(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING3_SHIFT)) & CCM_CCGR_TOG_SETTING3_MASK) /*! @} */ /* The count of CCM_CCGR_TOG */ #define CCM_CCGR_TOG_COUNT (103U) /*! @name TARGET_ROOT - Target Register */ /*! @{ */ #define CCM_TARGET_ROOT_POST_PODF_MASK (0x3FU) #define CCM_TARGET_ROOT_POST_PODF_SHIFT (0U) /*! POST_PODF * 0b000000..Divide by 1 * 0b000001..Divide by 2 * 0b000010..Divide by 3 * 0b000011..Divide by 4 * 0b000100..Divide by 5 * 0b000101..Divide by 6 * 0b111111..Divide by 64 */ #define CCM_TARGET_ROOT_POST_PODF(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_POST_PODF_MASK) #define CCM_TARGET_ROOT_PRE_PODF_MASK (0x70000U) #define CCM_TARGET_ROOT_PRE_PODF_SHIFT (16U) /*! PRE_PODF * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 3 * 0b011..Divide by 4 * 0b100..Divide by 5 * 0b101..Divide by 6 * 0b110..Divide by 7 * 0b111..Divide by 8 */ #define CCM_TARGET_ROOT_PRE_PODF(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_PRE_PODF_MASK) #define CCM_TARGET_ROOT_MUX_MASK (0x7000000U) #define CCM_TARGET_ROOT_MUX_SHIFT (24U) #define CCM_TARGET_ROOT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_MUX_SHIFT)) & CCM_TARGET_ROOT_MUX_MASK) #define CCM_TARGET_ROOT_ENABLE_MASK (0x10000000U) #define CCM_TARGET_ROOT_ENABLE_SHIFT (28U) /*! ENABLE * 0b0..clock root is OFF * 0b1..clock root is ON */ #define CCM_TARGET_ROOT_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_ENABLE_SHIFT)) & CCM_TARGET_ROOT_ENABLE_MASK) /*! @} */ /* The count of CCM_TARGET_ROOT */ #define CCM_TARGET_ROOT_COUNT (135U) /*! @name TARGET_ROOT_SET - Target Register */ /*! @{ */ #define CCM_TARGET_ROOT_SET_POST_PODF_MASK (0x3FU) #define CCM_TARGET_ROOT_SET_POST_PODF_SHIFT (0U) /*! POST_PODF * 0b000000..Divide by 1 * 0b000001..Divide by 2 * 0b000010..Divide by 3 * 0b000011..Divide by 4 * 0b000100..Divide by 5 * 0b000101..Divide by 6 * 0b111111..Divide by 64 */ #define CCM_TARGET_ROOT_SET_POST_PODF(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_POST_PODF_MASK) #define CCM_TARGET_ROOT_SET_PRE_PODF_MASK (0x70000U) #define CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT (16U) /*! PRE_PODF * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 3 * 0b011..Divide by 4 * 0b100..Divide by 5 * 0b101..Divide by 6 * 0b110..Divide by 7 * 0b111..Divide by 8 */ #define CCM_TARGET_ROOT_SET_PRE_PODF(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_PRE_PODF_MASK) #define CCM_TARGET_ROOT_SET_MUX_MASK (0x7000000U) #define CCM_TARGET_ROOT_SET_MUX_SHIFT (24U) #define CCM_TARGET_ROOT_SET_MUX(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_MUX_SHIFT)) & CCM_TARGET_ROOT_SET_MUX_MASK) #define CCM_TARGET_ROOT_SET_ENABLE_MASK (0x10000000U) #define CCM_TARGET_ROOT_SET_ENABLE_SHIFT (28U) /*! ENABLE * 0b0..clock root is OFF * 0b1..clock root is ON */ #define CCM_TARGET_ROOT_SET_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_ENABLE_SHIFT)) & CCM_TARGET_ROOT_SET_ENABLE_MASK) /*! @} */ /* The count of CCM_TARGET_ROOT_SET */ #define CCM_TARGET_ROOT_SET_COUNT (135U) /*! @name TARGET_ROOT_CLR - Target Register */ /*! @{ */ #define CCM_TARGET_ROOT_CLR_POST_PODF_MASK (0x3FU) #define CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT (0U) /*! POST_PODF * 0b000000..Divide by 1 * 0b000001..Divide by 2 * 0b000010..Divide by 3 * 0b000011..Divide by 4 * 0b000100..Divide by 5 * 0b000101..Divide by 6 * 0b111111..Divide by 64 */ #define CCM_TARGET_ROOT_CLR_POST_PODF(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_POST_PODF_MASK) #define CCM_TARGET_ROOT_CLR_PRE_PODF_MASK (0x70000U) #define CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT (16U) /*! PRE_PODF * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 3 * 0b011..Divide by 4 * 0b100..Divide by 5 * 0b101..Divide by 6 * 0b110..Divide by 7 * 0b111..Divide by 8 */ #define CCM_TARGET_ROOT_CLR_PRE_PODF(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_PRE_PODF_MASK) #define CCM_TARGET_ROOT_CLR_MUX_MASK (0x7000000U) #define CCM_TARGET_ROOT_CLR_MUX_SHIFT (24U) #define CCM_TARGET_ROOT_CLR_MUX(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_MUX_SHIFT)) & CCM_TARGET_ROOT_CLR_MUX_MASK) #define CCM_TARGET_ROOT_CLR_ENABLE_MASK (0x10000000U) #define CCM_TARGET_ROOT_CLR_ENABLE_SHIFT (28U) /*! ENABLE * 0b0..clock root is OFF * 0b1..clock root is ON */ #define CCM_TARGET_ROOT_CLR_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_ENABLE_SHIFT)) & CCM_TARGET_ROOT_CLR_ENABLE_MASK) /*! @} */ /* The count of CCM_TARGET_ROOT_CLR */ #define CCM_TARGET_ROOT_CLR_COUNT (135U) /*! @name TARGET_ROOT_TOG - Target Register */ /*! @{ */ #define CCM_TARGET_ROOT_TOG_POST_PODF_MASK (0x3FU) #define CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT (0U) /*! POST_PODF * 0b000000..Divide by 1 * 0b000001..Divide by 2 * 0b000010..Divide by 3 * 0b000011..Divide by 4 * 0b000100..Divide by 5 * 0b000101..Divide by 6 * 0b111111..Divide by 64 */ #define CCM_TARGET_ROOT_TOG_POST_PODF(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_POST_PODF_MASK) #define CCM_TARGET_ROOT_TOG_PRE_PODF_MASK (0x70000U) #define CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT (16U) /*! PRE_PODF * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 3 * 0b011..Divide by 4 * 0b100..Divide by 5 * 0b101..Divide by 6 * 0b110..Divide by 7 * 0b111..Divide by 8 */ #define CCM_TARGET_ROOT_TOG_PRE_PODF(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_PRE_PODF_MASK) #define CCM_TARGET_ROOT_TOG_MUX_MASK (0x7000000U) #define CCM_TARGET_ROOT_TOG_MUX_SHIFT (24U) #define CCM_TARGET_ROOT_TOG_MUX(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_MUX_SHIFT)) & CCM_TARGET_ROOT_TOG_MUX_MASK) #define CCM_TARGET_ROOT_TOG_ENABLE_MASK (0x10000000U) #define CCM_TARGET_ROOT_TOG_ENABLE_SHIFT (28U) /*! ENABLE * 0b0..clock root is OFF * 0b1..clock root is ON */ #define CCM_TARGET_ROOT_TOG_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_ENABLE_SHIFT)) & CCM_TARGET_ROOT_TOG_ENABLE_MASK) /*! @} */ /* The count of CCM_TARGET_ROOT_TOG */ #define CCM_TARGET_ROOT_TOG_COUNT (135U) /*! @name MISC - Miscellaneous Register */ /*! @{ */ #define CCM_MISC_AUTHEN_FAIL_MASK (0x1U) #define CCM_MISC_AUTHEN_FAIL_SHIFT (0U) #define CCM_MISC_AUTHEN_FAIL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_MISC_AUTHEN_FAIL_SHIFT)) & CCM_MISC_AUTHEN_FAIL_MASK) #define CCM_MISC_TIMEOUT_MASK (0x10U) #define CCM_MISC_TIMEOUT_SHIFT (4U) #define CCM_MISC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_TIMEOUT_SHIFT)) & CCM_MISC_TIMEOUT_MASK) #define CCM_MISC_VIOLATE_MASK (0x100U) #define CCM_MISC_VIOLATE_SHIFT (8U) #define CCM_MISC_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_VIOLATE_SHIFT)) & CCM_MISC_VIOLATE_MASK) /*! @} */ /* The count of CCM_MISC */ #define CCM_MISC_COUNT (135U) /*! @name MISC_ROOT_SET - Miscellaneous Register */ /*! @{ */ #define CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK (0x1U) #define CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT (0U) #define CCM_MISC_ROOT_SET_AUTHEN_FAIL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK) #define CCM_MISC_ROOT_SET_TIMEOUT_MASK (0x10U) #define CCM_MISC_ROOT_SET_TIMEOUT_SHIFT (4U) #define CCM_MISC_ROOT_SET_TIMEOUT(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_SET_TIMEOUT_MASK) #define CCM_MISC_ROOT_SET_VIOLATE_MASK (0x100U) #define CCM_MISC_ROOT_SET_VIOLATE_SHIFT (8U) #define CCM_MISC_ROOT_SET_VIOLATE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_VIOLATE_SHIFT)) & CCM_MISC_ROOT_SET_VIOLATE_MASK) /*! @} */ /* The count of CCM_MISC_ROOT_SET */ #define CCM_MISC_ROOT_SET_COUNT (135U) /*! @name MISC_ROOT_CLR - Miscellaneous Register */ /*! @{ */ #define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK (0x1U) #define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT (0U) #define CCM_MISC_ROOT_CLR_AUTHEN_FAIL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK) #define CCM_MISC_ROOT_CLR_TIMEOUT_MASK (0x10U) #define CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT (4U) #define CCM_MISC_ROOT_CLR_TIMEOUT(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_CLR_TIMEOUT_MASK) #define CCM_MISC_ROOT_CLR_VIOLATE_MASK (0x100U) #define CCM_MISC_ROOT_CLR_VIOLATE_SHIFT (8U) #define CCM_MISC_ROOT_CLR_VIOLATE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_VIOLATE_SHIFT)) & CCM_MISC_ROOT_CLR_VIOLATE_MASK) /*! @} */ /* The count of CCM_MISC_ROOT_CLR */ #define CCM_MISC_ROOT_CLR_COUNT (135U) /*! @name MISC_ROOT_TOG - Miscellaneous Register */ /*! @{ */ #define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK (0x1U) #define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT (0U) #define CCM_MISC_ROOT_TOG_AUTHEN_FAIL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK) #define CCM_MISC_ROOT_TOG_TIMEOUT_MASK (0x10U) #define CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT (4U) #define CCM_MISC_ROOT_TOG_TIMEOUT(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_TOG_TIMEOUT_MASK) #define CCM_MISC_ROOT_TOG_VIOLATE_MASK (0x100U) #define CCM_MISC_ROOT_TOG_VIOLATE_SHIFT (8U) #define CCM_MISC_ROOT_TOG_VIOLATE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_VIOLATE_SHIFT)) & CCM_MISC_ROOT_TOG_VIOLATE_MASK) /*! @} */ /* The count of CCM_MISC_ROOT_TOG */ #define CCM_MISC_ROOT_TOG_COUNT (135U) /*! @name POST - Post Divider Register */ /*! @{ */ #define CCM_POST_POST_PODF_MASK (0x3FU) #define CCM_POST_POST_PODF_SHIFT (0U) /*! POST_PODF * 0b000000..Divide by 1 * 0b000001..Divide by 2 * 0b000010..Divide by 3 * 0b000011..Divide by 4 * 0b000100..Divide by 5 * 0b000101..Divide by 6 * 0b111111..Divide by 64 */ #define CCM_POST_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_POST_PODF_SHIFT)) & CCM_POST_POST_PODF_MASK) #define CCM_POST_BUSY1_MASK (0x80U) #define CCM_POST_BUSY1_SHIFT (7U) #define CCM_POST_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY1_SHIFT)) & CCM_POST_BUSY1_MASK) #define CCM_POST_SELECT_MASK (0x10000000U) #define CCM_POST_SELECT_SHIFT (28U) /*! SELECT * 0b0..select branch A * 0b1..select branch B */ #define CCM_POST_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_SELECT_SHIFT)) & CCM_POST_SELECT_MASK) #define CCM_POST_BUSY2_MASK (0x80000000U) #define CCM_POST_BUSY2_SHIFT (31U) #define CCM_POST_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY2_SHIFT)) & CCM_POST_BUSY2_MASK) /*! @} */ /* The count of CCM_POST */ #define CCM_POST_COUNT (135U) /*! @name POST_ROOT_SET - Post Divider Register */ /*! @{ */ #define CCM_POST_ROOT_SET_POST_PODF_MASK (0x3FU) #define CCM_POST_ROOT_SET_POST_PODF_SHIFT (0U) /*! POST_PODF * 0b000000..Divide by 1 * 0b000001..Divide by 2 * 0b000010..Divide by 3 * 0b000011..Divide by 4 * 0b000100..Divide by 5 * 0b000101..Divide by 6 * 0b111111..Divide by 64 */ #define CCM_POST_ROOT_SET_POST_PODF(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_POST_PODF_SHIFT)) & CCM_POST_ROOT_SET_POST_PODF_MASK) #define CCM_POST_ROOT_SET_BUSY1_MASK (0x80U) #define CCM_POST_ROOT_SET_BUSY1_SHIFT (7U) #define CCM_POST_ROOT_SET_BUSY1(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY1_SHIFT)) & CCM_POST_ROOT_SET_BUSY1_MASK) #define CCM_POST_ROOT_SET_SELECT_MASK (0x10000000U) #define CCM_POST_ROOT_SET_SELECT_SHIFT (28U) /*! SELECT * 0b0..select branch A * 0b1..select branch B */ #define CCM_POST_ROOT_SET_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_SELECT_SHIFT)) & CCM_POST_ROOT_SET_SELECT_MASK) #define CCM_POST_ROOT_SET_BUSY2_MASK (0x80000000U) #define CCM_POST_ROOT_SET_BUSY2_SHIFT (31U) #define CCM_POST_ROOT_SET_BUSY2(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY2_SHIFT)) & CCM_POST_ROOT_SET_BUSY2_MASK) /*! @} */ /* The count of CCM_POST_ROOT_SET */ #define CCM_POST_ROOT_SET_COUNT (135U) /*! @name POST_ROOT_CLR - Post Divider Register */ /*! @{ */ #define CCM_POST_ROOT_CLR_POST_PODF_MASK (0x3FU) #define CCM_POST_ROOT_CLR_POST_PODF_SHIFT (0U) /*! POST_PODF * 0b000000..Divide by 1 * 0b000001..Divide by 2 * 0b000010..Divide by 3 * 0b000011..Divide by 4 * 0b000100..Divide by 5 * 0b000101..Divide by 6 * 0b111111..Divide by 64 */ #define CCM_POST_ROOT_CLR_POST_PODF(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_POST_PODF_SHIFT)) & CCM_POST_ROOT_CLR_POST_PODF_MASK) #define CCM_POST_ROOT_CLR_BUSY1_MASK (0x80U) #define CCM_POST_ROOT_CLR_BUSY1_SHIFT (7U) #define CCM_POST_ROOT_CLR_BUSY1(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY1_SHIFT)) & CCM_POST_ROOT_CLR_BUSY1_MASK) #define CCM_POST_ROOT_CLR_SELECT_MASK (0x10000000U) #define CCM_POST_ROOT_CLR_SELECT_SHIFT (28U) /*! SELECT * 0b0..select branch A * 0b1..select branch B */ #define CCM_POST_ROOT_CLR_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_SELECT_SHIFT)) & CCM_POST_ROOT_CLR_SELECT_MASK) #define CCM_POST_ROOT_CLR_BUSY2_MASK (0x80000000U) #define CCM_POST_ROOT_CLR_BUSY2_SHIFT (31U) #define CCM_POST_ROOT_CLR_BUSY2(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY2_SHIFT)) & CCM_POST_ROOT_CLR_BUSY2_MASK) /*! @} */ /* The count of CCM_POST_ROOT_CLR */ #define CCM_POST_ROOT_CLR_COUNT (135U) /*! @name POST_ROOT_TOG - Post Divider Register */ /*! @{ */ #define CCM_POST_ROOT_TOG_POST_PODF_MASK (0x3FU) #define CCM_POST_ROOT_TOG_POST_PODF_SHIFT (0U) /*! POST_PODF * 0b000000..Divide by 1 * 0b000001..Divide by 2 * 0b000010..Divide by 3 * 0b000011..Divide by 4 * 0b000100..Divide by 5 * 0b000101..Divide by 6 * 0b111111..Divide by 64 */ #define CCM_POST_ROOT_TOG_POST_PODF(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_POST_PODF_SHIFT)) & CCM_POST_ROOT_TOG_POST_PODF_MASK) #define CCM_POST_ROOT_TOG_BUSY1_MASK (0x80U) #define CCM_POST_ROOT_TOG_BUSY1_SHIFT (7U) #define CCM_POST_ROOT_TOG_BUSY1(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY1_SHIFT)) & CCM_POST_ROOT_TOG_BUSY1_MASK) #define CCM_POST_ROOT_TOG_SELECT_MASK (0x10000000U) #define CCM_POST_ROOT_TOG_SELECT_SHIFT (28U) /*! SELECT * 0b0..select branch A * 0b1..select branch B */ #define CCM_POST_ROOT_TOG_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_SELECT_SHIFT)) & CCM_POST_ROOT_TOG_SELECT_MASK) #define CCM_POST_ROOT_TOG_BUSY2_MASK (0x80000000U) #define CCM_POST_ROOT_TOG_BUSY2_SHIFT (31U) #define CCM_POST_ROOT_TOG_BUSY2(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY2_SHIFT)) & CCM_POST_ROOT_TOG_BUSY2_MASK) /*! @} */ /* The count of CCM_POST_ROOT_TOG */ #define CCM_POST_ROOT_TOG_COUNT (135U) /*! @name PRE - Pre Divider Register */ /*! @{ */ #define CCM_PRE_PRE_PODF_B_MASK (0x7U) #define CCM_PRE_PRE_PODF_B_SHIFT (0U) /*! PRE_PODF_B * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 3 * 0b011..Divide by 4 * 0b100..Divide by 5 * 0b101..Divide by 6 * 0b110..Divide by 7 * 0b111..Divide by 8 */ #define CCM_PRE_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_B_SHIFT)) & CCM_PRE_PRE_PODF_B_MASK) #define CCM_PRE_BUSY0_MASK (0x8U) #define CCM_PRE_BUSY0_SHIFT (3U) #define CCM_PRE_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY0_SHIFT)) & CCM_PRE_BUSY0_MASK) #define CCM_PRE_MUX_B_MASK (0x700U) #define CCM_PRE_MUX_B_SHIFT (8U) #define CCM_PRE_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_B_SHIFT)) & CCM_PRE_MUX_B_MASK) #define CCM_PRE_EN_B_MASK (0x1000U) #define CCM_PRE_EN_B_SHIFT (12U) /*! EN_B * 0b0..Clock shutdown * 0b1..Clock ON */ #define CCM_PRE_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_B_SHIFT)) & CCM_PRE_EN_B_MASK) #define CCM_PRE_BUSY1_MASK (0x8000U) #define CCM_PRE_BUSY1_SHIFT (15U) #define CCM_PRE_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY1_SHIFT)) & CCM_PRE_BUSY1_MASK) #define CCM_PRE_PRE_PODF_A_MASK (0x70000U) #define CCM_PRE_PRE_PODF_A_SHIFT (16U) /*! PRE_PODF_A * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 3 * 0b011..Divide by 4 * 0b100..Divide by 5 * 0b101..Divide by 6 * 0b110..Divide by 7 * 0b111..Divide by 8 */ #define CCM_PRE_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_A_SHIFT)) & CCM_PRE_PRE_PODF_A_MASK) #define CCM_PRE_BUSY3_MASK (0x80000U) #define CCM_PRE_BUSY3_SHIFT (19U) #define CCM_PRE_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY3_SHIFT)) & CCM_PRE_BUSY3_MASK) #define CCM_PRE_MUX_A_MASK (0x7000000U) #define CCM_PRE_MUX_A_SHIFT (24U) #define CCM_PRE_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_A_SHIFT)) & CCM_PRE_MUX_A_MASK) #define CCM_PRE_EN_A_MASK (0x10000000U) #define CCM_PRE_EN_A_SHIFT (28U) /*! EN_A * 0b0..Clock shutdown * 0b1..clock ON */ #define CCM_PRE_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_A_SHIFT)) & CCM_PRE_EN_A_MASK) #define CCM_PRE_BUSY4_MASK (0x80000000U) #define CCM_PRE_BUSY4_SHIFT (31U) #define CCM_PRE_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY4_SHIFT)) & CCM_PRE_BUSY4_MASK) /*! @} */ /* The count of CCM_PRE */ #define CCM_PRE_COUNT (135U) /*! @name PRE_ROOT_SET - Pre Divider Register */ /*! @{ */ #define CCM_PRE_ROOT_SET_PRE_PODF_B_MASK (0x7U) #define CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT (0U) /*! PRE_PODF_B * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 3 * 0b011..Divide by 4 * 0b100..Divide by 5 * 0b101..Divide by 6 * 0b110..Divide by 7 * 0b111..Divide by 8 */ #define CCM_PRE_ROOT_SET_PRE_PODF_B(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_B_MASK) #define CCM_PRE_ROOT_SET_BUSY0_MASK (0x8U) #define CCM_PRE_ROOT_SET_BUSY0_SHIFT (3U) #define CCM_PRE_ROOT_SET_BUSY0(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY0_SHIFT)) & CCM_PRE_ROOT_SET_BUSY0_MASK) #define CCM_PRE_ROOT_SET_MUX_B_MASK (0x700U) #define CCM_PRE_ROOT_SET_MUX_B_SHIFT (8U) #define CCM_PRE_ROOT_SET_MUX_B(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_B_SHIFT)) & CCM_PRE_ROOT_SET_MUX_B_MASK) #define CCM_PRE_ROOT_SET_EN_B_MASK (0x1000U) #define CCM_PRE_ROOT_SET_EN_B_SHIFT (12U) /*! EN_B * 0b0..Clock shutdown * 0b1..Clock ON */ #define CCM_PRE_ROOT_SET_EN_B(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_B_SHIFT)) & CCM_PRE_ROOT_SET_EN_B_MASK) #define CCM_PRE_ROOT_SET_BUSY1_MASK (0x8000U) #define CCM_PRE_ROOT_SET_BUSY1_SHIFT (15U) #define CCM_PRE_ROOT_SET_BUSY1(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY1_SHIFT)) & CCM_PRE_ROOT_SET_BUSY1_MASK) #define CCM_PRE_ROOT_SET_PRE_PODF_A_MASK (0x70000U) #define CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT (16U) /*! PRE_PODF_A * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 3 * 0b011..Divide by 4 * 0b100..Divide by 5 * 0b101..Divide by 6 * 0b110..Divide by 7 * 0b111..Divide by 8 */ #define CCM_PRE_ROOT_SET_PRE_PODF_A(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_A_MASK) #define CCM_PRE_ROOT_SET_BUSY3_MASK (0x80000U) #define CCM_PRE_ROOT_SET_BUSY3_SHIFT (19U) #define CCM_PRE_ROOT_SET_BUSY3(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY3_SHIFT)) & CCM_PRE_ROOT_SET_BUSY3_MASK) #define CCM_PRE_ROOT_SET_MUX_A_MASK (0x7000000U) #define CCM_PRE_ROOT_SET_MUX_A_SHIFT (24U) #define CCM_PRE_ROOT_SET_MUX_A(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_A_SHIFT)) & CCM_PRE_ROOT_SET_MUX_A_MASK) #define CCM_PRE_ROOT_SET_EN_A_MASK (0x10000000U) #define CCM_PRE_ROOT_SET_EN_A_SHIFT (28U) /*! EN_A * 0b0..Clock shutdown * 0b1..clock ON */ #define CCM_PRE_ROOT_SET_EN_A(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_A_SHIFT)) & CCM_PRE_ROOT_SET_EN_A_MASK) #define CCM_PRE_ROOT_SET_BUSY4_MASK (0x80000000U) #define CCM_PRE_ROOT_SET_BUSY4_SHIFT (31U) #define CCM_PRE_ROOT_SET_BUSY4(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY4_SHIFT)) & CCM_PRE_ROOT_SET_BUSY4_MASK) /*! @} */ /* The count of CCM_PRE_ROOT_SET */ #define CCM_PRE_ROOT_SET_COUNT (135U) /*! @name PRE_ROOT_CLR - Pre Divider Register */ /*! @{ */ #define CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK (0x7U) #define CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT (0U) /*! PRE_PODF_B * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 3 * 0b011..Divide by 4 * 0b100..Divide by 5 * 0b101..Divide by 6 * 0b110..Divide by 7 * 0b111..Divide by 8 */ #define CCM_PRE_ROOT_CLR_PRE_PODF_B(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK) #define CCM_PRE_ROOT_CLR_BUSY0_MASK (0x8U) #define CCM_PRE_ROOT_CLR_BUSY0_SHIFT (3U) #define CCM_PRE_ROOT_CLR_BUSY0(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY0_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY0_MASK) #define CCM_PRE_ROOT_CLR_MUX_B_MASK (0x700U) #define CCM_PRE_ROOT_CLR_MUX_B_SHIFT (8U) #define CCM_PRE_ROOT_CLR_MUX_B(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_B_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_B_MASK) #define CCM_PRE_ROOT_CLR_EN_B_MASK (0x1000U) #define CCM_PRE_ROOT_CLR_EN_B_SHIFT (12U) /*! EN_B * 0b0..Clock shutdown * 0b1..Clock ON */ #define CCM_PRE_ROOT_CLR_EN_B(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_B_SHIFT)) & CCM_PRE_ROOT_CLR_EN_B_MASK) #define CCM_PRE_ROOT_CLR_BUSY1_MASK (0x8000U) #define CCM_PRE_ROOT_CLR_BUSY1_SHIFT (15U) #define CCM_PRE_ROOT_CLR_BUSY1(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY1_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY1_MASK) #define CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK (0x70000U) #define CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT (16U) /*! PRE_PODF_A * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 3 * 0b011..Divide by 4 * 0b100..Divide by 5 * 0b101..Divide by 6 * 0b110..Divide by 7 * 0b111..Divide by 8 */ #define CCM_PRE_ROOT_CLR_PRE_PODF_A(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK) #define CCM_PRE_ROOT_CLR_BUSY3_MASK (0x80000U) #define CCM_PRE_ROOT_CLR_BUSY3_SHIFT (19U) #define CCM_PRE_ROOT_CLR_BUSY3(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY3_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY3_MASK) #define CCM_PRE_ROOT_CLR_MUX_A_MASK (0x7000000U) #define CCM_PRE_ROOT_CLR_MUX_A_SHIFT (24U) #define CCM_PRE_ROOT_CLR_MUX_A(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_A_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_A_MASK) #define CCM_PRE_ROOT_CLR_EN_A_MASK (0x10000000U) #define CCM_PRE_ROOT_CLR_EN_A_SHIFT (28U) /*! EN_A * 0b0..Clock shutdown * 0b1..clock ON */ #define CCM_PRE_ROOT_CLR_EN_A(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_A_SHIFT)) & CCM_PRE_ROOT_CLR_EN_A_MASK) #define CCM_PRE_ROOT_CLR_BUSY4_MASK (0x80000000U) #define CCM_PRE_ROOT_CLR_BUSY4_SHIFT (31U) #define CCM_PRE_ROOT_CLR_BUSY4(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY4_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY4_MASK) /*! @} */ /* The count of CCM_PRE_ROOT_CLR */ #define CCM_PRE_ROOT_CLR_COUNT (135U) /*! @name PRE_ROOT_TOG - Pre Divider Register */ /*! @{ */ #define CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK (0x7U) #define CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT (0U) /*! PRE_PODF_B * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 3 * 0b011..Divide by 4 * 0b100..Divide by 5 * 0b101..Divide by 6 * 0b110..Divide by 7 * 0b111..Divide by 8 */ #define CCM_PRE_ROOT_TOG_PRE_PODF_B(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK) #define CCM_PRE_ROOT_TOG_BUSY0_MASK (0x8U) #define CCM_PRE_ROOT_TOG_BUSY0_SHIFT (3U) #define CCM_PRE_ROOT_TOG_BUSY0(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY0_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY0_MASK) #define CCM_PRE_ROOT_TOG_MUX_B_MASK (0x700U) #define CCM_PRE_ROOT_TOG_MUX_B_SHIFT (8U) #define CCM_PRE_ROOT_TOG_MUX_B(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_B_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_B_MASK) #define CCM_PRE_ROOT_TOG_EN_B_MASK (0x1000U) #define CCM_PRE_ROOT_TOG_EN_B_SHIFT (12U) /*! EN_B * 0b0..Clock shutdown * 0b1..Clock ON */ #define CCM_PRE_ROOT_TOG_EN_B(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_B_SHIFT)) & CCM_PRE_ROOT_TOG_EN_B_MASK) #define CCM_PRE_ROOT_TOG_BUSY1_MASK (0x8000U) #define CCM_PRE_ROOT_TOG_BUSY1_SHIFT (15U) #define CCM_PRE_ROOT_TOG_BUSY1(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY1_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY1_MASK) #define CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK (0x70000U) #define CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT (16U) /*! PRE_PODF_A * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 3 * 0b011..Divide by 4 * 0b100..Divide by 5 * 0b101..Divide by 6 * 0b110..Divide by 7 * 0b111..Divide by 8 */ #define CCM_PRE_ROOT_TOG_PRE_PODF_A(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK) #define CCM_PRE_ROOT_TOG_BUSY3_MASK (0x80000U) #define CCM_PRE_ROOT_TOG_BUSY3_SHIFT (19U) #define CCM_PRE_ROOT_TOG_BUSY3(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY3_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY3_MASK) #define CCM_PRE_ROOT_TOG_MUX_A_MASK (0x7000000U) #define CCM_PRE_ROOT_TOG_MUX_A_SHIFT (24U) #define CCM_PRE_ROOT_TOG_MUX_A(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_A_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_A_MASK) #define CCM_PRE_ROOT_TOG_EN_A_MASK (0x10000000U) #define CCM_PRE_ROOT_TOG_EN_A_SHIFT (28U) /*! EN_A * 0b0..Clock shutdown * 0b1..clock ON */ #define CCM_PRE_ROOT_TOG_EN_A(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_A_SHIFT)) & CCM_PRE_ROOT_TOG_EN_A_MASK) #define CCM_PRE_ROOT_TOG_BUSY4_MASK (0x80000000U) #define CCM_PRE_ROOT_TOG_BUSY4_SHIFT (31U) #define CCM_PRE_ROOT_TOG_BUSY4(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY4_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY4_MASK) /*! @} */ /* The count of CCM_PRE_ROOT_TOG */ #define CCM_PRE_ROOT_TOG_COUNT (135U) /*! @name ACCESS_CTRL - Access Control Register */ /*! @{ */ #define CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK (0xFU) #define CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT (0U) #define CCM_ACCESS_CTRL_DOMAIN0_INFO(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK) #define CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK (0xF0U) #define CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT (4U) #define CCM_ACCESS_CTRL_DOMAIN1_INFO(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK) #define CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK (0xF00U) #define CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT (8U) #define CCM_ACCESS_CTRL_DOMAIN2_INFO(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK) #define CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK (0xF000U) #define CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT (12U) #define CCM_ACCESS_CTRL_DOMAIN3_INFO(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK) #define CCM_ACCESS_CTRL_OWNER_ID_MASK (0x30000U) #define CCM_ACCESS_CTRL_OWNER_ID_SHIFT (16U) /*! OWNER_ID * 0b00..domaino * 0b01..domain1 * 0b10..domain2 * 0b11..domain3 */ #define CCM_ACCESS_CTRL_OWNER_ID(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_OWNER_ID_MASK) #define CCM_ACCESS_CTRL_MUTEX_MASK (0x100000U) #define CCM_ACCESS_CTRL_MUTEX_SHIFT (20U) /*! MUTEX * 0b0..Semaphore is free to take * 0b1..Semaphore is taken */ #define CCM_ACCESS_CTRL_MUTEX(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_MUTEX_MASK) #define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK (0x1000000U) #define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT (24U) /*! DOMAIN0_WHITELIST * 0b0..Domain cannot change the setting * 0b1..Domain can change the setting */ #define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK) #define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK (0x2000000U) #define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT (25U) /*! DOMAIN1_WHITELIST * 0b0..Domain cannot change the setting * 0b1..Domain can change the setting */ #define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK) #define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK (0x4000000U) #define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT (26U) /*! DOMAIN2_WHITELIST * 0b0..Domain cannot change the setting * 0b1..Domain can change the setting */ #define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK) #define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK (0x8000000U) #define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT (27U) /*! DOMAIN3_WHITELIST * 0b0..Domain cannot change the setting * 0b1..Domain can change the setting */ #define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK) #define CCM_ACCESS_CTRL_SEMA_EN_MASK (0x10000000U) #define CCM_ACCESS_CTRL_SEMA_EN_SHIFT (28U) /*! SEMA_EN * 0b0..Disable * 0b1..Enable */ #define CCM_ACCESS_CTRL_SEMA_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_SEMA_EN_MASK) #define CCM_ACCESS_CTRL_LOCK_MASK (0x80000000U) #define CCM_ACCESS_CTRL_LOCK_SHIFT (31U) /*! LOCK * 0b0..Access control inactive * 0b1..Access control active */ #define CCM_ACCESS_CTRL_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_LOCK_SHIFT)) & CCM_ACCESS_CTRL_LOCK_MASK) /*! @} */ /* The count of CCM_ACCESS_CTRL */ #define CCM_ACCESS_CTRL_COUNT (135U) /*! @name ACCESS_CTRL_ROOT_SET - Access Control Register */ /*! @{ */ #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK (0xFU) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT (0U) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK (0xF0U) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT (4U) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK (0xF00U) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT (8U) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK (0xF000U) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT (12U) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK) #define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK (0x30000U) #define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT (16U) /*! OWNER_ID * 0b00..domaino * 0b01..domain1 * 0b10..domain2 * 0b11..domain3 */ #define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK) #define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK (0x100000U) #define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT (20U) /*! MUTEX * 0b0..Semaphore is free to take * 0b1..Semaphore is taken */ #define CCM_ACCESS_CTRL_ROOT_SET_MUTEX(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK (0x1000000U) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT (24U) /*! DOMAIN0_WHITELIST * 0b0..Domain cannot change the setting * 0b1..Domain can change the setting */ #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK (0x2000000U) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT (25U) /*! DOMAIN1_WHITELIST * 0b0..Domain cannot change the setting * 0b1..Domain can change the setting */ #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK (0x4000000U) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT (26U) /*! DOMAIN2_WHITELIST * 0b0..Domain cannot change the setting * 0b1..Domain can change the setting */ #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK (0x8000000U) #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT (27U) /*! DOMAIN3_WHITELIST * 0b0..Domain cannot change the setting * 0b1..Domain can change the setting */ #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK) #define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK (0x10000000U) #define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT (28U) /*! SEMA_EN * 0b0..Disable * 0b1..Enable */ #define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK) #define CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK (0x80000000U) #define CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT (31U) /*! LOCK * 0b0..Access control inactive * 0b1..Access control active */ #define CCM_ACCESS_CTRL_ROOT_SET_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK) /*! @} */ /* The count of CCM_ACCESS_CTRL_ROOT_SET */ #define CCM_ACCESS_CTRL_ROOT_SET_COUNT (135U) /*! @name ACCESS_CTRL_ROOT_CLR - Access Control Register */ /*! @{ */ #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK (0xFU) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT (0U) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK (0xF0U) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT (4U) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK (0xF00U) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT (8U) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK (0xF000U) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT (12U) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK) #define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK (0x30000U) #define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT (16U) /*! OWNER_ID * 0b00..domaino * 0b01..domain1 * 0b10..domain2 * 0b11..domain3 */ #define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK) #define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK (0x100000U) #define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT (20U) /*! MUTEX * 0b0..Semaphore is free to take * 0b1..Semaphore is taken */ #define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK (0x1000000U) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT (24U) /*! DOMAIN0_WHITELIST * 0b0..Domain cannot change the setting * 0b1..Domain can change the setting */ #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK (0x2000000U) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT (25U) /*! DOMAIN1_WHITELIST * 0b0..Domain cannot change the setting * 0b1..Domain can change the setting */ #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK (0x4000000U) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT (26U) /*! DOMAIN2_WHITELIST * 0b0..Domain cannot change the setting * 0b1..Domain can change the setting */ #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK (0x8000000U) #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT (27U) /*! DOMAIN3_WHITELIST * 0b0..Domain cannot change the setting * 0b1..Domain can change the setting */ #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK) #define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK (0x10000000U) #define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT (28U) /*! SEMA_EN * 0b0..Disable * 0b1..Enable */ #define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK) #define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK (0x80000000U) #define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT (31U) /*! LOCK * 0b0..Access control inactive * 0b1..Access control active */ #define CCM_ACCESS_CTRL_ROOT_CLR_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK) /*! @} */ /* The count of CCM_ACCESS_CTRL_ROOT_CLR */ #define CCM_ACCESS_CTRL_ROOT_CLR_COUNT (135U) /*! @name ACCESS_CTRL_ROOT_TOG - Access Control Register */ /*! @{ */ #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK (0xFU) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT (0U) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK (0xF0U) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT (4U) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK (0xF00U) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT (8U) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK (0xF000U) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT (12U) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK) #define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK (0x30000U) #define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT (16U) /*! OWNER_ID * 0b00..domaino * 0b01..domain1 * 0b10..domain2 * 0b11..domain3 */ #define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK) #define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK (0x100000U) #define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT (20U) /*! MUTEX * 0b0..Semaphore is free to take * 0b1..Semaphore is taken */ #define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK (0x1000000U) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT (24U) /*! DOMAIN0_WHITELIST * 0b0..Domain cannot change the setting * 0b1..Domain can change the setting */ #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK (0x2000000U) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT (25U) /*! DOMAIN1_WHITELIST * 0b0..Domain cannot change the setting * 0b1..Domain can change the setting */ #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK (0x4000000U) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT (26U) /*! DOMAIN2_WHITELIST * 0b0..Domain cannot change the setting * 0b1..Domain can change the setting */ #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK (0x8000000U) #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT (27U) /*! DOMAIN3_WHITELIST * 0b0..Domain cannot change the setting * 0b1..Domain can change the setting */ #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT)) & \ CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK) #define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK (0x10000000U) #define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT (28U) /*! SEMA_EN * 0b0..Disable * 0b1..Enable */ #define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK) #define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK (0x80000000U) #define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT (31U) /*! LOCK * 0b0..Access control inactive * 0b1..Access control active */ #define CCM_ACCESS_CTRL_ROOT_TOG_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK) /*! @} */ /* The count of CCM_ACCESS_CTRL_ROOT_TOG */ #define CCM_ACCESS_CTRL_ROOT_TOG_COUNT (135U) /*! * @} */ /* end of group CCM_Register_Masks */ /* CCM - Peripheral instance base addresses */ /** Peripheral CCM base address */ #define CCM_BASE (0x30380000u) /** Peripheral CCM base pointer */ #define CCM ((CCM_Type *)CCM_BASE) /** Array initializer of CCM peripheral base addresses */ #define CCM_BASE_ADDRS \ { \ CCM_BASE \ } /** Array initializer of CCM peripheral base pointers */ #define CCM_BASE_PTRS \ { \ CCM \ } /** Interrupt vectors for the CCM peripheral type */ #define CCM_IRQS \ { \ CCM_IRQ1_IRQn, CCM_IRQ2_IRQn \ } /*! * @} */ /* end of group CCM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CCM_ANALOG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer * @{ */ /** CCM_ANALOG - Register Layout Typedef */ typedef struct { __IO uint32_t AUDIO_PLL1_GEN_CTRL; /**< AUDIO PLL1 General Function Control Register, offset: 0x0 */ __IO uint32_t AUDIO_PLL1_FDIV_CTL0; /**< AUDIO PLL1 Divide and Fraction Data Control 0 Register, offset: 0x4 */ __IO uint32_t AUDIO_PLL1_FDIV_CTL1; /**< AUDIO PLL1 Divide and Fraction Data Control 1 Register, offset: 0x8 */ __IO uint32_t AUDIO_PLL1_SSCG_CTRL; /**< AUDIO PLL1 PLL SSCG Control Register, offset: 0xC */ __IO uint32_t AUDIO_PLL1_MNIT_CTRL; /**< AUDIO PLL1 PLL Monitoring Control Register, offset: 0x10 */ __IO uint32_t AUDIO_PLL2_GEN_CTRL; /**< AUDIO PLL2 General Function Control Register, offset: 0x14 */ __IO uint32_t AUDIO_PLL2_FDIV_CTL0; /**< AUDIO PLL2 Divide and Fraction Data Control 0 Register, offset: 0x18 */ __IO uint32_t AUDIO_PLL2_FDIV_CTL1; /**< AUDIO PLL2 Divide and Fraction Data Control 1 Register, offset: 0x1C */ __IO uint32_t AUDIO_PLL2_SSCG_CTRL; /**< AUDIO PLL2 PLL SSCG Control Register, offset: 0x20 */ __IO uint32_t AUDIO_PLL2_MNIT_CTRL; /**< AUDIO PLL2 PLL Monitoring Control Register, offset: 0x24 */ __IO uint32_t VIDEO_PLL1_GEN_CTRL; /**< VIDEO PLL1 General Function Control Register, offset: 0x28 */ __IO uint32_t VIDEO_PLL1_FDIV_CTL0; /**< VIDEO PLL1 Divide and Fraction Data Control 0 Register, offset: 0x2C */ __IO uint32_t VIDEO_PLL1_FDIV_CTL1; /**< VIDEO PLL1 Divide and Fraction Data Control 1 Register, offset: 0x30 */ __IO uint32_t VIDEO_PLL1_SSCG_CTRL; /**< VIDEO PLL1 PLL SSCG Control Register, offset: 0x34 */ __IO uint32_t VIDEO_PLL1_MNIT_CTRL; /**< VIDEO PLL1 PLL Monitoring Control Register, offset: 0x38 */ uint8_t RESERVED_0[20]; __IO uint32_t DRAM_PLL_GEN_CTRL; /**< DRAM PLL General Function Control Register, offset: 0x50 */ __IO uint32_t DRAM_PLL_FDIV_CTL0; /**< DRAM PLL Divide and Fraction Data Control 0 Register, offset: 0x54 */ __IO uint32_t DRAM_PLL_FDIV_CTL1; /**< DRAM PLL Divide and Fraction Data Control 1 Register, offset: 0x58 */ __IO uint32_t DRAM_PLL_SSCG_CTRL; /**< DRAM PLL PLL SSCG Control Register, offset: 0x5C */ __IO uint32_t DRAM_PLL_MNIT_CTRL; /**< DRAM PLL PLL Monitoring Control Register, offset: 0x60 */ __IO uint32_t GPU_PLL_GEN_CTRL; /**< GPU PLL General Function Control Register, offset: 0x64 */ __IO uint32_t GPU_PLL_FDIV_CTL0; /**< GPU PLL Divide and Fraction Data Control 0 Register, offset: 0x68 */ __IO uint32_t GPU_PLL_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x6C */ __IO uint32_t GPU_PLL_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x70 */ __IO uint32_t M7_ALT_PLL_GEN_CTRL; /**< M7 Alternate PLL General Function Control Register, offset: 0x74 */ __IO uint32_t M7_ALT_PLL_FDIV_CTL0; /**< M7 Alternate PLL Divide and Fraction Data Control 0 Register, offset: 0x78 */ __IO uint32_t M7_ALT_PLL_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x7C */ __IO uint32_t M7_ALT_PLL_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x80 */ __IO uint32_t ARM_PLL_GEN_CTRL; /**< ARM PLL General Function Control Register, offset: 0x84 */ __IO uint32_t ARM_PLL_FDIV_CTL0; /**< ARM PLL Divide and Fraction Data Control 0 Register, offset: 0x88 */ __IO uint32_t ARM_PLL_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x8C */ __IO uint32_t ARM_PLL_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x90 */ __IO uint32_t SYS_PLL1_GEN_CTRL; /**< SYS PLL1 General Function Control Register, offset: 0x94 */ __IO uint32_t SYS_PLL1_FDIV_CTL0; /**< SYS PLL1 Divide and Fraction Data Control 0 Register, offset: 0x98 */ __IO uint32_t SYS_PLL1_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x9C */ uint8_t RESERVED_1[96]; __IO uint32_t SYS_PLL1_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x100 */ __IO uint32_t SYS_PLL2_GEN_CTRL; /**< SYS PLL2 General Function Control Register, offset: 0x104 */ __IO uint32_t SYS_PLL2_FDIV_CTL0; /**< SYS PLL2 Divide and Fraction Data Control 0 Register, offset: 0x108 */ __IO uint32_t SYS_PLL2_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x10C */ __IO uint32_t SYS_PLL2_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x110 */ __IO uint32_t SYS_PLL3_GEN_CTRL; /**< SYS PLL3 General Function Control Register, offset: 0x114 */ __IO uint32_t SYS_PLL3_FDIV_CTL0; /**< SYS PLL3 Divide and Fraction Data Control 0 Register, offset: 0x118 */ __IO uint32_t SYS_PLL3_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x11C */ __IO uint32_t SYS_PLL3_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x120 */ __IO uint32_t OSC_MISC_CFG; /**< Osc Misc Configuration Register, offset: 0x124 */ __IO uint32_t ANAMIX_PLL_MNIT_CTL; /**< PLL Clock Output for Test Enable and Select Register, offset: 0x128 */ uint8_t RESERVED_2[1748]; __I uint32_t DIGPROG; /**< DIGPROG Register, offset: 0x800 */ } CCM_ANALOG_Type; /* ---------------------------------------------------------------------------- -- CCM_ANALOG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks * @{ */ /*! @name AUDIO_PLL1_GEN_CTRL - AUDIO PLL1 General Function Control Register */ /*! @{ */ #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U) /*! PLL_REF_CLK_SEL * 0b00..SYS_XTAL * 0b01..PAD_CLK * 0b10..Reserved * 0b11..Reserved */ #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U) /*! PAD_CLK_SEL * 0b00..CLKIN1 XOR CLKIN2 * 0b01..CLKIN2 * 0b10..CLKIN1 * 0b11..Reserved */ #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_MASK) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_MASK) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x2000U) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (13U) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_MASK) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U) #define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_MASK) /*! @} */ /*! @name AUDIO_PLL1_FDIV_CTL0 - AUDIO PLL1 Divide and Fraction Data Control 0 Register */ /*! @{ */ #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U) #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U) #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK) #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U) #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U) #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK) #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U) #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U) #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK) /*! @} */ /*! @name AUDIO_PLL1_FDIV_CTL1 - AUDIO PLL1 Divide and Fraction Data Control 1 Register */ /*! @{ */ #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU) #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT (0U) #define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_MASK) /*! @} */ /*! @name AUDIO_PLL1_SSCG_CTRL - AUDIO PLL1 PLL SSCG Control Register */ /*! @{ */ #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_MASK (0x3U) #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_SHIFT (0U) /*! SEL_PF * 0b00..Down spread * 0b01..Up spread * 0b1x..Center spread */ #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_MASK) #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U) #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U) #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK) #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U) #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U) #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK) #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_MASK (0x80000000U) #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT (31U) #define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_MASK) /*! @} */ /*! @name AUDIO_PLL1_MNIT_CTRL - AUDIO PLL1 PLL Monitoring Control Register */ /*! @{ */ #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_MASK (0x7U) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_SHIFT (0U) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_MASK) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_MASK (0x8U) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_SHIFT (3U) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_MASK) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_MASK (0x1F0U) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_SHIFT (4U) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_MASK) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_MASK (0x4000U) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_SHIFT (14U) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_MASK) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_MASK (0x8000U) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_SHIFT (15U) /*! FSEL * 0b0..FEED_OUT = FREF * 0b1..FEED_OUT = FEED */ #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_MASK) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U) /*! AFCINIT_SEL * 0b0..nominal delay * 0b1..nominal delay * 2 */ #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U) /*! PBIAS_CTRL * 0b0..0.50*VDD * 0b1..0.67*VDD */ #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x100000U) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (20U) #define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_MASK) /*! @} */ /*! @name AUDIO_PLL2_GEN_CTRL - AUDIO PLL2 General Function Control Register */ /*! @{ */ #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U) /*! PLL_REF_CLK_SEL * 0b00..SYS_XTAL * 0b01..PAD_CLK * 0b10..Reserved * 0b11..Reserved */ #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U) /*! PAD_CLK_SEL * 0b00..CLKIN1 XOR CLKIN2 * 0b01..CLKIN2 * 0b10..CLKIN1 * 0b11..Reserved */ #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_MASK (0x10U) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT (4U) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_MASK) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_MASK (0x200U) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT (9U) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_MASK) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_MASK (0x2000U) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT (13U) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_MASK) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_MASK (0x80000000U) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_SHIFT (31U) #define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_MASK) /*! @} */ /*! @name AUDIO_PLL2_FDIV_CTL0 - AUDIO PLL2 Divide and Fraction Data Control 0 Register */ /*! @{ */ #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U) #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U) #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK) #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U) #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U) #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK) #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U) #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U) #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK) /*! @} */ /*! @name AUDIO_PLL2_FDIV_CTL1 - AUDIO PLL2 Divide and Fraction Data Control 1 Register */ /*! @{ */ #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU) #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_SHIFT (0U) #define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_MASK) /*! @} */ /*! @name AUDIO_PLL2_SSCG_CTRL - AUDIO PLL2 PLL SSCG Control Register */ /*! @{ */ #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_MASK (0x3U) #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_SHIFT (0U) /*! SEL_PF * 0b00..Down spread * 0b01..Up spread * 0b1x..Center spread */ #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_MASK) #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U) #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U) #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_MASK) #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U) #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U) #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_MASK) #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_MASK (0x80000000U) #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_SHIFT (31U) #define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_MASK) /*! @} */ /*! @name AUDIO_PLL2_MNIT_CTRL - AUDIO PLL2 PLL Monitoring Control Register */ /*! @{ */ #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_MASK (0x7U) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_SHIFT (0U) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_MASK) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_MASK (0x8U) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_SHIFT (3U) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_MASK) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_MASK (0x1F0U) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_SHIFT (4U) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_MASK) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_MASK (0x4000U) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_SHIFT (14U) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_MASK) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_MASK (0x8000U) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_SHIFT (15U) /*! FSEL * 0b0..FEED_OUT = FREF * 0b1..FEED_OUT = FEED */ #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_MASK) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U) /*! AFCINIT_SEL * 0b0..nominal delay * 0b1..nominal delay * 2 */ #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U) /*! PBIAS_CTRL * 0b0..0.50*VDD * 0b1..0.67*VDD */ #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_MASK (0x100000U) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_SHIFT (20U) #define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_SHIFT)) & \ CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_MASK) /*! @} */ /*! @name VIDEO_PLL1_GEN_CTRL - VIDEO PLL1 General Function Control Register */ /*! @{ */ #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U) /*! PLL_REF_CLK_SEL * 0b00..SYS_XTAL * 0b01..PAD_CLK * 0b10..Reserved * 0b11..Reserved */ #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U) /*! PAD_CLK_SEL * 0b00..CLKIN1 XOR CLKIN2 * 0b01..CLKIN2 * 0b10..CLKIN1 * 0b11..Reserved */ #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_MASK) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_MASK) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x2000U) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (13U) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_MASK) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U) #define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_MASK) /*! @} */ /*! @name VIDEO_PLL1_FDIV_CTL0 - VIDEO PLL1 Divide and Fraction Data Control 0 Register */ /*! @{ */ #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U) #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U) #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK) #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U) #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U) #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK) #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U) #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U) #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK) /*! @} */ /*! @name VIDEO_PLL1_FDIV_CTL1 - VIDEO PLL1 Divide and Fraction Data Control 1 Register */ /*! @{ */ #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU) #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT (0U) #define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_MASK) /*! @} */ /*! @name VIDEO_PLL1_SSCG_CTRL - VIDEO PLL1 PLL SSCG Control Register */ /*! @{ */ #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_MASK (0x3U) #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_SHIFT (0U) /*! SEL_PF * 0b00..Down spread * 0b01..Up spread * 0b1x..Center spread */ #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_MASK) #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U) #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U) #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK) #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U) #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U) #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK) #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_MASK (0x80000000U) #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT (31U) #define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_MASK) /*! @} */ /*! @name VIDEO_PLL1_MNIT_CTRL - VIDEO PLL1 PLL Monitoring Control Register */ /*! @{ */ #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_MASK (0x7U) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_SHIFT (0U) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_MASK) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_MASK (0x8U) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_SHIFT (3U) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_MASK) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_MASK (0x1F0U) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_SHIFT (4U) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_MASK) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_MASK (0x4000U) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_SHIFT (14U) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_MASK) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_MASK (0x8000U) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_SHIFT (15U) /*! FSEL * 0b0..FEED_OUT = FREF * 0b1..FEED_OUT = FEED */ #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_MASK) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U) /*! AFCINIT_SEL * 0b0..nominal delay * 0b1..nominal delay * 2 */ #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U) /*! PBIAS_CTRL * 0b0..0.50*VDD * 0b1..0.67*VDD */ #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x100000U) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (20U) #define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & \ CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_MASK) /*! @} */ /*! @name DRAM_PLL_GEN_CTRL - DRAM PLL General Function Control Register */ /*! @{ */ #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U) /*! PLL_REF_CLK_SEL * 0b00..SYS_XTAL * 0b01..PAD_CLK * 0b10..Reserved * 0b11..Reserved */ #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U) /*! PAD_CLK_SEL * 0b00..CLKIN1 XOR CLKIN2 * 0b01..CLKIN2 * 0b10..CLKIN1 * 0b11..Reserved */ #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_MASK) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_MASK (0x200U) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT (9U) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_MASK) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_MASK (0x2000U) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT (13U) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_MASK) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U) #define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_MASK) /*! @} */ /*! @name DRAM_PLL_FDIV_CTL0 - DRAM PLL Divide and Fraction Data Control 0 Register */ /*! @{ */ #define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U) #define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U) #define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK) #define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U) #define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U) #define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK) #define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U) #define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U) #define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK) /*! @} */ /*! @name DRAM_PLL_FDIV_CTL1 - DRAM PLL Divide and Fraction Data Control 1 Register */ /*! @{ */ #define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU) #define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_SHIFT (0U) #define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_MASK) /*! @} */ /*! @name DRAM_PLL_SSCG_CTRL - DRAM PLL PLL SSCG Control Register */ /*! @{ */ #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_MASK (0x3U) #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_SHIFT (0U) /*! SEL_PF * 0b00..Down spread * 0b01..Up spread * 0b1x..Center spread */ #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_MASK) #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U) #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U) #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_MASK) #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U) #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U) #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_MASK) #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_MASK (0x80000000U) #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_SHIFT (31U) #define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_MASK) /*! @} */ /*! @name DRAM_PLL_MNIT_CTRL - DRAM PLL PLL Monitoring Control Register */ /*! @{ */ #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_MASK (0x7U) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_SHIFT (0U) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_MASK) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_MASK (0x8U) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_SHIFT (3U) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_MASK) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_MASK (0x1F0U) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_SHIFT (4U) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_MASK) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_MASK (0x4000U) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_SHIFT (14U) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_MASK) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_MASK (0x8000U) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_SHIFT (15U) /*! FSEL * 0b0..FEED_OUT = FREF * 0b1..FEED_OUT = FEED */ #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_MASK) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U) /*! AFCINIT_SEL * 0b0..nominal delay * 0b1..nominal delay * 2 */ #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U) /*! PBIAS_CTRL * 0b0..0.50*VDD * 0b1..0.67*VDD */ #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_MASK (0x100000U) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_SHIFT (20U) #define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & \ CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_MASK) /*! @} */ /*! @name GPU_PLL_GEN_CTRL - GPU PLL General Function Control Register */ /*! @{ */ #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U) /*! PLL_REF_CLK_SEL * 0b00..SYS_XTAL * 0b01..PAD_CLK * 0b10..Reserved * 0b11..Reserved */ #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \ CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U) /*! PAD_CLK_SEL * 0b00..CLKIN1 XOR CLKIN2 * 0b01..CLKIN2 * 0b10..CLKIN1 * 0b11..Reserved */ #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \ CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & \ CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_MASK) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \ CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_MASK (0x200U) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_SHIFT (9U) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_SHIFT)) & \ CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_MASK) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & \ CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_MASK) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \ CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U) /*! PLL_LOCK_SEL * 0b0..Using PLL maximum lock time * 0b1..Using PLL output lock */ #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & \ CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U) #define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & \ CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_MASK) /*! @} */ /*! @name GPU_PLL_FDIV_CTL0 - GPU PLL Divide and Fraction Data Control 0 Register */ /*! @{ */ #define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U) #define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U) #define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \ CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK) #define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U) #define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U) #define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \ CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK) #define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U) #define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U) #define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \ CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK) /*! @} */ /*! @name GPU_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */ /*! @{ */ #define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U) #define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U) #define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & \ CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK) #define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU) #define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U) #define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & \ CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK) #define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U) #define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U) #define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & \ CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK) /*! @} */ /*! @name GPU_PLL_MNIT_CTRL - PLL Monitoring Control Register */ /*! @{ */ #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_MASK (0x3U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_SHIFT (0U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_MASK) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & \ CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_MASK) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & \ CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_MASK) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & \ CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_MASK) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_MASK (0x4000U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_SHIFT (14U) /*! FSEL * 0b0..FEED_OUT = FREF * 0b1..FEED_OUT = FEED */ #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_MASK) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U) /*! AFCINIT_SEL * 0b0..nominal delay * 0b1..nominal delay * 2 */ #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \ CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \ CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U) /*! PBIAS_CTRL * 0b0..0.50*VDD * 0b1..0.67*VDD */ #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \ CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & \ CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_MASK) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & \ CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_MASK) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U) #define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & \ CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_MASK) /*! @} */ /*! @name M7_ALT_PLL_GEN_CTRL - M7 Alternate PLL General Function Control Register */ /*! @{ */ #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U) /*! PLL_REF_CLK_SEL * 0b00..SYS_XTAL * 0b01..PAD_CLK * 0b10..Reserved * 0b11..Reserved */ #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U) /*! PAD_CLK_SEL * 0b00..CLKIN1 XOR CLKIN2 * 0b01..CLKIN2 * 0b10..CLKIN1 * 0b11..Reserved */ #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PAD_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PAD_CLK_SEL_MASK) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_BYPASS_MASK) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_MASK (0x200U) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_SHIFT (9U) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_MASK) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_MASK) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U) /*! PLL_LOCK_SEL * 0b0..Using PLL maximum lock time * 0b1..Using PLL output lock */ #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U) #define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_MASK) /*! @} */ /*! @name M7_ALT_PLL_FDIV_CTL0 - M7 Alternate PLL Divide and Fraction Data Control 0 Register */ /*! @{ */ #define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U) #define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U) #define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_POST_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_POST_DIV_MASK) #define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U) #define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U) #define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_PRE_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK) #define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U) #define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U) #define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK) /*! @} */ /*! @name M7_ALT_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */ /*! @{ */ #define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U) #define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U) #define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_IN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK) #define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU) #define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U) #define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK) #define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U) #define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U) #define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK) /*! @} */ /*! @name M7_ALT_PLL_MNIT_CTRL - PLL Monitoring Control Register */ /*! @{ */ #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_ICP_MASK (0x3U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_ICP_SHIFT (0U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_ICP(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_ICP_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_ICP_MASK) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_EN_MASK) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_EXTAFC(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_EXTAFC_MASK) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FEED_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FEED_EN_MASK) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FSEL_MASK (0x4000U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FSEL_SHIFT (14U) /*! FSEL * 0b0..FEED_OUT = FREF * 0b1..FEED_OUT = FEED */ #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FSEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FSEL_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FSEL_MASK) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U) /*! AFCINIT_SEL * 0b0..nominal delay * 0b1..nominal delay * 2 */ #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFCINIT_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFCINIT_SEL_MASK) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U) /*! PBIAS_CTRL * 0b0..0.50*VDD * 0b1..0.67*VDD */ #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_MASK) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_SEL_MASK) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FOUT_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FOUT_MASK_MASK) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U) #define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_LRD_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & \ CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_LRD_EN_MASK) /*! @} */ /*! @name ARM_PLL_GEN_CTRL - ARM PLL General Function Control Register */ /*! @{ */ #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U) /*! PLL_REF_CLK_SEL * 0b00..SYS_XTAL * 0b01..PAD_CLK * 0b10..Reserved * 0b11..Reserved */ #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \ CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U) /*! PAD_CLK_SEL * 0b00..CLKIN1 XOR CLKIN2 * 0b01..CLKIN2 * 0b10..CLKIN1 * 0b11..Reserved */ #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \ CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & \ CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_MASK) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \ CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_MASK (0x200U) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT (9U) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT)) & \ CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_MASK) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & \ CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_MASK) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \ CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U) /*! PLL_LOCK_SEL * 0b0..Using PLL maximum lock time * 0b1..Using PLL output lock */ #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & \ CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U) #define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & \ CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_MASK) /*! @} */ /*! @name ARM_PLL_FDIV_CTL0 - ARM PLL Divide and Fraction Data Control 0 Register */ /*! @{ */ #define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U) #define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U) #define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \ CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK) #define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U) #define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U) #define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \ CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK) #define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U) #define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U) #define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \ CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK) /*! @} */ /*! @name ARM_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */ /*! @{ */ #define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U) #define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U) #define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & \ CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK) #define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU) #define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U) #define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & \ CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK) #define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U) #define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U) #define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & \ CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK) /*! @} */ /*! @name ARM_PLL_MNIT_CTRL - PLL Monitoring Control Register */ /*! @{ */ #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_MASK (0x3U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_SHIFT (0U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_MASK) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & \ CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_MASK) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & \ CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_MASK) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & \ CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_MASK) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_MASK (0x4000U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_SHIFT (14U) /*! FSEL * 0b0..FEED_OUT = FREF * 0b1..FEED_OUT = FEED */ #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_MASK) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U) /*! AFCINIT_SEL * 0b0..nominal delay * 0b1..nominal delay * 2 */ #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \ CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \ CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U) /*! PBIAS_CTRL * 0b0..0.50*VDD * 0b1..0.67*VDD */ #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \ CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & \ CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_MASK) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & \ CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_MASK) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U) #define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & \ CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_MASK) /*! @} */ /*! @name SYS_PLL1_GEN_CTRL - SYS PLL1 General Function Control Register */ /*! @{ */ #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U) /*! PLL_REF_CLK_SEL * 0b00..SYS_XTAL * 0b01..PAD_CLK * 0b10..Reserved * 0b11..Reserved */ #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U) /*! PAD_CLK_SEL * 0b00..CLKIN1 XOR CLKIN2 * 0b01..CLKIN2 * 0b10..CLKIN1 * 0b11..Reserved */ #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x800U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (11U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK (0x1000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT (12U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_MASK (0x2000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT (13U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK (0x4000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT (14U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_MASK (0x8000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT (15U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK (0x10000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT (16U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_MASK (0x20000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT (17U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK (0x40000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT (18U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_MASK (0x80000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT (19U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK (0x100000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT (20U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_MASK (0x200000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT (21U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK (0x400000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT (22U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_MASK (0x800000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT (23U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK (0x1000000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT (24U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_MASK (0x2000000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT (25U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK (0x4000000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT (26U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_MASK (0x8000000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT (27U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U) /*! PLL_LOCK_SEL * 0b0..Using PLL maximum lock time * 0b1..Using PLL output lock */ #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_MASK) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U) #define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK) /*! @} */ /*! @name SYS_PLL1_FDIV_CTL0 - SYS PLL1 Divide and Fraction Data Control 0 Register */ /*! @{ */ #define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U) #define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U) #define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK) #define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U) #define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U) #define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK) #define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U) #define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U) #define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK) /*! @} */ /*! @name SYS_PLL1_LOCKD_CTRL - PLL Lock Detector Control Register */ /*! @{ */ #define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U) #define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U) #define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_MASK) #define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU) #define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U) #define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_MASK) #define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U) #define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U) #define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_MASK) /*! @} */ /*! @name SYS_PLL1_MNIT_CTRL - PLL Monitoring Control Register */ /*! @{ */ #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_MASK (0x3U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_SHIFT (0U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_MASK) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_MASK (0x4U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_SHIFT (2U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_MASK) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_MASK (0xF8U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_SHIFT (3U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_MASK) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_MASK (0x2000U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_SHIFT (13U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_MASK) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_MASK (0x4000U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_SHIFT (14U) /*! FSEL * 0b0..FEED_OUT = FREF * 0b1..FEED_OUT = FEED */ #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_MASK) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U) /*! AFCINIT_SEL * 0b0..nominal delay * 0b1..nominal delay * 2 */ #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U) /*! PBIAS_CTRL * 0b0..0.50*VDD * 0b1..0.67*VDD */ #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x80000U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (19U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_MASK) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_MASK (0x100000U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_SHIFT (20U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_MASK) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_MASK (0x200000U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_SHIFT (21U) #define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_SHIFT)) & \ CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_MASK) /*! @} */ /*! @name SYS_PLL2_GEN_CTRL - SYS PLL2 General Function Control Register */ /*! @{ */ #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U) /*! PLL_REF_CLK_SEL * 0b00..SYS_XTAL * 0b01..PAD_CLK * 0b10..Reserved * 0b11..Reserved */ #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U) /*! PAD_CLK_SEL * 0b00..CLKIN1 XOR CLKIN2 * 0b01..CLKIN2 * 0b10..CLKIN1 * 0b11..Reserved */ #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_MASK (0x10U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT (4U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_MASK (0x200U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT (9U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_MASK (0x800U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT (11U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK (0x1000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT (12U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_MASK (0x2000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT (13U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK (0x4000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT (14U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_MASK (0x8000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT (15U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK (0x10000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT (16U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_MASK (0x20000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT (17U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK (0x40000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT (18U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_MASK (0x80000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT (19U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK (0x100000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT (20U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_MASK (0x200000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT (21U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK (0x400000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT (22U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_MASK (0x800000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT (23U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK (0x1000000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT (24U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_MASK (0x2000000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT (25U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK (0x4000000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT (26U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_MASK (0x8000000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT (27U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U) /*! PLL_LOCK_SEL * 0b0..Using PLL maximum lock time * 0b1..Using PLL output lock */ #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_MASK) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_MASK (0x80000000U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SHIFT (31U) #define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_MASK) /*! @} */ /*! @name SYS_PLL2_FDIV_CTL0 - SYS PLL2 Divide and Fraction Data Control 0 Register */ /*! @{ */ #define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U) #define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U) #define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK) #define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U) #define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U) #define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK) #define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U) #define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U) #define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK) /*! @} */ /*! @name SYS_PLL2_LOCKD_CTRL - PLL Lock Detector Control Register */ /*! @{ */ #define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U) #define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U) #define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_MASK) #define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU) #define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U) #define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_MASK) #define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U) #define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U) #define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_MASK) /*! @} */ /*! @name SYS_PLL2_MNIT_CTRL - PLL Monitoring Control Register */ /*! @{ */ #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_MASK (0x3U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_SHIFT (0U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_MASK) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_MASK (0x4U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_SHIFT (2U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_MASK) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_MASK (0xF8U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_SHIFT (3U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_MASK) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_MASK (0x2000U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_SHIFT (13U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_MASK) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_MASK (0x4000U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_SHIFT (14U) /*! FSEL * 0b0..FEED_OUT = FREF * 0b1..FEED_OUT = FEED */ #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_MASK) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U) /*! AFCINIT_SEL * 0b0..nominal delay * 0b1..nominal delay * 2 */ #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U) /*! PBIAS_CTRL * 0b0..0.50*VDD * 0b1..0.67*VDD */ #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_MASK (0x80000U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_SHIFT (19U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_MASK) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_MASK (0x100000U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_SHIFT (20U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_MASK) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_MASK (0x200000U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_SHIFT (21U) #define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_SHIFT)) & \ CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_MASK) /*! @} */ /*! @name SYS_PLL3_GEN_CTRL - SYS PLL3 General Function Control Register */ /*! @{ */ #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U) /*! PLL_REF_CLK_SEL * 0b00..SYS_XTAL * 0b01..PAD_CLK * 0b10..Reserved * 0b11..Reserved */ #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_MASK) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U) /*! PAD_CLK_SEL * 0b00..CLKIN1 XOR CLKIN2 * 0b01..CLKIN2 * 0b10..CLKIN1 * 0b11..Reserved */ #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_MASK) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_MASK (0x10U) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT (4U) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_MASK) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_MASK (0x200U) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT (9U) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_MASK) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_MASK (0x800U) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT (11U) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_MASK) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_MASK) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U) /*! PLL_LOCK_SEL * 0b0..Using PLL maximum lock time * 0b1..Using PLL output lock */ #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_MASK) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_MASK (0x80000000U) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SHIFT (31U) #define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_MASK) /*! @} */ /*! @name SYS_PLL3_FDIV_CTL0 - SYS PLL3 Divide and Fraction Data Control 0 Register */ /*! @{ */ #define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U) #define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U) #define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_MASK) #define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U) #define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U) #define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_MASK) #define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U) #define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U) #define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_MASK) /*! @} */ /*! @name SYS_PLL3_LOCKD_CTRL - PLL Lock Detector Control Register */ /*! @{ */ #define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U) #define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U) #define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_MASK) #define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU) #define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U) #define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_MASK) #define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U) #define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U) #define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_MASK) /*! @} */ /*! @name SYS_PLL3_MNIT_CTRL - PLL Monitoring Control Register */ /*! @{ */ #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_MASK (0x3U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_SHIFT (0U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_MASK) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_MASK (0x4U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_SHIFT (2U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_MASK) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_MASK (0xF8U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_SHIFT (3U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_MASK) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_MASK (0x2000U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_SHIFT (13U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_MASK) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_MASK (0x4000U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_SHIFT (14U) /*! FSEL * 0b0..FEED_OUT = FREF * 0b1..FEED_OUT = FEED */ #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_MASK) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U) /*! AFCINIT_SEL * 0b0..nominal delay * 0b1..nominal delay * 2 */ #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_MASK) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_MASK) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U) /*! PBIAS_CTRL * 0b0..0.50*VDD * 0b1..0.67*VDD */ #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_MASK) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_MASK (0x80000U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_SHIFT (19U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_MASK) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_MASK (0x100000U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_SHIFT (20U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_MASK) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_MASK (0x200000U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_SHIFT (21U) #define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_SHIFT)) & \ CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_MASK) /*! @} */ /*! @name OSC_MISC_CFG - Osc Misc Configuration Register */ /*! @{ */ #define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK (0x1U) #define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT (0U) /*! OSC_32K_SEL * 0b0..Divided by 24M clock * 0b1..32K Oscillator */ #define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT)) & \ CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK) /*! @} */ /*! @name ANAMIX_PLL_MNIT_CTL - PLL Clock Output for Test Enable and Select Register */ /*! @{ */ #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_MASK (0xFU) #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_SHIFT (0U) #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_SHIFT)) & \ CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_MASK) #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_MASK (0xF0U) #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_SHIFT (4U) #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_SHIFT)) & \ CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_MASK) #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_MASK (0x100U) #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_SHIFT (8U) #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_SHIFT)) & \ CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_MASK) #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_MASK (0xF0000U) #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_SHIFT (16U) #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_SHIFT)) & \ CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_MASK) #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_MASK (0xF00000U) #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_SHIFT (20U) #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_SHIFT)) & \ CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_MASK) #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_MASK (0x1000000U) #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_SHIFT (24U) #define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_SHIFT)) & \ CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_MASK) /*! @} */ /*! @name DIGPROG - DIGPROG Register */ /*! @{ */ #define CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK (0xFFU) #define CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT (0U) #define CCM_ANALOG_DIGPROG_DIGPROG_MINOR(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK) #define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK (0xFF00U) #define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT (8U) #define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT)) & \ CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK) #define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U) #define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT (16U) #define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER(x) \ (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT)) & \ CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK) /*! @} */ /*! * @} */ /* end of group CCM_ANALOG_Register_Masks */ /* CCM_ANALOG - Peripheral instance base addresses */ /** Peripheral CCM_ANALOG base address */ #define CCM_ANALOG_BASE (0x30360000u) /** Peripheral CCM_ANALOG base pointer */ #define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE) /** Array initializer of CCM_ANALOG peripheral base addresses */ #define CCM_ANALOG_BASE_ADDRS \ { \ CCM_ANALOG_BASE \ } /** Array initializer of CCM_ANALOG peripheral base pointers */ #define CCM_ANALOG_BASE_PTRS \ { \ CCM_ANALOG \ } /*! * @} */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DDRC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DDRC_Peripheral_Access_Layer DDRC Peripheral Access Layer * @{ */ /** DDRC - Register Layout Typedef */ typedef struct { __IO uint32_t MSTR; /**< Master Register0, offset: 0x0 */ __I uint32_t STAT; /**< Operating Mode Status Register, offset: 0x4 */ __IO uint32_t MSTR1; /**< Operating Mode Status Register, offset: 0x8 */ __IO uint32_t MRCTRL3; /**< Operating Mode Status Register, offset: 0xC */ __IO uint32_t MRCTRL0; /**< Mode Register Read/Write Control Register 0., offset: 0x10 */ __IO uint32_t MRCTRL1; /**< Mode Register Read/Write Control Register 1, offset: 0x14 */ __I uint32_t MRSTAT; /**< Mode Register Read/Write Status Register, offset: 0x18 */ __IO uint32_t MRCTRL2; /**< Mode Register Read/Write Control Register 2, offset: 0x1C */ __IO uint32_t DERATEEN; /**< Temperature Derate Enable Register, offset: 0x20 */ __IO uint32_t DERATEINT; /**< Temperature Derate Interval Register, offset: 0x24 */ uint8_t RESERVED_0[8]; __IO uint32_t PWRCTL; /**< Low Power Control Register, offset: 0x30 */ __IO uint32_t PWRTMG; /**< Low Power Timing Register, offset: 0x34 */ __IO uint32_t HWLPCTL; /**< Hardware Low Power Control Register, offset: 0x38 */ uint8_t RESERVED_1[20]; __IO uint32_t RFSHCTL0; /**< Refresh Control Register 0, offset: 0x50 */ __IO uint32_t RFSHCTL1; /**< Refresh Control Register 1, offset: 0x54 */ uint8_t RESERVED_2[8]; __IO uint32_t RFSHCTL3; /**< Refresh Control Register 3, offset: 0x60 */ __IO uint32_t RFSHTMG; /**< Refresh Timing Register, offset: 0x64 */ uint8_t RESERVED_3[104]; __IO uint32_t INIT0; /**< SDRAM Initialization Register 0, offset: 0xD0 */ __IO uint32_t INIT1; /**< SDRAM Initialization Register 1, offset: 0xD4 */ __IO uint32_t INIT2; /**< SDRAM Initialization Register 2, offset: 0xD8 */ __IO uint32_t INIT3; /**< SDRAM Initialization Register 3, offset: 0xDC */ __IO uint32_t INIT4; /**< SDRAM Initialization Register 4, offset: 0xE0 */ __IO uint32_t INIT5; /**< SDRAM Initialization Register 5, offset: 0xE4 */ __IO uint32_t INIT6; /**< SDRAM Initialization Register 6, offset: 0xE8 */ __IO uint32_t INIT7; /**< SDRAM Initialization Register 7, offset: 0xEC */ __IO uint32_t DIMMCTL; /**< DIMM Control Register, offset: 0xF0 */ __IO uint32_t RANKCTL; /**< Rank Control Register, offset: 0xF4 */ uint8_t RESERVED_4[8]; __IO uint32_t DRAMTMG0; /**< SDRAM Timing Register 0, offset: 0x100 */ __IO uint32_t DRAMTMG1; /**< SDRAM Timing Register 1, offset: 0x104 */ __IO uint32_t DRAMTMG2; /**< SDRAM Timing Register 2, offset: 0x108 */ __IO uint32_t DRAMTMG3; /**< SDRAM Timing Register 3, offset: 0x10C */ __IO uint32_t DRAMTMG4; /**< SDRAM Timing Register 4, offset: 0x110 */ __IO uint32_t DRAMTMG5; /**< SDRAM Timing Register 5, offset: 0x114 */ __IO uint32_t DRAMTMG6; /**< SDRAM Timing Register 6, offset: 0x118 */ __IO uint32_t DRAMTMG7; /**< SDRAM Timing Register 7, offset: 0x11C */ __IO uint32_t DRAMTMG8; /**< SDRAM Timing Register 8, offset: 0x120 */ __IO uint32_t DRAMTMG9; /**< SDRAM Timing Register 9, offset: 0x124 */ __IO uint32_t DRAMTMG10; /**< SDRAM Timing Register 10, offset: 0x128 */ __IO uint32_t DRAMTMG11; /**< SDRAM Timing Register 11, offset: 0x12C */ __IO uint32_t DRAMTMG12; /**< SDRAM Timing Register 12, offset: 0x130 */ __IO uint32_t DRAMTMG13; /**< SDRAM Timing Register 13, offset: 0x134 */ __IO uint32_t DRAMTMG14; /**< SDRAM Timing Register 14, offset: 0x138 */ __IO uint32_t DRAMTMG15; /**< SDRAM Timing Register 15, offset: 0x13C */ uint8_t RESERVED_5[64]; __IO uint32_t ZQCTL0; /**< ZQ Control Register 0, offset: 0x180 */ __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ __IO uint32_t ZQCTL2; /**< ZQ Control Register 2, offset: 0x188 */ __I uint32_t ZQSTAT; /**< ZQ Status Register, offset: 0x18C */ __IO uint32_t DFITMG0; /**< DFI Timing Register 0, offset: 0x190 */ __IO uint32_t DFITMG1; /**< DFI Timing Register 1, offset: 0x194 */ __IO uint32_t DFILPCFG0; /**< DFI Low Power Configuration Register 0, offset: 0x198 */ __IO uint32_t DFILPCFG1; /**< DFI Low Power Configuration Register 1, offset: 0x19C */ __IO uint32_t DFIUPD0; /**< DFI Update Register 0, offset: 0x1A0 */ __IO uint32_t DFIUPD1; /**< DFI Update Register 1, offset: 0x1A4 */ __IO uint32_t DFIUPD2; /**< DFI Update Register 2, offset: 0x1A8 */ uint8_t RESERVED_6[4]; __IO uint32_t DFIMISC; /**< DFI Miscellaneous Control Register, offset: 0x1B0 */ __IO uint32_t DFITMG2; /**< DFI Timing Register 2, offset: 0x1B4 */ __IO uint32_t DFITMG3; /**< DFI Timing Register 3, offset: 0x1B8 */ __I uint32_t DFISTAT; /**< DFI Status Register, offset: 0x1BC */ __IO uint32_t DBICTL; /**< DM/DBI Control Register, offset: 0x1C0 */ uint8_t RESERVED_7[60]; __IO uint32_t ADDRMAP0; /**< Address Map Register 0, offset: 0x200 */ __IO uint32_t ADDRMAP1; /**< Address Map Register 1, offset: 0x204 */ __IO uint32_t ADDRMAP2; /**< Address Map Register 2, offset: 0x208 */ __IO uint32_t ADDRMAP3; /**< Address Map Register 3, offset: 0x20C */ __IO uint32_t ADDRMAP4; /**< Address Map Register 4, offset: 0x210 */ __IO uint32_t ADDRMAP5; /**< Address Map Register 5, offset: 0x214 */ __IO uint32_t ADDRMAP6; /**< Address Map Register 6, offset: 0x218 */ __IO uint32_t ADDRMAP7; /**< Address Map Register 7, offset: 0x21C */ __IO uint32_t ADDRMAP8; /**< Address Map Register 8, offset: 0x220 */ __IO uint32_t ADDRMAP9; /**< Address Map Register 9, offset: 0x224 */ __IO uint32_t ADDRMAP10; /**< Address Map Register 10, offset: 0x228 */ __IO uint32_t ADDRMAP11; /**< Address Map Register 11, offset: 0x22C */ uint8_t RESERVED_8[16]; __IO uint32_t ODTCFG; /**< ODT Configuration Register, offset: 0x240 */ __IO uint32_t ODTMAP; /**< ODT/Rank Map Register, offset: 0x244 */ uint8_t RESERVED_9[8]; __IO uint32_t SCHED; /**< Scheduler Control Register, offset: 0x250 */ __IO uint32_t SCHED1; /**< Scheduler Control Register 1, offset: 0x254 */ uint8_t RESERVED_10[4]; __IO uint32_t PERFHPR1; /**< High Priority Read CAM Register 1, offset: 0x25C */ uint8_t RESERVED_11[4]; __IO uint32_t PERFLPR1; /**< Low Priority Read CAM Register 1, offset: 0x264 */ uint8_t RESERVED_12[4]; __IO uint32_t PERFWR1; /**< Write CAM Register 1, offset: 0x26C */ uint8_t RESERVED_13[144]; __IO uint32_t DBG0; /**< Debug Register 0, offset: 0x300 */ __IO uint32_t DBG1; /**< Debug Register 1, offset: 0x304 */ __I uint32_t DBGCAM; /**< CAM Debug Register, offset: 0x308 */ __IO uint32_t DBGCMD; /**< Command Debug Register, offset: 0x30C */ __I uint32_t DBGSTAT; /**< Status Debug Register, offset: 0x310 */ uint8_t RESERVED_14[12]; __IO uint32_t SWCTL; /**< Software Register Programming Control Enable, offset: 0x320 */ __I uint32_t SWSTAT; /**< Software Register Programming Control Status, offset: 0x324 */ uint8_t RESERVED_15[68]; __IO uint32_t POISONCFG; /**< AXI Poison Configuration Register., offset: 0x36C */ __I uint32_t POISONSTAT; /**< AXI Poison Status Register, offset: 0x370 */ uint8_t RESERVED_16[136]; __I uint32_t PSTAT; /**< Port Status Register, offset: 0x3FC */ __IO uint32_t PCCFG; /**< Port Common Configuration Register, offset: 0x400 */ __IO uint32_t PCFGR_0; /**< Port n Configuration Read Register, offset: 0x404 */ __IO uint32_t PCFGW_0; /**< Port n Configuration Write Register, offset: 0x408 */ uint8_t RESERVED_17[132]; __IO uint32_t PCTRL_0; /**< Port n Control Register, offset: 0x490 */ __IO uint32_t PCFGQOS0_0; /**< Port n Read QoS Configuration Register 0, offset: 0x494 */ __IO uint32_t PCFGQOS1_0; /**< Port n Read QoS Configuration Register 1, offset: 0x498 */ __IO uint32_t PCFGWQOS0_0; /**< Port n Write QoS Configuration Register 0, offset: 0x49C */ __IO uint32_t PCFGWQOS1_0; /**< Port n Write QoS Configuration Register 1, offset: 0x4A0 */ uint8_t RESERVED_18[7036]; __IO uint32_t DERATEEN_SHADOW; /**< [SHADOW] Temperature Derate Enable Register, offset: 0x2020 */ __IO uint32_t DERATEINT_SHADOW; /**< [SHADOW] Temperature Derate Interval Register, offset: 0x2024 */ uint8_t RESERVED_19[40]; __IO uint32_t RFSHCTL0_SHADOW; /**< [SHADOW] Refresh Control Register 0, offset: 0x2050 */ uint8_t RESERVED_20[16]; __IO uint32_t RFSHTMG_SHADOW; /**< [SHADOW] Refresh Timing Register, offset: 0x2064 */ uint8_t RESERVED_21[116]; __IO uint32_t INIT3_SHADOW; /**< [SHADOW] SDRAM Initialization Register 3, offset: 0x20DC */ __IO uint32_t INIT4_SHADOW; /**< [SHADOW] SDRAM Initialization Register 4, offset: 0x20E0 */ uint8_t RESERVED_22[4]; __IO uint32_t INIT6_SHADOW; /**< [SHADOW] SDRAM Initialization Register 6, offset: 0x20E8 */ __IO uint32_t INIT7_SHADOW; /**< [SHADOW] SDRAM Initialization Register 7, offset: 0x20EC */ uint8_t RESERVED_23[16]; __IO uint32_t DRAMTMG0_SHADOW; /**< [SHADOW] SDRAM Timing Register 0, offset: 0x2100 */ __IO uint32_t DRAMTMG1_SHADOW; /**< [SHADOW] SDRAM Timing Register 1, offset: 0x2104 */ __IO uint32_t DRAMTMG2_SHADOW; /**< [SHADOW] SDRAM Timing Register 2, offset: 0x2108 */ __IO uint32_t DRAMTMG3_SHADOW; /**< [SHADOW] SDRAM Timing Register 3, offset: 0x210C */ __IO uint32_t DRAMTMG4_SHADOW; /**< [SHADOW] SDRAM Timing Register 4, offset: 0x2110 */ __IO uint32_t DRAMTMG5_SHADOW; /**< [SHADOW] SDRAM Timing Register 5, offset: 0x2114 */ __IO uint32_t DRAMTMG6_SHADOW; /**< [SHADOW] SDRAM Timing Register 6, offset: 0x2118 */ __IO uint32_t DRAMTMG7_SHADOW; /**< [SHADOW] SDRAM Timing Register 7, offset: 0x211C */ __IO uint32_t DRAMTMG8_SHADOW; /**< [SHADOW] SDRAM Timing Register 8, offset: 0x2120 */ __IO uint32_t DRAMTMG9_SHADOW; /**< [SHADOW] SDRAM Timing Register 9, offset: 0x2124 */ __IO uint32_t DRAMTMG10_SHADOW; /**< [SHADOW] SDRAM Timing Register 10, offset: 0x2128 */ __IO uint32_t DRAMTMG11_SHADOW; /**< [SHADOW] SDRAM Timing Register 11, offset: 0x212C */ __IO uint32_t DRAMTMG12_SHADOW; /**< [SHADOW] SDRAM Timing Register 12, offset: 0x2130 */ __IO uint32_t DRAMTMG13_SHADOW; /**< [SHADOW] SDRAM Timing Register 13, offset: 0x2134 */ __IO uint32_t DRAMTMG14_SHADOW; /**< [SHADOW] SDRAM Timing Register 14, offset: 0x2138 */ __IO uint32_t DRAMTMG15_SHADOW; /**< [SHADOW] SDRAM Timing Register 15, offset: 0x213C */ uint8_t RESERVED_24[64]; __IO uint32_t ZQCTL0_SHADOW; /**< [SHADOW] ZQ Control Register 0, offset: 0x2180 */ uint8_t RESERVED_25[12]; __IO uint32_t DFITMG0_SHADOW; /**< [SHADOW] DFI Timing Register 0, offset: 0x2190 */ __IO uint32_t DFITMG1_SHADOW; /**< [SHADOW] DFI Timing Register 1, offset: 0x2194 */ uint8_t RESERVED_26[28]; __IO uint32_t DFITMG2_SHADOW; /**< [SHADOW] DFI Timing Register 2, offset: 0x21B4 */ __IO uint32_t DFITMG3_SHADOW; /**< [SHADOW] DFI Timing Register 3, offset: 0x21B8 */ uint8_t RESERVED_27[132]; __IO uint32_t ODTCFG_SHADOW; /**< [SHADOW] ODT Configuration Register, offset: 0x2240 */ } DDRC_Type; /* ---------------------------------------------------------------------------- -- DDRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DDRC_Register_Masks DDRC Register Masks * @{ */ /*! @name MSTR - Master Register0 */ /*! @{ */ #define DDRC_MSTR_ddr3_MASK (0x1U) #define DDRC_MSTR_ddr3_SHIFT (0U) #define DDRC_MSTR_ddr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ddr3_SHIFT)) & DDRC_MSTR_ddr3_MASK) #define DDRC_MSTR_lpddr2_MASK (0x4U) #define DDRC_MSTR_lpddr2_SHIFT (2U) #define DDRC_MSTR_lpddr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr2_SHIFT)) & DDRC_MSTR_lpddr2_MASK) #define DDRC_MSTR_lpddr3_MASK (0x8U) #define DDRC_MSTR_lpddr3_SHIFT (3U) #define DDRC_MSTR_lpddr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr3_SHIFT)) & DDRC_MSTR_lpddr3_MASK) #define DDRC_MSTR_ddr4_MASK (0x10U) #define DDRC_MSTR_ddr4_SHIFT (4U) #define DDRC_MSTR_ddr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ddr4_SHIFT)) & DDRC_MSTR_ddr4_MASK) #define DDRC_MSTR_lpddr4_MASK (0x20U) #define DDRC_MSTR_lpddr4_SHIFT (5U) #define DDRC_MSTR_lpddr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr4_SHIFT)) & DDRC_MSTR_lpddr4_MASK) #define DDRC_MSTR_burstchop_MASK (0x200U) #define DDRC_MSTR_burstchop_SHIFT (9U) #define DDRC_MSTR_burstchop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_burstchop_SHIFT)) & DDRC_MSTR_burstchop_MASK) #define DDRC_MSTR_en_2t_timing_mode_MASK (0x400U) #define DDRC_MSTR_en_2t_timing_mode_SHIFT (10U) #define DDRC_MSTR_en_2t_timing_mode(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_en_2t_timing_mode_SHIFT)) & DDRC_MSTR_en_2t_timing_mode_MASK) #define DDRC_MSTR_geardown_mode_MASK (0x800U) #define DDRC_MSTR_geardown_mode_SHIFT (11U) #define DDRC_MSTR_geardown_mode(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_geardown_mode_SHIFT)) & DDRC_MSTR_geardown_mode_MASK) #define DDRC_MSTR_data_bus_width_MASK (0x3000U) #define DDRC_MSTR_data_bus_width_SHIFT (12U) #define DDRC_MSTR_data_bus_width(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_data_bus_width_SHIFT)) & DDRC_MSTR_data_bus_width_MASK) #define DDRC_MSTR_dll_off_mode_MASK (0x8000U) #define DDRC_MSTR_dll_off_mode_SHIFT (15U) #define DDRC_MSTR_dll_off_mode(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_dll_off_mode_SHIFT)) & DDRC_MSTR_dll_off_mode_MASK) #define DDRC_MSTR_burst_rdwr_MASK (0xF0000U) #define DDRC_MSTR_burst_rdwr_SHIFT (16U) /*! burst_rdwr - SDRAM burst length used * 0b0001..Burst length of 2 (only supported for mDDR) * 0b0010..Burst length of 4 * 0b0100..Burst length of 8 * 0b1000..Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) */ #define DDRC_MSTR_burst_rdwr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_burst_rdwr_SHIFT)) & DDRC_MSTR_burst_rdwr_MASK) #define DDRC_MSTR_frequency_ratio_MASK (0x400000U) #define DDRC_MSTR_frequency_ratio_SHIFT (22U) /*! frequency_ratio - Selects the Frequency Ratio * 0b0..1:2 Mode * 0b1..1:1 Mode */ #define DDRC_MSTR_frequency_ratio(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_frequency_ratio_SHIFT)) & DDRC_MSTR_frequency_ratio_MASK) #define DDRC_MSTR_active_ranks_MASK (0x3000000U) #define DDRC_MSTR_active_ranks_SHIFT (24U) #define DDRC_MSTR_active_ranks(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_active_ranks_SHIFT)) & DDRC_MSTR_active_ranks_MASK) #define DDRC_MSTR_frequency_mode_MASK (0x20000000U) #define DDRC_MSTR_frequency_mode_SHIFT (29U) /*! frequency_mode - Choose which registers are used. * 0b0..Original Registers * 0b1..Shadow Registers */ #define DDRC_MSTR_frequency_mode(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_frequency_mode_SHIFT)) & DDRC_MSTR_frequency_mode_MASK) #define DDRC_MSTR_device_config_MASK (0xC0000000U) #define DDRC_MSTR_device_config_SHIFT (30U) /*! device_config - Indicates the configuration of the device used in the system. * 0b00..x4 device * 0b01..x8 device * 0b10..x16 device * 0b11..x32 device */ #define DDRC_MSTR_device_config(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_device_config_SHIFT)) & DDRC_MSTR_device_config_MASK) /*! @} */ /*! @name STAT - Operating Mode Status Register */ /*! @{ */ #define DDRC_STAT_operating_mode_MASK (0x7U) #define DDRC_STAT_operating_mode_SHIFT (0U) #define DDRC_STAT_operating_mode(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_operating_mode_SHIFT)) & DDRC_STAT_operating_mode_MASK) #define DDRC_STAT_selfref_type_MASK (0x30U) #define DDRC_STAT_selfref_type_SHIFT (4U) /*! selfref_type - Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if * it was under Automatic Self Refresh control only or not. * 0b00..SDRAM is not in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by * CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still in parity error window or retry * is in-progress. 0b11..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was caused by * Automatic Self Refresh only. If retry is enabled, this guarantees SRE command is executed correctly without parity * error. 0b10..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was not caused solely under * Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software * (reg_ddrc_selfref_sw). If retry is enabled, this guarantees SRE command is executed correctly without parity */ #define DDRC_STAT_selfref_type(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_selfref_type_SHIFT)) & DDRC_STAT_selfref_type_MASK) #define DDRC_STAT_selfref_state_MASK (0x300U) #define DDRC_STAT_selfref_state_SHIFT (8U) /*! selfref_state - Self refresh state. This indicates self refresh or self refresh power down state * for LPDDR4. This register is used for frequency change and MRR/MRW access during self refresh. * 0b00..SDRAM is not in Self Refresh. * 0b01..Self refresh 1 * 0b10..Self refresh power down * 0b11..Self refresh */ #define DDRC_STAT_selfref_state(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_selfref_state_SHIFT)) & DDRC_STAT_selfref_state_MASK) /*! @} */ /*! @name MSTR1 - Operating Mode Status Register */ /*! @{ */ #define DDRC_MSTR1_rank_tmgreg_sel_MASK (0x3U) #define DDRC_MSTR1_rank_tmgreg_sel_SHIFT (0U) /*! rank_tmgreg_sel - rank_tmgreg_sel * 0b00..USE DRAMTMGx registers for the rank * 0b01..USE MRAMTMGx registers for the rank */ #define DDRC_MSTR1_rank_tmgreg_sel(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_rank_tmgreg_sel_SHIFT)) & DDRC_MSTR1_rank_tmgreg_sel_MASK) #define DDRC_MSTR1_alt_addrmap_en_MASK (0x10000U) #define DDRC_MSTR1_alt_addrmap_en_SHIFT (16U) /*! alt_addrmap_en - Enable Alternative Address Map * 0b0..Disable Alternative Address Map * 0b1..Enable Alternative Address Map */ #define DDRC_MSTR1_alt_addrmap_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_alt_addrmap_en_SHIFT)) & DDRC_MSTR1_alt_addrmap_en_MASK) /*! @} */ /*! @name MRCTRL3 - Operating Mode Status Register */ /*! @{ */ #define DDRC_MRCTRL3_mr_rank_sel_MASK (0x3U) #define DDRC_MRCTRL3_mr_rank_sel_SHIFT (0U) #define DDRC_MRCTRL3_mr_rank_sel(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL3_mr_rank_sel_SHIFT)) & DDRC_MRCTRL3_mr_rank_sel_MASK) /*! @} */ /*! @name MRCTRL0 - Mode Register Read/Write Control Register 0. */ /*! @{ */ #define DDRC_MRCTRL0_mr_type_MASK (0x1U) #define DDRC_MRCTRL0_mr_type_SHIFT (0U) /*! mr_type - Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. * 0b0..Write * 0b1..Read */ #define DDRC_MRCTRL0_mr_type(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_type_SHIFT)) & DDRC_MRCTRL0_mr_type_MASK) #define DDRC_MRCTRL0_mpr_en_MASK (0x2U) #define DDRC_MRCTRL0_mpr_en_SHIFT (1U) /*! mpr_en - Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4). * 0b0..MRS * 0b1..WR/RD for MPR */ #define DDRC_MRCTRL0_mpr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mpr_en_SHIFT)) & DDRC_MRCTRL0_mpr_en_MASK) #define DDRC_MRCTRL0_pda_en_MASK (0x4U) #define DDRC_MRCTRL0_pda_en_SHIFT (2U) /*! pda_en - Indicates whether the mode register operation is MRS in PDA mode or not. Note that when * pba_mode=1, PBA access is initiated instead of PDA access. * 0b0..MRS * 0b1..MRS in Per DRAM Addressability */ #define DDRC_MRCTRL0_pda_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_pda_en_SHIFT)) & DDRC_MRCTRL0_pda_en_MASK) #define DDRC_MRCTRL0_sw_init_int_MASK (0x8U) #define DDRC_MRCTRL0_sw_init_int_SHIFT (3U) /*! sw_init_int - Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before * automatic SDRAM initialization routine or not. For DDR4, this bit can be used to initialize the * DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit can be used to * program additional mode registers before automatic SDRAM initialization if necessary. In LPDDR4 * independent channel mode, note that this must be programmed to both channels beforehand. Note that * this must be cleared to 0 after completing Software operation. Otherwise, SDRAM * initialization routine will not re-start. * 0b0..Software intervention is not allowed * 0b1..Software intervention is allowed */ #define DDRC_MRCTRL0_sw_init_int(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_sw_init_int_SHIFT)) & DDRC_MRCTRL0_sw_init_int_MASK) #define DDRC_MRCTRL0_mr_rank_MASK (0x30U) #define DDRC_MRCTRL0_mr_rank_SHIFT (4U) #define DDRC_MRCTRL0_mr_rank(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_rank_SHIFT)) & DDRC_MRCTRL0_mr_rank_MASK) #define DDRC_MRCTRL0_mr_addr_MASK (0xF000U) #define DDRC_MRCTRL0_mr_addr_SHIFT (12U) /*! mr_addr - Address of the mode register that is to be written to. * 0b0000..MR0 * 0b0001..MR1 * 0b0010..MR2 * 0b0011..MR3 * 0b0100..MR4 * 0b0101..MR5 * 0b0110..MR6 * 0b0111..MR7 */ #define DDRC_MRCTRL0_mr_addr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_addr_SHIFT)) & DDRC_MRCTRL0_mr_addr_MASK) #define DDRC_MRCTRL0_pba_mode_MASK (0x40000000U) #define DDRC_MRCTRL0_pba_mode_SHIFT (30U) #define DDRC_MRCTRL0_pba_mode(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_pba_mode_SHIFT)) & DDRC_MRCTRL0_pba_mode_MASK) #define DDRC_MRCTRL0_mr_wr_MASK (0x80000000U) #define DDRC_MRCTRL0_mr_wr_SHIFT (31U) #define DDRC_MRCTRL0_mr_wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_wr_SHIFT)) & DDRC_MRCTRL0_mr_wr_MASK) /*! @} */ /*! @name MRCTRL1 - Mode Register Read/Write Control Register 1 */ /*! @{ */ #define DDRC_MRCTRL1_mr_data_MASK (0x3FFFFU) #define DDRC_MRCTRL1_mr_data_SHIFT (0U) #define DDRC_MRCTRL1_mr_data(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL1_mr_data_SHIFT)) & DDRC_MRCTRL1_mr_data_MASK) /*! @} */ /*! @name MRSTAT - Mode Register Read/Write Status Register */ /*! @{ */ #define DDRC_MRSTAT_mr_wr_busy_MASK (0x1U) #define DDRC_MRSTAT_mr_wr_busy_SHIFT (0U) /*! mr_wr_busy - The SoC core may initiate a MR write operation only if this signal is low. This * signal goes high in the clock after the DDRC accepts the MRW/MRR request. It goes low when the * MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when * 'MRSTAT.mr_wr_busy' is high. * 0b0..Indicates that the SoC core can initiate a mode register write operation * 0b1..Indicates that mode register write operation is in progress */ #define DDRC_MRSTAT_mr_wr_busy(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_mr_wr_busy_SHIFT)) & DDRC_MRSTAT_mr_wr_busy_MASK) #define DDRC_MRSTAT_pda_done_MASK (0x100U) #define DDRC_MRSTAT_pda_done_SHIFT (8U) /*! pda_done - The SoC core may initiate a MR write operation in PDA/PBA mode only if this signal is * low. This signal goes high when three consecutive MRS commands related to the PDA/PBA mode * are issued to the SDRAM. This signal goes low when MRCTRL0.pda_en becomes 0. Therefore, it is * recommended to write MRCTRL0.pda_en to 0 after this signal goes high in order to prepare to * perform PDA operation next time * 0b0..Indicates that mode register write operation related to PDA/PBA is in progress or has not started yet. * 0b1..Indicates that mode register write operation related to PDA/PBA has competed. */ #define DDRC_MRSTAT_pda_done(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_pda_done_SHIFT)) & DDRC_MRSTAT_pda_done_MASK) /*! @} */ /*! @name MRCTRL2 - Mode Register Read/Write Control Register 2 */ /*! @{ */ #define DDRC_MRCTRL2_mr_device_sel_MASK (0xFFFFFFFFU) #define DDRC_MRCTRL2_mr_device_sel_SHIFT (0U) #define DDRC_MRCTRL2_mr_device_sel(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL2_mr_device_sel_SHIFT)) & DDRC_MRCTRL2_mr_device_sel_MASK) /*! @} */ /*! @name DERATEEN - Temperature Derate Enable Register */ /*! @{ */ #define DDRC_DERATEEN_derate_enable_MASK (0x1U) #define DDRC_DERATEEN_derate_enable_SHIFT (0U) /*! derate_enable - Enables derating. Present only in designs configured to support * LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. * 0b0..Timing parameter derating is disabled * 0b1..Timing parameter derating is enabled using MR4 read value. */ #define DDRC_DERATEEN_derate_enable(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_enable_SHIFT)) & DDRC_DERATEEN_derate_enable_MASK) #define DDRC_DERATEEN_derate_value_MASK (0x2U) #define DDRC_DERATEEN_derate_value_SHIFT (1U) /*! derate_value - Derate value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 * Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a * core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this * register field should be set to 1; otherwise it should be set to 0. * 0b0..Derating uses +1 * 0b1..Derating uses +2 */ #define DDRC_DERATEEN_derate_value(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_value_SHIFT)) & DDRC_DERATEEN_derate_value_MASK) #define DDRC_DERATEEN_derate_byte_MASK (0xF0U) #define DDRC_DERATEEN_derate_byte_SHIFT (4U) #define DDRC_DERATEEN_derate_byte(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_byte_SHIFT)) & DDRC_DERATEEN_derate_byte_MASK) #define DDRC_DERATEEN_rc_derate_value_MASK (0x300U) #define DDRC_DERATEEN_rc_derate_value_SHIFT (8U) /*! rc_derate_value - Derate value of tRC for LPDDR4. Present only in designs configured to support * LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the * core_ddrc_core_clk period, and rounding up the next integer. * 0b00..Derating uses +1 * 0b01..Derating uses +2 * 0b10..Derating uses +3 * 0b11..Derating uses +4 */ #define DDRC_DERATEEN_rc_derate_value(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_rc_derate_value_SHIFT)) & DDRC_DERATEEN_rc_derate_value_MASK) /*! @} */ /*! @name DERATEINT - Temperature Derate Interval Register */ /*! @{ */ #define DDRC_DERATEINT_mr4_read_interval_MASK (0xFFFFFFFFU) #define DDRC_DERATEINT_mr4_read_interval_SHIFT (0U) #define DDRC_DERATEINT_mr4_read_interval(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_mr4_read_interval_SHIFT)) & DDRC_DERATEINT_mr4_read_interval_MASK) /*! @} */ /*! @name PWRCTL - Low Power Control Register */ /*! @{ */ #define DDRC_PWRCTL_selfref_en_MASK (0x1U) #define DDRC_PWRCTL_selfref_en_SHIFT (0U) #define DDRC_PWRCTL_selfref_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_selfref_en_SHIFT)) & DDRC_PWRCTL_selfref_en_MASK) #define DDRC_PWRCTL_powerdown_en_MASK (0x2U) #define DDRC_PWRCTL_powerdown_en_SHIFT (1U) #define DDRC_PWRCTL_powerdown_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_powerdown_en_SHIFT)) & DDRC_PWRCTL_powerdown_en_MASK) #define DDRC_PWRCTL_deeppowerdown_en_MASK (0x4U) #define DDRC_PWRCTL_deeppowerdown_en_SHIFT (2U) #define DDRC_PWRCTL_deeppowerdown_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_deeppowerdown_en_SHIFT)) & DDRC_PWRCTL_deeppowerdown_en_MASK) #define DDRC_PWRCTL_en_dfi_dram_clk_disable_MASK (0x8U) #define DDRC_PWRCTL_en_dfi_dram_clk_disable_SHIFT (3U) #define DDRC_PWRCTL_en_dfi_dram_clk_disable(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_en_dfi_dram_clk_disable_SHIFT)) & \ DDRC_PWRCTL_en_dfi_dram_clk_disable_MASK) #define DDRC_PWRCTL_mpsm_en_MASK (0x10U) #define DDRC_PWRCTL_mpsm_en_SHIFT (4U) #define DDRC_PWRCTL_mpsm_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_mpsm_en_SHIFT)) & DDRC_PWRCTL_mpsm_en_MASK) #define DDRC_PWRCTL_selfref_sw_MASK (0x20U) #define DDRC_PWRCTL_selfref_sw_SHIFT (5U) /*! selfref_sw - A value of 1 to this register causes system to move to Self Refresh state * immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software * Entry/Exit to Self Refresh. * 0b0..Software Exit from Self Refresh * 0b1..Software Entry to Self Refresh */ #define DDRC_PWRCTL_selfref_sw(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_selfref_sw_SHIFT)) & DDRC_PWRCTL_selfref_sw_MASK) #define DDRC_PWRCTL_stay_in_selfref_MASK (0x40U) #define DDRC_PWRCTL_stay_in_selfref_SHIFT (6U) /*! stay_in_selfref - Self refresh state is an intermediate state to enter to Self refresh power * down state or exit Self refresh power down state for LPDDR4. This register controls transition * from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 0 - Allow * transition from Self refresh state * 0b0.. * 0b1.. */ #define DDRC_PWRCTL_stay_in_selfref(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_stay_in_selfref_SHIFT)) & DDRC_PWRCTL_stay_in_selfref_MASK) /*! @} */ /*! @name PWRTMG - Low Power Timing Register */ /*! @{ */ #define DDRC_PWRTMG_powerdown_to_x32_MASK (0x1FU) #define DDRC_PWRTMG_powerdown_to_x32_SHIFT (0U) #define DDRC_PWRTMG_powerdown_to_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_powerdown_to_x32_SHIFT)) & DDRC_PWRTMG_powerdown_to_x32_MASK) #define DDRC_PWRTMG_t_dpd_x4096_MASK (0xFF00U) #define DDRC_PWRTMG_t_dpd_x4096_SHIFT (8U) #define DDRC_PWRTMG_t_dpd_x4096(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_t_dpd_x4096_SHIFT)) & DDRC_PWRTMG_t_dpd_x4096_MASK) #define DDRC_PWRTMG_selfref_to_x32_MASK (0xFF0000U) #define DDRC_PWRTMG_selfref_to_x32_SHIFT (16U) #define DDRC_PWRTMG_selfref_to_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_selfref_to_x32_SHIFT)) & DDRC_PWRTMG_selfref_to_x32_MASK) /*! @} */ /*! @name HWLPCTL - Hardware Low Power Control Register */ /*! @{ */ #define DDRC_HWLPCTL_hw_lp_en_MASK (0x1U) #define DDRC_HWLPCTL_hw_lp_en_SHIFT (0U) #define DDRC_HWLPCTL_hw_lp_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_en_SHIFT)) & DDRC_HWLPCTL_hw_lp_en_MASK) #define DDRC_HWLPCTL_hw_lp_exit_idle_en_MASK (0x2U) #define DDRC_HWLPCTL_hw_lp_exit_idle_en_SHIFT (1U) #define DDRC_HWLPCTL_hw_lp_exit_idle_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_exit_idle_en_SHIFT)) & DDRC_HWLPCTL_hw_lp_exit_idle_en_MASK) #define DDRC_HWLPCTL_hw_lp_idle_x32_MASK (0xFFF0000U) #define DDRC_HWLPCTL_hw_lp_idle_x32_SHIFT (16U) #define DDRC_HWLPCTL_hw_lp_idle_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_idle_x32_SHIFT)) & DDRC_HWLPCTL_hw_lp_idle_x32_MASK) /*! @} */ /*! @name RFSHCTL0 - Refresh Control Register 0 */ /*! @{ */ #define DDRC_RFSHCTL0_per_bank_refresh_MASK (0x4U) #define DDRC_RFSHCTL0_per_bank_refresh_SHIFT (2U) /*! per_bank_refresh - Per bank refresh allows traffic to flow to other banks. Per bank refresh is * not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. * Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 * 0b1..Per bank refresh * 0b0..All bank refresh */ #define DDRC_RFSHCTL0_per_bank_refresh(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_per_bank_refresh_SHIFT)) & DDRC_RFSHCTL0_per_bank_refresh_MASK) #define DDRC_RFSHCTL0_refresh_burst_MASK (0x1F0U) #define DDRC_RFSHCTL0_refresh_burst_SHIFT (4U) #define DDRC_RFSHCTL0_refresh_burst(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_burst_SHIFT)) & DDRC_RFSHCTL0_refresh_burst_MASK) #define DDRC_RFSHCTL0_refresh_to_x32_MASK (0x1F000U) #define DDRC_RFSHCTL0_refresh_to_x32_SHIFT (12U) #define DDRC_RFSHCTL0_refresh_to_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_to_x32_SHIFT)) & DDRC_RFSHCTL0_refresh_to_x32_MASK) #define DDRC_RFSHCTL0_refresh_margin_MASK (0xF00000U) #define DDRC_RFSHCTL0_refresh_margin_SHIFT (20U) #define DDRC_RFSHCTL0_refresh_margin(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_margin_SHIFT)) & DDRC_RFSHCTL0_refresh_margin_MASK) /*! @} */ /*! @name RFSHCTL1 - Refresh Control Register 1 */ /*! @{ */ #define DDRC_RFSHCTL1_refresh_timer0_start_value_x32_MASK (0xFFFU) #define DDRC_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT (0U) #define DDRC_RFSHCTL1_refresh_timer0_start_value_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT)) & \ DDRC_RFSHCTL1_refresh_timer0_start_value_x32_MASK) #define DDRC_RFSHCTL1_refresh_timer1_start_value_x32_MASK (0xFFF0000U) #define DDRC_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT (16U) #define DDRC_RFSHCTL1_refresh_timer1_start_value_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT)) & \ DDRC_RFSHCTL1_refresh_timer1_start_value_x32_MASK) /*! @} */ /*! @name RFSHCTL3 - Refresh Control Register 3 */ /*! @{ */ #define DDRC_RFSHCTL3_dis_auto_refresh_MASK (0x1U) #define DDRC_RFSHCTL3_dis_auto_refresh_SHIFT (0U) #define DDRC_RFSHCTL3_dis_auto_refresh(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_dis_auto_refresh_SHIFT)) & DDRC_RFSHCTL3_dis_auto_refresh_MASK) #define DDRC_RFSHCTL3_refresh_update_level_MASK (0x2U) #define DDRC_RFSHCTL3_refresh_update_level_SHIFT (1U) #define DDRC_RFSHCTL3_refresh_update_level(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_refresh_update_level_SHIFT)) & \ DDRC_RFSHCTL3_refresh_update_level_MASK) #define DDRC_RFSHCTL3_refresh_mode_MASK (0x70U) #define DDRC_RFSHCTL3_refresh_mode_SHIFT (4U) #define DDRC_RFSHCTL3_refresh_mode(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_refresh_mode_SHIFT)) & DDRC_RFSHCTL3_refresh_mode_MASK) /*! @} */ /*! @name RFSHTMG - Refresh Timing Register */ /*! @{ */ #define DDRC_RFSHTMG_t_rfc_min_MASK (0x3FFU) #define DDRC_RFSHTMG_t_rfc_min_SHIFT (0U) #define DDRC_RFSHTMG_t_rfc_min(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_t_rfc_min_SHIFT)) & DDRC_RFSHTMG_t_rfc_min_MASK) #define DDRC_RFSHTMG_lpddr3_trefbw_en_MASK (0x8000U) #define DDRC_RFSHTMG_lpddr3_trefbw_en_SHIFT (15U) #define DDRC_RFSHTMG_lpddr3_trefbw_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_lpddr3_trefbw_en_SHIFT)) & DDRC_RFSHTMG_lpddr3_trefbw_en_MASK) #define DDRC_RFSHTMG_t_rfc_nom_x32_MASK (0xFFF0000U) #define DDRC_RFSHTMG_t_rfc_nom_x32_SHIFT (16U) #define DDRC_RFSHTMG_t_rfc_nom_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_t_rfc_nom_x32_SHIFT)) & DDRC_RFSHTMG_t_rfc_nom_x32_MASK) /*! @} */ /*! @name INIT0 - SDRAM Initialization Register 0 */ /*! @{ */ #define DDRC_INIT0_pre_cke_x1024_MASK (0xFFFU) #define DDRC_INIT0_pre_cke_x1024_SHIFT (0U) #define DDRC_INIT0_pre_cke_x1024(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_pre_cke_x1024_SHIFT)) & DDRC_INIT0_pre_cke_x1024_MASK) #define DDRC_INIT0_post_cke_x1024_MASK (0x3FF0000U) #define DDRC_INIT0_post_cke_x1024_SHIFT (16U) #define DDRC_INIT0_post_cke_x1024(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_post_cke_x1024_SHIFT)) & DDRC_INIT0_post_cke_x1024_MASK) #define DDRC_INIT0_skip_dram_init_MASK (0xC0000000U) #define DDRC_INIT0_skip_dram_init_SHIFT (30U) /*! skip_dram_init - If lower bit is enabled the SDRAM initialization routine is skipped. The upper * bit decides what state the controller starts up in when reset is removed - 00 - SDRAM * Intialization routine is run after power-up - 01 - SDRAM Initialization routine is skipped after * power-up. Controller starts up in Normal Mode - 11 - SDRAM Initialization routine is skipped after * power-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Initialization routine is run * after power-up. * 0b00..SDRAM Initialization routine is run after power-up * 0b01..SDRAM Initialization routine is skipped after power-up * 0b10..SDRAM Initialization routine is run after power-up * 0b11..SDRAM Initialization routine is skipped after power-up */ #define DDRC_INIT0_skip_dram_init(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_skip_dram_init_SHIFT)) & DDRC_INIT0_skip_dram_init_MASK) /*! @} */ /*! @name INIT1 - SDRAM Initialization Register 1 */ /*! @{ */ #define DDRC_INIT1_pre_ocd_x32_MASK (0xFU) #define DDRC_INIT1_pre_ocd_x32_SHIFT (0U) #define DDRC_INIT1_pre_ocd_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_pre_ocd_x32_SHIFT)) & DDRC_INIT1_pre_ocd_x32_MASK) #define DDRC_INIT1_dram_rstn_x1024_MASK (0x1FF0000U) #define DDRC_INIT1_dram_rstn_x1024_SHIFT (16U) #define DDRC_INIT1_dram_rstn_x1024(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_dram_rstn_x1024_SHIFT)) & DDRC_INIT1_dram_rstn_x1024_MASK) /*! @} */ /*! @name INIT2 - SDRAM Initialization Register 2 */ /*! @{ */ #define DDRC_INIT2_min_stable_clock_x1_MASK (0xFU) #define DDRC_INIT2_min_stable_clock_x1_SHIFT (0U) #define DDRC_INIT2_min_stable_clock_x1(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_min_stable_clock_x1_SHIFT)) & DDRC_INIT2_min_stable_clock_x1_MASK) #define DDRC_INIT2_idle_after_reset_x32_MASK (0xFF00U) #define DDRC_INIT2_idle_after_reset_x32_SHIFT (8U) #define DDRC_INIT2_idle_after_reset_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_idle_after_reset_x32_SHIFT)) & DDRC_INIT2_idle_after_reset_x32_MASK) /*! @} */ /*! @name INIT3 - SDRAM Initialization Register 3 */ /*! @{ */ #define DDRC_INIT3_emr_MASK (0xFFFFU) #define DDRC_INIT3_emr_SHIFT (0U) #define DDRC_INIT3_emr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_emr_SHIFT)) & DDRC_INIT3_emr_MASK) #define DDRC_INIT3_mr_MASK (0xFFFF0000U) #define DDRC_INIT3_mr_SHIFT (16U) #define DDRC_INIT3_mr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_mr_SHIFT)) & DDRC_INIT3_mr_MASK) /*! @} */ /*! @name INIT4 - SDRAM Initialization Register 4 */ /*! @{ */ #define DDRC_INIT4_emr3_MASK (0xFFFFU) #define DDRC_INIT4_emr3_SHIFT (0U) #define DDRC_INIT4_emr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_emr3_SHIFT)) & DDRC_INIT4_emr3_MASK) #define DDRC_INIT4_emr2_MASK (0xFFFF0000U) #define DDRC_INIT4_emr2_SHIFT (16U) #define DDRC_INIT4_emr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_emr2_SHIFT)) & DDRC_INIT4_emr2_MASK) /*! @} */ /*! @name INIT5 - SDRAM Initialization Register 5 */ /*! @{ */ #define DDRC_INIT5_max_auto_init_x1024_MASK (0x3FFU) #define DDRC_INIT5_max_auto_init_x1024_SHIFT (0U) #define DDRC_INIT5_max_auto_init_x1024(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_max_auto_init_x1024_SHIFT)) & DDRC_INIT5_max_auto_init_x1024_MASK) #define DDRC_INIT5_dev_zqinit_x32_MASK (0xFF0000U) #define DDRC_INIT5_dev_zqinit_x32_SHIFT (16U) #define DDRC_INIT5_dev_zqinit_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_dev_zqinit_x32_SHIFT)) & DDRC_INIT5_dev_zqinit_x32_MASK) /*! @} */ /*! @name INIT6 - SDRAM Initialization Register 6 */ /*! @{ */ #define DDRC_INIT6_mr5_MASK (0xFFFFU) #define DDRC_INIT6_mr5_SHIFT (0U) #define DDRC_INIT6_mr5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_mr5_SHIFT)) & DDRC_INIT6_mr5_MASK) #define DDRC_INIT6_mr4_MASK (0xFFFF0000U) #define DDRC_INIT6_mr4_SHIFT (16U) #define DDRC_INIT6_mr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_mr4_SHIFT)) & DDRC_INIT6_mr4_MASK) /*! @} */ /*! @name INIT7 - SDRAM Initialization Register 7 */ /*! @{ */ #define DDRC_INIT7_mr6_MASK (0xFFFF0000U) #define DDRC_INIT7_mr6_SHIFT (16U) #define DDRC_INIT7_mr6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_mr6_SHIFT)) & DDRC_INIT7_mr6_MASK) /*! @} */ /*! @name DIMMCTL - DIMM Control Register */ /*! @{ */ #define DDRC_DIMMCTL_dimm_stagger_cs_en_MASK (0x1U) #define DDRC_DIMMCTL_dimm_stagger_cs_en_SHIFT (0U) /*! dimm_stagger_cs_en - Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and * LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. * Even if this bit is set it does not take care of software driven MR commands (via * MRCTRL0/MRCTRL1), where software is responsible to send them to separate ranks as appropriate. * 0b0..Do not stagger accesses * 0b1..For(non-DDR4) Send all commands to even and odd ranks separately;For(DDR4) Send MRS commands to each ranks * separately */ #define DDRC_DIMMCTL_dimm_stagger_cs_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_stagger_cs_en_SHIFT)) & DDRC_DIMMCTL_dimm_stagger_cs_en_MASK) #define DDRC_DIMMCTL_dimm_addr_mirr_en_MASK (0x2U) #define DDRC_DIMMCTL_dimm_addr_mirr_en_SHIFT (1U) /*! dimm_addr_mirr_en - Address Mirroring Enable (for multi-rank UDIMM implementations and * multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address * mirroring for odd ranks, which means that the following address, bank address and bank group * bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for * the DDR4. Setting this bit ensures that, for mode register accesses during the automatic * initialization routine, these bits are swapped within the DDRC to compensate for this * UDIMM/RDIMM/LRDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 * UDIMM/RDIMM/LRDIMM, they are swapped during the automatic MRS access to enable/disable of a particular * DDR4 feature. Note: This has no effect on the address of any other memory accesses, or of * software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 * SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 * because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1. * 0b0..Do not implement address mirroring * 0b1..For odd ranks, implement address mirroring for MRS commands to during initialization and for any * automatic DDR4 MRS commands (to be used if UDIMM/RDIMM/LRDIMM implements address mirroring) */ #define DDRC_DIMMCTL_dimm_addr_mirr_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_addr_mirr_en_SHIFT)) & DDRC_DIMMCTL_dimm_addr_mirr_en_MASK) #define DDRC_DIMMCTL_dimm_output_inv_en_MASK (0x4U) #define DDRC_DIMMCTL_dimm_output_inv_en_SHIFT (2U) /*! dimm_output_inv_en - Output Inversion Enable (for DDR4 RDIMM/LRDIMM implementations only). DDR4 * RDIMM/LRDIMM implements the Output Inversion feature by default, which means that the * following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, * A17, BA0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the * DDRC during the automatic initialization routine and enabling of a particular DDR4 feature, * separate A-side and B-side mode register accesses are generated. For B-side mode register * accesses, these bits are inverted within the DDRC to compensate for this RDIMM/LRDIMM inversion. It * is recommended to set this bit always, if using DDR4 RDIMMs/LRDIMMs. Note: This has no effect * on the address of any other memory accesses, or of software-driven mode register accesses. * 0b0..Do not implement output inversion for B-side DRAMs. * 0b1..Implement output inversion for B-side DRAMs. */ #define DDRC_DIMMCTL_dimm_output_inv_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_output_inv_en_SHIFT)) & DDRC_DIMMCTL_dimm_output_inv_en_MASK) #define DDRC_DIMMCTL_mrs_a17_en_MASK (0x8U) #define DDRC_DIMMCTL_mrs_a17_en_SHIFT (3U) /*! mrs_a17_en - Enable for A17 bit of MRS command. A17 bit of the mode register address is * specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs * which do not have A17 are attached and the Output Inversion are enabled, this must be set to * 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on * the address of any other memory accesses, or of software-driven mode register accesses. * 0b0..Disabled * 0b1..Enabled */ #define DDRC_DIMMCTL_mrs_a17_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_mrs_a17_en_SHIFT)) & DDRC_DIMMCTL_mrs_a17_en_MASK) #define DDRC_DIMMCTL_mrs_bg1_en_MASK (0x10U) #define DDRC_DIMMCTL_mrs_bg1_en_SHIFT (4U) /*! mrs_bg1_en - Enable for BG1 bit of MRS command. BG1 bit of the mode register address is * specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs * which do not have BG1 are attached and both the CA parity and the Output Inversion are * enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: * This has no effect on the address of any other memory accesses, or of software-driven mode * register accesses. If address mirroring is enabled, this is applied to BG1 of even ranks and BG0 * of odd ranks. * 0b0..Disabled * 0b1..Enabled */ #define DDRC_DIMMCTL_mrs_bg1_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_mrs_bg1_en_SHIFT)) & DDRC_DIMMCTL_mrs_bg1_en_MASK) #define DDRC_DIMMCTL_dimm_dis_bg_mirroring_MASK (0x20U) #define DDRC_DIMMCTL_dimm_dis_bg_mirroring_SHIFT (5U) /*! dimm_dis_bg_mirroring - Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and * BG1 are NOT swapped even if Address Mirroring is enabled. This will be required for DDR4 DIMMs * with x16 devices. * 0b0..BG0 and BG1 are swapped if address mirroring is enabled. * 0b1..BG0 and BG1 are NOT swapped. */ #define DDRC_DIMMCTL_dimm_dis_bg_mirroring(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_dis_bg_mirroring_SHIFT)) & \ DDRC_DIMMCTL_dimm_dis_bg_mirroring_MASK) #define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_MASK (0x40U) #define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT (6U) #define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT)) & DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_MASK) /*! @} */ /*! @name RANKCTL - Rank Control Register */ /*! @{ */ #define DDRC_RANKCTL_max_rank_rd_MASK (0xFU) #define DDRC_RANKCTL_max_rank_rd_SHIFT (0U) #define DDRC_RANKCTL_max_rank_rd(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_max_rank_rd_SHIFT)) & DDRC_RANKCTL_max_rank_rd_MASK) #define DDRC_RANKCTL_diff_rank_rd_gap_MASK (0xF0U) #define DDRC_RANKCTL_diff_rank_rd_gap_SHIFT (4U) #define DDRC_RANKCTL_diff_rank_rd_gap(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_diff_rank_rd_gap_SHIFT)) & DDRC_RANKCTL_diff_rank_rd_gap_MASK) #define DDRC_RANKCTL_diff_rank_wr_gap_MASK (0xF00U) #define DDRC_RANKCTL_diff_rank_wr_gap_SHIFT (8U) #define DDRC_RANKCTL_diff_rank_wr_gap(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_diff_rank_wr_gap_SHIFT)) & DDRC_RANKCTL_diff_rank_wr_gap_MASK) /*! @} */ /*! @name DRAMTMG0 - SDRAM Timing Register 0 */ /*! @{ */ #define DDRC_DRAMTMG0_t_ras_min_MASK (0x3FU) #define DDRC_DRAMTMG0_t_ras_min_SHIFT (0U) #define DDRC_DRAMTMG0_t_ras_min(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_ras_min_SHIFT)) & DDRC_DRAMTMG0_t_ras_min_MASK) #define DDRC_DRAMTMG0_t_ras_max_MASK (0x7F00U) #define DDRC_DRAMTMG0_t_ras_max_SHIFT (8U) #define DDRC_DRAMTMG0_t_ras_max(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_ras_max_SHIFT)) & DDRC_DRAMTMG0_t_ras_max_MASK) #define DDRC_DRAMTMG0_t_faw_MASK (0x3F0000U) #define DDRC_DRAMTMG0_t_faw_SHIFT (16U) #define DDRC_DRAMTMG0_t_faw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_faw_SHIFT)) & DDRC_DRAMTMG0_t_faw_MASK) #define DDRC_DRAMTMG0_wr2pre_MASK (0x7F000000U) #define DDRC_DRAMTMG0_wr2pre_SHIFT (24U) #define DDRC_DRAMTMG0_wr2pre(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_wr2pre_SHIFT)) & DDRC_DRAMTMG0_wr2pre_MASK) /*! @} */ /*! @name DRAMTMG1 - SDRAM Timing Register 1 */ /*! @{ */ #define DDRC_DRAMTMG1_t_rc_MASK (0x7FU) #define DDRC_DRAMTMG1_t_rc_SHIFT (0U) #define DDRC_DRAMTMG1_t_rc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_t_rc_SHIFT)) & DDRC_DRAMTMG1_t_rc_MASK) #define DDRC_DRAMTMG1_rd2pre_MASK (0x3F00U) #define DDRC_DRAMTMG1_rd2pre_SHIFT (8U) #define DDRC_DRAMTMG1_rd2pre(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_rd2pre_SHIFT)) & DDRC_DRAMTMG1_rd2pre_MASK) #define DDRC_DRAMTMG1_t_xp_MASK (0x1F0000U) #define DDRC_DRAMTMG1_t_xp_SHIFT (16U) #define DDRC_DRAMTMG1_t_xp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_t_xp_SHIFT)) & DDRC_DRAMTMG1_t_xp_MASK) /*! @} */ /*! @name DRAMTMG2 - SDRAM Timing Register 2 */ /*! @{ */ #define DDRC_DRAMTMG2_wr2rd_MASK (0x3FU) #define DDRC_DRAMTMG2_wr2rd_SHIFT (0U) #define DDRC_DRAMTMG2_wr2rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_wr2rd_SHIFT)) & DDRC_DRAMTMG2_wr2rd_MASK) #define DDRC_DRAMTMG2_rd2wr_MASK (0x3F00U) #define DDRC_DRAMTMG2_rd2wr_SHIFT (8U) #define DDRC_DRAMTMG2_rd2wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_rd2wr_SHIFT)) & DDRC_DRAMTMG2_rd2wr_MASK) #define DDRC_DRAMTMG2_read_latency_MASK (0x3F0000U) #define DDRC_DRAMTMG2_read_latency_SHIFT (16U) #define DDRC_DRAMTMG2_read_latency(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_read_latency_SHIFT)) & DDRC_DRAMTMG2_read_latency_MASK) #define DDRC_DRAMTMG2_write_latency_MASK (0x3F000000U) #define DDRC_DRAMTMG2_write_latency_SHIFT (24U) #define DDRC_DRAMTMG2_write_latency(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_write_latency_SHIFT)) & DDRC_DRAMTMG2_write_latency_MASK) /*! @} */ /*! @name DRAMTMG3 - SDRAM Timing Register 3 */ /*! @{ */ #define DDRC_DRAMTMG3_t_mod_MASK (0x3FFU) #define DDRC_DRAMTMG3_t_mod_SHIFT (0U) #define DDRC_DRAMTMG3_t_mod(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mod_SHIFT)) & DDRC_DRAMTMG3_t_mod_MASK) #define DDRC_DRAMTMG3_t_mrd_MASK (0x3F000U) #define DDRC_DRAMTMG3_t_mrd_SHIFT (12U) #define DDRC_DRAMTMG3_t_mrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mrd_SHIFT)) & DDRC_DRAMTMG3_t_mrd_MASK) #define DDRC_DRAMTMG3_t_mrw_MASK (0x3FF00000U) #define DDRC_DRAMTMG3_t_mrw_SHIFT (20U) #define DDRC_DRAMTMG3_t_mrw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mrw_SHIFT)) & DDRC_DRAMTMG3_t_mrw_MASK) /*! @} */ /*! @name DRAMTMG4 - SDRAM Timing Register 4 */ /*! @{ */ #define DDRC_DRAMTMG4_t_rp_MASK (0x1FU) #define DDRC_DRAMTMG4_t_rp_SHIFT (0U) #define DDRC_DRAMTMG4_t_rp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rp_SHIFT)) & DDRC_DRAMTMG4_t_rp_MASK) #define DDRC_DRAMTMG4_t_rrd_MASK (0xF00U) #define DDRC_DRAMTMG4_t_rrd_SHIFT (8U) #define DDRC_DRAMTMG4_t_rrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rrd_SHIFT)) & DDRC_DRAMTMG4_t_rrd_MASK) #define DDRC_DRAMTMG4_t_ccd_MASK (0xF0000U) #define DDRC_DRAMTMG4_t_ccd_SHIFT (16U) #define DDRC_DRAMTMG4_t_ccd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_ccd_SHIFT)) & DDRC_DRAMTMG4_t_ccd_MASK) #define DDRC_DRAMTMG4_t_rcd_MASK (0x1F000000U) #define DDRC_DRAMTMG4_t_rcd_SHIFT (24U) #define DDRC_DRAMTMG4_t_rcd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rcd_SHIFT)) & DDRC_DRAMTMG4_t_rcd_MASK) /*! @} */ /*! @name DRAMTMG5 - SDRAM Timing Register 5 */ /*! @{ */ #define DDRC_DRAMTMG5_t_cke_MASK (0x1FU) #define DDRC_DRAMTMG5_t_cke_SHIFT (0U) #define DDRC_DRAMTMG5_t_cke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cke_SHIFT)) & DDRC_DRAMTMG5_t_cke_MASK) #define DDRC_DRAMTMG5_t_ckesr_MASK (0x3F00U) #define DDRC_DRAMTMG5_t_ckesr_SHIFT (8U) #define DDRC_DRAMTMG5_t_ckesr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_ckesr_SHIFT)) & DDRC_DRAMTMG5_t_ckesr_MASK) #define DDRC_DRAMTMG5_t_cksre_MASK (0xF0000U) #define DDRC_DRAMTMG5_t_cksre_SHIFT (16U) #define DDRC_DRAMTMG5_t_cksre(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cksre_SHIFT)) & DDRC_DRAMTMG5_t_cksre_MASK) #define DDRC_DRAMTMG5_t_cksrx_MASK (0xF000000U) #define DDRC_DRAMTMG5_t_cksrx_SHIFT (24U) #define DDRC_DRAMTMG5_t_cksrx(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cksrx_SHIFT)) & DDRC_DRAMTMG5_t_cksrx_MASK) /*! @} */ /*! @name DRAMTMG6 - SDRAM Timing Register 6 */ /*! @{ */ #define DDRC_DRAMTMG6_t_ckcsx_MASK (0xFU) #define DDRC_DRAMTMG6_t_ckcsx_SHIFT (0U) #define DDRC_DRAMTMG6_t_ckcsx(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckcsx_SHIFT)) & DDRC_DRAMTMG6_t_ckcsx_MASK) #define DDRC_DRAMTMG6_t_ckdpdx_MASK (0xF0000U) #define DDRC_DRAMTMG6_t_ckdpdx_SHIFT (16U) #define DDRC_DRAMTMG6_t_ckdpdx(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckdpdx_SHIFT)) & DDRC_DRAMTMG6_t_ckdpdx_MASK) #define DDRC_DRAMTMG6_t_ckdpde_MASK (0xF000000U) #define DDRC_DRAMTMG6_t_ckdpde_SHIFT (24U) #define DDRC_DRAMTMG6_t_ckdpde(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckdpde_SHIFT)) & DDRC_DRAMTMG6_t_ckdpde_MASK) /*! @} */ /*! @name DRAMTMG7 - SDRAM Timing Register 7 */ /*! @{ */ #define DDRC_DRAMTMG7_t_ckpdx_MASK (0xFU) #define DDRC_DRAMTMG7_t_ckpdx_SHIFT (0U) #define DDRC_DRAMTMG7_t_ckpdx(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_t_ckpdx_SHIFT)) & DDRC_DRAMTMG7_t_ckpdx_MASK) #define DDRC_DRAMTMG7_t_ckpde_MASK (0xF00U) #define DDRC_DRAMTMG7_t_ckpde_SHIFT (8U) #define DDRC_DRAMTMG7_t_ckpde(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_t_ckpde_SHIFT)) & DDRC_DRAMTMG7_t_ckpde_MASK) /*! @} */ /*! @name DRAMTMG8 - SDRAM Timing Register 8 */ /*! @{ */ #define DDRC_DRAMTMG8_t_xs_x32_MASK (0x7FU) #define DDRC_DRAMTMG8_t_xs_x32_SHIFT (0U) #define DDRC_DRAMTMG8_t_xs_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_x32_MASK) #define DDRC_DRAMTMG8_t_xs_dll_x32_MASK (0x7F00U) #define DDRC_DRAMTMG8_t_xs_dll_x32_SHIFT (8U) #define DDRC_DRAMTMG8_t_xs_dll_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_dll_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_dll_x32_MASK) #define DDRC_DRAMTMG8_t_xs_abort_x32_MASK (0x7F0000U) #define DDRC_DRAMTMG8_t_xs_abort_x32_SHIFT (16U) #define DDRC_DRAMTMG8_t_xs_abort_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_abort_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_abort_x32_MASK) #define DDRC_DRAMTMG8_t_xs_fast_x32_MASK (0x7F000000U) #define DDRC_DRAMTMG8_t_xs_fast_x32_SHIFT (24U) #define DDRC_DRAMTMG8_t_xs_fast_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_fast_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_fast_x32_MASK) /*! @} */ /*! @name DRAMTMG9 - SDRAM Timing Register 9 */ /*! @{ */ #define DDRC_DRAMTMG9_wr2rd_s_MASK (0x3FU) #define DDRC_DRAMTMG9_wr2rd_s_SHIFT (0U) #define DDRC_DRAMTMG9_wr2rd_s(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_wr2rd_s_SHIFT)) & DDRC_DRAMTMG9_wr2rd_s_MASK) #define DDRC_DRAMTMG9_t_rrd_s_MASK (0xF00U) #define DDRC_DRAMTMG9_t_rrd_s_SHIFT (8U) #define DDRC_DRAMTMG9_t_rrd_s(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_t_rrd_s_SHIFT)) & DDRC_DRAMTMG9_t_rrd_s_MASK) #define DDRC_DRAMTMG9_t_ccd_s_MASK (0x70000U) #define DDRC_DRAMTMG9_t_ccd_s_SHIFT (16U) #define DDRC_DRAMTMG9_t_ccd_s(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_t_ccd_s_SHIFT)) & DDRC_DRAMTMG9_t_ccd_s_MASK) #define DDRC_DRAMTMG9_ddr4_wr_preamble_MASK (0x40000000U) #define DDRC_DRAMTMG9_ddr4_wr_preamble_SHIFT (30U) #define DDRC_DRAMTMG9_ddr4_wr_preamble(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_ddr4_wr_preamble_SHIFT)) & DDRC_DRAMTMG9_ddr4_wr_preamble_MASK) /*! @} */ /*! @name DRAMTMG10 - SDRAM Timing Register 10 */ /*! @{ */ #define DDRC_DRAMTMG10_t_gear_hold_MASK (0x3U) #define DDRC_DRAMTMG10_t_gear_hold_SHIFT (0U) #define DDRC_DRAMTMG10_t_gear_hold(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_gear_hold_SHIFT)) & DDRC_DRAMTMG10_t_gear_hold_MASK) #define DDRC_DRAMTMG10_t_gear_setup_MASK (0xCU) #define DDRC_DRAMTMG10_t_gear_setup_SHIFT (2U) #define DDRC_DRAMTMG10_t_gear_setup(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_gear_setup_SHIFT)) & DDRC_DRAMTMG10_t_gear_setup_MASK) #define DDRC_DRAMTMG10_t_cmd_gear_MASK (0x1F00U) #define DDRC_DRAMTMG10_t_cmd_gear_SHIFT (8U) #define DDRC_DRAMTMG10_t_cmd_gear(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_cmd_gear_SHIFT)) & DDRC_DRAMTMG10_t_cmd_gear_MASK) #define DDRC_DRAMTMG10_t_sync_gear_MASK (0x1F0000U) #define DDRC_DRAMTMG10_t_sync_gear_SHIFT (16U) #define DDRC_DRAMTMG10_t_sync_gear(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_sync_gear_SHIFT)) & DDRC_DRAMTMG10_t_sync_gear_MASK) /*! @} */ /*! @name DRAMTMG11 - SDRAM Timing Register 11 */ /*! @{ */ #define DDRC_DRAMTMG11_t_ckmpe_MASK (0x1FU) #define DDRC_DRAMTMG11_t_ckmpe_SHIFT (0U) #define DDRC_DRAMTMG11_t_ckmpe(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_ckmpe_SHIFT)) & DDRC_DRAMTMG11_t_ckmpe_MASK) #define DDRC_DRAMTMG11_t_mpx_s_MASK (0x300U) #define DDRC_DRAMTMG11_t_mpx_s_SHIFT (8U) #define DDRC_DRAMTMG11_t_mpx_s(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_mpx_s_SHIFT)) & DDRC_DRAMTMG11_t_mpx_s_MASK) #define DDRC_DRAMTMG11_t_mpx_lh_MASK (0x1F0000U) #define DDRC_DRAMTMG11_t_mpx_lh_SHIFT (16U) #define DDRC_DRAMTMG11_t_mpx_lh(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_mpx_lh_SHIFT)) & DDRC_DRAMTMG11_t_mpx_lh_MASK) #define DDRC_DRAMTMG11_post_mpsm_gap_x32_MASK (0x7F000000U) #define DDRC_DRAMTMG11_post_mpsm_gap_x32_SHIFT (24U) #define DDRC_DRAMTMG11_post_mpsm_gap_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_post_mpsm_gap_x32_SHIFT)) & DDRC_DRAMTMG11_post_mpsm_gap_x32_MASK) /*! @} */ /*! @name DRAMTMG12 - SDRAM Timing Register 12 */ /*! @{ */ #define DDRC_DRAMTMG12_t_mrd_pda_MASK (0x1FU) #define DDRC_DRAMTMG12_t_mrd_pda_SHIFT (0U) #define DDRC_DRAMTMG12_t_mrd_pda(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_mrd_pda_SHIFT)) & DDRC_DRAMTMG12_t_mrd_pda_MASK) #define DDRC_DRAMTMG12_t_ckehcmd_MASK (0xF00U) #define DDRC_DRAMTMG12_t_ckehcmd_SHIFT (8U) #define DDRC_DRAMTMG12_t_ckehcmd(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_ckehcmd_SHIFT)) & DDRC_DRAMTMG12_t_ckehcmd_MASK) #define DDRC_DRAMTMG12_t_cmdcke_MASK (0x30000U) #define DDRC_DRAMTMG12_t_cmdcke_SHIFT (16U) #define DDRC_DRAMTMG12_t_cmdcke(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_cmdcke_SHIFT)) & DDRC_DRAMTMG12_t_cmdcke_MASK) /*! @} */ /*! @name DRAMTMG13 - SDRAM Timing Register 13 */ /*! @{ */ #define DDRC_DRAMTMG13_t_ppd_MASK (0x7U) #define DDRC_DRAMTMG13_t_ppd_SHIFT (0U) #define DDRC_DRAMTMG13_t_ppd(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_t_ppd_SHIFT)) & DDRC_DRAMTMG13_t_ppd_MASK) #define DDRC_DRAMTMG13_t_ccd_mw_MASK (0x3F0000U) #define DDRC_DRAMTMG13_t_ccd_mw_SHIFT (16U) #define DDRC_DRAMTMG13_t_ccd_mw(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_t_ccd_mw_SHIFT)) & DDRC_DRAMTMG13_t_ccd_mw_MASK) #define DDRC_DRAMTMG13_odtloff_MASK (0x7F000000U) #define DDRC_DRAMTMG13_odtloff_SHIFT (24U) #define DDRC_DRAMTMG13_odtloff(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_odtloff_SHIFT)) & DDRC_DRAMTMG13_odtloff_MASK) /*! @} */ /*! @name DRAMTMG14 - SDRAM Timing Register 14 */ /*! @{ */ #define DDRC_DRAMTMG14_t_xsr_MASK (0xFFFU) #define DDRC_DRAMTMG14_t_xsr_SHIFT (0U) #define DDRC_DRAMTMG14_t_xsr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_t_xsr_SHIFT)) & DDRC_DRAMTMG14_t_xsr_MASK) /*! @} */ /*! @name DRAMTMG15 - SDRAM Timing Register 15 */ /*! @{ */ #define DDRC_DRAMTMG15_t_stab_x32_MASK (0xFFU) #define DDRC_DRAMTMG15_t_stab_x32_SHIFT (0U) #define DDRC_DRAMTMG15_t_stab_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_t_stab_x32_SHIFT)) & DDRC_DRAMTMG15_t_stab_x32_MASK) #define DDRC_DRAMTMG15_en_dfi_lp_t_stab_MASK (0x80000000U) #define DDRC_DRAMTMG15_en_dfi_lp_t_stab_SHIFT (31U) /*! en_dfi_lp_t_stab - Enable DFI tSTAB * 0b0..Disable using tSTAB when exiting DFI LP * 0b1..Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to * save maximum power. */ #define DDRC_DRAMTMG15_en_dfi_lp_t_stab(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_en_dfi_lp_t_stab_SHIFT)) & DDRC_DRAMTMG15_en_dfi_lp_t_stab_MASK) /*! @} */ /*! @name ZQCTL0 - ZQ Control Register 0 */ /*! @{ */ #define DDRC_ZQCTL0_t_zq_short_nop_MASK (0x3FFU) #define DDRC_ZQCTL0_t_zq_short_nop_SHIFT (0U) #define DDRC_ZQCTL0_t_zq_short_nop(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_t_zq_short_nop_SHIFT)) & DDRC_ZQCTL0_t_zq_short_nop_MASK) #define DDRC_ZQCTL0_t_zq_long_nop_MASK (0x7FF0000U) #define DDRC_ZQCTL0_t_zq_long_nop_SHIFT (16U) #define DDRC_ZQCTL0_t_zq_long_nop(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_t_zq_long_nop_SHIFT)) & DDRC_ZQCTL0_t_zq_long_nop_MASK) #define DDRC_ZQCTL0_dis_mpsmx_zqcl_MASK (0x10000000U) #define DDRC_ZQCTL0_dis_mpsmx_zqcl_SHIFT (28U) /*! dis_mpsmx_zqcl - Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC * configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting * MPSM mode. * 0b0..Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. * This is only present for designs supporting DDR4 devices. * 0b1..Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. */ #define DDRC_ZQCTL0_dis_mpsmx_zqcl(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_mpsmx_zqcl_SHIFT)) & DDRC_ZQCTL0_dis_mpsmx_zqcl_MASK) #define DDRC_ZQCTL0_zq_resistor_shared_MASK (0x20000000U) #define DDRC_ZQCTL0_zq_resistor_shared_SHIFT (29U) /*! zq_resistor_shared - ZQ resistor sharing * 0b0..ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 * devices. 0b1..Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands * are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to * different ranks do not overlap. */ #define DDRC_ZQCTL0_zq_resistor_shared(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_zq_resistor_shared_SHIFT)) & DDRC_ZQCTL0_zq_resistor_shared_MASK) #define DDRC_ZQCTL0_dis_srx_zqcl_MASK (0x40000000U) #define DDRC_ZQCTL0_dis_srx_zqcl_SHIFT (30U) /*! dis_srx_zqcl - Disable ZQCL/MPC * 0b0..Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable * when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting * DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. * 0b1..Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable * when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ #define DDRC_ZQCTL0_dis_srx_zqcl(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_srx_zqcl_SHIFT)) & DDRC_ZQCTL0_dis_srx_zqcl_MASK) #define DDRC_ZQCTL0_dis_auto_zq_MASK (0x80000000U) #define DDRC_ZQCTL0_dis_auto_zq_SHIFT (31U) /*! dis_auto_zq - Disable Auto ZQCS/MPC * 0b0..Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024. * 0b1..Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used * instead to issue ZQ calibration request from APB module. */ #define DDRC_ZQCTL0_dis_auto_zq(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_auto_zq_SHIFT)) & DDRC_ZQCTL0_dis_auto_zq_MASK) /*! @} */ /*! @name ZQCTL1 - ZQ Control Register 1 */ /*! @{ */ #define DDRC_ZQCTL1_t_zq_short_interval_x1024_MASK (0xFFFFFU) #define DDRC_ZQCTL1_t_zq_short_interval_x1024_SHIFT (0U) #define DDRC_ZQCTL1_t_zq_short_interval_x1024(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_t_zq_short_interval_x1024_SHIFT)) & \ DDRC_ZQCTL1_t_zq_short_interval_x1024_MASK) #define DDRC_ZQCTL1_t_zq_reset_nop_MASK (0x3FF00000U) #define DDRC_ZQCTL1_t_zq_reset_nop_SHIFT (20U) #define DDRC_ZQCTL1_t_zq_reset_nop(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_t_zq_reset_nop_SHIFT)) & DDRC_ZQCTL1_t_zq_reset_nop_MASK) /*! @} */ /*! @name ZQCTL2 - ZQ Control Register 2 */ /*! @{ */ #define DDRC_ZQCTL2_zq_reset_MASK (0x1U) #define DDRC_ZQCTL2_zq_reset_SHIFT (0U) #define DDRC_ZQCTL2_zq_reset(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL2_zq_reset_SHIFT)) & DDRC_ZQCTL2_zq_reset_MASK) /*! @} */ /*! @name ZQSTAT - ZQ Status Register */ /*! @{ */ #define DDRC_ZQSTAT_zq_reset_busy_MASK (0x1U) #define DDRC_ZQSTAT_zq_reset_busy_SHIFT (0U) /*! zq_reset_busy - SoC core may initiate a ZQ Reset operation only if this signal is low. This * signal goes high in the clock after the DDRC accepts the ZQ Reset request. It goes low when the ZQ * Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended * not to perform ZQ Reset commands when this signal is high. * 0b0..Indicates that the SoC core can initiate a ZQ Reset operation * 0b1..Indicates that ZQ Reset operation is in progress */ #define DDRC_ZQSTAT_zq_reset_busy(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ZQSTAT_zq_reset_busy_SHIFT)) & DDRC_ZQSTAT_zq_reset_busy_MASK) /*! @} */ /*! @name DFITMG0 - DFI Timing Register 0 */ /*! @{ */ #define DDRC_DFITMG0_dfi_tphy_wrlat_MASK (0x3FU) #define DDRC_DFITMG0_dfi_tphy_wrlat_SHIFT (0U) #define DDRC_DFITMG0_dfi_tphy_wrlat(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_tphy_wrlat_SHIFT)) & DDRC_DFITMG0_dfi_tphy_wrlat_MASK) #define DDRC_DFITMG0_dfi_tphy_wrdata_MASK (0x3F00U) #define DDRC_DFITMG0_dfi_tphy_wrdata_SHIFT (8U) #define DDRC_DFITMG0_dfi_tphy_wrdata(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_tphy_wrdata_SHIFT)) & DDRC_DFITMG0_dfi_tphy_wrdata_MASK) #define DDRC_DFITMG0_dfi_wrdata_use_sdr_MASK (0x8000U) #define DDRC_DFITMG0_dfi_wrdata_use_sdr_SHIFT (15U) #define DDRC_DFITMG0_dfi_wrdata_use_sdr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_wrdata_use_sdr_SHIFT)) & DDRC_DFITMG0_dfi_wrdata_use_sdr_MASK) #define DDRC_DFITMG0_dfi_t_rddata_en_MASK (0x7F0000U) #define DDRC_DFITMG0_dfi_t_rddata_en_SHIFT (16U) #define DDRC_DFITMG0_dfi_t_rddata_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_t_rddata_en_SHIFT)) & DDRC_DFITMG0_dfi_t_rddata_en_MASK) #define DDRC_DFITMG0_dfi_rddata_use_sdr_MASK (0x800000U) #define DDRC_DFITMG0_dfi_rddata_use_sdr_SHIFT (23U) #define DDRC_DFITMG0_dfi_rddata_use_sdr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_rddata_use_sdr_SHIFT)) & DDRC_DFITMG0_dfi_rddata_use_sdr_MASK) #define DDRC_DFITMG0_dfi_t_ctrl_delay_MASK (0x1F000000U) #define DDRC_DFITMG0_dfi_t_ctrl_delay_SHIFT (24U) #define DDRC_DFITMG0_dfi_t_ctrl_delay(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_t_ctrl_delay_SHIFT)) & DDRC_DFITMG0_dfi_t_ctrl_delay_MASK) /*! @} */ /*! @name DFITMG1 - DFI Timing Register 1 */ /*! @{ */ #define DDRC_DFITMG1_dfi_t_dram_clk_enable_MASK (0x1FU) #define DDRC_DFITMG1_dfi_t_dram_clk_enable_SHIFT (0U) #define DDRC_DFITMG1_dfi_t_dram_clk_enable(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_dram_clk_enable_SHIFT)) & \ DDRC_DFITMG1_dfi_t_dram_clk_enable_MASK) #define DDRC_DFITMG1_dfi_t_dram_clk_disable_MASK (0x1F00U) #define DDRC_DFITMG1_dfi_t_dram_clk_disable_SHIFT (8U) #define DDRC_DFITMG1_dfi_t_dram_clk_disable(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_dram_clk_disable_SHIFT)) & \ DDRC_DFITMG1_dfi_t_dram_clk_disable_MASK) #define DDRC_DFITMG1_dfi_t_wrdata_delay_MASK (0x1F0000U) #define DDRC_DFITMG1_dfi_t_wrdata_delay_SHIFT (16U) #define DDRC_DFITMG1_dfi_t_wrdata_delay(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_wrdata_delay_SHIFT)) & DDRC_DFITMG1_dfi_t_wrdata_delay_MASK) #define DDRC_DFITMG1_dfi_t_parin_lat_MASK (0x3000000U) #define DDRC_DFITMG1_dfi_t_parin_lat_SHIFT (24U) #define DDRC_DFITMG1_dfi_t_parin_lat(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_parin_lat_SHIFT)) & DDRC_DFITMG1_dfi_t_parin_lat_MASK) #define DDRC_DFITMG1_dfi_t_cmd_lat_MASK (0xF0000000U) #define DDRC_DFITMG1_dfi_t_cmd_lat_SHIFT (28U) #define DDRC_DFITMG1_dfi_t_cmd_lat(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_cmd_lat_SHIFT)) & DDRC_DFITMG1_dfi_t_cmd_lat_MASK) /*! @} */ /*! @name DFILPCFG0 - DFI Low Power Configuration Register 0 */ /*! @{ */ #define DDRC_DFILPCFG0_dfi_lp_en_pd_MASK (0x1U) #define DDRC_DFILPCFG0_dfi_lp_en_pd_SHIFT (0U) #define DDRC_DFILPCFG0_dfi_lp_en_pd(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_pd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_pd_MASK) #define DDRC_DFILPCFG0_dfi_lp_wakeup_pd_MASK (0xF0U) #define DDRC_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT (4U) /*! dfi_lp_wakeup_pd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down * mode is entered. Determines the DFI's tlp_wakeup time: * 0b0000..16 cycles * 0b0001..32 cycles * 0b0010..64 cycles * 0b0011..128 cycles * 0b0100..256 cycles * 0b0101..512 cycles * 0b0110..1024 cycles * 0b0111..2048 cycles * 0b1000..4096 cycles * 0b1001..8192 cycles * 0b1010..16384 cycles * 0b1011..32768 cycles * 0b1100..65536 cycles * 0b1101..131072 cycles * 0b1110..262144 cycles * 0b1111..Unlimited cycles */ #define DDRC_DFILPCFG0_dfi_lp_wakeup_pd(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_pd_MASK) #define DDRC_DFILPCFG0_dfi_lp_en_sr_MASK (0x100U) #define DDRC_DFILPCFG0_dfi_lp_en_sr_SHIFT (8U) /*! dfi_lp_en_sr - Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - * Enabled 0b0..Disabled 0b1..Enabled */ #define DDRC_DFILPCFG0_dfi_lp_en_sr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_sr_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_sr_MASK) #define DDRC_DFILPCFG0_dfi_lp_wakeup_sr_MASK (0xF000U) #define DDRC_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT (12U) /*! dfi_lp_wakeup_sr - Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh * mode is entered. Determines the DFI's tlp_wakeup time: * 0b0000..16 cycles * 0b0001..32 cycles * 0b0010..64 cycles * 0b0011..128 cycles * 0b0100..256 cycles * 0b0101..512 cycles * 0b0110..1024 cycles * 0b0111..2048 cycles * 0b1000..4096 cycles * 0b1001..8192 cycles * 0b1010..16384 cycles * 0b1011..32768 cycles * 0b1100..65536 cycles * 0b1101..131072 cycles * 0b1110..262144 cycles * 0b1111..Unlimited cycles */ #define DDRC_DFILPCFG0_dfi_lp_wakeup_sr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_sr_MASK) #define DDRC_DFILPCFG0_dfi_lp_en_dpd_MASK (0x10000U) #define DDRC_DFILPCFG0_dfi_lp_en_dpd_SHIFT (16U) #define DDRC_DFILPCFG0_dfi_lp_en_dpd(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_dpd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_dpd_MASK) #define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_MASK (0xF00000U) #define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT (20U) /*! dfi_lp_wakeup_dpd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power * Down mode is entered. Determines the DFI's tlp_wakeup time: This is only present for designs * supporting mDDR or LPDDR2/LPDDR3 devices. * 0b0000..16 cycles * 0b0001..32 cycles * 0b0010..64 cycles * 0b0011..128 cycles * 0b0100..256 cycles * 0b0101..512 cycles * 0b0110..1024 cycles * 0b0111..2048 cycles * 0b1000..4096 cycles * 0b1001..8192 cycles * 0b1010..16384 cycles * 0b1011..32768 cycles * 0b1100..65536 cycles * 0b1101..131072 cycles * 0b1110..262144 cycles * 0b1111..Unlimited cycles */ #define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_MASK) #define DDRC_DFILPCFG0_dfi_tlp_resp_MASK (0x1F000000U) #define DDRC_DFILPCFG0_dfi_tlp_resp_SHIFT (24U) #define DDRC_DFILPCFG0_dfi_tlp_resp(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_tlp_resp_SHIFT)) & DDRC_DFILPCFG0_dfi_tlp_resp_MASK) /*! @} */ /*! @name DFILPCFG1 - DFI Low Power Configuration Register 1 */ /*! @{ */ #define DDRC_DFILPCFG1_dfi_lp_en_mpsm_MASK (0x1U) #define DDRC_DFILPCFG1_dfi_lp_en_mpsm_SHIFT (0U) #define DDRC_DFILPCFG1_dfi_lp_en_mpsm(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_dfi_lp_en_mpsm_SHIFT)) & DDRC_DFILPCFG1_dfi_lp_en_mpsm_MASK) #define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK (0xF0U) #define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT (4U) /*! dfi_lp_wakeup_mpsm - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum * Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: * 0b0000..16 cycles * 0b0001..32 cycles * 0b0010..64 cycles * 0b0011..128 cycles * 0b0100..256 cycles * 0b0101..512 cycles * 0b0110..1024 cycles * 0b0111..2048 cycles * 0b1000..4096 cycles * 0b1001..8192 cycles * 0b1010..16384 cycles * 0b1011..32768 cycles * 0b1100..65536 cycles * 0b1101..131072 cycles * 0b1110..262144 cycles * 0b1111..Unlimited cycles */ #define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT)) & DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK) /*! @} */ /*! @name DFIUPD0 - DFI Update Register 0 */ /*! @{ */ #define DDRC_DFIUPD0_dfi_t_ctrlup_min_MASK (0x3FFU) #define DDRC_DFIUPD0_dfi_t_ctrlup_min_SHIFT (0U) #define DDRC_DFIUPD0_dfi_t_ctrlup_min(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dfi_t_ctrlup_min_SHIFT)) & DDRC_DFIUPD0_dfi_t_ctrlup_min_MASK) #define DDRC_DFIUPD0_dfi_t_ctrlup_max_MASK (0x3FF0000U) #define DDRC_DFIUPD0_dfi_t_ctrlup_max_SHIFT (16U) #define DDRC_DFIUPD0_dfi_t_ctrlup_max(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dfi_t_ctrlup_max_SHIFT)) & DDRC_DFIUPD0_dfi_t_ctrlup_max_MASK) #define DDRC_DFIUPD0_ctrlupd_pre_srx_MASK (0x20000000U) #define DDRC_DFIUPD0_ctrlupd_pre_srx_SHIFT (29U) /*! ctrlupd_pre_srx - Selects dfi_ctrlupd_req requirements at SRX: - 0 : send ctrlupd after SRX - 1 * : send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact, * because no dfi_ctrlupd_req will be issued when SRX. * 0b0..send ctrlupd after SRX * 0b1..send ctrlupd before SRX */ #define DDRC_DFIUPD0_ctrlupd_pre_srx(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_ctrlupd_pre_srx_SHIFT)) & DDRC_DFIUPD0_ctrlupd_pre_srx_MASK) #define DDRC_DFIUPD0_dis_auto_ctrlupd_srx_MASK (0x40000000U) #define DDRC_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT (30U) /*! dis_auto_ctrlupd_srx - Auto ctrlupd request generation * 0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC at self-refresh exit. * 0b0..DDRC issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on DFIUPD0.ctrlupd_pre_srx. */ #define DDRC_DFIUPD0_dis_auto_ctrlupd_srx(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT)) & DDRC_DFIUPD0_dis_auto_ctrlupd_srx_MASK) #define DDRC_DFIUPD0_dis_auto_ctrlupd_MASK (0x80000000U) #define DDRC_DFIUPD0_dis_auto_ctrlupd_SHIFT (31U) /*! dis_auto_ctrlupd - automatic dfi_ctrlupd_req generation by the DDRC * 0b0..DDRC issues dfi_ctrlupd_req periodically. * 0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC. The core must issue the dfi_ctrlupd_req * signal using register reg_ddrc_ctrlupd. */ #define DDRC_DFIUPD0_dis_auto_ctrlupd(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dis_auto_ctrlupd_SHIFT)) & DDRC_DFIUPD0_dis_auto_ctrlupd_MASK) /*! @} */ /*! @name DFIUPD1 - DFI Update Register 1 */ /*! @{ */ #define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK (0xFFU) #define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT (0U) #define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT)) & \ DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK) #define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK (0xFF0000U) #define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT (16U) #define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT)) & \ DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK) /*! @} */ /*! @name DFIUPD2 - DFI Update Register 2 */ /*! @{ */ #define DDRC_DFIUPD2_dfi_phyupd_en_MASK (0x80000000U) #define DDRC_DFIUPD2_dfi_phyupd_en_SHIFT (31U) /*! dfi_phyupd_en - Enables the support for acknowledging PHY-initiated updates: * 0b0..Disabled * 0b1..Enabled */ #define DDRC_DFIUPD2_dfi_phyupd_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD2_dfi_phyupd_en_SHIFT)) & DDRC_DFIUPD2_dfi_phyupd_en_MASK) /*! @} */ /*! @name DFIMISC - DFI Miscellaneous Control Register */ /*! @{ */ #define DDRC_DFIMISC_dfi_init_complete_en_MASK (0x1U) #define DDRC_DFIMISC_dfi_init_complete_en_SHIFT (0U) #define DDRC_DFIMISC_dfi_init_complete_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_init_complete_en_SHIFT)) & DDRC_DFIMISC_dfi_init_complete_en_MASK) #define DDRC_DFIMISC_phy_dbi_mode_MASK (0x2U) #define DDRC_DFIMISC_phy_dbi_mode_SHIFT (1U) /*! phy_dbi_mode - DBI implemented in DDRC or PHY. Present only in designs configured to support DDR4 and LPDDR4. * 0b0..DDRC implements DBI functionality. * 0b1..PHY implements DBI functionality. */ #define DDRC_DFIMISC_phy_dbi_mode(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_phy_dbi_mode_SHIFT)) & DDRC_DFIMISC_phy_dbi_mode_MASK) #define DDRC_DFIMISC_dfi_data_cs_polarity_MASK (0x4U) #define DDRC_DFIMISC_dfi_data_cs_polarity_SHIFT (2U) /*! dfi_data_cs_polarity - Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. * 0b0..Signals are active low * 0b1..Signals are active high */ #define DDRC_DFIMISC_dfi_data_cs_polarity(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_data_cs_polarity_SHIFT)) & DDRC_DFIMISC_dfi_data_cs_polarity_MASK) #define DDRC_DFIMISC_ctl_idle_en_MASK (0x10U) #define DDRC_DFIMISC_ctl_idle_en_SHIFT (4U) #define DDRC_DFIMISC_ctl_idle_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_ctl_idle_en_SHIFT)) & DDRC_DFIMISC_ctl_idle_en_MASK) #define DDRC_DFIMISC_dfi_init_start_MASK (0x20U) #define DDRC_DFIMISC_dfi_init_start_SHIFT (5U) #define DDRC_DFIMISC_dfi_init_start(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_init_start_SHIFT)) & DDRC_DFIMISC_dfi_init_start_MASK) #define DDRC_DFIMISC_dfi_frequency_MASK (0x1F00U) #define DDRC_DFIMISC_dfi_frequency_SHIFT (8U) #define DDRC_DFIMISC_dfi_frequency(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_frequency_SHIFT)) & DDRC_DFIMISC_dfi_frequency_MASK) /*! @} */ /*! @name DFITMG2 - DFI Timing Register 2 */ /*! @{ */ #define DDRC_DFITMG2_dfi_tphy_wrcslat_MASK (0x3FU) #define DDRC_DFITMG2_dfi_tphy_wrcslat_SHIFT (0U) #define DDRC_DFITMG2_dfi_tphy_wrcslat(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_dfi_tphy_wrcslat_SHIFT)) & DDRC_DFITMG2_dfi_tphy_wrcslat_MASK) #define DDRC_DFITMG2_dfi_tphy_rdcslat_MASK (0x7F00U) #define DDRC_DFITMG2_dfi_tphy_rdcslat_SHIFT (8U) #define DDRC_DFITMG2_dfi_tphy_rdcslat(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_dfi_tphy_rdcslat_SHIFT)) & DDRC_DFITMG2_dfi_tphy_rdcslat_MASK) /*! @} */ /*! @name DFITMG3 - DFI Timing Register 3 */ /*! @{ */ #define DDRC_DFITMG3_dfi_t_geardown_delay_MASK (0x1FU) #define DDRC_DFITMG3_dfi_t_geardown_delay_SHIFT (0U) #define DDRC_DFITMG3_dfi_t_geardown_delay(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_dfi_t_geardown_delay_SHIFT)) & DDRC_DFITMG3_dfi_t_geardown_delay_MASK) /*! @} */ /*! @name DFISTAT - DFI Status Register */ /*! @{ */ #define DDRC_DFISTAT_dfi_init_complete_MASK (0x1U) #define DDRC_DFISTAT_dfi_init_complete_SHIFT (0U) #define DDRC_DFISTAT_dfi_init_complete(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_dfi_init_complete_SHIFT)) & DDRC_DFISTAT_dfi_init_complete_MASK) #define DDRC_DFISTAT_dfi_lp_ack_MASK (0x2U) #define DDRC_DFISTAT_dfi_lp_ack_SHIFT (1U) #define DDRC_DFISTAT_dfi_lp_ack(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_dfi_lp_ack_SHIFT)) & DDRC_DFISTAT_dfi_lp_ack_MASK) /*! @} */ /*! @name DBICTL - DM/DBI Control Register */ /*! @{ */ #define DDRC_DBICTL_dm_en_MASK (0x1U) #define DDRC_DBICTL_dm_en_SHIFT (0U) /*! dm_en - DM enable signal in DDRC. This signal must be set the same logical value as DRAM's mode * register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal * must be set to 0. - LPDDR4: Set this to inverted value of MR13[5] which is opposite polarity * from this signal * 0b0..DM is disabled * 0b1..DM is enabled */ #define DDRC_DBICTL_dm_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_dm_en_SHIFT)) & DDRC_DBICTL_dm_en_MASK) #define DDRC_DBICTL_wr_dbi_en_MASK (0x2U) #define DDRC_DBICTL_wr_dbi_en_SHIFT (1U) /*! wr_dbi_en - This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A11. * When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7] * 0b0..Write DBI is disabled * 0b1..Write DBI is enabled. */ #define DDRC_DBICTL_wr_dbi_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_wr_dbi_en_SHIFT)) & DDRC_DBICTL_wr_dbi_en_MASK) #define DDRC_DBICTL_rd_dbi_en_MASK (0x4U) #define DDRC_DBICTL_rd_dbi_en_SHIFT (2U) #define DDRC_DBICTL_rd_dbi_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_rd_dbi_en_SHIFT)) & DDRC_DBICTL_rd_dbi_en_MASK) /*! @} */ /*! @name ADDRMAP0 - Address Map Register 0 */ /*! @{ */ #define DDRC_ADDRMAP0_addrmap_cs_bit0_MASK (0x1FU) #define DDRC_ADDRMAP0_addrmap_cs_bit0_SHIFT (0U) #define DDRC_ADDRMAP0_addrmap_cs_bit0(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP0_addrmap_cs_bit0_SHIFT)) & DDRC_ADDRMAP0_addrmap_cs_bit0_MASK) /*! @} */ /*! @name ADDRMAP1 - Address Map Register 1 */ /*! @{ */ #define DDRC_ADDRMAP1_addrmap_bank_b0_MASK (0x1FU) #define DDRC_ADDRMAP1_addrmap_bank_b0_SHIFT (0U) #define DDRC_ADDRMAP1_addrmap_bank_b0(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b0_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b0_MASK) #define DDRC_ADDRMAP1_addrmap_bank_b1_MASK (0x1F00U) #define DDRC_ADDRMAP1_addrmap_bank_b1_SHIFT (8U) #define DDRC_ADDRMAP1_addrmap_bank_b1(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b1_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b1_MASK) #define DDRC_ADDRMAP1_addrmap_bank_b2_MASK (0x1F0000U) #define DDRC_ADDRMAP1_addrmap_bank_b2_SHIFT (16U) #define DDRC_ADDRMAP1_addrmap_bank_b2(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b2_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b2_MASK) /*! @} */ /*! @name ADDRMAP2 - Address Map Register 2 */ /*! @{ */ #define DDRC_ADDRMAP2_addrmap_col_b2_MASK (0xFU) #define DDRC_ADDRMAP2_addrmap_col_b2_SHIFT (0U) #define DDRC_ADDRMAP2_addrmap_col_b2(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b2_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b2_MASK) #define DDRC_ADDRMAP2_addrmap_col_b3_MASK (0xF00U) #define DDRC_ADDRMAP2_addrmap_col_b3_SHIFT (8U) #define DDRC_ADDRMAP2_addrmap_col_b3(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b3_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b3_MASK) #define DDRC_ADDRMAP2_addrmap_col_b4_MASK (0xF0000U) #define DDRC_ADDRMAP2_addrmap_col_b4_SHIFT (16U) #define DDRC_ADDRMAP2_addrmap_col_b4(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b4_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b4_MASK) #define DDRC_ADDRMAP2_addrmap_col_b5_MASK (0xF000000U) #define DDRC_ADDRMAP2_addrmap_col_b5_SHIFT (24U) #define DDRC_ADDRMAP2_addrmap_col_b5(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b5_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b5_MASK) /*! @} */ /*! @name ADDRMAP3 - Address Map Register 3 */ /*! @{ */ #define DDRC_ADDRMAP3_addrmap_col_b6_MASK (0xFU) #define DDRC_ADDRMAP3_addrmap_col_b6_SHIFT (0U) #define DDRC_ADDRMAP3_addrmap_col_b6(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b6_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b6_MASK) #define DDRC_ADDRMAP3_addrmap_col_b7_MASK (0xF00U) #define DDRC_ADDRMAP3_addrmap_col_b7_SHIFT (8U) #define DDRC_ADDRMAP3_addrmap_col_b7(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b7_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b7_MASK) #define DDRC_ADDRMAP3_addrmap_col_b8_MASK (0xF0000U) #define DDRC_ADDRMAP3_addrmap_col_b8_SHIFT (16U) #define DDRC_ADDRMAP3_addrmap_col_b8(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b8_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b8_MASK) #define DDRC_ADDRMAP3_addrmap_col_b9_MASK (0xF000000U) #define DDRC_ADDRMAP3_addrmap_col_b9_SHIFT (24U) #define DDRC_ADDRMAP3_addrmap_col_b9(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b9_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b9_MASK) /*! @} */ /*! @name ADDRMAP4 - Address Map Register 4 */ /*! @{ */ #define DDRC_ADDRMAP4_addrmap_col_b10_MASK (0xFU) #define DDRC_ADDRMAP4_addrmap_col_b10_SHIFT (0U) #define DDRC_ADDRMAP4_addrmap_col_b10(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_addrmap_col_b10_SHIFT)) & DDRC_ADDRMAP4_addrmap_col_b10_MASK) #define DDRC_ADDRMAP4_addrmap_col_b11_MASK (0xF00U) #define DDRC_ADDRMAP4_addrmap_col_b11_SHIFT (8U) #define DDRC_ADDRMAP4_addrmap_col_b11(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_addrmap_col_b11_SHIFT)) & DDRC_ADDRMAP4_addrmap_col_b11_MASK) /*! @} */ /*! @name ADDRMAP5 - Address Map Register 5 */ /*! @{ */ #define DDRC_ADDRMAP5_addrmap_row_b0_MASK (0xFU) #define DDRC_ADDRMAP5_addrmap_row_b0_SHIFT (0U) #define DDRC_ADDRMAP5_addrmap_row_b0(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b0_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b0_MASK) #define DDRC_ADDRMAP5_addrmap_row_b1_MASK (0xF00U) #define DDRC_ADDRMAP5_addrmap_row_b1_SHIFT (8U) #define DDRC_ADDRMAP5_addrmap_row_b1(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b1_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b1_MASK) #define DDRC_ADDRMAP5_addrmap_row_b2_10_MASK (0xF0000U) #define DDRC_ADDRMAP5_addrmap_row_b2_10_SHIFT (16U) #define DDRC_ADDRMAP5_addrmap_row_b2_10(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b2_10_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b2_10_MASK) #define DDRC_ADDRMAP5_addrmap_row_b11_MASK (0xF000000U) #define DDRC_ADDRMAP5_addrmap_row_b11_SHIFT (24U) #define DDRC_ADDRMAP5_addrmap_row_b11(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b11_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b11_MASK) /*! @} */ /*! @name ADDRMAP6 - Address Map Register 6 */ /*! @{ */ #define DDRC_ADDRMAP6_addrmap_row_b12_MASK (0xFU) #define DDRC_ADDRMAP6_addrmap_row_b12_SHIFT (0U) #define DDRC_ADDRMAP6_addrmap_row_b12(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b12_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b12_MASK) #define DDRC_ADDRMAP6_addrmap_row_b13_MASK (0xF00U) #define DDRC_ADDRMAP6_addrmap_row_b13_SHIFT (8U) #define DDRC_ADDRMAP6_addrmap_row_b13(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b13_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b13_MASK) #define DDRC_ADDRMAP6_addrmap_row_b14_MASK (0xF0000U) #define DDRC_ADDRMAP6_addrmap_row_b14_SHIFT (16U) #define DDRC_ADDRMAP6_addrmap_row_b14(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b14_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b14_MASK) #define DDRC_ADDRMAP6_addrmap_row_b15_MASK (0xF000000U) #define DDRC_ADDRMAP6_addrmap_row_b15_SHIFT (24U) #define DDRC_ADDRMAP6_addrmap_row_b15(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b15_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b15_MASK) #define DDRC_ADDRMAP6_lpddr3_6gb_12gb_MASK (0x80000000U) #define DDRC_ADDRMAP6_lpddr3_6gb_12gb_SHIFT (31U) #define DDRC_ADDRMAP6_lpddr3_6gb_12gb(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_lpddr3_6gb_12gb_SHIFT)) & DDRC_ADDRMAP6_lpddr3_6gb_12gb_MASK) /*! @} */ /*! @name ADDRMAP7 - Address Map Register 7 */ /*! @{ */ #define DDRC_ADDRMAP7_addrmap_row_b16_MASK (0xFU) #define DDRC_ADDRMAP7_addrmap_row_b16_SHIFT (0U) #define DDRC_ADDRMAP7_addrmap_row_b16(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_addrmap_row_b16_SHIFT)) & DDRC_ADDRMAP7_addrmap_row_b16_MASK) #define DDRC_ADDRMAP7_addrmap_row_b17_MASK (0xF00U) #define DDRC_ADDRMAP7_addrmap_row_b17_SHIFT (8U) #define DDRC_ADDRMAP7_addrmap_row_b17(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_addrmap_row_b17_SHIFT)) & DDRC_ADDRMAP7_addrmap_row_b17_MASK) /*! @} */ /*! @name ADDRMAP8 - Address Map Register 8 */ /*! @{ */ #define DDRC_ADDRMAP8_addrmap_bg_b0_MASK (0x1FU) #define DDRC_ADDRMAP8_addrmap_bg_b0_SHIFT (0U) #define DDRC_ADDRMAP8_addrmap_bg_b0(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_addrmap_bg_b0_SHIFT)) & DDRC_ADDRMAP8_addrmap_bg_b0_MASK) #define DDRC_ADDRMAP8_addrmap_bg_b1_MASK (0x3F00U) #define DDRC_ADDRMAP8_addrmap_bg_b1_SHIFT (8U) #define DDRC_ADDRMAP8_addrmap_bg_b1(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_addrmap_bg_b1_SHIFT)) & DDRC_ADDRMAP8_addrmap_bg_b1_MASK) /*! @} */ /*! @name ADDRMAP9 - Address Map Register 9 */ /*! @{ */ #define DDRC_ADDRMAP9_addrmap_row_b2_MASK (0xFU) #define DDRC_ADDRMAP9_addrmap_row_b2_SHIFT (0U) #define DDRC_ADDRMAP9_addrmap_row_b2(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b2_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b2_MASK) #define DDRC_ADDRMAP9_addrmap_row_b3_MASK (0xF00U) #define DDRC_ADDRMAP9_addrmap_row_b3_SHIFT (8U) #define DDRC_ADDRMAP9_addrmap_row_b3(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b3_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b3_MASK) #define DDRC_ADDRMAP9_addrmap_row_b4_MASK (0xF0000U) #define DDRC_ADDRMAP9_addrmap_row_b4_SHIFT (16U) #define DDRC_ADDRMAP9_addrmap_row_b4(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b4_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b4_MASK) #define DDRC_ADDRMAP9_addrmap_row_b5_MASK (0xF000000U) #define DDRC_ADDRMAP9_addrmap_row_b5_SHIFT (24U) #define DDRC_ADDRMAP9_addrmap_row_b5(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b5_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b5_MASK) /*! @} */ /*! @name ADDRMAP10 - Address Map Register 10 */ /*! @{ */ #define DDRC_ADDRMAP10_addrmap_row_b6_MASK (0xFU) #define DDRC_ADDRMAP10_addrmap_row_b6_SHIFT (0U) #define DDRC_ADDRMAP10_addrmap_row_b6(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b6_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b6_MASK) #define DDRC_ADDRMAP10_addrmap_row_b7_MASK (0xF00U) #define DDRC_ADDRMAP10_addrmap_row_b7_SHIFT (8U) #define DDRC_ADDRMAP10_addrmap_row_b7(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b7_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b7_MASK) #define DDRC_ADDRMAP10_addrmap_row_b8_MASK (0xF0000U) #define DDRC_ADDRMAP10_addrmap_row_b8_SHIFT (16U) #define DDRC_ADDRMAP10_addrmap_row_b8(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b8_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b8_MASK) #define DDRC_ADDRMAP10_addrmap_row_b9_MASK (0xF000000U) #define DDRC_ADDRMAP10_addrmap_row_b9_SHIFT (24U) #define DDRC_ADDRMAP10_addrmap_row_b9(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b9_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b9_MASK) /*! @} */ /*! @name ADDRMAP11 - Address Map Register 11 */ /*! @{ */ #define DDRC_ADDRMAP11_addrmap_row_b10_MASK (0xFU) #define DDRC_ADDRMAP11_addrmap_row_b10_SHIFT (0U) #define DDRC_ADDRMAP11_addrmap_row_b10(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP11_addrmap_row_b10_SHIFT)) & DDRC_ADDRMAP11_addrmap_row_b10_MASK) /*! @} */ /*! @name ODTCFG - ODT Configuration Register */ /*! @{ */ #define DDRC_ODTCFG_rd_odt_delay_MASK (0x7CU) #define DDRC_ODTCFG_rd_odt_delay_SHIFT (2U) #define DDRC_ODTCFG_rd_odt_delay(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_rd_odt_delay_SHIFT)) & DDRC_ODTCFG_rd_odt_delay_MASK) #define DDRC_ODTCFG_rd_odt_hold_MASK (0xF00U) #define DDRC_ODTCFG_rd_odt_hold_SHIFT (8U) #define DDRC_ODTCFG_rd_odt_hold(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_rd_odt_hold_SHIFT)) & DDRC_ODTCFG_rd_odt_hold_MASK) #define DDRC_ODTCFG_wr_odt_delay_MASK (0x1F0000U) #define DDRC_ODTCFG_wr_odt_delay_SHIFT (16U) #define DDRC_ODTCFG_wr_odt_delay(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_wr_odt_delay_SHIFT)) & DDRC_ODTCFG_wr_odt_delay_MASK) #define DDRC_ODTCFG_wr_odt_hold_MASK (0xF000000U) #define DDRC_ODTCFG_wr_odt_hold_SHIFT (24U) #define DDRC_ODTCFG_wr_odt_hold(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_wr_odt_hold_SHIFT)) & DDRC_ODTCFG_wr_odt_hold_MASK) /*! @} */ /*! @name ODTMAP - ODT/Rank Map Register */ /*! @{ */ #define DDRC_ODTMAP_rank0_wr_odt_MASK (0x3U) #define DDRC_ODTMAP_rank0_wr_odt_SHIFT (0U) #define DDRC_ODTMAP_rank0_wr_odt(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank0_wr_odt_SHIFT)) & DDRC_ODTMAP_rank0_wr_odt_MASK) #define DDRC_ODTMAP_rank0_rd_odt_MASK (0x30U) #define DDRC_ODTMAP_rank0_rd_odt_SHIFT (4U) #define DDRC_ODTMAP_rank0_rd_odt(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank0_rd_odt_SHIFT)) & DDRC_ODTMAP_rank0_rd_odt_MASK) #define DDRC_ODTMAP_rank1_wr_odt_MASK (0x300U) #define DDRC_ODTMAP_rank1_wr_odt_SHIFT (8U) #define DDRC_ODTMAP_rank1_wr_odt(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank1_wr_odt_SHIFT)) & DDRC_ODTMAP_rank1_wr_odt_MASK) #define DDRC_ODTMAP_rank1_rd_odt_MASK (0x3000U) #define DDRC_ODTMAP_rank1_rd_odt_SHIFT (12U) #define DDRC_ODTMAP_rank1_rd_odt(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank1_rd_odt_SHIFT)) & DDRC_ODTMAP_rank1_rd_odt_MASK) /*! @} */ /*! @name SCHED - Scheduler Control Register */ /*! @{ */ #define DDRC_SCHED_force_low_pri_n_MASK (0x1U) #define DDRC_SCHED_force_low_pri_n_SHIFT (0U) #define DDRC_SCHED_force_low_pri_n(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_force_low_pri_n_SHIFT)) & DDRC_SCHED_force_low_pri_n_MASK) #define DDRC_SCHED_prefer_write_MASK (0x2U) #define DDRC_SCHED_prefer_write_SHIFT (1U) #define DDRC_SCHED_prefer_write(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_prefer_write_SHIFT)) & DDRC_SCHED_prefer_write_MASK) #define DDRC_SCHED_pageclose_MASK (0x4U) #define DDRC_SCHED_pageclose_SHIFT (2U) #define DDRC_SCHED_pageclose(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_pageclose_SHIFT)) & DDRC_SCHED_pageclose_MASK) #define DDRC_SCHED_lpr_num_entries_MASK (0x1F00U) #define DDRC_SCHED_lpr_num_entries_SHIFT (8U) #define DDRC_SCHED_lpr_num_entries(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_lpr_num_entries_SHIFT)) & DDRC_SCHED_lpr_num_entries_MASK) #define DDRC_SCHED_go2critical_hysteresis_MASK (0xFF0000U) #define DDRC_SCHED_go2critical_hysteresis_SHIFT (16U) #define DDRC_SCHED_go2critical_hysteresis(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_go2critical_hysteresis_SHIFT)) & DDRC_SCHED_go2critical_hysteresis_MASK) #define DDRC_SCHED_rdwr_idle_gap_MASK (0x7F000000U) #define DDRC_SCHED_rdwr_idle_gap_SHIFT (24U) #define DDRC_SCHED_rdwr_idle_gap(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_rdwr_idle_gap_SHIFT)) & DDRC_SCHED_rdwr_idle_gap_MASK) /*! @} */ /*! @name SCHED1 - Scheduler Control Register 1 */ /*! @{ */ #define DDRC_SCHED1_pageclose_timer_MASK (0xFFU) #define DDRC_SCHED1_pageclose_timer_SHIFT (0U) #define DDRC_SCHED1_pageclose_timer(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED1_pageclose_timer_SHIFT)) & DDRC_SCHED1_pageclose_timer_MASK) /*! @} */ /*! @name PERFHPR1 - High Priority Read CAM Register 1 */ /*! @{ */ #define DDRC_PERFHPR1_hpr_max_starve_MASK (0xFFFFU) #define DDRC_PERFHPR1_hpr_max_starve_SHIFT (0U) #define DDRC_PERFHPR1_hpr_max_starve(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_hpr_max_starve_SHIFT)) & DDRC_PERFHPR1_hpr_max_starve_MASK) #define DDRC_PERFHPR1_hpr_xact_run_length_MASK (0xFF000000U) #define DDRC_PERFHPR1_hpr_xact_run_length_SHIFT (24U) #define DDRC_PERFHPR1_hpr_xact_run_length(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_hpr_xact_run_length_SHIFT)) & DDRC_PERFHPR1_hpr_xact_run_length_MASK) /*! @} */ /*! @name PERFLPR1 - Low Priority Read CAM Register 1 */ /*! @{ */ #define DDRC_PERFLPR1_lpr_max_starve_MASK (0xFFFFU) #define DDRC_PERFLPR1_lpr_max_starve_SHIFT (0U) #define DDRC_PERFLPR1_lpr_max_starve(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_lpr_max_starve_SHIFT)) & DDRC_PERFLPR1_lpr_max_starve_MASK) #define DDRC_PERFLPR1_lpr_xact_run_length_MASK (0xFF000000U) #define DDRC_PERFLPR1_lpr_xact_run_length_SHIFT (24U) #define DDRC_PERFLPR1_lpr_xact_run_length(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_lpr_xact_run_length_SHIFT)) & DDRC_PERFLPR1_lpr_xact_run_length_MASK) /*! @} */ /*! @name PERFWR1 - Write CAM Register 1 */ /*! @{ */ #define DDRC_PERFWR1_w_max_starve_MASK (0xFFFFU) #define DDRC_PERFWR1_w_max_starve_SHIFT (0U) #define DDRC_PERFWR1_w_max_starve(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_w_max_starve_SHIFT)) & DDRC_PERFWR1_w_max_starve_MASK) #define DDRC_PERFWR1_w_xact_run_length_MASK (0xFF000000U) #define DDRC_PERFWR1_w_xact_run_length_SHIFT (24U) #define DDRC_PERFWR1_w_xact_run_length(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_w_xact_run_length_SHIFT)) & DDRC_PERFWR1_w_xact_run_length_MASK) /*! @} */ /*! @name DBG0 - Debug Register 0 */ /*! @{ */ #define DDRC_DBG0_dis_wc_MASK (0x1U) #define DDRC_DBG0_dis_wc_SHIFT (0U) #define DDRC_DBG0_dis_wc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_wc_SHIFT)) & DDRC_DBG0_dis_wc_MASK) #define DDRC_DBG0_dis_rd_bypass_MASK (0x2U) #define DDRC_DBG0_dis_rd_bypass_SHIFT (1U) #define DDRC_DBG0_dis_rd_bypass(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_rd_bypass_SHIFT)) & DDRC_DBG0_dis_rd_bypass_MASK) #define DDRC_DBG0_dis_act_bypass_MASK (0x4U) #define DDRC_DBG0_dis_act_bypass_SHIFT (2U) #define DDRC_DBG0_dis_act_bypass(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_act_bypass_SHIFT)) & DDRC_DBG0_dis_act_bypass_MASK) #define DDRC_DBG0_dis_collision_page_opt_MASK (0x10U) #define DDRC_DBG0_dis_collision_page_opt_SHIFT (4U) #define DDRC_DBG0_dis_collision_page_opt(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_collision_page_opt_SHIFT)) & DDRC_DBG0_dis_collision_page_opt_MASK) /*! @} */ /*! @name DBG1 - Debug Register 1 */ /*! @{ */ #define DDRC_DBG1_dis_dq_MASK (0x1U) #define DDRC_DBG1_dis_dq_SHIFT (0U) #define DDRC_DBG1_dis_dq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG1_dis_dq_SHIFT)) & DDRC_DBG1_dis_dq_MASK) #define DDRC_DBG1_dis_hif_MASK (0x2U) #define DDRC_DBG1_dis_hif_SHIFT (1U) #define DDRC_DBG1_dis_hif(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG1_dis_hif_SHIFT)) & DDRC_DBG1_dis_hif_MASK) /*! @} */ /*! @name DBGCAM - CAM Debug Register */ /*! @{ */ #define DDRC_DBGCAM_dbg_hpr_q_depth_MASK (0x3FU) #define DDRC_DBGCAM_dbg_hpr_q_depth_SHIFT (0U) #define DDRC_DBGCAM_dbg_hpr_q_depth(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_hpr_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_hpr_q_depth_MASK) #define DDRC_DBGCAM_dbg_lpr_q_depth_MASK (0x3F00U) #define DDRC_DBGCAM_dbg_lpr_q_depth_SHIFT (8U) #define DDRC_DBGCAM_dbg_lpr_q_depth(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_lpr_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_lpr_q_depth_MASK) #define DDRC_DBGCAM_dbg_w_q_depth_MASK (0x3F0000U) #define DDRC_DBGCAM_dbg_w_q_depth_SHIFT (16U) #define DDRC_DBGCAM_dbg_w_q_depth(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_w_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_w_q_depth_MASK) #define DDRC_DBGCAM_dbg_stall_MASK (0x1000000U) #define DDRC_DBGCAM_dbg_stall_SHIFT (24U) #define DDRC_DBGCAM_dbg_stall(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_SHIFT)) & DDRC_DBGCAM_dbg_stall_MASK) #define DDRC_DBGCAM_dbg_rd_q_empty_MASK (0x2000000U) #define DDRC_DBGCAM_dbg_rd_q_empty_SHIFT (25U) #define DDRC_DBGCAM_dbg_rd_q_empty(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_rd_q_empty_SHIFT)) & DDRC_DBGCAM_dbg_rd_q_empty_MASK) #define DDRC_DBGCAM_dbg_wr_q_empty_MASK (0x4000000U) #define DDRC_DBGCAM_dbg_wr_q_empty_SHIFT (26U) #define DDRC_DBGCAM_dbg_wr_q_empty(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_wr_q_empty_SHIFT)) & DDRC_DBGCAM_dbg_wr_q_empty_MASK) #define DDRC_DBGCAM_rd_data_pipeline_empty_MASK (0x10000000U) #define DDRC_DBGCAM_rd_data_pipeline_empty_SHIFT (28U) #define DDRC_DBGCAM_rd_data_pipeline_empty(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_rd_data_pipeline_empty_SHIFT)) & \ DDRC_DBGCAM_rd_data_pipeline_empty_MASK) #define DDRC_DBGCAM_wr_data_pipeline_empty_MASK (0x20000000U) #define DDRC_DBGCAM_wr_data_pipeline_empty_SHIFT (29U) #define DDRC_DBGCAM_wr_data_pipeline_empty(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_wr_data_pipeline_empty_SHIFT)) & \ DDRC_DBGCAM_wr_data_pipeline_empty_MASK) #define DDRC_DBGCAM_dbg_stall_wr_MASK (0x40000000U) #define DDRC_DBGCAM_dbg_stall_wr_SHIFT (30U) #define DDRC_DBGCAM_dbg_stall_wr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_wr_SHIFT)) & DDRC_DBGCAM_dbg_stall_wr_MASK) #define DDRC_DBGCAM_dbg_stall_rd_MASK (0x80000000U) #define DDRC_DBGCAM_dbg_stall_rd_SHIFT (31U) #define DDRC_DBGCAM_dbg_stall_rd(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_rd_SHIFT)) & DDRC_DBGCAM_dbg_stall_rd_MASK) /*! @} */ /*! @name DBGCMD - Command Debug Register */ /*! @{ */ #define DDRC_DBGCMD_rank0_refresh_MASK (0x1U) #define DDRC_DBGCMD_rank0_refresh_SHIFT (0U) #define DDRC_DBGCMD_rank0_refresh(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_rank0_refresh_SHIFT)) & DDRC_DBGCMD_rank0_refresh_MASK) #define DDRC_DBGCMD_rank1_refresh_MASK (0x2U) #define DDRC_DBGCMD_rank1_refresh_SHIFT (1U) #define DDRC_DBGCMD_rank1_refresh(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_rank1_refresh_SHIFT)) & DDRC_DBGCMD_rank1_refresh_MASK) #define DDRC_DBGCMD_zq_calib_short_MASK (0x10U) #define DDRC_DBGCMD_zq_calib_short_SHIFT (4U) #define DDRC_DBGCMD_zq_calib_short(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_zq_calib_short_SHIFT)) & DDRC_DBGCMD_zq_calib_short_MASK) #define DDRC_DBGCMD_ctrlupd_MASK (0x20U) #define DDRC_DBGCMD_ctrlupd_SHIFT (5U) #define DDRC_DBGCMD_ctrlupd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_ctrlupd_SHIFT)) & DDRC_DBGCMD_ctrlupd_MASK) /*! @} */ /*! @name DBGSTAT - Status Debug Register */ /*! @{ */ #define DDRC_DBGSTAT_rank0_refresh_busy_MASK (0x1U) #define DDRC_DBGSTAT_rank0_refresh_busy_SHIFT (0U) #define DDRC_DBGSTAT_rank0_refresh_busy(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_rank0_refresh_busy_SHIFT)) & DDRC_DBGSTAT_rank0_refresh_busy_MASK) #define DDRC_DBGSTAT_rank1_refresh_busy_MASK (0x2U) #define DDRC_DBGSTAT_rank1_refresh_busy_SHIFT (1U) #define DDRC_DBGSTAT_rank1_refresh_busy(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_rank1_refresh_busy_SHIFT)) & DDRC_DBGSTAT_rank1_refresh_busy_MASK) #define DDRC_DBGSTAT_zq_calib_short_busy_MASK (0x10U) #define DDRC_DBGSTAT_zq_calib_short_busy_SHIFT (4U) #define DDRC_DBGSTAT_zq_calib_short_busy(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_zq_calib_short_busy_SHIFT)) & DDRC_DBGSTAT_zq_calib_short_busy_MASK) #define DDRC_DBGSTAT_ctrlupd_busy_MASK (0x20U) #define DDRC_DBGSTAT_ctrlupd_busy_SHIFT (5U) #define DDRC_DBGSTAT_ctrlupd_busy(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_ctrlupd_busy_SHIFT)) & DDRC_DBGSTAT_ctrlupd_busy_MASK) /*! @} */ /*! @name SWCTL - Software Register Programming Control Enable */ /*! @{ */ #define DDRC_SWCTL_sw_done_MASK (0x1U) #define DDRC_SWCTL_sw_done_SHIFT (0U) #define DDRC_SWCTL_sw_done(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SWCTL_sw_done_SHIFT)) & DDRC_SWCTL_sw_done_MASK) /*! @} */ /*! @name SWSTAT - Software Register Programming Control Status */ /*! @{ */ #define DDRC_SWSTAT_sw_done_ack_MASK (0x1U) #define DDRC_SWSTAT_sw_done_ack_SHIFT (0U) #define DDRC_SWSTAT_sw_done_ack(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_SWSTAT_sw_done_ack_SHIFT)) & DDRC_SWSTAT_sw_done_ack_MASK) /*! @} */ /*! @name POISONCFG - AXI Poison Configuration Register. */ /*! @{ */ #define DDRC_POISONCFG_wr_poison_slverr_en_MASK (0x1U) #define DDRC_POISONCFG_wr_poison_slverr_en_SHIFT (0U) #define DDRC_POISONCFG_wr_poison_slverr_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_slverr_en_SHIFT)) & \ DDRC_POISONCFG_wr_poison_slverr_en_MASK) #define DDRC_POISONCFG_wr_poison_intr_en_MASK (0x10U) #define DDRC_POISONCFG_wr_poison_intr_en_SHIFT (4U) #define DDRC_POISONCFG_wr_poison_intr_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_intr_en_SHIFT)) & DDRC_POISONCFG_wr_poison_intr_en_MASK) #define DDRC_POISONCFG_wr_poison_intr_clr_MASK (0x100U) #define DDRC_POISONCFG_wr_poison_intr_clr_SHIFT (8U) #define DDRC_POISONCFG_wr_poison_intr_clr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_intr_clr_SHIFT)) & DDRC_POISONCFG_wr_poison_intr_clr_MASK) #define DDRC_POISONCFG_rd_poison_slverr_en_MASK (0x10000U) #define DDRC_POISONCFG_rd_poison_slverr_en_SHIFT (16U) #define DDRC_POISONCFG_rd_poison_slverr_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_slverr_en_SHIFT)) & \ DDRC_POISONCFG_rd_poison_slverr_en_MASK) #define DDRC_POISONCFG_rd_poison_intr_en_MASK (0x100000U) #define DDRC_POISONCFG_rd_poison_intr_en_SHIFT (20U) #define DDRC_POISONCFG_rd_poison_intr_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_intr_en_SHIFT)) & DDRC_POISONCFG_rd_poison_intr_en_MASK) #define DDRC_POISONCFG_rd_poison_intr_clr_MASK (0x1000000U) #define DDRC_POISONCFG_rd_poison_intr_clr_SHIFT (24U) #define DDRC_POISONCFG_rd_poison_intr_clr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_intr_clr_SHIFT)) & DDRC_POISONCFG_rd_poison_intr_clr_MASK) /*! @} */ /*! @name POISONSTAT - AXI Poison Status Register */ /*! @{ */ #define DDRC_POISONSTAT_wr_poison_intr_0_MASK (0x1U) #define DDRC_POISONSTAT_wr_poison_intr_0_SHIFT (0U) #define DDRC_POISONSTAT_wr_poison_intr_0(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_POISONSTAT_wr_poison_intr_0_SHIFT)) & DDRC_POISONSTAT_wr_poison_intr_0_MASK) #define DDRC_POISONSTAT_rd_poison_intr_0_MASK (0x10000U) #define DDRC_POISONSTAT_rd_poison_intr_0_SHIFT (16U) #define DDRC_POISONSTAT_rd_poison_intr_0(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_POISONSTAT_rd_poison_intr_0_SHIFT)) & DDRC_POISONSTAT_rd_poison_intr_0_MASK) /*! @} */ /*! @name PSTAT - Port Status Register */ /*! @{ */ #define DDRC_PSTAT_rd_port_busy_0_MASK (0x1U) #define DDRC_PSTAT_rd_port_busy_0_SHIFT (0U) #define DDRC_PSTAT_rd_port_busy_0(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PSTAT_rd_port_busy_0_SHIFT)) & DDRC_PSTAT_rd_port_busy_0_MASK) #define DDRC_PSTAT_wr_port_busy_0_MASK (0x10000U) #define DDRC_PSTAT_wr_port_busy_0_SHIFT (16U) #define DDRC_PSTAT_wr_port_busy_0(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PSTAT_wr_port_busy_0_SHIFT)) & DDRC_PSTAT_wr_port_busy_0_MASK) /*! @} */ /*! @name PCCFG - Port Common Configuration Register */ /*! @{ */ #define DDRC_PCCFG_go2critical_en_MASK (0x1U) #define DDRC_PCCFG_go2critical_en_SHIFT (0U) #define DDRC_PCCFG_go2critical_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_go2critical_en_SHIFT)) & DDRC_PCCFG_go2critical_en_MASK) #define DDRC_PCCFG_pagematch_limit_MASK (0x10U) #define DDRC_PCCFG_pagematch_limit_SHIFT (4U) #define DDRC_PCCFG_pagematch_limit(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_pagematch_limit_SHIFT)) & DDRC_PCCFG_pagematch_limit_MASK) #define DDRC_PCCFG_bl_exp_mode_MASK (0x100U) #define DDRC_PCCFG_bl_exp_mode_SHIFT (8U) #define DDRC_PCCFG_bl_exp_mode(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_bl_exp_mode_SHIFT)) & DDRC_PCCFG_bl_exp_mode_MASK) /*! @} */ /*! @name PCFGR_0 - Port n Configuration Read Register */ /*! @{ */ #define DDRC_PCFGR_0_rd_port_priority_MASK (0x3FFU) #define DDRC_PCFGR_0_rd_port_priority_SHIFT (0U) #define DDRC_PCFGR_0_rd_port_priority(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_priority_SHIFT)) & DDRC_PCFGR_0_rd_port_priority_MASK) #define DDRC_PCFGR_0_rd_port_aging_en_MASK (0x1000U) #define DDRC_PCFGR_0_rd_port_aging_en_SHIFT (12U) #define DDRC_PCFGR_0_rd_port_aging_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_aging_en_SHIFT)) & DDRC_PCFGR_0_rd_port_aging_en_MASK) #define DDRC_PCFGR_0_rd_port_urgent_en_MASK (0x2000U) #define DDRC_PCFGR_0_rd_port_urgent_en_SHIFT (13U) #define DDRC_PCFGR_0_rd_port_urgent_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_urgent_en_SHIFT)) & DDRC_PCFGR_0_rd_port_urgent_en_MASK) #define DDRC_PCFGR_0_rd_port_pagematch_en_MASK (0x4000U) #define DDRC_PCFGR_0_rd_port_pagematch_en_SHIFT (14U) #define DDRC_PCFGR_0_rd_port_pagematch_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_pagematch_en_SHIFT)) & DDRC_PCFGR_0_rd_port_pagematch_en_MASK) #define DDRC_PCFGR_0_rdwr_ordered_en_MASK (0x10000U) #define DDRC_PCFGR_0_rdwr_ordered_en_SHIFT (16U) #define DDRC_PCFGR_0_rdwr_ordered_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rdwr_ordered_en_SHIFT)) & DDRC_PCFGR_0_rdwr_ordered_en_MASK) /*! @} */ /*! @name PCFGW_0 - Port n Configuration Write Register */ /*! @{ */ #define DDRC_PCFGW_0_wr_port_priority_MASK (0x3FFU) #define DDRC_PCFGW_0_wr_port_priority_SHIFT (0U) #define DDRC_PCFGW_0_wr_port_priority(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_priority_SHIFT)) & DDRC_PCFGW_0_wr_port_priority_MASK) #define DDRC_PCFGW_0_wr_port_aging_en_MASK (0x1000U) #define DDRC_PCFGW_0_wr_port_aging_en_SHIFT (12U) #define DDRC_PCFGW_0_wr_port_aging_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_aging_en_SHIFT)) & DDRC_PCFGW_0_wr_port_aging_en_MASK) #define DDRC_PCFGW_0_wr_port_urgent_en_MASK (0x2000U) #define DDRC_PCFGW_0_wr_port_urgent_en_SHIFT (13U) #define DDRC_PCFGW_0_wr_port_urgent_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_urgent_en_SHIFT)) & DDRC_PCFGW_0_wr_port_urgent_en_MASK) #define DDRC_PCFGW_0_wr_port_pagematch_en_MASK (0x4000U) #define DDRC_PCFGW_0_wr_port_pagematch_en_SHIFT (14U) #define DDRC_PCFGW_0_wr_port_pagematch_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_pagematch_en_SHIFT)) & DDRC_PCFGW_0_wr_port_pagematch_en_MASK) /*! @} */ /*! @name PCTRL_0 - Port n Control Register */ /*! @{ */ #define DDRC_PCTRL_0_port_en_MASK (0x1U) #define DDRC_PCTRL_0_port_en_SHIFT (0U) #define DDRC_PCTRL_0_port_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCTRL_0_port_en_SHIFT)) & DDRC_PCTRL_0_port_en_MASK) /*! @} */ /*! @name PCFGQOS0_0 - Port n Read QoS Configuration Register 0 */ /*! @{ */ #define DDRC_PCFGQOS0_0_rqos_map_level1_MASK (0xFU) #define DDRC_PCFGQOS0_0_rqos_map_level1_SHIFT (0U) #define DDRC_PCFGQOS0_0_rqos_map_level1(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_level1_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_level1_MASK) #define DDRC_PCFGQOS0_0_rqos_map_region0_MASK (0x30000U) #define DDRC_PCFGQOS0_0_rqos_map_region0_SHIFT (16U) #define DDRC_PCFGQOS0_0_rqos_map_region0(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_region0_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_region0_MASK) #define DDRC_PCFGQOS0_0_rqos_map_region1_MASK (0x300000U) #define DDRC_PCFGQOS0_0_rqos_map_region1_SHIFT (20U) #define DDRC_PCFGQOS0_0_rqos_map_region1(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_region1_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_region1_MASK) /*! @} */ /*! @name PCFGQOS1_0 - Port n Read QoS Configuration Register 1 */ /*! @{ */ #define DDRC_PCFGQOS1_0_rqos_map_timeoutb_MASK (0x7FFU) #define DDRC_PCFGQOS1_0_rqos_map_timeoutb_SHIFT (0U) #define DDRC_PCFGQOS1_0_rqos_map_timeoutb(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS1_0_rqos_map_timeoutb_SHIFT)) & DDRC_PCFGQOS1_0_rqos_map_timeoutb_MASK) #define DDRC_PCFGQOS1_0_rqos_map_timeoutr_MASK (0x7FF0000U) #define DDRC_PCFGQOS1_0_rqos_map_timeoutr_SHIFT (16U) #define DDRC_PCFGQOS1_0_rqos_map_timeoutr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS1_0_rqos_map_timeoutr_SHIFT)) & DDRC_PCFGQOS1_0_rqos_map_timeoutr_MASK) /*! @} */ /*! @name PCFGWQOS0_0 - Port n Write QoS Configuration Register 0 */ /*! @{ */ #define DDRC_PCFGWQOS0_0_wqos_map_level_MASK (0xFU) #define DDRC_PCFGWQOS0_0_wqos_map_level_SHIFT (0U) #define DDRC_PCFGWQOS0_0_wqos_map_level(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_level_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_level_MASK) #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) #define DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT (16U) #define DDRC_PCFGWQOS0_0_wqos_map_region0(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK) #define DDRC_PCFGWQOS0_0_wqos_map_region1_MASK (0x300000U) #define DDRC_PCFGWQOS0_0_wqos_map_region1_SHIFT (20U) #define DDRC_PCFGWQOS0_0_wqos_map_region1(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region1_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region1_MASK) /*! @} */ /*! @name PCFGWQOS1_0 - Port n Write QoS Configuration Register 1 */ /*! @{ */ #define DDRC_PCFGWQOS1_0_wqos_map_timeout_MASK (0x7FFU) #define DDRC_PCFGWQOS1_0_wqos_map_timeout_SHIFT (0U) #define DDRC_PCFGWQOS1_0_wqos_map_timeout(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS1_0_wqos_map_timeout_SHIFT)) & DDRC_PCFGWQOS1_0_wqos_map_timeout_MASK) /*! @} */ /*! @name DERATEEN_SHADOW - [SHADOW] Temperature Derate Enable Register */ /*! @{ */ #define DDRC_DERATEEN_SHADOW_derate_enable_MASK (0x1U) #define DDRC_DERATEEN_SHADOW_derate_enable_SHIFT (0U) #define DDRC_DERATEEN_SHADOW_derate_enable(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_enable_SHIFT)) & \ DDRC_DERATEEN_SHADOW_derate_enable_MASK) #define DDRC_DERATEEN_SHADOW_derate_value_MASK (0x2U) #define DDRC_DERATEEN_SHADOW_derate_value_SHIFT (1U) #define DDRC_DERATEEN_SHADOW_derate_value(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_value_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_value_MASK) #define DDRC_DERATEEN_SHADOW_derate_byte_MASK (0xF0U) #define DDRC_DERATEEN_SHADOW_derate_byte_SHIFT (4U) #define DDRC_DERATEEN_SHADOW_derate_byte(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_byte_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_byte_MASK) #define DDRC_DERATEEN_SHADOW_rc_derate_value_MASK (0x300U) #define DDRC_DERATEEN_SHADOW_rc_derate_value_SHIFT (8U) #define DDRC_DERATEEN_SHADOW_rc_derate_value(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_rc_derate_value_SHIFT)) & \ DDRC_DERATEEN_SHADOW_rc_derate_value_MASK) /*! @} */ /*! @name DERATEINT_SHADOW - [SHADOW] Temperature Derate Interval Register */ /*! @{ */ #define DDRC_DERATEINT_SHADOW_mr4_read_interval_MASK (0xFFFFFFFFU) #define DDRC_DERATEINT_SHADOW_mr4_read_interval_SHIFT (0U) #define DDRC_DERATEINT_SHADOW_mr4_read_interval(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_SHADOW_mr4_read_interval_SHIFT)) & \ DDRC_DERATEINT_SHADOW_mr4_read_interval_MASK) /*! @} */ /*! @name RFSHCTL0_SHADOW - [SHADOW] Refresh Control Register 0 */ /*! @{ */ #define DDRC_RFSHCTL0_SHADOW_per_bank_refresh_MASK (0x4U) #define DDRC_RFSHCTL0_SHADOW_per_bank_refresh_SHIFT (2U) #define DDRC_RFSHCTL0_SHADOW_per_bank_refresh(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_per_bank_refresh_SHIFT)) & \ DDRC_RFSHCTL0_SHADOW_per_bank_refresh_MASK) #define DDRC_RFSHCTL0_SHADOW_refresh_burst_MASK (0x1F0U) #define DDRC_RFSHCTL0_SHADOW_refresh_burst_SHIFT (4U) #define DDRC_RFSHCTL0_SHADOW_refresh_burst(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_burst_SHIFT)) & \ DDRC_RFSHCTL0_SHADOW_refresh_burst_MASK) #define DDRC_RFSHCTL0_SHADOW_refresh_to_x32_MASK (0x1F000U) #define DDRC_RFSHCTL0_SHADOW_refresh_to_x32_SHIFT (12U) #define DDRC_RFSHCTL0_SHADOW_refresh_to_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_to_x32_SHIFT)) & \ DDRC_RFSHCTL0_SHADOW_refresh_to_x32_MASK) #define DDRC_RFSHCTL0_SHADOW_refresh_margin_MASK (0xF00000U) #define DDRC_RFSHCTL0_SHADOW_refresh_margin_SHIFT (20U) #define DDRC_RFSHCTL0_SHADOW_refresh_margin(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_margin_SHIFT)) & \ DDRC_RFSHCTL0_SHADOW_refresh_margin_MASK) /*! @} */ /*! @name RFSHTMG_SHADOW - [SHADOW] Refresh Timing Register */ /*! @{ */ #define DDRC_RFSHTMG_SHADOW_t_rfc_min_MASK (0x3FFU) #define DDRC_RFSHTMG_SHADOW_t_rfc_min_SHIFT (0U) #define DDRC_RFSHTMG_SHADOW_t_rfc_min(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_t_rfc_min_SHIFT)) & DDRC_RFSHTMG_SHADOW_t_rfc_min_MASK) #define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_MASK (0x8000U) #define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_SHIFT (15U) #define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_SHIFT)) & \ DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_MASK) #define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_MASK (0xFFF0000U) #define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_SHIFT (16U) #define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_SHIFT)) & DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_MASK) /*! @} */ /*! @name INIT3_SHADOW - [SHADOW] SDRAM Initialization Register 3 */ /*! @{ */ #define DDRC_INIT3_SHADOW_emr_MASK (0xFFFFU) #define DDRC_INIT3_SHADOW_emr_SHIFT (0U) #define DDRC_INIT3_SHADOW_emr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_SHADOW_emr_SHIFT)) & DDRC_INIT3_SHADOW_emr_MASK) #define DDRC_INIT3_SHADOW_mr_MASK (0xFFFF0000U) #define DDRC_INIT3_SHADOW_mr_SHIFT (16U) #define DDRC_INIT3_SHADOW_mr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_SHADOW_mr_SHIFT)) & DDRC_INIT3_SHADOW_mr_MASK) /*! @} */ /*! @name INIT4_SHADOW - [SHADOW] SDRAM Initialization Register 4 */ /*! @{ */ #define DDRC_INIT4_SHADOW_emr3_MASK (0xFFFFU) #define DDRC_INIT4_SHADOW_emr3_SHIFT (0U) #define DDRC_INIT4_SHADOW_emr3(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_SHADOW_emr3_SHIFT)) & DDRC_INIT4_SHADOW_emr3_MASK) #define DDRC_INIT4_SHADOW_emr2_MASK (0xFFFF0000U) #define DDRC_INIT4_SHADOW_emr2_SHIFT (16U) #define DDRC_INIT4_SHADOW_emr2(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_SHADOW_emr2_SHIFT)) & DDRC_INIT4_SHADOW_emr2_MASK) /*! @} */ /*! @name INIT6_SHADOW - [SHADOW] SDRAM Initialization Register 6 */ /*! @{ */ #define DDRC_INIT6_SHADOW_mr5_MASK (0xFFFFU) #define DDRC_INIT6_SHADOW_mr5_SHIFT (0U) #define DDRC_INIT6_SHADOW_mr5(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_SHADOW_mr5_SHIFT)) & DDRC_INIT6_SHADOW_mr5_MASK) #define DDRC_INIT6_SHADOW_mr4_MASK (0xFFFF0000U) #define DDRC_INIT6_SHADOW_mr4_SHIFT (16U) #define DDRC_INIT6_SHADOW_mr4(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_SHADOW_mr4_SHIFT)) & DDRC_INIT6_SHADOW_mr4_MASK) /*! @} */ /*! @name INIT7_SHADOW - [SHADOW] SDRAM Initialization Register 7 */ /*! @{ */ #define DDRC_INIT7_SHADOW_mr6_MASK (0xFFFF0000U) #define DDRC_INIT7_SHADOW_mr6_SHIFT (16U) #define DDRC_INIT7_SHADOW_mr6(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_SHADOW_mr6_SHIFT)) & DDRC_INIT7_SHADOW_mr6_MASK) /*! @} */ /*! @name DRAMTMG0_SHADOW - [SHADOW] SDRAM Timing Register 0 */ /*! @{ */ #define DDRC_DRAMTMG0_SHADOW_t_ras_min_MASK (0x3FU) #define DDRC_DRAMTMG0_SHADOW_t_ras_min_SHIFT (0U) #define DDRC_DRAMTMG0_SHADOW_t_ras_min(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_ras_min_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_ras_min_MASK) #define DDRC_DRAMTMG0_SHADOW_t_ras_max_MASK (0x7F00U) #define DDRC_DRAMTMG0_SHADOW_t_ras_max_SHIFT (8U) #define DDRC_DRAMTMG0_SHADOW_t_ras_max(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_ras_max_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_ras_max_MASK) #define DDRC_DRAMTMG0_SHADOW_t_faw_MASK (0x3F0000U) #define DDRC_DRAMTMG0_SHADOW_t_faw_SHIFT (16U) #define DDRC_DRAMTMG0_SHADOW_t_faw(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_faw_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_faw_MASK) #define DDRC_DRAMTMG0_SHADOW_wr2pre_MASK (0x7F000000U) #define DDRC_DRAMTMG0_SHADOW_wr2pre_SHIFT (24U) #define DDRC_DRAMTMG0_SHADOW_wr2pre(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_wr2pre_SHIFT)) & DDRC_DRAMTMG0_SHADOW_wr2pre_MASK) /*! @} */ /*! @name DRAMTMG1_SHADOW - [SHADOW] SDRAM Timing Register 1 */ /*! @{ */ #define DDRC_DRAMTMG1_SHADOW_t_rc_MASK (0x7FU) #define DDRC_DRAMTMG1_SHADOW_t_rc_SHIFT (0U) #define DDRC_DRAMTMG1_SHADOW_t_rc(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_t_rc_SHIFT)) & DDRC_DRAMTMG1_SHADOW_t_rc_MASK) #define DDRC_DRAMTMG1_SHADOW_rd2pre_MASK (0x3F00U) #define DDRC_DRAMTMG1_SHADOW_rd2pre_SHIFT (8U) #define DDRC_DRAMTMG1_SHADOW_rd2pre(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_rd2pre_SHIFT)) & DDRC_DRAMTMG1_SHADOW_rd2pre_MASK) #define DDRC_DRAMTMG1_SHADOW_t_xp_MASK (0x1F0000U) #define DDRC_DRAMTMG1_SHADOW_t_xp_SHIFT (16U) #define DDRC_DRAMTMG1_SHADOW_t_xp(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_t_xp_SHIFT)) & DDRC_DRAMTMG1_SHADOW_t_xp_MASK) /*! @} */ /*! @name DRAMTMG2_SHADOW - [SHADOW] SDRAM Timing Register 2 */ /*! @{ */ #define DDRC_DRAMTMG2_SHADOW_wr2rd_MASK (0x3FU) #define DDRC_DRAMTMG2_SHADOW_wr2rd_SHIFT (0U) #define DDRC_DRAMTMG2_SHADOW_wr2rd(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_wr2rd_SHIFT)) & DDRC_DRAMTMG2_SHADOW_wr2rd_MASK) #define DDRC_DRAMTMG2_SHADOW_rd2wr_MASK (0x3F00U) #define DDRC_DRAMTMG2_SHADOW_rd2wr_SHIFT (8U) #define DDRC_DRAMTMG2_SHADOW_rd2wr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_rd2wr_SHIFT)) & DDRC_DRAMTMG2_SHADOW_rd2wr_MASK) #define DDRC_DRAMTMG2_SHADOW_read_latency_MASK (0x3F0000U) #define DDRC_DRAMTMG2_SHADOW_read_latency_SHIFT (16U) #define DDRC_DRAMTMG2_SHADOW_read_latency(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_read_latency_SHIFT)) & DDRC_DRAMTMG2_SHADOW_read_latency_MASK) #define DDRC_DRAMTMG2_SHADOW_write_latency_MASK (0x3F000000U) #define DDRC_DRAMTMG2_SHADOW_write_latency_SHIFT (24U) #define DDRC_DRAMTMG2_SHADOW_write_latency(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_write_latency_SHIFT)) & \ DDRC_DRAMTMG2_SHADOW_write_latency_MASK) /*! @} */ /*! @name DRAMTMG3_SHADOW - [SHADOW] SDRAM Timing Register 3 */ /*! @{ */ #define DDRC_DRAMTMG3_SHADOW_t_mod_MASK (0x3FFU) #define DDRC_DRAMTMG3_SHADOW_t_mod_SHIFT (0U) #define DDRC_DRAMTMG3_SHADOW_t_mod(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mod_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mod_MASK) #define DDRC_DRAMTMG3_SHADOW_t_mrd_MASK (0x3F000U) #define DDRC_DRAMTMG3_SHADOW_t_mrd_SHIFT (12U) #define DDRC_DRAMTMG3_SHADOW_t_mrd(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mrd_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mrd_MASK) #define DDRC_DRAMTMG3_SHADOW_t_mrw_MASK (0x3FF00000U) #define DDRC_DRAMTMG3_SHADOW_t_mrw_SHIFT (20U) #define DDRC_DRAMTMG3_SHADOW_t_mrw(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mrw_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mrw_MASK) /*! @} */ /*! @name DRAMTMG4_SHADOW - [SHADOW] SDRAM Timing Register 4 */ /*! @{ */ #define DDRC_DRAMTMG4_SHADOW_t_rp_MASK (0x1FU) #define DDRC_DRAMTMG4_SHADOW_t_rp_SHIFT (0U) #define DDRC_DRAMTMG4_SHADOW_t_rp(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rp_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rp_MASK) #define DDRC_DRAMTMG4_SHADOW_t_rrd_MASK (0xF00U) #define DDRC_DRAMTMG4_SHADOW_t_rrd_SHIFT (8U) #define DDRC_DRAMTMG4_SHADOW_t_rrd(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rrd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rrd_MASK) #define DDRC_DRAMTMG4_SHADOW_t_ccd_MASK (0xF0000U) #define DDRC_DRAMTMG4_SHADOW_t_ccd_SHIFT (16U) #define DDRC_DRAMTMG4_SHADOW_t_ccd(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_ccd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_ccd_MASK) #define DDRC_DRAMTMG4_SHADOW_t_rcd_MASK (0x1F000000U) #define DDRC_DRAMTMG4_SHADOW_t_rcd_SHIFT (24U) #define DDRC_DRAMTMG4_SHADOW_t_rcd(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rcd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rcd_MASK) /*! @} */ /*! @name DRAMTMG5_SHADOW - [SHADOW] SDRAM Timing Register 5 */ /*! @{ */ #define DDRC_DRAMTMG5_SHADOW_t_cke_MASK (0x1FU) #define DDRC_DRAMTMG5_SHADOW_t_cke_SHIFT (0U) #define DDRC_DRAMTMG5_SHADOW_t_cke(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cke_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cke_MASK) #define DDRC_DRAMTMG5_SHADOW_t_ckesr_MASK (0x3F00U) #define DDRC_DRAMTMG5_SHADOW_t_ckesr_SHIFT (8U) #define DDRC_DRAMTMG5_SHADOW_t_ckesr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_ckesr_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_ckesr_MASK) #define DDRC_DRAMTMG5_SHADOW_t_cksre_MASK (0xF0000U) #define DDRC_DRAMTMG5_SHADOW_t_cksre_SHIFT (16U) #define DDRC_DRAMTMG5_SHADOW_t_cksre(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cksre_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cksre_MASK) #define DDRC_DRAMTMG5_SHADOW_t_cksrx_MASK (0xF000000U) #define DDRC_DRAMTMG5_SHADOW_t_cksrx_SHIFT (24U) #define DDRC_DRAMTMG5_SHADOW_t_cksrx(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cksrx_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cksrx_MASK) /*! @} */ /*! @name DRAMTMG6_SHADOW - [SHADOW] SDRAM Timing Register 6 */ /*! @{ */ #define DDRC_DRAMTMG6_SHADOW_t_ckcsx_MASK (0xFU) #define DDRC_DRAMTMG6_SHADOW_t_ckcsx_SHIFT (0U) #define DDRC_DRAMTMG6_SHADOW_t_ckcsx(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckcsx_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckcsx_MASK) #define DDRC_DRAMTMG6_SHADOW_t_ckdpdx_MASK (0xF0000U) #define DDRC_DRAMTMG6_SHADOW_t_ckdpdx_SHIFT (16U) #define DDRC_DRAMTMG6_SHADOW_t_ckdpdx(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckdpdx_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckdpdx_MASK) #define DDRC_DRAMTMG6_SHADOW_t_ckdpde_MASK (0xF000000U) #define DDRC_DRAMTMG6_SHADOW_t_ckdpde_SHIFT (24U) #define DDRC_DRAMTMG6_SHADOW_t_ckdpde(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckdpde_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckdpde_MASK) /*! @} */ /*! @name DRAMTMG7_SHADOW - [SHADOW] SDRAM Timing Register 7 */ /*! @{ */ #define DDRC_DRAMTMG7_SHADOW_t_ckpdx_MASK (0xFU) #define DDRC_DRAMTMG7_SHADOW_t_ckpdx_SHIFT (0U) #define DDRC_DRAMTMG7_SHADOW_t_ckpdx(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_SHADOW_t_ckpdx_SHIFT)) & DDRC_DRAMTMG7_SHADOW_t_ckpdx_MASK) #define DDRC_DRAMTMG7_SHADOW_t_ckpde_MASK (0xF00U) #define DDRC_DRAMTMG7_SHADOW_t_ckpde_SHIFT (8U) #define DDRC_DRAMTMG7_SHADOW_t_ckpde(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_SHADOW_t_ckpde_SHIFT)) & DDRC_DRAMTMG7_SHADOW_t_ckpde_MASK) /*! @} */ /*! @name DRAMTMG8_SHADOW - [SHADOW] SDRAM Timing Register 8 */ /*! @{ */ #define DDRC_DRAMTMG8_SHADOW_t_xs_x32_MASK (0x7FU) #define DDRC_DRAMTMG8_SHADOW_t_xs_x32_SHIFT (0U) #define DDRC_DRAMTMG8_SHADOW_t_xs_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_x32_MASK) #define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_MASK (0x7F00U) #define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_SHIFT (8U) #define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_MASK) #define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_MASK (0x7F0000U) #define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_SHIFT (16U) #define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_SHIFT)) & \ DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_MASK) #define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_MASK (0x7F000000U) #define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_SHIFT (24U) #define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_SHIFT)) & \ DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_MASK) /*! @} */ /*! @name DRAMTMG9_SHADOW - [SHADOW] SDRAM Timing Register 9 */ /*! @{ */ #define DDRC_DRAMTMG9_SHADOW_wr2rd_s_MASK (0x3FU) #define DDRC_DRAMTMG9_SHADOW_wr2rd_s_SHIFT (0U) #define DDRC_DRAMTMG9_SHADOW_wr2rd_s(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_wr2rd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_wr2rd_s_MASK) #define DDRC_DRAMTMG9_SHADOW_t_rrd_s_MASK (0xF00U) #define DDRC_DRAMTMG9_SHADOW_t_rrd_s_SHIFT (8U) #define DDRC_DRAMTMG9_SHADOW_t_rrd_s(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_t_rrd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_t_rrd_s_MASK) #define DDRC_DRAMTMG9_SHADOW_t_ccd_s_MASK (0x70000U) #define DDRC_DRAMTMG9_SHADOW_t_ccd_s_SHIFT (16U) #define DDRC_DRAMTMG9_SHADOW_t_ccd_s(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_t_ccd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_t_ccd_s_MASK) #define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_MASK (0x40000000U) #define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_SHIFT (30U) #define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_SHIFT)) & \ DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_MASK) /*! @} */ /*! @name DRAMTMG10_SHADOW - [SHADOW] SDRAM Timing Register 10 */ /*! @{ */ #define DDRC_DRAMTMG10_SHADOW_t_gear_hold_MASK (0x3U) #define DDRC_DRAMTMG10_SHADOW_t_gear_hold_SHIFT (0U) #define DDRC_DRAMTMG10_SHADOW_t_gear_hold(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_gear_hold_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_gear_hold_MASK) #define DDRC_DRAMTMG10_SHADOW_t_gear_setup_MASK (0xCU) #define DDRC_DRAMTMG10_SHADOW_t_gear_setup_SHIFT (2U) #define DDRC_DRAMTMG10_SHADOW_t_gear_setup(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_gear_setup_SHIFT)) & \ DDRC_DRAMTMG10_SHADOW_t_gear_setup_MASK) #define DDRC_DRAMTMG10_SHADOW_t_cmd_gear_MASK (0x1F00U) #define DDRC_DRAMTMG10_SHADOW_t_cmd_gear_SHIFT (8U) #define DDRC_DRAMTMG10_SHADOW_t_cmd_gear(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_cmd_gear_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_cmd_gear_MASK) #define DDRC_DRAMTMG10_SHADOW_t_sync_gear_MASK (0x1F0000U) #define DDRC_DRAMTMG10_SHADOW_t_sync_gear_SHIFT (16U) #define DDRC_DRAMTMG10_SHADOW_t_sync_gear(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_sync_gear_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_sync_gear_MASK) /*! @} */ /*! @name DRAMTMG11_SHADOW - [SHADOW] SDRAM Timing Register 11 */ /*! @{ */ #define DDRC_DRAMTMG11_SHADOW_t_ckmpe_MASK (0x1FU) #define DDRC_DRAMTMG11_SHADOW_t_ckmpe_SHIFT (0U) #define DDRC_DRAMTMG11_SHADOW_t_ckmpe(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_ckmpe_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_ckmpe_MASK) #define DDRC_DRAMTMG11_SHADOW_t_mpx_s_MASK (0x300U) #define DDRC_DRAMTMG11_SHADOW_t_mpx_s_SHIFT (8U) #define DDRC_DRAMTMG11_SHADOW_t_mpx_s(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_mpx_s_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_mpx_s_MASK) #define DDRC_DRAMTMG11_SHADOW_t_mpx_lh_MASK (0x1F0000U) #define DDRC_DRAMTMG11_SHADOW_t_mpx_lh_SHIFT (16U) #define DDRC_DRAMTMG11_SHADOW_t_mpx_lh(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_mpx_lh_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_mpx_lh_MASK) #define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_MASK (0x7F000000U) #define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_SHIFT (24U) #define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_SHIFT)) & \ DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_MASK) /*! @} */ /*! @name DRAMTMG12_SHADOW - [SHADOW] SDRAM Timing Register 12 */ /*! @{ */ #define DDRC_DRAMTMG12_SHADOW_t_mrd_pda_MASK (0x1FU) #define DDRC_DRAMTMG12_SHADOW_t_mrd_pda_SHIFT (0U) #define DDRC_DRAMTMG12_SHADOW_t_mrd_pda(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_mrd_pda_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_mrd_pda_MASK) #define DDRC_DRAMTMG12_SHADOW_t_ckehcmd_MASK (0xF00U) #define DDRC_DRAMTMG12_SHADOW_t_ckehcmd_SHIFT (8U) #define DDRC_DRAMTMG12_SHADOW_t_ckehcmd(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_ckehcmd_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_ckehcmd_MASK) #define DDRC_DRAMTMG12_SHADOW_t_cmdcke_MASK (0x30000U) #define DDRC_DRAMTMG12_SHADOW_t_cmdcke_SHIFT (16U) #define DDRC_DRAMTMG12_SHADOW_t_cmdcke(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_cmdcke_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_cmdcke_MASK) /*! @} */ /*! @name DRAMTMG13_SHADOW - [SHADOW] SDRAM Timing Register 13 */ /*! @{ */ #define DDRC_DRAMTMG13_SHADOW_t_ppd_MASK (0x7U) #define DDRC_DRAMTMG13_SHADOW_t_ppd_SHIFT (0U) #define DDRC_DRAMTMG13_SHADOW_t_ppd(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_t_ppd_SHIFT)) & DDRC_DRAMTMG13_SHADOW_t_ppd_MASK) #define DDRC_DRAMTMG13_SHADOW_t_ccd_mw_MASK (0x3F0000U) #define DDRC_DRAMTMG13_SHADOW_t_ccd_mw_SHIFT (16U) #define DDRC_DRAMTMG13_SHADOW_t_ccd_mw(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_t_ccd_mw_SHIFT)) & DDRC_DRAMTMG13_SHADOW_t_ccd_mw_MASK) #define DDRC_DRAMTMG13_SHADOW_odtloff_MASK (0x7F000000U) #define DDRC_DRAMTMG13_SHADOW_odtloff_SHIFT (24U) #define DDRC_DRAMTMG13_SHADOW_odtloff(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_odtloff_SHIFT)) & DDRC_DRAMTMG13_SHADOW_odtloff_MASK) /*! @} */ /*! @name DRAMTMG14_SHADOW - [SHADOW] SDRAM Timing Register 14 */ /*! @{ */ #define DDRC_DRAMTMG14_SHADOW_t_xsr_MASK (0xFFFU) #define DDRC_DRAMTMG14_SHADOW_t_xsr_SHIFT (0U) #define DDRC_DRAMTMG14_SHADOW_t_xsr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_SHADOW_t_xsr_SHIFT)) & DDRC_DRAMTMG14_SHADOW_t_xsr_MASK) /*! @} */ /*! @name DRAMTMG15_SHADOW - [SHADOW] SDRAM Timing Register 15 */ /*! @{ */ #define DDRC_DRAMTMG15_SHADOW_t_stab_x32_MASK (0xFFU) #define DDRC_DRAMTMG15_SHADOW_t_stab_x32_SHIFT (0U) #define DDRC_DRAMTMG15_SHADOW_t_stab_x32(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_SHADOW_t_stab_x32_SHIFT)) & DDRC_DRAMTMG15_SHADOW_t_stab_x32_MASK) #define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_MASK (0x80000000U) #define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_SHIFT (31U) #define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_SHIFT)) & \ DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_MASK) /*! @} */ /*! @name ZQCTL0_SHADOW - [SHADOW] ZQ Control Register 0 */ /*! @{ */ #define DDRC_ZQCTL0_SHADOW_t_zq_short_nop_MASK (0x3FFU) #define DDRC_ZQCTL0_SHADOW_t_zq_short_nop_SHIFT (0U) #define DDRC_ZQCTL0_SHADOW_t_zq_short_nop(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_t_zq_short_nop_SHIFT)) & DDRC_ZQCTL0_SHADOW_t_zq_short_nop_MASK) #define DDRC_ZQCTL0_SHADOW_t_zq_long_nop_MASK (0x7FF0000U) #define DDRC_ZQCTL0_SHADOW_t_zq_long_nop_SHIFT (16U) #define DDRC_ZQCTL0_SHADOW_t_zq_long_nop(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_t_zq_long_nop_SHIFT)) & DDRC_ZQCTL0_SHADOW_t_zq_long_nop_MASK) #define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_MASK (0x10000000U) #define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_SHIFT (28U) #define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_MASK) #define DDRC_ZQCTL0_SHADOW_zq_resistor_shared_MASK (0x20000000U) #define DDRC_ZQCTL0_SHADOW_zq_resistor_shared_SHIFT (29U) #define DDRC_ZQCTL0_SHADOW_zq_resistor_shared(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_zq_resistor_shared_SHIFT)) & \ DDRC_ZQCTL0_SHADOW_zq_resistor_shared_MASK) #define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_MASK (0x40000000U) #define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_SHIFT (30U) #define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_MASK) #define DDRC_ZQCTL0_SHADOW_dis_auto_zq_MASK (0x80000000U) #define DDRC_ZQCTL0_SHADOW_dis_auto_zq_SHIFT (31U) #define DDRC_ZQCTL0_SHADOW_dis_auto_zq(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_auto_zq_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_auto_zq_MASK) /*! @} */ /*! @name DFITMG0_SHADOW - [SHADOW] DFI Timing Register 0 */ /*! @{ */ #define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_MASK (0x3FU) #define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_SHIFT (0U) #define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_SHIFT)) & \ DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_MASK) #define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_MASK (0x3F00U) #define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_SHIFT (8U) #define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_SHIFT)) & \ DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_MASK) #define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_MASK (0x8000U) #define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_SHIFT (15U) #define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_SHIFT)) & \ DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_MASK) #define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_MASK (0x7F0000U) #define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_SHIFT (16U) #define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_SHIFT)) & \ DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_MASK) #define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_MASK (0x800000U) #define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_SHIFT (23U) #define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_SHIFT)) & \ DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_MASK) #define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_MASK (0x1F000000U) #define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_SHIFT (24U) #define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_SHIFT)) & \ DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_MASK) /*! @} */ /*! @name DFITMG1_SHADOW - [SHADOW] DFI Timing Register 1 */ /*! @{ */ #define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_MASK (0x1FU) #define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_SHIFT (0U) #define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_SHIFT)) & \ DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_MASK) #define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_MASK (0x1F00U) #define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_SHIFT (8U) #define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_SHIFT)) & \ DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_MASK) #define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_MASK (0x1F0000U) #define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_SHIFT (16U) #define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_SHIFT)) & \ DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_MASK) #define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_MASK (0x3000000U) #define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_SHIFT (24U) #define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_SHIFT)) & \ DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_MASK) #define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_MASK (0xF0000000U) #define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_SHIFT (28U) #define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_MASK) /*! @} */ /*! @name DFITMG2_SHADOW - [SHADOW] DFI Timing Register 2 */ /*! @{ */ #define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_MASK (0x3FU) #define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_SHIFT (0U) #define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_SHIFT)) & \ DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_MASK) #define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_MASK (0x7F00U) #define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_SHIFT (8U) #define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_SHIFT)) & \ DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_MASK) /*! @} */ /*! @name DFITMG3_SHADOW - [SHADOW] DFI Timing Register 3 */ /*! @{ */ #define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_MASK (0x1FU) #define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_SHIFT (0U) #define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_SHIFT)) & \ DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_MASK) /*! @} */ /*! @name ODTCFG_SHADOW - [SHADOW] ODT Configuration Register */ /*! @{ */ #define DDRC_ODTCFG_SHADOW_rd_odt_delay_MASK (0x7CU) #define DDRC_ODTCFG_SHADOW_rd_odt_delay_SHIFT (2U) #define DDRC_ODTCFG_SHADOW_rd_odt_delay(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_rd_odt_delay_SHIFT)) & DDRC_ODTCFG_SHADOW_rd_odt_delay_MASK) #define DDRC_ODTCFG_SHADOW_rd_odt_hold_MASK (0xF00U) #define DDRC_ODTCFG_SHADOW_rd_odt_hold_SHIFT (8U) #define DDRC_ODTCFG_SHADOW_rd_odt_hold(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_rd_odt_hold_SHIFT)) & DDRC_ODTCFG_SHADOW_rd_odt_hold_MASK) #define DDRC_ODTCFG_SHADOW_wr_odt_delay_MASK (0x1F0000U) #define DDRC_ODTCFG_SHADOW_wr_odt_delay_SHIFT (16U) #define DDRC_ODTCFG_SHADOW_wr_odt_delay(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_wr_odt_delay_SHIFT)) & DDRC_ODTCFG_SHADOW_wr_odt_delay_MASK) #define DDRC_ODTCFG_SHADOW_wr_odt_hold_MASK (0xF000000U) #define DDRC_ODTCFG_SHADOW_wr_odt_hold_SHIFT (24U) #define DDRC_ODTCFG_SHADOW_wr_odt_hold(x) \ (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_wr_odt_hold_SHIFT)) & DDRC_ODTCFG_SHADOW_wr_odt_hold_MASK) /*! @} */ /*! * @} */ /* end of group DDRC_Register_Masks */ /* DDRC - Peripheral instance base addresses */ /** Peripheral DDRC base address */ #define DDRC_BASE (0x3D400000u) /** Peripheral DDRC base pointer */ #define DDRC ((DDRC_Type *)DDRC_BASE) /** Array initializer of DDRC peripheral base addresses */ #define DDRC_BASE_ADDRS \ { \ DDRC_BASE \ } /** Array initializer of DDRC peripheral base pointers */ #define DDRC_BASE_PTRS \ { \ DDRC \ } /*! * @} */ /* end of group DDRC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DWC_DDRPHYA_ANIB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DWC_DDRPHYA_ANIB_Peripheral_Access_Layer DWC_DDRPHYA_ANIB Peripheral Access Layer * @{ */ /** DWC_DDRPHYA_ANIB - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[52]; __IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x34 */ uint8_t RESERVED_1[24]; __IO uint16_t AFORCEDRVCONT; /**< Force Address/Command Driven (Lanes A3-A0), offset: 0x4E */ __IO uint16_t AFORCETRICONT; /**< Force Address/Command Tristate (Lanes A3-A0), offset: 0x50 */ uint8_t RESERVED_2[52]; __IO uint16_t ATXIMPEDANCE; /**< Address TX impedance controls, offset: 0x86 */ uint8_t RESERVED_3[30]; __I uint16_t ATESTPRBSERR; /**< Address Loopback PRBS Error status for an entire ACX4 block, offset: 0xA6 */ uint8_t RESERVED_4[2]; __IO uint16_t ATXSLEWRATE; /**< Address TX slew rate and predriver controls, offset: 0xAA */ __I uint16_t ATESTPRBSERRCNT; /**< Address Loopback Test Result register, offset: 0xAC */ uint8_t RESERVED_5[82]; __IO uint16_t ATXDLY_P0; /**< Address/Command Delay, per pstate., offset: 0x100 */ uint8_t RESERVED_6[2097150]; __IO uint16_t ATXDLY_P1; /**< Address/Command Delay, per pstate., offset: 0x200100 */ uint8_t RESERVED_7[2097150]; __IO uint16_t ATXDLY_P2; /**< Address/Command Delay, per pstate., offset: 0x400100 */ uint8_t RESERVED_8[2097150]; __IO uint16_t ATXDLY_P3; /**< Address/Command Delay, per pstate., offset: 0x600100 */ } DWC_DDRPHYA_ANIB_Type; /* ---------------------------------------------------------------------------- -- DWC_DDRPHYA_ANIB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DWC_DDRPHYA_ANIB_Register_Masks DWC_DDRPHYA_ANIB Register Masks * @{ */ /*! @name MTESTMUXSEL - Digital Observation Pin control */ /*! @{ */ #define DWC_DDRPHYA_ANIB_MTESTMUXSEL_MtestMuxSel_MASK (0x3FU) #define DWC_DDRPHYA_ANIB_MTESTMUXSEL_MtestMuxSel_SHIFT (0U) #define DWC_DDRPHYA_ANIB_MTESTMUXSEL_MtestMuxSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_MTESTMUXSEL_MtestMuxSel_SHIFT)) & \ DWC_DDRPHYA_ANIB_MTESTMUXSEL_MtestMuxSel_MASK) /*! @} */ /*! @name AFORCEDRVCONT - Force Address/Command Driven (Lanes A3-A0) */ /*! @{ */ #define DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AForceDrvCont_MASK (0xFU) #define DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AForceDrvCont_SHIFT (0U) #define DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AForceDrvCont(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AForceDrvCont_SHIFT)) & \ DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AForceDrvCont_MASK) /*! @} */ /*! @name AFORCETRICONT - Force Address/Command Tristate (Lanes A3-A0) */ /*! @{ */ #define DWC_DDRPHYA_ANIB_AFORCETRICONT_AForceTriCont_MASK (0xFU) #define DWC_DDRPHYA_ANIB_AFORCETRICONT_AForceTriCont_SHIFT (0U) #define DWC_DDRPHYA_ANIB_AFORCETRICONT_AForceTriCont(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_AFORCETRICONT_AForceTriCont_SHIFT)) & \ DWC_DDRPHYA_ANIB_AFORCETRICONT_AForceTriCont_MASK) /*! @} */ /*! @name ATXIMPEDANCE - Address TX impedance controls */ /*! @{ */ #define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenP_MASK (0x1FU) #define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenP_SHIFT (0U) #define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenP_SHIFT)) & \ DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenP_MASK) #define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenN_MASK (0x3E0U) #define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenN_SHIFT (5U) #define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenN_SHIFT)) & \ DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenN_MASK) /*! @} */ /*! @name ATESTPRBSERR - Address Loopback PRBS Error status for an entire ACX4 block */ /*! @{ */ #define DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATestPrbsErr_MASK (0xFU) #define DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATestPrbsErr_SHIFT (0U) #define DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATestPrbsErr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATestPrbsErr_SHIFT)) & \ DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATestPrbsErr_MASK) /*! @} */ /*! @name ATXSLEWRATE - Address TX slew rate and predriver controls */ /*! @{ */ #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreP_MASK (0xFU) #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreP_SHIFT (0U) #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreP_SHIFT)) & \ DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreP_MASK) #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreN_MASK (0xF0U) #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreN_SHIFT (4U) #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreN_SHIFT)) & \ DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreN_MASK) #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreDrvMode_MASK (0x700U) #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreDrvMode_SHIFT (8U) #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreDrvMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreDrvMode_SHIFT)) & \ DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreDrvMode_MASK) /*! @} */ /*! @name ATESTPRBSERRCNT - Address Loopback Test Result register */ /*! @{ */ #define DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATestPrbsErrCnt_MASK (0xFFFFU) #define DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATestPrbsErrCnt_SHIFT (0U) #define DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATestPrbsErrCnt(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATestPrbsErrCnt_SHIFT)) & \ DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATestPrbsErrCnt_MASK) /*! @} */ /*! @name ATXDLY_P0 - Address/Command Delay, per pstate. */ /*! @{ */ #define DWC_DDRPHYA_ANIB_ATXDLY_P0_ATxDly_p0_MASK (0x7FU) #define DWC_DDRPHYA_ANIB_ATXDLY_P0_ATxDly_p0_SHIFT (0U) #define DWC_DDRPHYA_ANIB_ATXDLY_P0_ATxDly_p0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P0_ATxDly_p0_SHIFT)) & \ DWC_DDRPHYA_ANIB_ATXDLY_P0_ATxDly_p0_MASK) /*! @} */ /*! @name ATXDLY_P1 - Address/Command Delay, per pstate. */ /*! @{ */ #define DWC_DDRPHYA_ANIB_ATXDLY_P1_ATxDly_p1_MASK (0x7FU) #define DWC_DDRPHYA_ANIB_ATXDLY_P1_ATxDly_p1_SHIFT (0U) #define DWC_DDRPHYA_ANIB_ATXDLY_P1_ATxDly_p1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P1_ATxDly_p1_SHIFT)) & \ DWC_DDRPHYA_ANIB_ATXDLY_P1_ATxDly_p1_MASK) /*! @} */ /*! @name ATXDLY_P2 - Address/Command Delay, per pstate. */ /*! @{ */ #define DWC_DDRPHYA_ANIB_ATXDLY_P2_ATxDly_p2_MASK (0x7FU) #define DWC_DDRPHYA_ANIB_ATXDLY_P2_ATxDly_p2_SHIFT (0U) #define DWC_DDRPHYA_ANIB_ATXDLY_P2_ATxDly_p2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P2_ATxDly_p2_SHIFT)) & \ DWC_DDRPHYA_ANIB_ATXDLY_P2_ATxDly_p2_MASK) /*! @} */ /*! @name ATXDLY_P3 - Address/Command Delay, per pstate. */ /*! @{ */ #define DWC_DDRPHYA_ANIB_ATXDLY_P3_ATxDly_p3_MASK (0x7FU) #define DWC_DDRPHYA_ANIB_ATXDLY_P3_ATxDly_p3_SHIFT (0U) #define DWC_DDRPHYA_ANIB_ATXDLY_P3_ATxDly_p3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P3_ATxDly_p3_SHIFT)) & \ DWC_DDRPHYA_ANIB_ATXDLY_P3_ATxDly_p3_MASK) /*! @} */ /*! * @} */ /* end of group DWC_DDRPHYA_ANIB_Register_Masks */ /* DWC_DDRPHYA_ANIB - Peripheral instance base addresses */ /** Peripheral DWC_DDRPHYA_ANIB0 base address */ #define DWC_DDRPHYA_ANIB0_BASE (0x3C000000u) /** Peripheral DWC_DDRPHYA_ANIB0 base pointer */ #define DWC_DDRPHYA_ANIB0 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB0_BASE) /** Peripheral DWC_DDRPHYA_ANIB1 base address */ #define DWC_DDRPHYA_ANIB1_BASE (0x3C001000u) /** Peripheral DWC_DDRPHYA_ANIB1 base pointer */ #define DWC_DDRPHYA_ANIB1 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB1_BASE) /** Peripheral DWC_DDRPHYA_ANIB2 base address */ #define DWC_DDRPHYA_ANIB2_BASE (0x3C002000u) /** Peripheral DWC_DDRPHYA_ANIB2 base pointer */ #define DWC_DDRPHYA_ANIB2 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB2_BASE) /** Peripheral DWC_DDRPHYA_ANIB3 base address */ #define DWC_DDRPHYA_ANIB3_BASE (0x3C003000u) /** Peripheral DWC_DDRPHYA_ANIB3 base pointer */ #define DWC_DDRPHYA_ANIB3 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB3_BASE) /** Peripheral DWC_DDRPHYA_ANIB4 base address */ #define DWC_DDRPHYA_ANIB4_BASE (0x3C004000u) /** Peripheral DWC_DDRPHYA_ANIB4 base pointer */ #define DWC_DDRPHYA_ANIB4 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB4_BASE) /** Peripheral DWC_DDRPHYA_ANIB5 base address */ #define DWC_DDRPHYA_ANIB5_BASE (0x3C005000u) /** Peripheral DWC_DDRPHYA_ANIB5 base pointer */ #define DWC_DDRPHYA_ANIB5 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB5_BASE) /** Peripheral DWC_DDRPHYA_ANIB6 base address */ #define DWC_DDRPHYA_ANIB6_BASE (0x3C006000u) /** Peripheral DWC_DDRPHYA_ANIB6 base pointer */ #define DWC_DDRPHYA_ANIB6 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB6_BASE) /** Peripheral DWC_DDRPHYA_ANIB7 base address */ #define DWC_DDRPHYA_ANIB7_BASE (0x3C007000u) /** Peripheral DWC_DDRPHYA_ANIB7 base pointer */ #define DWC_DDRPHYA_ANIB7 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB7_BASE) /** Peripheral DWC_DDRPHYA_ANIB8 base address */ #define DWC_DDRPHYA_ANIB8_BASE (0x3C008000u) /** Peripheral DWC_DDRPHYA_ANIB8 base pointer */ #define DWC_DDRPHYA_ANIB8 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB8_BASE) /** Peripheral DWC_DDRPHYA_ANIB9 base address */ #define DWC_DDRPHYA_ANIB9_BASE (0x3C009000u) /** Peripheral DWC_DDRPHYA_ANIB9 base pointer */ #define DWC_DDRPHYA_ANIB9 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB9_BASE) /** Array initializer of DWC_DDRPHYA_ANIB peripheral base addresses */ #define DWC_DDRPHYA_ANIB_BASE_ADDRS \ { \ DWC_DDRPHYA_ANIB0_BASE, DWC_DDRPHYA_ANIB1_BASE, DWC_DDRPHYA_ANIB2_BASE, DWC_DDRPHYA_ANIB3_BASE, \ DWC_DDRPHYA_ANIB4_BASE, DWC_DDRPHYA_ANIB5_BASE, DWC_DDRPHYA_ANIB6_BASE, DWC_DDRPHYA_ANIB7_BASE, \ DWC_DDRPHYA_ANIB8_BASE, DWC_DDRPHYA_ANIB9_BASE \ } /** Array initializer of DWC_DDRPHYA_ANIB peripheral base pointers */ #define DWC_DDRPHYA_ANIB_BASE_PTRS \ { \ DWC_DDRPHYA_ANIB0, DWC_DDRPHYA_ANIB1, DWC_DDRPHYA_ANIB2, DWC_DDRPHYA_ANIB3, DWC_DDRPHYA_ANIB4, \ DWC_DDRPHYA_ANIB5, DWC_DDRPHYA_ANIB6, DWC_DDRPHYA_ANIB7, DWC_DDRPHYA_ANIB8, DWC_DDRPHYA_ANIB9 \ } /*! * @} */ /* end of group DWC_DDRPHYA_ANIB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DWC_DDRPHYA_APBONLY Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DWC_DDRPHYA_APBONLY_Peripheral_Access_Layer DWC_DDRPHYA_APBONLY Peripheral Access Layer * @{ */ /** DWC_DDRPHYA_APBONLY - Register Layout Typedef */ typedef struct { __IO uint16_t MICROCONTMUXSEL; /**< PMU Config Mux Select, offset: 0x0 */ uint8_t RESERVED_0[6]; __I uint16_t UCTSHADOWREGS; /**< PMU/Controller Protocol - Controller Read-only Shadow, offset: 0x8 */ uint8_t RESERVED_1[86]; __IO uint16_t DCTWRITEONLY; /**< Reserved for future use., offset: 0x60 */ __IO uint16_t DCTWRITEPROT; /**< DCT downstream mailbox protocol CSR., offset: 0x62 */ __I uint16_t UCTWRITEONLYSHADOW; /**< Read-only view of the csr UctDatWriteOnly, offset: 0x64 */ uint8_t RESERVED_2[2]; __I uint16_t UCTDATWRITEONLYSHADOW; /**< Read-only view of the csr UctDatWriteOnly, offset: 0x68 */ uint8_t RESERVED_3[4]; __IO uint16_t DFICFGRDDATAVALIDTICKS; /**< Number of DfiClk ticks required for valid csr Rd Data., offset: 0x6E */ uint8_t RESERVED_4[194]; __IO uint16_t MICRORESET; /**< Controls reset and clock shutdown on the local microcontroller, offset: 0x132 */ uint8_t RESERVED_5[192]; __I uint16_t DFIINITCOMPLETESHADOW; /**< dfi_init_complete - Controller Read-only Shadow, offset: 0x1F4 */ } DWC_DDRPHYA_APBONLY_Type; /* ---------------------------------------------------------------------------- -- DWC_DDRPHYA_APBONLY Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DWC_DDRPHYA_APBONLY_Register_Masks DWC_DDRPHYA_APBONLY Register Masks * @{ */ /*! @name MICROCONTMUXSEL - PMU Config Mux Select */ /*! @{ */ #define DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MicroContMuxSel_MASK (0x1U) #define DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MicroContMuxSel_SHIFT (0U) #define DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MicroContMuxSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MicroContMuxSel_SHIFT)) & \ DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MicroContMuxSel_MASK) /*! @} */ /*! @name UCTSHADOWREGS - PMU/Controller Protocol - Controller Read-only Shadow */ /*! @{ */ #define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctWriteProtShadow_MASK (0x1U) #define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctWriteProtShadow_SHIFT (0U) #define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctWriteProtShadow(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctWriteProtShadow_SHIFT)) & \ DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctWriteProtShadow_MASK) #define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctDatWriteProtShadow_MASK (0x2U) #define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctDatWriteProtShadow_SHIFT (1U) #define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctDatWriteProtShadow(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctDatWriteProtShadow_SHIFT)) & \ DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctDatWriteProtShadow_MASK) /*! @} */ /*! @name DCTWRITEONLY - Reserved for future use. */ /*! @{ */ #define DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DctWriteOnly_MASK (0xFFFFU) #define DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DctWriteOnly_SHIFT (0U) #define DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DctWriteOnly(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DctWriteOnly_SHIFT)) & \ DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DctWriteOnly_MASK) /*! @} */ /*! @name DCTWRITEPROT - DCT downstream mailbox protocol CSR. */ /*! @{ */ #define DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DctWriteProt_MASK (0x1U) #define DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DctWriteProt_SHIFT (0U) #define DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DctWriteProt(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DctWriteProt_SHIFT)) & \ DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DctWriteProt_MASK) /*! @} */ /*! @name UCTWRITEONLYSHADOW - Read-only view of the csr UctDatWriteOnly */ /*! @{ */ #define DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UctWriteOnlyShadow_MASK (0xFFFFU) #define DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UctWriteOnlyShadow_SHIFT (0U) #define DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UctWriteOnlyShadow(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UctWriteOnlyShadow_SHIFT)) & \ DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UctWriteOnlyShadow_MASK) /*! @} */ /*! @name UCTDATWRITEONLYSHADOW - Read-only view of the csr UctDatWriteOnly */ /*! @{ */ #define DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UctDatWriteOnlyShadow_MASK (0xFFFFU) #define DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UctDatWriteOnlyShadow_SHIFT (0U) #define DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UctDatWriteOnlyShadow(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UctDatWriteOnlyShadow_SHIFT)) & \ DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UctDatWriteOnlyShadow_MASK) /*! @} */ /*! @name DFICFGRDDATAVALIDTICKS - Number of DfiClk ticks required for valid csr Rd Data. */ /*! @{ */ #define DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DfiCfgRdDataValidTicks_MASK (0x3FU) #define DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DfiCfgRdDataValidTicks_SHIFT (0U) #define DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DfiCfgRdDataValidTicks(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DfiCfgRdDataValidTicks_SHIFT)) & \ DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DfiCfgRdDataValidTicks_MASK) /*! @} */ /*! @name MICRORESET - Controls reset and clock shutdown on the local microcontroller */ /*! @{ */ #define DWC_DDRPHYA_APBONLY_MICRORESET_StallToMicro_MASK (0x1U) #define DWC_DDRPHYA_APBONLY_MICRORESET_StallToMicro_SHIFT (0U) #define DWC_DDRPHYA_APBONLY_MICRORESET_StallToMicro(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_StallToMicro_SHIFT)) & \ DWC_DDRPHYA_APBONLY_MICRORESET_StallToMicro_MASK) #define DWC_DDRPHYA_APBONLY_MICRORESET_TestWakeup_MASK (0x2U) #define DWC_DDRPHYA_APBONLY_MICRORESET_TestWakeup_SHIFT (1U) #define DWC_DDRPHYA_APBONLY_MICRORESET_TestWakeup(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_TestWakeup_SHIFT)) & \ DWC_DDRPHYA_APBONLY_MICRORESET_TestWakeup_MASK) #define DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMicro_MASK (0x4U) #define DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMicro_SHIFT (2U) #define DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMicro(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMicro_SHIFT)) & \ DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMicro_MASK) #define DWC_DDRPHYA_APBONLY_MICRORESET_ResetToMicro_MASK (0x8U) #define DWC_DDRPHYA_APBONLY_MICRORESET_ResetToMicro_SHIFT (3U) #define DWC_DDRPHYA_APBONLY_MICRORESET_ResetToMicro(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_ResetToMicro_SHIFT)) & \ DWC_DDRPHYA_APBONLY_MICRORESET_ResetToMicro_MASK) /*! @} */ /*! @name DFIINITCOMPLETESHADOW - dfi_init_complete - Controller Read-only Shadow */ /*! @{ */ #define DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DfiInitCompleteShadow_MASK (0x1U) #define DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DfiInitCompleteShadow_SHIFT (0U) #define DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DfiInitCompleteShadow(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DfiInitCompleteShadow_SHIFT)) & \ DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DfiInitCompleteShadow_MASK) /*! @} */ /*! * @} */ /* end of group DWC_DDRPHYA_APBONLY_Register_Masks */ /* DWC_DDRPHYA_APBONLY - Peripheral instance base addresses */ /** Peripheral DWC_DDRPHYA_APBONLY0 base address */ #define DWC_DDRPHYA_APBONLY0_BASE (0x3C0D0000u) /** Peripheral DWC_DDRPHYA_APBONLY0 base pointer */ #define DWC_DDRPHYA_APBONLY0 ((DWC_DDRPHYA_APBONLY_Type *)DWC_DDRPHYA_APBONLY0_BASE) /** Array initializer of DWC_DDRPHYA_APBONLY peripheral base addresses */ #define DWC_DDRPHYA_APBONLY_BASE_ADDRS \ { \ DWC_DDRPHYA_APBONLY0_BASE \ } /** Array initializer of DWC_DDRPHYA_APBONLY peripheral base pointers */ #define DWC_DDRPHYA_APBONLY_BASE_PTRS \ { \ DWC_DDRPHYA_APBONLY0 \ } /*! * @} */ /* end of group DWC_DDRPHYA_APBONLY_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DWC_DDRPHYA_DBYTE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DWC_DDRPHYA_DBYTE_Peripheral_Access_Layer DWC_DDRPHYA_DBYTE Peripheral Access Layer * @{ */ /** DWC_DDRPHYA_DBYTE - Register Layout Typedef */ typedef struct { __IO uint16_t DBYTEMISCMODE; /**< DBYTE Module Disable, offset: 0x0 */ uint8_t RESERVED_0[50]; __IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x34 */ uint8_t RESERVED_1[10]; __IO uint16_t DFIMRL_P0; /**< DFI MaxReadLatency, offset: 0x40 */ uint8_t RESERVED_2[30]; __IO uint16_t VREFDAC1_R0; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x60 */ uint8_t RESERVED_3[30]; __IO uint16_t VREFDAC0_R0; /**< VrefDAC0 control for DQ Receiver, offset: 0x80 */ __IO uint16_t TXIMPEDANCECTRL0_B0_P0; /**< Data TX impedance controls, offset: 0x82 */ uint8_t RESERVED_4[2]; __IO uint16_t DQDQSRCVCNTRL_B0_P0; /**< Dq/Dqs receiver control, offset: 0x86 */ uint8_t RESERVED_5[8]; __IO uint16_t TXEQUALIZATIONMODE_P0; /**< Tx dq driver equalization mode controls., offset: 0x90 */ __IO uint16_t TXIMPEDANCECTRL1_B0_P0; /**< TX impedance controls, offset: 0x92 */ __IO uint16_t DQDQSRCVCNTRL1; /**< Dq/Dqs receiver control, offset: 0x94 */ __IO uint16_t TXIMPEDANCECTRL2_B0_P0; /**< TX equalization impedance controls, offset: 0x96 */ __IO uint16_t DQDQSRCVCNTRL2_P0; /**< Dq/Dqs receiver control, offset: 0x98 */ __IO uint16_t TXODTDRVSTREN_B0_P0; /**< TX ODT driver strength control, offset: 0x9A */ uint8_t RESERVED_6[16]; __I uint16_t RXFIFOCHECKSTATUS; /**< Status of RX FIFO Consistency Checks, offset: 0xAC */ __I uint16_t RXFIFOCHECKERRVALUES; /**< Contains the captured values associated with an RxFifo consistency error, offset: 0xAE */ __I uint16_t RXFIFOINFO; /**< Data Receive FIFO Pointer Values, offset: 0xB0 */ __IO uint16_t RXFIFOVISIBILITY; /**< RX FIFO visibility, offset: 0xB2 */ __I uint16_t RXFIFOCONTENTSDQ3210; /**< RX FIFO contents, lane[3:0], offset: 0xB4 */ __I uint16_t RXFIFOCONTENTSDQ7654; /**< RX FIFO contents, lane[7:4], offset: 0xB6 */ __I uint16_t RXFIFOCONTENTSDBI; /**< RX FIFO contents, dbi, offset: 0xB8 */ uint8_t RESERVED_7[4]; __IO uint16_t TXSLEWRATE_B0_P0; /**< TX slew rate controls, offset: 0xBE */ uint8_t RESERVED_8[16]; __IO uint16_t RXPBDLYTG0_R0; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xD0 */ __IO uint16_t RXPBDLYTG1_R0; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xD2 */ __IO uint16_t RXPBDLYTG2_R0; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xD4 */ __IO uint16_t RXPBDLYTG3_R0; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xD6 */ uint8_t RESERVED_9[40]; __IO uint16_t RXENDLYTG0_U0_P0; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x100 */ __IO uint16_t RXENDLYTG1_U0_P0; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x102 */ __IO uint16_t RXENDLYTG2_U0_P0; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x104 */ __IO uint16_t RXENDLYTG3_U0_P0; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x106 */ uint8_t RESERVED_10[16]; __IO uint16_t RXCLKDLYTG0_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x118 */ __IO uint16_t RXCLKDLYTG1_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x11A */ __IO uint16_t RXCLKDLYTG2_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x11C */ __IO uint16_t RXCLKDLYTG3_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x11E */ __IO uint16_t RXCLKCDLYTG0_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x120 */ __IO uint16_t RXCLKCDLYTG1_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x122 */ __IO uint16_t RXCLKCDLYTG2_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x124 */ uint8_t RESERVED_11[2]; __IO uint16_t RXCLKCDLYTG3_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x128 */ uint8_t RESERVED_12[22]; __IO uint16_t DQLNSEL[8]; /**< Maps Phy DQ lane to memory DQ0, array offset: 0x140, array step: 0x2 */ uint8_t RESERVED_13[48]; __IO uint16_t TXDQDLYTG0_R0_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x180 */ __IO uint16_t TXDQDLYTG1_R0_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x182 */ __IO uint16_t TXDQDLYTG2_R0_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x184 */ __IO uint16_t TXDQDLYTG3_R0_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x186 */ uint8_t RESERVED_14[24]; __IO uint16_t TXDQSDLYTG0_U0_P0; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x1A0 */ __IO uint16_t TXDQSDLYTG1_U0_P0; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x1A2 */ __IO uint16_t TXDQSDLYTG2_U0_P0; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x1A4 */ __IO uint16_t TXDQSDLYTG3_U0_P0; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x1A6 */ uint8_t RESERVED_15[32]; __I uint16_t DXLCDLSTATUS; /**< Debug status of the DBYTE LCDL, offset: 0x1C8 */ uint8_t RESERVED_16[150]; __IO uint16_t VREFDAC1_R1; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x260 */ uint8_t RESERVED_17[30]; __IO uint16_t VREFDAC0_R1; /**< VrefDAC0 control for DQ Receiver, offset: 0x280 */ __IO uint16_t TXIMPEDANCECTRL0_B1_P0; /**< Data TX impedance controls, offset: 0x282 */ uint8_t RESERVED_18[2]; __IO uint16_t DQDQSRCVCNTRL_B1_P0; /**< Dq/Dqs receiver control, offset: 0x286 */ uint8_t RESERVED_19[10]; __IO uint16_t TXIMPEDANCECTRL1_B1_P0; /**< TX impedance controls, offset: 0x292 */ uint8_t RESERVED_20[2]; __IO uint16_t TXIMPEDANCECTRL2_B1_P0; /**< TX equalization impedance controls, offset: 0x296 */ uint8_t RESERVED_21[2]; __IO uint16_t TXODTDRVSTREN_B1_P0; /**< TX ODT driver strength control, offset: 0x29A */ uint8_t RESERVED_22[34]; __IO uint16_t TXSLEWRATE_B1_P0; /**< TX slew rate controls, offset: 0x2BE */ uint8_t RESERVED_23[16]; __IO uint16_t RXPBDLYTG0_R1; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x2D0 */ __IO uint16_t RXPBDLYTG1_R1; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x2D2 */ __IO uint16_t RXPBDLYTG2_R1; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x2D4 */ __IO uint16_t RXPBDLYTG3_R1; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x2D6 */ uint8_t RESERVED_24[40]; __IO uint16_t RXENDLYTG0_U1_P0; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x300 */ __IO uint16_t RXENDLYTG1_U1_P0; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x302 */ __IO uint16_t RXENDLYTG2_U1_P0; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x304 */ __IO uint16_t RXENDLYTG3_U1_P0; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x306 */ uint8_t RESERVED_25[16]; __IO uint16_t RXCLKDLYTG0_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x318 */ __IO uint16_t RXCLKDLYTG1_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x31A */ __IO uint16_t RXCLKDLYTG2_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x31C */ __IO uint16_t RXCLKDLYTG3_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x31E */ __IO uint16_t RXCLKCDLYTG0_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x320 */ __IO uint16_t RXCLKCDLYTG1_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x322 */ __IO uint16_t RXCLKCDLYTG2_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x324 */ uint8_t RESERVED_26[2]; __IO uint16_t RXCLKCDLYTG3_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x328 */ uint8_t RESERVED_27[86]; __IO uint16_t TXDQDLYTG0_R1_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x380 */ __IO uint16_t TXDQDLYTG1_R1_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x382 */ __IO uint16_t TXDQDLYTG2_R1_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x384 */ __IO uint16_t TXDQDLYTG3_R1_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x386 */ uint8_t RESERVED_28[24]; __IO uint16_t TXDQSDLYTG0_U1_P0; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x3A0 */ __IO uint16_t TXDQSDLYTG1_U1_P0; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x3A2 */ __IO uint16_t TXDQSDLYTG2_U1_P0; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x3A4 */ __IO uint16_t TXDQSDLYTG3_U1_P0; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x3A6 */ uint8_t RESERVED_29[184]; __IO uint16_t VREFDAC1_R2; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x460 */ uint8_t RESERVED_30[30]; __IO uint16_t VREFDAC0_R2; /**< VrefDAC0 control for DQ Receiver, offset: 0x480 */ uint8_t RESERVED_31[78]; __IO uint16_t RXPBDLYTG0_R2; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x4D0 */ __IO uint16_t RXPBDLYTG1_R2; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x4D2 */ __IO uint16_t RXPBDLYTG2_R2; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x4D4 */ __IO uint16_t RXPBDLYTG3_R2; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x4D6 */ uint8_t RESERVED_32[168]; __IO uint16_t TXDQDLYTG0_R2_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x580 */ __IO uint16_t TXDQDLYTG1_R2_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x582 */ __IO uint16_t TXDQDLYTG2_R2_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x584 */ __IO uint16_t TXDQDLYTG3_R2_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x586 */ uint8_t RESERVED_33[216]; __IO uint16_t VREFDAC1_R3; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x660 */ uint8_t RESERVED_34[30]; __IO uint16_t VREFDAC0_R3; /**< VrefDAC0 control for DQ Receiver, offset: 0x680 */ uint8_t RESERVED_35[78]; __IO uint16_t RXPBDLYTG0_R3; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x6D0 */ __IO uint16_t RXPBDLYTG1_R3; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x6D2 */ __IO uint16_t RXPBDLYTG2_R3; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x6D4 */ __IO uint16_t RXPBDLYTG3_R3; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x6D6 */ uint8_t RESERVED_36[168]; __IO uint16_t TXDQDLYTG0_R3_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x780 */ __IO uint16_t TXDQDLYTG1_R3_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x782 */ __IO uint16_t TXDQDLYTG2_R3_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x784 */ __IO uint16_t TXDQDLYTG3_R3_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x786 */ uint8_t RESERVED_37[216]; __IO uint16_t VREFDAC1_R4; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x860 */ uint8_t RESERVED_38[30]; __IO uint16_t VREFDAC0_R4; /**< VrefDAC0 control for DQ Receiver, offset: 0x880 */ uint8_t RESERVED_39[78]; __IO uint16_t RXPBDLYTG0_R4; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x8D0 */ __IO uint16_t RXPBDLYTG1_R4; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x8D2 */ __IO uint16_t RXPBDLYTG2_R4; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x8D4 */ __IO uint16_t RXPBDLYTG3_R4; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x8D6 */ uint8_t RESERVED_40[168]; __IO uint16_t TXDQDLYTG0_R4_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x980 */ __IO uint16_t TXDQDLYTG1_R4_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x982 */ __IO uint16_t TXDQDLYTG2_R4_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x984 */ __IO uint16_t TXDQDLYTG3_R4_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x986 */ uint8_t RESERVED_41[216]; __IO uint16_t VREFDAC1_R5; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0xA60 */ uint8_t RESERVED_42[30]; __IO uint16_t VREFDAC0_R5; /**< VrefDAC0 control for DQ Receiver, offset: 0xA80 */ uint8_t RESERVED_43[78]; __IO uint16_t RXPBDLYTG0_R5; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xAD0 */ __IO uint16_t RXPBDLYTG1_R5; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xAD2 */ __IO uint16_t RXPBDLYTG2_R5; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xAD4 */ __IO uint16_t RXPBDLYTG3_R5; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xAD6 */ uint8_t RESERVED_44[168]; __IO uint16_t TXDQDLYTG0_R5_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0xB80 */ __IO uint16_t TXDQDLYTG1_R5_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0xB82 */ __IO uint16_t TXDQDLYTG2_R5_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0xB84 */ __IO uint16_t TXDQDLYTG3_R5_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0xB86 */ uint8_t RESERVED_45[216]; __IO uint16_t VREFDAC1_R6; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0xC60 */ uint8_t RESERVED_46[30]; __IO uint16_t VREFDAC0_R6; /**< VrefDAC0 control for DQ Receiver, offset: 0xC80 */ uint8_t RESERVED_47[78]; __IO uint16_t RXPBDLYTG0_R6; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xCD0 */ __IO uint16_t RXPBDLYTG1_R6; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xCD2 */ __IO uint16_t RXPBDLYTG2_R6; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xCD4 */ __IO uint16_t RXPBDLYTG3_R6; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xCD6 */ uint8_t RESERVED_48[168]; __IO uint16_t TXDQDLYTG0_R6_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0xD80 */ __IO uint16_t TXDQDLYTG1_R6_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0xD82 */ __IO uint16_t TXDQDLYTG2_R6_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0xD84 */ __IO uint16_t TXDQDLYTG3_R6_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0xD86 */ uint8_t RESERVED_49[216]; __IO uint16_t VREFDAC1_R7; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0xE60 */ uint8_t RESERVED_50[30]; __IO uint16_t VREFDAC0_R7; /**< VrefDAC0 control for DQ Receiver, offset: 0xE80 */ uint8_t RESERVED_51[78]; __IO uint16_t RXPBDLYTG0_R7; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xED0 */ __IO uint16_t RXPBDLYTG1_R7; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xED2 */ __IO uint16_t RXPBDLYTG2_R7; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xED4 */ __IO uint16_t RXPBDLYTG3_R7; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xED6 */ uint8_t RESERVED_52[168]; __IO uint16_t TXDQDLYTG0_R7_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0xF80 */ __IO uint16_t TXDQDLYTG1_R7_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0xF82 */ __IO uint16_t TXDQDLYTG2_R7_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0xF84 */ __IO uint16_t TXDQDLYTG3_R7_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0xF86 */ uint8_t RESERVED_53[216]; __IO uint16_t VREFDAC1_R8; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x1060 */ uint8_t RESERVED_54[30]; __IO uint16_t VREFDAC0_R8; /**< VrefDAC0 control for DQ Receiver, offset: 0x1080 */ uint8_t RESERVED_55[78]; __IO uint16_t RXPBDLYTG0_R8; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x10D0 */ __IO uint16_t RXPBDLYTG1_R8; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x10D2 */ __IO uint16_t RXPBDLYTG2_R8; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x10D4 */ __IO uint16_t RXPBDLYTG3_R8; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x10D6 */ uint8_t RESERVED_56[168]; __IO uint16_t TXDQDLYTG0_R8_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x1180 */ __IO uint16_t TXDQDLYTG1_R8_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x1182 */ __IO uint16_t TXDQDLYTG2_R8_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x1184 */ __IO uint16_t TXDQDLYTG3_R8_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x1186 */ uint8_t RESERVED_57[2092728]; __IO uint16_t DFIMRL_P1; /**< DFI MaxReadLatency, offset: 0x200040 */ uint8_t RESERVED_58[64]; __IO uint16_t TXIMPEDANCECTRL0_B0_P1; /**< Data TX impedance controls, offset: 0x200082 */ uint8_t RESERVED_59[2]; __IO uint16_t DQDQSRCVCNTRL_B0_P1; /**< Dq/Dqs receiver control, offset: 0x200086 */ uint8_t RESERVED_60[8]; __IO uint16_t TXEQUALIZATIONMODE_P1; /**< Tx dq driver equalization mode controls., offset: 0x200090 */ __IO uint16_t TXIMPEDANCECTRL1_B0_P1; /**< TX impedance controls, offset: 0x200092 */ uint8_t RESERVED_61[2]; __IO uint16_t TXIMPEDANCECTRL2_B0_P1; /**< TX equalization impedance controls, offset: 0x200096 */ __IO uint16_t DQDQSRCVCNTRL2_P1; /**< Dq/Dqs receiver control, offset: 0x200098 */ __IO uint16_t TXODTDRVSTREN_B0_P1; /**< TX ODT driver strength control, offset: 0x20009A */ uint8_t RESERVED_62[34]; __IO uint16_t TXSLEWRATE_B0_P1; /**< TX slew rate controls, offset: 0x2000BE */ uint8_t RESERVED_63[64]; __IO uint16_t RXENDLYTG0_U0_P1; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x200100 */ __IO uint16_t RXENDLYTG1_U0_P1; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x200102 */ __IO uint16_t RXENDLYTG2_U0_P1; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x200104 */ __IO uint16_t RXENDLYTG3_U0_P1; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x200106 */ uint8_t RESERVED_64[16]; __IO uint16_t RXCLKDLYTG0_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x200118 */ __IO uint16_t RXCLKDLYTG1_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x20011A */ __IO uint16_t RXCLKDLYTG2_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x20011C */ __IO uint16_t RXCLKDLYTG3_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x20011E */ __IO uint16_t RXCLKCDLYTG0_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200120 */ __IO uint16_t RXCLKCDLYTG1_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200122 */ __IO uint16_t RXCLKCDLYTG2_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x200124 */ uint8_t RESERVED_65[2]; __IO uint16_t RXCLKCDLYTG3_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x200128 */ uint8_t RESERVED_66[86]; __IO uint16_t TXDQDLYTG0_R0_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200180 */ __IO uint16_t TXDQDLYTG1_R0_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200182 */ __IO uint16_t TXDQDLYTG2_R0_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200184 */ __IO uint16_t TXDQDLYTG3_R0_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200186 */ uint8_t RESERVED_67[24]; __IO uint16_t TXDQSDLYTG0_U0_P1; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x2001A0 */ __IO uint16_t TXDQSDLYTG1_U0_P1; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x2001A2 */ __IO uint16_t TXDQSDLYTG2_U0_P1; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x2001A4 */ __IO uint16_t TXDQSDLYTG3_U0_P1; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x2001A6 */ uint8_t RESERVED_68[218]; __IO uint16_t TXIMPEDANCECTRL0_B1_P1; /**< Data TX impedance controls, offset: 0x200282 */ uint8_t RESERVED_69[2]; __IO uint16_t DQDQSRCVCNTRL_B1_P1; /**< Dq/Dqs receiver control, offset: 0x200286 */ uint8_t RESERVED_70[10]; __IO uint16_t TXIMPEDANCECTRL1_B1_P1; /**< TX impedance controls, offset: 0x200292 */ uint8_t RESERVED_71[2]; __IO uint16_t TXIMPEDANCECTRL2_B1_P1; /**< TX equalization impedance controls, offset: 0x200296 */ uint8_t RESERVED_72[2]; __IO uint16_t TXODTDRVSTREN_B1_P1; /**< TX ODT driver strength control, offset: 0x20029A */ uint8_t RESERVED_73[34]; __IO uint16_t TXSLEWRATE_B1_P1; /**< TX slew rate controls, offset: 0x2002BE */ uint8_t RESERVED_74[64]; __IO uint16_t RXENDLYTG0_U1_P1; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x200300 */ __IO uint16_t RXENDLYTG1_U1_P1; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x200302 */ __IO uint16_t RXENDLYTG2_U1_P1; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x200304 */ __IO uint16_t RXENDLYTG3_U1_P1; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x200306 */ uint8_t RESERVED_75[16]; __IO uint16_t RXCLKDLYTG0_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x200318 */ __IO uint16_t RXCLKDLYTG1_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x20031A */ __IO uint16_t RXCLKDLYTG2_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x20031C */ __IO uint16_t RXCLKDLYTG3_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x20031E */ __IO uint16_t RXCLKCDLYTG0_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200320 */ __IO uint16_t RXCLKCDLYTG1_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200322 */ __IO uint16_t RXCLKCDLYTG2_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x200324 */ uint8_t RESERVED_76[2]; __IO uint16_t RXCLKCDLYTG3_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x200328 */ uint8_t RESERVED_77[86]; __IO uint16_t TXDQDLYTG0_R1_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200380 */ __IO uint16_t TXDQDLYTG1_R1_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200382 */ __IO uint16_t TXDQDLYTG2_R1_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200384 */ __IO uint16_t TXDQDLYTG3_R1_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200386 */ uint8_t RESERVED_78[24]; __IO uint16_t TXDQSDLYTG0_U1_P1; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x2003A0 */ __IO uint16_t TXDQSDLYTG1_U1_P1; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x2003A2 */ __IO uint16_t TXDQSDLYTG2_U1_P1; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x2003A4 */ __IO uint16_t TXDQSDLYTG3_U1_P1; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x2003A6 */ uint8_t RESERVED_79[472]; __IO uint16_t TXDQDLYTG0_R2_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200580 */ __IO uint16_t TXDQDLYTG1_R2_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200582 */ __IO uint16_t TXDQDLYTG2_R2_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200584 */ __IO uint16_t TXDQDLYTG3_R2_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200586 */ uint8_t RESERVED_80[504]; __IO uint16_t TXDQDLYTG0_R3_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200780 */ __IO uint16_t TXDQDLYTG1_R3_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200782 */ __IO uint16_t TXDQDLYTG2_R3_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200784 */ __IO uint16_t TXDQDLYTG3_R3_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200786 */ uint8_t RESERVED_81[504]; __IO uint16_t TXDQDLYTG0_R4_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200980 */ __IO uint16_t TXDQDLYTG1_R4_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200982 */ __IO uint16_t TXDQDLYTG2_R4_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200984 */ __IO uint16_t TXDQDLYTG3_R4_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200986 */ uint8_t RESERVED_82[504]; __IO uint16_t TXDQDLYTG0_R5_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200B80 */ __IO uint16_t TXDQDLYTG1_R5_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200B82 */ __IO uint16_t TXDQDLYTG2_R5_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200B84 */ __IO uint16_t TXDQDLYTG3_R5_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200B86 */ uint8_t RESERVED_83[504]; __IO uint16_t TXDQDLYTG0_R6_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200D80 */ __IO uint16_t TXDQDLYTG1_R6_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200D82 */ __IO uint16_t TXDQDLYTG2_R6_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200D84 */ __IO uint16_t TXDQDLYTG3_R6_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200D86 */ uint8_t RESERVED_84[504]; __IO uint16_t TXDQDLYTG0_R7_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200F80 */ __IO uint16_t TXDQDLYTG1_R7_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200F82 */ __IO uint16_t TXDQDLYTG2_R7_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200F84 */ __IO uint16_t TXDQDLYTG3_R7_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200F86 */ uint8_t RESERVED_85[504]; __IO uint16_t TXDQDLYTG0_R8_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x201180 */ __IO uint16_t TXDQDLYTG1_R8_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x201182 */ __IO uint16_t TXDQDLYTG2_R8_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x201184 */ __IO uint16_t TXDQDLYTG3_R8_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x201186 */ uint8_t RESERVED_86[2092728]; __IO uint16_t DFIMRL_P2; /**< DFI MaxReadLatency, offset: 0x400040 */ uint8_t RESERVED_87[64]; __IO uint16_t TXIMPEDANCECTRL0_B0_P2; /**< Data TX impedance controls, offset: 0x400082 */ uint8_t RESERVED_88[2]; __IO uint16_t DQDQSRCVCNTRL_B0_P2; /**< Dq/Dqs receiver control, offset: 0x400086 */ uint8_t RESERVED_89[8]; __IO uint16_t TXEQUALIZATIONMODE_P2; /**< Tx dq driver equalization mode controls., offset: 0x400090 */ __IO uint16_t TXIMPEDANCECTRL1_B0_P2; /**< TX impedance controls, offset: 0x400092 */ uint8_t RESERVED_90[2]; __IO uint16_t TXIMPEDANCECTRL2_B0_P2; /**< TX equalization impedance controls, offset: 0x400096 */ __IO uint16_t DQDQSRCVCNTRL2_P2; /**< Dq/Dqs receiver control, offset: 0x400098 */ __IO uint16_t TXODTDRVSTREN_B0_P2; /**< TX ODT driver strength control, offset: 0x40009A */ uint8_t RESERVED_91[34]; __IO uint16_t TXSLEWRATE_B0_P2; /**< TX slew rate controls, offset: 0x4000BE */ uint8_t RESERVED_92[64]; __IO uint16_t RXENDLYTG0_U0_P2; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x400100 */ __IO uint16_t RXENDLYTG1_U0_P2; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x400102 */ __IO uint16_t RXENDLYTG2_U0_P2; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x400104 */ __IO uint16_t RXENDLYTG3_U0_P2; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x400106 */ uint8_t RESERVED_93[16]; __IO uint16_t RXCLKDLYTG0_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x400118 */ __IO uint16_t RXCLKDLYTG1_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x40011A */ __IO uint16_t RXCLKDLYTG2_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x40011C */ __IO uint16_t RXCLKDLYTG3_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x40011E */ __IO uint16_t RXCLKCDLYTG0_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400120 */ __IO uint16_t RXCLKCDLYTG1_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400122 */ __IO uint16_t RXCLKCDLYTG2_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x400124 */ uint8_t RESERVED_94[2]; __IO uint16_t RXCLKCDLYTG3_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x400128 */ uint8_t RESERVED_95[50]; __IO uint16_t PPTDQSCNTINVTRNTG0_P2; /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation, offset: 0x40015C */ __IO uint16_t PPTDQSCNTINVTRNTG1_P2; /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation, offset: 0x40015E */ uint8_t RESERVED_96[32]; __IO uint16_t TXDQDLYTG0_R0_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400180 */ __IO uint16_t TXDQDLYTG1_R0_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400182 */ __IO uint16_t TXDQDLYTG2_R0_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400184 */ __IO uint16_t TXDQDLYTG3_R0_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400186 */ uint8_t RESERVED_97[24]; __IO uint16_t TXDQSDLYTG0_U0_P2; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x4001A0 */ __IO uint16_t TXDQSDLYTG1_U0_P2; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x4001A2 */ __IO uint16_t TXDQSDLYTG2_U0_P2; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x4001A4 */ __IO uint16_t TXDQSDLYTG3_U0_P2; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x4001A6 */ uint8_t RESERVED_98[218]; __IO uint16_t TXIMPEDANCECTRL0_B1_P2; /**< Data TX impedance controls, offset: 0x400282 */ uint8_t RESERVED_99[2]; __IO uint16_t DQDQSRCVCNTRL_B1_P2; /**< Dq/Dqs receiver control, offset: 0x400286 */ uint8_t RESERVED_100[10]; __IO uint16_t TXIMPEDANCECTRL1_B1_P2; /**< TX impedance controls, offset: 0x400292 */ uint8_t RESERVED_101[2]; __IO uint16_t TXIMPEDANCECTRL2_B1_P2; /**< TX equalization impedance controls, offset: 0x400296 */ uint8_t RESERVED_102[2]; __IO uint16_t TXODTDRVSTREN_B1_P2; /**< TX ODT driver strength control, offset: 0x40029A */ uint8_t RESERVED_103[34]; __IO uint16_t TXSLEWRATE_B1_P2; /**< TX slew rate controls, offset: 0x4002BE */ uint8_t RESERVED_104[64]; __IO uint16_t RXENDLYTG0_U1_P2; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x400300 */ __IO uint16_t RXENDLYTG1_U1_P2; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x400302 */ __IO uint16_t RXENDLYTG2_U1_P2; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x400304 */ __IO uint16_t RXENDLYTG3_U1_P2; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x400306 */ uint8_t RESERVED_105[16]; __IO uint16_t RXCLKDLYTG0_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x400318 */ __IO uint16_t RXCLKDLYTG1_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x40031A */ __IO uint16_t RXCLKDLYTG2_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x40031C */ __IO uint16_t RXCLKDLYTG3_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x40031E */ __IO uint16_t RXCLKCDLYTG0_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400320 */ __IO uint16_t RXCLKCDLYTG1_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400322 */ __IO uint16_t RXCLKCDLYTG2_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x400324 */ uint8_t RESERVED_106[2]; __IO uint16_t RXCLKCDLYTG3_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x400328 */ uint8_t RESERVED_107[86]; __IO uint16_t TXDQDLYTG0_R1_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400380 */ __IO uint16_t TXDQDLYTG1_R1_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400382 */ __IO uint16_t TXDQDLYTG2_R1_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400384 */ __IO uint16_t TXDQDLYTG3_R1_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400386 */ uint8_t RESERVED_108[24]; __IO uint16_t TXDQSDLYTG0_U1_P2; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x4003A0 */ __IO uint16_t TXDQSDLYTG1_U1_P2; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x4003A2 */ __IO uint16_t TXDQSDLYTG2_U1_P2; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x4003A4 */ __IO uint16_t TXDQSDLYTG3_U1_P2; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x4003A6 */ uint8_t RESERVED_109[472]; __IO uint16_t TXDQDLYTG0_R2_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400580 */ __IO uint16_t TXDQDLYTG1_R2_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400582 */ __IO uint16_t TXDQDLYTG2_R2_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400584 */ __IO uint16_t TXDQDLYTG3_R2_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400586 */ uint8_t RESERVED_110[504]; __IO uint16_t TXDQDLYTG0_R3_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400780 */ __IO uint16_t TXDQDLYTG1_R3_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400782 */ __IO uint16_t TXDQDLYTG2_R3_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400784 */ __IO uint16_t TXDQDLYTG3_R3_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400786 */ uint8_t RESERVED_111[504]; __IO uint16_t TXDQDLYTG0_R4_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400980 */ __IO uint16_t TXDQDLYTG1_R4_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400982 */ __IO uint16_t TXDQDLYTG2_R4_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400984 */ __IO uint16_t TXDQDLYTG3_R4_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400986 */ uint8_t RESERVED_112[504]; __IO uint16_t TXDQDLYTG0_R5_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400B80 */ __IO uint16_t TXDQDLYTG1_R5_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400B82 */ __IO uint16_t TXDQDLYTG2_R5_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400B84 */ __IO uint16_t TXDQDLYTG3_R5_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400B86 */ uint8_t RESERVED_113[504]; __IO uint16_t TXDQDLYTG0_R6_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400D80 */ __IO uint16_t TXDQDLYTG1_R6_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400D82 */ __IO uint16_t TXDQDLYTG2_R6_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400D84 */ __IO uint16_t TXDQDLYTG3_R6_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400D86 */ uint8_t RESERVED_114[504]; __IO uint16_t TXDQDLYTG0_R7_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400F80 */ __IO uint16_t TXDQDLYTG1_R7_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400F82 */ __IO uint16_t TXDQDLYTG2_R7_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400F84 */ __IO uint16_t TXDQDLYTG3_R7_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400F86 */ uint8_t RESERVED_115[504]; __IO uint16_t TXDQDLYTG0_R8_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x401180 */ __IO uint16_t TXDQDLYTG1_R8_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x401182 */ __IO uint16_t TXDQDLYTG2_R8_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x401184 */ __IO uint16_t TXDQDLYTG3_R8_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x401186 */ uint8_t RESERVED_116[2092728]; __IO uint16_t DFIMRL_P3; /**< DFI MaxReadLatency, offset: 0x600040 */ uint8_t RESERVED_117[64]; __IO uint16_t TXIMPEDANCECTRL0_B0_P3; /**< Data TX impedance controls, offset: 0x600082 */ uint8_t RESERVED_118[2]; __IO uint16_t DQDQSRCVCNTRL_B0_P3; /**< Dq/Dqs receiver control, offset: 0x600086 */ uint8_t RESERVED_119[8]; __IO uint16_t TXEQUALIZATIONMODE_P3; /**< Tx dq driver equalization mode controls., offset: 0x600090 */ __IO uint16_t TXIMPEDANCECTRL1_B0_P3; /**< TX impedance controls, offset: 0x600092 */ uint8_t RESERVED_120[2]; __IO uint16_t TXIMPEDANCECTRL2_B0_P3; /**< TX equalization impedance controls, offset: 0x600096 */ __IO uint16_t DQDQSRCVCNTRL2_P3; /**< Dq/Dqs receiver control, offset: 0x600098 */ __IO uint16_t TXODTDRVSTREN_B0_P3; /**< TX ODT driver strength control, offset: 0x60009A */ uint8_t RESERVED_121[34]; __IO uint16_t TXSLEWRATE_B0_P3; /**< TX slew rate controls, offset: 0x6000BE */ uint8_t RESERVED_122[64]; __IO uint16_t RXENDLYTG0_U0_P3; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x600100 */ __IO uint16_t RXENDLYTG1_U0_P3; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x600102 */ __IO uint16_t RXENDLYTG2_U0_P3; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x600104 */ __IO uint16_t RXENDLYTG3_U0_P3; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x600106 */ uint8_t RESERVED_123[16]; __IO uint16_t RXCLKDLYTG0_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x600118 */ __IO uint16_t RXCLKDLYTG1_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x60011A */ __IO uint16_t RXCLKDLYTG2_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x60011C */ __IO uint16_t RXCLKDLYTG3_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x60011E */ __IO uint16_t RXCLKCDLYTG0_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600120 */ __IO uint16_t RXCLKCDLYTG1_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600122 */ __IO uint16_t RXCLKCDLYTG2_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x600124 */ uint8_t RESERVED_124[2]; __IO uint16_t RXCLKCDLYTG3_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x600128 */ uint8_t RESERVED_125[50]; __IO uint16_t PPTDQSCNTINVTRNTG0_P3; /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation, offset: 0x60015C */ __IO uint16_t PPTDQSCNTINVTRNTG1_P3; /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation, offset: 0x60015E */ uint8_t RESERVED_126[32]; __IO uint16_t TXDQDLYTG0_R0_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600180 */ __IO uint16_t TXDQDLYTG1_R0_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600182 */ __IO uint16_t TXDQDLYTG2_R0_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600184 */ __IO uint16_t TXDQDLYTG3_R0_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600186 */ uint8_t RESERVED_127[24]; __IO uint16_t TXDQSDLYTG0_U0_P3; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x6001A0 */ __IO uint16_t TXDQSDLYTG1_U0_P3; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x6001A2 */ __IO uint16_t TXDQSDLYTG2_U0_P3; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x6001A4 */ __IO uint16_t TXDQSDLYTG3_U0_P3; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x6001A6 */ uint8_t RESERVED_128[218]; __IO uint16_t TXIMPEDANCECTRL0_B1_P3; /**< Data TX impedance controls, offset: 0x600282 */ uint8_t RESERVED_129[2]; __IO uint16_t DQDQSRCVCNTRL_B1_P3; /**< Dq/Dqs receiver control, offset: 0x600286 */ uint8_t RESERVED_130[10]; __IO uint16_t TXIMPEDANCECTRL1_B1_P3; /**< TX impedance controls, offset: 0x600292 */ uint8_t RESERVED_131[2]; __IO uint16_t TXIMPEDANCECTRL2_B1_P3; /**< TX equalization impedance controls, offset: 0x600296 */ uint8_t RESERVED_132[2]; __IO uint16_t TXODTDRVSTREN_B1_P3; /**< TX ODT driver strength control, offset: 0x60029A */ uint8_t RESERVED_133[34]; __IO uint16_t TXSLEWRATE_B1_P3; /**< TX slew rate controls, offset: 0x6002BE */ uint8_t RESERVED_134[64]; __IO uint16_t RXENDLYTG0_U1_P3; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x600300 */ __IO uint16_t RXENDLYTG1_U1_P3; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x600302 */ __IO uint16_t RXENDLYTG2_U1_P3; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x600304 */ __IO uint16_t RXENDLYTG3_U1_P3; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x600306 */ uint8_t RESERVED_135[16]; __IO uint16_t RXCLKDLYTG0_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x600318 */ __IO uint16_t RXCLKDLYTG1_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x60031A */ __IO uint16_t RXCLKDLYTG2_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x60031C */ __IO uint16_t RXCLKDLYTG3_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x60031E */ __IO uint16_t RXCLKCDLYTG0_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600320 */ __IO uint16_t RXCLKCDLYTG1_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600322 */ __IO uint16_t RXCLKCDLYTG2_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x600324 */ uint8_t RESERVED_136[2]; __IO uint16_t RXCLKCDLYTG3_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x600328 */ uint8_t RESERVED_137[86]; __IO uint16_t TXDQDLYTG0_R1_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600380 */ __IO uint16_t TXDQDLYTG1_R1_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600382 */ __IO uint16_t TXDQDLYTG2_R1_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600384 */ __IO uint16_t TXDQDLYTG3_R1_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600386 */ uint8_t RESERVED_138[24]; __IO uint16_t TXDQSDLYTG0_U1_P3; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x6003A0 */ __IO uint16_t TXDQSDLYTG1_U1_P3; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x6003A2 */ __IO uint16_t TXDQSDLYTG2_U1_P3; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x6003A4 */ __IO uint16_t TXDQSDLYTG3_U1_P3; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x6003A6 */ uint8_t RESERVED_139[472]; __IO uint16_t TXDQDLYTG0_R2_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600580 */ __IO uint16_t TXDQDLYTG1_R2_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600582 */ __IO uint16_t TXDQDLYTG2_R2_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600584 */ __IO uint16_t TXDQDLYTG3_R2_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600586 */ uint8_t RESERVED_140[504]; __IO uint16_t TXDQDLYTG0_R3_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600780 */ __IO uint16_t TXDQDLYTG1_R3_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600782 */ __IO uint16_t TXDQDLYTG2_R3_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600784 */ __IO uint16_t TXDQDLYTG3_R3_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600786 */ uint8_t RESERVED_141[504]; __IO uint16_t TXDQDLYTG0_R4_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600980 */ __IO uint16_t TXDQDLYTG1_R4_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600982 */ __IO uint16_t TXDQDLYTG2_R4_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600984 */ __IO uint16_t TXDQDLYTG3_R4_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600986 */ uint8_t RESERVED_142[504]; __IO uint16_t TXDQDLYTG0_R5_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600B80 */ __IO uint16_t TXDQDLYTG1_R5_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600B82 */ __IO uint16_t TXDQDLYTG2_R5_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600B84 */ __IO uint16_t TXDQDLYTG3_R5_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600B86 */ uint8_t RESERVED_143[504]; __IO uint16_t TXDQDLYTG0_R6_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600D80 */ __IO uint16_t TXDQDLYTG1_R6_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600D82 */ __IO uint16_t TXDQDLYTG2_R6_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600D84 */ __IO uint16_t TXDQDLYTG3_R6_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600D86 */ uint8_t RESERVED_144[504]; __IO uint16_t TXDQDLYTG0_R7_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600F80 */ __IO uint16_t TXDQDLYTG1_R7_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600F82 */ __IO uint16_t TXDQDLYTG2_R7_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600F84 */ __IO uint16_t TXDQDLYTG3_R7_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600F86 */ uint8_t RESERVED_145[504]; __IO uint16_t TXDQDLYTG0_R8_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x601180 */ __IO uint16_t TXDQDLYTG1_R8_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x601182 */ __IO uint16_t TXDQDLYTG2_R8_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x601184 */ __IO uint16_t TXDQDLYTG3_R8_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x601186 */ } DWC_DDRPHYA_DBYTE_Type; /* ---------------------------------------------------------------------------- -- DWC_DDRPHYA_DBYTE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DWC_DDRPHYA_DBYTE_Register_Masks DWC_DDRPHYA_DBYTE Register Masks * @{ */ /*! @name DBYTEMISCMODE - DBYTE Module Disable */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DByteDisable_MASK (0x4U) #define DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DByteDisable_SHIFT (2U) #define DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DByteDisable(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DByteDisable_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DByteDisable_MASK) /*! @} */ /*! @name MTESTMUXSEL - Digital Observation Pin control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MtestMuxSel_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MtestMuxSel_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MtestMuxSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MtestMuxSel_SHIFT)) & \ DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MtestMuxSel_MASK) /*! @} */ /*! @name DFIMRL_P0 - DFI MaxReadLatency */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_p0_MASK (0x1FU) #define DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_p0_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_p0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_p0_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_p0_MASK) /*! @} */ /*! @name VREFDAC1_R0 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VrefDAC1_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VrefDAC1_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VrefDAC1_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VrefDAC1_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VrefDAC1_rx_MASK) /*! @} */ /*! @name VREFDAC0_R0 - VrefDAC0 control for DQ Receiver */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VrefDAC0_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VrefDAC0_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VrefDAC0_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VrefDAC0_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VrefDAC0_rx_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL0_B0_P0 - Data TX impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqN_MASK) /*! @} */ /*! @name DQDQSRCVCNTRL_B0_P0 - Dq/Dqs receiver control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SelAnalogVref_MASK (0x1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SelAnalogVref_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SelAnalogVref(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SelAnalogVref_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SelAnalogVref_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_ExtVrefRange_MASK (0x2U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_ExtVrefRange_SHIFT (1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_ExtVrefRange(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_ExtVrefRange_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_ExtVrefRange_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DfeCtrl_MASK (0xCU) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DfeCtrl_SHIFT (2U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DfeCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DfeCtrl_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DfeCtrl_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MajorModeDbyte_MASK (0x70U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MajorModeDbyte_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MajorModeDbyte(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MajorModeDbyte_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MajorModeDbyte_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GainCurrAdj_MASK (0xF80U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GainCurrAdj_SHIFT (7U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GainCurrAdj(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GainCurrAdj_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GainCurrAdj_MASK) /*! @} */ /*! @name TXEQUALIZATIONMODE_P0 - Tx dq driver equalization mode controls. */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TxEqMode_MASK (0x3U) #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TxEqMode_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TxEqMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TxEqMode_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TxEqMode_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL1_B0_P0 - TX impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqN_MASK) /*! @} */ /*! @name DQDQSRCVCNTRL1 - Dq/Dqs receiver control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvr_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvr_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvr_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvr_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvrDqs_MASK (0x200U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvrDqs_SHIFT (9U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvrDqs(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvrDqs_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvrDqs_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RxPadStandbyEn_MASK (0x400U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RxPadStandbyEn_SHIFT (10U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RxPadStandbyEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RxPadStandbyEn_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RxPadStandbyEn_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_EnLPReqPDR_MASK (0x800U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_EnLPReqPDR_SHIFT (11U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_EnLPReqPDR(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_EnLPReqPDR_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_EnLPReqPDR_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL2_B0_P0 - TX equalization impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQHiDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQHiDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQHiDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQHiDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQHiDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQLoDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQLoDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQLoDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQLoDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQLoDqN_MASK) /*! @} */ /*! @name DQDQSRCVCNTRL2_P0 - Dq/Dqs receiver control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_EnRxAgressivePDR_MASK (0x1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_EnRxAgressivePDR_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_EnRxAgressivePDR(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_EnRxAgressivePDR_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_EnRxAgressivePDR_MASK) /*! @} */ /*! @name TXODTDRVSTREN_B0_P0 - TX ODT driver strength control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenP_MASK) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenN_MASK) /*! @} */ /*! @name RXFIFOCHECKSTATUS - Status of RX FIFO Consistency Checks */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocErr_MASK (0x1U) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocErr_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocErr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocErr_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocErr_MASK) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocErr_MASK (0x2U) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocErr_SHIFT (1U) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocErr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocErr_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocErr_MASK) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocUErr_MASK (0x4U) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocUErr_SHIFT (2U) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocUErr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocUErr_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocUErr_MASK) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocUErr_MASK (0x8U) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocUErr_SHIFT (3U) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocUErr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocUErr_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocUErr_MASK) /*! @} */ /*! @name RXFIFOCHECKERRVALUES - Contains the captured values associated with an RxFifo consistency error */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocErrValue_MASK (0xFU) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocErrValue_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocErrValue(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocErrValue_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocErrValue_MASK) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocErrValue_MASK (0xF0U) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocErrValue_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocErrValue(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocErrValue_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocErrValue_MASK) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocUErrValue_MASK (0xF00U) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocUErrValue_SHIFT (8U) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocUErrValue(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocUErrValue_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocUErrValue_MASK) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocUErrValue_MASK (0xF000U) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocUErrValue_SHIFT (12U) #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocUErrValue(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocUErrValue_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocUErrValue_MASK) /*! @} */ /*! @name RXFIFOINFO - Data Receive FIFO Pointer Values */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLoc_MASK (0xFU) #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLoc_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLoc(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLoc_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLoc_MASK) #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLoc_MASK (0xF0U) #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLoc_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLoc(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLoc_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLoc_MASK) #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLocU_MASK (0xF00U) #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLocU_SHIFT (8U) #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLocU(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLocU_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLocU_MASK) #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLocU_MASK (0xF000U) #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLocU_SHIFT (12U) #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLocU(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLocU_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLocU_MASK) /*! @} */ /*! @name RXFIFOVISIBILITY - RX FIFO visibility */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtr_MASK (0x7U) #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtr_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtr_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtr_MASK) #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtrOvr_MASK (0x8U) #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtrOvr_SHIFT (3U) #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtrOvr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtrOvr_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtrOvr_MASK) #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdEn_MASK (0x10U) #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdEn_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdEn_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdEn_MASK) /*! @} */ /*! @name RXFIFOCONTENTSDQ3210 - RX FIFO contents, lane[3:0] */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RxFifoContentsDQ3210_MASK (0xFFFFU) #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RxFifoContentsDQ3210_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RxFifoContentsDQ3210(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RxFifoContentsDQ3210_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RxFifoContentsDQ3210_MASK) /*! @} */ /*! @name RXFIFOCONTENTSDQ7654 - RX FIFO contents, lane[7:4] */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RxFifoContentsDQ7654_MASK (0xFFFFU) #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RxFifoContentsDQ7654_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RxFifoContentsDQ7654(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RxFifoContentsDQ7654_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RxFifoContentsDQ7654_MASK) /*! @} */ /*! @name RXFIFOCONTENTSDBI - RX FIFO contents, dbi */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RxFifoContentsDBI_MASK (0xFU) #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RxFifoContentsDBI_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RxFifoContentsDBI(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RxFifoContentsDBI_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RxFifoContentsDBI_MASK) /*! @} */ /*! @name TXSLEWRATE_B0_P0 - TX slew rate controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreP_MASK (0xFU) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreP_MASK) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreN_MASK (0xF0U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreN_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreN_MASK) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreDrvMode_MASK (0x700U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreDrvMode_SHIFT (8U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreDrvMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreDrvMode_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreDrvMode_MASK) /*! @} */ /*! @name RXPBDLYTG0_R0 - Read DQ per-bit BDL delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RxPBDlyTg0_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RxPBDlyTg0_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RxPBDlyTg0_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RxPBDlyTg0_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RxPBDlyTg0_rx_MASK) /*! @} */ /*! @name RXPBDLYTG1_R0 - Read DQ per-bit BDL delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RxPBDlyTg1_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RxPBDlyTg1_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RxPBDlyTg1_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RxPBDlyTg1_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RxPBDlyTg1_rx_MASK) /*! @} */ /*! @name RXPBDLYTG2_R0 - Read DQ per-bit BDL delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RxPBDlyTg2_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RxPBDlyTg2_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RxPBDlyTg2_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RxPBDlyTg2_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RxPBDlyTg2_rx_MASK) /*! @} */ /*! @name RXPBDLYTG3_R0 - Read DQ per-bit BDL delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RxPBDlyTg3_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RxPBDlyTg3_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RxPBDlyTg3_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RxPBDlyTg3_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RxPBDlyTg3_rx_MASK) /*! @} */ /*! @name RXENDLYTG0_U0_P0 - Trained Receive Enable Delay (For Timing Group 0) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RxEnDlyTg0_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RxEnDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RxEnDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RxEnDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RxEnDlyTg0_un_px_MASK) /*! @} */ /*! @name RXENDLYTG1_U0_P0 - Trained Receive Enable Delay (For Timing Group 1) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RxEnDlyTg1_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RxEnDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RxEnDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RxEnDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RxEnDlyTg1_un_px_MASK) /*! @} */ /*! @name RXENDLYTG2_U0_P0 - Trained Receive Enable Delay (For Timing Group 2) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RxEnDlyTg2_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RxEnDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RxEnDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RxEnDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RxEnDlyTg2_un_px_MASK) /*! @} */ /*! @name RXENDLYTG3_U0_P0 - Trained Receive Enable Delay (For Timing Group 3) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RxEnDlyTg3_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RxEnDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RxEnDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RxEnDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RxEnDlyTg3_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG0_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RxClkDlyTg0_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RxClkDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RxClkDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RxClkDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RxClkDlyTg0_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG1_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RxClkDlyTg1_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RxClkDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RxClkDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RxClkDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RxClkDlyTg1_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG2_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RxClkDlyTg2_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RxClkDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RxClkDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RxClkDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RxClkDlyTg2_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG3_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RxClkDlyTg3_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RxClkDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RxClkDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RxClkDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RxClkDlyTg3_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG0_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RxClkcDlyTg0_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RxClkcDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RxClkcDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RxClkcDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RxClkcDlyTg0_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG1_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RxClkcDlyTg1_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RxClkcDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RxClkcDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RxClkcDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RxClkcDlyTg1_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG2_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RxClkcDlyTg2_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RxClkcDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RxClkcDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RxClkcDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RxClkcDlyTg2_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG3_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RxClkcDlyTg3_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RxClkcDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RxClkcDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RxClkcDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RxClkcDlyTg3_un_px_MASK) /*! @} */ /*! @name DQLNSEL - Maps Phy DQ lane to memory DQ0 */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DQLNSEL_DqLnSel_MASK (0x7U) #define DWC_DDRPHYA_DBYTE_DQLNSEL_DqLnSel_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DQLNSEL_DqLnSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQLNSEL_DqLnSel_SHIFT)) & DWC_DDRPHYA_DBYTE_DQLNSEL_DqLnSel_MASK) /*! @} */ /* The count of DWC_DDRPHYA_DBYTE_DQLNSEL */ #define DWC_DDRPHYA_DBYTE_DQLNSEL_COUNT (8U) /*! @name TXDQDLYTG0_R0_P0 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R0_P0 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R0_P0 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R0_P0 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQSDLYTG0_U0_P0 - Write DQS Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TxDqsDlyTg0_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TxDqsDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TxDqsDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TxDqsDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TxDqsDlyTg0_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG1_U0_P0 - Write DQS Delay (Timing Group DEST=1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TxDqsDlyTg1_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TxDqsDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TxDqsDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TxDqsDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TxDqsDlyTg1_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG2_U0_P0 - Write DQS Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TxDqsDlyTg2_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TxDqsDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TxDqsDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TxDqsDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TxDqsDlyTg2_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG3_U0_P0 - Write DQS Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TxDqsDlyTg3_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TxDqsDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TxDqsDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TxDqsDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TxDqsDlyTg3_un_px_MASK) /*! @} */ /*! @name DXLCDLSTATUS - Debug status of the DBYTE LCDL */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlFineSnapVal_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlFineSnapVal_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlFineSnapVal(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlFineSnapVal_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlFineSnapVal_MASK) #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlPhdSnapVal_MASK (0x400U) #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlPhdSnapVal_SHIFT (10U) #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlPhdSnapVal(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlPhdSnapVal_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlPhdSnapVal_MASK) #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyLock_MASK (0x800U) #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyLock_SHIFT (11U) #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyLock(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyLock_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyLock_MASK) #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyUnlock_MASK (0x1000U) #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyUnlock_SHIFT (12U) #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyUnlock(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyUnlock_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyUnlock_MASK) #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlLiveLock_MASK (0x2000U) #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlLiveLock_SHIFT (13U) #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlLiveLock(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlLiveLock_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlLiveLock_MASK) /*! @} */ /*! @name VREFDAC1_R1 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VrefDAC1_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VrefDAC1_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VrefDAC1_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VrefDAC1_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VrefDAC1_rx_MASK) /*! @} */ /*! @name VREFDAC0_R1 - VrefDAC0 control for DQ Receiver */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VrefDAC0_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VrefDAC0_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VrefDAC0_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VrefDAC0_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VrefDAC0_rx_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL0_B1_P0 - Data TX impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqN_MASK) /*! @} */ /*! @name DQDQSRCVCNTRL_B1_P0 - Dq/Dqs receiver control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SelAnalogVref_MASK (0x1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SelAnalogVref_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SelAnalogVref(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SelAnalogVref_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SelAnalogVref_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_ExtVrefRange_MASK (0x2U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_ExtVrefRange_SHIFT (1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_ExtVrefRange(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_ExtVrefRange_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_ExtVrefRange_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DfeCtrl_MASK (0xCU) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DfeCtrl_SHIFT (2U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DfeCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DfeCtrl_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DfeCtrl_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MajorModeDbyte_MASK (0x70U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MajorModeDbyte_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MajorModeDbyte(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MajorModeDbyte_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MajorModeDbyte_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GainCurrAdj_MASK (0xF80U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GainCurrAdj_SHIFT (7U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GainCurrAdj(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GainCurrAdj_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GainCurrAdj_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL1_B1_P0 - TX impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqN_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL2_B1_P0 - TX equalization impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQHiDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQHiDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQHiDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQHiDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQHiDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQLoDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQLoDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQLoDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQLoDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQLoDqN_MASK) /*! @} */ /*! @name TXODTDRVSTREN_B1_P0 - TX ODT driver strength control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenP_MASK) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenN_MASK) /*! @} */ /*! @name TXSLEWRATE_B1_P0 - TX slew rate controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreP_MASK (0xFU) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreP_MASK) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreN_MASK (0xF0U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreN_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreN_MASK) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreDrvMode_MASK (0x700U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreDrvMode_SHIFT (8U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreDrvMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreDrvMode_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreDrvMode_MASK) /*! @} */ /*! @name RXPBDLYTG0_R1 - Read DQ per-bit BDL delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RxPBDlyTg0_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RxPBDlyTg0_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RxPBDlyTg0_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RxPBDlyTg0_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RxPBDlyTg0_rx_MASK) /*! @} */ /*! @name RXPBDLYTG1_R1 - Read DQ per-bit BDL delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RxPBDlyTg1_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RxPBDlyTg1_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RxPBDlyTg1_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RxPBDlyTg1_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RxPBDlyTg1_rx_MASK) /*! @} */ /*! @name RXPBDLYTG2_R1 - Read DQ per-bit BDL delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RxPBDlyTg2_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RxPBDlyTg2_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RxPBDlyTg2_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RxPBDlyTg2_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RxPBDlyTg2_rx_MASK) /*! @} */ /*! @name RXPBDLYTG3_R1 - Read DQ per-bit BDL delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RxPBDlyTg3_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RxPBDlyTg3_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RxPBDlyTg3_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RxPBDlyTg3_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RxPBDlyTg3_rx_MASK) /*! @} */ /*! @name RXENDLYTG0_U1_P0 - Trained Receive Enable Delay (For Timing Group 0) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RxEnDlyTg0_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RxEnDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RxEnDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RxEnDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RxEnDlyTg0_un_px_MASK) /*! @} */ /*! @name RXENDLYTG1_U1_P0 - Trained Receive Enable Delay (For Timing Group 1) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RxEnDlyTg1_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RxEnDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RxEnDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RxEnDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RxEnDlyTg1_un_px_MASK) /*! @} */ /*! @name RXENDLYTG2_U1_P0 - Trained Receive Enable Delay (For Timing Group 2) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RxEnDlyTg2_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RxEnDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RxEnDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RxEnDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RxEnDlyTg2_un_px_MASK) /*! @} */ /*! @name RXENDLYTG3_U1_P0 - Trained Receive Enable Delay (For Timing Group 3) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RxEnDlyTg3_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RxEnDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RxEnDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RxEnDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RxEnDlyTg3_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG0_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RxClkDlyTg0_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RxClkDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RxClkDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RxClkDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RxClkDlyTg0_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG1_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RxClkDlyTg1_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RxClkDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RxClkDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RxClkDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RxClkDlyTg1_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG2_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RxClkDlyTg2_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RxClkDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RxClkDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RxClkDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RxClkDlyTg2_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG3_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RxClkDlyTg3_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RxClkDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RxClkDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RxClkDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RxClkDlyTg3_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG0_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RxClkcDlyTg0_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RxClkcDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RxClkcDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RxClkcDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RxClkcDlyTg0_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG1_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RxClkcDlyTg1_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RxClkcDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RxClkcDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RxClkcDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RxClkcDlyTg1_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG2_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RxClkcDlyTg2_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RxClkcDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RxClkcDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RxClkcDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RxClkcDlyTg2_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG3_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RxClkcDlyTg3_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RxClkcDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RxClkcDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RxClkcDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RxClkcDlyTg3_un_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R1_P0 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R1_P0 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R1_P0 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R1_P0 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQSDLYTG0_U1_P0 - Write DQS Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TxDqsDlyTg0_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TxDqsDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TxDqsDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TxDqsDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TxDqsDlyTg0_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG1_U1_P0 - Write DQS Delay (Timing Group DEST=1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TxDqsDlyTg1_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TxDqsDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TxDqsDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TxDqsDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TxDqsDlyTg1_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG2_U1_P0 - Write DQS Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TxDqsDlyTg2_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TxDqsDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TxDqsDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TxDqsDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TxDqsDlyTg2_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG3_U1_P0 - Write DQS Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TxDqsDlyTg3_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TxDqsDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TxDqsDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TxDqsDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TxDqsDlyTg3_un_px_MASK) /*! @} */ /*! @name VREFDAC1_R2 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VrefDAC1_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VrefDAC1_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VrefDAC1_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VrefDAC1_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VrefDAC1_rx_MASK) /*! @} */ /*! @name VREFDAC0_R2 - VrefDAC0 control for DQ Receiver */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VrefDAC0_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VrefDAC0_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VrefDAC0_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VrefDAC0_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VrefDAC0_rx_MASK) /*! @} */ /*! @name RXPBDLYTG0_R2 - Read DQ per-bit BDL delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RxPBDlyTg0_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RxPBDlyTg0_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RxPBDlyTg0_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RxPBDlyTg0_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RxPBDlyTg0_rx_MASK) /*! @} */ /*! @name RXPBDLYTG1_R2 - Read DQ per-bit BDL delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RxPBDlyTg1_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RxPBDlyTg1_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RxPBDlyTg1_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RxPBDlyTg1_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RxPBDlyTg1_rx_MASK) /*! @} */ /*! @name RXPBDLYTG2_R2 - Read DQ per-bit BDL delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RxPBDlyTg2_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RxPBDlyTg2_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RxPBDlyTg2_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RxPBDlyTg2_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RxPBDlyTg2_rx_MASK) /*! @} */ /*! @name RXPBDLYTG3_R2 - Read DQ per-bit BDL delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RxPBDlyTg3_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RxPBDlyTg3_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RxPBDlyTg3_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RxPBDlyTg3_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RxPBDlyTg3_rx_MASK) /*! @} */ /*! @name TXDQDLYTG0_R2_P0 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R2_P0 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R2_P0 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R2_P0 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name VREFDAC1_R3 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VrefDAC1_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VrefDAC1_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VrefDAC1_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VrefDAC1_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VrefDAC1_rx_MASK) /*! @} */ /*! @name VREFDAC0_R3 - VrefDAC0 control for DQ Receiver */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VrefDAC0_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VrefDAC0_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VrefDAC0_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VrefDAC0_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VrefDAC0_rx_MASK) /*! @} */ /*! @name RXPBDLYTG0_R3 - Read DQ per-bit BDL delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RxPBDlyTg0_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RxPBDlyTg0_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RxPBDlyTg0_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RxPBDlyTg0_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RxPBDlyTg0_rx_MASK) /*! @} */ /*! @name RXPBDLYTG1_R3 - Read DQ per-bit BDL delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RxPBDlyTg1_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RxPBDlyTg1_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RxPBDlyTg1_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RxPBDlyTg1_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RxPBDlyTg1_rx_MASK) /*! @} */ /*! @name RXPBDLYTG2_R3 - Read DQ per-bit BDL delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RxPBDlyTg2_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RxPBDlyTg2_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RxPBDlyTg2_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RxPBDlyTg2_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RxPBDlyTg2_rx_MASK) /*! @} */ /*! @name RXPBDLYTG3_R3 - Read DQ per-bit BDL delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RxPBDlyTg3_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RxPBDlyTg3_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RxPBDlyTg3_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RxPBDlyTg3_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RxPBDlyTg3_rx_MASK) /*! @} */ /*! @name TXDQDLYTG0_R3_P0 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R3_P0 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R3_P0 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R3_P0 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name VREFDAC1_R4 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VrefDAC1_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VrefDAC1_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VrefDAC1_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VrefDAC1_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VrefDAC1_rx_MASK) /*! @} */ /*! @name VREFDAC0_R4 - VrefDAC0 control for DQ Receiver */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VrefDAC0_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VrefDAC0_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VrefDAC0_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VrefDAC0_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VrefDAC0_rx_MASK) /*! @} */ /*! @name RXPBDLYTG0_R4 - Read DQ per-bit BDL delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RxPBDlyTg0_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RxPBDlyTg0_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RxPBDlyTg0_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RxPBDlyTg0_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RxPBDlyTg0_rx_MASK) /*! @} */ /*! @name RXPBDLYTG1_R4 - Read DQ per-bit BDL delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RxPBDlyTg1_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RxPBDlyTg1_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RxPBDlyTg1_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RxPBDlyTg1_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RxPBDlyTg1_rx_MASK) /*! @} */ /*! @name RXPBDLYTG2_R4 - Read DQ per-bit BDL delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RxPBDlyTg2_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RxPBDlyTg2_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RxPBDlyTg2_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RxPBDlyTg2_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RxPBDlyTg2_rx_MASK) /*! @} */ /*! @name RXPBDLYTG3_R4 - Read DQ per-bit BDL delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RxPBDlyTg3_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RxPBDlyTg3_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RxPBDlyTg3_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RxPBDlyTg3_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RxPBDlyTg3_rx_MASK) /*! @} */ /*! @name TXDQDLYTG0_R4_P0 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R4_P0 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R4_P0 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R4_P0 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name VREFDAC1_R5 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VrefDAC1_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VrefDAC1_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VrefDAC1_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VrefDAC1_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VrefDAC1_rx_MASK) /*! @} */ /*! @name VREFDAC0_R5 - VrefDAC0 control for DQ Receiver */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VrefDAC0_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VrefDAC0_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VrefDAC0_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VrefDAC0_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VrefDAC0_rx_MASK) /*! @} */ /*! @name RXPBDLYTG0_R5 - Read DQ per-bit BDL delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RxPBDlyTg0_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RxPBDlyTg0_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RxPBDlyTg0_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RxPBDlyTg0_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RxPBDlyTg0_rx_MASK) /*! @} */ /*! @name RXPBDLYTG1_R5 - Read DQ per-bit BDL delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RxPBDlyTg1_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RxPBDlyTg1_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RxPBDlyTg1_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RxPBDlyTg1_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RxPBDlyTg1_rx_MASK) /*! @} */ /*! @name RXPBDLYTG2_R5 - Read DQ per-bit BDL delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RxPBDlyTg2_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RxPBDlyTg2_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RxPBDlyTg2_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RxPBDlyTg2_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RxPBDlyTg2_rx_MASK) /*! @} */ /*! @name RXPBDLYTG3_R5 - Read DQ per-bit BDL delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RxPBDlyTg3_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RxPBDlyTg3_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RxPBDlyTg3_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RxPBDlyTg3_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RxPBDlyTg3_rx_MASK) /*! @} */ /*! @name TXDQDLYTG0_R5_P0 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R5_P0 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R5_P0 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R5_P0 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name VREFDAC1_R6 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VrefDAC1_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VrefDAC1_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VrefDAC1_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VrefDAC1_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VrefDAC1_rx_MASK) /*! @} */ /*! @name VREFDAC0_R6 - VrefDAC0 control for DQ Receiver */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VrefDAC0_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VrefDAC0_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VrefDAC0_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VrefDAC0_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VrefDAC0_rx_MASK) /*! @} */ /*! @name RXPBDLYTG0_R6 - Read DQ per-bit BDL delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RxPBDlyTg0_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RxPBDlyTg0_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RxPBDlyTg0_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RxPBDlyTg0_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RxPBDlyTg0_rx_MASK) /*! @} */ /*! @name RXPBDLYTG1_R6 - Read DQ per-bit BDL delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RxPBDlyTg1_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RxPBDlyTg1_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RxPBDlyTg1_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RxPBDlyTg1_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RxPBDlyTg1_rx_MASK) /*! @} */ /*! @name RXPBDLYTG2_R6 - Read DQ per-bit BDL delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RxPBDlyTg2_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RxPBDlyTg2_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RxPBDlyTg2_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RxPBDlyTg2_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RxPBDlyTg2_rx_MASK) /*! @} */ /*! @name RXPBDLYTG3_R6 - Read DQ per-bit BDL delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RxPBDlyTg3_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RxPBDlyTg3_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RxPBDlyTg3_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RxPBDlyTg3_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RxPBDlyTg3_rx_MASK) /*! @} */ /*! @name TXDQDLYTG0_R6_P0 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R6_P0 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R6_P0 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R6_P0 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name VREFDAC1_R7 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VrefDAC1_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VrefDAC1_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VrefDAC1_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VrefDAC1_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VrefDAC1_rx_MASK) /*! @} */ /*! @name VREFDAC0_R7 - VrefDAC0 control for DQ Receiver */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VrefDAC0_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VrefDAC0_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VrefDAC0_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VrefDAC0_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VrefDAC0_rx_MASK) /*! @} */ /*! @name RXPBDLYTG0_R7 - Read DQ per-bit BDL delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RxPBDlyTg0_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RxPBDlyTg0_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RxPBDlyTg0_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RxPBDlyTg0_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RxPBDlyTg0_rx_MASK) /*! @} */ /*! @name RXPBDLYTG1_R7 - Read DQ per-bit BDL delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RxPBDlyTg1_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RxPBDlyTg1_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RxPBDlyTg1_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RxPBDlyTg1_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RxPBDlyTg1_rx_MASK) /*! @} */ /*! @name RXPBDLYTG2_R7 - Read DQ per-bit BDL delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RxPBDlyTg2_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RxPBDlyTg2_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RxPBDlyTg2_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RxPBDlyTg2_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RxPBDlyTg2_rx_MASK) /*! @} */ /*! @name RXPBDLYTG3_R7 - Read DQ per-bit BDL delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RxPBDlyTg3_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RxPBDlyTg3_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RxPBDlyTg3_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RxPBDlyTg3_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RxPBDlyTg3_rx_MASK) /*! @} */ /*! @name TXDQDLYTG0_R7_P0 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R7_P0 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R7_P0 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R7_P0 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name VREFDAC1_R8 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VrefDAC1_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VrefDAC1_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VrefDAC1_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VrefDAC1_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VrefDAC1_rx_MASK) /*! @} */ /*! @name VREFDAC0_R8 - VrefDAC0 control for DQ Receiver */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VrefDAC0_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VrefDAC0_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VrefDAC0_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VrefDAC0_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VrefDAC0_rx_MASK) /*! @} */ /*! @name RXPBDLYTG0_R8 - Read DQ per-bit BDL delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RxPBDlyTg0_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RxPBDlyTg0_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RxPBDlyTg0_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RxPBDlyTg0_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RxPBDlyTg0_rx_MASK) /*! @} */ /*! @name RXPBDLYTG1_R8 - Read DQ per-bit BDL delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RxPBDlyTg1_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RxPBDlyTg1_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RxPBDlyTg1_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RxPBDlyTg1_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RxPBDlyTg1_rx_MASK) /*! @} */ /*! @name RXPBDLYTG2_R8 - Read DQ per-bit BDL delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RxPBDlyTg2_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RxPBDlyTg2_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RxPBDlyTg2_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RxPBDlyTg2_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RxPBDlyTg2_rx_MASK) /*! @} */ /*! @name RXPBDLYTG3_R8 - Read DQ per-bit BDL delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RxPBDlyTg3_rx_MASK (0x7FU) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RxPBDlyTg3_rx_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RxPBDlyTg3_rx(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RxPBDlyTg3_rx_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RxPBDlyTg3_rx_MASK) /*! @} */ /*! @name TXDQDLYTG0_R8_P0 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R8_P0 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R8_P0 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R8_P0 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name DFIMRL_P1 - DFI MaxReadLatency */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_p1_MASK (0x1FU) #define DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_p1_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_p1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_p1_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_p1_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL0_B0_P1 - Data TX impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqN_MASK) /*! @} */ /*! @name DQDQSRCVCNTRL_B0_P1 - Dq/Dqs receiver control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SelAnalogVref_MASK (0x1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SelAnalogVref_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SelAnalogVref(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SelAnalogVref_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SelAnalogVref_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_ExtVrefRange_MASK (0x2U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_ExtVrefRange_SHIFT (1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_ExtVrefRange(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_ExtVrefRange_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_ExtVrefRange_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DfeCtrl_MASK (0xCU) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DfeCtrl_SHIFT (2U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DfeCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DfeCtrl_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DfeCtrl_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MajorModeDbyte_MASK (0x70U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MajorModeDbyte_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MajorModeDbyte(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MajorModeDbyte_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MajorModeDbyte_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GainCurrAdj_MASK (0xF80U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GainCurrAdj_SHIFT (7U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GainCurrAdj(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GainCurrAdj_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GainCurrAdj_MASK) /*! @} */ /*! @name TXEQUALIZATIONMODE_P1 - Tx dq driver equalization mode controls. */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TxEqMode_MASK (0x3U) #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TxEqMode_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TxEqMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TxEqMode_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TxEqMode_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL1_B0_P1 - TX impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqN_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL2_B0_P1 - TX equalization impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQHiDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQHiDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQHiDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQHiDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQHiDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQLoDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQLoDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQLoDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQLoDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQLoDqN_MASK) /*! @} */ /*! @name DQDQSRCVCNTRL2_P1 - Dq/Dqs receiver control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_EnRxAgressivePDR_MASK (0x1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_EnRxAgressivePDR_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_EnRxAgressivePDR(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_EnRxAgressivePDR_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_EnRxAgressivePDR_MASK) /*! @} */ /*! @name TXODTDRVSTREN_B0_P1 - TX ODT driver strength control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenP_MASK) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenN_MASK) /*! @} */ /*! @name TXSLEWRATE_B0_P1 - TX slew rate controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreP_MASK (0xFU) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreP_MASK) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreN_MASK (0xF0U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreN_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreN_MASK) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreDrvMode_MASK (0x700U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreDrvMode_SHIFT (8U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreDrvMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreDrvMode_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreDrvMode_MASK) /*! @} */ /*! @name RXENDLYTG0_U0_P1 - Trained Receive Enable Delay (For Timing Group 0) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RxEnDlyTg0_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RxEnDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RxEnDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RxEnDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RxEnDlyTg0_un_px_MASK) /*! @} */ /*! @name RXENDLYTG1_U0_P1 - Trained Receive Enable Delay (For Timing Group 1) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RxEnDlyTg1_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RxEnDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RxEnDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RxEnDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RxEnDlyTg1_un_px_MASK) /*! @} */ /*! @name RXENDLYTG2_U0_P1 - Trained Receive Enable Delay (For Timing Group 2) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RxEnDlyTg2_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RxEnDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RxEnDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RxEnDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RxEnDlyTg2_un_px_MASK) /*! @} */ /*! @name RXENDLYTG3_U0_P1 - Trained Receive Enable Delay (For Timing Group 3) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RxEnDlyTg3_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RxEnDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RxEnDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RxEnDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RxEnDlyTg3_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG0_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RxClkDlyTg0_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RxClkDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RxClkDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RxClkDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RxClkDlyTg0_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG1_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RxClkDlyTg1_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RxClkDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RxClkDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RxClkDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RxClkDlyTg1_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG2_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RxClkDlyTg2_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RxClkDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RxClkDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RxClkDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RxClkDlyTg2_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG3_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RxClkDlyTg3_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RxClkDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RxClkDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RxClkDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RxClkDlyTg3_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG0_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RxClkcDlyTg0_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RxClkcDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RxClkcDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RxClkcDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RxClkcDlyTg0_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG1_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RxClkcDlyTg1_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RxClkcDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RxClkcDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RxClkcDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RxClkcDlyTg1_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG2_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RxClkcDlyTg2_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RxClkcDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RxClkcDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RxClkcDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RxClkcDlyTg2_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG3_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RxClkcDlyTg3_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RxClkcDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RxClkcDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RxClkcDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RxClkcDlyTg3_un_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R0_P1 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R0_P1 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R0_P1 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R0_P1 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQSDLYTG0_U0_P1 - Write DQS Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TxDqsDlyTg0_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TxDqsDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TxDqsDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TxDqsDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TxDqsDlyTg0_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG1_U0_P1 - Write DQS Delay (Timing Group DEST=1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TxDqsDlyTg1_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TxDqsDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TxDqsDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TxDqsDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TxDqsDlyTg1_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG2_U0_P1 - Write DQS Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TxDqsDlyTg2_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TxDqsDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TxDqsDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TxDqsDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TxDqsDlyTg2_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG3_U0_P1 - Write DQS Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TxDqsDlyTg3_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TxDqsDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TxDqsDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TxDqsDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TxDqsDlyTg3_un_px_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL0_B1_P1 - Data TX impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqN_MASK) /*! @} */ /*! @name DQDQSRCVCNTRL_B1_P1 - Dq/Dqs receiver control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SelAnalogVref_MASK (0x1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SelAnalogVref_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SelAnalogVref(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SelAnalogVref_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SelAnalogVref_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_ExtVrefRange_MASK (0x2U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_ExtVrefRange_SHIFT (1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_ExtVrefRange(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_ExtVrefRange_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_ExtVrefRange_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DfeCtrl_MASK (0xCU) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DfeCtrl_SHIFT (2U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DfeCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DfeCtrl_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DfeCtrl_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MajorModeDbyte_MASK (0x70U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MajorModeDbyte_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MajorModeDbyte(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MajorModeDbyte_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MajorModeDbyte_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GainCurrAdj_MASK (0xF80U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GainCurrAdj_SHIFT (7U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GainCurrAdj(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GainCurrAdj_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GainCurrAdj_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL1_B1_P1 - TX impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqN_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL2_B1_P1 - TX equalization impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQHiDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQHiDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQHiDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQHiDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQHiDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQLoDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQLoDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQLoDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQLoDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQLoDqN_MASK) /*! @} */ /*! @name TXODTDRVSTREN_B1_P1 - TX ODT driver strength control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenP_MASK) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenN_MASK) /*! @} */ /*! @name TXSLEWRATE_B1_P1 - TX slew rate controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreP_MASK (0xFU) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreP_MASK) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreN_MASK (0xF0U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreN_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreN_MASK) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreDrvMode_MASK (0x700U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreDrvMode_SHIFT (8U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreDrvMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreDrvMode_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreDrvMode_MASK) /*! @} */ /*! @name RXENDLYTG0_U1_P1 - Trained Receive Enable Delay (For Timing Group 0) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RxEnDlyTg0_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RxEnDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RxEnDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RxEnDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RxEnDlyTg0_un_px_MASK) /*! @} */ /*! @name RXENDLYTG1_U1_P1 - Trained Receive Enable Delay (For Timing Group 1) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RxEnDlyTg1_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RxEnDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RxEnDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RxEnDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RxEnDlyTg1_un_px_MASK) /*! @} */ /*! @name RXENDLYTG2_U1_P1 - Trained Receive Enable Delay (For Timing Group 2) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RxEnDlyTg2_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RxEnDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RxEnDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RxEnDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RxEnDlyTg2_un_px_MASK) /*! @} */ /*! @name RXENDLYTG3_U1_P1 - Trained Receive Enable Delay (For Timing Group 3) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RxEnDlyTg3_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RxEnDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RxEnDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RxEnDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RxEnDlyTg3_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG0_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RxClkDlyTg0_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RxClkDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RxClkDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RxClkDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RxClkDlyTg0_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG1_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RxClkDlyTg1_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RxClkDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RxClkDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RxClkDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RxClkDlyTg1_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG2_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RxClkDlyTg2_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RxClkDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RxClkDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RxClkDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RxClkDlyTg2_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG3_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RxClkDlyTg3_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RxClkDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RxClkDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RxClkDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RxClkDlyTg3_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG0_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RxClkcDlyTg0_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RxClkcDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RxClkcDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RxClkcDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RxClkcDlyTg0_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG1_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RxClkcDlyTg1_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RxClkcDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RxClkcDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RxClkcDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RxClkcDlyTg1_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG2_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RxClkcDlyTg2_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RxClkcDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RxClkcDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RxClkcDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RxClkcDlyTg2_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG3_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RxClkcDlyTg3_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RxClkcDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RxClkcDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RxClkcDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RxClkcDlyTg3_un_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R1_P1 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R1_P1 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R1_P1 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R1_P1 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQSDLYTG0_U1_P1 - Write DQS Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TxDqsDlyTg0_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TxDqsDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TxDqsDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TxDqsDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TxDqsDlyTg0_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG1_U1_P1 - Write DQS Delay (Timing Group DEST=1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TxDqsDlyTg1_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TxDqsDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TxDqsDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TxDqsDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TxDqsDlyTg1_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG2_U1_P1 - Write DQS Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TxDqsDlyTg2_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TxDqsDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TxDqsDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TxDqsDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TxDqsDlyTg2_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG3_U1_P1 - Write DQS Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TxDqsDlyTg3_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TxDqsDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TxDqsDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TxDqsDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TxDqsDlyTg3_un_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R2_P1 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R2_P1 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R2_P1 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R2_P1 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R3_P1 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R3_P1 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R3_P1 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R3_P1 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R4_P1 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R4_P1 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R4_P1 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R4_P1 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R5_P1 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R5_P1 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R5_P1 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R5_P1 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R6_P1 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R6_P1 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R6_P1 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R6_P1 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R7_P1 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R7_P1 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R7_P1 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R7_P1 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R8_P1 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R8_P1 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R8_P1 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R8_P1 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name DFIMRL_P2 - DFI MaxReadLatency */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_p2_MASK (0x1FU) #define DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_p2_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_p2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_p2_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_p2_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL0_B0_P2 - Data TX impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqN_MASK) /*! @} */ /*! @name DQDQSRCVCNTRL_B0_P2 - Dq/Dqs receiver control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SelAnalogVref_MASK (0x1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SelAnalogVref_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SelAnalogVref(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SelAnalogVref_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SelAnalogVref_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_ExtVrefRange_MASK (0x2U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_ExtVrefRange_SHIFT (1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_ExtVrefRange(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_ExtVrefRange_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_ExtVrefRange_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DfeCtrl_MASK (0xCU) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DfeCtrl_SHIFT (2U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DfeCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DfeCtrl_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DfeCtrl_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MajorModeDbyte_MASK (0x70U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MajorModeDbyte_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MajorModeDbyte(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MajorModeDbyte_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MajorModeDbyte_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GainCurrAdj_MASK (0xF80U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GainCurrAdj_SHIFT (7U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GainCurrAdj(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GainCurrAdj_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GainCurrAdj_MASK) /*! @} */ /*! @name TXEQUALIZATIONMODE_P2 - Tx dq driver equalization mode controls. */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TxEqMode_MASK (0x3U) #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TxEqMode_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TxEqMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TxEqMode_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TxEqMode_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL1_B0_P2 - TX impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqN_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL2_B0_P2 - TX equalization impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQHiDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQHiDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQHiDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQHiDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQHiDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQLoDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQLoDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQLoDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQLoDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQLoDqN_MASK) /*! @} */ /*! @name DQDQSRCVCNTRL2_P2 - Dq/Dqs receiver control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_EnRxAgressivePDR_MASK (0x1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_EnRxAgressivePDR_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_EnRxAgressivePDR(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_EnRxAgressivePDR_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_EnRxAgressivePDR_MASK) /*! @} */ /*! @name TXODTDRVSTREN_B0_P2 - TX ODT driver strength control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenP_MASK) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenN_MASK) /*! @} */ /*! @name TXSLEWRATE_B0_P2 - TX slew rate controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreP_MASK (0xFU) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreP_MASK) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreN_MASK (0xF0U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreN_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreN_MASK) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreDrvMode_MASK (0x700U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreDrvMode_SHIFT (8U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreDrvMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreDrvMode_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreDrvMode_MASK) /*! @} */ /*! @name RXENDLYTG0_U0_P2 - Trained Receive Enable Delay (For Timing Group 0) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RxEnDlyTg0_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RxEnDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RxEnDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RxEnDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RxEnDlyTg0_un_px_MASK) /*! @} */ /*! @name RXENDLYTG1_U0_P2 - Trained Receive Enable Delay (For Timing Group 1) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RxEnDlyTg1_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RxEnDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RxEnDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RxEnDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RxEnDlyTg1_un_px_MASK) /*! @} */ /*! @name RXENDLYTG2_U0_P2 - Trained Receive Enable Delay (For Timing Group 2) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RxEnDlyTg2_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RxEnDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RxEnDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RxEnDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RxEnDlyTg2_un_px_MASK) /*! @} */ /*! @name RXENDLYTG3_U0_P2 - Trained Receive Enable Delay (For Timing Group 3) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RxEnDlyTg3_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RxEnDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RxEnDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RxEnDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RxEnDlyTg3_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG0_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RxClkDlyTg0_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RxClkDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RxClkDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RxClkDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RxClkDlyTg0_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG1_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RxClkDlyTg1_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RxClkDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RxClkDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RxClkDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RxClkDlyTg1_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG2_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RxClkDlyTg2_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RxClkDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RxClkDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RxClkDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RxClkDlyTg2_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG3_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RxClkDlyTg3_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RxClkDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RxClkDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RxClkDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RxClkDlyTg3_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG0_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RxClkcDlyTg0_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RxClkcDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RxClkcDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RxClkcDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RxClkcDlyTg0_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG1_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RxClkcDlyTg1_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RxClkcDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RxClkcDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RxClkcDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RxClkcDlyTg1_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG2_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RxClkcDlyTg2_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RxClkcDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RxClkcDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RxClkcDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RxClkcDlyTg2_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG3_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RxClkcDlyTg3_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RxClkcDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RxClkcDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RxClkcDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RxClkcDlyTg3_un_px_MASK) /*! @} */ /*! @name PPTDQSCNTINVTRNTG0_P2 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PptDqsCntInvTrnTg0_p2_MASK (0xFFFFU) #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PptDqsCntInvTrnTg0_p2_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PptDqsCntInvTrnTg0_p2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PptDqsCntInvTrnTg0_p2_SHIFT)) & \ DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PptDqsCntInvTrnTg0_p2_MASK) /*! @} */ /*! @name PPTDQSCNTINVTRNTG1_P2 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PptDqsCntInvTrnTg1_p2_MASK (0xFFFFU) #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PptDqsCntInvTrnTg1_p2_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PptDqsCntInvTrnTg1_p2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PptDqsCntInvTrnTg1_p2_SHIFT)) & \ DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PptDqsCntInvTrnTg1_p2_MASK) /*! @} */ /*! @name TXDQDLYTG0_R0_P2 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R0_P2 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R0_P2 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R0_P2 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQSDLYTG0_U0_P2 - Write DQS Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TxDqsDlyTg0_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TxDqsDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TxDqsDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TxDqsDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TxDqsDlyTg0_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG1_U0_P2 - Write DQS Delay (Timing Group DEST=1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TxDqsDlyTg1_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TxDqsDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TxDqsDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TxDqsDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TxDqsDlyTg1_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG2_U0_P2 - Write DQS Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TxDqsDlyTg2_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TxDqsDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TxDqsDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TxDqsDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TxDqsDlyTg2_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG3_U0_P2 - Write DQS Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TxDqsDlyTg3_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TxDqsDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TxDqsDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TxDqsDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TxDqsDlyTg3_un_px_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL0_B1_P2 - Data TX impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqN_MASK) /*! @} */ /*! @name DQDQSRCVCNTRL_B1_P2 - Dq/Dqs receiver control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SelAnalogVref_MASK (0x1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SelAnalogVref_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SelAnalogVref(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SelAnalogVref_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SelAnalogVref_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_ExtVrefRange_MASK (0x2U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_ExtVrefRange_SHIFT (1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_ExtVrefRange(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_ExtVrefRange_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_ExtVrefRange_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DfeCtrl_MASK (0xCU) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DfeCtrl_SHIFT (2U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DfeCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DfeCtrl_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DfeCtrl_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MajorModeDbyte_MASK (0x70U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MajorModeDbyte_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MajorModeDbyte(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MajorModeDbyte_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MajorModeDbyte_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GainCurrAdj_MASK (0xF80U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GainCurrAdj_SHIFT (7U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GainCurrAdj(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GainCurrAdj_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GainCurrAdj_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL1_B1_P2 - TX impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqN_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL2_B1_P2 - TX equalization impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQHiDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQHiDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQHiDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQHiDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQHiDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQLoDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQLoDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQLoDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQLoDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQLoDqN_MASK) /*! @} */ /*! @name TXODTDRVSTREN_B1_P2 - TX ODT driver strength control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenP_MASK) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenN_MASK) /*! @} */ /*! @name TXSLEWRATE_B1_P2 - TX slew rate controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreP_MASK (0xFU) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreP_MASK) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreN_MASK (0xF0U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreN_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreN_MASK) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreDrvMode_MASK (0x700U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreDrvMode_SHIFT (8U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreDrvMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreDrvMode_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreDrvMode_MASK) /*! @} */ /*! @name RXENDLYTG0_U1_P2 - Trained Receive Enable Delay (For Timing Group 0) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RxEnDlyTg0_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RxEnDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RxEnDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RxEnDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RxEnDlyTg0_un_px_MASK) /*! @} */ /*! @name RXENDLYTG1_U1_P2 - Trained Receive Enable Delay (For Timing Group 1) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RxEnDlyTg1_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RxEnDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RxEnDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RxEnDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RxEnDlyTg1_un_px_MASK) /*! @} */ /*! @name RXENDLYTG2_U1_P2 - Trained Receive Enable Delay (For Timing Group 2) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RxEnDlyTg2_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RxEnDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RxEnDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RxEnDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RxEnDlyTg2_un_px_MASK) /*! @} */ /*! @name RXENDLYTG3_U1_P2 - Trained Receive Enable Delay (For Timing Group 3) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RxEnDlyTg3_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RxEnDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RxEnDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RxEnDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RxEnDlyTg3_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG0_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RxClkDlyTg0_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RxClkDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RxClkDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RxClkDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RxClkDlyTg0_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG1_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RxClkDlyTg1_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RxClkDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RxClkDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RxClkDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RxClkDlyTg1_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG2_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RxClkDlyTg2_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RxClkDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RxClkDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RxClkDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RxClkDlyTg2_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG3_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RxClkDlyTg3_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RxClkDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RxClkDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RxClkDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RxClkDlyTg3_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG0_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RxClkcDlyTg0_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RxClkcDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RxClkcDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RxClkcDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RxClkcDlyTg0_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG1_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RxClkcDlyTg1_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RxClkcDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RxClkcDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RxClkcDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RxClkcDlyTg1_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG2_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RxClkcDlyTg2_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RxClkcDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RxClkcDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RxClkcDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RxClkcDlyTg2_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG3_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RxClkcDlyTg3_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RxClkcDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RxClkcDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RxClkcDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RxClkcDlyTg3_un_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R1_P2 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R1_P2 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R1_P2 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R1_P2 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQSDLYTG0_U1_P2 - Write DQS Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TxDqsDlyTg0_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TxDqsDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TxDqsDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TxDqsDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TxDqsDlyTg0_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG1_U1_P2 - Write DQS Delay (Timing Group DEST=1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TxDqsDlyTg1_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TxDqsDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TxDqsDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TxDqsDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TxDqsDlyTg1_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG2_U1_P2 - Write DQS Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TxDqsDlyTg2_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TxDqsDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TxDqsDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TxDqsDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TxDqsDlyTg2_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG3_U1_P2 - Write DQS Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TxDqsDlyTg3_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TxDqsDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TxDqsDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TxDqsDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TxDqsDlyTg3_un_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R2_P2 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R2_P2 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R2_P2 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R2_P2 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R3_P2 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R3_P2 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R3_P2 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R3_P2 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R4_P2 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R4_P2 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R4_P2 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R4_P2 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R5_P2 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R5_P2 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R5_P2 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R5_P2 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R6_P2 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R6_P2 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R6_P2 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R6_P2 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R7_P2 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R7_P2 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R7_P2 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R7_P2 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R8_P2 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R8_P2 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R8_P2 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R8_P2 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name DFIMRL_P3 - DFI MaxReadLatency */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_p3_MASK (0x1FU) #define DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_p3_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_p3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_p3_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_p3_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL0_B0_P3 - Data TX impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqN_MASK) /*! @} */ /*! @name DQDQSRCVCNTRL_B0_P3 - Dq/Dqs receiver control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SelAnalogVref_MASK (0x1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SelAnalogVref_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SelAnalogVref(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SelAnalogVref_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SelAnalogVref_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_ExtVrefRange_MASK (0x2U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_ExtVrefRange_SHIFT (1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_ExtVrefRange(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_ExtVrefRange_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_ExtVrefRange_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DfeCtrl_MASK (0xCU) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DfeCtrl_SHIFT (2U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DfeCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DfeCtrl_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DfeCtrl_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MajorModeDbyte_MASK (0x70U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MajorModeDbyte_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MajorModeDbyte(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MajorModeDbyte_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MajorModeDbyte_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GainCurrAdj_MASK (0xF80U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GainCurrAdj_SHIFT (7U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GainCurrAdj(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GainCurrAdj_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GainCurrAdj_MASK) /*! @} */ /*! @name TXEQUALIZATIONMODE_P3 - Tx dq driver equalization mode controls. */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TxEqMode_MASK (0x3U) #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TxEqMode_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TxEqMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TxEqMode_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TxEqMode_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL1_B0_P3 - TX impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqN_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL2_B0_P3 - TX equalization impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQHiDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQHiDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQHiDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQHiDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQHiDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQLoDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQLoDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQLoDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQLoDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQLoDqN_MASK) /*! @} */ /*! @name DQDQSRCVCNTRL2_P3 - Dq/Dqs receiver control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_EnRxAgressivePDR_MASK (0x1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_EnRxAgressivePDR_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_EnRxAgressivePDR(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_EnRxAgressivePDR_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_EnRxAgressivePDR_MASK) /*! @} */ /*! @name TXODTDRVSTREN_B0_P3 - TX ODT driver strength control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenP_MASK) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenN_MASK) /*! @} */ /*! @name TXSLEWRATE_B0_P3 - TX slew rate controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreP_MASK (0xFU) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreP_MASK) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreN_MASK (0xF0U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreN_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreN_MASK) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreDrvMode_MASK (0x700U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreDrvMode_SHIFT (8U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreDrvMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreDrvMode_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreDrvMode_MASK) /*! @} */ /*! @name RXENDLYTG0_U0_P3 - Trained Receive Enable Delay (For Timing Group 0) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RxEnDlyTg0_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RxEnDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RxEnDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RxEnDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RxEnDlyTg0_un_px_MASK) /*! @} */ /*! @name RXENDLYTG1_U0_P3 - Trained Receive Enable Delay (For Timing Group 1) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RxEnDlyTg1_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RxEnDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RxEnDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RxEnDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RxEnDlyTg1_un_px_MASK) /*! @} */ /*! @name RXENDLYTG2_U0_P3 - Trained Receive Enable Delay (For Timing Group 2) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RxEnDlyTg2_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RxEnDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RxEnDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RxEnDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RxEnDlyTg2_un_px_MASK) /*! @} */ /*! @name RXENDLYTG3_U0_P3 - Trained Receive Enable Delay (For Timing Group 3) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RxEnDlyTg3_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RxEnDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RxEnDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RxEnDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RxEnDlyTg3_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG0_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RxClkDlyTg0_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RxClkDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RxClkDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RxClkDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RxClkDlyTg0_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG1_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RxClkDlyTg1_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RxClkDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RxClkDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RxClkDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RxClkDlyTg1_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG2_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RxClkDlyTg2_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RxClkDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RxClkDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RxClkDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RxClkDlyTg2_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG3_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RxClkDlyTg3_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RxClkDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RxClkDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RxClkDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RxClkDlyTg3_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG0_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RxClkcDlyTg0_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RxClkcDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RxClkcDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RxClkcDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RxClkcDlyTg0_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG1_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RxClkcDlyTg1_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RxClkcDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RxClkcDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RxClkcDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RxClkcDlyTg1_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG2_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RxClkcDlyTg2_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RxClkcDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RxClkcDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RxClkcDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RxClkcDlyTg2_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG3_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RxClkcDlyTg3_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RxClkcDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RxClkcDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RxClkcDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RxClkcDlyTg3_un_px_MASK) /*! @} */ /*! @name PPTDQSCNTINVTRNTG0_P3 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PptDqsCntInvTrnTg0_p3_MASK (0xFFFFU) #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PptDqsCntInvTrnTg0_p3_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PptDqsCntInvTrnTg0_p3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PptDqsCntInvTrnTg0_p3_SHIFT)) & \ DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PptDqsCntInvTrnTg0_p3_MASK) /*! @} */ /*! @name PPTDQSCNTINVTRNTG1_P3 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PptDqsCntInvTrnTg1_p3_MASK (0xFFFFU) #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PptDqsCntInvTrnTg1_p3_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PptDqsCntInvTrnTg1_p3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PptDqsCntInvTrnTg1_p3_SHIFT)) & \ DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PptDqsCntInvTrnTg1_p3_MASK) /*! @} */ /*! @name TXDQDLYTG0_R0_P3 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R0_P3 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R0_P3 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R0_P3 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQSDLYTG0_U0_P3 - Write DQS Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TxDqsDlyTg0_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TxDqsDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TxDqsDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TxDqsDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TxDqsDlyTg0_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG1_U0_P3 - Write DQS Delay (Timing Group DEST=1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TxDqsDlyTg1_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TxDqsDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TxDqsDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TxDqsDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TxDqsDlyTg1_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG2_U0_P3 - Write DQS Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TxDqsDlyTg2_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TxDqsDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TxDqsDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TxDqsDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TxDqsDlyTg2_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG3_U0_P3 - Write DQS Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TxDqsDlyTg3_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TxDqsDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TxDqsDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TxDqsDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TxDqsDlyTg3_un_px_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL0_B1_P3 - Data TX impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqN_MASK) /*! @} */ /*! @name DQDQSRCVCNTRL_B1_P3 - Dq/Dqs receiver control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SelAnalogVref_MASK (0x1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SelAnalogVref_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SelAnalogVref(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SelAnalogVref_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SelAnalogVref_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_ExtVrefRange_MASK (0x2U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_ExtVrefRange_SHIFT (1U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_ExtVrefRange(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_ExtVrefRange_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_ExtVrefRange_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DfeCtrl_MASK (0xCU) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DfeCtrl_SHIFT (2U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DfeCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DfeCtrl_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DfeCtrl_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MajorModeDbyte_MASK (0x70U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MajorModeDbyte_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MajorModeDbyte(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MajorModeDbyte_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MajorModeDbyte_MASK) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GainCurrAdj_MASK (0xF80U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GainCurrAdj_SHIFT (7U) #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GainCurrAdj(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GainCurrAdj_SHIFT)) & \ DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GainCurrAdj_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL1_B1_P3 - TX impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqN_MASK) /*! @} */ /*! @name TXIMPEDANCECTRL2_B1_P3 - TX equalization impedance controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQHiDqP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQHiDqP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQHiDqP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQHiDqP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQHiDqP_MASK) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQLoDqN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQLoDqN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQLoDqN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQLoDqN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQLoDqN_MASK) /*! @} */ /*! @name TXODTDRVSTREN_B1_P3 - TX ODT driver strength control */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenP_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenP_MASK) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenN_MASK (0xFC0U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenN_SHIFT (6U) #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenN_MASK) /*! @} */ /*! @name TXSLEWRATE_B1_P3 - TX slew rate controls */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreP_MASK (0xFU) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreP_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreP_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreP_MASK) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreN_MASK (0xF0U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreN_SHIFT (4U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreN_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreN_MASK) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreDrvMode_MASK (0x700U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreDrvMode_SHIFT (8U) #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreDrvMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreDrvMode_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreDrvMode_MASK) /*! @} */ /*! @name RXENDLYTG0_U1_P3 - Trained Receive Enable Delay (For Timing Group 0) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RxEnDlyTg0_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RxEnDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RxEnDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RxEnDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RxEnDlyTg0_un_px_MASK) /*! @} */ /*! @name RXENDLYTG1_U1_P3 - Trained Receive Enable Delay (For Timing Group 1) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RxEnDlyTg1_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RxEnDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RxEnDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RxEnDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RxEnDlyTg1_un_px_MASK) /*! @} */ /*! @name RXENDLYTG2_U1_P3 - Trained Receive Enable Delay (For Timing Group 2) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RxEnDlyTg2_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RxEnDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RxEnDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RxEnDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RxEnDlyTg2_un_px_MASK) /*! @} */ /*! @name RXENDLYTG3_U1_P3 - Trained Receive Enable Delay (For Timing Group 3) */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RxEnDlyTg3_un_px_MASK (0x7FFU) #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RxEnDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RxEnDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RxEnDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RxEnDlyTg3_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG0_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RxClkDlyTg0_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RxClkDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RxClkDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RxClkDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RxClkDlyTg0_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG1_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RxClkDlyTg1_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RxClkDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RxClkDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RxClkDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RxClkDlyTg1_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG2_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RxClkDlyTg2_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RxClkDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RxClkDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RxClkDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RxClkDlyTg2_un_px_MASK) /*! @} */ /*! @name RXCLKDLYTG3_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RxClkDlyTg3_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RxClkDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RxClkDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RxClkDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RxClkDlyTg3_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG0_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RxClkcDlyTg0_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RxClkcDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RxClkcDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RxClkcDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RxClkcDlyTg0_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG1_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RxClkcDlyTg1_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RxClkcDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RxClkcDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RxClkcDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RxClkcDlyTg1_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG2_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RxClkcDlyTg2_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RxClkcDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RxClkcDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RxClkcDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RxClkcDlyTg2_un_px_MASK) /*! @} */ /*! @name RXCLKCDLYTG3_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RxClkcDlyTg3_un_px_MASK (0x3FU) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RxClkcDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RxClkcDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RxClkcDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RxClkcDlyTg3_un_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R1_P3 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R1_P3 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R1_P3 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R1_P3 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQSDLYTG0_U1_P3 - Write DQS Delay (Timing Group DEST=0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TxDqsDlyTg0_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TxDqsDlyTg0_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TxDqsDlyTg0_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TxDqsDlyTg0_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TxDqsDlyTg0_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG1_U1_P3 - Write DQS Delay (Timing Group DEST=1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TxDqsDlyTg1_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TxDqsDlyTg1_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TxDqsDlyTg1_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TxDqsDlyTg1_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TxDqsDlyTg1_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG2_U1_P3 - Write DQS Delay (Timing Group DEST=2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TxDqsDlyTg2_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TxDqsDlyTg2_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TxDqsDlyTg2_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TxDqsDlyTg2_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TxDqsDlyTg2_un_px_MASK) /*! @} */ /*! @name TXDQSDLYTG3_U1_P3 - Write DQS Delay (Timing Group DEST=3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TxDqsDlyTg3_un_px_MASK (0x3FFU) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TxDqsDlyTg3_un_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TxDqsDlyTg3_un_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TxDqsDlyTg3_un_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TxDqsDlyTg3_un_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R2_P3 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R2_P3 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R2_P3 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R2_P3 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R3_P3 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R3_P3 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R3_P3 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R3_P3 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R4_P3 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R4_P3 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R4_P3 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R4_P3 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R5_P3 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R5_P3 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R5_P3 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R5_P3 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R6_P3 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R6_P3 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R6_P3 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R6_P3 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R7_P3 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R7_P3 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R7_P3 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R7_P3 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG0_R8_P3 - Write DQ Delay (Timing Group 0). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TxDqDlyTg0_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TxDqDlyTg0_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TxDqDlyTg0_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TxDqDlyTg0_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG1_R8_P3 - Write DQ Delay (Timing Group 1). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TxDqDlyTg1_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TxDqDlyTg1_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TxDqDlyTg1_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TxDqDlyTg1_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG2_R8_P3 - Write DQ Delay (Timing Group 2). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TxDqDlyTg2_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TxDqDlyTg2_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TxDqDlyTg2_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TxDqDlyTg2_rn_px_MASK) /*! @} */ /*! @name TXDQDLYTG3_R8_P3 - Write DQ Delay (Timing Group 3). */ /*! @{ */ #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TxDqDlyTg3_rn_px_SHIFT (0U) #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TxDqDlyTg3_rn_px(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TxDqDlyTg3_rn_px_SHIFT)) & \ DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TxDqDlyTg3_rn_px_MASK) /*! @} */ /*! * @} */ /* end of group DWC_DDRPHYA_DBYTE_Register_Masks */ /* DWC_DDRPHYA_DBYTE - Peripheral instance base addresses */ /** Peripheral DWC_DDRPHYA_DBYTE0 base address */ #define DWC_DDRPHYA_DBYTE0_BASE (0x3C010000u) /** Peripheral DWC_DDRPHYA_DBYTE0 base pointer */ #define DWC_DDRPHYA_DBYTE0 ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE0_BASE) /** Peripheral DWC_DDRPHYA_DBYTE1 base address */ #define DWC_DDRPHYA_DBYTE1_BASE (0x3C011000u) /** Peripheral DWC_DDRPHYA_DBYTE1 base pointer */ #define DWC_DDRPHYA_DBYTE1 ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE1_BASE) /** Peripheral DWC_DDRPHYA_DBYTE2 base address */ #define DWC_DDRPHYA_DBYTE2_BASE (0x3C012000u) /** Peripheral DWC_DDRPHYA_DBYTE2 base pointer */ #define DWC_DDRPHYA_DBYTE2 ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE2_BASE) /** Peripheral DWC_DDRPHYA_DBYTE3 base address */ #define DWC_DDRPHYA_DBYTE3_BASE (0x3C013000u) /** Peripheral DWC_DDRPHYA_DBYTE3 base pointer */ #define DWC_DDRPHYA_DBYTE3 ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE3_BASE) /** Array initializer of DWC_DDRPHYA_DBYTE peripheral base addresses */ #define DWC_DDRPHYA_DBYTE_BASE_ADDRS \ { \ DWC_DDRPHYA_DBYTE0_BASE, DWC_DDRPHYA_DBYTE1_BASE, DWC_DDRPHYA_DBYTE2_BASE, DWC_DDRPHYA_DBYTE3_BASE \ } /** Array initializer of DWC_DDRPHYA_DBYTE peripheral base pointers */ #define DWC_DDRPHYA_DBYTE_BASE_PTRS \ { \ DWC_DDRPHYA_DBYTE0, DWC_DDRPHYA_DBYTE1, DWC_DDRPHYA_DBYTE2, DWC_DDRPHYA_DBYTE3 \ } /*! * @} */ /* end of group DWC_DDRPHYA_DBYTE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DWC_DDRPHYA_DRTUB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DWC_DDRPHYA_DRTUB_Peripheral_Access_Layer DWC_DDRPHYA_DRTUB Peripheral Access Layer * @{ */ /** DWC_DDRPHYA_DRTUB - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[256]; __IO uint16_t UCCLKHCLKENABLES; /**< Ucclk and Hclk enables, offset: 0x100 */ __IO uint16_t CURPSTATE0B; /**< PIE current Pstate value, offset: 0x102 */ uint8_t RESERVED_1[214]; __I uint16_t CUSTPUBREV; /**< Customer settable by the customer, offset: 0x1DA */ __I uint16_t PUBREV; /**< The hardware version of this PUB, excluding the PHY, offset: 0x1DC */ } DWC_DDRPHYA_DRTUB_Type; /* ---------------------------------------------------------------------------- -- DWC_DDRPHYA_DRTUB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DWC_DDRPHYA_DRTUB_Register_Masks DWC_DDRPHYA_DRTUB Register Masks * @{ */ /*! @name UCCLKHCLKENABLES - Ucclk and Hclk enables */ /*! @{ */ #define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UcclkEn_MASK (0x1U) #define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UcclkEn_SHIFT (0U) #define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UcclkEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UcclkEn_SHIFT)) & \ DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UcclkEn_MASK) #define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HclkEn_MASK (0x2U) #define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HclkEn_SHIFT (1U) #define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HclkEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HclkEn_SHIFT)) & \ DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HclkEn_MASK) /*! @} */ /*! @name CURPSTATE0B - PIE current Pstate value */ /*! @{ */ #define DWC_DDRPHYA_DRTUB_CURPSTATE0B_CurPstate0b_MASK (0xFU) #define DWC_DDRPHYA_DRTUB_CURPSTATE0B_CurPstate0b_SHIFT (0U) #define DWC_DDRPHYA_DRTUB_CURPSTATE0B_CurPstate0b(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_CURPSTATE0B_CurPstate0b_SHIFT)) & \ DWC_DDRPHYA_DRTUB_CURPSTATE0B_CurPstate0b_MASK) /*! @} */ /*! @name CUSTPUBREV - Customer settable by the customer */ /*! @{ */ #define DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_MASK (0x3FU) #define DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_SHIFT (0U) #define DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_SHIFT)) & \ DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_MASK) /*! @} */ /*! @name PUBREV - The hardware version of this PUB, excluding the PHY */ /*! @{ */ #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_MASK (0xFU) #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_SHIFT (0U) #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_SHIFT)) & DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_MASK) #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_MASK (0xF0U) #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_SHIFT (4U) #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_SHIFT)) & DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_MASK) #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_MASK (0xFF00U) #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_SHIFT (8U) #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_SHIFT)) & DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_MASK) /*! @} */ /*! * @} */ /* end of group DWC_DDRPHYA_DRTUB_Register_Masks */ /* DWC_DDRPHYA_DRTUB - Peripheral instance base addresses */ /** Peripheral DWC_DDRPHYA_DRTUB0 base address */ #define DWC_DDRPHYA_DRTUB0_BASE (0x3C0C0000u) /** Peripheral DWC_DDRPHYA_DRTUB0 base pointer */ #define DWC_DDRPHYA_DRTUB0 ((DWC_DDRPHYA_DRTUB_Type *)DWC_DDRPHYA_DRTUB0_BASE) /** Array initializer of DWC_DDRPHYA_DRTUB peripheral base addresses */ #define DWC_DDRPHYA_DRTUB_BASE_ADDRS \ { \ DWC_DDRPHYA_DRTUB0_BASE \ } /** Array initializer of DWC_DDRPHYA_DRTUB peripheral base pointers */ #define DWC_DDRPHYA_DRTUB_BASE_PTRS \ { \ DWC_DDRPHYA_DRTUB0 \ } /*! * @} */ /* end of group DWC_DDRPHYA_DRTUB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DWC_DDRPHYA_INITENG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DWC_DDRPHYA_INITENG_Peripheral_Access_Layer DWC_DDRPHYA_INITENG Peripheral Access Layer * @{ */ /** DWC_DDRPHYA_INITENG - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[80]; __IO uint16_t PHYINLP3; /**< Indicator for PIE Lower Power 3 (LP3) Status, offset: 0x50 */ } DWC_DDRPHYA_INITENG_Type; /* ---------------------------------------------------------------------------- -- DWC_DDRPHYA_INITENG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DWC_DDRPHYA_INITENG_Register_Masks DWC_DDRPHYA_INITENG Register Masks * @{ */ /*! @name PHYINLP3 - Indicator for PIE Lower Power 3 (LP3) Status */ /*! @{ */ #define DWC_DDRPHYA_INITENG_PHYINLP3_PhyInLP3_MASK (0x1U) #define DWC_DDRPHYA_INITENG_PHYINLP3_PhyInLP3_SHIFT (0U) #define DWC_DDRPHYA_INITENG_PHYINLP3_PhyInLP3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_INITENG_PHYINLP3_PhyInLP3_SHIFT)) & \ DWC_DDRPHYA_INITENG_PHYINLP3_PhyInLP3_MASK) /*! @} */ /*! * @} */ /* end of group DWC_DDRPHYA_INITENG_Register_Masks */ /* DWC_DDRPHYA_INITENG - Peripheral instance base addresses */ /** Peripheral DWC_DDRPHYA_INITENG0 base address */ #define DWC_DDRPHYA_INITENG0_BASE (0x3C090000u) /** Peripheral DWC_DDRPHYA_INITENG0 base pointer */ #define DWC_DDRPHYA_INITENG0 ((DWC_DDRPHYA_INITENG_Type *)DWC_DDRPHYA_INITENG0_BASE) /** Array initializer of DWC_DDRPHYA_INITENG peripheral base addresses */ #define DWC_DDRPHYA_INITENG_BASE_ADDRS \ { \ DWC_DDRPHYA_INITENG0_BASE \ } /** Array initializer of DWC_DDRPHYA_INITENG peripheral base pointers */ #define DWC_DDRPHYA_INITENG_BASE_PTRS \ { \ DWC_DDRPHYA_INITENG0 \ } /*! * @} */ /* end of group DWC_DDRPHYA_INITENG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DWC_DDRPHYA_MASTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DWC_DDRPHYA_MASTER_Peripheral_Access_Layer DWC_DDRPHYA_MASTER Peripheral Access Layer * @{ */ /** DWC_DDRPHYA_MASTER - Register Layout Typedef */ typedef struct { __IO uint16_t RXFIFOINIT; /**< Rx FIFO pointer initialization control, offset: 0x0 */ __IO uint16_t FORCECLKDISABLE; /**< Clock gating control, offset: 0x2 */ uint8_t RESERVED_0[2]; __IO uint16_t FORCEINTERNALUPDATE; /**< This Register used by Training Firmware to force an internal PHY Update Event., offset: 0x6 */ __I uint16_t PHYCONFIG; /**< Read Only displays PHY Configuration., offset: 0x8 */ __IO uint16_t PGCR; /**< PHY General Configuration Register(PGCR)., offset: 0xA */ uint8_t RESERVED_1[2]; __IO uint16_t TESTBUMPCNTRL1; /**< Test Bump Control1, offset: 0xE */ __IO uint16_t CALUCLKINFO_P0; /**< Impedance Calibration Clock Ratio, offset: 0x10 */ uint8_t RESERVED_2[2]; __IO uint16_t TESTBUMPCNTRL; /**< Test Bump Control, offset: 0x14 */ __IO uint16_t SEQ0BDLY0_P0; /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x16 */ __IO uint16_t SEQ0BDLY1_P0; /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x18 */ __IO uint16_t SEQ0BDLY2_P0; /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x1A */ __IO uint16_t SEQ0BDLY3_P0; /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x1C */ __I uint16_t PHYALERTSTATUS; /**< PHY Alert status bit, offset: 0x1E */ __IO uint16_t PPTTRAINSETUP_P0; /**< Setup Intervals for DFI PHY Master operations, offset: 0x20 */ uint8_t RESERVED_3[2]; __IO uint16_t ATESTMODE; /**< ATestMode control, offset: 0x24 */ uint8_t RESERVED_4[2]; __I uint16_t TXCALBINP; /**< TX P Impedance Calibration observation, offset: 0x28 */ __I uint16_t TXCALBINN; /**< TX N Impedance Calibration observation, offset: 0x2A */ __IO uint16_t TXCALPOVR; /**< TX P Impedance Calibration override, offset: 0x2C */ __IO uint16_t TXCALNOVR; /**< TX N Impedance Calibration override, offset: 0x2E */ __IO uint16_t DFIMODE; /**< Enables for update and low-power interfaces for DFI0 and DFI1, offset: 0x30 */ __IO uint16_t TRISTATEMODECA_P0; /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x32 */ __IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x34 */ __IO uint16_t MTESTPGMINFO; /**< Digital Observation Pin program info for debug, offset: 0x36 */ __IO uint16_t DYNPWRDNUP; /**< Dynaimc Power Up/Down control, offset: 0x38 */ uint8_t RESERVED_5[2]; __IO uint16_t PHYTID; /**< PHY Technology ID Register, offset: 0x3C */ uint8_t RESERVED_6[2]; __IO uint16_t HWTMRL_P0; /**< HWT MaxReadLatency., offset: 0x40 */ __IO uint16_t DFIPHYUPD; /**< DFI PhyUpdate Request time counter (in MEMCLKs), offset: 0x42 */ __IO uint16_t PDAMRSWRITEMODE; /**< Controls the write DQ generation for Per-Dram-Addressing of MRS, offset: 0x44 */ __IO uint16_t DFIGEARDOWNCTL; /**< Controls whether dfi_geardown_en will cause CS and CKE timing to change., offset: 0x46 */ __IO uint16_t DQSPREAMBLECONTROL_P0; /**< Control the PHY logic related to the read and write DQS preamble, offset: 0x48 */ __IO uint16_t MASTERX4CONFIG; /**< DBYTE module controls to select X4 Dram device mode, offset: 0x4A */ __IO uint16_t WRLEVBITS; /**< Write level feedback DQ observability select., offset: 0x4C */ __IO uint16_t ENABLECSMULTICAST; /**< In DDR4 Mode , this controls whether CS_N[3:2] should be multicast on CID[1:0], offset: 0x4E */ __IO uint16_t HWTLPCSMULTICAST; /**< Drives cs_n[0] onto cs_n[1] during training, offset: 0x50 */ uint8_t RESERVED_7[6]; __IO uint16_t ACX4ANIBDIS; /**< Disable for unused ACX Nibbles, offset: 0x58 */ __IO uint16_t DMIPINPRESENT_P0; /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x5A */ __IO uint16_t ARDPTRINITVAL_P0; /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x5C */ uint8_t RESERVED_8[22]; __IO uint16_t DBYTEDLLMODECNTRL; /**< DLL Mode control CSR for DBYTEs, offset: 0x74 */ uint8_t RESERVED_9[20]; __IO uint16_t CALOFFSETS; /**< Impedance Calibration offsets control, offset: 0x8A */ uint8_t RESERVED_10[2]; __IO uint16_t SARINITVALS; /**< Sar Init Vals, offset: 0x8E */ uint8_t RESERVED_11[2]; __IO uint16_t CALPEXTOVR; /**< Impedance Calibration PExt Override control, offset: 0x92 */ __IO uint16_t CALCMPR5OVR; /**< Impedance Calibration Cmpr 50 control, offset: 0x94 */ __IO uint16_t CALNINTOVR; /**< Impedance Calibration NInt Override control, offset: 0x96 */ uint8_t RESERVED_12[8]; __IO uint16_t CALDRVSTR0; /**< Impedance Calibration driver strength control, offset: 0xA0 */ uint8_t RESERVED_13[10]; __IO uint16_t PROCODTTIMECTL_P0; /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0xAC */ uint8_t RESERVED_14[8]; __IO uint16_t MEMALERTCONTROL; /**< This Register is used to configure the MemAlert Receiver, offset: 0xB6 */ __IO uint16_t MEMALERTCONTROL2; /**< This Register is used to configure the MemAlert Receiver, offset: 0xB8 */ uint8_t RESERVED_15[6]; __IO uint16_t MEMRESETL; /**< Protection and control of BP_MemReset_L, offset: 0xC0 */ uint8_t RESERVED_16[24]; __IO uint16_t DRIVECSLOWONTOHIGH; /**< Drive CS_N 3:0 onto CS_N 7:4, offset: 0xDA */ __IO uint16_t PUBMODE; /**< PUBMODE - HWT Mux Select, offset: 0xDC */ __I uint16_t MISCPHYSTATUS; /**< Misc PHY status bits, offset: 0xDE */ __IO uint16_t CORELOOPBACKSEL; /**< Controls whether the loopback path bypasses the final PAD node., offset: 0xE0 */ __IO uint16_t DLLTRAINPARAM; /**< DLL Various Training Parameters, offset: 0xE2 */ uint8_t RESERVED_17[4]; __IO uint16_t HWTLPCSENBYPASS; /**< CSn Disable Bypass for LPDDR3/4, offset: 0xE8 */ __IO uint16_t DFICAMODE; /**< Dfi Command/Address Mode, offset: 0xEA */ uint8_t RESERVED_18[4]; __IO uint16_t DLLCONTROL; /**< DLL Lock State machine control register, offset: 0xF0 */ __IO uint16_t PULSEDLLUPDATEPHASE; /**< DLL update phase control, offset: 0xF2 */ uint8_t RESERVED_19[4]; __IO uint16_t DLLGAINCTL_P0; /**< DLL gain control, offset: 0xF8 */ uint8_t RESERVED_20[22]; __IO uint16_t CALRATE; /**< Impedance Calibration Control, offset: 0x110 */ __IO uint16_t CALZAP; /**< Impedance Calibration Zap/Reset, offset: 0x112 */ uint8_t RESERVED_21[2]; __IO uint16_t PSTATE; /**< PSTATE Selection, offset: 0x116 */ uint8_t RESERVED_22[2]; __IO uint16_t PLLOUTGATECONTROL; /**< PLL Output Control, offset: 0x11A */ uint8_t RESERVED_23[4]; __IO uint16_t PORCONTROL; /**< PMU Power-on Reset Control (PLL/DLL Lock Done), offset: 0x120 */ uint8_t RESERVED_24[12]; __I uint16_t CALBUSY; /**< Impedance Calibration Busy Status, offset: 0x12E */ __IO uint16_t CALMISC2; /**< Miscellaneous impedance calibration controls., offset: 0x130 */ uint8_t RESERVED_25[2]; __IO uint16_t CALMISC; /**< Controls for disabling the impedance calibration of certain targets., offset: 0x134 */ __I uint16_t CALVREFS; /**< , offset: 0x136 */ __I uint16_t CALCMPR5; /**< Impedance Calibration Cmpr control, offset: 0x138 */ __I uint16_t CALNINT; /**< Impedance Calibration NInt control, offset: 0x13A */ __I uint16_t CALPEXT; /**< Impedance Calibration PExt control, offset: 0x13C */ uint8_t RESERVED_26[18]; __IO uint16_t CALCMPINVERT; /**< Impedance Calibration Cmp Invert control, offset: 0x150 */ uint8_t RESERVED_27[10]; __IO uint16_t CALCMPANACNTRL; /**< Impedance Calibration Cmpana control, offset: 0x15C */ uint8_t RESERVED_28[2]; __IO uint16_t DFIRDDATACSDESTMAP_P0; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x160 */ uint8_t RESERVED_29[2]; __IO uint16_t VREFINGLOBAL_P0; /**< PHY Global Vref Controls, offset: 0x164 */ uint8_t RESERVED_30[2]; __IO uint16_t DFIWRDATACSDESTMAP_P0; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x168 */ __I uint16_t MASUPDGOODCTR; /**< Counts successful PHY Master Interface Updates (PPTs), offset: 0x16A */ __I uint16_t PHYUPD0GOODCTR; /**< Counts successful PHY-initiated DFI0 Interface Updates, offset: 0x16C */ __I uint16_t PHYUPD1GOODCTR; /**< Counts successful PHY-initiated DFI1 Interface Updates, offset: 0x16E */ __I uint16_t CTLUPD0GOODCTR; /**< Counts successful Memory Controller DFI0 Interface Updates, offset: 0x170 */ __I uint16_t CTLUPD1GOODCTR; /**< Counts successful Memory Controller DFI1 Interface Updates, offset: 0x172 */ __I uint16_t MASUPDFAILCTR; /**< Counts unsuccessful PHY Master Interface Updates, offset: 0x174 */ __I uint16_t PHYUPD0FAILCTR; /**< Counts unsuccessful PHY-initiated DFI0 Interface Updates, offset: 0x176 */ __I uint16_t PHYUPD1FAILCTR; /**< Counts unsuccessful PHY-initiated DFI1 Interface Updates, offset: 0x178 */ __IO uint16_t PHYPERFCTRENABLE; /**< Enables for Performance Counters, offset: 0x17A */ uint8_t RESERVED_31[10]; __IO uint16_t PLLPWRDN; /**< PLL Power Down, offset: 0x186 */ __IO uint16_t PLLRESET; /**< PLL Reset, offset: 0x188 */ __IO uint16_t PLLCTRL2_P0; /**< PState dependent PLL Control Register 2, offset: 0x18A */ __IO uint16_t PLLCTRL0; /**< PLL Control Register 0, offset: 0x18C */ __IO uint16_t PLLCTRL1_P0; /**< PState dependent PLL Control Register 1, offset: 0x18E */ __IO uint16_t PLLTST; /**< PLL Testing Control Register, offset: 0x190 */ __I uint16_t PLLLOCKSTATUS; /**< PLL's pll_lock pin output, offset: 0x192 */ __IO uint16_t PLLTESTMODE_P0; /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x194 */ __IO uint16_t PLLCTRL3; /**< PLL Control Register 3, offset: 0x196 */ __IO uint16_t PLLCTRL4_P0; /**< PState dependent PLL Control Register 4, offset: 0x198 */ __I uint16_t PLLENDOFCAL; /**< PLL's eoc (end of calibration) output, offset: 0x19A */ __I uint16_t PLLSTANDBYEFF; /**< PLL's standby_eff (effective standby) output, offset: 0x19C */ __I uint16_t PLLDACVALOUT; /**< PLL's Dacval_out output, offset: 0x19E */ uint8_t RESERVED_32[38]; __IO uint16_t LCDLDBGCNTL; /**< Controls for use in observing and testing the LCDLs., offset: 0x1C6 */ __I uint16_t ACLCDLSTATUS; /**< Debug status of the DBYTE LCDL, offset: 0x1C8 */ uint8_t RESERVED_33[16]; __I uint16_t CUSTPHYREV; /**< Customer settable by the customer, offset: 0x1DA */ __I uint16_t PHYREV; /**< The hardware version of this PHY, excluding the PUB, offset: 0x1DC */ __IO uint16_t LP3EXITSEQ0BSTARTVECTOR; /**< Start vector value to be used for LP3-exit or Init PIE Sequence, offset: 0x1DE */ __IO uint16_t DFIFREQXLAT0; /**< DFI Frequency Translation Register 0, offset: 0x1E0 */ __IO uint16_t DFIFREQXLAT1; /**< DFI Frequency Translation Register 1, offset: 0x1E2 */ __IO uint16_t DFIFREQXLAT2; /**< DFI Frequency Translation Register 2, offset: 0x1E4 */ __IO uint16_t DFIFREQXLAT3; /**< DFI Frequency Translation Register 3, offset: 0x1E6 */ __IO uint16_t DFIFREQXLAT4; /**< DFI Frequency Translation Register 4, offset: 0x1E8 */ __IO uint16_t DFIFREQXLAT5; /**< DFI Frequency Translation Register 5, offset: 0x1EA */ __IO uint16_t DFIFREQXLAT6; /**< DFI Frequency Translation Register 6, offset: 0x1EC */ __IO uint16_t DFIFREQXLAT7; /**< DFI Frequency Translation Register 7, offset: 0x1EE */ __IO uint16_t TXRDPTRINIT; /**< TxRdPtrInit control register, offset: 0x1F0 */ __IO uint16_t DFIINITCOMPLETE; /**< DFI Init Complete control, offset: 0x1F2 */ __IO uint16_t DFIFREQRATIO_P0; /**< DFI Frequency Ratio, offset: 0x1F4 */ __IO uint16_t RXFIFOCHECKS; /**< Enable more frequent consistency checks of the RX FIFOs, offset: 0x1F6 */ uint8_t RESERVED_34[6]; __IO uint16_t MTESTDTOCTRL; /**< , offset: 0x1FE */ __IO uint16_t MAPCAA0TODFI; /**< Maps PHY CAA lane 0 from dfi0_address of the index of the register contents, offset: 0x200 */ __IO uint16_t MAPCAA1TODFI; /**< Maps PHY CAA lane 1 from dfi0_address of the index of the register contents, offset: 0x202 */ __IO uint16_t MAPCAA2TODFI; /**< Maps PHY CAA lane 2 from dfi0_address of the index of the register contents, offset: 0x204 */ __IO uint16_t MAPCAA3TODFI; /**< Maps PHY CAA lane 3 from dfi0_address of the index of the register contents, offset: 0x206 */ __IO uint16_t MAPCAA4TODFI; /**< Maps PHY CAA lane 4 from dfi0_address of the index of the register contents, offset: 0x208 */ __IO uint16_t MAPCAA5TODFI; /**< Maps PHY CAA lane 5 from dfi0_address of the index of the register contents, offset: 0x20A */ __IO uint16_t MAPCAA6TODFI; /**< Maps PHY CAA lane 6 from dfi0_address of the index of the register contents, offset: 0x20C */ __IO uint16_t MAPCAA7TODFI; /**< Maps PHY CAA lane 7 from dfi0_address of the index of the register contents, offset: 0x20E */ __IO uint16_t MAPCAA8TODFI; /**< Maps PHY CAA lane 8 from dfi0_address of the index of the register contents, offset: 0x210 */ __IO uint16_t MAPCAA9TODFI; /**< Maps PHY CAA lane 9 from dfi0_address of the index of the register contents, offset: 0x212 */ uint8_t RESERVED_35[12]; __IO uint16_t MAPCAB0TODFI; /**< Maps PHY CAB lane 0 from dfi1_address of the index of the register contents, offset: 0x220 */ __IO uint16_t MAPCAB1TODFI; /**< Maps PHY CAB lane 1 from dfi1_address of the index of the register contents, offset: 0x222 */ __IO uint16_t MAPCAB2TODFI; /**< Maps PHY CAB lane 2 from dfi1_address of the index of the register contents, offset: 0x224 */ __IO uint16_t MAPCAB3TODFI; /**< Maps PHY CAB lane 3 from dfi1_address of the index of the register contents, offset: 0x226 */ __IO uint16_t MAPCAB4TODFI; /**< Maps PHY CAB lane 4 from dfi1_address of the index of the register contents, offset: 0x228 */ __IO uint16_t MAPCAB5TODFI; /**< Maps PHY CAB lane 5 from dfi1_address of the index of the register contents, offset: 0x22A */ __IO uint16_t MAPCAB6TODFI; /**< Maps PHY CAB lane 6 from dfi1_address of the index of the register contents, offset: 0x22C */ __IO uint16_t MAPCAB7TODFI; /**< Maps PHY CAB lane 7 from dfi1_address of the index of the register contents, offset: 0x22E */ __IO uint16_t MAPCAB8TODFI; /**< Maps PHY CAB lane 8 from dfi1_address of the index of the register contents, offset: 0x230 */ __IO uint16_t MAPCAB9TODFI; /**< Maps PHY CAB lane 9 from dfi1_address of the index of the register contents, offset: 0x232 */ uint8_t RESERVED_36[2]; __IO uint16_t PHYINTERRUPTENABLE; /**< Interrupt Enable Bits, offset: 0x236 */ __IO uint16_t PHYINTERRUPTFWCONTROL; /**< Interrupt Firmware Control Bits, offset: 0x238 */ __IO uint16_t PHYINTERRUPTMASK; /**< Interrupt Mask Bits, offset: 0x23A */ __IO uint16_t PHYINTERRUPTCLEAR; /**< Interrupt Clear Bits, offset: 0x23C */ __I uint16_t PHYINTERRUPTSTATUS; /**< Interrupt Status Bits, offset: 0x23E */ __IO uint16_t HWTSWIZZLEHWTADDRESS0; /**< Signal swizzle selection for HWT swizzle, offset: 0x240 */ __IO uint16_t HWTSWIZZLEHWTADDRESS1; /**< Signal swizzle selection for HWT swizzle, offset: 0x242 */ __IO uint16_t HWTSWIZZLEHWTADDRESS2; /**< Signal swizzle selection for HWT swizzle, offset: 0x244 */ __IO uint16_t HWTSWIZZLEHWTADDRESS3; /**< Signal swizzle selection for HWT swizzle, offset: 0x246 */ __IO uint16_t HWTSWIZZLEHWTADDRESS4; /**< Signal swizzle selection for HWT swizzle, offset: 0x248 */ __IO uint16_t HWTSWIZZLEHWTADDRESS5; /**< Signal swizzle selection for HWT swizzle, offset: 0x24A */ __IO uint16_t HWTSWIZZLEHWTADDRESS6; /**< Signal swizzle selection for HWT swizzle, offset: 0x24C */ __IO uint16_t HWTSWIZZLEHWTADDRESS7; /**< Signal swizzle selection for HWT swizzle, offset: 0x24E */ __IO uint16_t HWTSWIZZLEHWTADDRESS8; /**< Signal swizzle selection for HWT swizzle, offset: 0x250 */ __IO uint16_t HWTSWIZZLEHWTADDRESS9; /**< Signal swizzle selection for HWT swizzle, offset: 0x252 */ __IO uint16_t HWTSWIZZLEHWTADDRESS10; /**< Signal swizzle selection for HWT swizzle, offset: 0x254 */ __IO uint16_t HWTSWIZZLEHWTADDRESS11; /**< Signal swizzle selection for HWT swizzle, offset: 0x256 */ __IO uint16_t HWTSWIZZLEHWTADDRESS12; /**< Signal swizzle selection for HWT swizzle, offset: 0x258 */ __IO uint16_t HWTSWIZZLEHWTADDRESS13; /**< Signal swizzle selection for HWT swizzle, offset: 0x25A */ __IO uint16_t HWTSWIZZLEHWTADDRESS14; /**< Signal swizzle selection for HWT swizzle, offset: 0x25C */ __IO uint16_t HWTSWIZZLEHWTADDRESS15; /**< Signal swizzle selection for HWT swizzle, offset: 0x25E */ __IO uint16_t HWTSWIZZLEHWTADDRESS17; /**< Signal swizzle selection for HWT swizzle, offset: 0x260 */ __IO uint16_t HWTSWIZZLEHWTACTN; /**< Signal swizzle selection for HWT swizzle, offset: 0x262 */ __IO uint16_t HWTSWIZZLEHWTBANK0; /**< Signal swizzle selection for HWT swizzle, offset: 0x264 */ __IO uint16_t HWTSWIZZLEHWTBANK1; /**< Signal swizzle selection for HWT swizzle, offset: 0x266 */ __IO uint16_t HWTSWIZZLEHWTBANK2; /**< Signal swizzle selection for HWT swizzle, offset: 0x268 */ __IO uint16_t HWTSWIZZLEHWTBG0; /**< Signal swizzle selection for HWT swizzle, offset: 0x26A */ __IO uint16_t HWTSWIZZLEHWTBG1; /**< Signal swizzle selection for HWT swizzle, offset: 0x26C */ __IO uint16_t HWTSWIZZLEHWTCASN; /**< Signal swizzle selection for HWT swizzle, offset: 0x26E */ __IO uint16_t HWTSWIZZLEHWTRASN; /**< Signal swizzle selection for HWT swizzle, offset: 0x270 */ __IO uint16_t HWTSWIZZLEHWTWEN; /**< Signal swizzle selection for HWT swizzle, offset: 0x272 */ __IO uint16_t HWTSWIZZLEHWTPARITYIN; /**< Signal swizzle selection for HWT swizzle, offset: 0x274 */ uint8_t RESERVED_37[2]; __IO uint16_t DFIHANDSHAKEDELAYS0; /**< Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal assertions exceed the programmed delays, offset: 0x278 */ __IO uint16_t DFIHANDSHAKEDELAYS1; /**< Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal assertions exceed the programmed delays, offset: 0x27A */ uint8_t RESERVED_38[2096532]; __IO uint16_t CALUCLKINFO_P1; /**< Impedance Calibration Clock Ratio, offset: 0x200010 */ uint8_t RESERVED_39[4]; __IO uint16_t SEQ0BDLY0_P1; /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x200016 */ __IO uint16_t SEQ0BDLY1_P1; /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x200018 */ __IO uint16_t SEQ0BDLY2_P1; /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x20001A */ __IO uint16_t SEQ0BDLY3_P1; /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x20001C */ uint8_t RESERVED_40[2]; __IO uint16_t PPTTRAINSETUP_P1; /**< Setup Intervals for DFI PHY Master operations, offset: 0x200020 */ uint8_t RESERVED_41[16]; __IO uint16_t TRISTATEMODECA_P1; /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x200032 */ uint8_t RESERVED_42[12]; __IO uint16_t HWTMRL_P1; /**< HWT MaxReadLatency., offset: 0x200040 */ uint8_t RESERVED_43[6]; __IO uint16_t DQSPREAMBLECONTROL_P1; /**< Control the PHY logic related to the read and write DQS preamble, offset: 0x200048 */ uint8_t RESERVED_44[16]; __IO uint16_t DMIPINPRESENT_P1; /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x20005A */ __IO uint16_t ARDPTRINITVAL_P1; /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x20005C */ uint8_t RESERVED_45[78]; __IO uint16_t PROCODTTIMECTL_P1; /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0x2000AC */ uint8_t RESERVED_46[74]; __IO uint16_t DLLGAINCTL_P1; /**< DLL gain control, offset: 0x2000F8 */ uint8_t RESERVED_47[102]; __IO uint16_t DFIRDDATACSDESTMAP_P1; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x200160 */ uint8_t RESERVED_48[2]; __IO uint16_t VREFINGLOBAL_P1; /**< PHY Global Vref Controls, offset: 0x200164 */ uint8_t RESERVED_49[2]; __IO uint16_t DFIWRDATACSDESTMAP_P1; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x200168 */ uint8_t RESERVED_50[32]; __IO uint16_t PLLCTRL2_P1; /**< PState dependent PLL Control Register 2, offset: 0x20018A */ uint8_t RESERVED_51[2]; __IO uint16_t PLLCTRL1_P1; /**< PState dependent PLL Control Register 1, offset: 0x20018E */ uint8_t RESERVED_52[4]; __IO uint16_t PLLTESTMODE_P1; /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x200194 */ uint8_t RESERVED_53[2]; __IO uint16_t PLLCTRL4_P1; /**< PState dependent PLL Control Register 4, offset: 0x200198 */ uint8_t RESERVED_54[90]; __IO uint16_t DFIFREQRATIO_P1; /**< DFI Frequency Ratio, offset: 0x2001F4 */ uint8_t RESERVED_55[2096666]; __IO uint16_t CALUCLKINFO_P2; /**< Impedance Calibration Clock Ratio, offset: 0x400010 */ uint8_t RESERVED_56[4]; __IO uint16_t SEQ0BDLY0_P2; /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x400016 */ __IO uint16_t SEQ0BDLY1_P2; /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x400018 */ __IO uint16_t SEQ0BDLY2_P2; /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x40001A */ __IO uint16_t SEQ0BDLY3_P2; /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x40001C */ uint8_t RESERVED_57[2]; __IO uint16_t PPTTRAINSETUP_P2; /**< Setup Intervals for DFI PHY Master operations, offset: 0x400020 */ uint8_t RESERVED_58[16]; __IO uint16_t TRISTATEMODECA_P2; /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x400032 */ uint8_t RESERVED_59[12]; __IO uint16_t HWTMRL_P2; /**< HWT MaxReadLatency., offset: 0x400040 */ uint8_t RESERVED_60[6]; __IO uint16_t DQSPREAMBLECONTROL_P2; /**< Control the PHY logic related to the read and write DQS preamble, offset: 0x400048 */ uint8_t RESERVED_61[16]; __IO uint16_t DMIPINPRESENT_P2; /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x40005A */ __IO uint16_t ARDPTRINITVAL_P2; /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x40005C */ uint8_t RESERVED_62[78]; __IO uint16_t PROCODTTIMECTL_P2; /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0x4000AC */ uint8_t RESERVED_63[74]; __IO uint16_t DLLGAINCTL_P2; /**< DLL gain control, offset: 0x4000F8 */ uint8_t RESERVED_64[102]; __IO uint16_t DFIRDDATACSDESTMAP_P2; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x400160 */ uint8_t RESERVED_65[2]; __IO uint16_t VREFINGLOBAL_P2; /**< PHY Global Vref Controls, offset: 0x400164 */ uint8_t RESERVED_66[2]; __IO uint16_t DFIWRDATACSDESTMAP_P2; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x400168 */ uint8_t RESERVED_67[32]; __IO uint16_t PLLCTRL2_P2; /**< PState dependent PLL Control Register 2, offset: 0x40018A */ uint8_t RESERVED_68[2]; __IO uint16_t PLLCTRL1_P2; /**< PState dependent PLL Control Register 1, offset: 0x40018E */ uint8_t RESERVED_69[4]; __IO uint16_t PLLTESTMODE_P2; /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x400194 */ uint8_t RESERVED_70[2]; __IO uint16_t PLLCTRL4_P2; /**< PState dependent PLL Control Register 4, offset: 0x400198 */ uint8_t RESERVED_71[90]; __IO uint16_t DFIFREQRATIO_P2; /**< DFI Frequency Ratio, offset: 0x4001F4 */ uint8_t RESERVED_72[2096666]; __IO uint16_t CALUCLKINFO_P3; /**< Impedance Calibration Clock Ratio, offset: 0x600010 */ uint8_t RESERVED_73[4]; __IO uint16_t SEQ0BDLY0_P3; /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x600016 */ __IO uint16_t SEQ0BDLY1_P3; /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x600018 */ __IO uint16_t SEQ0BDLY2_P3; /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x60001A */ __IO uint16_t SEQ0BDLY3_P3; /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x60001C */ uint8_t RESERVED_74[2]; __IO uint16_t PPTTRAINSETUP_P3; /**< Setup Intervals for DFI PHY Master operations, offset: 0x600020 */ uint8_t RESERVED_75[16]; __IO uint16_t TRISTATEMODECA_P3; /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x600032 */ uint8_t RESERVED_76[12]; __IO uint16_t HWTMRL_P3; /**< HWT MaxReadLatency., offset: 0x600040 */ uint8_t RESERVED_77[6]; __IO uint16_t DQSPREAMBLECONTROL_P3; /**< Control the PHY logic related to the read and write DQS preamble, offset: 0x600048 */ uint8_t RESERVED_78[16]; __IO uint16_t DMIPINPRESENT_P3; /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x60005A */ __IO uint16_t ARDPTRINITVAL_P3; /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x60005C */ uint8_t RESERVED_79[78]; __IO uint16_t PROCODTTIMECTL_P3; /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0x6000AC */ uint8_t RESERVED_80[74]; __IO uint16_t DLLGAINCTL_P3; /**< DLL gain control, offset: 0x6000F8 */ uint8_t RESERVED_81[102]; __IO uint16_t DFIRDDATACSDESTMAP_P3; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x600160 */ uint8_t RESERVED_82[2]; __IO uint16_t VREFINGLOBAL_P3; /**< PHY Global Vref Controls, offset: 0x600164 */ uint8_t RESERVED_83[2]; __IO uint16_t DFIWRDATACSDESTMAP_P3; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x600168 */ uint8_t RESERVED_84[32]; __IO uint16_t PLLCTRL2_P3; /**< PState dependent PLL Control Register 2, offset: 0x60018A */ uint8_t RESERVED_85[2]; __IO uint16_t PLLCTRL1_P3; /**< PState dependent PLL Control Register 1, offset: 0x60018E */ uint8_t RESERVED_86[4]; __IO uint16_t PLLTESTMODE_P3; /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x600194 */ uint8_t RESERVED_87[2]; __IO uint16_t PLLCTRL4_P3; /**< PState dependent PLL Control Register 4, offset: 0x600198 */ uint8_t RESERVED_88[90]; __IO uint16_t DFIFREQRATIO_P3; /**< DFI Frequency Ratio, offset: 0x6001F4 */ } DWC_DDRPHYA_MASTER_Type; /* ---------------------------------------------------------------------------- -- DWC_DDRPHYA_MASTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DWC_DDRPHYA_MASTER_Register_Masks DWC_DDRPHYA_MASTER Register Masks * @{ */ /*! @name RXFIFOINIT - Rx FIFO pointer initialization control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_RXFIFOINIT_RxFifoInitPtr_MASK (0x1U) #define DWC_DDRPHYA_MASTER_RXFIFOINIT_RxFifoInitPtr_SHIFT (0U) #define DWC_DDRPHYA_MASTER_RXFIFOINIT_RxFifoInitPtr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_RXFIFOINIT_RxFifoInitPtr_SHIFT)) & \ DWC_DDRPHYA_MASTER_RXFIFOINIT_RxFifoInitPtr_MASK) #define DWC_DDRPHYA_MASTER_RXFIFOINIT_InhibitRxFifoRd_MASK (0x2U) #define DWC_DDRPHYA_MASTER_RXFIFOINIT_InhibitRxFifoRd_SHIFT (1U) #define DWC_DDRPHYA_MASTER_RXFIFOINIT_InhibitRxFifoRd(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_RXFIFOINIT_InhibitRxFifoRd_SHIFT)) & \ DWC_DDRPHYA_MASTER_RXFIFOINIT_InhibitRxFifoRd_MASK) /*! @} */ /*! @name FORCECLKDISABLE - Clock gating control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_FORCECLKDISABLE_ForceClkDisable_MASK (0xFU) #define DWC_DDRPHYA_MASTER_FORCECLKDISABLE_ForceClkDisable_SHIFT (0U) #define DWC_DDRPHYA_MASTER_FORCECLKDISABLE_ForceClkDisable(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_FORCECLKDISABLE_ForceClkDisable_SHIFT)) & \ DWC_DDRPHYA_MASTER_FORCECLKDISABLE_ForceClkDisable_MASK) /*! @} */ /*! @name FORCEINTERNALUPDATE - This Register used by Training Firmware to force an internal PHY Update Event. */ /*! @{ */ #define DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_ForceInternalUpdate_MASK (0x1U) #define DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_ForceInternalUpdate_SHIFT (0U) #define DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_ForceInternalUpdate(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_ForceInternalUpdate_SHIFT)) & \ DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_ForceInternalUpdate_MASK) /*! @} */ /*! @name PHYCONFIG - Read Only displays PHY Configuration. */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigAnibs_MASK (0xFU) #define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigAnibs_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigAnibs(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigAnibs_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigAnibs_MASK) #define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDbytes_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDbytes_SHIFT (4U) #define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDbytes(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDbytes_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDbytes_MASK) #define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDfi_MASK (0x300U) #define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDfi_SHIFT (8U) #define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDfi_MASK) /*! @} */ /*! @name PGCR - PHY General Configuration Register(PGCR). */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PGCR_RxClkRiseFallMode_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PGCR_RxClkRiseFallMode_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PGCR_RxClkRiseFallMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PGCR_RxClkRiseFallMode_SHIFT)) & \ DWC_DDRPHYA_MASTER_PGCR_RxClkRiseFallMode_MASK) /*! @} */ /*! @name TESTBUMPCNTRL1 - Test Bump Control1 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestMajorMode_MASK (0x7U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestMajorMode_SHIFT (0U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestMajorMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestMajorMode_SHIFT)) & \ DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestMajorMode_MASK) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestBiasBypassEn_MASK (0x8U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestBiasBypassEn_SHIFT (3U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestBiasBypassEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestBiasBypassEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestBiasBypassEn_MASK) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestAnalogOutCtrl_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestAnalogOutCtrl_SHIFT (4U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestAnalogOutCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestAnalogOutCtrl_SHIFT)) & \ DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestAnalogOutCtrl_MASK) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestGainCurrAdj_MASK (0x1F00U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestGainCurrAdj_SHIFT (8U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestGainCurrAdj(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestGainCurrAdj_SHIFT)) & \ DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestGainCurrAdj_MASK) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestSelExternalVref_MASK (0x2000U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestSelExternalVref_SHIFT (13U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestSelExternalVref(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestSelExternalVref_SHIFT)) & \ DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestSelExternalVref_MASK) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestExtVrefRange_MASK (0x4000U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestExtVrefRange_SHIFT (14U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestExtVrefRange(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestExtVrefRange_SHIFT)) & \ DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestExtVrefRange_MASK) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestPowerGateEn_MASK (0x8000U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestPowerGateEn_SHIFT (15U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestPowerGateEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestPowerGateEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestPowerGateEn_MASK) /*! @} */ /*! @name CALUCLKINFO_P0 - Impedance Calibration Clock Ratio */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CalUClkTicksPer1uS_MASK (0x3FFU) #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CalUClkTicksPer1uS_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CalUClkTicksPer1uS(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CalUClkTicksPer1uS_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CalUClkTicksPer1uS_MASK) /*! @} */ /*! @name TESTBUMPCNTRL - Test Bump Control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpEn_MASK (0x3U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpEn_SHIFT (0U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpEn_MASK) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpToggle_MASK (0x4U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpToggle_SHIFT (2U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpToggle(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpToggle_SHIFT)) & \ DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpToggle_MASK) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpDataSel_MASK (0x1F8U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpDataSel_SHIFT (3U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpDataSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpDataSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpDataSel_MASK) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_ForceMtestOnAlert_MASK (0x200U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_ForceMtestOnAlert_SHIFT (9U) #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_ForceMtestOnAlert(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_ForceMtestOnAlert_SHIFT)) & \ DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_ForceMtestOnAlert_MASK) /*! @} */ /*! @name SEQ0BDLY0_P0 - PHY Initialization Engine (PIE) Delay Register 0 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_Seq0BDLY0_p0_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_Seq0BDLY0_p0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_Seq0BDLY0_p0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_Seq0BDLY0_p0_SHIFT)) & \ DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_Seq0BDLY0_p0_MASK) /*! @} */ /*! @name SEQ0BDLY1_P0 - PHY Initialization Engine (PIE) Delay Register 1 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_Seq0BDLY1_p0_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_Seq0BDLY1_p0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_Seq0BDLY1_p0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_Seq0BDLY1_p0_SHIFT)) & \ DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_Seq0BDLY1_p0_MASK) /*! @} */ /*! @name SEQ0BDLY2_P0 - PHY Initialization Engine (PIE) Delay Register 2 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_Seq0BDLY2_p0_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_Seq0BDLY2_p0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_Seq0BDLY2_p0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_Seq0BDLY2_p0_SHIFT)) & \ DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_Seq0BDLY2_p0_MASK) /*! @} */ /*! @name SEQ0BDLY3_P0 - PHY Initialization Engine (PIE) Delay Register 3 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_Seq0BDLY3_p0_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_Seq0BDLY3_p0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_Seq0BDLY3_p0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_Seq0BDLY3_p0_SHIFT)) & \ DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_Seq0BDLY3_p0_MASK) /*! @} */ /*! @name PHYALERTSTATUS - PHY Alert status bit */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PhyAlert_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PhyAlert_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PhyAlert(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PhyAlert_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PhyAlert_MASK) /*! @} */ /*! @name PPTTRAINSETUP_P0 - Setup Intervals for DFI PHY Master operations */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrTrainInterval_MASK (0xFU) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrTrainInterval_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrTrainInterval(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrTrainInterval_SHIFT)) & \ DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrTrainInterval_MASK) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrMaxReqToAck_MASK (0x70U) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrMaxReqToAck_SHIFT (4U) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrMaxReqToAck(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrMaxReqToAck_SHIFT)) & \ DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrMaxReqToAck_MASK) /*! @} */ /*! @name ATESTMODE - ATestMode control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_ATESTMODE_ATestPrbsEn_MASK (0x1U) #define DWC_DDRPHYA_MASTER_ATESTMODE_ATestPrbsEn_SHIFT (0U) #define DWC_DDRPHYA_MASTER_ATESTMODE_ATestPrbsEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ATESTMODE_ATestPrbsEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_ATESTMODE_ATestPrbsEn_MASK) #define DWC_DDRPHYA_MASTER_ATESTMODE_ATestClkEn_MASK (0x2U) #define DWC_DDRPHYA_MASTER_ATESTMODE_ATestClkEn_SHIFT (1U) #define DWC_DDRPHYA_MASTER_ATESTMODE_ATestClkEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ATESTMODE_ATestClkEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_ATESTMODE_ATestClkEn_MASK) #define DWC_DDRPHYA_MASTER_ATESTMODE_ATestModeSel_MASK (0x1CU) #define DWC_DDRPHYA_MASTER_ATESTMODE_ATestModeSel_SHIFT (2U) #define DWC_DDRPHYA_MASTER_ATESTMODE_ATestModeSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ATESTMODE_ATestModeSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_ATESTMODE_ATestModeSel_MASK) /*! @} */ /*! @name TXCALBINP - TX P Impedance Calibration observation */ /*! @{ */ #define DWC_DDRPHYA_MASTER_TXCALBINP_TxCalBinP_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_TXCALBINP_TxCalBinP_SHIFT (0U) #define DWC_DDRPHYA_MASTER_TXCALBINP_TxCalBinP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALBINP_TxCalBinP_SHIFT)) & \ DWC_DDRPHYA_MASTER_TXCALBINP_TxCalBinP_MASK) /*! @} */ /*! @name TXCALBINN - TX N Impedance Calibration observation */ /*! @{ */ #define DWC_DDRPHYA_MASTER_TXCALBINN_TxCalBinN_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_TXCALBINN_TxCalBinN_SHIFT (0U) #define DWC_DDRPHYA_MASTER_TXCALBINN_TxCalBinN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALBINN_TxCalBinN_SHIFT)) & \ DWC_DDRPHYA_MASTER_TXCALBINN_TxCalBinN_MASK) /*! @} */ /*! @name TXCALPOVR - TX P Impedance Calibration override */ /*! @{ */ #define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrVal_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrVal_SHIFT (0U) #define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrVal(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrVal_SHIFT)) & \ DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrVal_MASK) #define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrEn_MASK (0x20U) #define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrEn_SHIFT (5U) #define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrEn_MASK) /*! @} */ /*! @name TXCALNOVR - TX N Impedance Calibration override */ /*! @{ */ #define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrVal_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrVal_SHIFT (0U) #define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrVal(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrVal_SHIFT)) & \ DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrVal_MASK) #define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrEn_MASK (0x20U) #define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrEn_SHIFT (5U) #define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrEn_MASK) /*! @} */ /*! @name DFIMODE - Enables for update and low-power interfaces for DFI0 and DFI1 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIMODE_Dfi0Enable_MASK (0x1U) #define DWC_DDRPHYA_MASTER_DFIMODE_Dfi0Enable_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIMODE_Dfi0Enable(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIMODE_Dfi0Enable_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIMODE_Dfi0Enable_MASK) #define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Enable_MASK (0x2U) #define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Enable_SHIFT (1U) #define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Enable(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Enable_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Enable_MASK) #define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Override_MASK (0x4U) #define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Override_SHIFT (2U) #define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Override(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Override_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Override_MASK) /*! @} */ /*! @name TRISTATEMODECA_P0 - Mode select register for MEMCLK/Address/Command Tristates */ /*! @{ */ #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DisDynAdrTri_MASK (0x1U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DisDynAdrTri_SHIFT (0U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DisDynAdrTri(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DisDynAdrTri_SHIFT)) & \ DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DisDynAdrTri_MASK) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMode_MASK (0x2U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMode_SHIFT (1U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMode_SHIFT)) & \ DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMode_MASK) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CkDisVal_MASK (0xCU) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CkDisVal_SHIFT (2U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CkDisVal(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CkDisVal_SHIFT)) & \ DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CkDisVal_MASK) /*! @} */ /*! @name MTESTMUXSEL - Digital Observation Pin control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MTESTMUXSEL_MtestMuxSel_MASK (0x3FU) #define DWC_DDRPHYA_MASTER_MTESTMUXSEL_MtestMuxSel_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MTESTMUXSEL_MtestMuxSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MTESTMUXSEL_MtestMuxSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_MTESTMUXSEL_MtestMuxSel_MASK) /*! @} */ /*! @name MTESTPGMINFO - Digital Observation Pin program info for debug */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MTESTPGMINFO_MtestPgmInfo_MASK (0x1U) #define DWC_DDRPHYA_MASTER_MTESTPGMINFO_MtestPgmInfo_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MTESTPGMINFO_MtestPgmInfo(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MTESTPGMINFO_MtestPgmInfo_SHIFT)) & \ DWC_DDRPHYA_MASTER_MTESTPGMINFO_MtestPgmInfo_MASK) /*! @} */ /*! @name DYNPWRDNUP - Dynaimc Power Up/Down control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DYNPWRDNUP_DynPowerDown_MASK (0x1U) #define DWC_DDRPHYA_MASTER_DYNPWRDNUP_DynPowerDown_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DYNPWRDNUP_DynPowerDown(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DYNPWRDNUP_DynPowerDown_SHIFT)) & \ DWC_DDRPHYA_MASTER_DYNPWRDNUP_DynPowerDown_MASK) /*! @} */ /*! @name PHYTID - PHY Technology ID Register */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PHYTID_PhyTID_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_PHYTID_PhyTID_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PHYTID_PhyTID(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYTID_PhyTID_SHIFT)) & DWC_DDRPHYA_MASTER_PHYTID_PhyTID_MASK) /*! @} */ /*! @name HWTMRL_P0 - HWT MaxReadLatency. */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTMRL_P0_HwtMRL_p0_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTMRL_P0_HwtMRL_p0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTMRL_P0_HwtMRL_p0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P0_HwtMRL_p0_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTMRL_P0_HwtMRL_p0_MASK) /*! @} */ /*! @name DFIPHYUPD - DFI PhyUpdate Request time counter (in MEMCLKs) */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_MASK (0xFU) #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_MASK) #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_MASK (0x70U) #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_MASK) #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_MASK (0x80U) #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_SHIFT (7U) #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_MASK) #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_MASK (0xF00U) #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_MASK) #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_MASK (0xF000U) #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_SHIFT (12U) #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_MASK) /*! @} */ /*! @name PDAMRSWRITEMODE - Controls the write DQ generation for Per-Dram-Addressing of MRS */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PdaMrsWriteMode_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PdaMrsWriteMode_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PdaMrsWriteMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PdaMrsWriteMode_SHIFT)) & \ DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PdaMrsWriteMode_MASK) /*! @} */ /*! @name DFIGEARDOWNCTL - Controls whether dfi_geardown_en will cause CS and CKE timing to change. */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_MASK (0x3U) #define DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_MASK) /*! @} */ /*! @name DQSPREAMBLECONTROL_P0 - Control the PHY logic related to the read and write DQS preamble */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckRxDqsPre_MASK (0x1U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckRxDqsPre_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckRxDqsPre(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckRxDqsPre_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckRxDqsPre_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckTxDqsPre_MASK (0x2U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckTxDqsPre_SHIFT (1U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckTxDqsPre(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckTxDqsPre_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckTxDqsPre_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_PositionDfeInit_MASK (0x1CU) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_PositionDfeInit_SHIFT (2U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_PositionDfeInit(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_PositionDfeInit_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_PositionDfeInit_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TglTwoTckTxDqsPre_MASK (0x20U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TglTwoTckTxDqsPre_SHIFT (5U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TglTwoTckTxDqsPre(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TglTwoTckTxDqsPre_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TglTwoTckTxDqsPre_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4PostambleExt_MASK (0x40U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4PostambleExt_SHIFT (6U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4PostambleExt(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4PostambleExt_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4PostambleExt_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4SttcPreBridgeRxEn_MASK (0x80U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4SttcPreBridgeRxEn_SHIFT (7U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4SttcPreBridgeRxEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4SttcPreBridgeRxEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4SttcPreBridgeRxEn_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_MASK (0x100U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_MASK) /*! @} */ /*! @name MASTERX4CONFIG - DBYTE module controls to select X4 Dram device mode */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_SHIFT)) & \ DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_MASK) /*! @} */ /*! @name WRLEVBITS - Write level feedback DQ observability select. */ /*! @{ */ #define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSL_MASK (0xFU) #define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSL_SHIFT (0U) #define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSL(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSL_SHIFT)) & \ DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSL_MASK) #define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSU_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSU_SHIFT (4U) #define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSU(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSU_SHIFT)) & \ DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSU_MASK) /*! @} */ /*! @name ENABLECSMULTICAST - In DDR4 Mode , this controls whether CS_N[3:2] should be multicast on CID[1:0] */ /*! @{ */ #define DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_EnableCsMulticast_MASK (0x1U) #define DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_EnableCsMulticast_SHIFT (0U) #define DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_EnableCsMulticast(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_EnableCsMulticast_SHIFT)) & \ DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_EnableCsMulticast_MASK) /*! @} */ /*! @name HWTLPCSMULTICAST - Drives cs_n[0] onto cs_n[1] during training */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HwtLpCsMultiCast_MASK (0x1U) #define DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HwtLpCsMultiCast_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HwtLpCsMultiCast(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HwtLpCsMultiCast_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HwtLpCsMultiCast_MASK) /*! @} */ /*! @name ACX4ANIBDIS - Disable for unused ACX Nibbles */ /*! @{ */ #define DWC_DDRPHYA_MASTER_ACX4ANIBDIS_Acx4AnibDis_MASK (0xFFFU) #define DWC_DDRPHYA_MASTER_ACX4ANIBDIS_Acx4AnibDis_SHIFT (0U) #define DWC_DDRPHYA_MASTER_ACX4ANIBDIS_Acx4AnibDis(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACX4ANIBDIS_Acx4AnibDis_SHIFT)) & \ DWC_DDRPHYA_MASTER_ACX4ANIBDIS_Acx4AnibDis_MASK) /*! @} */ /*! @name DMIPINPRESENT_P0 - This Register is used to enable the Read-DBI function in each DBYTE */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RdDbiEnabled_MASK (0x1U) #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RdDbiEnabled_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RdDbiEnabled(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RdDbiEnabled_SHIFT)) & \ DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RdDbiEnabled_MASK) /*! @} */ /*! @name ARDPTRINITVAL_P0 - Address/Command FIFO ReadPointer Initial Value */ /*! @{ */ #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARdPtrInitVal_p0_MASK (0xFU) #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARdPtrInitVal_p0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARdPtrInitVal_p0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARdPtrInitVal_p0_SHIFT)) & \ DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARdPtrInitVal_p0_MASK) /*! @} */ /*! @name DBYTEDLLMODECNTRL - DLL Mode control CSR for DBYTEs */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DllRxPreambleMode_MASK (0x2U) #define DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DllRxPreambleMode_SHIFT (1U) #define DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DllRxPreambleMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DllRxPreambleMode_SHIFT)) & \ DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DllRxPreambleMode_MASK) /*! @} */ /*! @name CALOFFSETS - Impedance Calibration offsets control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALOFFSETS_CalCmpr5Offset_MASK (0x3FU) #define DWC_DDRPHYA_MASTER_CALOFFSETS_CalCmpr5Offset_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALOFFSETS_CalCmpr5Offset(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALOFFSETS_CalCmpr5Offset_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALOFFSETS_CalCmpr5Offset_MASK) #define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPdThOffset_MASK (0x3C0U) #define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPdThOffset_SHIFT (6U) #define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPdThOffset(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPdThOffset_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPdThOffset_MASK) #define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPuThOffset_MASK (0x3C00U) #define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPuThOffset_SHIFT (10U) #define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPuThOffset(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPuThOffset_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPuThOffset_MASK) /*! @} */ /*! @name SARINITVALS - Sar Init Vals */ /*! @{ */ #define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitOFFSET05_MASK (0x7U) #define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitOFFSET05_SHIFT (0U) #define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitOFFSET05(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SARINITVALS_SarInitOFFSET05_SHIFT)) & \ DWC_DDRPHYA_MASTER_SARINITVALS_SarInitOFFSET05_MASK) #define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitNINT_MASK (0x38U) #define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitNINT_SHIFT (3U) #define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitNINT(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SARINITVALS_SarInitNINT_SHIFT)) & \ DWC_DDRPHYA_MASTER_SARINITVALS_SarInitNINT_MASK) #define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitPEXT_MASK (0x1C0U) #define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitPEXT_SHIFT (6U) #define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitPEXT(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SARINITVALS_SarInitPEXT_SHIFT)) & \ DWC_DDRPHYA_MASTER_SARINITVALS_SarInitPEXT_MASK) /*! @} */ /*! @name CALPEXTOVR - Impedance Calibration PExt Override control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALPEXTOVR_CalPExtOvr_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_CALPEXTOVR_CalPExtOvr_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALPEXTOVR_CalPExtOvr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALPEXTOVR_CalPExtOvr_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALPEXTOVR_CalPExtOvr_MASK) /*! @} */ /*! @name CALCMPR5OVR - Impedance Calibration Cmpr 50 control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALCMPR5OVR_CalCmpr5Ovr_MASK (0xFFU) #define DWC_DDRPHYA_MASTER_CALCMPR5OVR_CalCmpr5Ovr_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALCMPR5OVR_CalCmpr5Ovr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPR5OVR_CalCmpr5Ovr_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALCMPR5OVR_CalCmpr5Ovr_MASK) /*! @} */ /*! @name CALNINTOVR - Impedance Calibration NInt Override control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALNINTOVR_CalNIntOvr_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_CALNINTOVR_CalNIntOvr_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALNINTOVR_CalNIntOvr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALNINTOVR_CalNIntOvr_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALNINTOVR_CalNIntOvr_MASK) /*! @} */ /*! @name CALDRVSTR0 - Impedance Calibration driver strength control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPd50_MASK (0xFU) #define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPd50_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPd50(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPd50_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPd50_MASK) #define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPu50_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPu50_SHIFT (4U) #define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPu50(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPu50_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPu50_MASK) /*! @} */ /*! @name PROCODTTIMECTL_P0 - READ DATA On-Die Termination Timing Control (by PHY) */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtTailWidth_MASK (0x3U) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtTailWidth_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtTailWidth(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtTailWidth_SHIFT)) & \ DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtTailWidth_MASK) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtStartDelay_MASK (0xCU) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtStartDelay_SHIFT (2U) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtStartDelay(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtStartDelay_SHIFT)) & \ DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtStartDelay_MASK) /*! @} */ /*! @name MEMALERTCONTROL - This Register is used to configure the MemAlert Receiver */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefLevel_MASK (0x7FU) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefLevel_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefLevel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefLevel_SHIFT)) & \ DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefLevel_MASK) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefExtEn_MASK (0x80U) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefExtEn_SHIFT (7U) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefExtEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefExtEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefExtEn_MASK) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuStren_MASK (0xF00U) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuStren_SHIFT (8U) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuStren(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuStren_SHIFT)) & \ DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuStren_MASK) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuEn_MASK (0x1000U) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuEn_SHIFT (12U) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuEn_MASK) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRxEn_MASK (0x2000U) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRxEn_SHIFT (13U) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRxEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRxEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRxEn_MASK) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDisableVal_MASK (0x4000U) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDisableVal_SHIFT (14U) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDisableVal(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDisableVal_SHIFT)) & \ DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDisableVal_MASK) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTForceError_MASK (0x8000U) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTForceError_SHIFT (15U) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTForceError(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTForceError_SHIFT)) & \ DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTForceError_MASK) /*! @} */ /*! @name MEMALERTCONTROL2 - This Register is used to configure the MemAlert Receiver */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSyncBypass_MASK (0x1U) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSyncBypass_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSyncBypass(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSyncBypass_SHIFT)) & \ DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSyncBypass_MASK) /*! @} */ /*! @name MEMRESETL - Protection and control of BP_MemReset_L */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MEMRESETL_MemResetLValue_MASK (0x1U) #define DWC_DDRPHYA_MASTER_MEMRESETL_MemResetLValue_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MEMRESETL_MemResetLValue(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMRESETL_MemResetLValue_SHIFT)) & \ DWC_DDRPHYA_MASTER_MEMRESETL_MemResetLValue_MASK) #define DWC_DDRPHYA_MASTER_MEMRESETL_ProtectMemReset_MASK (0x2U) #define DWC_DDRPHYA_MASTER_MEMRESETL_ProtectMemReset_SHIFT (1U) #define DWC_DDRPHYA_MASTER_MEMRESETL_ProtectMemReset(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMRESETL_ProtectMemReset_SHIFT)) & \ DWC_DDRPHYA_MASTER_MEMRESETL_ProtectMemReset_MASK) /*! @} */ /*! @name DRIVECSLOWONTOHIGH - Drive CS_N 3:0 onto CS_N 7:4 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CsLowOntoHigh_MASK (0x1U) #define DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CsLowOntoHigh_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CsLowOntoHigh(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CsLowOntoHigh_SHIFT)) & \ DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CsLowOntoHigh_MASK) /*! @} */ /*! @name PUBMODE - PUBMODE - HWT Mux Select */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PUBMODE_HwtMemSrc_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PUBMODE_HwtMemSrc_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PUBMODE_HwtMemSrc(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PUBMODE_HwtMemSrc_SHIFT)) & \ DWC_DDRPHYA_MASTER_PUBMODE_HwtMemSrc_MASK) /*! @} */ /*! @name MISCPHYSTATUS - Misc PHY status bits */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DctSane_MASK (0x1U) #define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DctSane_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DctSane(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DctSane_SHIFT)) & \ DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DctSane_MASK) #define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMemReset_MASK (0x2U) #define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMemReset_SHIFT (1U) #define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMemReset(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMemReset_SHIFT)) & \ DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMemReset_MASK) /*! @} */ /*! @name CORELOOPBACKSEL - Controls whether the loopback path bypasses the final PAD node. */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CoreLoopbackSel_MASK (0x1U) #define DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CoreLoopbackSel_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CoreLoopbackSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CoreLoopbackSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CoreLoopbackSel_MASK) /*! @} */ /*! @name DLLTRAINPARAM - DLL Various Training Parameters */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DLLTRAINPARAM_ExtendPhdTime_MASK (0x3U) #define DWC_DDRPHYA_MASTER_DLLTRAINPARAM_ExtendPhdTime_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DLLTRAINPARAM_ExtendPhdTime(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLTRAINPARAM_ExtendPhdTime_SHIFT)) & \ DWC_DDRPHYA_MASTER_DLLTRAINPARAM_ExtendPhdTime_MASK) /*! @} */ /*! @name HWTLPCSENBYPASS - CSn Disable Bypass for LPDDR3/4 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HwtLpCsEnBypass_MASK (0x1U) #define DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HwtLpCsEnBypass_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HwtLpCsEnBypass(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HwtLpCsEnBypass_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HwtLpCsEnBypass_MASK) /*! @} */ /*! @name DFICAMODE - Dfi Command/Address Mode */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp3CAMode_MASK (0x1U) #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp3CAMode_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp3CAMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp3CAMode_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp3CAMode_MASK) #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4CAMode_MASK (0x2U) #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4CAMode_SHIFT (1U) #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4CAMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4CAMode_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4CAMode_MASK) #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp4CAMode_MASK (0x4U) #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp4CAMode_SHIFT (2U) #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp4CAMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp4CAMode_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp4CAMode_MASK) #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4AltCAMode_MASK (0x8U) #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4AltCAMode_SHIFT (3U) #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4AltCAMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4AltCAMode_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4AltCAMode_MASK) /*! @} */ /*! @name DLLCONTROL - DLL Lock State machine control register */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRelock_MASK (0x1U) #define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRelock_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRelock(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRelock_SHIFT)) & \ DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRelock_MASK) #define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetSlave_MASK (0x2U) #define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetSlave_SHIFT (1U) #define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetSlave(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetSlave_SHIFT)) & \ DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetSlave_MASK) #define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRSVD_MASK (0x4U) #define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRSVD_SHIFT (2U) #define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRSVD(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRSVD_SHIFT)) & \ DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRSVD_MASK) /*! @} */ /*! @name PULSEDLLUPDATEPHASE - DLL update phase control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseDbyteDllUpdatePhase_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseDbyteDllUpdatePhase_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseDbyteDllUpdatePhase(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseDbyteDllUpdatePhase_SHIFT)) & \ DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseDbyteDllUpdatePhase_MASK) #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACkDllUpdatePhase_MASK (0x2U) #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACkDllUpdatePhase_SHIFT (1U) #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACkDllUpdatePhase(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACkDllUpdatePhase_SHIFT)) & \ DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACkDllUpdatePhase_MASK) #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACaDllUpdatePhase_MASK (0x4U) #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACaDllUpdatePhase_SHIFT (2U) #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACaDllUpdatePhase(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACaDllUpdatePhase_SHIFT)) & \ DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACaDllUpdatePhase_MASK) #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UpdatePhaseDestReserved_MASK (0x38U) #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UpdatePhaseDestReserved_SHIFT (3U) #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UpdatePhaseDestReserved(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UpdatePhaseDestReserved_SHIFT)) & \ DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UpdatePhaseDestReserved_MASK) #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TrainUpdatePhaseOnLongBubble_MASK (0x40U) #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TrainUpdatePhaseOnLongBubble_SHIFT (6U) #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TrainUpdatePhaseOnLongBubble(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TrainUpdatePhaseOnLongBubble_SHIFT)) & \ DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TrainUpdatePhaseOnLongBubble_MASK) #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_AlwaysUpdateLcdlPhase_MASK (0x80U) #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_AlwaysUpdateLcdlPhase_SHIFT (7U) #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_AlwaysUpdateLcdlPhase(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_AlwaysUpdateLcdlPhase_SHIFT)) & \ DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_AlwaysUpdateLcdlPhase_MASK) /*! @} */ /*! @name DLLGAINCTL_P0 - DLL gain control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainIV_MASK (0xFU) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainIV_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainIV(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainIV_SHIFT)) & \ DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainIV_MASK) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainTV_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainTV_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainTV(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainTV_SHIFT)) & \ DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainTV_MASK) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllSeedSel_MASK (0xF00U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllSeedSel_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllSeedSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllSeedSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllSeedSel_MASK) /*! @} */ /*! @name CALRATE - Impedance Calibration Control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALRATE_CalInterval_MASK (0xFU) #define DWC_DDRPHYA_MASTER_CALRATE_CalInterval_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALRATE_CalInterval(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_CalInterval_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALRATE_CalInterval_MASK) #define DWC_DDRPHYA_MASTER_CALRATE_CalRun_MASK (0x10U) #define DWC_DDRPHYA_MASTER_CALRATE_CalRun_SHIFT (4U) #define DWC_DDRPHYA_MASTER_CALRATE_CalRun(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_CalRun_SHIFT)) & DWC_DDRPHYA_MASTER_CALRATE_CalRun_MASK) #define DWC_DDRPHYA_MASTER_CALRATE_CalOnce_MASK (0x20U) #define DWC_DDRPHYA_MASTER_CALRATE_CalOnce_SHIFT (5U) #define DWC_DDRPHYA_MASTER_CALRATE_CalOnce(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_CalOnce_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALRATE_CalOnce_MASK) #define DWC_DDRPHYA_MASTER_CALRATE_DisableBackgroundZQUpdates_MASK (0x40U) #define DWC_DDRPHYA_MASTER_CALRATE_DisableBackgroundZQUpdates_SHIFT (6U) #define DWC_DDRPHYA_MASTER_CALRATE_DisableBackgroundZQUpdates(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_DisableBackgroundZQUpdates_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALRATE_DisableBackgroundZQUpdates_MASK) /*! @} */ /*! @name CALZAP - Impedance Calibration Zap/Reset */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALZAP_CalZap_MASK (0x1U) #define DWC_DDRPHYA_MASTER_CALZAP_CalZap_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALZAP_CalZap(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALZAP_CalZap_SHIFT)) & DWC_DDRPHYA_MASTER_CALZAP_CalZap_MASK) /*! @} */ /*! @name PSTATE - PSTATE Selection */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PSTATE_PState_MASK (0xFU) #define DWC_DDRPHYA_MASTER_PSTATE_PState_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PSTATE_PState(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PSTATE_PState_SHIFT)) & DWC_DDRPHYA_MASTER_PSTATE_PState_MASK) /*! @} */ /*! @name PLLOUTGATECONTROL - PLL Output Control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PclkGateEn_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PclkGateEn_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PclkGateEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PclkGateEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PclkGateEn_MASK) /*! @} */ /*! @name PORCONTROL - PMU Power-on Reset Control (PLL/DLL Lock Done) */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PORCONTROL_PllDllLockDone_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PORCONTROL_PllDllLockDone_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PORCONTROL_PllDllLockDone(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PORCONTROL_PllDllLockDone_SHIFT)) & \ DWC_DDRPHYA_MASTER_PORCONTROL_PllDllLockDone_MASK) /*! @} */ /*! @name CALBUSY - Impedance Calibration Busy Status */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALBUSY_CalBusy_MASK (0x1U) #define DWC_DDRPHYA_MASTER_CALBUSY_CalBusy_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALBUSY_CalBusy(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALBUSY_CalBusy_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALBUSY_CalBusy_MASK) /*! @} */ /*! @name CALMISC2 - Miscellaneous impedance calibration controls. */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALMISC2_CalNumVotes_MASK (0x7U) #define DWC_DDRPHYA_MASTER_CALMISC2_CalNumVotes_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALMISC2_CalNumVotes(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CalNumVotes_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALMISC2_CalNumVotes_MASK) #define DWC_DDRPHYA_MASTER_CALMISC2_CalCmptrResTrim_MASK (0x1000U) #define DWC_DDRPHYA_MASTER_CALMISC2_CalCmptrResTrim_SHIFT (12U) #define DWC_DDRPHYA_MASTER_CALMISC2_CalCmptrResTrim(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CalCmptrResTrim_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALMISC2_CalCmptrResTrim_MASK) #define DWC_DDRPHYA_MASTER_CALMISC2_CalCancelRoundErrDis_MASK (0x2000U) #define DWC_DDRPHYA_MASTER_CALMISC2_CalCancelRoundErrDis_SHIFT (13U) #define DWC_DDRPHYA_MASTER_CALMISC2_CalCancelRoundErrDis(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CalCancelRoundErrDis_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALMISC2_CalCancelRoundErrDis_MASK) #define DWC_DDRPHYA_MASTER_CALMISC2_CalSlowCmpana_MASK (0x4000U) #define DWC_DDRPHYA_MASTER_CALMISC2_CalSlowCmpana_SHIFT (14U) #define DWC_DDRPHYA_MASTER_CALMISC2_CalSlowCmpana(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CalSlowCmpana_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALMISC2_CalSlowCmpana_MASK) /*! @} */ /*! @name CALMISC - Controls for disabling the impedance calibration of certain targets. */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALMISC_CalCmpr5Dis_MASK (0x1U) #define DWC_DDRPHYA_MASTER_CALMISC_CalCmpr5Dis_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALMISC_CalCmpr5Dis(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC_CalCmpr5Dis_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALMISC_CalCmpr5Dis_MASK) #define DWC_DDRPHYA_MASTER_CALMISC_CalNIntDis_MASK (0x2U) #define DWC_DDRPHYA_MASTER_CALMISC_CalNIntDis_SHIFT (1U) #define DWC_DDRPHYA_MASTER_CALMISC_CalNIntDis(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC_CalNIntDis_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALMISC_CalNIntDis_MASK) #define DWC_DDRPHYA_MASTER_CALMISC_CalPExtDis_MASK (0x4U) #define DWC_DDRPHYA_MASTER_CALMISC_CalPExtDis_SHIFT (2U) #define DWC_DDRPHYA_MASTER_CALMISC_CalPExtDis(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC_CalPExtDis_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALMISC_CalPExtDis_MASK) /*! @} */ /*! @name CALVREFS - */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALVREFS_CalVRefs_MASK (0x3U) #define DWC_DDRPHYA_MASTER_CALVREFS_CalVRefs_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALVREFS_CalVRefs(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALVREFS_CalVRefs_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALVREFS_CalVRefs_MASK) /*! @} */ /*! @name CALCMPR5 - Impedance Calibration Cmpr control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALCMPR5_CalCmpr5_MASK (0xFFU) #define DWC_DDRPHYA_MASTER_CALCMPR5_CalCmpr5_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALCMPR5_CalCmpr5(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPR5_CalCmpr5_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALCMPR5_CalCmpr5_MASK) /*! @} */ /*! @name CALNINT - Impedance Calibration NInt control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALNINT_CalNIntThB_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_CALNINT_CalNIntThB_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALNINT_CalNIntThB(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALNINT_CalNIntThB_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALNINT_CalNIntThB_MASK) /*! @} */ /*! @name CALPEXT - Impedance Calibration PExt control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALPEXT_CalPExtThB_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_CALPEXT_CalPExtThB_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALPEXT_CalPExtThB(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALPEXT_CalPExtThB_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALPEXT_CalPExtThB_MASK) /*! @} */ /*! @name CALCMPINVERT - Impedance Calibration Cmp Invert control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDac50_MASK (0x1U) #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDac50_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDac50(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDac50_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDac50_MASK) #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPd50_MASK (0x2U) #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPd50_SHIFT (1U) #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPd50(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPd50_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPd50_MASK) #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPu50_MASK (0x4U) #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPu50_SHIFT (2U) #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPu50(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPu50_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPu50_MASK) #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPd_MASK (0x8U) #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPd_SHIFT (3U) #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPd(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPd_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPd_MASK) #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPu_MASK (0x10U) #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPu_SHIFT (4U) #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPu(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPu_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPu_MASK) /*! @} */ /*! @name CALCMPANACNTRL - Impedance Calibration Cmpana control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainCurrAdj_MASK (0xFFU) #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainCurrAdj_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainCurrAdj(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainCurrAdj_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainCurrAdj_MASK) #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainResAdj_MASK (0x100U) #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainResAdj_SHIFT (8U) #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainResAdj(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainResAdj_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainResAdj_MASK) #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprBiasBypassEn_MASK (0x200U) #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprBiasBypassEn_SHIFT (9U) #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprBiasBypassEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprBiasBypassEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprBiasBypassEn_MASK) /*! @} */ /*! @name DFIRDDATACSDESTMAP_P0 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm0_MASK (0x3U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm0_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm0_MASK) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm1_MASK (0xCU) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm1_SHIFT (2U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm1_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm1_MASK) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm2_MASK (0x30U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm2_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm2_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm2_MASK) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm3_MASK (0xC0U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm3_SHIFT (6U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm3_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm3_MASK) /*! @} */ /*! @name VREFINGLOBAL_P0 - PHY Global Vref Controls */ /*! @{ */ #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInSel_MASK (0x7U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInSel_SHIFT (0U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInSel_MASK) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInDAC_MASK (0x3F8U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInDAC_SHIFT (3U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInDAC(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInDAC_SHIFT)) & \ DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInDAC_MASK) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInTrim_MASK (0x3C00U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInTrim_SHIFT (10U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInTrim(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInTrim_SHIFT)) & \ DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInTrim_MASK) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInMode_MASK (0x4000U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInMode_SHIFT (14U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInMode_SHIFT)) & \ DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInMode_MASK) /*! @} */ /*! @name DFIWRDATACSDESTMAP_P0 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm0_MASK (0x3U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm0_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm0_MASK) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm1_MASK (0xCU) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm1_SHIFT (2U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm1_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm1_MASK) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm2_MASK (0x30U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm2_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm2_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm2_MASK) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm3_MASK (0xC0U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm3_SHIFT (6U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm3_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm3_MASK) /*! @} */ /*! @name MASUPDGOODCTR - Counts successful PHY Master Interface Updates (PPTs) */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MasUpdGoodCtr_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MasUpdGoodCtr_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MasUpdGoodCtr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MasUpdGoodCtr_SHIFT)) & \ DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MasUpdGoodCtr_MASK) /*! @} */ /*! @name PHYUPD0GOODCTR - Counts successful PHY-initiated DFI0 Interface Updates */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PhyUpd0GoodCtr_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PhyUpd0GoodCtr_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PhyUpd0GoodCtr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PhyUpd0GoodCtr_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PhyUpd0GoodCtr_MASK) /*! @} */ /*! @name PHYUPD1GOODCTR - Counts successful PHY-initiated DFI1 Interface Updates */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PhyUpd1GoodCtr_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PhyUpd1GoodCtr_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PhyUpd1GoodCtr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PhyUpd1GoodCtr_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PhyUpd1GoodCtr_MASK) /*! @} */ /*! @name CTLUPD0GOODCTR - Counts successful Memory Controller DFI0 Interface Updates */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CtlUpd0GoodCtr_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CtlUpd0GoodCtr_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CtlUpd0GoodCtr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CtlUpd0GoodCtr_SHIFT)) & \ DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CtlUpd0GoodCtr_MASK) /*! @} */ /*! @name CTLUPD1GOODCTR - Counts successful Memory Controller DFI1 Interface Updates */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CtlUpd1GoodCtr_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CtlUpd1GoodCtr_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CtlUpd1GoodCtr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CtlUpd1GoodCtr_SHIFT)) & \ DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CtlUpd1GoodCtr_MASK) /*! @} */ /*! @name MASUPDFAILCTR - Counts unsuccessful PHY Master Interface Updates */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MasUpdFailCtr_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MasUpdFailCtr_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MasUpdFailCtr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MasUpdFailCtr_SHIFT)) & \ DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MasUpdFailCtr_MASK) /*! @} */ /*! @name PHYUPD0FAILCTR - Counts unsuccessful PHY-initiated DFI0 Interface Updates */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PhyUpd0FailCtr_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PhyUpd0FailCtr_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PhyUpd0FailCtr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PhyUpd0FailCtr_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PhyUpd0FailCtr_MASK) /*! @} */ /*! @name PHYUPD1FAILCTR - Counts unsuccessful PHY-initiated DFI1 Interface Updates */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PhyUpd1FailCtr_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PhyUpd1FailCtr_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PhyUpd1FailCtr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PhyUpd1FailCtr_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PhyUpd1FailCtr_MASK) /*! @} */ /*! @name PHYPERFCTRENABLE - Enables for Performance Counters */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdGoodCtl_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdGoodCtl_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdGoodCtl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdGoodCtl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdGoodCtl_MASK) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0GoodCtl_MASK (0x2U) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0GoodCtl_SHIFT (1U) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0GoodCtl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0GoodCtl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0GoodCtl_MASK) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1GoodCtl_MASK (0x4U) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1GoodCtl_SHIFT (2U) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1GoodCtl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1GoodCtl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1GoodCtl_MASK) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd0GoodCtl_MASK (0x8U) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd0GoodCtl_SHIFT (3U) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd0GoodCtl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd0GoodCtl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd0GoodCtl_MASK) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd1GoodCtl_MASK (0x10U) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd1GoodCtl_SHIFT (4U) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd1GoodCtl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd1GoodCtl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd1GoodCtl_MASK) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdFailCtl_MASK (0x20U) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdFailCtl_SHIFT (5U) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdFailCtl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdFailCtl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdFailCtl_MASK) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0FailCtl_MASK (0x40U) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0FailCtl_SHIFT (6U) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0FailCtl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0FailCtl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0FailCtl_MASK) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1FailCtl_MASK (0x80U) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1FailCtl_SHIFT (7U) #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1FailCtl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1FailCtl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1FailCtl_MASK) /*! @} */ /*! @name PLLPWRDN - PLL Power Down */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLPWRDN_PllPwrDn_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PLLPWRDN_PllPwrDn_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLPWRDN_PllPwrDn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLPWRDN_PllPwrDn_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLPWRDN_PllPwrDn_MASK) /*! @} */ /*! @name PLLRESET - PLL Reset */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLRESET_PllReset_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PLLRESET_PllReset_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLRESET_PllReset(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLRESET_PllReset_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLRESET_PllReset_MASK) /*! @} */ /*! @name PLLCTRL2_P0 - PState dependent PLL Control Register 2 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PllFreqSel_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PllFreqSel_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PllFreqSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PllFreqSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PllFreqSel_MASK) /*! @} */ /*! @name PLLCTRL0 - PLL Control Register 0 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllStandby_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllStandby_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllStandby(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllStandby_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL0_PllStandby_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypSel_MASK (0x2U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypSel_SHIFT (1U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypSel_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllX2Mode_MASK (0x4U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllX2Mode_SHIFT (2U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllX2Mode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllX2Mode_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL0_PllX2Mode_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllOutBypEn_MASK (0x8U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllOutBypEn_SHIFT (3U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllOutBypEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllOutBypEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL0_PllOutBypEn_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllPreset_MASK (0x10U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllPreset_SHIFT (4U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllPreset(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllPreset_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL0_PllPreset_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypassMode_MASK (0x20U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypassMode_SHIFT (5U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypassMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypassMode_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypassMode_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSelDfiFreqRatio_MASK (0x40U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSelDfiFreqRatio_SHIFT (6U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSelDfiFreqRatio(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllSelDfiFreqRatio_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL0_PllSelDfiFreqRatio_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusFlush_MASK (0x80U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusFlush_SHIFT (7U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusFlush(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusFlush_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusFlush_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusByp_MASK (0x100U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusByp_SHIFT (8U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusByp(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusByp_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusByp_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllReserved10x9_MASK (0x600U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllReserved10x9_SHIFT (9U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllReserved10x9(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllReserved10x9_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL0_PllReserved10x9_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllGearShift_MASK (0x800U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllGearShift_SHIFT (11U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllGearShift(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllGearShift_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL0_PllGearShift_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockCntSel_MASK (0x1000U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockCntSel_SHIFT (12U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockCntSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockCntSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockCntSel_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockPhSel_MASK (0x6000U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockPhSel_SHIFT (13U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockPhSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockPhSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockPhSel_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSpareCtrl0_MASK (0x8000U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSpareCtrl0_SHIFT (15U) #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSpareCtrl0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllSpareCtrl0_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL0_PllSpareCtrl0_MASK) /*! @} */ /*! @name PLLCTRL1_P0 - PState dependent PLL Control Register 1 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpIntCtrl_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpIntCtrl_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpIntCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpIntCtrl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpIntCtrl_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpPropCtrl_MASK (0x1E0U) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpPropCtrl_SHIFT (5U) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpPropCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpPropCtrl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpPropCtrl_MASK) /*! @} */ /*! @name PLLTST - PLL Testing Control Register */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstEn_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstEn_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstEn_MASK) #define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstSel_MASK (0x1EU) #define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstSel_SHIFT (1U) #define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstSel_MASK) #define DWC_DDRPHYA_MASTER_PLLTST_PllDigTstSel_MASK (0x1E0U) #define DWC_DDRPHYA_MASTER_PLLTST_PllDigTstSel_SHIFT (5U) #define DWC_DDRPHYA_MASTER_PLLTST_PllDigTstSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTST_PllDigTstSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLTST_PllDigTstSel_MASK) /*! @} */ /*! @name PLLLOCKSTATUS - PLL's pll_lock pin output */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PllLockStatus_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PllLockStatus_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PllLockStatus(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PllLockStatus_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PllLockStatus_MASK) /*! @} */ /*! @name PLLTESTMODE_P0 - Additional controls for PLL CP/VCO modes of operation */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PllTestMode_p0_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PllTestMode_p0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PllTestMode_p0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PllTestMode_p0_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PllTestMode_p0_MASK) /*! @} */ /*! @name PLLCTRL3 - PLL Control Register 3 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllSpare_MASK (0xFU) #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllSpare_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllSpare(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PllSpare_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL3_PllSpare_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllMaxRange_MASK (0x1F0U) #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllMaxRange_SHIFT (4U) #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllMaxRange(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PllMaxRange_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL3_PllMaxRange_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllDacValIn_MASK (0x3E00U) #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllDacValIn_SHIFT (9U) #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllDacValIn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PllDacValIn_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL3_PllDacValIn_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllForceCal_MASK (0x4000U) #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllForceCal_SHIFT (14U) #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllForceCal(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PllForceCal_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL3_PllForceCal_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllEnCal_MASK (0x8000U) #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllEnCal_SHIFT (15U) #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllEnCal(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PllEnCal_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL3_PllEnCal_MASK) /*! @} */ /*! @name PLLCTRL4_P0 - PState dependent PLL Control Register 4 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpIntGsCtrl_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpIntGsCtrl_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpIntGsCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpIntGsCtrl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpIntGsCtrl_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpPropGsCtrl_MASK (0x1E0U) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpPropGsCtrl_SHIFT (5U) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpPropGsCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpPropGsCtrl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpPropGsCtrl_MASK) /*! @} */ /*! @name PLLENDOFCAL - PLL's eoc (end of calibration) output */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLENDOFCAL_PllEndofCal_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PLLENDOFCAL_PllEndofCal_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLENDOFCAL_PllEndofCal(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLENDOFCAL_PllEndofCal_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLENDOFCAL_PllEndofCal_MASK) /*! @} */ /*! @name PLLSTANDBYEFF - PLL's standby_eff (effective standby) output */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PllStandbyEff_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PllStandbyEff_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PllStandbyEff(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PllStandbyEff_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PllStandbyEff_MASK) /*! @} */ /*! @name PLLDACVALOUT - PLL's Dacval_out output */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLDACVALOUT_PllDacValOut_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_PLLDACVALOUT_PllDacValOut_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLDACVALOUT_PllDacValOut(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLDACVALOUT_PllDacValOut_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLDACVALOUT_PllDacValOut_MASK) /*! @} */ /*! @name LCDLDBGCNTL - Controls for use in observing and testing the LCDLs. */ /*! @{ */ #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvrVal_MASK (0x1FFU) #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvrVal_SHIFT (0U) #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvrVal(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvrVal_SHIFT)) & \ DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvrVal_MASK) #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvr_MASK (0x200U) #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvr_SHIFT (9U) #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvr_SHIFT)) & \ DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvr_MASK) #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineSnap_MASK (0x400U) #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineSnap_SHIFT (10U) #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineSnap(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineSnap_SHIFT)) & \ DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineSnap_MASK) #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlTstEnable_MASK (0x800U) #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlTstEnable_SHIFT (11U) #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlTstEnable(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlTstEnable_SHIFT)) & \ DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlTstEnable_MASK) #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlStatusSel_MASK (0xF000U) #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlStatusSel_SHIFT (12U) #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlStatusSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlStatusSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlStatusSel_MASK) /*! @} */ /*! @name ACLCDLSTATUS - Debug status of the DBYTE LCDL */ /*! @{ */ #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlFineSnapVal_MASK (0x3FFU) #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlFineSnapVal_SHIFT (0U) #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlFineSnapVal(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlFineSnapVal_SHIFT)) & \ DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlFineSnapVal_MASK) #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlPhdSnapVal_MASK (0x400U) #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlPhdSnapVal_SHIFT (10U) #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlPhdSnapVal(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlPhdSnapVal_SHIFT)) & \ DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlPhdSnapVal_MASK) #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyLock_MASK (0x800U) #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyLock_SHIFT (11U) #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyLock(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyLock_SHIFT)) & \ DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyLock_MASK) #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyUnlock_MASK (0x1000U) #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyUnlock_SHIFT (12U) #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyUnlock(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyUnlock_SHIFT)) & \ DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyUnlock_MASK) #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlLiveLock_MASK (0x2000U) #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlLiveLock_SHIFT (13U) #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlLiveLock(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlLiveLock_SHIFT)) & \ DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlLiveLock_MASK) /*! @} */ /*! @name CUSTPHYREV - Customer settable by the customer */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_MASK (0x3FU) #define DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_SHIFT)) & \ DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_MASK) /*! @} */ /*! @name PHYREV - The hardware version of this PHY, excluding the PUB */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_MASK (0xFU) #define DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PHYREV_PHYMNR(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_MASK) #define DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_SHIFT (4U) #define DWC_DDRPHYA_MASTER_PHYREV_PHYMDR(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_MASK) #define DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_MASK (0xFF00U) #define DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_SHIFT (8U) #define DWC_DDRPHYA_MASTER_PHYREV_PHYMJR(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_MASK) /*! @} */ /*! @name LP3EXITSEQ0BSTARTVECTOR - Start vector value to be used for LP3-exit or Init PIE Sequence */ /*! @{ */ #define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllEnabled_MASK (0xFU) #define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllEnabled_SHIFT (0U) #define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllEnabled(x) \ (((uint16_t)( \ ((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllEnabled_SHIFT)) & \ DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllEnabled_MASK) #define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllBypassed_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllBypassed_SHIFT (4U) #define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllBypassed(x) \ (((uint16_t)( \ ((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllBypassed_SHIFT)) & \ DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllBypassed_MASK) /*! @} */ /*! @name DFIFREQXLAT0 - DFI Frequency Translation Register 0 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal0_MASK (0xFU) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal0_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal0_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal1_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal1_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal1_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal1_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal2_MASK (0xF00U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal2_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal2_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal2_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal3_MASK (0xF000U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal3_SHIFT (12U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal3_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal3_MASK) /*! @} */ /*! @name DFIFREQXLAT1 - DFI Frequency Translation Register 1 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal4_MASK (0xFU) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal4_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal4(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal4_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal4_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal5_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal5_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal5(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal5_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal5_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal6_MASK (0xF00U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal6_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal6(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal6_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal6_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal7_MASK (0xF000U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal7_SHIFT (12U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal7(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal7_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal7_MASK) /*! @} */ /*! @name DFIFREQXLAT2 - DFI Frequency Translation Register 2 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal8_MASK (0xFU) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal8_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal8(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal8_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal8_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal9_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal9_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal9(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal9_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal9_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal10_MASK (0xF00U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal10_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal10(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal10_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal10_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal11_MASK (0xF000U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal11_SHIFT (12U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal11(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal11_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal11_MASK) /*! @} */ /*! @name DFIFREQXLAT3 - DFI Frequency Translation Register 3 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal12_MASK (0xFU) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal12_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal12(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal12_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal12_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal13_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal13_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal13(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal13_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal13_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal14_MASK (0xF00U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal14_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal14(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal14_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal14_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal15_MASK (0xF000U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal15_SHIFT (12U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal15(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal15_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal15_MASK) /*! @} */ /*! @name DFIFREQXLAT4 - DFI Frequency Translation Register 4 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal16_MASK (0xFU) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal16_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal16(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal16_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal16_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal17_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal17_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal17(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal17_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal17_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal18_MASK (0xF00U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal18_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal18(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal18_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal18_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal19_MASK (0xF000U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal19_SHIFT (12U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal19(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal19_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal19_MASK) /*! @} */ /*! @name DFIFREQXLAT5 - DFI Frequency Translation Register 5 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal20_MASK (0xFU) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal20_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal20(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal20_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal20_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal21_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal21_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal21(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal21_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal21_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal22_MASK (0xF00U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal22_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal22(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal22_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal22_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal23_MASK (0xF000U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal23_SHIFT (12U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal23(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal23_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal23_MASK) /*! @} */ /*! @name DFIFREQXLAT6 - DFI Frequency Translation Register 6 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal24_MASK (0xFU) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal24_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal24(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal24_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal24_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal25_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal25_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal25(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal25_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal25_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal26_MASK (0xF00U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal26_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal26(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal26_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal26_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal27_MASK (0xF000U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal27_SHIFT (12U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal27(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal27_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal27_MASK) /*! @} */ /*! @name DFIFREQXLAT7 - DFI Frequency Translation Register 7 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal28_MASK (0xFU) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal28_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal28(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal28_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal28_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal29_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal29_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal29(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal29_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal29_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal30_MASK (0xF00U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal30_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal30(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal30_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal30_MASK) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal31_MASK (0xF000U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal31_SHIFT (12U) #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal31(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal31_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal31_MASK) /*! @} */ /*! @name TXRDPTRINIT - TxRdPtrInit control register */ /*! @{ */ #define DWC_DDRPHYA_MASTER_TXRDPTRINIT_TxRdPtrInit_MASK (0x1U) #define DWC_DDRPHYA_MASTER_TXRDPTRINIT_TxRdPtrInit_SHIFT (0U) #define DWC_DDRPHYA_MASTER_TXRDPTRINIT_TxRdPtrInit(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXRDPTRINIT_TxRdPtrInit_SHIFT)) & \ DWC_DDRPHYA_MASTER_TXRDPTRINIT_TxRdPtrInit_MASK) /*! @} */ /*! @name DFIINITCOMPLETE - DFI Init Complete control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DfiInitComplete_MASK (0x1U) #define DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DfiInitComplete_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DfiInitComplete(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DfiInitComplete_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DfiInitComplete_MASK) /*! @} */ /*! @name DFIFREQRATIO_P0 - DFI Frequency Ratio */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DfiFreqRatio_p0_MASK (0x3U) #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DfiFreqRatio_p0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DfiFreqRatio_p0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DfiFreqRatio_p0_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DfiFreqRatio_p0_MASK) /*! @} */ /*! @name RXFIFOCHECKS - Enable more frequent consistency checks of the RX FIFOs */ /*! @{ */ #define DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DoFrequentRxFifoChecks_MASK (0x1U) #define DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DoFrequentRxFifoChecks_SHIFT (0U) #define DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DoFrequentRxFifoChecks(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DoFrequentRxFifoChecks_SHIFT)) & \ DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DoFrequentRxFifoChecks_MASK) /*! @} */ /*! @name MTESTDTOCTRL - */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTestDtoCtrl_MASK (0x1U) #define DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTestDtoCtrl_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTestDtoCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTestDtoCtrl_SHIFT)) & \ DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTestDtoCtrl_MASK) /*! @} */ /*! @name MAPCAA0TODFI - Maps PHY CAA lane 0 from dfi0_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MapCAA0toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MapCAA0toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MapCAA0toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MapCAA0toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MapCAA0toDfi_MASK) /*! @} */ /*! @name MAPCAA1TODFI - Maps PHY CAA lane 1 from dfi0_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MapCAA1toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MapCAA1toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MapCAA1toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MapCAA1toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MapCAA1toDfi_MASK) /*! @} */ /*! @name MAPCAA2TODFI - Maps PHY CAA lane 2 from dfi0_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MapCAA2toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MapCAA2toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MapCAA2toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MapCAA2toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MapCAA2toDfi_MASK) /*! @} */ /*! @name MAPCAA3TODFI - Maps PHY CAA lane 3 from dfi0_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MapCAA3toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MapCAA3toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MapCAA3toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MapCAA3toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MapCAA3toDfi_MASK) /*! @} */ /*! @name MAPCAA4TODFI - Maps PHY CAA lane 4 from dfi0_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MapCAA4toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MapCAA4toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MapCAA4toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MapCAA4toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MapCAA4toDfi_MASK) /*! @} */ /*! @name MAPCAA5TODFI - Maps PHY CAA lane 5 from dfi0_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MapCAA5toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MapCAA5toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MapCAA5toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MapCAA5toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MapCAA5toDfi_MASK) /*! @} */ /*! @name MAPCAA6TODFI - Maps PHY CAA lane 6 from dfi0_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MapCAA6toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MapCAA6toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MapCAA6toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MapCAA6toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MapCAA6toDfi_MASK) /*! @} */ /*! @name MAPCAA7TODFI - Maps PHY CAA lane 7 from dfi0_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MapCAA7toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MapCAA7toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MapCAA7toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MapCAA7toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MapCAA7toDfi_MASK) /*! @} */ /*! @name MAPCAA8TODFI - Maps PHY CAA lane 8 from dfi0_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MapCAA8toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MapCAA8toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MapCAA8toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MapCAA8toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MapCAA8toDfi_MASK) /*! @} */ /*! @name MAPCAA9TODFI - Maps PHY CAA lane 9 from dfi0_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MapCAA9toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MapCAA9toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MapCAA9toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MapCAA9toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MapCAA9toDfi_MASK) /*! @} */ /*! @name MAPCAB0TODFI - Maps PHY CAB lane 0 from dfi1_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MapCAB0toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MapCAB0toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MapCAB0toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MapCAB0toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MapCAB0toDfi_MASK) /*! @} */ /*! @name MAPCAB1TODFI - Maps PHY CAB lane 1 from dfi1_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MapCAB1toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MapCAB1toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MapCAB1toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MapCAB1toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MapCAB1toDfi_MASK) /*! @} */ /*! @name MAPCAB2TODFI - Maps PHY CAB lane 2 from dfi1_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MapCAB2toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MapCAB2toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MapCAB2toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MapCAB2toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MapCAB2toDfi_MASK) /*! @} */ /*! @name MAPCAB3TODFI - Maps PHY CAB lane 3 from dfi1_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MapCAB3toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MapCAB3toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MapCAB3toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MapCAB3toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MapCAB3toDfi_MASK) /*! @} */ /*! @name MAPCAB4TODFI - Maps PHY CAB lane 4 from dfi1_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MapCAB4toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MapCAB4toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MapCAB4toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MapCAB4toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MapCAB4toDfi_MASK) /*! @} */ /*! @name MAPCAB5TODFI - Maps PHY CAB lane 5 from dfi1_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MapCAB5toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MapCAB5toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MapCAB5toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MapCAB5toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MapCAB5toDfi_MASK) /*! @} */ /*! @name MAPCAB6TODFI - Maps PHY CAB lane 6 from dfi1_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MapCAB6toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MapCAB6toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MapCAB6toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MapCAB6toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MapCAB6toDfi_MASK) /*! @} */ /*! @name MAPCAB7TODFI - Maps PHY CAB lane 7 from dfi1_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MapCAB7toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MapCAB7toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MapCAB7toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MapCAB7toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MapCAB7toDfi_MASK) /*! @} */ /*! @name MAPCAB8TODFI - Maps PHY CAB lane 8 from dfi1_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MapCAB8toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MapCAB8toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MapCAB8toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MapCAB8toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MapCAB8toDfi_MASK) /*! @} */ /*! @name MAPCAB9TODFI - Maps PHY CAB lane 9 from dfi1_address of the index of the register contents */ /*! @{ */ #define DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MapCAB9toDfi_MASK (0xFU) #define DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MapCAB9toDfi_SHIFT (0U) #define DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MapCAB9toDfi(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MapCAB9toDfi_SHIFT)) & \ DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MapCAB9toDfi_MASK) /*! @} */ /*! @name PHYINTERRUPTENABLE - Interrupt Enable Bits */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngCmpltEn_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngCmpltEn_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngCmpltEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngCmpltEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngCmpltEn_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyInitCmpltEn_MASK (0x2U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyInitCmpltEn_SHIFT (1U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyInitCmpltEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyInitCmpltEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyInitCmpltEn_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngFailEn_MASK (0x4U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngFailEn_SHIFT (2U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngFailEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngFailEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngFailEn_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyFWReservedEn_MASK (0xF8U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyFWReservedEn_SHIFT (3U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyFWReservedEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyFWReservedEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyFWReservedEn_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyVTDriftAlarmEn_MASK (0x300U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyVTDriftAlarmEn_SHIFT (8U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyVTDriftAlarmEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyVTDriftAlarmEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyVTDriftAlarmEn_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyRxFifoCheckEn_MASK (0x400U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyRxFifoCheckEn_SHIFT (10U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyRxFifoCheckEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyRxFifoCheckEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyRxFifoCheckEn_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyHWReservedEn_MASK (0xF800U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyHWReservedEn_SHIFT (11U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyHWReservedEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyHWReservedEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyHWReservedEn_MASK) /*! @} */ /*! @name PHYINTERRUPTFWCONTROL - Interrupt Firmware Control Bits */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngCmpltFW_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngCmpltFW_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngCmpltFW(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngCmpltFW_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngCmpltFW_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyInitCmpltFW_MASK (0x2U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyInitCmpltFW_SHIFT (1U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyInitCmpltFW(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyInitCmpltFW_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyInitCmpltFW_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngFailFW_MASK (0x4U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngFailFW_SHIFT (2U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngFailFW(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngFailFW_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngFailFW_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyFWReservedFW_MASK (0xF8U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyFWReservedFW_SHIFT (3U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyFWReservedFW(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyFWReservedFW_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyFWReservedFW_MASK) /*! @} */ /*! @name PHYINTERRUPTMASK - Interrupt Mask Bits */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngCmpltMsk_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngCmpltMsk_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngCmpltMsk(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngCmpltMsk_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngCmpltMsk_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyInitCmpltMsk_MASK (0x2U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyInitCmpltMsk_SHIFT (1U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyInitCmpltMsk(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyInitCmpltMsk_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyInitCmpltMsk_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngFailMsk_MASK (0x4U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngFailMsk_SHIFT (2U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngFailMsk(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngFailMsk_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngFailMsk_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyFWReservedMsk_MASK (0xF8U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyFWReservedMsk_SHIFT (3U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyFWReservedMsk(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyFWReservedMsk_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyFWReservedMsk_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyVTDriftAlarmMsk_MASK (0x300U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyVTDriftAlarmMsk_SHIFT (8U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyVTDriftAlarmMsk(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyVTDriftAlarmMsk_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyVTDriftAlarmMsk_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyRxFifoCheckMsk_MASK (0x400U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyRxFifoCheckMsk_SHIFT (10U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyRxFifoCheckMsk(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyRxFifoCheckMsk_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyRxFifoCheckMsk_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyHWReservedMsk_MASK (0xF800U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyHWReservedMsk_SHIFT (11U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyHWReservedMsk(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyHWReservedMsk_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyHWReservedMsk_MASK) /*! @} */ /*! @name PHYINTERRUPTCLEAR - Interrupt Clear Bits */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngCmpltClr_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngCmpltClr_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngCmpltClr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngCmpltClr_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngCmpltClr_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyInitCmpltClr_MASK (0x2U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyInitCmpltClr_SHIFT (1U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyInitCmpltClr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyInitCmpltClr_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyInitCmpltClr_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngFailClr_MASK (0x4U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngFailClr_SHIFT (2U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngFailClr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngFailClr_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngFailClr_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyFWReservedClr_MASK (0xF8U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyFWReservedClr_SHIFT (3U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyFWReservedClr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyFWReservedClr_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyFWReservedClr_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyVTDriftAlarmClr_MASK (0x300U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyVTDriftAlarmClr_SHIFT (8U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyVTDriftAlarmClr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyVTDriftAlarmClr_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyVTDriftAlarmClr_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyRxFifoCheckClr_MASK (0x400U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyRxFifoCheckClr_SHIFT (10U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyRxFifoCheckClr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyRxFifoCheckClr_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyRxFifoCheckClr_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyHWReservedClr_MASK (0xF800U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyHWReservedClr_SHIFT (11U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyHWReservedClr(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyHWReservedClr_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyHWReservedClr_MASK) /*! @} */ /*! @name PHYINTERRUPTSTATUS - Interrupt Status Bits */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngCmplt_MASK (0x1U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngCmplt_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngCmplt(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngCmplt_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngCmplt_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyInitCmplt_MASK (0x2U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyInitCmplt_SHIFT (1U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyInitCmplt(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyInitCmplt_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyInitCmplt_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngFail_MASK (0x4U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngFail_SHIFT (2U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngFail(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngFail_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngFail_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyFWReserved_MASK (0xF8U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyFWReserved_SHIFT (3U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyFWReserved(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyFWReserved_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyFWReserved_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDriftAlarm_MASK (0x300U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDriftAlarm_SHIFT (8U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDriftAlarm(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDriftAlarm_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDriftAlarm_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyRxFifoCheck_MASK (0x400U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyRxFifoCheck_SHIFT (10U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyRxFifoCheck(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyRxFifoCheck_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyRxFifoCheck_MASK) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyHWReserved_MASK (0xF800U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyHWReserved_SHIFT (11U) #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyHWReserved(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyHWReserved_SHIFT)) & \ DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyHWReserved_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTADDRESS0 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HwtSwizzleHwtAddress0_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HwtSwizzleHwtAddress0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HwtSwizzleHwtAddress0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HwtSwizzleHwtAddress0_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HwtSwizzleHwtAddress0_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTADDRESS1 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HwtSwizzleHwtAddress1_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HwtSwizzleHwtAddress1_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HwtSwizzleHwtAddress1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HwtSwizzleHwtAddress1_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HwtSwizzleHwtAddress1_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTADDRESS2 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HwtSwizzleHwtAddress2_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HwtSwizzleHwtAddress2_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HwtSwizzleHwtAddress2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HwtSwizzleHwtAddress2_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HwtSwizzleHwtAddress2_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTADDRESS3 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HwtSwizzleHwtAddress3_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HwtSwizzleHwtAddress3_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HwtSwizzleHwtAddress3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HwtSwizzleHwtAddress3_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HwtSwizzleHwtAddress3_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTADDRESS4 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HwtSwizzleHwtAddress4_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HwtSwizzleHwtAddress4_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HwtSwizzleHwtAddress4(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HwtSwizzleHwtAddress4_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HwtSwizzleHwtAddress4_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTADDRESS5 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HwtSwizzleHwtAddress5_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HwtSwizzleHwtAddress5_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HwtSwizzleHwtAddress5(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HwtSwizzleHwtAddress5_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HwtSwizzleHwtAddress5_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTADDRESS6 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HwtSwizzleHwtAddress6_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HwtSwizzleHwtAddress6_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HwtSwizzleHwtAddress6(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HwtSwizzleHwtAddress6_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HwtSwizzleHwtAddress6_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTADDRESS7 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HwtSwizzleHwtAddress7_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HwtSwizzleHwtAddress7_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HwtSwizzleHwtAddress7(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HwtSwizzleHwtAddress7_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HwtSwizzleHwtAddress7_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTADDRESS8 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HwtSwizzleHwtAddress8_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HwtSwizzleHwtAddress8_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HwtSwizzleHwtAddress8(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HwtSwizzleHwtAddress8_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HwtSwizzleHwtAddress8_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTADDRESS9 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HwtSwizzleHwtAddress9_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HwtSwizzleHwtAddress9_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HwtSwizzleHwtAddress9(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HwtSwizzleHwtAddress9_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HwtSwizzleHwtAddress9_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTADDRESS10 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HwtSwizzleHwtAddress10_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HwtSwizzleHwtAddress10_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HwtSwizzleHwtAddress10(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HwtSwizzleHwtAddress10_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HwtSwizzleHwtAddress10_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTADDRESS11 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HwtSwizzleHwtAddress11_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HwtSwizzleHwtAddress11_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HwtSwizzleHwtAddress11(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HwtSwizzleHwtAddress11_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HwtSwizzleHwtAddress11_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTADDRESS12 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HwtSwizzleHwtAddress12_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HwtSwizzleHwtAddress12_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HwtSwizzleHwtAddress12(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HwtSwizzleHwtAddress12_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HwtSwizzleHwtAddress12_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTADDRESS13 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HwtSwizzleHwtAddress13_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HwtSwizzleHwtAddress13_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HwtSwizzleHwtAddress13(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HwtSwizzleHwtAddress13_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HwtSwizzleHwtAddress13_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTADDRESS14 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HwtSwizzleHwtAddress14_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HwtSwizzleHwtAddress14_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HwtSwizzleHwtAddress14(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HwtSwizzleHwtAddress14_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HwtSwizzleHwtAddress14_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTADDRESS15 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HwtSwizzleHwtAddress15_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HwtSwizzleHwtAddress15_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HwtSwizzleHwtAddress15(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HwtSwizzleHwtAddress15_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HwtSwizzleHwtAddress15_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTADDRESS17 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HwtSwizzleHwtAddress17_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HwtSwizzleHwtAddress17_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HwtSwizzleHwtAddress17(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HwtSwizzleHwtAddress17_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HwtSwizzleHwtAddress17_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTACTN - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HwtSwizzleHwtActN_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HwtSwizzleHwtActN_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HwtSwizzleHwtActN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HwtSwizzleHwtActN_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HwtSwizzleHwtActN_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTBANK0 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HwtSwizzleHwtBank0_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HwtSwizzleHwtBank0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HwtSwizzleHwtBank0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HwtSwizzleHwtBank0_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HwtSwizzleHwtBank0_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTBANK1 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HwtSwizzleHwtBank1_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HwtSwizzleHwtBank1_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HwtSwizzleHwtBank1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HwtSwizzleHwtBank1_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HwtSwizzleHwtBank1_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTBANK2 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HwtSwizzleHwtBank2_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HwtSwizzleHwtBank2_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HwtSwizzleHwtBank2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HwtSwizzleHwtBank2_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HwtSwizzleHwtBank2_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTBG0 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HwtSwizzleHwtBg0_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HwtSwizzleHwtBg0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HwtSwizzleHwtBg0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HwtSwizzleHwtBg0_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HwtSwizzleHwtBg0_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTBG1 - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HwtSwizzleHwtBg1_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HwtSwizzleHwtBg1_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HwtSwizzleHwtBg1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HwtSwizzleHwtBg1_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HwtSwizzleHwtBg1_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTCASN - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HwtSwizzleHwtCasN_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HwtSwizzleHwtCasN_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HwtSwizzleHwtCasN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HwtSwizzleHwtCasN_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HwtSwizzleHwtCasN_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTRASN - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HwtSwizzleHwtRasN_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HwtSwizzleHwtRasN_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HwtSwizzleHwtRasN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HwtSwizzleHwtRasN_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HwtSwizzleHwtRasN_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTWEN - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HwtSwizzleHwtWeN_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HwtSwizzleHwtWeN_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HwtSwizzleHwtWeN(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HwtSwizzleHwtWeN_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HwtSwizzleHwtWeN_MASK) /*! @} */ /*! @name HWTSWIZZLEHWTPARITYIN - Signal swizzle selection for HWT swizzle */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HwtSwizzleHwtParityIn_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HwtSwizzleHwtParityIn_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HwtSwizzleHwtParityIn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HwtSwizzleHwtParityIn_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HwtSwizzleHwtParityIn_MASK) /*! @} */ /*! @name DFIHANDSHAKEDELAYS0 - Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal * assertions exceed the programmed delays */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdAckDelay0_MASK (0xFU) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdAckDelay0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdAckDelay0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdAckDelay0_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdAckDelay0_MASK) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdReqDelay0_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdReqDelay0_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdReqDelay0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdReqDelay0_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdReqDelay0_MASK) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdAckDelay0_MASK (0xF00U) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdAckDelay0_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdAckDelay0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdAckDelay0_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdAckDelay0_MASK) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdReqDelay0_MASK (0xF000U) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdReqDelay0_SHIFT (12U) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdReqDelay0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdReqDelay0_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdReqDelay0_MASK) /*! @} */ /*! @name DFIHANDSHAKEDELAYS1 - Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal * assertions exceed the programmed delays */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdAckDelay1_MASK (0xFU) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdAckDelay1_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdAckDelay1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdAckDelay1_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdAckDelay1_MASK) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdReqDelay1_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdReqDelay1_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdReqDelay1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdReqDelay1_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdReqDelay1_MASK) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdAckDelay1_MASK (0xF00U) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdAckDelay1_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdAckDelay1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdAckDelay1_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdAckDelay1_MASK) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdReqDelay1_MASK (0xF000U) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdReqDelay1_SHIFT (12U) #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdReqDelay1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdReqDelay1_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdReqDelay1_MASK) /*! @} */ /*! @name CALUCLKINFO_P1 - Impedance Calibration Clock Ratio */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CalUClkTicksPer1uS_MASK (0x3FFU) #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CalUClkTicksPer1uS_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CalUClkTicksPer1uS(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CalUClkTicksPer1uS_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CalUClkTicksPer1uS_MASK) /*! @} */ /*! @name SEQ0BDLY0_P1 - PHY Initialization Engine (PIE) Delay Register 0 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_Seq0BDLY0_p1_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_Seq0BDLY0_p1_SHIFT (0U) #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_Seq0BDLY0_p1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_Seq0BDLY0_p1_SHIFT)) & \ DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_Seq0BDLY0_p1_MASK) /*! @} */ /*! @name SEQ0BDLY1_P1 - PHY Initialization Engine (PIE) Delay Register 1 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_Seq0BDLY1_p1_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_Seq0BDLY1_p1_SHIFT (0U) #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_Seq0BDLY1_p1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_Seq0BDLY1_p1_SHIFT)) & \ DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_Seq0BDLY1_p1_MASK) /*! @} */ /*! @name SEQ0BDLY2_P1 - PHY Initialization Engine (PIE) Delay Register 2 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_Seq0BDLY2_p1_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_Seq0BDLY2_p1_SHIFT (0U) #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_Seq0BDLY2_p1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_Seq0BDLY2_p1_SHIFT)) & \ DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_Seq0BDLY2_p1_MASK) /*! @} */ /*! @name SEQ0BDLY3_P1 - PHY Initialization Engine (PIE) Delay Register 3 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_Seq0BDLY3_p1_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_Seq0BDLY3_p1_SHIFT (0U) #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_Seq0BDLY3_p1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_Seq0BDLY3_p1_SHIFT)) & \ DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_Seq0BDLY3_p1_MASK) /*! @} */ /*! @name PPTTRAINSETUP_P1 - Setup Intervals for DFI PHY Master operations */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrTrainInterval_MASK (0xFU) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrTrainInterval_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrTrainInterval(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrTrainInterval_SHIFT)) & \ DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrTrainInterval_MASK) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrMaxReqToAck_MASK (0x70U) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrMaxReqToAck_SHIFT (4U) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrMaxReqToAck(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrMaxReqToAck_SHIFT)) & \ DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrMaxReqToAck_MASK) /*! @} */ /*! @name TRISTATEMODECA_P1 - Mode select register for MEMCLK/Address/Command Tristates */ /*! @{ */ #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DisDynAdrTri_MASK (0x1U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DisDynAdrTri_SHIFT (0U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DisDynAdrTri(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DisDynAdrTri_SHIFT)) & \ DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DisDynAdrTri_MASK) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMode_MASK (0x2U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMode_SHIFT (1U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMode_SHIFT)) & \ DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMode_MASK) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CkDisVal_MASK (0xCU) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CkDisVal_SHIFT (2U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CkDisVal(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CkDisVal_SHIFT)) & \ DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CkDisVal_MASK) /*! @} */ /*! @name HWTMRL_P1 - HWT MaxReadLatency. */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTMRL_P1_HwtMRL_p1_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTMRL_P1_HwtMRL_p1_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTMRL_P1_HwtMRL_p1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P1_HwtMRL_p1_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTMRL_P1_HwtMRL_p1_MASK) /*! @} */ /*! @name DQSPREAMBLECONTROL_P1 - Control the PHY logic related to the read and write DQS preamble */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckRxDqsPre_MASK (0x1U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckRxDqsPre_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckRxDqsPre(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckRxDqsPre_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckRxDqsPre_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckTxDqsPre_MASK (0x2U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckTxDqsPre_SHIFT (1U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckTxDqsPre(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckTxDqsPre_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckTxDqsPre_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_PositionDfeInit_MASK (0x1CU) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_PositionDfeInit_SHIFT (2U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_PositionDfeInit(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_PositionDfeInit_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_PositionDfeInit_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TglTwoTckTxDqsPre_MASK (0x20U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TglTwoTckTxDqsPre_SHIFT (5U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TglTwoTckTxDqsPre(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TglTwoTckTxDqsPre_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TglTwoTckTxDqsPre_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4PostambleExt_MASK (0x40U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4PostambleExt_SHIFT (6U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4PostambleExt(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4PostambleExt_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4PostambleExt_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4SttcPreBridgeRxEn_MASK (0x80U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4SttcPreBridgeRxEn_SHIFT (7U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4SttcPreBridgeRxEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4SttcPreBridgeRxEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4SttcPreBridgeRxEn_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_MASK (0x100U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_MASK) /*! @} */ /*! @name DMIPINPRESENT_P1 - This Register is used to enable the Read-DBI function in each DBYTE */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RdDbiEnabled_MASK (0x1U) #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RdDbiEnabled_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RdDbiEnabled(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RdDbiEnabled_SHIFT)) & \ DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RdDbiEnabled_MASK) /*! @} */ /*! @name ARDPTRINITVAL_P1 - Address/Command FIFO ReadPointer Initial Value */ /*! @{ */ #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARdPtrInitVal_p1_MASK (0xFU) #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARdPtrInitVal_p1_SHIFT (0U) #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARdPtrInitVal_p1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARdPtrInitVal_p1_SHIFT)) & \ DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARdPtrInitVal_p1_MASK) /*! @} */ /*! @name PROCODTTIMECTL_P1 - READ DATA On-Die Termination Timing Control (by PHY) */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtTailWidth_MASK (0x3U) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtTailWidth_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtTailWidth(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtTailWidth_SHIFT)) & \ DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtTailWidth_MASK) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtStartDelay_MASK (0xCU) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtStartDelay_SHIFT (2U) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtStartDelay(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtStartDelay_SHIFT)) & \ DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtStartDelay_MASK) /*! @} */ /*! @name DLLGAINCTL_P1 - DLL gain control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainIV_MASK (0xFU) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainIV_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainIV(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainIV_SHIFT)) & \ DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainIV_MASK) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainTV_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainTV_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainTV(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainTV_SHIFT)) & \ DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainTV_MASK) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllSeedSel_MASK (0xF00U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllSeedSel_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllSeedSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllSeedSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllSeedSel_MASK) /*! @} */ /*! @name DFIRDDATACSDESTMAP_P1 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm0_MASK (0x3U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm0_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm0_MASK) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm1_MASK (0xCU) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm1_SHIFT (2U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm1_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm1_MASK) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm2_MASK (0x30U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm2_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm2_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm2_MASK) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm3_MASK (0xC0U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm3_SHIFT (6U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm3_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm3_MASK) /*! @} */ /*! @name VREFINGLOBAL_P1 - PHY Global Vref Controls */ /*! @{ */ #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInSel_MASK (0x7U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInSel_SHIFT (0U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInSel_MASK) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInDAC_MASK (0x3F8U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInDAC_SHIFT (3U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInDAC(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInDAC_SHIFT)) & \ DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInDAC_MASK) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInTrim_MASK (0x3C00U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInTrim_SHIFT (10U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInTrim(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInTrim_SHIFT)) & \ DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInTrim_MASK) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInMode_MASK (0x4000U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInMode_SHIFT (14U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInMode_SHIFT)) & \ DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInMode_MASK) /*! @} */ /*! @name DFIWRDATACSDESTMAP_P1 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm0_MASK (0x3U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm0_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm0_MASK) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm1_MASK (0xCU) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm1_SHIFT (2U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm1_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm1_MASK) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm2_MASK (0x30U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm2_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm2_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm2_MASK) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm3_MASK (0xC0U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm3_SHIFT (6U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm3_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm3_MASK) /*! @} */ /*! @name PLLCTRL2_P1 - PState dependent PLL Control Register 2 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PllFreqSel_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PllFreqSel_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PllFreqSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PllFreqSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PllFreqSel_MASK) /*! @} */ /*! @name PLLCTRL1_P1 - PState dependent PLL Control Register 1 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpIntCtrl_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpIntCtrl_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpIntCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpIntCtrl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpIntCtrl_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpPropCtrl_MASK (0x1E0U) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpPropCtrl_SHIFT (5U) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpPropCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpPropCtrl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpPropCtrl_MASK) /*! @} */ /*! @name PLLTESTMODE_P1 - Additional controls for PLL CP/VCO modes of operation */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PllTestMode_p1_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PllTestMode_p1_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PllTestMode_p1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PllTestMode_p1_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PllTestMode_p1_MASK) /*! @} */ /*! @name PLLCTRL4_P1 - PState dependent PLL Control Register 4 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpIntGsCtrl_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpIntGsCtrl_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpIntGsCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpIntGsCtrl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpIntGsCtrl_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpPropGsCtrl_MASK (0x1E0U) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpPropGsCtrl_SHIFT (5U) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpPropGsCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpPropGsCtrl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpPropGsCtrl_MASK) /*! @} */ /*! @name DFIFREQRATIO_P1 - DFI Frequency Ratio */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DfiFreqRatio_p1_MASK (0x3U) #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DfiFreqRatio_p1_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DfiFreqRatio_p1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DfiFreqRatio_p1_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DfiFreqRatio_p1_MASK) /*! @} */ /*! @name CALUCLKINFO_P2 - Impedance Calibration Clock Ratio */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CalUClkTicksPer1uS_MASK (0x3FFU) #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CalUClkTicksPer1uS_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CalUClkTicksPer1uS(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CalUClkTicksPer1uS_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CalUClkTicksPer1uS_MASK) /*! @} */ /*! @name SEQ0BDLY0_P2 - PHY Initialization Engine (PIE) Delay Register 0 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_Seq0BDLY0_p2_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_Seq0BDLY0_p2_SHIFT (0U) #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_Seq0BDLY0_p2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_Seq0BDLY0_p2_SHIFT)) & \ DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_Seq0BDLY0_p2_MASK) /*! @} */ /*! @name SEQ0BDLY1_P2 - PHY Initialization Engine (PIE) Delay Register 1 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_Seq0BDLY1_p2_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_Seq0BDLY1_p2_SHIFT (0U) #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_Seq0BDLY1_p2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_Seq0BDLY1_p2_SHIFT)) & \ DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_Seq0BDLY1_p2_MASK) /*! @} */ /*! @name SEQ0BDLY2_P2 - PHY Initialization Engine (PIE) Delay Register 2 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_Seq0BDLY2_p2_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_Seq0BDLY2_p2_SHIFT (0U) #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_Seq0BDLY2_p2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_Seq0BDLY2_p2_SHIFT)) & \ DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_Seq0BDLY2_p2_MASK) /*! @} */ /*! @name SEQ0BDLY3_P2 - PHY Initialization Engine (PIE) Delay Register 3 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_Seq0BDLY3_p2_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_Seq0BDLY3_p2_SHIFT (0U) #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_Seq0BDLY3_p2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_Seq0BDLY3_p2_SHIFT)) & \ DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_Seq0BDLY3_p2_MASK) /*! @} */ /*! @name PPTTRAINSETUP_P2 - Setup Intervals for DFI PHY Master operations */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrTrainInterval_MASK (0xFU) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrTrainInterval_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrTrainInterval(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrTrainInterval_SHIFT)) & \ DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrTrainInterval_MASK) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrMaxReqToAck_MASK (0x70U) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrMaxReqToAck_SHIFT (4U) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrMaxReqToAck(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrMaxReqToAck_SHIFT)) & \ DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrMaxReqToAck_MASK) /*! @} */ /*! @name TRISTATEMODECA_P2 - Mode select register for MEMCLK/Address/Command Tristates */ /*! @{ */ #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DisDynAdrTri_MASK (0x1U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DisDynAdrTri_SHIFT (0U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DisDynAdrTri(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DisDynAdrTri_SHIFT)) & \ DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DisDynAdrTri_MASK) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMode_MASK (0x2U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMode_SHIFT (1U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMode_SHIFT)) & \ DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMode_MASK) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CkDisVal_MASK (0xCU) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CkDisVal_SHIFT (2U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CkDisVal(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CkDisVal_SHIFT)) & \ DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CkDisVal_MASK) /*! @} */ /*! @name HWTMRL_P2 - HWT MaxReadLatency. */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTMRL_P2_HwtMRL_p2_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTMRL_P2_HwtMRL_p2_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTMRL_P2_HwtMRL_p2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P2_HwtMRL_p2_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTMRL_P2_HwtMRL_p2_MASK) /*! @} */ /*! @name DQSPREAMBLECONTROL_P2 - Control the PHY logic related to the read and write DQS preamble */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckRxDqsPre_MASK (0x1U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckRxDqsPre_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckRxDqsPre(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckRxDqsPre_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckRxDqsPre_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckTxDqsPre_MASK (0x2U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckTxDqsPre_SHIFT (1U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckTxDqsPre(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckTxDqsPre_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckTxDqsPre_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_PositionDfeInit_MASK (0x1CU) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_PositionDfeInit_SHIFT (2U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_PositionDfeInit(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_PositionDfeInit_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_PositionDfeInit_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TglTwoTckTxDqsPre_MASK (0x20U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TglTwoTckTxDqsPre_SHIFT (5U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TglTwoTckTxDqsPre(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TglTwoTckTxDqsPre_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TglTwoTckTxDqsPre_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4PostambleExt_MASK (0x40U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4PostambleExt_SHIFT (6U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4PostambleExt(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4PostambleExt_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4PostambleExt_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4SttcPreBridgeRxEn_MASK (0x80U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4SttcPreBridgeRxEn_SHIFT (7U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4SttcPreBridgeRxEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4SttcPreBridgeRxEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4SttcPreBridgeRxEn_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_MASK (0x100U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_MASK) /*! @} */ /*! @name DMIPINPRESENT_P2 - This Register is used to enable the Read-DBI function in each DBYTE */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RdDbiEnabled_MASK (0x1U) #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RdDbiEnabled_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RdDbiEnabled(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RdDbiEnabled_SHIFT)) & \ DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RdDbiEnabled_MASK) /*! @} */ /*! @name ARDPTRINITVAL_P2 - Address/Command FIFO ReadPointer Initial Value */ /*! @{ */ #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARdPtrInitVal_p2_MASK (0xFU) #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARdPtrInitVal_p2_SHIFT (0U) #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARdPtrInitVal_p2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARdPtrInitVal_p2_SHIFT)) & \ DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARdPtrInitVal_p2_MASK) /*! @} */ /*! @name PROCODTTIMECTL_P2 - READ DATA On-Die Termination Timing Control (by PHY) */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtTailWidth_MASK (0x3U) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtTailWidth_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtTailWidth(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtTailWidth_SHIFT)) & \ DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtTailWidth_MASK) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtStartDelay_MASK (0xCU) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtStartDelay_SHIFT (2U) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtStartDelay(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtStartDelay_SHIFT)) & \ DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtStartDelay_MASK) /*! @} */ /*! @name DLLGAINCTL_P2 - DLL gain control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainIV_MASK (0xFU) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainIV_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainIV(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainIV_SHIFT)) & \ DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainIV_MASK) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainTV_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainTV_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainTV(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainTV_SHIFT)) & \ DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainTV_MASK) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllSeedSel_MASK (0xF00U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllSeedSel_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllSeedSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllSeedSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllSeedSel_MASK) /*! @} */ /*! @name DFIRDDATACSDESTMAP_P2 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm0_MASK (0x3U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm0_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm0_MASK) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm1_MASK (0xCU) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm1_SHIFT (2U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm1_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm1_MASK) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm2_MASK (0x30U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm2_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm2_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm2_MASK) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm3_MASK (0xC0U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm3_SHIFT (6U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm3_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm3_MASK) /*! @} */ /*! @name VREFINGLOBAL_P2 - PHY Global Vref Controls */ /*! @{ */ #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInSel_MASK (0x7U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInSel_SHIFT (0U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInSel_MASK) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInDAC_MASK (0x3F8U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInDAC_SHIFT (3U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInDAC(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInDAC_SHIFT)) & \ DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInDAC_MASK) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInTrim_MASK (0x3C00U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInTrim_SHIFT (10U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInTrim(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInTrim_SHIFT)) & \ DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInTrim_MASK) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInMode_MASK (0x4000U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInMode_SHIFT (14U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInMode_SHIFT)) & \ DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInMode_MASK) /*! @} */ /*! @name DFIWRDATACSDESTMAP_P2 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm0_MASK (0x3U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm0_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm0_MASK) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm1_MASK (0xCU) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm1_SHIFT (2U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm1_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm1_MASK) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm2_MASK (0x30U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm2_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm2_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm2_MASK) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm3_MASK (0xC0U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm3_SHIFT (6U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm3_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm3_MASK) /*! @} */ /*! @name PLLCTRL2_P2 - PState dependent PLL Control Register 2 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PllFreqSel_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PllFreqSel_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PllFreqSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PllFreqSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PllFreqSel_MASK) /*! @} */ /*! @name PLLCTRL1_P2 - PState dependent PLL Control Register 1 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpIntCtrl_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpIntCtrl_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpIntCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpIntCtrl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpIntCtrl_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpPropCtrl_MASK (0x1E0U) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpPropCtrl_SHIFT (5U) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpPropCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpPropCtrl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpPropCtrl_MASK) /*! @} */ /*! @name PLLTESTMODE_P2 - Additional controls for PLL CP/VCO modes of operation */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PllTestMode_p2_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PllTestMode_p2_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PllTestMode_p2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PllTestMode_p2_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PllTestMode_p2_MASK) /*! @} */ /*! @name PLLCTRL4_P2 - PState dependent PLL Control Register 4 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpIntGsCtrl_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpIntGsCtrl_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpIntGsCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpIntGsCtrl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpIntGsCtrl_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpPropGsCtrl_MASK (0x1E0U) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpPropGsCtrl_SHIFT (5U) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpPropGsCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpPropGsCtrl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpPropGsCtrl_MASK) /*! @} */ /*! @name DFIFREQRATIO_P2 - DFI Frequency Ratio */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DfiFreqRatio_p2_MASK (0x3U) #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DfiFreqRatio_p2_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DfiFreqRatio_p2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DfiFreqRatio_p2_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DfiFreqRatio_p2_MASK) /*! @} */ /*! @name CALUCLKINFO_P3 - Impedance Calibration Clock Ratio */ /*! @{ */ #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CalUClkTicksPer1uS_MASK (0x3FFU) #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CalUClkTicksPer1uS_SHIFT (0U) #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CalUClkTicksPer1uS(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CalUClkTicksPer1uS_SHIFT)) & \ DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CalUClkTicksPer1uS_MASK) /*! @} */ /*! @name SEQ0BDLY0_P3 - PHY Initialization Engine (PIE) Delay Register 0 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_Seq0BDLY0_p3_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_Seq0BDLY0_p3_SHIFT (0U) #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_Seq0BDLY0_p3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_Seq0BDLY0_p3_SHIFT)) & \ DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_Seq0BDLY0_p3_MASK) /*! @} */ /*! @name SEQ0BDLY1_P3 - PHY Initialization Engine (PIE) Delay Register 1 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_Seq0BDLY1_p3_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_Seq0BDLY1_p3_SHIFT (0U) #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_Seq0BDLY1_p3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_Seq0BDLY1_p3_SHIFT)) & \ DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_Seq0BDLY1_p3_MASK) /*! @} */ /*! @name SEQ0BDLY2_P3 - PHY Initialization Engine (PIE) Delay Register 2 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_Seq0BDLY2_p3_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_Seq0BDLY2_p3_SHIFT (0U) #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_Seq0BDLY2_p3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_Seq0BDLY2_p3_SHIFT)) & \ DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_Seq0BDLY2_p3_MASK) /*! @} */ /*! @name SEQ0BDLY3_P3 - PHY Initialization Engine (PIE) Delay Register 3 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_Seq0BDLY3_p3_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_Seq0BDLY3_p3_SHIFT (0U) #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_Seq0BDLY3_p3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_Seq0BDLY3_p3_SHIFT)) & \ DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_Seq0BDLY3_p3_MASK) /*! @} */ /*! @name PPTTRAINSETUP_P3 - Setup Intervals for DFI PHY Master operations */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrTrainInterval_MASK (0xFU) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrTrainInterval_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrTrainInterval(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrTrainInterval_SHIFT)) & \ DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrTrainInterval_MASK) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrMaxReqToAck_MASK (0x70U) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrMaxReqToAck_SHIFT (4U) #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrMaxReqToAck(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrMaxReqToAck_SHIFT)) & \ DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrMaxReqToAck_MASK) /*! @} */ /*! @name TRISTATEMODECA_P3 - Mode select register for MEMCLK/Address/Command Tristates */ /*! @{ */ #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DisDynAdrTri_MASK (0x1U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DisDynAdrTri_SHIFT (0U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DisDynAdrTri(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DisDynAdrTri_SHIFT)) & \ DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DisDynAdrTri_MASK) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMode_MASK (0x2U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMode_SHIFT (1U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMode_SHIFT)) & \ DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMode_MASK) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CkDisVal_MASK (0xCU) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CkDisVal_SHIFT (2U) #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CkDisVal(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CkDisVal_SHIFT)) & \ DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CkDisVal_MASK) /*! @} */ /*! @name HWTMRL_P3 - HWT MaxReadLatency. */ /*! @{ */ #define DWC_DDRPHYA_MASTER_HWTMRL_P3_HwtMRL_p3_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_HWTMRL_P3_HwtMRL_p3_SHIFT (0U) #define DWC_DDRPHYA_MASTER_HWTMRL_P3_HwtMRL_p3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P3_HwtMRL_p3_SHIFT)) & \ DWC_DDRPHYA_MASTER_HWTMRL_P3_HwtMRL_p3_MASK) /*! @} */ /*! @name DQSPREAMBLECONTROL_P3 - Control the PHY logic related to the read and write DQS preamble */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckRxDqsPre_MASK (0x1U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckRxDqsPre_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckRxDqsPre(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckRxDqsPre_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckRxDqsPre_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckTxDqsPre_MASK (0x2U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckTxDqsPre_SHIFT (1U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckTxDqsPre(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckTxDqsPre_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckTxDqsPre_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_PositionDfeInit_MASK (0x1CU) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_PositionDfeInit_SHIFT (2U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_PositionDfeInit(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_PositionDfeInit_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_PositionDfeInit_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TglTwoTckTxDqsPre_MASK (0x20U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TglTwoTckTxDqsPre_SHIFT (5U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TglTwoTckTxDqsPre(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TglTwoTckTxDqsPre_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TglTwoTckTxDqsPre_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4PostambleExt_MASK (0x40U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4PostambleExt_SHIFT (6U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4PostambleExt(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4PostambleExt_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4PostambleExt_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4SttcPreBridgeRxEn_MASK (0x80U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4SttcPreBridgeRxEn_SHIFT (7U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4SttcPreBridgeRxEn(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4SttcPreBridgeRxEn_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4SttcPreBridgeRxEn_MASK) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_MASK (0x100U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_SHIFT)) & \ DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_MASK) /*! @} */ /*! @name DMIPINPRESENT_P3 - This Register is used to enable the Read-DBI function in each DBYTE */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RdDbiEnabled_MASK (0x1U) #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RdDbiEnabled_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RdDbiEnabled(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RdDbiEnabled_SHIFT)) & \ DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RdDbiEnabled_MASK) /*! @} */ /*! @name ARDPTRINITVAL_P3 - Address/Command FIFO ReadPointer Initial Value */ /*! @{ */ #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARdPtrInitVal_p3_MASK (0xFU) #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARdPtrInitVal_p3_SHIFT (0U) #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARdPtrInitVal_p3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARdPtrInitVal_p3_SHIFT)) & \ DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARdPtrInitVal_p3_MASK) /*! @} */ /*! @name PROCODTTIMECTL_P3 - READ DATA On-Die Termination Timing Control (by PHY) */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtTailWidth_MASK (0x3U) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtTailWidth_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtTailWidth(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtTailWidth_SHIFT)) & \ DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtTailWidth_MASK) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtStartDelay_MASK (0xCU) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtStartDelay_SHIFT (2U) #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtStartDelay(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtStartDelay_SHIFT)) & \ DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtStartDelay_MASK) /*! @} */ /*! @name DLLGAINCTL_P3 - DLL gain control */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainIV_MASK (0xFU) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainIV_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainIV(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainIV_SHIFT)) & \ DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainIV_MASK) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainTV_MASK (0xF0U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainTV_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainTV(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainTV_SHIFT)) & \ DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainTV_MASK) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllSeedSel_MASK (0xF00U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllSeedSel_SHIFT (8U) #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllSeedSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllSeedSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllSeedSel_MASK) /*! @} */ /*! @name DFIRDDATACSDESTMAP_P3 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm0_MASK (0x3U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm0_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm0_MASK) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm1_MASK (0xCU) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm1_SHIFT (2U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm1_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm1_MASK) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm2_MASK (0x30U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm2_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm2_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm2_MASK) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm3_MASK (0xC0U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm3_SHIFT (6U) #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm3_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm3_MASK) /*! @} */ /*! @name VREFINGLOBAL_P3 - PHY Global Vref Controls */ /*! @{ */ #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInSel_MASK (0x7U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInSel_SHIFT (0U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInSel_MASK) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInDAC_MASK (0x3F8U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInDAC_SHIFT (3U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInDAC(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInDAC_SHIFT)) & \ DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInDAC_MASK) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInTrim_MASK (0x3C00U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInTrim_SHIFT (10U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInTrim(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInTrim_SHIFT)) & \ DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInTrim_MASK) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInMode_MASK (0x4000U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInMode_SHIFT (14U) #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInMode(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInMode_SHIFT)) & \ DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInMode_MASK) /*! @} */ /*! @name DFIWRDATACSDESTMAP_P3 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm0_MASK (0x3U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm0_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm0(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm0_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm0_MASK) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm1_MASK (0xCU) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm1_SHIFT (2U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm1(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm1_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm1_MASK) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm2_MASK (0x30U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm2_SHIFT (4U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm2(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm2_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm2_MASK) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm3_MASK (0xC0U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm3_SHIFT (6U) #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm3_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm3_MASK) /*! @} */ /*! @name PLLCTRL2_P3 - PState dependent PLL Control Register 2 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PllFreqSel_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PllFreqSel_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PllFreqSel(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PllFreqSel_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PllFreqSel_MASK) /*! @} */ /*! @name PLLCTRL1_P3 - PState dependent PLL Control Register 1 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpIntCtrl_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpIntCtrl_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpIntCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpIntCtrl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpIntCtrl_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpPropCtrl_MASK (0x1E0U) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpPropCtrl_SHIFT (5U) #define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpPropCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpPropCtrl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpPropCtrl_MASK) /*! @} */ /*! @name PLLTESTMODE_P3 - Additional controls for PLL CP/VCO modes of operation */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PllTestMode_p3_MASK (0xFFFFU) #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PllTestMode_p3_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PllTestMode_p3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PllTestMode_p3_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PllTestMode_p3_MASK) /*! @} */ /*! @name PLLCTRL4_P3 - PState dependent PLL Control Register 4 */ /*! @{ */ #define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpIntGsCtrl_MASK (0x1FU) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpIntGsCtrl_SHIFT (0U) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpIntGsCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpIntGsCtrl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpIntGsCtrl_MASK) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpPropGsCtrl_MASK (0x1E0U) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpPropGsCtrl_SHIFT (5U) #define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpPropGsCtrl(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpPropGsCtrl_SHIFT)) & \ DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpPropGsCtrl_MASK) /*! @} */ /*! @name DFIFREQRATIO_P3 - DFI Frequency Ratio */ /*! @{ */ #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DfiFreqRatio_p3_MASK (0x3U) #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DfiFreqRatio_p3_SHIFT (0U) #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DfiFreqRatio_p3(x) \ (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DfiFreqRatio_p3_SHIFT)) & \ DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DfiFreqRatio_p3_MASK) /*! @} */ /*! * @} */ /* end of group DWC_DDRPHYA_MASTER_Register_Masks */ /* DWC_DDRPHYA_MASTER - Peripheral instance base addresses */ /** Peripheral DWC_DDRPHYA_MASTER0 base address */ #define DWC_DDRPHYA_MASTER0_BASE (0x3C020000u) /** Peripheral DWC_DDRPHYA_MASTER0 base pointer */ #define DWC_DDRPHYA_MASTER0 ((DWC_DDRPHYA_MASTER_Type *)DWC_DDRPHYA_MASTER0_BASE) /** Array initializer of DWC_DDRPHYA_MASTER peripheral base addresses */ #define DWC_DDRPHYA_MASTER_BASE_ADDRS \ { \ DWC_DDRPHYA_MASTER0_BASE \ } /** Array initializer of DWC_DDRPHYA_MASTER peripheral base pointers */ #define DWC_DDRPHYA_MASTER_BASE_PTRS \ { \ DWC_DDRPHYA_MASTER0 \ } /*! * @} */ /* end of group DWC_DDRPHYA_MASTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ECSPI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ECSPI_Peripheral_Access_Layer ECSPI Peripheral Access Layer * @{ */ /** ECSPI - Register Layout Typedef */ typedef struct { __I uint32_t RXDATA; /**< Receive Data Register, offset: 0x0 */ __O uint32_t TXDATA; /**< Transmit Data Register, offset: 0x4 */ __IO uint32_t CONREG; /**< Control Register, offset: 0x8 */ __IO uint32_t CONFIGREG; /**< Config Register, offset: 0xC */ __IO uint32_t INTREG; /**< Interrupt Control Register, offset: 0x10 */ __IO uint32_t DMAREG; /**< DMA Control Register, offset: 0x14 */ __IO uint32_t STATREG; /**< Status Register, offset: 0x18 */ __IO uint32_t PERIODREG; /**< Sample Period Control Register, offset: 0x1C */ __IO uint32_t TESTREG; /**< Test Control Register, offset: 0x20 */ uint8_t RESERVED_0[28]; __O uint32_t MSGDATA; /**< Message Data Register, offset: 0x40 */ } ECSPI_Type; /* ---------------------------------------------------------------------------- -- ECSPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ECSPI_Register_Masks ECSPI Register Masks * @{ */ /*! @name RXDATA - Receive Data Register */ /*! @{ */ #define ECSPI_RXDATA_ECSPI_RXDATA_MASK (0xFFFFFFFFU) #define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT (0U) #define ECSPI_RXDATA_ECSPI_RXDATA(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_RXDATA_ECSPI_RXDATA_SHIFT)) & ECSPI_RXDATA_ECSPI_RXDATA_MASK) /*! @} */ /*! @name TXDATA - Transmit Data Register */ /*! @{ */ #define ECSPI_TXDATA_ECSPI_TXDATA_MASK (0xFFFFFFFFU) #define ECSPI_TXDATA_ECSPI_TXDATA_SHIFT (0U) #define ECSPI_TXDATA_ECSPI_TXDATA(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_TXDATA_ECSPI_TXDATA_SHIFT)) & ECSPI_TXDATA_ECSPI_TXDATA_MASK) /*! @} */ /*! @name CONREG - Control Register */ /*! @{ */ #define ECSPI_CONREG_EN_MASK (0x1U) #define ECSPI_CONREG_EN_SHIFT (0U) /*! EN * 0b0..Disable the block. * 0b1..Enable the block. */ #define ECSPI_CONREG_EN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_EN_SHIFT)) & ECSPI_CONREG_EN_MASK) #define ECSPI_CONREG_HT_MASK (0x2U) #define ECSPI_CONREG_HT_SHIFT (1U) /*! HT * 0b0..Disable HT mode. * 0b1..Enable HT mode. */ #define ECSPI_CONREG_HT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_HT_SHIFT)) & ECSPI_CONREG_HT_MASK) #define ECSPI_CONREG_XCH_MASK (0x4U) #define ECSPI_CONREG_XCH_SHIFT (2U) /*! XCH * 0b0..Idle. * 0b1..Initiates exchange (write) or busy (read). */ #define ECSPI_CONREG_XCH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_XCH_SHIFT)) & ECSPI_CONREG_XCH_MASK) #define ECSPI_CONREG_SMC_MASK (0x8U) #define ECSPI_CONREG_SMC_SHIFT (3U) /*! SMC * 0b0..SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst or * multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer to XCH and SS_CTL * descriptions. * 0b1..Immediately starts a SPI burst when data is written in TXFIFO. */ #define ECSPI_CONREG_SMC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_SMC_SHIFT)) & ECSPI_CONREG_SMC_MASK) #define ECSPI_CONREG_CHANNEL_MODE_MASK (0xF0U) #define ECSPI_CONREG_CHANNEL_MODE_SHIFT (4U) /*! CHANNEL_MODE * 0b0000..Slave mode. * 0b0001..Master mode. */ #define ECSPI_CONREG_CHANNEL_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_MODE_SHIFT)) & ECSPI_CONREG_CHANNEL_MODE_MASK) #define ECSPI_CONREG_POST_DIVIDER_MASK (0xF00U) #define ECSPI_CONREG_POST_DIVIDER_SHIFT (8U) /*! POST_DIVIDER * 0b0000..Divide by 1. * 0b0001..Divide by 2. * 0b0010..Divide by 4. * 0b1110..Divide by 2 14 . * 0b1111..Divide by 2 15 . */ #define ECSPI_CONREG_POST_DIVIDER(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_POST_DIVIDER_SHIFT)) & ECSPI_CONREG_POST_DIVIDER_MASK) #define ECSPI_CONREG_PRE_DIVIDER_MASK (0xF000U) #define ECSPI_CONREG_PRE_DIVIDER_SHIFT (12U) /*! PRE_DIVIDER * 0b0000..Divide by 1. * 0b0001..Divide by 2. * 0b0010..Divide by 3. * 0b1101..Divide by 14. * 0b1110..Divide by 15. * 0b1111..Divide by 16. */ #define ECSPI_CONREG_PRE_DIVIDER(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_PRE_DIVIDER_SHIFT)) & ECSPI_CONREG_PRE_DIVIDER_MASK) #define ECSPI_CONREG_DRCTL_MASK (0x30000U) #define ECSPI_CONREG_DRCTL_SHIFT (16U) /*! DRCTL * 0b00..The SPI_RDY signal is a don't care. * 0b01..Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered). * 0b10..Burst will be triggered by a low level of the SPI_RDY signal (level-triggered). * 0b11..Reserved. */ #define ECSPI_CONREG_DRCTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_DRCTL_SHIFT)) & ECSPI_CONREG_DRCTL_MASK) #define ECSPI_CONREG_CHANNEL_SELECT_MASK (0xC0000U) #define ECSPI_CONREG_CHANNEL_SELECT_SHIFT (18U) /*! CHANNEL_SELECT * 0b00..Channel 0 is selected. Chip Select 0 (SS0) will be asserted. * 0b01..Channel 1 is selected. Chip Select 1 (SS1) will be asserted. * 0b10..Channel 2 is selected. Chip Select 2 (SS2) will be asserted. * 0b11..Channel 3 is selected. Chip Select 3 (SS3) will be asserted. */ #define ECSPI_CONREG_CHANNEL_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_SELECT_SHIFT)) & ECSPI_CONREG_CHANNEL_SELECT_MASK) #define ECSPI_CONREG_BURST_LENGTH_MASK (0xFFF00000U) #define ECSPI_CONREG_BURST_LENGTH_SHIFT (20U) /*! BURST_LENGTH * 0b000000000000..A SPI burst contains the 1 LSB in a word. * 0b000000000001..A SPI burst contains the 2 LSB in a word. * 0b000000000010..A SPI burst contains the 3 LSB in a word. * 0b000000011111..A SPI burst contains all 32 bits in a word. * 0b000000100000..A SPI burst contains the 1 LSB in first word and all 32 bits in second word. * 0b000000100001..A SPI burst contains the 2 LSB in first word and all 32 bits in second word. * 0b111111111110..A SPI burst contains the 31 LSB in first word and 2^7 -1 words. * 0b111111111111..A SPI burst contains 2^7 words. */ #define ECSPI_CONREG_BURST_LENGTH(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_BURST_LENGTH_SHIFT)) & ECSPI_CONREG_BURST_LENGTH_MASK) /*! @} */ /*! @name CONFIGREG - Config Register */ /*! @{ */ #define ECSPI_CONFIGREG_SCLK_PHA_MASK (0xFU) #define ECSPI_CONFIGREG_SCLK_PHA_SHIFT (0U) /*! SCLK_PHA * 0b0000..Phase 0 operation. * 0b0001..Phase 1 operation. */ #define ECSPI_CONFIGREG_SCLK_PHA(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_PHA_SHIFT)) & ECSPI_CONFIGREG_SCLK_PHA_MASK) #define ECSPI_CONFIGREG_SCLK_POL_MASK (0xF0U) #define ECSPI_CONFIGREG_SCLK_POL_SHIFT (4U) /*! SCLK_POL * 0b0000..Active high polarity (0 = Idle). * 0b0001..Active low polarity (1 = Idle). */ #define ECSPI_CONFIGREG_SCLK_POL(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_POL_SHIFT)) & ECSPI_CONFIGREG_SCLK_POL_MASK) #define ECSPI_CONFIGREG_SS_CTL_MASK (0xF00U) #define ECSPI_CONFIGREG_SS_CTL_SHIFT (8U) /*! SS_CTL * 0b0000..In master mode - only one SPI burst will be transmitted. * 0b0001..In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be * transmitted. The SPI transfer will automatically stop when the TXFIFO is empty. * 0b0000..In slave mode - an SPI burst is completed when the number of bits received in the shift register is * equal to (BURST LENGTH + 1). Only the n least-significant bits (n = BURST LENGTH[4:0] + 1) of the first * received word are valid. All bits subsequent to the first received word in RXFIFO are valid. * 0b0001..Reserved */ #define ECSPI_CONFIGREG_SS_CTL(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_CTL_SHIFT)) & ECSPI_CONFIGREG_SS_CTL_MASK) #define ECSPI_CONFIGREG_SS_POL_MASK (0xF000U) #define ECSPI_CONFIGREG_SS_POL_SHIFT (12U) /*! SS_POL * 0b0000..Active low. * 0b0001..Active high. */ #define ECSPI_CONFIGREG_SS_POL(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_POL_SHIFT)) & ECSPI_CONFIGREG_SS_POL_MASK) #define ECSPI_CONFIGREG_DATA_CTL_MASK (0xF0000U) #define ECSPI_CONFIGREG_DATA_CTL_SHIFT (16U) /*! DATA_CTL * 0b0000..Stay high. * 0b0001..Stay low. */ #define ECSPI_CONFIGREG_DATA_CTL(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_DATA_CTL_SHIFT)) & ECSPI_CONFIGREG_DATA_CTL_MASK) #define ECSPI_CONFIGREG_SCLK_CTL_MASK (0xF00000U) #define ECSPI_CONFIGREG_SCLK_CTL_SHIFT (20U) /*! SCLK_CTL * 0b0000..Stay low. * 0b0001..Stay high. */ #define ECSPI_CONFIGREG_SCLK_CTL(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_CTL_SHIFT)) & ECSPI_CONFIGREG_SCLK_CTL_MASK) #define ECSPI_CONFIGREG_HT_LENGTH_MASK (0x1F000000U) #define ECSPI_CONFIGREG_HT_LENGTH_SHIFT (24U) #define ECSPI_CONFIGREG_HT_LENGTH(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_HT_LENGTH_SHIFT)) & ECSPI_CONFIGREG_HT_LENGTH_MASK) /*! @} */ /*! @name INTREG - Interrupt Control Register */ /*! @{ */ #define ECSPI_INTREG_TEEN_MASK (0x1U) #define ECSPI_INTREG_TEEN_SHIFT (0U) /*! TEEN * 0b0..Disable * 0b1..Enable */ #define ECSPI_INTREG_TEEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TEEN_SHIFT)) & ECSPI_INTREG_TEEN_MASK) #define ECSPI_INTREG_TDREN_MASK (0x2U) #define ECSPI_INTREG_TDREN_SHIFT (1U) /*! TDREN * 0b0..Disable * 0b1..Enable */ #define ECSPI_INTREG_TDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TDREN_SHIFT)) & ECSPI_INTREG_TDREN_MASK) #define ECSPI_INTREG_TFEN_MASK (0x4U) #define ECSPI_INTREG_TFEN_SHIFT (2U) /*! TFEN * 0b0..Disable * 0b1..Enable */ #define ECSPI_INTREG_TFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TFEN_SHIFT)) & ECSPI_INTREG_TFEN_MASK) #define ECSPI_INTREG_RREN_MASK (0x8U) #define ECSPI_INTREG_RREN_SHIFT (3U) /*! RREN * 0b0..Disable * 0b1..Enable */ #define ECSPI_INTREG_RREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RREN_SHIFT)) & ECSPI_INTREG_RREN_MASK) #define ECSPI_INTREG_RDREN_MASK (0x10U) #define ECSPI_INTREG_RDREN_SHIFT (4U) /*! RDREN * 0b0..Disable * 0b1..Enable */ #define ECSPI_INTREG_RDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RDREN_SHIFT)) & ECSPI_INTREG_RDREN_MASK) #define ECSPI_INTREG_RFEN_MASK (0x20U) #define ECSPI_INTREG_RFEN_SHIFT (5U) /*! RFEN * 0b0..Disable * 0b1..Enable */ #define ECSPI_INTREG_RFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RFEN_SHIFT)) & ECSPI_INTREG_RFEN_MASK) #define ECSPI_INTREG_ROEN_MASK (0x40U) #define ECSPI_INTREG_ROEN_SHIFT (6U) /*! ROEN * 0b0..Disable * 0b1..Enable */ #define ECSPI_INTREG_ROEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_ROEN_SHIFT)) & ECSPI_INTREG_ROEN_MASK) #define ECSPI_INTREG_TCEN_MASK (0x80U) #define ECSPI_INTREG_TCEN_SHIFT (7U) /*! TCEN * 0b0..Disable * 0b1..Enable */ #define ECSPI_INTREG_TCEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TCEN_SHIFT)) & ECSPI_INTREG_TCEN_MASK) /*! @} */ /*! @name DMAREG - DMA Control Register */ /*! @{ */ #define ECSPI_DMAREG_TX_THRESHOLD_MASK (0x3FU) #define ECSPI_DMAREG_TX_THRESHOLD_SHIFT (0U) #define ECSPI_DMAREG_TX_THRESHOLD(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_TX_THRESHOLD_MASK) #define ECSPI_DMAREG_TEDEN_MASK (0x80U) #define ECSPI_DMAREG_TEDEN_SHIFT (7U) /*! TEDEN * 0b0..Disable * 0b1..Enable */ #define ECSPI_DMAREG_TEDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TEDEN_SHIFT)) & ECSPI_DMAREG_TEDEN_MASK) #define ECSPI_DMAREG_RX_THRESHOLD_MASK (0x3F0000U) #define ECSPI_DMAREG_RX_THRESHOLD_SHIFT (16U) #define ECSPI_DMAREG_RX_THRESHOLD(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_RX_THRESHOLD_MASK) #define ECSPI_DMAREG_RXDEN_MASK (0x800000U) #define ECSPI_DMAREG_RXDEN_SHIFT (23U) /*! RXDEN * 0b0..Disable * 0b1..Enable */ #define ECSPI_DMAREG_RXDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXDEN_SHIFT)) & ECSPI_DMAREG_RXDEN_MASK) #define ECSPI_DMAREG_RX_DMA_LENGTH_MASK (0x3F000000U) #define ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT (24U) #define ECSPI_DMAREG_RX_DMA_LENGTH(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT)) & ECSPI_DMAREG_RX_DMA_LENGTH_MASK) #define ECSPI_DMAREG_RXTDEN_MASK (0x80000000U) #define ECSPI_DMAREG_RXTDEN_SHIFT (31U) /*! RXTDEN * 0b0..Disable * 0b1..Enable */ #define ECSPI_DMAREG_RXTDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXTDEN_SHIFT)) & ECSPI_DMAREG_RXTDEN_MASK) /*! @} */ /*! @name STATREG - Status Register */ /*! @{ */ #define ECSPI_STATREG_TE_MASK (0x1U) #define ECSPI_STATREG_TE_SHIFT (0U) /*! TE * 0b0..TXFIFO contains one or more words. * 0b1..TXFIFO is empty. */ #define ECSPI_STATREG_TE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TE_SHIFT)) & ECSPI_STATREG_TE_MASK) #define ECSPI_STATREG_TDR_MASK (0x2U) #define ECSPI_STATREG_TDR_SHIFT (1U) /*! TDR * 0b0..Number of valid data slots in TXFIFO is greater than TX_THRESHOLD. * 0b1..Number of valid data slots in TXFIFO is not greater than TX_THRESHOLD. */ #define ECSPI_STATREG_TDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TDR_SHIFT)) & ECSPI_STATREG_TDR_MASK) #define ECSPI_STATREG_TF_MASK (0x4U) #define ECSPI_STATREG_TF_SHIFT (2U) /*! TF * 0b0..TXFIFO is not Full. * 0b1..TXFIFO is Full. */ #define ECSPI_STATREG_TF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TF_SHIFT)) & ECSPI_STATREG_TF_MASK) #define ECSPI_STATREG_RR_MASK (0x8U) #define ECSPI_STATREG_RR_SHIFT (3U) /*! RR * 0b0..No valid data in RXFIFO. * 0b1..More than 1 word in RXFIFO. */ #define ECSPI_STATREG_RR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RR_SHIFT)) & ECSPI_STATREG_RR_MASK) #define ECSPI_STATREG_RDR_MASK (0x10U) #define ECSPI_STATREG_RDR_SHIFT (4U) /*! RDR * 0b0..When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. * 0b1..When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a DMA TAIL DMA * condition exists. 0b0..When RXTDE is clear - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. * 0b1..When RXTDE is clear - Number of data entries in the RXFIFO is greater than RX_THRESHOLD. */ #define ECSPI_STATREG_RDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RDR_SHIFT)) & ECSPI_STATREG_RDR_MASK) #define ECSPI_STATREG_RF_MASK (0x20U) #define ECSPI_STATREG_RF_SHIFT (5U) /*! RF * 0b0..Not Full. * 0b1..Full. */ #define ECSPI_STATREG_RF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RF_SHIFT)) & ECSPI_STATREG_RF_MASK) #define ECSPI_STATREG_RO_MASK (0x40U) #define ECSPI_STATREG_RO_SHIFT (6U) /*! RO * 0b0..RXFIFO has no overflow. * 0b1..RXFIFO has overflowed. */ #define ECSPI_STATREG_RO(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RO_SHIFT)) & ECSPI_STATREG_RO_MASK) #define ECSPI_STATREG_TC_MASK (0x80U) #define ECSPI_STATREG_TC_SHIFT (7U) /*! TC * 0b0..Transfer in progress. * 0b1..Transfer completed. */ #define ECSPI_STATREG_TC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TC_SHIFT)) & ECSPI_STATREG_TC_MASK) /*! @} */ /*! @name PERIODREG - Sample Period Control Register */ /*! @{ */ #define ECSPI_PERIODREG_SAMPLE_PERIOD_MASK (0x7FFFU) #define ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT (0U) /*! SAMPLE_PERIOD * 0b000000000000000..0 wait states inserted * 0b000000000000001..1 wait state inserted * 0b111111111111110..32766 wait states inserted * 0b111111111111111..32767 wait states inserted */ #define ECSPI_PERIODREG_SAMPLE_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT)) & ECSPI_PERIODREG_SAMPLE_PERIOD_MASK) #define ECSPI_PERIODREG_CSRC_MASK (0x8000U) #define ECSPI_PERIODREG_CSRC_SHIFT (15U) /*! CSRC * 0b0..SPI Clock (SCLK) * 0b1..Low-Frequency Reference Clock (32.768 KHz) */ #define ECSPI_PERIODREG_CSRC(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSRC_SHIFT)) & ECSPI_PERIODREG_CSRC_MASK) #define ECSPI_PERIODREG_CSD_CTL_MASK (0x3F0000U) #define ECSPI_PERIODREG_CSD_CTL_SHIFT (16U) #define ECSPI_PERIODREG_CSD_CTL(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSD_CTL_SHIFT)) & ECSPI_PERIODREG_CSD_CTL_MASK) /*! @} */ /*! @name TESTREG - Test Control Register */ /*! @{ */ #define ECSPI_TESTREG_TXCNT_MASK (0x7FU) #define ECSPI_TESTREG_TXCNT_SHIFT (0U) #define ECSPI_TESTREG_TXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_TXCNT_SHIFT)) & ECSPI_TESTREG_TXCNT_MASK) #define ECSPI_TESTREG_RXCNT_MASK (0x7F00U) #define ECSPI_TESTREG_RXCNT_SHIFT (8U) #define ECSPI_TESTREG_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_RXCNT_SHIFT)) & ECSPI_TESTREG_RXCNT_MASK) #define ECSPI_TESTREG_LBC_MASK (0x80000000U) #define ECSPI_TESTREG_LBC_SHIFT (31U) /*! LBC * 0b0..Not connected. * 0b1..Transmitter and receiver sections internally connected for Loopback. */ #define ECSPI_TESTREG_LBC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_LBC_SHIFT)) & ECSPI_TESTREG_LBC_MASK) /*! @} */ /*! @name MSGDATA - Message Data Register */ /*! @{ */ #define ECSPI_MSGDATA_ECSPI_MSGDATA_MASK (0xFFFFFFFFU) #define ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT (0U) #define ECSPI_MSGDATA_ECSPI_MSGDATA(x) \ (((uint32_t)(((uint32_t)(x)) << ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT)) & ECSPI_MSGDATA_ECSPI_MSGDATA_MASK) /*! @} */ /*! * @} */ /* end of group ECSPI_Register_Masks */ /* ECSPI - Peripheral instance base addresses */ /** Peripheral ECSPI1 base address */ #define ECSPI1_BASE (0x30820000u) /** Peripheral ECSPI1 base pointer */ #define ECSPI1 ((ECSPI_Type *)ECSPI1_BASE) /** Peripheral ECSPI2 base address */ #define ECSPI2_BASE (0x30830000u) /** Peripheral ECSPI2 base pointer */ #define ECSPI2 ((ECSPI_Type *)ECSPI2_BASE) /** Peripheral ECSPI3 base address */ #define ECSPI3_BASE (0x30840000u) /** Peripheral ECSPI3 base pointer */ #define ECSPI3 ((ECSPI_Type *)ECSPI3_BASE) /** Array initializer of ECSPI peripheral base addresses */ #define ECSPI_BASE_ADDRS \ { \ 0u, ECSPI1_BASE, ECSPI2_BASE, ECSPI3_BASE \ } /** Array initializer of ECSPI peripheral base pointers */ #define ECSPI_BASE_PTRS \ { \ (ECSPI_Type *)0u, ECSPI1, ECSPI2, ECSPI3 \ } /** Interrupt vectors for the ECSPI peripheral type */ #define ECSPI_IRQS \ { \ NotAvail_IRQn, ECSPI1_IRQn, ECSPI2_IRQn, ECSPI3_IRQn \ } /*! * @} */ /* end of group ECSPI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ENET Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer * @{ */ /** ENET - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ uint8_t RESERVED_1[4]; __IO uint32_t RDAR; /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */ __IO uint32_t TDAR; /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */ uint8_t RESERVED_2[12]; __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ uint8_t RESERVED_3[24]; __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ uint8_t RESERVED_4[28]; __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ uint8_t RESERVED_5[28]; __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ uint8_t RESERVED_6[60]; __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ uint8_t RESERVED_7[28]; __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ __IO uint32_t TXIC[3]; /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */ uint8_t RESERVED_8[4]; __IO uint32_t RXIC[3]; /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_9[12]; __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ uint8_t RESERVED_10[28]; __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ uint8_t RESERVED_11[24]; __IO uint32_t RDSR1; /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */ __IO uint32_t TDSR1; /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */ __IO uint32_t MRBR1; /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */ __IO uint32_t RDSR2; /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */ __IO uint32_t TDSR2; /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */ __IO uint32_t MRBR2; /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */ uint8_t RESERVED_12[8]; __IO uint32_t RDSR; /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */ __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */ __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */ uint8_t RESERVED_13[4]; __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ uint8_t RESERVED_14[12]; __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ __IO uint32_t RCMR[2]; /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */ uint8_t RESERVED_15[8]; __IO uint32_t DMACFG[2]; /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */ __IO uint32_t RDAR1; /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */ __IO uint32_t TDAR1; /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */ __IO uint32_t RDAR2; /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */ __IO uint32_t TDAR2; /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */ __IO uint32_t QOS; /**< QOS Scheme, offset: 0x1F0 */ uint8_t RESERVED_16[12]; uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */ __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */ __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */ __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ uint8_t RESERVED_17[12]; __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */ __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ uint8_t RESERVED_18[284]; __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ uint8_t RESERVED_19[488]; __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ struct { /* offset: 0x608, array step: 0x8 */ __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ } CHANNEL[4]; } ENET_Type; /* ---------------------------------------------------------------------------- -- ENET Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_Register_Masks ENET Register Masks * @{ */ /*! @name EIR - Interrupt Event Register */ /*! @{ */ #define ENET_EIR_RXB1_MASK (0x1U) #define ENET_EIR_RXB1_SHIFT (0U) #define ENET_EIR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK) #define ENET_EIR_RXF1_MASK (0x2U) #define ENET_EIR_RXF1_SHIFT (1U) #define ENET_EIR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK) #define ENET_EIR_TXB1_MASK (0x4U) #define ENET_EIR_TXB1_SHIFT (2U) #define ENET_EIR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK) #define ENET_EIR_TXF1_MASK (0x8U) #define ENET_EIR_TXF1_SHIFT (3U) #define ENET_EIR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK) #define ENET_EIR_RXB2_MASK (0x10U) #define ENET_EIR_RXB2_SHIFT (4U) #define ENET_EIR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK) #define ENET_EIR_RXF2_MASK (0x20U) #define ENET_EIR_RXF2_SHIFT (5U) #define ENET_EIR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK) #define ENET_EIR_TXB2_MASK (0x40U) #define ENET_EIR_TXB2_SHIFT (6U) #define ENET_EIR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK) #define ENET_EIR_TXF2_MASK (0x80U) #define ENET_EIR_TXF2_SHIFT (7U) #define ENET_EIR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK) #define ENET_EIR_RXFLUSH_0_MASK (0x1000U) #define ENET_EIR_RXFLUSH_0_SHIFT (12U) #define ENET_EIR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK) #define ENET_EIR_RXFLUSH_1_MASK (0x2000U) #define ENET_EIR_RXFLUSH_1_SHIFT (13U) #define ENET_EIR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK) #define ENET_EIR_RXFLUSH_2_MASK (0x4000U) #define ENET_EIR_RXFLUSH_2_SHIFT (14U) #define ENET_EIR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK) #define ENET_EIR_TS_TIMER_MASK (0x8000U) #define ENET_EIR_TS_TIMER_SHIFT (15U) #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) #define ENET_EIR_TS_AVAIL_MASK (0x10000U) #define ENET_EIR_TS_AVAIL_SHIFT (16U) #define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) #define ENET_EIR_WAKEUP_MASK (0x20000U) #define ENET_EIR_WAKEUP_SHIFT (17U) #define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) #define ENET_EIR_PLR_MASK (0x40000U) #define ENET_EIR_PLR_SHIFT (18U) #define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) #define ENET_EIR_UN_MASK (0x80000U) #define ENET_EIR_UN_SHIFT (19U) #define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) #define ENET_EIR_RL_MASK (0x100000U) #define ENET_EIR_RL_SHIFT (20U) #define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) #define ENET_EIR_LC_MASK (0x200000U) #define ENET_EIR_LC_SHIFT (21U) #define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) #define ENET_EIR_EBERR_MASK (0x400000U) #define ENET_EIR_EBERR_SHIFT (22U) #define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) #define ENET_EIR_MII_MASK (0x800000U) #define ENET_EIR_MII_SHIFT (23U) #define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) #define ENET_EIR_RXB_MASK (0x1000000U) #define ENET_EIR_RXB_SHIFT (24U) #define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) #define ENET_EIR_RXF_MASK (0x2000000U) #define ENET_EIR_RXF_SHIFT (25U) #define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) #define ENET_EIR_TXB_MASK (0x4000000U) #define ENET_EIR_TXB_SHIFT (26U) #define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) #define ENET_EIR_TXF_MASK (0x8000000U) #define ENET_EIR_TXF_SHIFT (27U) #define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) #define ENET_EIR_GRA_MASK (0x10000000U) #define ENET_EIR_GRA_SHIFT (28U) #define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) #define ENET_EIR_BABT_MASK (0x20000000U) #define ENET_EIR_BABT_SHIFT (29U) #define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) #define ENET_EIR_BABR_MASK (0x40000000U) #define ENET_EIR_BABR_SHIFT (30U) #define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) /*! @} */ /*! @name EIMR - Interrupt Mask Register */ /*! @{ */ #define ENET_EIMR_RXB1_MASK (0x1U) #define ENET_EIMR_RXB1_SHIFT (0U) #define ENET_EIMR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK) #define ENET_EIMR_RXF1_MASK (0x2U) #define ENET_EIMR_RXF1_SHIFT (1U) #define ENET_EIMR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK) #define ENET_EIMR_TXB1_MASK (0x4U) #define ENET_EIMR_TXB1_SHIFT (2U) #define ENET_EIMR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK) #define ENET_EIMR_TXF1_MASK (0x8U) #define ENET_EIMR_TXF1_SHIFT (3U) #define ENET_EIMR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK) #define ENET_EIMR_RXB2_MASK (0x10U) #define ENET_EIMR_RXB2_SHIFT (4U) #define ENET_EIMR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK) #define ENET_EIMR_RXF2_MASK (0x20U) #define ENET_EIMR_RXF2_SHIFT (5U) #define ENET_EIMR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK) #define ENET_EIMR_TXB2_MASK (0x40U) #define ENET_EIMR_TXB2_SHIFT (6U) #define ENET_EIMR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK) #define ENET_EIMR_TXF2_MASK (0x80U) #define ENET_EIMR_TXF2_SHIFT (7U) #define ENET_EIMR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK) #define ENET_EIMR_RXFLUSH_0_MASK (0x1000U) #define ENET_EIMR_RXFLUSH_0_SHIFT (12U) #define ENET_EIMR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK) #define ENET_EIMR_RXFLUSH_1_MASK (0x2000U) #define ENET_EIMR_RXFLUSH_1_SHIFT (13U) #define ENET_EIMR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK) #define ENET_EIMR_RXFLUSH_2_MASK (0x4000U) #define ENET_EIMR_RXFLUSH_2_SHIFT (14U) #define ENET_EIMR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK) #define ENET_EIMR_TS_TIMER_MASK (0x8000U) #define ENET_EIMR_TS_TIMER_SHIFT (15U) #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) #define ENET_EIMR_TS_AVAIL_MASK (0x10000U) #define ENET_EIMR_TS_AVAIL_SHIFT (16U) #define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) #define ENET_EIMR_WAKEUP_MASK (0x20000U) #define ENET_EIMR_WAKEUP_SHIFT (17U) #define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) #define ENET_EIMR_PLR_MASK (0x40000U) #define ENET_EIMR_PLR_SHIFT (18U) #define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) #define ENET_EIMR_UN_MASK (0x80000U) #define ENET_EIMR_UN_SHIFT (19U) #define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) #define ENET_EIMR_RL_MASK (0x100000U) #define ENET_EIMR_RL_SHIFT (20U) #define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) #define ENET_EIMR_LC_MASK (0x200000U) #define ENET_EIMR_LC_SHIFT (21U) #define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) #define ENET_EIMR_EBERR_MASK (0x400000U) #define ENET_EIMR_EBERR_SHIFT (22U) #define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) #define ENET_EIMR_MII_MASK (0x800000U) #define ENET_EIMR_MII_SHIFT (23U) #define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) #define ENET_EIMR_RXB_MASK (0x1000000U) #define ENET_EIMR_RXB_SHIFT (24U) #define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) #define ENET_EIMR_RXF_MASK (0x2000000U) #define ENET_EIMR_RXF_SHIFT (25U) #define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) #define ENET_EIMR_TXB_MASK (0x4000000U) #define ENET_EIMR_TXB_SHIFT (26U) /*! TXB - TXB Interrupt Mask * 0b0..The corresponding interrupt source is masked. * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) #define ENET_EIMR_TXF_MASK (0x8000000U) #define ENET_EIMR_TXF_SHIFT (27U) /*! TXF - TXF Interrupt Mask * 0b0..The corresponding interrupt source is masked. * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) #define ENET_EIMR_GRA_MASK (0x10000000U) #define ENET_EIMR_GRA_SHIFT (28U) /*! GRA - GRA Interrupt Mask * 0b0..The corresponding interrupt source is masked. * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) #define ENET_EIMR_BABT_MASK (0x20000000U) #define ENET_EIMR_BABT_SHIFT (29U) /*! BABT - BABT Interrupt Mask * 0b0..The corresponding interrupt source is masked. * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) #define ENET_EIMR_BABR_MASK (0x40000000U) #define ENET_EIMR_BABR_SHIFT (30U) /*! BABR - BABR Interrupt Mask * 0b0..The corresponding interrupt source is masked. * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) /*! @} */ /*! @name RDAR - Receive Descriptor Active Register - Ring 0 */ /*! @{ */ #define ENET_RDAR_RDAR_MASK (0x1000000U) #define ENET_RDAR_RDAR_SHIFT (24U) #define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) /*! @} */ /*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */ /*! @{ */ #define ENET_TDAR_TDAR_MASK (0x1000000U) #define ENET_TDAR_TDAR_SHIFT (24U) #define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) /*! @} */ /*! @name ECR - Ethernet Control Register */ /*! @{ */ #define ENET_ECR_RESET_MASK (0x1U) #define ENET_ECR_RESET_SHIFT (0U) #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) #define ENET_ECR_ETHEREN_MASK (0x2U) #define ENET_ECR_ETHEREN_SHIFT (1U) /*! ETHEREN - Ethernet Enable * 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted * frame. 0b1..MAC is enabled, and reception and transmission are possible. */ #define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) #define ENET_ECR_MAGICEN_MASK (0x4U) #define ENET_ECR_MAGICEN_SHIFT (2U) /*! MAGICEN - Magic Packet Detection Enable * 0b0..Magic detection logic disabled. * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. */ #define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) #define ENET_ECR_SLEEP_MASK (0x8U) #define ENET_ECR_SLEEP_SHIFT (3U) /*! SLEEP - Sleep Mode Enable * 0b0..Normal operating mode. * 0b1..Sleep mode. */ #define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) #define ENET_ECR_EN1588_MASK (0x10U) #define ENET_ECR_EN1588_SHIFT (4U) /*! EN1588 - EN1588 Enable * 0b0..Legacy FEC buffer descriptors and functions enabled. * 0b1..Enhanced frame time-stamping functions enabled. */ #define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) #define ENET_ECR_SPEED_MASK (0x20U) #define ENET_ECR_SPEED_SHIFT (5U) /*! SPEED * 0b0..10/100-Mbit/s mode * 0b1..1000-Mbit/s mode */ #define ENET_ECR_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK) #define ENET_ECR_DBGEN_MASK (0x40U) #define ENET_ECR_DBGEN_SHIFT (6U) /*! DBGEN - Debug Enable * 0b0..MAC continues operation in debug mode. * 0b1..MAC enters hardware freeze mode when the processor is in debug mode. */ #define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) #define ENET_ECR_DBSWP_MASK (0x100U) #define ENET_ECR_DBSWP_SHIFT (8U) /*! DBSWP - Descriptor Byte Swapping Enable * 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. * 0b1..The buffer descriptor bytes are swapped to support little-endian devices. */ #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) #define ENET_ECR_SVLANEN_MASK (0x200U) #define ENET_ECR_SVLANEN_SHIFT (9U) /*! SVLANEN - S-VLAN enable * 0b0..Only the EtherType 0x8100 will be considered for VLAN detection. * 0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in * receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the * classification match comparators, RCMRn. */ #define ENET_ECR_SVLANEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK) #define ENET_ECR_VLANUSE2ND_MASK (0x400U) #define ENET_ECR_VLANUSE2ND_SHIFT (10U) /*! VLANUSE2ND - VLAN use second tag * 0b0..Always extract data from the first VLAN tag if it exists. * 0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A * double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The * second tag must be a C-VLAN */ #define ENET_ECR_VLANUSE2ND(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK) #define ENET_ECR_SVLANDBL_MASK (0x800U) #define ENET_ECR_SVLANDBL_SHIFT (11U) #define ENET_ECR_SVLANDBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK) /*! @} */ /*! @name MMFR - MII Management Frame Register */ /*! @{ */ #define ENET_MMFR_DATA_MASK (0xFFFFU) #define ENET_MMFR_DATA_SHIFT (0U) #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) #define ENET_MMFR_TA_MASK (0x30000U) #define ENET_MMFR_TA_SHIFT (16U) #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) #define ENET_MMFR_RA_MASK (0x7C0000U) #define ENET_MMFR_RA_SHIFT (18U) #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) #define ENET_MMFR_PA_MASK (0xF800000U) #define ENET_MMFR_PA_SHIFT (23U) #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) #define ENET_MMFR_OP_MASK (0x30000000U) #define ENET_MMFR_OP_SHIFT (28U) #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) #define ENET_MMFR_ST_MASK (0xC0000000U) #define ENET_MMFR_ST_SHIFT (30U) #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) /*! @} */ /*! @name MSCR - MII Speed Control Register */ /*! @{ */ #define ENET_MSCR_MII_SPEED_MASK (0x7EU) #define ENET_MSCR_MII_SPEED_SHIFT (1U) #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) #define ENET_MSCR_DIS_PRE_MASK (0x80U) #define ENET_MSCR_DIS_PRE_SHIFT (7U) /*! DIS_PRE - Disable Preamble * 0b0..Preamble enabled. * 0b1..Preamble (32 ones) is not prepended to the MII management frame. */ #define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) #define ENET_MSCR_HOLDTIME_MASK (0x700U) #define ENET_MSCR_HOLDTIME_SHIFT (8U) /*! HOLDTIME - Hold time On MDIO Output * 0b000..1 internal module clock cycle * 0b001..2 internal module clock cycles * 0b010..3 internal module clock cycles * 0b111..8 internal module clock cycles */ #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) /*! @} */ /*! @name MIBC - MIB Control Register */ /*! @{ */ #define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) #define ENET_MIBC_MIB_CLEAR_SHIFT (29U) /*! MIB_CLEAR - MIB Clear * 0b0..See note above. * 0b1..All statistics counters are reset to 0. */ #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) #define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) #define ENET_MIBC_MIB_IDLE_SHIFT (30U) /*! MIB_IDLE - MIB Idle * 0b0..The MIB block is updating MIB counters. * 0b1..The MIB block is not currently updating any MIB counters. */ #define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) #define ENET_MIBC_MIB_DIS_MASK (0x80000000U) #define ENET_MIBC_MIB_DIS_SHIFT (31U) /*! MIB_DIS - Disable MIB Logic * 0b0..MIB logic is enabled. * 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters. */ #define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) /*! @} */ /*! @name RCR - Receive Control Register */ /*! @{ */ #define ENET_RCR_LOOP_MASK (0x1U) #define ENET_RCR_LOOP_SHIFT (0U) /*! LOOP - Internal Loopback * 0b0..Loopback disabled. * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT * must be cleared. */ #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) #define ENET_RCR_DRT_MASK (0x2U) #define ENET_RCR_DRT_SHIFT (1U) /*! DRT - Disable Receive On Transmit * 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit * activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex * mode.) */ #define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) #define ENET_RCR_MII_MODE_MASK (0x4U) #define ENET_RCR_MII_MODE_SHIFT (2U) /*! MII_MODE - Media Independent Interface Mode * 0b0..Reserved. * 0b1..MII or RMII mode, as indicated by the RMII_MODE field. */ #define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) #define ENET_RCR_PROM_MASK (0x8U) #define ENET_RCR_PROM_SHIFT (3U) /*! PROM - Promiscuous Mode * 0b0..Disabled. * 0b1..Enabled. */ #define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) #define ENET_RCR_BC_REJ_MASK (0x10U) #define ENET_RCR_BC_REJ_SHIFT (4U) #define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) #define ENET_RCR_FCE_MASK (0x20U) #define ENET_RCR_FCE_SHIFT (5U) #define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) #define ENET_RCR_RGMII_EN_MASK (0x40U) #define ENET_RCR_RGMII_EN_SHIFT (6U) /*! RGMII_EN - RGMII Mode Enable * 0b0..MAC configured for non-RGMII operation * 0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If * ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode. */ #define ENET_RCR_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK) #define ENET_RCR_RMII_MODE_MASK (0x100U) #define ENET_RCR_RMII_MODE_SHIFT (8U) /*! RMII_MODE - RMII Mode Enable * 0b0..MAC configured for MII mode. * 0b1..MAC configured for RMII operation. */ #define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) #define ENET_RCR_RMII_10T_MASK (0x200U) #define ENET_RCR_RMII_10T_SHIFT (9U) /*! RMII_10T * 0b0..100-Mbit/s operation. * 0b1..10-Mbit/s operation. */ #define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) #define ENET_RCR_PADEN_MASK (0x1000U) #define ENET_RCR_PADEN_SHIFT (12U) /*! PADEN - Enable Frame Padding Remove On Receive * 0b0..No padding is removed on receive by the MAC. * 0b1..Padding is removed from received frames. */ #define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) #define ENET_RCR_PAUFWD_MASK (0x2000U) #define ENET_RCR_PAUFWD_SHIFT (13U) /*! PAUFWD - Terminate/Forward Pause Frames * 0b0..Pause frames are terminated and discarded in the MAC. * 0b1..Pause frames are forwarded to the user application. */ #define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) #define ENET_RCR_CRCFWD_MASK (0x4000U) #define ENET_RCR_CRCFWD_SHIFT (14U) /*! CRCFWD - Terminate/Forward Received CRC * 0b0..The CRC field of received frames is transmitted to the user application. * 0b1..The CRC field is stripped from the frame. */ #define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) #define ENET_RCR_CFEN_MASK (0x8000U) #define ENET_RCR_CFEN_SHIFT (15U) /*! CFEN - MAC Control Frame Enable * 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client * interface. 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. */ #define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) #define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) #define ENET_RCR_MAX_FL_SHIFT (16U) #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) #define ENET_RCR_NLC_MASK (0x40000000U) #define ENET_RCR_NLC_SHIFT (30U) /*! NLC - Payload Length Check Disable * 0b0..The payload length check is disabled. * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the * EIR[PLR] field. */ #define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) #define ENET_RCR_GRS_MASK (0x80000000U) #define ENET_RCR_GRS_SHIFT (31U) #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) /*! @} */ /*! @name TCR - Transmit Control Register */ /*! @{ */ #define ENET_TCR_GTS_MASK (0x1U) #define ENET_TCR_GTS_SHIFT (0U) #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) #define ENET_TCR_FDEN_MASK (0x4U) #define ENET_TCR_FDEN_SHIFT (2U) #define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) #define ENET_TCR_TFC_PAUSE_MASK (0x8U) #define ENET_TCR_TFC_PAUSE_SHIFT (3U) /*! TFC_PAUSE - Transmit Frame Control Pause * 0b0..No PAUSE frame transmitted. * 0b1..The MAC stops transmission of data frames after the current transmission is complete. */ #define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) #define ENET_TCR_RFC_PAUSE_MASK (0x10U) #define ENET_TCR_RFC_PAUSE_SHIFT (4U) #define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) #define ENET_TCR_ADDSEL_MASK (0xE0U) #define ENET_TCR_ADDSEL_SHIFT (5U) /*! ADDSEL - Source MAC Address Select On Transmit * 0b000..Node MAC address programmed on PADDR1/2 registers. * 0b100..Reserved. * 0b101..Reserved. * 0b110..Reserved. */ #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) #define ENET_TCR_ADDINS_MASK (0x100U) #define ENET_TCR_ADDINS_SHIFT (8U) /*! ADDINS - Set MAC Address On Transmit * 0b0..The source MAC address is not modified by the MAC. * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. */ #define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) #define ENET_TCR_CRCFWD_MASK (0x200U) #define ENET_TCR_CRCFWD_SHIFT (9U) /*! CRCFWD - Forward Frame From Application With CRC * 0b0..TxBD[TC] controls whether the frame has a CRC from the application. * 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the * application. */ #define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) /*! @} */ /*! @name PALR - Physical Address Lower Register */ /*! @{ */ #define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) #define ENET_PALR_PADDR1_SHIFT (0U) #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) /*! @} */ /*! @name PAUR - Physical Address Upper Register */ /*! @{ */ #define ENET_PAUR_TYPE_MASK (0xFFFFU) #define ENET_PAUR_TYPE_SHIFT (0U) #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) #define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) #define ENET_PAUR_PADDR2_SHIFT (16U) #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) /*! @} */ /*! @name OPD - Opcode/Pause Duration Register */ /*! @{ */ #define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) #define ENET_OPD_PAUSE_DUR_SHIFT (0U) #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) #define ENET_OPD_OPCODE_MASK (0xFFFF0000U) #define ENET_OPD_OPCODE_SHIFT (16U) #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) /*! @} */ /*! @name TXIC - Transmit Interrupt Coalescing Register */ /*! @{ */ #define ENET_TXIC_ICTT_MASK (0xFFFFU) #define ENET_TXIC_ICTT_SHIFT (0U) #define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) #define ENET_TXIC_ICFT_MASK (0xFF00000U) #define ENET_TXIC_ICFT_SHIFT (20U) #define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) #define ENET_TXIC_ICCS_MASK (0x40000000U) #define ENET_TXIC_ICCS_SHIFT (30U) /*! ICCS - Interrupt Coalescing Timer Clock Source Select * 0b0..Use MII/GMII TX clocks. * 0b1..Use ENET system clock. */ #define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) #define ENET_TXIC_ICEN_MASK (0x80000000U) #define ENET_TXIC_ICEN_SHIFT (31U) /*! ICEN - Interrupt Coalescing Enable * 0b0..Disable Interrupt coalescing. * 0b1..Enable Interrupt coalescing. */ #define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) /*! @} */ /* The count of ENET_TXIC */ #define ENET_TXIC_COUNT (3U) /*! @name RXIC - Receive Interrupt Coalescing Register */ /*! @{ */ #define ENET_RXIC_ICTT_MASK (0xFFFFU) #define ENET_RXIC_ICTT_SHIFT (0U) #define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) #define ENET_RXIC_ICFT_MASK (0xFF00000U) #define ENET_RXIC_ICFT_SHIFT (20U) #define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) #define ENET_RXIC_ICCS_MASK (0x40000000U) #define ENET_RXIC_ICCS_SHIFT (30U) /*! ICCS - Interrupt Coalescing Timer Clock Source Select * 0b0..Use MII/GMII TX clocks. * 0b1..Use ENET system clock. */ #define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) #define ENET_RXIC_ICEN_MASK (0x80000000U) #define ENET_RXIC_ICEN_SHIFT (31U) /*! ICEN - Interrupt Coalescing Enable * 0b0..Disable Interrupt coalescing. * 0b1..Enable Interrupt coalescing. */ #define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) /*! @} */ /* The count of ENET_RXIC */ #define ENET_RXIC_COUNT (3U) /*! @name IAUR - Descriptor Individual Upper Address Register */ /*! @{ */ #define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) #define ENET_IAUR_IADDR1_SHIFT (0U) #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) /*! @} */ /*! @name IALR - Descriptor Individual Lower Address Register */ /*! @{ */ #define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) #define ENET_IALR_IADDR2_SHIFT (0U) #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) /*! @} */ /*! @name GAUR - Descriptor Group Upper Address Register */ /*! @{ */ #define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) #define ENET_GAUR_GADDR1_SHIFT (0U) #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) /*! @} */ /*! @name GALR - Descriptor Group Lower Address Register */ /*! @{ */ #define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) #define ENET_GALR_GADDR2_SHIFT (0U) #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) /*! @} */ /*! @name TFWR - Transmit FIFO Watermark Register */ /*! @{ */ #define ENET_TFWR_TFWR_MASK (0x3FU) #define ENET_TFWR_TFWR_SHIFT (0U) /*! TFWR - Transmit FIFO Write * 0b000000..64 bytes written. * 0b000001..64 bytes written. * 0b000010..128 bytes written. * 0b000011..192 bytes written. * 0b111111..4032 bytes written. */ #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) #define ENET_TFWR_STRFWD_MASK (0x100U) #define ENET_TFWR_STRFWD_SHIFT (8U) /*! STRFWD - Store And Forward Enable * 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. * 0b1..Enabled. */ #define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) /*! @} */ /*! @name RDSR1 - Receive Descriptor Ring 1 Start Register */ /*! @{ */ #define ENET_RDSR1_R_DES_START_MASK (0xFFFFFFF8U) #define ENET_RDSR1_R_DES_START_SHIFT (3U) #define ENET_RDSR1_R_DES_START(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK) /*! @} */ /*! @name TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register */ /*! @{ */ #define ENET_TDSR1_X_DES_START_MASK (0xFFFFFFF8U) #define ENET_TDSR1_X_DES_START_SHIFT (3U) #define ENET_TDSR1_X_DES_START(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK) /*! @} */ /*! @name MRBR1 - Maximum Receive Buffer Size Register - Ring 1 */ /*! @{ */ #define ENET_MRBR1_R_BUF_SIZE_MASK (0x7F0U) #define ENET_MRBR1_R_BUF_SIZE_SHIFT (4U) #define ENET_MRBR1_R_BUF_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK) /*! @} */ /*! @name RDSR2 - Receive Descriptor Ring 2 Start Register */ /*! @{ */ #define ENET_RDSR2_R_DES_START_MASK (0xFFFFFFF8U) #define ENET_RDSR2_R_DES_START_SHIFT (3U) #define ENET_RDSR2_R_DES_START(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK) /*! @} */ /*! @name TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register */ /*! @{ */ #define ENET_TDSR2_X_DES_START_MASK (0xFFFFFFF8U) #define ENET_TDSR2_X_DES_START_SHIFT (3U) #define ENET_TDSR2_X_DES_START(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK) /*! @} */ /*! @name MRBR2 - Maximum Receive Buffer Size Register - Ring 2 */ /*! @{ */ #define ENET_MRBR2_R_BUF_SIZE_MASK (0x7F0U) #define ENET_MRBR2_R_BUF_SIZE_SHIFT (4U) #define ENET_MRBR2_R_BUF_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK) /*! @} */ /*! @name RDSR - Receive Descriptor Ring 0 Start Register */ /*! @{ */ #define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) #define ENET_RDSR_R_DES_START_SHIFT (3U) #define ENET_RDSR_R_DES_START(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) /*! @} */ /*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */ /*! @{ */ #define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) #define ENET_TDSR_X_DES_START_SHIFT (3U) #define ENET_TDSR_X_DES_START(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) /*! @} */ /*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */ /*! @{ */ #define ENET_MRBR_R_BUF_SIZE_MASK (0x7F0U) #define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) #define ENET_MRBR_R_BUF_SIZE(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) /*! @} */ /*! @name RSFL - Receive FIFO Section Full Threshold */ /*! @{ */ #define ENET_RSFL_RX_SECTION_FULL_MASK (0x3FFU) #define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) #define ENET_RSFL_RX_SECTION_FULL(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) /*! @} */ /*! @name RSEM - Receive FIFO Section Empty Threshold */ /*! @{ */ #define ENET_RSEM_RX_SECTION_EMPTY_MASK (0x3FFU) #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) #define ENET_RSEM_RX_SECTION_EMPTY(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) #define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) #define ENET_RSEM_STAT_SECTION_EMPTY(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) /*! @} */ /*! @name RAEM - Receive FIFO Almost Empty Threshold */ /*! @{ */ #define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0x3FFU) #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) #define ENET_RAEM_RX_ALMOST_EMPTY(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) /*! @} */ /*! @name RAFL - Receive FIFO Almost Full Threshold */ /*! @{ */ #define ENET_RAFL_RX_ALMOST_FULL_MASK (0x3FFU) #define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) #define ENET_RAFL_RX_ALMOST_FULL(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) /*! @} */ /*! @name TSEM - Transmit FIFO Section Empty Threshold */ /*! @{ */ #define ENET_TSEM_TX_SECTION_EMPTY_MASK (0x3FFU) #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) #define ENET_TSEM_TX_SECTION_EMPTY(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) /*! @} */ /*! @name TAEM - Transmit FIFO Almost Empty Threshold */ /*! @{ */ #define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0x3FFU) #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) #define ENET_TAEM_TX_ALMOST_EMPTY(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) /*! @} */ /*! @name TAFL - Transmit FIFO Almost Full Threshold */ /*! @{ */ #define ENET_TAFL_TX_ALMOST_FULL_MASK (0x3FFU) #define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) #define ENET_TAFL_TX_ALMOST_FULL(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) /*! @} */ /*! @name TIPG - Transmit Inter-Packet Gap */ /*! @{ */ #define ENET_TIPG_IPG_MASK (0x1FU) #define ENET_TIPG_IPG_SHIFT (0U) #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) /*! @} */ /*! @name FTRL - Frame Truncation Length */ /*! @{ */ #define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) #define ENET_FTRL_TRUNC_FL_SHIFT (0U) #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) /*! @} */ /*! @name TACC - Transmit Accelerator Function Configuration */ /*! @{ */ #define ENET_TACC_SHIFT16_MASK (0x1U) #define ENET_TACC_SHIFT16_SHIFT (0U) /*! SHIFT16 - TX FIFO Shift-16 * 0b0..Disabled. * 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the * frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This * function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is * extended to a 16-byte header. */ #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) #define ENET_TACC_IPCHK_MASK (0x8U) #define ENET_TACC_IPCHK_SHIFT (3U) /*! IPCHK * 0b0..Checksum is not inserted. * 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must * be cleared. If a non-IP frame is transmitted the frame is not modified. */ #define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) #define ENET_TACC_PROCHK_MASK (0x10U) #define ENET_TACC_PROCHK_SHIFT (4U) /*! PROCHK * 0b0..Checksum not inserted. * 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the * frame. The checksum field must be cleared. The other frames are not modified. */ #define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) /*! @} */ /*! @name RACC - Receive Accelerator Function Configuration */ /*! @{ */ #define ENET_RACC_PADREM_MASK (0x1U) #define ENET_RACC_PADREM_SHIFT (0U) /*! PADREM - Enable Padding Removal For Short IP Frames * 0b0..Padding not removed. * 0b1..Any bytes following the IP payload section of the frame are removed from the frame. */ #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) #define ENET_RACC_IPDIS_MASK (0x2U) #define ENET_RACC_IPDIS_SHIFT (1U) /*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum * 0b0..Frames with wrong IPv4 header checksum are not discarded. * 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no * header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in * store and forward mode (RSFL cleared). */ #define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) #define ENET_RACC_PRODIS_MASK (0x4U) #define ENET_RACC_PRODIS_SHIFT (2U) /*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum * 0b0..Frames with wrong checksum are not discarded. * 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame * is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL * cleared). */ #define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) #define ENET_RACC_LINEDIS_MASK (0x40U) #define ENET_RACC_LINEDIS_SHIFT (6U) /*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors * 0b0..Frames with errors are not discarded. * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user * application interface. */ #define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) #define ENET_RACC_SHIFT16_MASK (0x80U) #define ENET_RACC_SHIFT16_SHIFT (7U) /*! SHIFT16 - RX FIFO Shift-16 * 0b0..Disabled. * 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. */ #define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) /*! @} */ /*! @name RCMR - Receive Classification Match Register for Class n */ /*! @{ */ #define ENET_RCMR_CMP0_MASK (0x7U) #define ENET_RCMR_CMP0_SHIFT (0U) #define ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK) #define ENET_RCMR_CMP1_MASK (0x70U) #define ENET_RCMR_CMP1_SHIFT (4U) #define ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK) #define ENET_RCMR_CMP2_MASK (0x700U) #define ENET_RCMR_CMP2_SHIFT (8U) #define ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK) #define ENET_RCMR_CMP3_MASK (0x7000U) #define ENET_RCMR_CMP3_SHIFT (12U) #define ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK) #define ENET_RCMR_MATCHEN_MASK (0x10000U) #define ENET_RCMR_MATCHEN_SHIFT (16U) /*! MATCHEN - Match Enable * 0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert. * 0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received. */ #define ENET_RCMR_MATCHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK) /*! @} */ /* The count of ENET_RCMR */ #define ENET_RCMR_COUNT (2U) /*! @name DMACFG - DMA Class Based Configuration */ /*! @{ */ #define ENET_DMACFG_IDLE_SLOPE_MASK (0xFFFFU) #define ENET_DMACFG_IDLE_SLOPE_SHIFT (0U) #define ENET_DMACFG_IDLE_SLOPE(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK) #define ENET_DMACFG_DMA_CLASS_EN_MASK (0x10000U) #define ENET_DMACFG_DMA_CLASS_EN_SHIFT (16U) /*! DMA_CLASS_EN - DMA class enable * 0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also * requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2 * queues are disabled then their frames will be placed in queue 0. * 0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic. */ #define ENET_DMACFG_DMA_CLASS_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK) #define ENET_DMACFG_CALC_NOIPG_MASK (0x20000U) #define ENET_DMACFG_CALC_NOIPG_SHIFT (17U) /*! CALC_NOIPG - Calculate no IPG * 0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred * for a frame when doing bandwidth calculations. This is the default. * 0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping, * when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every * frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames * will become more bandwidth than large frames due to the relation of data to IPG overhead). */ #define ENET_DMACFG_CALC_NOIPG(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK) /*! @} */ /* The count of ENET_DMACFG */ #define ENET_DMACFG_COUNT (2U) /*! @name RDAR1 - Receive Descriptor Active Register - Ring 1 */ /*! @{ */ #define ENET_RDAR1_RDAR_MASK (0x1000000U) #define ENET_RDAR1_RDAR_SHIFT (24U) #define ENET_RDAR1_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK) /*! @} */ /*! @name TDAR1 - Transmit Descriptor Active Register - Ring 1 */ /*! @{ */ #define ENET_TDAR1_TDAR_MASK (0x1000000U) #define ENET_TDAR1_TDAR_SHIFT (24U) #define ENET_TDAR1_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK) /*! @} */ /*! @name RDAR2 - Receive Descriptor Active Register - Ring 2 */ /*! @{ */ #define ENET_RDAR2_RDAR_MASK (0x1000000U) #define ENET_RDAR2_RDAR_SHIFT (24U) #define ENET_RDAR2_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK) /*! @} */ /*! @name TDAR2 - Transmit Descriptor Active Register - Ring 2 */ /*! @{ */ #define ENET_TDAR2_TDAR_MASK (0x1000000U) #define ENET_TDAR2_TDAR_SHIFT (24U) #define ENET_TDAR2_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK) /*! @} */ /*! @name QOS - QOS Scheme */ /*! @{ */ #define ENET_QOS_TX_SCHEME_MASK (0x7U) #define ENET_QOS_TX_SCHEME_SHIFT (0U) /*! TX_SCHEME - TX scheme configuration * 0b000..Credit-based scheme * 0b001..Round-robin scheme */ #define ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK) #define ENET_QOS_RX_FLUSH0_MASK (0x8U) #define ENET_QOS_RX_FLUSH0_SHIFT (3U) /*! RX_FLUSH0 - RX Flush Ring 0 * 0b0..Disable * 0b1..Enable */ #define ENET_QOS_RX_FLUSH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK) #define ENET_QOS_RX_FLUSH1_MASK (0x10U) #define ENET_QOS_RX_FLUSH1_SHIFT (4U) /*! RX_FLUSH1 - RX Flush Ring 1 * 0b0..Disable * 0b1..Enable */ #define ENET_QOS_RX_FLUSH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK) #define ENET_QOS_RX_FLUSH2_MASK (0x20U) #define ENET_QOS_RX_FLUSH2_SHIFT (5U) /*! RX_FLUSH2 - RX Flush Ring 2 * 0b0..Disable * 0b1..Enable */ #define ENET_QOS_RX_FLUSH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK) /*! @} */ /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ /*! @{ */ #define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) #define ENET_RMON_T_PACKETS_TXPKTS(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ /*! @{ */ #define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) #define ENET_RMON_T_BC_PKT_TXPKTS(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ /*! @{ */ #define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) #define ENET_RMON_T_MC_PKT_TXPKTS(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ /*! @{ */ #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ /*! @{ */ #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ /*! @{ */ #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) #define ENET_RMON_T_OVERSIZE_TXPKTS(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ /*! @{ */ #define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) #define ENET_RMON_T_FRAG_TXPKTS(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ /*! @{ */ #define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) #define ENET_RMON_T_JAB_TXPKTS(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_COL - Tx Collision Count Statistic Register */ /*! @{ */ #define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) #define ENET_RMON_T_COL_TXPKTS(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P64_TXPKTS(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P65TO127_TXPKTS(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P128TO255_TXPKTS(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P256TO511_TXPKTS(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P512TO1023_TXPKTS(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P1024TO2047_TXPKTS(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ /*! @{ */ #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P_GTE2048_TXPKTS(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ /*! @{ */ #define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) #define ENET_RMON_T_OCTETS_TXOCTS(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) /*! @} */ /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ /*! @{ */ #define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) #define ENET_IEEE_T_FRAME_OK_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) /*! @} */ /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ /*! @{ */ #define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) #define ENET_IEEE_T_1COL_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) /*! @} */ /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ /*! @{ */ #define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) #define ENET_IEEE_T_MCOL_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) /*! @} */ /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ /*! @{ */ #define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) #define ENET_IEEE_T_DEF_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) /*! @} */ /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ /*! @{ */ #define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) #define ENET_IEEE_T_LCOL_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) /*! @} */ /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ /*! @{ */ #define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) #define ENET_IEEE_T_EXCOL_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) /*! @} */ /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ /*! @{ */ #define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) #define ENET_IEEE_T_MACERR_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) /*! @} */ /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ /*! @{ */ #define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) #define ENET_IEEE_T_CSERR_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) /*! @} */ /*! @name IEEE_T_SQE - Reserved Statistic Register */ /*! @{ */ #define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) #define ENET_IEEE_T_SQE_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) /*! @} */ /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ /*! @{ */ #define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) #define ENET_IEEE_T_FDXFC_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) /*! @} */ /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ /*! @{ */ #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) #define ENET_IEEE_T_OCTETS_OK_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) /*! @} */ /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ /*! @{ */ #define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) #define ENET_RMON_R_PACKETS_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) /*! @} */ /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ /*! @{ */ #define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) #define ENET_RMON_R_BC_PKT_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) /*! @} */ /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ /*! @{ */ #define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) #define ENET_RMON_R_MC_PKT_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) /*! @} */ /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ /*! @{ */ #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) #define ENET_RMON_R_CRC_ALIGN_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) /*! @} */ /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ /*! @{ */ #define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) #define ENET_RMON_R_UNDERSIZE_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) /*! @} */ /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ /*! @{ */ #define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) #define ENET_RMON_R_OVERSIZE_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) /*! @} */ /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ /*! @{ */ #define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) #define ENET_RMON_R_FRAG_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) /*! @} */ /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ /*! @{ */ #define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_JAB_COUNT_SHIFT (0U) #define ENET_RMON_R_JAB_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) /*! @} */ /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P64_COUNT_SHIFT (0U) #define ENET_RMON_R_P64_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) /*! @} */ /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) #define ENET_RMON_R_P65TO127_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) /*! @} */ /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) #define ENET_RMON_R_P128TO255_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) /*! @} */ /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) #define ENET_RMON_R_P256TO511_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) /*! @} */ /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) #define ENET_RMON_R_P512TO1023_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) /*! @} */ /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) #define ENET_RMON_R_P1024TO2047_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) /*! @} */ /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ /*! @{ */ #define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) #define ENET_RMON_R_P_GTE2048_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) /*! @} */ /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ /*! @{ */ #define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) #define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) #define ENET_RMON_R_OCTETS_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) /*! @} */ /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ /*! @{ */ #define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) #define ENET_IEEE_R_DROP_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) /*! @} */ /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ /*! @{ */ #define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) #define ENET_IEEE_R_FRAME_OK_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) /*! @} */ /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ /*! @{ */ #define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) #define ENET_IEEE_R_CRC_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) /*! @} */ /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ /*! @{ */ #define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) #define ENET_IEEE_R_ALIGN_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) /*! @} */ /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ /*! @{ */ #define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) #define ENET_IEEE_R_MACERR_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) /*! @} */ /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ /*! @{ */ #define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) #define ENET_IEEE_R_FDXFC_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) /*! @} */ /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ /*! @{ */ #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) #define ENET_IEEE_R_OCTETS_OK_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) /*! @} */ /*! @name ATCR - Adjustable Timer Control Register */ /*! @{ */ #define ENET_ATCR_EN_MASK (0x1U) #define ENET_ATCR_EN_SHIFT (0U) /*! EN - Enable Timer * 0b0..The timer stops at the current value. * 0b1..The timer starts incrementing. */ #define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) #define ENET_ATCR_OFFEN_MASK (0x4U) #define ENET_ATCR_OFFEN_SHIFT (2U) /*! OFFEN - Enable One-Shot Offset Event * 0b0..Disable. * 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared * when the offset event is reached, so no further event occurs until the field is set again. The timer * offset value must be set before setting this field. */ #define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) #define ENET_ATCR_OFFRST_MASK (0x8U) #define ENET_ATCR_OFFRST_SHIFT (3U) /*! OFFRST - Reset Timer On Offset Event * 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. * 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a * timer interrupt. */ #define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) #define ENET_ATCR_PEREN_MASK (0x10U) #define ENET_ATCR_PEREN_SHIFT (4U) /*! PEREN - Enable Periodical Event * 0b0..Disable. * 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when * the timer wraps around according to the periodic setting ATPER. The timer period value must be set before * setting this bit. Not all devices contain the event signal output. See the chip configuration details. */ #define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) #define ENET_ATCR_PINPER_MASK (0x80U) #define ENET_ATCR_PINPER_SHIFT (7U) /*! PINPER * 0b0..Disable. * 0b1..Enable. */ #define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) #define ENET_ATCR_RESTART_MASK (0x200U) #define ENET_ATCR_RESTART_SHIFT (9U) #define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) #define ENET_ATCR_CAPTURE_MASK (0x800U) #define ENET_ATCR_CAPTURE_SHIFT (11U) /*! CAPTURE - Capture Timer Value * 0b0..No effect. * 0b1..The current time is captured and can be read from the ATVR register. */ #define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) #define ENET_ATCR_SLAVE_MASK (0x2000U) #define ENET_ATCR_SLAVE_SHIFT (13U) /*! SLAVE - Enable Timer Slave Mode * 0b0..The timer is active and all configuration fields in this register are relevant. * 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except * CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. */ #define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) /*! @} */ /*! @name ATVR - Timer Value Register */ /*! @{ */ #define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) #define ENET_ATVR_ATIME_SHIFT (0U) #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) /*! @} */ /*! @name ATOFF - Timer Offset Register */ /*! @{ */ #define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) #define ENET_ATOFF_OFFSET_SHIFT (0U) #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) /*! @} */ /*! @name ATPER - Timer Period Register */ /*! @{ */ #define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) #define ENET_ATPER_PERIOD_SHIFT (0U) #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) /*! @} */ /*! @name ATCOR - Timer Correction Register */ /*! @{ */ #define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) #define ENET_ATCOR_COR_SHIFT (0U) #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) /*! @} */ /*! @name ATINC - Time-Stamping Clock Period Register */ /*! @{ */ #define ENET_ATINC_INC_MASK (0x7FU) #define ENET_ATINC_INC_SHIFT (0U) #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) #define ENET_ATINC_INC_CORR_MASK (0x7F00U) #define ENET_ATINC_INC_CORR_SHIFT (8U) #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) /*! @} */ /*! @name ATSTMP - Timestamp of Last Transmitted Frame */ /*! @{ */ #define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) #define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) #define ENET_ATSTMP_TIMESTAMP(x) \ (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) /*! @} */ /*! @name TGSR - Timer Global Status Register */ /*! @{ */ #define ENET_TGSR_TF0_MASK (0x1U) #define ENET_TGSR_TF0_SHIFT (0U) /*! TF0 - Copy Of Timer Flag For Channel 0 * 0b0..Timer Flag for Channel 0 is clear * 0b1..Timer Flag for Channel 0 is set */ #define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) #define ENET_TGSR_TF1_MASK (0x2U) #define ENET_TGSR_TF1_SHIFT (1U) /*! TF1 - Copy Of Timer Flag For Channel 1 * 0b0..Timer Flag for Channel 1 is clear * 0b1..Timer Flag for Channel 1 is set */ #define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) #define ENET_TGSR_TF2_MASK (0x4U) #define ENET_TGSR_TF2_SHIFT (2U) /*! TF2 - Copy Of Timer Flag For Channel 2 * 0b0..Timer Flag for Channel 2 is clear * 0b1..Timer Flag for Channel 2 is set */ #define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) #define ENET_TGSR_TF3_MASK (0x8U) #define ENET_TGSR_TF3_SHIFT (3U) /*! TF3 - Copy Of Timer Flag For Channel 3 * 0b0..Timer Flag for Channel 3 is clear * 0b1..Timer Flag for Channel 3 is set */ #define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) /*! @} */ /*! @name TCSR - Timer Control Status Register */ /*! @{ */ #define ENET_TCSR_TDRE_MASK (0x1U) #define ENET_TCSR_TDRE_SHIFT (0U) /*! TDRE - Timer DMA Request Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) #define ENET_TCSR_TMODE_MASK (0x3CU) #define ENET_TCSR_TMODE_SHIFT (2U) /*! TMODE - Timer Mode * 0b0000..Timer Channel is disabled. * 0b0001..Timer Channel is configured for Input Capture on rising edge. * 0b0010..Timer Channel is configured for Input Capture on falling edge. * 0b0011..Timer Channel is configured for Input Capture on both edges. * 0b0100..Timer Channel is configured for Output Compare - software only. * 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. * 0b0110..Timer Channel is configured for Output Compare - clear output on compare. * 0b0111..Timer Channel is configured for Output Compare - set output on compare. * 0b1000..Reserved * 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. * 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. * 0b110x..Reserved * 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. * 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle. */ #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) #define ENET_TCSR_TIE_MASK (0x40U) #define ENET_TCSR_TIE_SHIFT (6U) /*! TIE - Timer Interrupt Enable * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) #define ENET_TCSR_TF_MASK (0x80U) #define ENET_TCSR_TF_SHIFT (7U) /*! TF - Timer Flag * 0b0..Input Capture or Output Compare has not occurred. * 0b1..Input Capture or Output Compare has occurred. */ #define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) /*! @} */ /* The count of ENET_TCSR */ #define ENET_TCSR_COUNT (4U) /*! @name TCCR - Timer Compare Capture Register */ /*! @{ */ #define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) #define ENET_TCCR_TCC_SHIFT (0U) #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) /*! @} */ /* The count of ENET_TCCR */ #define ENET_TCCR_COUNT (4U) /*! * @} */ /* end of group ENET_Register_Masks */ /* ENET - Peripheral instance base addresses */ /** Peripheral ENET base address */ #define ENET_BASE (0x30BE0000u) /** Peripheral ENET base pointer */ #define ENET ((ENET_Type *)ENET_BASE) /** Array initializer of ENET peripheral base addresses */ #define ENET_BASE_ADDRS \ { \ ENET_BASE \ } /** Array initializer of ENET peripheral base pointers */ #define ENET_BASE_PTRS \ { \ ENET \ } /** Interrupt vectors for the ENET peripheral type */ #define ENET_Transmit_IRQS \ { \ ENET_IRQn \ } #define ENET_Receive_IRQS \ { \ ENET_IRQn \ } #define ENET_Error_IRQS \ { \ ENET_IRQn \ } #define ENET_1588_Timer_IRQS \ { \ ENET_IRQn \ } /* ENET Buffer Descriptor and Buffer Address Alignment. */ #define ENET_BUFF_ALIGNMENT (64U) /*! * @} */ /* end of group ENET_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FlexSPI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FlexSPI_Peripheral_Access_Layer FlexSPI Peripheral Access Layer * @{ */ /** FlexSPI - Register Layout Typedef */ typedef struct { __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ __IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */ __IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */ __IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */ __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */ __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ __IO uint32_t AHBRXBUFCR0[8]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[32]; __IO uint32_t FLSHCR0[4]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ __IO uint32_t FLSHCR1[4]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ __IO uint32_t FLSHCR2[4]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ uint8_t RESERVED_2[8]; __IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */ __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ uint8_t RESERVED_3[8]; __IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */ __IO uint32_t DLPR; /**< Data Learn Pattern Register, offset: 0xB4 */ __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ __IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_4[24]; __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ __I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */ __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */ __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ __I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */ uint8_t RESERVED_5[8]; __I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */ __O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */ __IO uint32_t LUT[128]; /**< LUT 0..LUT 127, array offset: 0x200, array step: 0x4 */ } FlexSPI_Type; /* ---------------------------------------------------------------------------- -- FlexSPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FlexSPI_Register_Masks FlexSPI Register Masks * @{ */ /*! @name MCR0 - Module Control Register 0 */ /*! @{ */ #define FlexSPI_MCR0_SWRESET_MASK (0x1U) #define FlexSPI_MCR0_SWRESET_SHIFT (0U) #define FlexSPI_MCR0_SWRESET(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_SWRESET_SHIFT)) & FlexSPI_MCR0_SWRESET_MASK) #define FlexSPI_MCR0_MDIS_MASK (0x2U) #define FlexSPI_MCR0_MDIS_SHIFT (1U) #define FlexSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_MDIS_SHIFT)) & FlexSPI_MCR0_MDIS_MASK) #define FlexSPI_MCR0_RXCLKSRC_MASK (0x30U) #define FlexSPI_MCR0_RXCLKSRC_SHIFT (4U) /*! RXCLKSRC - Sample Clock source selection for Flash Reading * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally. * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. * 0b10..Reserved * 0b11..Flash provided Read strobe and input from DQS pad */ #define FlexSPI_MCR0_RXCLKSRC(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_RXCLKSRC_SHIFT)) & FlexSPI_MCR0_RXCLKSRC_MASK) #define FlexSPI_MCR0_ARDFEN_MASK (0x40U) #define FlexSPI_MCR0_ARDFEN_SHIFT (6U) /*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO. * 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error * response. 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return * data zero but no bus error response. */ #define FlexSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_ARDFEN_SHIFT)) & FlexSPI_MCR0_ARDFEN_MASK) #define FlexSPI_MCR0_ATDFEN_MASK (0x80U) #define FlexSPI_MCR0_ATDFEN_SHIFT (7U) /*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO. * 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error * response. 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be * ignored but no bus error response. */ #define FlexSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_ATDFEN_SHIFT)) & FlexSPI_MCR0_ATDFEN_MASK) #define FlexSPI_MCR0_SERCLKDIV_MASK (0x700U) #define FlexSPI_MCR0_SERCLKDIV_SHIFT (8U) /*! SERCLKDIV - The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on * clocking. 0b000..Divided by 1 0b001..Divided by 2 0b010..Divided by 3 0b011..Divided by 4 0b100..Divided by 5 * 0b101..Divided by 6 * 0b110..Divided by 7 * 0b111..Divided by 8 */ #define FlexSPI_MCR0_SERCLKDIV(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_SERCLKDIV_SHIFT)) & FlexSPI_MCR0_SERCLKDIV_MASK) #define FlexSPI_MCR0_HSEN_MASK (0x800U) #define FlexSPI_MCR0_HSEN_SHIFT (11U) /*! HSEN - Half Speed Serial Flash access Enable. * 0b0..Disable divide by 2 of serial flash clock for half speed commands. * 0b1..Enable divide by 2 of serial flash clock for half speed commands. */ #define FlexSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_HSEN_SHIFT)) & FlexSPI_MCR0_HSEN_MASK) #define FlexSPI_MCR0_DOZEEN_MASK (0x1000U) #define FlexSPI_MCR0_DOZEEN_SHIFT (12U) /*! DOZEEN - Doze mode enable bit * 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request * from system. 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode * request from system. */ #define FlexSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_DOZEEN_SHIFT)) & FlexSPI_MCR0_DOZEEN_MASK) #define FlexSPI_MCR0_COMBINATIONEN_MASK (0x2000U) #define FlexSPI_MCR0_COMBINATIONEN_SHIFT (13U) /*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and * B_DATA[3:0]). 0b0..Disable. 0b1..Enable. */ #define FlexSPI_MCR0_COMBINATIONEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_COMBINATIONEN_SHIFT)) & FlexSPI_MCR0_COMBINATIONEN_MASK) #define FlexSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) #define FlexSPI_MCR0_SCKFREERUNEN_SHIFT (14U) /*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications, * external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is * enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2). * 0b0..Disable. * 0b1..Enable. */ #define FlexSPI_MCR0_SCKFREERUNEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_SCKFREERUNEN_SHIFT)) & FlexSPI_MCR0_SCKFREERUNEN_MASK) #define FlexSPI_MCR0_LEARNEN_MASK (0x8000U) #define FlexSPI_MCR0_LEARNEN_SHIFT (15U) /*! LEARNEN - This bit is used to enable/disable data learning feature. When data learning is * disabled, the sampling clock phase 0 is always used for RX data sampling even if LEARN instruction * is correctly executed. * 0b0..Disable. * 0b1..Enable. */ #define FlexSPI_MCR0_LEARNEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_LEARNEN_SHIFT)) & FlexSPI_MCR0_LEARNEN_MASK) #define FlexSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) #define FlexSPI_MCR0_IPGRANTWAIT_SHIFT (16U) #define FlexSPI_MCR0_IPGRANTWAIT(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_IPGRANTWAIT_SHIFT)) & FlexSPI_MCR0_IPGRANTWAIT_MASK) #define FlexSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) #define FlexSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) #define FlexSPI_MCR0_AHBGRANTWAIT(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FlexSPI_MCR0_AHBGRANTWAIT_MASK) /*! @} */ /*! @name MCR1 - Module Control Register 1 */ /*! @{ */ #define FlexSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) #define FlexSPI_MCR1_AHBBUSWAIT_SHIFT (0U) #define FlexSPI_MCR1_AHBBUSWAIT(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR1_AHBBUSWAIT_SHIFT)) & FlexSPI_MCR1_AHBBUSWAIT_MASK) #define FlexSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) #define FlexSPI_MCR1_SEQWAIT_SHIFT (16U) #define FlexSPI_MCR1_SEQWAIT(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR1_SEQWAIT_SHIFT)) & FlexSPI_MCR1_SEQWAIT_MASK) /*! @} */ /*! @name MCR2 - Module Control Register 2 */ /*! @{ */ #define FlexSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) #define FlexSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) /*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned * automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or * AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP * mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. * 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. * 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. */ #define FlexSPI_MCR2_CLRAHBBUFOPT(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FlexSPI_MCR2_CLRAHBBUFOPT_MASK) #define FlexSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) #define FlexSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) #define FlexSPI_MCR2_CLRLEARNPHASE(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FlexSPI_MCR2_CLRLEARNPHASE_MASK) #define FlexSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) #define FlexSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) /*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2. * 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash * A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, * FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be * ignored. * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. * FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. */ #define FlexSPI_MCR2_SAMEDEVICEEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FlexSPI_MCR2_SAMEDEVICEEN_MASK) #define FlexSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) #define FlexSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) /*! SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to * A_SCLK). In this case, port B flash access is not available. After changing the value of this * field, MCR0[SWRESET] should be set. * 0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is * not available. 0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available. */ #define FlexSPI_MCR2_SCKBDIFFOPT(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FlexSPI_MCR2_SCKBDIFFOPT_MASK) #define FlexSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) #define FlexSPI_MCR2_RESUMEWAIT_SHIFT (24U) #define FlexSPI_MCR2_RESUMEWAIT(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_RESUMEWAIT_SHIFT)) & FlexSPI_MCR2_RESUMEWAIT_MASK) /*! @} */ /*! @name AHBCR - AHB Bus Control Register */ /*! @{ */ #define FlexSPI_AHBCR_APAREN_MASK (0x1U) #define FlexSPI_AHBCR_APAREN_SHIFT (0U) /*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) . * 0b0..Flash will be accessed in Individual mode. * 0b1..Flash will be accessed in Parallel mode. */ #define FlexSPI_AHBCR_APAREN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_APAREN_SHIFT)) & FlexSPI_AHBCR_APAREN_MASK) #define FlexSPI_AHBCR_CACHABLEEN_MASK (0x8U) #define FlexSPI_AHBCR_CACHABLEEN_SHIFT (3U) /*! CACHABLEEN - Enable AHB bus cachable read access support. * 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. * 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. */ #define FlexSPI_AHBCR_CACHABLEEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_CACHABLEEN_SHIFT)) & FlexSPI_AHBCR_CACHABLEEN_MASK) #define FlexSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) #define FlexSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) /*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat * of AHB write access, refer for more details about AHB bufferable write. * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus * ready after all data is transmitted to External device and AHB command finished. * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is * granted by arbitrator and will not wait for AHB command finished. */ #define FlexSPI_AHBCR_BUFFERABLEEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FlexSPI_AHBCR_BUFFERABLEEN_MASK) #define FlexSPI_AHBCR_PREFETCHEN_MASK (0x20U) #define FlexSPI_AHBCR_PREFETCHEN_SHIFT (5U) #define FlexSPI_AHBCR_PREFETCHEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_PREFETCHEN_SHIFT)) & FlexSPI_AHBCR_PREFETCHEN_MASK) #define FlexSPI_AHBCR_READADDROPT_MASK (0x40U) #define FlexSPI_AHBCR_READADDROPT_SHIFT (6U) /*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment * limitation. 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode * or flash is wordaddressable. 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch * more data than AHB burst required to meet the alignment requirement. */ #define FlexSPI_AHBCR_READADDROPT(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_READADDROPT_SHIFT)) & FlexSPI_AHBCR_READADDROPT_MASK) /*! @} */ /*! @name INTEN - Interrupt Enable Register */ /*! @{ */ #define FlexSPI_INTEN_IPCMDDONEEN_MASK (0x1U) #define FlexSPI_INTEN_IPCMDDONEEN_SHIFT (0U) #define FlexSPI_INTEN_IPCMDDONEEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPCMDDONEEN_SHIFT)) & FlexSPI_INTEN_IPCMDDONEEN_MASK) #define FlexSPI_INTEN_IPCMDGEEN_MASK (0x2U) #define FlexSPI_INTEN_IPCMDGEEN_SHIFT (1U) #define FlexSPI_INTEN_IPCMDGEEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPCMDGEEN_SHIFT)) & FlexSPI_INTEN_IPCMDGEEN_MASK) #define FlexSPI_INTEN_AHBCMDGEEN_MASK (0x4U) #define FlexSPI_INTEN_AHBCMDGEEN_SHIFT (2U) #define FlexSPI_INTEN_AHBCMDGEEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_AHBCMDGEEN_SHIFT)) & FlexSPI_INTEN_AHBCMDGEEN_MASK) #define FlexSPI_INTEN_IPCMDERREN_MASK (0x8U) #define FlexSPI_INTEN_IPCMDERREN_SHIFT (3U) #define FlexSPI_INTEN_IPCMDERREN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPCMDERREN_SHIFT)) & FlexSPI_INTEN_IPCMDERREN_MASK) #define FlexSPI_INTEN_AHBCMDERREN_MASK (0x10U) #define FlexSPI_INTEN_AHBCMDERREN_SHIFT (4U) #define FlexSPI_INTEN_AHBCMDERREN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_AHBCMDERREN_SHIFT)) & FlexSPI_INTEN_AHBCMDERREN_MASK) #define FlexSPI_INTEN_IPRXWAEN_MASK (0x20U) #define FlexSPI_INTEN_IPRXWAEN_SHIFT (5U) #define FlexSPI_INTEN_IPRXWAEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPRXWAEN_SHIFT)) & FlexSPI_INTEN_IPRXWAEN_MASK) #define FlexSPI_INTEN_IPTXWEEN_MASK (0x40U) #define FlexSPI_INTEN_IPTXWEEN_SHIFT (6U) #define FlexSPI_INTEN_IPTXWEEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPTXWEEN_SHIFT)) & FlexSPI_INTEN_IPTXWEEN_MASK) #define FlexSPI_INTEN_DATALEARNFAILEN_MASK (0x80U) #define FlexSPI_INTEN_DATALEARNFAILEN_SHIFT (7U) #define FlexSPI_INTEN_DATALEARNFAILEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FlexSPI_INTEN_DATALEARNFAILEN_MASK) #define FlexSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) #define FlexSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) #define FlexSPI_INTEN_SCKSTOPBYRDEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FlexSPI_INTEN_SCKSTOPBYRDEN_MASK) #define FlexSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) #define FlexSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) #define FlexSPI_INTEN_SCKSTOPBYWREN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FlexSPI_INTEN_SCKSTOPBYWREN_MASK) #define FlexSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U) #define FlexSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U) #define FlexSPI_INTEN_AHBBUSTIMEOUTEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FlexSPI_INTEN_AHBBUSTIMEOUTEN_MASK) #define FlexSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) #define FlexSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) #define FlexSPI_INTEN_SEQTIMEOUTEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FlexSPI_INTEN_SEQTIMEOUTEN_MASK) /*! @} */ /*! @name INTR - Interrupt Register */ /*! @{ */ #define FlexSPI_INTR_IPCMDDONE_MASK (0x1U) #define FlexSPI_INTR_IPCMDDONE_SHIFT (0U) #define FlexSPI_INTR_IPCMDDONE(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPCMDDONE_SHIFT)) & FlexSPI_INTR_IPCMDDONE_MASK) #define FlexSPI_INTR_IPCMDGE_MASK (0x2U) #define FlexSPI_INTR_IPCMDGE_SHIFT (1U) #define FlexSPI_INTR_IPCMDGE(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPCMDGE_SHIFT)) & FlexSPI_INTR_IPCMDGE_MASK) #define FlexSPI_INTR_AHBCMDGE_MASK (0x4U) #define FlexSPI_INTR_AHBCMDGE_SHIFT (2U) #define FlexSPI_INTR_AHBCMDGE(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_AHBCMDGE_SHIFT)) & FlexSPI_INTR_AHBCMDGE_MASK) #define FlexSPI_INTR_IPCMDERR_MASK (0x8U) #define FlexSPI_INTR_IPCMDERR_SHIFT (3U) #define FlexSPI_INTR_IPCMDERR(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPCMDERR_SHIFT)) & FlexSPI_INTR_IPCMDERR_MASK) #define FlexSPI_INTR_AHBCMDERR_MASK (0x10U) #define FlexSPI_INTR_AHBCMDERR_SHIFT (4U) #define FlexSPI_INTR_AHBCMDERR(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_AHBCMDERR_SHIFT)) & FlexSPI_INTR_AHBCMDERR_MASK) #define FlexSPI_INTR_IPRXWA_MASK (0x20U) #define FlexSPI_INTR_IPRXWA_SHIFT (5U) #define FlexSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPRXWA_SHIFT)) & FlexSPI_INTR_IPRXWA_MASK) #define FlexSPI_INTR_IPTXWE_MASK (0x40U) #define FlexSPI_INTR_IPTXWE_SHIFT (6U) #define FlexSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPTXWE_SHIFT)) & FlexSPI_INTR_IPTXWE_MASK) #define FlexSPI_INTR_DATALEARNFAIL_MASK (0x80U) #define FlexSPI_INTR_DATALEARNFAIL_SHIFT (7U) #define FlexSPI_INTR_DATALEARNFAIL(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_DATALEARNFAIL_SHIFT)) & FlexSPI_INTR_DATALEARNFAIL_MASK) #define FlexSPI_INTR_SCKSTOPBYRD_MASK (0x100U) #define FlexSPI_INTR_SCKSTOPBYRD_SHIFT (8U) #define FlexSPI_INTR_SCKSTOPBYRD(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_SCKSTOPBYRD_SHIFT)) & FlexSPI_INTR_SCKSTOPBYRD_MASK) #define FlexSPI_INTR_SCKSTOPBYWR_MASK (0x200U) #define FlexSPI_INTR_SCKSTOPBYWR_SHIFT (9U) #define FlexSPI_INTR_SCKSTOPBYWR(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_SCKSTOPBYWR_SHIFT)) & FlexSPI_INTR_SCKSTOPBYWR_MASK) #define FlexSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U) #define FlexSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U) #define FlexSPI_INTR_AHBBUSTIMEOUT(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FlexSPI_INTR_AHBBUSTIMEOUT_MASK) #define FlexSPI_INTR_SEQTIMEOUT_MASK (0x800U) #define FlexSPI_INTR_SEQTIMEOUT_SHIFT (11U) #define FlexSPI_INTR_SEQTIMEOUT(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_SEQTIMEOUT_SHIFT)) & FlexSPI_INTR_SEQTIMEOUT_MASK) /*! @} */ /*! @name LUTKEY - LUT Key Register */ /*! @{ */ #define FlexSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) #define FlexSPI_LUTKEY_KEY_SHIFT (0U) #define FlexSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUTKEY_KEY_SHIFT)) & FlexSPI_LUTKEY_KEY_MASK) /*! @} */ /*! @name LUTCR - LUT Control Register */ /*! @{ */ #define FlexSPI_LUTCR_LOCK_MASK (0x1U) #define FlexSPI_LUTCR_LOCK_SHIFT (0U) #define FlexSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUTCR_LOCK_SHIFT)) & FlexSPI_LUTCR_LOCK_MASK) #define FlexSPI_LUTCR_UNLOCK_MASK (0x2U) #define FlexSPI_LUTCR_UNLOCK_SHIFT (1U) #define FlexSPI_LUTCR_UNLOCK(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUTCR_UNLOCK_SHIFT)) & FlexSPI_LUTCR_UNLOCK_MASK) /*! @} */ /*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */ /*! @{ */ #define FlexSPI_AHBRXBUFCR0_BUFSZ_MASK (0x1FFU) #define FlexSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) #define FlexSPI_AHBRXBUFCR0_BUFSZ(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FlexSPI_AHBRXBUFCR0_BUFSZ_MASK) #define FlexSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) #define FlexSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) #define FlexSPI_AHBRXBUFCR0_MSTRID(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FlexSPI_AHBRXBUFCR0_MSTRID_MASK) #define FlexSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U) #define FlexSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) #define FlexSPI_AHBRXBUFCR0_PRIORITY(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FlexSPI_AHBRXBUFCR0_PRIORITY_MASK) #define FlexSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) #define FlexSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) #define FlexSPI_AHBRXBUFCR0_PREFETCHEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FlexSPI_AHBRXBUFCR0_PREFETCHEN_MASK) /*! @} */ /* The count of FlexSPI_AHBRXBUFCR0 */ #define FlexSPI_AHBRXBUFCR0_COUNT (8U) /*! @name FLSHCR0 - Flash Control Register 0 */ /*! @{ */ #define FlexSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) #define FlexSPI_FLSHCR0_FLSHSZ_SHIFT (0U) #define FlexSPI_FLSHCR0_FLSHSZ(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR0_FLSHSZ_SHIFT)) & FlexSPI_FLSHCR0_FLSHSZ_MASK) /*! @} */ /* The count of FlexSPI_FLSHCR0 */ #define FlexSPI_FLSHCR0_COUNT (4U) /*! @name FLSHCR1 - Flash Control Register 1 */ /*! @{ */ #define FlexSPI_FLSHCR1_TCSS_MASK (0x1FU) #define FlexSPI_FLSHCR1_TCSS_SHIFT (0U) #define FlexSPI_FLSHCR1_TCSS(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_TCSS_SHIFT)) & FlexSPI_FLSHCR1_TCSS_MASK) #define FlexSPI_FLSHCR1_TCSH_MASK (0x3E0U) #define FlexSPI_FLSHCR1_TCSH_SHIFT (5U) #define FlexSPI_FLSHCR1_TCSH(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_TCSH_SHIFT)) & FlexSPI_FLSHCR1_TCSH_MASK) #define FlexSPI_FLSHCR1_WA_MASK (0x400U) #define FlexSPI_FLSHCR1_WA_SHIFT (10U) #define FlexSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_WA_SHIFT)) & FlexSPI_FLSHCR1_WA_MASK) #define FlexSPI_FLSHCR1_CAS_MASK (0x7800U) #define FlexSPI_FLSHCR1_CAS_SHIFT (11U) #define FlexSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_CAS_SHIFT)) & FlexSPI_FLSHCR1_CAS_MASK) #define FlexSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) #define FlexSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) /*! CSINTERVALUNIT - CS interval unit * 0b0..The CS interval unit is 1 serial clock cycle * 0b1..The CS interval unit is 256 serial clock cycle */ #define FlexSPI_FLSHCR1_CSINTERVALUNIT(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FlexSPI_FLSHCR1_CSINTERVALUNIT_MASK) #define FlexSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) #define FlexSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) #define FlexSPI_FLSHCR1_CSINTERVAL(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FlexSPI_FLSHCR1_CSINTERVAL_MASK) /*! @} */ /* The count of FlexSPI_FLSHCR1 */ #define FlexSPI_FLSHCR1_COUNT (4U) /*! @name FLSHCR2 - Flash Control Register 2 */ /*! @{ */ #define FlexSPI_FLSHCR2_ARDSEQID_MASK (0x1FU) #define FlexSPI_FLSHCR2_ARDSEQID_SHIFT (0U) #define FlexSPI_FLSHCR2_ARDSEQID(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_ARDSEQID_SHIFT)) & FlexSPI_FLSHCR2_ARDSEQID_MASK) #define FlexSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) #define FlexSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) #define FlexSPI_FLSHCR2_ARDSEQNUM(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FlexSPI_FLSHCR2_ARDSEQNUM_MASK) #define FlexSPI_FLSHCR2_AWRSEQID_MASK (0x1F00U) #define FlexSPI_FLSHCR2_AWRSEQID_SHIFT (8U) #define FlexSPI_FLSHCR2_AWRSEQID(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_AWRSEQID_SHIFT)) & FlexSPI_FLSHCR2_AWRSEQID_MASK) #define FlexSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) #define FlexSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) #define FlexSPI_FLSHCR2_AWRSEQNUM(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FlexSPI_FLSHCR2_AWRSEQNUM_MASK) #define FlexSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) #define FlexSPI_FLSHCR2_AWRWAIT_SHIFT (16U) #define FlexSPI_FLSHCR2_AWRWAIT(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_AWRWAIT_SHIFT)) & FlexSPI_FLSHCR2_AWRWAIT_MASK) #define FlexSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) #define FlexSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) /*! AWRWAITUNIT - AWRWAIT unit * 0b000..The AWRWAIT unit is 2 ahb clock cycle * 0b001..The AWRWAIT unit is 8 ahb clock cycle * 0b010..The AWRWAIT unit is 32 ahb clock cycle * 0b011..The AWRWAIT unit is 128 ahb clock cycle * 0b100..The AWRWAIT unit is 512 ahb clock cycle * 0b101..The AWRWAIT unit is 2048 ahb clock cycle * 0b110..The AWRWAIT unit is 8192 ahb clock cycle * 0b111..The AWRWAIT unit is 32768 ahb clock cycle */ #define FlexSPI_FLSHCR2_AWRWAITUNIT(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FlexSPI_FLSHCR2_AWRWAITUNIT_MASK) #define FlexSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) #define FlexSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) #define FlexSPI_FLSHCR2_CLRINSTRPTR(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FlexSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ /* The count of FlexSPI_FLSHCR2 */ #define FlexSPI_FLSHCR2_COUNT (4U) /*! @name FLSHCR4 - Flash Control Register 4 */ /*! @{ */ #define FlexSPI_FLSHCR4_WMOPT1_MASK (0x1U) #define FlexSPI_FLSHCR4_WMOPT1_SHIFT (0U) /*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment * limitation. 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB * write burst start address alignment when flash is accessed in individual mode. 0b1..DQS pin will not be used as Write * Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is * accessed in individual mode. */ #define FlexSPI_FLSHCR4_WMOPT1(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR4_WMOPT1_SHIFT)) & FlexSPI_FLSHCR4_WMOPT1_MASK) #define FlexSPI_FLSHCR4_WMENA_MASK (0x4U) #define FlexSPI_FLSHCR4_WMENA_SHIFT (2U) /*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for * memory device on port A, this bit must be set. * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external * device. */ #define FlexSPI_FLSHCR4_WMENA(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR4_WMENA_SHIFT)) & FlexSPI_FLSHCR4_WMENA_MASK) #define FlexSPI_FLSHCR4_WMENB_MASK (0x8U) #define FlexSPI_FLSHCR4_WMENB_SHIFT (3U) /*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for * memory device on port B, this bit must be set. * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external * device. */ #define FlexSPI_FLSHCR4_WMENB(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR4_WMENB_SHIFT)) & FlexSPI_FLSHCR4_WMENB_MASK) /*! @} */ /*! @name IPCR0 - IP Control Register 0 */ /*! @{ */ #define FlexSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) #define FlexSPI_IPCR0_SFAR_SHIFT (0U) #define FlexSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR0_SFAR_SHIFT)) & FlexSPI_IPCR0_SFAR_MASK) /*! @} */ /*! @name IPCR1 - IP Control Register 1 */ /*! @{ */ #define FlexSPI_IPCR1_IDATSZ_MASK (0xFFFFU) #define FlexSPI_IPCR1_IDATSZ_SHIFT (0U) #define FlexSPI_IPCR1_IDATSZ(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR1_IDATSZ_SHIFT)) & FlexSPI_IPCR1_IDATSZ_MASK) #define FlexSPI_IPCR1_ISEQID_MASK (0x1F0000U) #define FlexSPI_IPCR1_ISEQID_SHIFT (16U) #define FlexSPI_IPCR1_ISEQID(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR1_ISEQID_SHIFT)) & FlexSPI_IPCR1_ISEQID_MASK) #define FlexSPI_IPCR1_ISEQNUM_MASK (0x7000000U) #define FlexSPI_IPCR1_ISEQNUM_SHIFT (24U) #define FlexSPI_IPCR1_ISEQNUM(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR1_ISEQNUM_SHIFT)) & FlexSPI_IPCR1_ISEQNUM_MASK) #define FlexSPI_IPCR1_IPAREN_MASK (0x80000000U) #define FlexSPI_IPCR1_IPAREN_SHIFT (31U) /*! IPAREN - Parallel mode Enabled for IP command. * 0b0..Flash will be accessed in Individual mode. * 0b1..Flash will be accessed in Parallel mode. */ #define FlexSPI_IPCR1_IPAREN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR1_IPAREN_SHIFT)) & FlexSPI_IPCR1_IPAREN_MASK) /*! @} */ /*! @name IPCMD - IP Command Register */ /*! @{ */ #define FlexSPI_IPCMD_TRG_MASK (0x1U) #define FlexSPI_IPCMD_TRG_SHIFT (0U) #define FlexSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCMD_TRG_SHIFT)) & FlexSPI_IPCMD_TRG_MASK) /*! @} */ /*! @name DLPR - Data Learn Pattern Register */ /*! @{ */ #define FlexSPI_DLPR_DLP_MASK (0xFFFFFFFFU) #define FlexSPI_DLPR_DLP_SHIFT (0U) #define FlexSPI_DLPR_DLP(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLPR_DLP_SHIFT)) & FlexSPI_DLPR_DLP_MASK) /*! @} */ /*! @name IPRXFCR - IP RX FIFO Control Register */ /*! @{ */ #define FlexSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) #define FlexSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) #define FlexSPI_IPRXFCR_CLRIPRXF(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FlexSPI_IPRXFCR_CLRIPRXF_MASK) #define FlexSPI_IPRXFCR_RXDMAEN_MASK (0x2U) #define FlexSPI_IPRXFCR_RXDMAEN_SHIFT (1U) /*! RXDMAEN - IP RX FIFO reading by DMA enabled. * 0b0..IP RX FIFO would be read by processor. * 0b1..IP RX FIFO would be read by DMA. */ #define FlexSPI_IPRXFCR_RXDMAEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFCR_RXDMAEN_SHIFT)) & FlexSPI_IPRXFCR_RXDMAEN_MASK) #define FlexSPI_IPRXFCR_RXWMRK_MASK (0xFCU) #define FlexSPI_IPRXFCR_RXWMRK_SHIFT (2U) #define FlexSPI_IPRXFCR_RXWMRK(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFCR_RXWMRK_SHIFT)) & FlexSPI_IPRXFCR_RXWMRK_MASK) /*! @} */ /*! @name IPTXFCR - IP TX FIFO Control Register */ /*! @{ */ #define FlexSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) #define FlexSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) #define FlexSPI_IPTXFCR_CLRIPTXF(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FlexSPI_IPTXFCR_CLRIPTXF_MASK) #define FlexSPI_IPTXFCR_TXDMAEN_MASK (0x2U) #define FlexSPI_IPTXFCR_TXDMAEN_SHIFT (1U) /*! TXDMAEN - IP TX FIFO filling by DMA enabled. * 0b0..IP TX FIFO would be filled by processor. * 0b1..IP TX FIFO would be filled by DMA. */ #define FlexSPI_IPTXFCR_TXDMAEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFCR_TXDMAEN_SHIFT)) & FlexSPI_IPTXFCR_TXDMAEN_MASK) #define FlexSPI_IPTXFCR_TXWMRK_MASK (0x1FCU) #define FlexSPI_IPTXFCR_TXWMRK_SHIFT (2U) #define FlexSPI_IPTXFCR_TXWMRK(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFCR_TXWMRK_SHIFT)) & FlexSPI_IPTXFCR_TXWMRK_MASK) /*! @} */ /*! @name DLLCR - DLL Control Register 0 */ /*! @{ */ #define FlexSPI_DLLCR_DLLEN_MASK (0x1U) #define FlexSPI_DLLCR_DLLEN_SHIFT (0U) #define FlexSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_DLLEN_SHIFT)) & FlexSPI_DLLCR_DLLEN_MASK) #define FlexSPI_DLLCR_DLLRESET_MASK (0x2U) #define FlexSPI_DLLCR_DLLRESET_SHIFT (1U) #define FlexSPI_DLLCR_DLLRESET(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_DLLRESET_SHIFT)) & FlexSPI_DLLCR_DLLRESET_MASK) #define FlexSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) #define FlexSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) #define FlexSPI_DLLCR_SLVDLYTARGET(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FlexSPI_DLLCR_SLVDLYTARGET_MASK) #define FlexSPI_DLLCR_OVRDEN_MASK (0x100U) #define FlexSPI_DLLCR_OVRDEN_SHIFT (8U) #define FlexSPI_DLLCR_OVRDEN(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_OVRDEN_SHIFT)) & FlexSPI_DLLCR_OVRDEN_MASK) #define FlexSPI_DLLCR_OVRDVAL_MASK (0x7E00U) #define FlexSPI_DLLCR_OVRDVAL_SHIFT (9U) #define FlexSPI_DLLCR_OVRDVAL(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_OVRDVAL_SHIFT)) & FlexSPI_DLLCR_OVRDVAL_MASK) /*! @} */ /* The count of FlexSPI_DLLCR */ #define FlexSPI_DLLCR_COUNT (2U) /*! @name STS0 - Status Register 0 */ /*! @{ */ #define FlexSPI_STS0_SEQIDLE_MASK (0x1U) #define FlexSPI_STS0_SEQIDLE_SHIFT (0U) #define FlexSPI_STS0_SEQIDLE(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_SEQIDLE_SHIFT)) & FlexSPI_STS0_SEQIDLE_MASK) #define FlexSPI_STS0_ARBIDLE_MASK (0x2U) #define FlexSPI_STS0_ARBIDLE_SHIFT (1U) #define FlexSPI_STS0_ARBIDLE(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_ARBIDLE_SHIFT)) & FlexSPI_STS0_ARBIDLE_MASK) #define FlexSPI_STS0_ARBCMDSRC_MASK (0xCU) #define FlexSPI_STS0_ARBCMDSRC_SHIFT (2U) /*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted * by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). * 0b00..Triggered by AHB read command (triggered by AHB read). * 0b01..Triggered by AHB write command (triggered by AHB Write). * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). * 0b11..Triggered by suspended command (resumed). */ #define FlexSPI_STS0_ARBCMDSRC(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_ARBCMDSRC_SHIFT)) & FlexSPI_STS0_ARBCMDSRC_MASK) #define FlexSPI_STS0_DATALEARNPHASEA_MASK (0xF0U) #define FlexSPI_STS0_DATALEARNPHASEA_SHIFT (4U) #define FlexSPI_STS0_DATALEARNPHASEA(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_DATALEARNPHASEA_SHIFT)) & FlexSPI_STS0_DATALEARNPHASEA_MASK) #define FlexSPI_STS0_DATALEARNPHASEB_MASK (0xF00U) #define FlexSPI_STS0_DATALEARNPHASEB_SHIFT (8U) #define FlexSPI_STS0_DATALEARNPHASEB(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_DATALEARNPHASEB_SHIFT)) & FlexSPI_STS0_DATALEARNPHASEB_MASK) /*! @} */ /*! @name STS1 - Status Register 1 */ /*! @{ */ #define FlexSPI_STS1_AHBCMDERRID_MASK (0x1FU) #define FlexSPI_STS1_AHBCMDERRID_SHIFT (0U) #define FlexSPI_STS1_AHBCMDERRID(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS1_AHBCMDERRID_SHIFT)) & FlexSPI_STS1_AHBCMDERRID_MASK) #define FlexSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) #define FlexSPI_STS1_AHBCMDERRCODE_SHIFT (8U) /*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be * cleared when INTR[AHBCMDERR] is write-1-clear(w1c). * 0b0000..No error. * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence. * 0b0011..There is unknown instruction opcode in the sequence. * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. * 0b1110..Sequence execution timeout. */ #define FlexSPI_STS1_AHBCMDERRCODE(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS1_AHBCMDERRCODE_SHIFT)) & FlexSPI_STS1_AHBCMDERRCODE_MASK) #define FlexSPI_STS1_IPCMDERRID_MASK (0x1F0000U) #define FlexSPI_STS1_IPCMDERRID_SHIFT (16U) #define FlexSPI_STS1_IPCMDERRID(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS1_IPCMDERRID_SHIFT)) & FlexSPI_STS1_IPCMDERRID_MASK) #define FlexSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) #define FlexSPI_STS1_IPCMDERRCODE_SHIFT (24U) /*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be * cleared when INTR[IPCMDERR] is write-1-clear(w1c). * 0b0000..No error. * 0b0010..IP command with JMP_ON_CS instruction used in the sequence. * 0b0011..There is unknown instruction opcode in the sequence. * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. * 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2). * 0b1110..Sequence execution timeout. * 0b1111..Flash boundary crossed. */ #define FlexSPI_STS1_IPCMDERRCODE(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS1_IPCMDERRCODE_SHIFT)) & FlexSPI_STS1_IPCMDERRCODE_MASK) /*! @} */ /*! @name STS2 - Status Register 2 */ /*! @{ */ #define FlexSPI_STS2_ASLVLOCK_MASK (0x1U) #define FlexSPI_STS2_ASLVLOCK_SHIFT (0U) #define FlexSPI_STS2_ASLVLOCK(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_ASLVLOCK_SHIFT)) & FlexSPI_STS2_ASLVLOCK_MASK) #define FlexSPI_STS2_AREFLOCK_MASK (0x2U) #define FlexSPI_STS2_AREFLOCK_SHIFT (1U) #define FlexSPI_STS2_AREFLOCK(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_AREFLOCK_SHIFT)) & FlexSPI_STS2_AREFLOCK_MASK) #define FlexSPI_STS2_ASLVSEL_MASK (0xFCU) #define FlexSPI_STS2_ASLVSEL_SHIFT (2U) #define FlexSPI_STS2_ASLVSEL(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_ASLVSEL_SHIFT)) & FlexSPI_STS2_ASLVSEL_MASK) #define FlexSPI_STS2_AREFSEL_MASK (0x3F00U) #define FlexSPI_STS2_AREFSEL_SHIFT (8U) #define FlexSPI_STS2_AREFSEL(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_AREFSEL_SHIFT)) & FlexSPI_STS2_AREFSEL_MASK) #define FlexSPI_STS2_BSLVLOCK_MASK (0x10000U) #define FlexSPI_STS2_BSLVLOCK_SHIFT (16U) #define FlexSPI_STS2_BSLVLOCK(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_BSLVLOCK_SHIFT)) & FlexSPI_STS2_BSLVLOCK_MASK) #define FlexSPI_STS2_BREFLOCK_MASK (0x20000U) #define FlexSPI_STS2_BREFLOCK_SHIFT (17U) #define FlexSPI_STS2_BREFLOCK(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_BREFLOCK_SHIFT)) & FlexSPI_STS2_BREFLOCK_MASK) #define FlexSPI_STS2_BSLVSEL_MASK (0xFC0000U) #define FlexSPI_STS2_BSLVSEL_SHIFT (18U) #define FlexSPI_STS2_BSLVSEL(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_BSLVSEL_SHIFT)) & FlexSPI_STS2_BSLVSEL_MASK) #define FlexSPI_STS2_BREFSEL_MASK (0x3F000000U) #define FlexSPI_STS2_BREFSEL_SHIFT (24U) #define FlexSPI_STS2_BREFSEL(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_BREFSEL_SHIFT)) & FlexSPI_STS2_BREFSEL_MASK) /*! @} */ /*! @name AHBSPNDSTS - AHB Suspend Status Register */ /*! @{ */ #define FlexSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) #define FlexSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) #define FlexSPI_AHBSPNDSTS_ACTIVE(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FlexSPI_AHBSPNDSTS_ACTIVE_MASK) #define FlexSPI_AHBSPNDSTS_BUFID_MASK (0xEU) #define FlexSPI_AHBSPNDSTS_BUFID_SHIFT (1U) #define FlexSPI_AHBSPNDSTS_BUFID(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBSPNDSTS_BUFID_SHIFT)) & FlexSPI_AHBSPNDSTS_BUFID_MASK) #define FlexSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) #define FlexSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) #define FlexSPI_AHBSPNDSTS_DATLFT(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FlexSPI_AHBSPNDSTS_DATLFT_MASK) /*! @} */ /*! @name IPRXFSTS - IP RX FIFO Status Register */ /*! @{ */ #define FlexSPI_IPRXFSTS_FILL_MASK (0xFFU) #define FlexSPI_IPRXFSTS_FILL_SHIFT (0U) #define FlexSPI_IPRXFSTS_FILL(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFSTS_FILL_SHIFT)) & FlexSPI_IPRXFSTS_FILL_MASK) #define FlexSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) #define FlexSPI_IPRXFSTS_RDCNTR_SHIFT (16U) #define FlexSPI_IPRXFSTS_RDCNTR(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFSTS_RDCNTR_SHIFT)) & FlexSPI_IPRXFSTS_RDCNTR_MASK) /*! @} */ /*! @name IPTXFSTS - IP TX FIFO Status Register */ /*! @{ */ #define FlexSPI_IPTXFSTS_FILL_MASK (0xFFU) #define FlexSPI_IPTXFSTS_FILL_SHIFT (0U) #define FlexSPI_IPTXFSTS_FILL(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFSTS_FILL_SHIFT)) & FlexSPI_IPTXFSTS_FILL_MASK) #define FlexSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) #define FlexSPI_IPTXFSTS_WRCNTR_SHIFT (16U) #define FlexSPI_IPTXFSTS_WRCNTR(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFSTS_WRCNTR_SHIFT)) & FlexSPI_IPTXFSTS_WRCNTR_MASK) /*! @} */ /*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */ /*! @{ */ #define FlexSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) #define FlexSPI_RFDR_RXDATA_SHIFT (0U) #define FlexSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_RFDR_RXDATA_SHIFT)) & FlexSPI_RFDR_RXDATA_MASK) /*! @} */ /* The count of FlexSPI_RFDR */ #define FlexSPI_RFDR_COUNT (32U) /*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */ /*! @{ */ #define FlexSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) #define FlexSPI_TFDR_TXDATA_SHIFT (0U) #define FlexSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_TFDR_TXDATA_SHIFT)) & FlexSPI_TFDR_TXDATA_MASK) /*! @} */ /* The count of FlexSPI_TFDR */ #define FlexSPI_TFDR_COUNT (32U) /*! @name LUT - LUT 0..LUT 127 */ /*! @{ */ #define FlexSPI_LUT_OPERAND0_MASK (0xFFU) #define FlexSPI_LUT_OPERAND0_SHIFT (0U) #define FlexSPI_LUT_OPERAND0(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_OPERAND0_SHIFT)) & FlexSPI_LUT_OPERAND0_MASK) #define FlexSPI_LUT_NUM_PADS0_MASK (0x300U) #define FlexSPI_LUT_NUM_PADS0_SHIFT (8U) #define FlexSPI_LUT_NUM_PADS0(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_NUM_PADS0_SHIFT)) & FlexSPI_LUT_NUM_PADS0_MASK) #define FlexSPI_LUT_OPCODE0_MASK (0xFC00U) #define FlexSPI_LUT_OPCODE0_SHIFT (10U) #define FlexSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_OPCODE0_SHIFT)) & FlexSPI_LUT_OPCODE0_MASK) #define FlexSPI_LUT_OPERAND1_MASK (0xFF0000U) #define FlexSPI_LUT_OPERAND1_SHIFT (16U) #define FlexSPI_LUT_OPERAND1(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_OPERAND1_SHIFT)) & FlexSPI_LUT_OPERAND1_MASK) #define FlexSPI_LUT_NUM_PADS1_MASK (0x3000000U) #define FlexSPI_LUT_NUM_PADS1_SHIFT (24U) #define FlexSPI_LUT_NUM_PADS1(x) \ (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_NUM_PADS1_SHIFT)) & FlexSPI_LUT_NUM_PADS1_MASK) #define FlexSPI_LUT_OPCODE1_MASK (0xFC000000U) #define FlexSPI_LUT_OPCODE1_SHIFT (26U) #define FlexSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_OPCODE1_SHIFT)) & FlexSPI_LUT_OPCODE1_MASK) /*! @} */ /* The count of FlexSPI_LUT */ #define FlexSPI_LUT_COUNT (128U) /*! * @} */ /* end of group FlexSPI_Register_Masks */ /* FlexSPI - Peripheral instance base addresses */ /** Peripheral FLEXSPI base address */ #define FLEXSPI_BASE (0x30BB0000u) /** Peripheral FLEXSPI base pointer */ #define FLEXSPI ((FlexSPI_Type *)FLEXSPI_BASE) /** Array initializer of FlexSPI peripheral base addresses */ #define FlexSPI_BASE_ADDRS \ { \ FLEXSPI_BASE \ } /** Array initializer of FlexSPI peripheral base pointers */ #define FlexSPI_BASE_PTRS \ { \ FLEXSPI \ } /*! * @} */ /* end of group FlexSPI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer * @{ */ /** GPC - Register Layout Typedef */ typedef struct { __IO uint32_t LPCR_A53_BSC; /**< Basic Low power control register of A53 platform, offset: 0x0 */ __IO uint32_t LPCR_A53_AD; /**< Advanced Low power control register of A53 platform, offset: 0x4 */ __IO uint32_t LPCR_M7; /**< Low power control register of CPU1, offset: 0x8 */ uint8_t RESERVED_0[8]; __IO uint32_t SLPCR; /**< System low power control register, offset: 0x14 */ __IO uint32_t MST_CPU_MAPPING; /**< MASTER LPM Handshake, offset: 0x18 */ uint8_t RESERVED_1[4]; __IO uint32_t MLPCR; /**< Memory low power control register, offset: 0x20 */ __IO uint32_t PGC_ACK_SEL_A53; /**< PGC acknowledge signal selection of A53 platform, offset: 0x24 */ __IO uint32_t PGC_ACK_SEL_M7; /**< PGC acknowledge signal selection of M7 platform, offset: 0x28 */ __IO uint32_t MISC; /**< GPC Miscellaneous register, offset: 0x2C */ __IO uint32_t IMR_CORE0_A53[4]; /**< IRQ masking register 1 of A53 core0..IRQ masking register 4 of A53 core0, array offset: 0x30, array step: 0x4 */ __IO uint32_t IMR_CORE1_A53[4]; /**< IRQ masking register 1 of A53 core1..IRQ masking register 4 of A53 core1, array offset: 0x40, array step: 0x4 */ __IO uint32_t IMR_M7[4]; /**< IRQ masking register 1 of M7..IRQ masking register 4 of M7, array offset: 0x50, array step: 0x4 */ uint8_t RESERVED_2[16]; __I uint32_t ISR_A53[4]; /**< IRQ status register 1 of A53..IRQ status register 4 of A53, array offset: 0x70, array step: 0x4 */ __I uint32_t ISR_M7[4]; /**< IRQ status register 1 of M7..IRQ status register 4 of M7, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_3[32]; __IO uint32_t SLT0_CFG; /**< Slot configure register for CPUs, offset: 0xB0 */ __IO uint32_t SLT1_CFG; /**< Slot configure register for CPUs, offset: 0xB4 */ __IO uint32_t SLT2_CFG; /**< Slot configure register for CPUs, offset: 0xB8 */ __IO uint32_t SLT3_CFG; /**< Slot configure register for CPUs, offset: 0xBC */ __IO uint32_t SLT4_CFG; /**< Slot configure register for CPUs, offset: 0xC0 */ __IO uint32_t SLT5_CFG; /**< Slot configure register for CPUs, offset: 0xC4 */ __IO uint32_t SLT6_CFG; /**< Slot configure register for CPUs, offset: 0xC8 */ __IO uint32_t SLT7_CFG; /**< Slot configure register for CPUs, offset: 0xCC */ __IO uint32_t SLT8_CFG; /**< Slot configure register for CPUs, offset: 0xD0 */ __IO uint32_t SLT9_CFG; /**< Slot configure register for CPUs, offset: 0xD4 */ __IO uint32_t SLT10_CFG; /**< Slot configure register for CPUs, offset: 0xD8 */ __IO uint32_t SLT11_CFG; /**< Slot configure register for CPUs, offset: 0xDC */ __IO uint32_t SLT12_CFG; /**< Slot configure register for CPUs, offset: 0xE0 */ __IO uint32_t SLT13_CFG; /**< Slot configure register for CPUs, offset: 0xE4 */ __IO uint32_t SLT14_CFG; /**< Slot configure register for CPUs, offset: 0xE8 */ __IO uint32_t PGC_CPU_0_1_MAPPING; /**< PGC CPU mapping, offset: 0xEC */ __IO uint32_t CPU_PGC_SW_PUP_REQ; /**< CPU PGC software power up trigger, offset: 0xF0 */ __IO uint32_t MIX_PGC_SW_PUP_REQ; /**< MIX PGC software power up trigger, offset: 0xF4 */ __IO uint32_t PU_PGC_SW_PUP_REQ; /**< PU PGC software up trigger, offset: 0xF8 */ __IO uint32_t CPU_PGC_SW_PDN_REQ; /**< CPU PGC software down trigger, offset: 0xFC */ __IO uint32_t MIX_PGC_SW_PDN_REQ; /**< MIX PGC software power down trigger, offset: 0x100 */ __IO uint32_t PU_PGC_SW_PDN_REQ; /**< PU PGC software down trigger, offset: 0x104 */ __IO uint32_t LPCR_A53_BSC2; /**< Basic Low power control register of A53 platform, offset: 0x108 */ uint8_t RESERVED_4[36]; __I uint32_t CPU_PGC_PUP_STATUS1; /**< CPU PGC software up trigger status1, offset: 0x130 */ __I uint32_t A53_MIX_PGC_PUP_STATUS[3]; /**< A53 MIX software up trigger status register, array offset: 0x134, array step: 0x4 */ __I uint32_t M7_MIX_PGC_PUP_STATUS[3]; /**< M7 MIX PGC software up trigger status register, array offset: 0x140, array step: 0x4 */ __I uint32_t A53_PU_PGC_PUP_STATUS[3]; /**< A53 PU software up trigger status register, array offset: 0x14C, array step: 0x4 */ __I uint32_t M7_PU_PGC_PUP_STATUS[3]; /**< M7 PU PGC software up trigger status register, array offset: 0x158, array step: 0x4 */ uint8_t RESERVED_5[12]; __I uint32_t CPU_PGC_PDN_STATUS1; /**< CPU PGC software dn trigger status1, offset: 0x170 */ __I uint32_t A53_MIX_PGC_PDN_STATUS[3]; /**< A53 MIX software down trigger status register, array offset: 0x174, array step: 0x4 */ __I uint32_t M7_MIX_PGC_PDN_STATUS[3]; /**< M7 MIX PGC software power down trigger status register, array offset: 0x180, array step: 0x4 */ __I uint32_t A53_PU_PGC_PDN_STATUS[3]; /**< A53 PU PGC software down trigger status, array offset: 0x18C, array step: 0x4 */ __I uint32_t M7_PU_PGC_PDN_STATUS[3]; /**< M7 PU PGC software down trigger status, array offset: 0x198, array step: 0x4 */ uint8_t RESERVED_6[12]; __IO uint32_t A53_MIX_PDN_FLG; /**< A53 MIX PDN FLG, offset: 0x1B0 */ __IO uint32_t A53_PU_PDN_FLG; /**< A53 PU PDN FLG, offset: 0x1B4 */ __IO uint32_t M7_MIX_PDN_FLG; /**< M7 MIX PDN FLG, offset: 0x1B8 */ __IO uint32_t M7_PU_PDN_FLG; /**< M7 PU PDN FLG, offset: 0x1BC */ __IO uint32_t IMR_CORE2_A53[4]; /**< IRQ masking register 1 of A53 core2..IRQ masking register 4 of A53 core2, array offset: 0x1C0, array step: 0x4 */ __IO uint32_t IMR_CORE3_A53[4]; /**< IRQ masking register 1 of A53 core3..IRQ masking register 4 of A53 core3, array offset: 0x1D0, array step: 0x4 */ __IO uint32_t ACK_SEL_A53_PU; /**< PGC acknowledge signal selection of A53 platform for PUs, offset: 0x1E0 */ __IO uint32_t ACK_SEL_M7_PU; /**< PGC acknowledge signal selection of M7 platform for PUs, offset: 0x1E4 */ __IO uint32_t SLT15_CFG; /**< Slot configure register for PGC CPUs, offset: 0x1E8 */ __IO uint32_t SLT16_CFG; /**< Slot configure register for PGC CPUs, offset: 0x1EC */ __IO uint32_t SLT17_CFG; /**< Slot configure register for PGC CPUs, offset: 0x1F0 */ __IO uint32_t SLT18_CFG; /**< Slot configure register for PGC CPUs, offset: 0x1F4 */ __IO uint32_t SLT19_CFG; /**< Slot configure register for PGC CPUs, offset: 0x1F8 */ __IO uint32_t PU_PWRHSK; /**< Power handshake register, offset: 0x1FC */ __IO uint32_t SLT_CFG_PU[20]; /**< Slot configure register for PGC PUs, array offset: 0x200, array step: 0x4 */ } GPC_Type; /* ---------------------------------------------------------------------------- -- GPC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPC_Register_Masks GPC Register Masks * @{ */ /*! @name LPCR_A53_BSC - Basic Low power control register of A53 platform */ /*! @{ */ #define GPC_LPCR_A53_BSC_LPM0_MASK (0x3U) #define GPC_LPCR_A53_BSC_LPM0_SHIFT (0U) /*! LPM0 * 0b00..Remain in RUN mode * 0b01..Transfer to WAIT mode * 0b10..Transfer to STOP mode * 0b11..Reserved */ #define GPC_LPCR_A53_BSC_LPM0(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_LPM0_SHIFT)) & GPC_LPCR_A53_BSC_LPM0_MASK) #define GPC_LPCR_A53_BSC_LPM1_MASK (0xCU) #define GPC_LPCR_A53_BSC_LPM1_SHIFT (2U) /*! LPM1 * 0b00..Remain in RUN mode * 0b01..Transfer to WAIT mode * 0b10..Transfer to STOP mode * 0b11..Reserved */ #define GPC_LPCR_A53_BSC_LPM1(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_LPM1_SHIFT)) & GPC_LPCR_A53_BSC_LPM1_MASK) #define GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK_MASK (0x40U) #define GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK_SHIFT (6U) /*! MST0_LPM_HSK_MASK - MASTER0 LPM handshake mask * 0b0..enable MASTER0 LPM handshake, wait ACK from MASTER0 * 0b1..disable MASTER0 LPM handshake, mask ACK from MASTER0 */ #define GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK_SHIFT)) & \ GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK_MASK) #define GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK_MASK (0x80U) #define GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK_SHIFT (7U) /*! MST1_LPM_HSK_MASK - MASTER1 LPM handshake mask * 0b0..enable MASTER1 LPM handshake, wait ACK from MASTER1 * 0b1..disable MASTER1 LPM handshake, mask ACK from MASTER1 */ #define GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK_SHIFT)) & \ GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK_MASK) #define GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK_MASK (0x100U) #define GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK_SHIFT (8U) /*! MST2_LPM_HSK_MASK - MASTER2 LPM handshake mask * 0b0..enable MASTER2 LPM handshake, wait ACK from MASTER2 * 0b1..disable MASTER2 LPM handshake, mask ACK from MASTER2 */ #define GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK_SHIFT)) & \ GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK_MASK) #define GPC_LPCR_A53_BSC_MST3_LPM_HSK_MASK_MASK (0x200U) #define GPC_LPCR_A53_BSC_MST3_LPM_HSK_MASK_SHIFT (9U) /*! MST3_LPM_HSK_MASK - MASTER3 LPM handshake mask * 0b0..enable MASTER3 LPM handshake, wait ACK from MASTER3 * 0b1..disable MASTER3 LPM handshake, mask ACK from MASTER3 */ #define GPC_LPCR_A53_BSC_MST3_LPM_HSK_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST3_LPM_HSK_MASK_SHIFT)) & \ GPC_LPCR_A53_BSC_MST3_LPM_HSK_MASK_MASK) #define GPC_LPCR_A53_BSC_MST4_LPM_HSK_MASK_MASK (0x400U) #define GPC_LPCR_A53_BSC_MST4_LPM_HSK_MASK_SHIFT (10U) /*! MST4_LPM_HSK_MASK - MASTER4 LPM handshake mask * 0b0..enable MASTER4 LPM handshake, wait ACK from MASTER4 * 0b1..disable MASTER4 LPM handshake, mask ACK from MASTER4 */ #define GPC_LPCR_A53_BSC_MST4_LPM_HSK_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST4_LPM_HSK_MASK_SHIFT)) & \ GPC_LPCR_A53_BSC_MST4_LPM_HSK_MASK_MASK) #define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_MASK (0x4000U) #define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_SHIFT (14U) /*! CPU_CLK_ON_LPM * 0b0..A53 clock disabled on wait/stop mode * 0b1..A53 clock enabled on wait/stop mode */ #define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_SHIFT)) & GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_MASK) #define GPC_LPCR_A53_BSC_MASK_CORE0_WFI_MASK (0x10000U) #define GPC_LPCR_A53_BSC_MASK_CORE0_WFI_SHIFT (16U) /*! MASK_CORE0_WFI * 0b0..WFI for CORE0 is not masked * 0b1..WFI for CORE0 is masked */ #define GPC_LPCR_A53_BSC_MASK_CORE0_WFI(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE0_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE0_WFI_MASK) #define GPC_LPCR_A53_BSC_MASK_CORE1_WFI_MASK (0x20000U) #define GPC_LPCR_A53_BSC_MASK_CORE1_WFI_SHIFT (17U) /*! MASK_CORE1_WFI * 0b0..WFI for CORE1 is not masked * 0b1..WFI for CORE1 is masked */ #define GPC_LPCR_A53_BSC_MASK_CORE1_WFI(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE1_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE1_WFI_MASK) #define GPC_LPCR_A53_BSC_MASK_CORE2_WFI_MASK (0x40000U) #define GPC_LPCR_A53_BSC_MASK_CORE2_WFI_SHIFT (18U) /*! MASK_CORE2_WFI * 0b0..WFI for CORE2 is not masked * 0b1..WFI for CORE2 is masked */ #define GPC_LPCR_A53_BSC_MASK_CORE2_WFI(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE2_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE2_WFI_MASK) #define GPC_LPCR_A53_BSC_MASK_CORE3_WFI_MASK (0x80000U) #define GPC_LPCR_A53_BSC_MASK_CORE3_WFI_SHIFT (19U) /*! MASK_CORE3_WFI * 0b0..WFI for CORE3 is not masked * 0b1..WFI for CORE3 is masked */ #define GPC_LPCR_A53_BSC_MASK_CORE3_WFI(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE3_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE3_WFI_MASK) #define GPC_LPCR_A53_BSC_IRQ_SRC_C2_MASK (0x400000U) #define GPC_LPCR_A53_BSC_IRQ_SRC_C2_SHIFT (22U) /*! IRQ_SRC_C2 * 0b0..core2 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53 Platform for more * specific information. 0b1..core2 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down * during low power mode when this bit is set to 1'b1. */ #define GPC_LPCR_A53_BSC_IRQ_SRC_C2(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C2_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C2_MASK) #define GPC_LPCR_A53_BSC_IRQ_SRC_C3_MASK (0x800000U) #define GPC_LPCR_A53_BSC_IRQ_SRC_C3_SHIFT (23U) /*! IRQ_SRC_C3 * 0b0..core3 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53 Platform for more * specific information. 0b1..core3 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down * during low power mode when this bit is set to 1'b1. */ #define GPC_LPCR_A53_BSC_IRQ_SRC_C3(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C3_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C3_MASK) #define GPC_LPCR_A53_BSC_MASK_SCU_WFI_MASK (0x1000000U) #define GPC_LPCR_A53_BSC_MASK_SCU_WFI_SHIFT (24U) /*! MASK_SCU_WFI * 0b0..WFI for SCU is not masked * 0b1..WFI for SCU is masked */ #define GPC_LPCR_A53_BSC_MASK_SCU_WFI(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_SCU_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_SCU_WFI_MASK) #define GPC_LPCR_A53_BSC_MASK_L2CC_WFI_MASK (0x4000000U) #define GPC_LPCR_A53_BSC_MASK_L2CC_WFI_SHIFT (26U) /*! MASK_L2CC_WFI * 0b0..WFI for L2 cache controller is not masked * 0b1..WFI for L2 cache controller is masked */ #define GPC_LPCR_A53_BSC_MASK_L2CC_WFI(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_L2CC_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_L2CC_WFI_MASK) #define GPC_LPCR_A53_BSC_IRQ_SRC_C0_MASK (0x10000000U) #define GPC_LPCR_A53_BSC_IRQ_SRC_C0_SHIFT (28U) /*! IRQ_SRC_C0 * 0b0..core0 wakeup source from external INT[127:0], masked by IMR0 refer to "Power up process for A53 platform" for * more specific information 0b1..core0 wakeup source from GIC(nFIQ[0]/nIRQ[0] ), SCU should not be power down during * low power mode when this bit is set to 1'b1 */ #define GPC_LPCR_A53_BSC_IRQ_SRC_C0(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C0_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C0_MASK) #define GPC_LPCR_A53_BSC_IRQ_SRC_C1_MASK (0x20000000U) #define GPC_LPCR_A53_BSC_IRQ_SRC_C1_SHIFT (29U) /*! IRQ_SRC_C1 * 0b0..core1 wakeup source from external INT[127:0], masked by IMR1 refer to "Power up process for A53 platform" for * more specific information 0b1..core1 wakeup source from GIC(nFIQ[1]/nIRQ[1] ), SCU should not be power down during * low power mode when this bit is set to 1'b1 */ #define GPC_LPCR_A53_BSC_IRQ_SRC_C1(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C1_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C1_MASK) #define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_MASK (0x40000000U) #define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_SHIFT (30U) /*! IRQ_SRC_A53_WUP * 0b0..LPM wakeup source be "OR" result of * LPCR_A53_BSC[IRQ_SRC_C0]/LPCR_A53_BSC[IRQ_SRC_C1]/LPCR_A53_BSC[IRQ_SRC_C2]/LPCR_A53_BSC[IRQ_SRC_C3] setting * 0b1..LPM wakeup source from external INT[127:0], masked by IMR0 */ #define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_MASK) #define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_MASK (0x80000000U) #define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_SHIFT (31U) /*! MASK_DSM_TRIGGER * 0b0..DSM trigger of A53 platform will not be masked * 0b1..DSM trigger of A53 platform will be masked */ #define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_SHIFT)) & GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_MASK) /*! @} */ /*! @name LPCR_A53_AD - Advanced Low power control register of A53 platform */ /*! @{ */ #define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_MASK (0x1U) #define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_SHIFT (0U) /*! EN_C0_WFI_PDN * 0b0..CORE0 will not be power down with WFI request * 0b1..CORE0 will be power down with WFI request */ #define GPC_LPCR_A53_AD_EN_C0_WFI_PDN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_WFI_PDN_MASK) #define GPC_LPCR_A53_AD_EN_C0_PDN_MASK (0x2U) #define GPC_LPCR_A53_AD_EN_C0_PDN_SHIFT (1U) /*! EN_C0_PDN * 0b0..CORE0 will not be power down with low power mode request * 0b1..CORE0 will be power down with low power mode request */ #define GPC_LPCR_A53_AD_EN_C0_PDN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_PDN_MASK) #define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_MASK (0x4U) #define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_SHIFT (2U) /*! EN_C1_WFI_PDN * 0b0..CORE1 will not be power down with WFI request * 0b1..CORE1 will be power down with WFI request */ #define GPC_LPCR_A53_AD_EN_C1_WFI_PDN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_WFI_PDN_MASK) #define GPC_LPCR_A53_AD_EN_C1_PDN_MASK (0x8U) #define GPC_LPCR_A53_AD_EN_C1_PDN_SHIFT (3U) /*! EN_C1_PDN * 0b0..CORE1 will not be power down with low power mode request * 0b1..CORE1 will be power down with low power mode request */ #define GPC_LPCR_A53_AD_EN_C1_PDN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_PDN_MASK) #define GPC_LPCR_A53_AD_EN_PLAT_PDN_MASK (0x10U) #define GPC_LPCR_A53_AD_EN_PLAT_PDN_SHIFT (4U) /*! EN_PLAT_PDN * 0b0..SCU and L2 cache RAM will not be power down with low power mode request * 0b1..SCU and L2 cache RAM will be power down with low power mode request */ #define GPC_LPCR_A53_AD_EN_PLAT_PDN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_PLAT_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_PLAT_PDN_MASK) #define GPC_LPCR_A53_AD_EN_L2_WFI_PDN_MASK (0x20U) #define GPC_LPCR_A53_AD_EN_L2_WFI_PDN_SHIFT (5U) /*! EN_L2_WFI_PDN * 0b0..SCU and L2 will not be power down with WFI request * 0b1..SCU and L2 will be power down with WFI request (default) */ #define GPC_LPCR_A53_AD_EN_L2_WFI_PDN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_L2_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_L2_WFI_PDN_MASK) #define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_MASK (0x100U) #define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_SHIFT (8U) /*! EN_C0_IRQ_PUP * 0b0..CORE0 will not power up with IRQ request * 0b1..CORE0 will power up with IRQ request */ #define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_MASK) #define GPC_LPCR_A53_AD_EN_C0_PUP_MASK (0x200U) #define GPC_LPCR_A53_AD_EN_C0_PUP_SHIFT (9U) /*! EN_C0_PUP * 0b0..CORE0 will not power up with low power mode request * 0b1..CORE0 will power up with low power mode request */ #define GPC_LPCR_A53_AD_EN_C0_PUP(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_PUP_MASK) #define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_MASK (0x400U) #define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_SHIFT (10U) /*! EN_C1_IRQ_PUP * 0b0..CORE1 will not power up with IRQ request * 0b1..CORE1 will power up with IRQ request */ #define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_MASK) #define GPC_LPCR_A53_AD_EN_C1_PUP_MASK (0x800U) #define GPC_LPCR_A53_AD_EN_C1_PUP_SHIFT (11U) /*! EN_C1_PUP * 0b0..CORE1 will not power up with low power mode request (only used wake up from CPU01_OFF mode) * 0b1..CORE1 will power up with low power mode request */ #define GPC_LPCR_A53_AD_EN_C1_PUP(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_PUP_MASK) #define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_MASK (0x10000U) #define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_SHIFT (16U) /*! EN_C2_WFI_PDN * 0b0..CORE2 will not be power down with WFI request * 0b1..CORE2 will be power down with WFI request */ #define GPC_LPCR_A53_AD_EN_C2_WFI_PDN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_WFI_PDN_MASK) #define GPC_LPCR_A53_AD_EN_C2_PDN_MASK (0x20000U) #define GPC_LPCR_A53_AD_EN_C2_PDN_SHIFT (17U) /*! EN_C2_PDN * 0b0..CORE2 will not be power down with low power mode request * 0b1..CORE2 will be power down with low power mode request */ #define GPC_LPCR_A53_AD_EN_C2_PDN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_PDN_MASK) #define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_MASK (0x40000U) #define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_SHIFT (18U) /*! EN_C3_WFI_PDN * 0b0..CORE3 will not be power down with WFI request * 0b1..CORE3 will be power down with WFI request */ #define GPC_LPCR_A53_AD_EN_C3_WFI_PDN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_WFI_PDN_MASK) #define GPC_LPCR_A53_AD_EN_C3_PDN_MASK (0x80000U) #define GPC_LPCR_A53_AD_EN_C3_PDN_SHIFT (19U) /*! EN_C3_PDN * 0b0..CORE3 will not be power down with low power mode request * 0b1..CORE3 will be power down with low power mode request */ #define GPC_LPCR_A53_AD_EN_C3_PDN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_PDN_MASK) #define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_MASK (0x100000U) #define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_SHIFT (20U) /*! EN_C0_WFI_PDN_DIS * 0b0..Disable WIFI power down core0 * 0b1..Enable WIFI power down core0 */ #define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_MASK) #define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_MASK (0x200000U) #define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_SHIFT (21U) /*! EN_C1_WFI_PDN_DIS * 0b0..Disable WIFI power down core1 * 0b1..Enable WIFI power down core1 */ #define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_MASK) #define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_MASK (0x400000U) #define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_SHIFT (22U) /*! EN_C2_WFI_PDN_DIS * 0b0..Disable WIFI power down core2 * 0b1..Enable WIFI power down core2 */ #define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_MASK) #define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_MASK (0x800000U) #define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_SHIFT (23U) /*! EN_C3_WFI_PDN_DIS * 0b0..Disable WFI power down core3 * 0b1..Enable WFI power down core3 */ #define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_MASK) #define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_MASK (0x1000000U) #define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_SHIFT (24U) /*! EN_C2_IRQ_PUP * 0b0..CORE2 will not power up with IRQ request * 0b1..CORE2 will power up with IRQ request */ #define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_MASK) #define GPC_LPCR_A53_AD_EN_C2_PUP_MASK (0x2000000U) #define GPC_LPCR_A53_AD_EN_C2_PUP_SHIFT (25U) /*! EN_C2_PUP * 0b0..CORE2 will not power up with lower power mode request * 0b1..CORE2 will power up with low power mode request (only used wake up from CPU_OFF) */ #define GPC_LPCR_A53_AD_EN_C2_PUP(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_PUP_MASK) #define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_MASK (0x4000000U) #define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_SHIFT (26U) /*! EN_C3_IRQ_PUP * 0b0..CORE3 will not power up with IRQ request * 0b1..CORE3 will power up with IRQ request */ #define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_MASK) #define GPC_LPCR_A53_AD_EN_C3_PUP_MASK (0x8000000U) #define GPC_LPCR_A53_AD_EN_C3_PUP_SHIFT (27U) /*! EN_C3_PUP * 0b0..CORE3 will not power up with lower power mode request * 0b1..CORE3 will power up with low power mode request (only used wake up from CPU_OFF) */ #define GPC_LPCR_A53_AD_EN_C3_PUP(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_PUP_MASK) #define GPC_LPCR_A53_AD_L2PGE_MASK (0x80000000U) #define GPC_LPCR_A53_AD_L2PGE_SHIFT (31U) /*! L2PGE * 0b0..L2 cache RAM will power down with SCU power domain in A53 platform (used for ALL_OFF mode) * 0b1..L2 cache RAM will not power down with SCU power domain in A53 platform (used for ALL_OFF mode) */ #define GPC_LPCR_A53_AD_L2PGE(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_L2PGE_SHIFT)) & GPC_LPCR_A53_AD_L2PGE_MASK) /*! @} */ /*! @name LPCR_M7 - Low power control register of CPU1 */ /*! @{ */ #define GPC_LPCR_M7_LPM0_MASK (0x3U) #define GPC_LPCR_M7_LPM0_SHIFT (0U) /*! LPM0 * 0b00..Remain in RUN mode * 0b01..Transfer to WAIT mode * 0b10..Transfer to STOP mode * 0b11..Reserved */ #define GPC_LPCR_M7_LPM0(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_LPM0_SHIFT)) & GPC_LPCR_M7_LPM0_MASK) #define GPC_LPCR_M7_EN_M7_PDN_MASK (0x4U) #define GPC_LPCR_M7_EN_M7_PDN_SHIFT (2U) #define GPC_LPCR_M7_EN_M7_PDN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_EN_M7_PDN_SHIFT)) & GPC_LPCR_M7_EN_M7_PDN_MASK) #define GPC_LPCR_M7_EN_M7_PUP_MASK (0x8U) #define GPC_LPCR_M7_EN_M7_PUP_SHIFT (3U) #define GPC_LPCR_M7_EN_M7_PUP(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_EN_M7_PUP_SHIFT)) & GPC_LPCR_M7_EN_M7_PUP_MASK) #define GPC_LPCR_M7_CPU_CLK_ON_LPM_MASK (0x4000U) #define GPC_LPCR_M7_CPU_CLK_ON_LPM_SHIFT (14U) /*! CPU_CLK_ON_LPM * 0b0..M7 clock disabled on wait/stop mode. * 0b1..M7 clock enabled on wait/stop mode. */ #define GPC_LPCR_M7_CPU_CLK_ON_LPM(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_CPU_CLK_ON_LPM_SHIFT)) & GPC_LPCR_M7_CPU_CLK_ON_LPM_MASK) #define GPC_LPCR_M7_MASK_M7_WFI_MASK (0x10000U) #define GPC_LPCR_M7_MASK_M7_WFI_SHIFT (16U) /*! MASK_M7_WFI * 0b0..WFI for M7 is not masked * 0b1..WFI for M7 is masked */ #define GPC_LPCR_M7_MASK_M7_WFI(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_MASK_M7_WFI_SHIFT)) & GPC_LPCR_M7_MASK_M7_WFI_MASK) #define GPC_LPCR_M7_MASK_DSM_TRIGGER_MASK (0x80000000U) #define GPC_LPCR_M7_MASK_DSM_TRIGGER_SHIFT (31U) /*! MASK_DSM_TRIGGER * 0b0..DSM trigger of M7 platform will not be masked * 0b1..DSM trigger of M7 platform will be masked */ #define GPC_LPCR_M7_MASK_DSM_TRIGGER(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_MASK_DSM_TRIGGER_SHIFT)) & GPC_LPCR_M7_MASK_DSM_TRIGGER_MASK) /*! @} */ /*! @name SLPCR - System low power control register */ /*! @{ */ #define GPC_SLPCR_BYPASS_PMIC_READY_MASK (0x1U) #define GPC_SLPCR_BYPASS_PMIC_READY_SHIFT (0U) /*! BYPASS_PMIC_READY * 0b0..Don't bypass the PMIC_READY signal - GPC will wait for its assertion during exit of low power mode if standby * voltage was enabled 0b1..Bypass the PMIC_READY signal - GPC will not wait for its assertion during exit of low power * mode if standby voltage was enabled */ #define GPC_SLPCR_BYPASS_PMIC_READY(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_BYPASS_PMIC_READY_SHIFT)) & GPC_SLPCR_BYPASS_PMIC_READY_MASK) #define GPC_SLPCR_SBYOS_MASK (0x2U) #define GPC_SLPCR_SBYOS_SHIFT (1U) /*! SBYOS * 0b0..On chip oscillator will not be powered down, after next entrance to DSM. * 0b1..On chip oscillator will be powered down, after next entrance to DSM. When returning from DSM, external * oscillator will be enabled again, on chip oscillator will return to oscillator mode , and after oscnt count * GPC will continue with the exit from DSM process. */ #define GPC_SLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_SBYOS_SHIFT)) & GPC_SLPCR_SBYOS_MASK) #define GPC_SLPCR_VSTBY_MASK (0x4U) #define GPC_SLPCR_VSTBY_SHIFT (2U) /*! VSTBY * 0b0..Voltage will not be changed to standby voltage after next entrance to stop mode. (PMIC_STBY_REQ will remain * negated - '0') 0b1..Voltage will be changed to standby voltage after next entrance to stop mode. */ #define GPC_SLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_VSTBY_SHIFT)) & GPC_SLPCR_VSTBY_MASK) #define GPC_SLPCR_STBY_COUNT_MASK (0x38U) #define GPC_SLPCR_STBY_COUNT_SHIFT (3U) /*! STBY_COUNT * 0b000..GPC will wait 4 ckil clock cycles * 0b001..GPC will wait 8 ckil clock cycles * 0b010..GPC will wait 16 ckil clock cycles * 0b011..GPC will wait 32 ckil clock cycles * 0b100..GPC will wait 64 ckil clock cycles * 0b101..GPC will wait 128 ckil clock cycles * 0b110..GPC will wait 256 ckil clock cycles * 0b111..GPC will wait 512 ckil clock cycles */ #define GPC_SLPCR_STBY_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_STBY_COUNT_SHIFT)) & GPC_SLPCR_STBY_COUNT_MASK) #define GPC_SLPCR_COSC_PWRDOWN_MASK (0x40U) #define GPC_SLPCR_COSC_PWRDOWN_SHIFT (6U) /*! COSC_PWRDOWN * 0b0..On-chip oscillator will not be powered down, i.e. cosc_pwrdown = 0 * 0b1..On-chip oscillator will be powered down, i.e. cosc_pwrdown = 1 */ #define GPC_SLPCR_COSC_PWRDOWN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_COSC_PWRDOWN_SHIFT)) & GPC_SLPCR_COSC_PWRDOWN_MASK) #define GPC_SLPCR_COSC_EN_MASK (0x80U) #define GPC_SLPCR_COSC_EN_SHIFT (7U) /*! COSC_EN * 0b0..Disable on-chip oscillator * 0b1..Enable on-chip oscillator */ #define GPC_SLPCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_COSC_EN_SHIFT)) & GPC_SLPCR_COSC_EN_MASK) #define GPC_SLPCR_OSCCNT_MASK (0xFF00U) #define GPC_SLPCR_OSCCNT_SHIFT (8U) /*! OSCCNT * 0b00000000..count 1 ckil * 0b11111111..count 256 ckils */ #define GPC_SLPCR_OSCCNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_OSCCNT_SHIFT)) & GPC_SLPCR_OSCCNT_MASK) #define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_MASK (0x10000U) #define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_SHIFT (16U) #define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_SHIFT)) & \ GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_MASK) #define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_MASK (0x20000U) #define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_SHIFT (17U) #define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_SHIFT)) & \ GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_MASK) #define GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE_MASK (0x40000U) #define GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE_SHIFT (18U) #define GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE_SHIFT)) & GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE_MASK) #define GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE_MASK (0x80000U) #define GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE_SHIFT (19U) #define GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE_SHIFT)) & GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE_MASK) #define GPC_SLPCR_DISABLE_A53_IS_DSM_MASK (0x800000U) #define GPC_SLPCR_DISABLE_A53_IS_DSM_SHIFT (23U) /*! DISABLE_A53_IS_DSM * 0b0..Enable A53 isolation signal in DSM * 0b1..Disable A53 isolation signal in DSM */ #define GPC_SLPCR_DISABLE_A53_IS_DSM(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_DISABLE_A53_IS_DSM_SHIFT)) & GPC_SLPCR_DISABLE_A53_IS_DSM_MASK) #define GPC_SLPCR_REG_BYPASS_COUNT_MASK (0x3F000000U) #define GPC_SLPCR_REG_BYPASS_COUNT_SHIFT (24U) /*! REG_BYPASS_COUNT * 0b000000..no delay * 0b000001..1 CKIL clock period delay * 0b111111..63 CKIL clock period delay */ #define GPC_SLPCR_REG_BYPASS_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_REG_BYPASS_COUNT_SHIFT)) & GPC_SLPCR_REG_BYPASS_COUNT_MASK) #define GPC_SLPCR_RBC_EN_MASK (0x40000000U) #define GPC_SLPCR_RBC_EN_SHIFT (30U) /*! RBC_EN * 0b0..REG_BYPASS_COUNTER disabled * 0b1..REG_BYPASS_COUNTER enabled */ #define GPC_SLPCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_RBC_EN_SHIFT)) & GPC_SLPCR_RBC_EN_MASK) #define GPC_SLPCR_EN_DSM_MASK (0x80000000U) #define GPC_SLPCR_EN_DSM_SHIFT (31U) /*! EN_DSM * 0b0..DSM disabled * 0b1..DSM enabled */ #define GPC_SLPCR_EN_DSM(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_DSM_SHIFT)) & GPC_SLPCR_EN_DSM_MASK) /*! @} */ /*! @name MST_CPU_MAPPING - MASTER LPM Handshake */ /*! @{ */ #define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_MASK (0x1U) #define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_SHIFT (0U) /*! MST0_CPU_MAPPING - MASTER0 CPU Mapping * 0b0..GPC will not send out power off requirement * 0b1..GPC will send out power off requirement */ #define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_SHIFT)) & \ GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_MASK) #define GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING_MASK (0x2U) #define GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING_SHIFT (1U) /*! MST1_CPU_MAPPING - MASTER0 CPU Mapping * 0b0..GPC will not send out power off requirement * 0b1..GPC will send out power off requirement */ #define GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING_SHIFT)) & \ GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING_MASK) #define GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING_MASK (0x4U) #define GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING_SHIFT (2U) /*! MST2_CPU_MAPPING - MASTER2 CPU Mapping * 0b0..GPC will not send out power off requirement * 0b1..GPC will send out power off requirement */ #define GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING_SHIFT)) & \ GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING_MASK) #define GPC_MST_CPU_MAPPING_MST3_CPU_MAPPING_MASK (0x8U) #define GPC_MST_CPU_MAPPING_MST3_CPU_MAPPING_SHIFT (3U) /*! MST3_CPU_MAPPING - MASTER3 CPU Mapping * 0b0..GPC will not send out power off requirement * 0b1..GPC will send out power off requirement */ #define GPC_MST_CPU_MAPPING_MST3_CPU_MAPPING(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST3_CPU_MAPPING_SHIFT)) & \ GPC_MST_CPU_MAPPING_MST3_CPU_MAPPING_MASK) #define GPC_MST_CPU_MAPPING_MST4_CPU_MAPPING_MASK (0x10U) #define GPC_MST_CPU_MAPPING_MST4_CPU_MAPPING_SHIFT (4U) /*! MST4_CPU_MAPPING - MASTER4 CPU Mapping * 0b0..GPC will not send out power off requirement * 0b1..GPC will send out power off requirement */ #define GPC_MST_CPU_MAPPING_MST4_CPU_MAPPING(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST4_CPU_MAPPING_SHIFT)) & \ GPC_MST_CPU_MAPPING_MST4_CPU_MAPPING_MASK) /*! @} */ /*! @name MLPCR - Memory low power control register */ /*! @{ */ #define GPC_MLPCR_MEMLP_CTL_DIS_MASK (0x1U) #define GPC_MLPCR_MEMLP_CTL_DIS_SHIFT (0U) /*! MEMLP_CTL_DIS * 0b0..Enable RAM low power control * 0b1..Disable RAM low power control */ #define GPC_MLPCR_MEMLP_CTL_DIS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_CTL_DIS_SHIFT)) & GPC_MLPCR_MEMLP_CTL_DIS_MASK) #define GPC_MLPCR_MEMLP_RET_SEL_MASK (0x2U) #define GPC_MLPCR_MEMLP_RET_SEL_SHIFT (1U) /*! MEMLP_RET_SEL * 0b0..retention mode 2 * 0b1..retention mode 1 */ #define GPC_MLPCR_MEMLP_RET_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_RET_SEL_SHIFT)) & GPC_MLPCR_MEMLP_RET_SEL_MASK) #define GPC_MLPCR_ROMLP_PDN_DIS_MASK (0x4U) #define GPC_MLPCR_ROMLP_PDN_DIS_SHIFT (2U) /*! ROMLP_PDN_DIS * 0b0..Enable ROM shut down control(should also enable RAM low power control); * 0b1..Disable ROM shut down control */ #define GPC_MLPCR_ROMLP_PDN_DIS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_ROMLP_PDN_DIS_SHIFT)) & GPC_MLPCR_ROMLP_PDN_DIS_MASK) #define GPC_MLPCR_MEMLP_ENT_CNT_MASK (0xFF00U) #define GPC_MLPCR_MEMLP_ENT_CNT_SHIFT (8U) #define GPC_MLPCR_MEMLP_ENT_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_ENT_CNT_SHIFT)) & GPC_MLPCR_MEMLP_ENT_CNT_MASK) #define GPC_MLPCR_MEM_EXT_CNT_MASK (0xFF0000U) #define GPC_MLPCR_MEM_EXT_CNT_SHIFT (16U) #define GPC_MLPCR_MEM_EXT_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEM_EXT_CNT_SHIFT)) & GPC_MLPCR_MEM_EXT_CNT_MASK) #define GPC_MLPCR_MEMLP_RET_PGEN_MASK (0xFF000000U) #define GPC_MLPCR_MEMLP_RET_PGEN_SHIFT (24U) #define GPC_MLPCR_MEMLP_RET_PGEN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_RET_PGEN_SHIFT)) & GPC_MLPCR_MEMLP_RET_PGEN_MASK) /*! @} */ /*! @name PGC_ACK_SEL_A53 - PGC acknowledge signal selection of A53 platform */ /*! @{ */ #define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_MASK (0x1U) #define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_SHIFT (0U) #define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_MASK) #define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_MASK (0x2U) #define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_SHIFT (1U) #define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_MASK) #define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_MASK (0x4U) #define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_SHIFT (2U) #define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_MASK) #define GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK_MASK (0x8U) #define GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK_SHIFT (3U) #define GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK_MASK) #define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_MASK (0x2000U) #define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_SHIFT (13U) #define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_MASK) #define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_MASK (0x4000U) #define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_SHIFT (14U) #define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_MASK) #define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_MASK (0x8000U) #define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_SHIFT (15U) #define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_MASK) #define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_MASK (0x10000U) #define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_SHIFT (16U) #define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_MASK) #define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_MASK (0x20000U) #define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_SHIFT (17U) #define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_MASK) #define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_MASK (0x40000U) #define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_SHIFT (18U) #define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_MASK) #define GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK_MASK (0x80000U) #define GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK_SHIFT (19U) #define GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK_MASK) #define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_MASK (0x20000000U) #define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_SHIFT (29U) #define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_MASK) #define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_MASK (0x40000000U) #define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_SHIFT (30U) #define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_MASK) #define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_MASK (0x80000000U) #define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_SHIFT (31U) #define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_MASK) /*! @} */ /*! @name PGC_ACK_SEL_M7 - PGC acknowledge signal selection of M7 platform */ /*! @{ */ #define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK_MASK (0x1U) #define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK_SHIFT (0U) #define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK_MASK) #define GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK_MASK (0x2U) #define GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK_SHIFT (1U) #define GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK_MASK) #define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK_MASK (0x8000U) #define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK_SHIFT (15U) #define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK_MASK) #define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK_MASK (0x10000U) #define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK_SHIFT (16U) #define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK_MASK) #define GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK_MASK (0x20000U) #define GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK_SHIFT (17U) #define GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK_MASK) #define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK_MASK (0x80000000U) #define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK_SHIFT (31U) #define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK_SHIFT)) & \ GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK_MASK) /*! @} */ /*! @name MISC - GPC Miscellaneous register */ /*! @{ */ #define GPC_MISC_M7_SLEEP_HOLD_REQ_B_MASK (0x1U) #define GPC_MISC_M7_SLEEP_HOLD_REQ_B_SHIFT (0U) /*! M7_SLEEP_HOLD_REQ_B * 0b0..Hold M7 platform in sleep mode. This bit is a software control bit to M7 platform. * 0b1..Don't hold M7 platform in sleep mode. */ #define GPC_MISC_M7_SLEEP_HOLD_REQ_B(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M7_SLEEP_HOLD_REQ_B_SHIFT)) & GPC_MISC_M7_SLEEP_HOLD_REQ_B_MASK) #define GPC_MISC_A53_SLEEP_HOLD_REQ_B_MASK (0x2U) #define GPC_MISC_A53_SLEEP_HOLD_REQ_B_SHIFT (1U) /*! A53_SLEEP_HOLD_REQ_B * 0b0..Hold A53 platform in sleep mode. This bit is a software control bit to A53 platform. * 0b1..Don't hold A53 platform in sleep mode. */ #define GPC_MISC_A53_SLEEP_HOLD_REQ_B(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MISC_A53_SLEEP_HOLD_REQ_B_SHIFT)) & GPC_MISC_A53_SLEEP_HOLD_REQ_B_MASK) #define GPC_MISC_GPC_IRQ_MASK_MASK (0x20U) #define GPC_MISC_GPC_IRQ_MASK_SHIFT (5U) /*! GPC_IRQ_MASK * 0b0..Not masked * 0b1..Interrupt / event is masked */ #define GPC_MISC_GPC_IRQ_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MISC_GPC_IRQ_MASK_SHIFT)) & GPC_MISC_GPC_IRQ_MASK_MASK) #define GPC_MISC_M7_PDN_REQ_MASK_MASK (0x100U) #define GPC_MISC_M7_PDN_REQ_MASK_SHIFT (8U) /*! M7_PDN_REQ_MASK * 0b0..M7 power down request to virtual M7 PGC will be masked. * 0b1..M7 power down request to virtual M7 PGC will not be masked. Set this bit to 1'b1 when M7 virtual PGC is used. */ #define GPC_MISC_M7_PDN_REQ_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M7_PDN_REQ_MASK_SHIFT)) & GPC_MISC_M7_PDN_REQ_MASK_MASK) #define GPC_MISC_A53_BYPASS_PUP_MASK_MASK (0x1000000U) #define GPC_MISC_A53_BYPASS_PUP_MASK_SHIFT (24U) #define GPC_MISC_A53_BYPASS_PUP_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MISC_A53_BYPASS_PUP_MASK_SHIFT)) & GPC_MISC_A53_BYPASS_PUP_MASK_MASK) #define GPC_MISC_M7_BYPASS_PUP_MASK_MASK (0x2000000U) #define GPC_MISC_M7_BYPASS_PUP_MASK_SHIFT (25U) #define GPC_MISC_M7_BYPASS_PUP_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M7_BYPASS_PUP_MASK_SHIFT)) & GPC_MISC_M7_BYPASS_PUP_MASK_MASK) /*! @} */ /*! @name IMR_CORE0_A53 - IRQ masking register 1 of A53 core0..IRQ masking register 4 of A53 core0 */ /*! @{ */ #define GPC_IMR_CORE0_A53_IMR1_CORE0_A53_MASK (0xFFFFFFFFU) #define GPC_IMR_CORE0_A53_IMR1_CORE0_A53_SHIFT (0U) /*! IMR1_CORE0_A53 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_CORE0_A53_IMR1_CORE0_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR1_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR1_CORE0_A53_MASK) #define GPC_IMR_CORE0_A53_IMR2_CORE0_A53_MASK (0xFFFFFFFFU) #define GPC_IMR_CORE0_A53_IMR2_CORE0_A53_SHIFT (0U) /*! IMR2_CORE0_A53 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_CORE0_A53_IMR2_CORE0_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR2_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR2_CORE0_A53_MASK) #define GPC_IMR_CORE0_A53_IMR3_CORE0_A53_MASK (0xFFFFFFFFU) #define GPC_IMR_CORE0_A53_IMR3_CORE0_A53_SHIFT (0U) /*! IMR3_CORE0_A53 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_CORE0_A53_IMR3_CORE0_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR3_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR3_CORE0_A53_MASK) #define GPC_IMR_CORE0_A53_IMR4_CORE0_A53_MASK (0xFFFFFFFFU) #define GPC_IMR_CORE0_A53_IMR4_CORE0_A53_SHIFT (0U) /*! IMR4_CORE0_A53 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_CORE0_A53_IMR4_CORE0_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR4_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR4_CORE0_A53_MASK) /*! @} */ /* The count of GPC_IMR_CORE0_A53 */ #define GPC_IMR_CORE0_A53_COUNT (4U) /*! @name IMR_CORE1_A53 - IRQ masking register 1 of A53 core1..IRQ masking register 4 of A53 core1 */ /*! @{ */ #define GPC_IMR_CORE1_A53_IMR1_CORE1_A53_MASK (0xFFFFFFFFU) #define GPC_IMR_CORE1_A53_IMR1_CORE1_A53_SHIFT (0U) /*! IMR1_CORE1_A53 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_CORE1_A53_IMR1_CORE1_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR1_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR1_CORE1_A53_MASK) #define GPC_IMR_CORE1_A53_IMR2_CORE1_A53_MASK (0xFFFFFFFFU) #define GPC_IMR_CORE1_A53_IMR2_CORE1_A53_SHIFT (0U) /*! IMR2_CORE1_A53 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_CORE1_A53_IMR2_CORE1_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR2_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR2_CORE1_A53_MASK) #define GPC_IMR_CORE1_A53_IMR3_CORE1_A53_MASK (0xFFFFFFFFU) #define GPC_IMR_CORE1_A53_IMR3_CORE1_A53_SHIFT (0U) /*! IMR3_CORE1_A53 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_CORE1_A53_IMR3_CORE1_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR3_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR3_CORE1_A53_MASK) #define GPC_IMR_CORE1_A53_IMR4_CORE1_A53_MASK (0xFFFFFFFFU) #define GPC_IMR_CORE1_A53_IMR4_CORE1_A53_SHIFT (0U) /*! IMR4_CORE1_A53 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_CORE1_A53_IMR4_CORE1_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR4_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR4_CORE1_A53_MASK) /*! @} */ /* The count of GPC_IMR_CORE1_A53 */ #define GPC_IMR_CORE1_A53_COUNT (4U) /*! @name IMR_M7 - IRQ masking register 1 of M7..IRQ masking register 4 of M7 */ /*! @{ */ #define GPC_IMR_M7_IMR1_M7_MASK (0xFFFFFFFFU) #define GPC_IMR_M7_IMR1_M7_SHIFT (0U) /*! IMR1_M7 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_M7_IMR1_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M7_IMR1_M7_SHIFT)) & GPC_IMR_M7_IMR1_M7_MASK) #define GPC_IMR_M7_IMR2_M7_MASK (0xFFFFFFFFU) #define GPC_IMR_M7_IMR2_M7_SHIFT (0U) /*! IMR2_M7 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_M7_IMR2_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M7_IMR2_M7_SHIFT)) & GPC_IMR_M7_IMR2_M7_MASK) #define GPC_IMR_M7_IMR3_M7_MASK (0xFFFFFFFFU) #define GPC_IMR_M7_IMR3_M7_SHIFT (0U) /*! IMR3_M7 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_M7_IMR3_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M7_IMR3_M7_SHIFT)) & GPC_IMR_M7_IMR3_M7_MASK) #define GPC_IMR_M7_IMR4_M7_MASK (0xFFFFFFFFU) #define GPC_IMR_M7_IMR4_M7_SHIFT (0U) /*! IMR4_M7 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_M7_IMR4_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M7_IMR4_M7_SHIFT)) & GPC_IMR_M7_IMR4_M7_MASK) /*! @} */ /* The count of GPC_IMR_M7 */ #define GPC_IMR_M7_COUNT (4U) /*! @name ISR_A53 - IRQ status register 1 of A53..IRQ status register 4 of A53 */ /*! @{ */ #define GPC_ISR_A53_ISR1_A53_MASK (0xFFFFFFFFU) #define GPC_ISR_A53_ISR1_A53_SHIFT (0U) #define GPC_ISR_A53_ISR1_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR1_A53_SHIFT)) & GPC_ISR_A53_ISR1_A53_MASK) #define GPC_ISR_A53_ISR2_A53_MASK (0xFFFFFFFFU) #define GPC_ISR_A53_ISR2_A53_SHIFT (0U) #define GPC_ISR_A53_ISR2_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR2_A53_SHIFT)) & GPC_ISR_A53_ISR2_A53_MASK) #define GPC_ISR_A53_ISR3_A53_MASK (0xFFFFFFFFU) #define GPC_ISR_A53_ISR3_A53_SHIFT (0U) #define GPC_ISR_A53_ISR3_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR3_A53_SHIFT)) & GPC_ISR_A53_ISR3_A53_MASK) #define GPC_ISR_A53_ISR4_A53_MASK (0xFFFFFFFFU) #define GPC_ISR_A53_ISR4_A53_SHIFT (0U) #define GPC_ISR_A53_ISR4_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR4_A53_SHIFT)) & GPC_ISR_A53_ISR4_A53_MASK) /*! @} */ /* The count of GPC_ISR_A53 */ #define GPC_ISR_A53_COUNT (4U) /*! @name ISR_M7 - IRQ status register 1 of M7..IRQ status register 4 of M7 */ /*! @{ */ #define GPC_ISR_M7_ISR1_M7_MASK (0xFFFFFFFFU) #define GPC_ISR_M7_ISR1_M7_SHIFT (0U) #define GPC_ISR_M7_ISR1_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M7_ISR1_M7_SHIFT)) & GPC_ISR_M7_ISR1_M7_MASK) #define GPC_ISR_M7_ISR2_M7_MASK (0xFFFFFFFFU) #define GPC_ISR_M7_ISR2_M7_SHIFT (0U) #define GPC_ISR_M7_ISR2_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M7_ISR2_M7_SHIFT)) & GPC_ISR_M7_ISR2_M7_MASK) #define GPC_ISR_M7_ISR3_M7_MASK (0xFFFFFFFFU) #define GPC_ISR_M7_ISR3_M7_SHIFT (0U) #define GPC_ISR_M7_ISR3_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M7_ISR3_M7_SHIFT)) & GPC_ISR_M7_ISR3_M7_MASK) #define GPC_ISR_M7_ISR4_M7_MASK (0xFFFFFFFFU) #define GPC_ISR_M7_ISR4_M7_SHIFT (0U) #define GPC_ISR_M7_ISR4_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M7_ISR4_M7_SHIFT)) & GPC_ISR_M7_ISR4_M7_MASK) /*! @} */ /* The count of GPC_ISR_M7 */ #define GPC_ISR_M7_COUNT (4U) /*! @name SLT0_CFG - Slot configure register for CPUs */ /*! @{ */ #define GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT0_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT0_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT0_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT0_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT0_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT0_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name SLT1_CFG - Slot configure register for CPUs */ /*! @{ */ #define GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT1_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT1_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT1_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT1_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT1_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT1_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name SLT2_CFG - Slot configure register for CPUs */ /*! @{ */ #define GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT2_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT2_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT2_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT2_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT2_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT2_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name SLT3_CFG - Slot configure register for CPUs */ /*! @{ */ #define GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT3_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT3_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT3_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT3_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT3_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT3_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name SLT4_CFG - Slot configure register for CPUs */ /*! @{ */ #define GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT4_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT4_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT4_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT4_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT4_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT4_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name SLT5_CFG - Slot configure register for CPUs */ /*! @{ */ #define GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT5_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT5_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT5_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT5_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT5_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT5_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name SLT6_CFG - Slot configure register for CPUs */ /*! @{ */ #define GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT6_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT6_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT6_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT6_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT6_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT6_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name SLT7_CFG - Slot configure register for CPUs */ /*! @{ */ #define GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT7_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT7_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT7_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT7_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT7_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT7_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name SLT8_CFG - Slot configure register for CPUs */ /*! @{ */ #define GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT8_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT8_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT8_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT8_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT8_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT8_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name SLT9_CFG - Slot configure register for CPUs */ /*! @{ */ #define GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT9_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT9_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT9_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT9_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT9_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT9_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name SLT10_CFG - Slot configure register for CPUs */ /*! @{ */ #define GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT10_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT10_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT10_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT10_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT10_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT10_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT10_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT10_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name SLT11_CFG - Slot configure register for CPUs */ /*! @{ */ #define GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT11_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT11_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT11_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT11_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT11_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT11_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT11_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT11_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name SLT12_CFG - Slot configure register for CPUs */ /*! @{ */ #define GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT12_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT12_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT12_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT12_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT12_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT12_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT12_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT12_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name SLT13_CFG - Slot configure register for CPUs */ /*! @{ */ #define GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT13_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT13_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT13_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT13_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT13_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT13_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT13_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT13_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name SLT14_CFG - Slot configure register for CPUs */ /*! @{ */ #define GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT14_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT14_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT14_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT14_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT14_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT14_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT14_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT14_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name PGC_CPU_0_1_MAPPING - PGC CPU mapping */ /*! @{ */ #define GPC_PGC_CPU_0_1_MAPPING_NOC_A53_DOMAIN_MASK (0x2U) #define GPC_PGC_CPU_0_1_MAPPING_NOC_A53_DOMAIN_SHIFT (1U) #define GPC_PGC_CPU_0_1_MAPPING_NOC_A53_DOMAIN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_NOC_A53_DOMAIN_SHIFT)) & \ GPC_PGC_CPU_0_1_MAPPING_NOC_A53_DOMAIN_MASK) #define GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_MASK (0x4U) #define GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_SHIFT (2U) #define GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_SHIFT)) & \ GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_MASK) #define GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_MASK (0x10U) #define GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_SHIFT (4U) #define GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_SHIFT)) & \ GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_MASK) #define GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_MASK (0x80U) #define GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_SHIFT (7U) #define GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_SHIFT)) & \ GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_MASK) #define GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_MASK (0x200U) #define GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_SHIFT (9U) #define GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_SHIFT)) & \ GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_MASK) #define GPC_PGC_CPU_0_1_MAPPING_DISPMIX_A53_DOMAIN_MASK (0x1000U) #define GPC_PGC_CPU_0_1_MAPPING_DISPMIX_A53_DOMAIN_SHIFT (12U) #define GPC_PGC_CPU_0_1_MAPPING_DISPMIX_A53_DOMAIN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DISPMIX_A53_DOMAIN_SHIFT)) & \ GPC_PGC_CPU_0_1_MAPPING_DISPMIX_A53_DOMAIN_MASK) #define GPC_PGC_CPU_0_1_MAPPING_NOC_M7_DOMAIN_MASK (0x20000U) #define GPC_PGC_CPU_0_1_MAPPING_NOC_M7_DOMAIN_SHIFT (17U) #define GPC_PGC_CPU_0_1_MAPPING_NOC_M7_DOMAIN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_NOC_M7_DOMAIN_SHIFT)) & \ GPC_PGC_CPU_0_1_MAPPING_NOC_M7_DOMAIN_MASK) #define GPC_PGC_CPU_0_1_MAPPING_MIPI_M7_DOMAIN_MASK (0x40000U) #define GPC_PGC_CPU_0_1_MAPPING_MIPI_M7_DOMAIN_SHIFT (18U) #define GPC_PGC_CPU_0_1_MAPPING_MIPI_M7_DOMAIN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_M7_DOMAIN_SHIFT)) & \ GPC_PGC_CPU_0_1_MAPPING_MIPI_M7_DOMAIN_MASK) #define GPC_PGC_CPU_0_1_MAPPING_OTG1_M7_DOMAIN_MASK (0x100000U) #define GPC_PGC_CPU_0_1_MAPPING_OTG1_M7_DOMAIN_SHIFT (20U) #define GPC_PGC_CPU_0_1_MAPPING_OTG1_M7_DOMAIN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_OTG1_M7_DOMAIN_SHIFT)) & \ GPC_PGC_CPU_0_1_MAPPING_OTG1_M7_DOMAIN_MASK) #define GPC_PGC_CPU_0_1_MAPPING_DDR1_M7_DOMAIN_MASK (0x800000U) #define GPC_PGC_CPU_0_1_MAPPING_DDR1_M7_DOMAIN_SHIFT (23U) #define GPC_PGC_CPU_0_1_MAPPING_DDR1_M7_DOMAIN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DDR1_M7_DOMAIN_SHIFT)) & \ GPC_PGC_CPU_0_1_MAPPING_DDR1_M7_DOMAIN_MASK) #define GPC_PGC_CPU_0_1_MAPPING_GPUMIX_M7_DOMAIN_MASK (0x2000000U) #define GPC_PGC_CPU_0_1_MAPPING_GPUMIX_M7_DOMAIN_SHIFT (25U) #define GPC_PGC_CPU_0_1_MAPPING_GPUMIX_M7_DOMAIN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_GPUMIX_M7_DOMAIN_SHIFT)) & \ GPC_PGC_CPU_0_1_MAPPING_GPUMIX_M7_DOMAIN_MASK) #define GPC_PGC_CPU_0_1_MAPPING_DISPMIX_M7_DOMAIN_MASK (0x10000000U) #define GPC_PGC_CPU_0_1_MAPPING_DISPMIX_M7_DOMAIN_SHIFT (28U) #define GPC_PGC_CPU_0_1_MAPPING_DISPMIX_M7_DOMAIN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DISPMIX_M7_DOMAIN_SHIFT)) & \ GPC_PGC_CPU_0_1_MAPPING_DISPMIX_M7_DOMAIN_MASK) /*! @} */ /*! @name CPU_PGC_SW_PUP_REQ - CPU PGC software power up trigger */ /*! @{ */ #define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_MASK (0x1U) #define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_SHIFT (0U) #define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_SHIFT)) & \ GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_MASK) #define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_MASK (0x2U) #define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_SHIFT (1U) #define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_SHIFT)) & \ GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_MASK) #define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_MASK (0x4U) #define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_SHIFT (2U) #define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_SHIFT)) & \ GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_MASK) #define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_MASK (0x8U) #define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_SHIFT (3U) #define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_SHIFT)) & \ GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_MASK) #define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_MASK (0x10U) #define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_SHIFT (4U) #define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_SHIFT)) & \ GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_MASK) /*! @} */ /*! @name MIX_PGC_SW_PUP_REQ - MIX PGC software power up trigger */ /*! @{ */ #define GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ_MASK (0x2U) #define GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ_SHIFT (1U) #define GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ_SHIFT)) & \ GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ_MASK) /*! @} */ /*! @name PU_PGC_SW_PUP_REQ - PU PGC software up trigger */ /*! @{ */ #define GPC_PU_PGC_SW_PUP_REQ_MIPI_DSI_SW_PUP_REQ_MASK (0x1U) #define GPC_PU_PGC_SW_PUP_REQ_MIPI_DSI_SW_PUP_REQ_SHIFT (0U) #define GPC_PU_PGC_SW_PUP_REQ_MIPI_DSI_SW_PUP_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MIPI_DSI_SW_PUP_REQ_SHIFT)) & \ GPC_PU_PGC_SW_PUP_REQ_MIPI_DSI_SW_PUP_REQ_MASK) #define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_MASK (0x4U) #define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_SHIFT (2U) #define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_SHIFT)) & \ GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_MASK) #define GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_MASK (0x20U) #define GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_SHIFT (5U) #define GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_SHIFT)) & \ GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_MASK) #define GPC_PU_PGC_SW_PUP_REQ_GPUMIX_SW_PUP_REQ_MASK (0x80U) #define GPC_PU_PGC_SW_PUP_REQ_GPUMIX_SW_PUP_REQ_SHIFT (7U) #define GPC_PU_PGC_SW_PUP_REQ_GPUMIX_SW_PUP_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_GPUMIX_SW_PUP_REQ_SHIFT)) & \ GPC_PU_PGC_SW_PUP_REQ_GPUMIX_SW_PUP_REQ_MASK) #define GPC_PU_PGC_SW_PUP_REQ_DISPMIX_SW_PUP_REQ_MASK (0x400U) #define GPC_PU_PGC_SW_PUP_REQ_DISPMIX_SW_PUP_REQ_SHIFT (10U) #define GPC_PU_PGC_SW_PUP_REQ_DISPMIX_SW_PUP_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_DISPMIX_SW_PUP_REQ_SHIFT)) & \ GPC_PU_PGC_SW_PUP_REQ_DISPMIX_SW_PUP_REQ_MASK) /*! @} */ /*! @name CPU_PGC_SW_PDN_REQ - CPU PGC software down trigger */ /*! @{ */ #define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_MASK (0x1U) #define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_SHIFT (0U) #define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_SHIFT)) & \ GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_MASK) #define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_MASK (0x2U) #define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_SHIFT (1U) #define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_SHIFT)) & \ GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_MASK) #define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ_MASK (0x4U) #define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ_SHIFT (2U) #define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ_SHIFT)) & \ GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ_MASK) #define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_MASK (0x8U) #define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_SHIFT (3U) #define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_SHIFT)) & \ GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_MASK) #define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ_MASK (0x10U) #define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ_SHIFT (4U) #define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ_SHIFT)) & \ GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ_MASK) /*! @} */ /*! @name MIX_PGC_SW_PDN_REQ - MIX PGC software power down trigger */ /*! @{ */ #define GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ_MASK (0x2U) #define GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ_SHIFT (1U) #define GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ_SHIFT)) & \ GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ_MASK) /*! @} */ /*! @name PU_PGC_SW_PDN_REQ - PU PGC software down trigger */ /*! @{ */ #define GPC_PU_PGC_SW_PDN_REQ_MIPI_DSI_SW_PDN_REQ_MASK (0x1U) #define GPC_PU_PGC_SW_PDN_REQ_MIPI_DSI_SW_PDN_REQ_SHIFT (0U) #define GPC_PU_PGC_SW_PDN_REQ_MIPI_DSI_SW_PDN_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MIPI_DSI_SW_PDN_REQ_SHIFT)) & \ GPC_PU_PGC_SW_PDN_REQ_MIPI_DSI_SW_PDN_REQ_MASK) #define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_MASK (0x4U) #define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_SHIFT (2U) #define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_SHIFT)) & \ GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_MASK) #define GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_MASK (0x20U) #define GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_SHIFT (5U) #define GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_SHIFT)) & \ GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_MASK) #define GPC_PU_PGC_SW_PDN_REQ_GPUMIX_SW_PDN_REQ_MASK (0x80U) #define GPC_PU_PGC_SW_PDN_REQ_GPUMIX_SW_PDN_REQ_SHIFT (7U) #define GPC_PU_PGC_SW_PDN_REQ_GPUMIX_SW_PDN_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_GPUMIX_SW_PDN_REQ_SHIFT)) & \ GPC_PU_PGC_SW_PDN_REQ_GPUMIX_SW_PDN_REQ_MASK) #define GPC_PU_PGC_SW_PDN_REQ_DISPMIX_SW_PDN_REQ_MASK (0x400U) #define GPC_PU_PGC_SW_PDN_REQ_DISPMIX_SW_PDN_REQ_SHIFT (10U) #define GPC_PU_PGC_SW_PDN_REQ_DISPMIX_SW_PDN_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_DISPMIX_SW_PDN_REQ_SHIFT)) & \ GPC_PU_PGC_SW_PDN_REQ_DISPMIX_SW_PDN_REQ_MASK) /*! @} */ /*! @name LPCR_A53_BSC2 - Basic Low power control register of A53 platform */ /*! @{ */ #define GPC_LPCR_A53_BSC2_LPM2_MASK (0x3U) #define GPC_LPCR_A53_BSC2_LPM2_SHIFT (0U) /*! LPM2 * 0b00..Remain in RUN mode * 0b01..Transfer to WAIT mode * 0b10..Transfer to STOP mode * 0b11..Reserved */ #define GPC_LPCR_A53_BSC2_LPM2(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC2_LPM2_SHIFT)) & GPC_LPCR_A53_BSC2_LPM2_MASK) #define GPC_LPCR_A53_BSC2_LPM3_MASK (0xCU) #define GPC_LPCR_A53_BSC2_LPM3_SHIFT (2U) /*! LPM3 * 0b00..Remain in RUN mode * 0b01..Transfer to WAIT mode * 0b10..Transfer to STOP mode * 0b11..Reserved */ #define GPC_LPCR_A53_BSC2_LPM3(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC2_LPM3_SHIFT)) & GPC_LPCR_A53_BSC2_LPM3_MASK) /*! @} */ /*! @name CPU_PGC_PUP_STATUS1 - CPU PGC software up trigger status1 */ /*! @{ */ #define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_MASK (0x1U) #define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_SHIFT (0U) #define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_SHIFT)) & \ GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_MASK) #define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_MASK (0x2U) #define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_SHIFT (1U) #define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_SHIFT)) & \ GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_MASK) #define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_MASK (0x4U) #define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_SHIFT (2U) #define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_SHIFT)) & \ GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_MASK) #define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS_MASK (0x8U) #define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS_SHIFT (3U) #define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS_SHIFT)) & \ GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS_MASK) #define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ_MASK (0x10U) #define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ_SHIFT (4U) #define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ_SHIFT)) & \ GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ_MASK) /*! @} */ /*! @name A53_MIX_PGC_PUP_STATUS - A53 MIX software up trigger status register */ /*! @{ */ #define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_MASK (0x1U) #define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_SHIFT (0U) #define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_SHIFT)) & \ GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_MASK) /*! @} */ /* The count of GPC_A53_MIX_PGC_PUP_STATUS */ #define GPC_A53_MIX_PGC_PUP_STATUS_COUNT (3U) /*! @name M7_MIX_PGC_PUP_STATUS - M7 MIX PGC software up trigger status register */ /*! @{ */ #define GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS_MASK (0x1U) #define GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS_SHIFT (0U) #define GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS_SHIFT)) & \ GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS_MASK) /*! @} */ /* The count of GPC_M7_MIX_PGC_PUP_STATUS */ #define GPC_M7_MIX_PGC_PUP_STATUS_COUNT (3U) /*! @name A53_PU_PGC_PUP_STATUS - A53 PU software up trigger status register */ /*! @{ */ #define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY_PUP_STATUS_MASK (0x1U) #define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY_PUP_STATUS_SHIFT (0U) #define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY_PUP_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY_PUP_STATUS_SHIFT)) & \ GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY_PUP_STATUS_MASK) #define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_MASK (0x4U) #define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_SHIFT (2U) #define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_SHIFT)) & \ GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_MASK) #define GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_MASK (0x20U) #define GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_SHIFT (5U) #define GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_SHIFT)) & \ GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_MASK) #define GPC_A53_PU_PGC_PUP_STATUS_A53_GPUMIX_PUP_STATUS_MASK (0x80U) #define GPC_A53_PU_PGC_PUP_STATUS_A53_GPUMIX_PUP_STATUS_SHIFT (7U) #define GPC_A53_PU_PGC_PUP_STATUS_A53_GPUMIX_PUP_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_GPUMIX_PUP_STATUS_SHIFT)) & \ GPC_A53_PU_PGC_PUP_STATUS_A53_GPUMIX_PUP_STATUS_MASK) #define GPC_A53_PU_PGC_PUP_STATUS_A53_DISPMIX_PUP_STATUS_MASK (0x400U) #define GPC_A53_PU_PGC_PUP_STATUS_A53_DISPMIX_PUP_STATUS_SHIFT (10U) #define GPC_A53_PU_PGC_PUP_STATUS_A53_DISPMIX_PUP_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_DISPMIX_PUP_STATUS_SHIFT)) & \ GPC_A53_PU_PGC_PUP_STATUS_A53_DISPMIX_PUP_STATUS_MASK) /*! @} */ /* The count of GPC_A53_PU_PGC_PUP_STATUS */ #define GPC_A53_PU_PGC_PUP_STATUS_COUNT (3U) /*! @name M7_PU_PGC_PUP_STATUS - M7 PU PGC software up trigger status register */ /*! @{ */ #define GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY_PUP_STATUS_MASK (0x1U) #define GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY_PUP_STATUS_SHIFT (0U) #define GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY_PUP_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY_PUP_STATUS_SHIFT)) & \ GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY_PUP_STATUS_MASK) #define GPC_M7_PU_PGC_PUP_STATUS_M7_OTG1_PUP_STATUS_MASK (0x4U) #define GPC_M7_PU_PGC_PUP_STATUS_M7_OTG1_PUP_STATUS_SHIFT (2U) #define GPC_M7_PU_PGC_PUP_STATUS_M7_OTG1_PUP_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_OTG1_PUP_STATUS_SHIFT)) & \ GPC_M7_PU_PGC_PUP_STATUS_M7_OTG1_PUP_STATUS_MASK) #define GPC_M7_PU_PGC_PUP_STATUS_M7_DDR1_PUP_STATUS_MASK (0x20U) #define GPC_M7_PU_PGC_PUP_STATUS_M7_DDR1_PUP_STATUS_SHIFT (5U) #define GPC_M7_PU_PGC_PUP_STATUS_M7_DDR1_PUP_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_DDR1_PUP_STATUS_SHIFT)) & \ GPC_M7_PU_PGC_PUP_STATUS_M7_DDR1_PUP_STATUS_MASK) #define GPC_M7_PU_PGC_PUP_STATUS_M7_GPUMIX_PUP_STATUS_MASK (0x80U) #define GPC_M7_PU_PGC_PUP_STATUS_M7_GPUMIX_PUP_STATUS_SHIFT (7U) #define GPC_M7_PU_PGC_PUP_STATUS_M7_GPUMIX_PUP_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_GPUMIX_PUP_STATUS_SHIFT)) & \ GPC_M7_PU_PGC_PUP_STATUS_M7_GPUMIX_PUP_STATUS_MASK) #define GPC_M7_PU_PGC_PUP_STATUS_M7_DISPMIX_PUP_STATUS_MASK (0x400U) #define GPC_M7_PU_PGC_PUP_STATUS_M7_DISPMIX_PUP_STATUS_SHIFT (10U) #define GPC_M7_PU_PGC_PUP_STATUS_M7_DISPMIX_PUP_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_DISPMIX_PUP_STATUS_SHIFT)) & \ GPC_M7_PU_PGC_PUP_STATUS_M7_DISPMIX_PUP_STATUS_MASK) /*! @} */ /* The count of GPC_M7_PU_PGC_PUP_STATUS */ #define GPC_M7_PU_PGC_PUP_STATUS_COUNT (3U) /*! @name CPU_PGC_PDN_STATUS1 - CPU PGC software dn trigger status1 */ /*! @{ */ #define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_MASK (0x1U) #define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_SHIFT (0U) #define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_SHIFT)) & \ GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_MASK) #define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_MASK (0x2U) #define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_SHIFT (1U) #define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_SHIFT)) & \ GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_MASK) #define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_MASK (0x4U) #define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_SHIFT (2U) #define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_SHIFT)) & \ GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_MASK) #define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS_MASK (0x8U) #define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS_SHIFT (3U) #define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS_SHIFT)) & \ GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS_MASK) #define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ_MASK (0x10U) #define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ_SHIFT (4U) #define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ_SHIFT)) & \ GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ_MASK) /*! @} */ /*! @name A53_MIX_PGC_PDN_STATUS - A53 MIX software down trigger status register */ /*! @{ */ #define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_MASK (0x1U) #define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_SHIFT (0U) #define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_SHIFT)) & \ GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_MASK) /*! @} */ /* The count of GPC_A53_MIX_PGC_PDN_STATUS */ #define GPC_A53_MIX_PGC_PDN_STATUS_COUNT (3U) /*! @name M7_MIX_PGC_PDN_STATUS - M7 MIX PGC software power down trigger status register */ /*! @{ */ #define GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS_MASK (0x1U) #define GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS_SHIFT (0U) #define GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS_SHIFT)) & \ GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS_MASK) /*! @} */ /* The count of GPC_M7_MIX_PGC_PDN_STATUS */ #define GPC_M7_MIX_PGC_PDN_STATUS_COUNT (3U) /*! @name A53_PU_PGC_PDN_STATUS - A53 PU PGC software down trigger status */ /*! @{ */ #define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY_PDN_STATUS_MASK (0x1U) #define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY_PDN_STATUS_SHIFT (0U) #define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY_PDN_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY_PDN_STATUS_SHIFT)) & \ GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY_PDN_STATUS_MASK) #define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_MASK (0x4U) #define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_SHIFT (2U) #define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_SHIFT)) & \ GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_MASK) #define GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_MASK (0x20U) #define GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_SHIFT (5U) #define GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_SHIFT)) & \ GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_MASK) #define GPC_A53_PU_PGC_PDN_STATUS_A53_GPUMIX_PDN_STATUS_MASK (0x80U) #define GPC_A53_PU_PGC_PDN_STATUS_A53_GPUMIX_PDN_STATUS_SHIFT (7U) #define GPC_A53_PU_PGC_PDN_STATUS_A53_GPUMIX_PDN_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_GPUMIX_PDN_STATUS_SHIFT)) & \ GPC_A53_PU_PGC_PDN_STATUS_A53_GPUMIX_PDN_STATUS_MASK) #define GPC_A53_PU_PGC_PDN_STATUS_A53_DISPMIX_PDN_STATUS_MASK (0x400U) #define GPC_A53_PU_PGC_PDN_STATUS_A53_DISPMIX_PDN_STATUS_SHIFT (10U) #define GPC_A53_PU_PGC_PDN_STATUS_A53_DISPMIX_PDN_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_DISPMIX_PDN_STATUS_SHIFT)) & \ GPC_A53_PU_PGC_PDN_STATUS_A53_DISPMIX_PDN_STATUS_MASK) /*! @} */ /* The count of GPC_A53_PU_PGC_PDN_STATUS */ #define GPC_A53_PU_PGC_PDN_STATUS_COUNT (3U) /*! @name M7_PU_PGC_PDN_STATUS - M7 PU PGC software down trigger status */ /*! @{ */ #define GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY_PDN_STATUS_MASK (0x1U) #define GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY_PDN_STATUS_SHIFT (0U) #define GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY_PDN_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY_PDN_STATUS_SHIFT)) & \ GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY_PDN_STATUS_MASK) #define GPC_M7_PU_PGC_PDN_STATUS_M7_OTG1_PDN_STATUS_MASK (0x4U) #define GPC_M7_PU_PGC_PDN_STATUS_M7_OTG1_PDN_STATUS_SHIFT (2U) #define GPC_M7_PU_PGC_PDN_STATUS_M7_OTG1_PDN_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_OTG1_PDN_STATUS_SHIFT)) & \ GPC_M7_PU_PGC_PDN_STATUS_M7_OTG1_PDN_STATUS_MASK) #define GPC_M7_PU_PGC_PDN_STATUS_M7_DDR1_PDN_STATUS_MASK (0x20U) #define GPC_M7_PU_PGC_PDN_STATUS_M7_DDR1_PDN_STATUS_SHIFT (5U) #define GPC_M7_PU_PGC_PDN_STATUS_M7_DDR1_PDN_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_DDR1_PDN_STATUS_SHIFT)) & \ GPC_M7_PU_PGC_PDN_STATUS_M7_DDR1_PDN_STATUS_MASK) #define GPC_M7_PU_PGC_PDN_STATUS_M7_GPUMIX_PDN_STATUS_MASK (0x80U) #define GPC_M7_PU_PGC_PDN_STATUS_M7_GPUMIX_PDN_STATUS_SHIFT (7U) #define GPC_M7_PU_PGC_PDN_STATUS_M7_GPUMIX_PDN_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_GPUMIX_PDN_STATUS_SHIFT)) & \ GPC_M7_PU_PGC_PDN_STATUS_M7_GPUMIX_PDN_STATUS_MASK) #define GPC_M7_PU_PGC_PDN_STATUS_M7_DISPMIX_PDN_STATUS_MASK (0x400U) #define GPC_M7_PU_PGC_PDN_STATUS_M7_DISPMIX_PDN_STATUS_SHIFT (10U) #define GPC_M7_PU_PGC_PDN_STATUS_M7_DISPMIX_PDN_STATUS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_DISPMIX_PDN_STATUS_SHIFT)) & \ GPC_M7_PU_PGC_PDN_STATUS_M7_DISPMIX_PDN_STATUS_MASK) /*! @} */ /* The count of GPC_M7_PU_PGC_PDN_STATUS */ #define GPC_M7_PU_PGC_PDN_STATUS_COUNT (3U) /*! @name A53_MIX_PDN_FLG - A53 MIX PDN FLG */ /*! @{ */ #define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_MASK (0x1U) #define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_SHIFT (0U) #define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_SHIFT)) & \ GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_MASK) /*! @} */ /*! @name A53_PU_PDN_FLG - A53 PU PDN FLG */ /*! @{ */ #define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_MASK (0x3FFFU) #define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_SHIFT (0U) #define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_SHIFT)) & GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_MASK) /*! @} */ /*! @name M7_MIX_PDN_FLG - M7 MIX PDN FLG */ /*! @{ */ #define GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG_MASK (0x1U) #define GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG_SHIFT (0U) #define GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG_SHIFT)) & \ GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG_MASK) /*! @} */ /*! @name M7_PU_PDN_FLG - M7 PU PDN FLG */ /*! @{ */ #define GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG_MASK (0x3FFFU) #define GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG_SHIFT (0U) #define GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG_SHIFT)) & GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG_MASK) /*! @} */ /*! @name IMR_CORE2_A53 - IRQ masking register 1 of A53 core2..IRQ masking register 4 of A53 core2 */ /*! @{ */ #define GPC_IMR_CORE2_A53_IMR1_CORE2_A53_MASK (0xFFFFFFFFU) #define GPC_IMR_CORE2_A53_IMR1_CORE2_A53_SHIFT (0U) /*! IMR1_CORE2_A53 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_CORE2_A53_IMR1_CORE2_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR1_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR1_CORE2_A53_MASK) #define GPC_IMR_CORE2_A53_IMR2_CORE2_A53_MASK (0xFFFFFFFFU) #define GPC_IMR_CORE2_A53_IMR2_CORE2_A53_SHIFT (0U) /*! IMR2_CORE2_A53 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_CORE2_A53_IMR2_CORE2_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR2_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR2_CORE2_A53_MASK) #define GPC_IMR_CORE2_A53_IMR3_CORE2_A53_MASK (0xFFFFFFFFU) #define GPC_IMR_CORE2_A53_IMR3_CORE2_A53_SHIFT (0U) /*! IMR3_CORE2_A53 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_CORE2_A53_IMR3_CORE2_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR3_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR3_CORE2_A53_MASK) #define GPC_IMR_CORE2_A53_IMR4_CORE2_A53_MASK (0xFFFFFFFFU) #define GPC_IMR_CORE2_A53_IMR4_CORE2_A53_SHIFT (0U) /*! IMR4_CORE2_A53 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_CORE2_A53_IMR4_CORE2_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR4_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR4_CORE2_A53_MASK) /*! @} */ /* The count of GPC_IMR_CORE2_A53 */ #define GPC_IMR_CORE2_A53_COUNT (4U) /*! @name IMR_CORE3_A53 - IRQ masking register 1 of A53 core3..IRQ masking register 4 of A53 core3 */ /*! @{ */ #define GPC_IMR_CORE3_A53_IMR1_CORE3_A53_MASK (0xFFFFFFFFU) #define GPC_IMR_CORE3_A53_IMR1_CORE3_A53_SHIFT (0U) /*! IMR1_CORE3_A53 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_CORE3_A53_IMR1_CORE3_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR1_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR1_CORE3_A53_MASK) #define GPC_IMR_CORE3_A53_IMR2_CORE3_A53_MASK (0xFFFFFFFFU) #define GPC_IMR_CORE3_A53_IMR2_CORE3_A53_SHIFT (0U) /*! IMR2_CORE3_A53 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_CORE3_A53_IMR2_CORE3_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR2_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR2_CORE3_A53_MASK) #define GPC_IMR_CORE3_A53_IMR3_CORE3_A53_MASK (0xFFFFFFFFU) #define GPC_IMR_CORE3_A53_IMR3_CORE3_A53_SHIFT (0U) /*! IMR3_CORE3_A53 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_CORE3_A53_IMR3_CORE3_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR3_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR3_CORE3_A53_MASK) #define GPC_IMR_CORE3_A53_IMR4_CORE3_A53_MASK (0xFFFFFFFFU) #define GPC_IMR_CORE3_A53_IMR4_CORE3_A53_SHIFT (0U) /*! IMR4_CORE3_A53 * 0b00000000000000000000000000000000..IRQ not masked * 0b00000000000000000000000000000001..IRQ masked */ #define GPC_IMR_CORE3_A53_IMR4_CORE3_A53(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR4_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR4_CORE3_A53_MASK) /*! @} */ /* The count of GPC_IMR_CORE3_A53 */ #define GPC_IMR_CORE3_A53_COUNT (4U) /*! @name ACK_SEL_A53_PU - PGC acknowledge signal selection of A53 platform for PUs */ /*! @{ */ #define GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_MASK (0x4U) #define GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_SHIFT (2U) #define GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_SHIFT)) & \ GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_MASK) #define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_MASK (0x10U) #define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_SHIFT (4U) #define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_SHIFT)) & \ GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_MASK) #define GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_MASK (0x80U) #define GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_SHIFT (7U) #define GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_SHIFT)) & \ GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_MASK) #define GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PDN_ACK_MASK (0x200U) #define GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PDN_ACK_SHIFT (9U) #define GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PDN_ACK_SHIFT)) & \ GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PDN_ACK_MASK) #define GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PDN_ACK_MASK (0x1000U) #define GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PDN_ACK_SHIFT (12U) #define GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PDN_ACK_SHIFT)) & \ GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PDN_ACK_MASK) #define GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_MASK (0x40000U) #define GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_SHIFT (18U) #define GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_SHIFT)) & \ GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_MASK) #define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_MASK (0x100000U) #define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_SHIFT (20U) #define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_SHIFT)) & \ GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_MASK) #define GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_MASK (0x800000U) #define GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_SHIFT (23U) #define GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_SHIFT)) & \ GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_MASK) #define GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PUP_ACK_MASK (0x2000000U) #define GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PUP_ACK_SHIFT (25U) #define GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PUP_ACK_SHIFT)) & \ GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PUP_ACK_MASK) #define GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PUP_ACK_MASK (0x10000000U) #define GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PUP_ACK_SHIFT (28U) #define GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PUP_ACK_SHIFT)) & \ GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PUP_ACK_MASK) /*! @} */ /*! @name ACK_SEL_M7_PU - PGC acknowledge signal selection of M7 platform for PUs */ /*! @{ */ #define GPC_ACK_SEL_M7_PU_MIPI_PGC_PDN_ACK_MASK (0x4U) #define GPC_ACK_SEL_M7_PU_MIPI_PGC_PDN_ACK_SHIFT (2U) #define GPC_ACK_SEL_M7_PU_MIPI_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_MIPI_PGC_PDN_ACK_SHIFT)) & \ GPC_ACK_SEL_M7_PU_MIPI_PGC_PDN_ACK_MASK) #define GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PDN_ACK_MASK (0x10U) #define GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PDN_ACK_SHIFT (4U) #define GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PDN_ACK_SHIFT)) & \ GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PDN_ACK_MASK) #define GPC_ACK_SEL_M7_PU_DDR1_PGC_PDN_ACK_MASK (0x80U) #define GPC_ACK_SEL_M7_PU_DDR1_PGC_PDN_ACK_SHIFT (7U) #define GPC_ACK_SEL_M7_PU_DDR1_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_DDR1_PGC_PDN_ACK_SHIFT)) & \ GPC_ACK_SEL_M7_PU_DDR1_PGC_PDN_ACK_MASK) #define GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PDN_ACK_MASK (0x200U) #define GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PDN_ACK_SHIFT (9U) #define GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PDN_ACK_SHIFT)) & \ GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PDN_ACK_MASK) #define GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PDN_ACK_MASK (0x1000U) #define GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PDN_ACK_SHIFT (12U) #define GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PDN_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PDN_ACK_SHIFT)) & \ GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PDN_ACK_MASK) #define GPC_ACK_SEL_M7_PU_MIPI_PGC_PUP_ACK_MASK (0x40000U) #define GPC_ACK_SEL_M7_PU_MIPI_PGC_PUP_ACK_SHIFT (18U) #define GPC_ACK_SEL_M7_PU_MIPI_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_MIPI_PGC_PUP_ACK_SHIFT)) & \ GPC_ACK_SEL_M7_PU_MIPI_PGC_PUP_ACK_MASK) #define GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PUP_ACK_MASK (0x100000U) #define GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PUP_ACK_SHIFT (20U) #define GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PUP_ACK_SHIFT)) & \ GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PUP_ACK_MASK) #define GPC_ACK_SEL_M7_PU_DDR1_PGC_PUP_ACK_MASK (0x800000U) #define GPC_ACK_SEL_M7_PU_DDR1_PGC_PUP_ACK_SHIFT (23U) #define GPC_ACK_SEL_M7_PU_DDR1_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_DDR1_PGC_PUP_ACK_SHIFT)) & \ GPC_ACK_SEL_M7_PU_DDR1_PGC_PUP_ACK_MASK) #define GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PUP_ACK_MASK (0x2000000U) #define GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PUP_ACK_SHIFT (25U) #define GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PUP_ACK_SHIFT)) & \ GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PUP_ACK_MASK) #define GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PUP_ACK_MASK (0x10000000U) #define GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PUP_ACK_SHIFT (28U) #define GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PUP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PUP_ACK_SHIFT)) & \ GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PUP_ACK_MASK) /*! @} */ /*! @name SLT15_CFG - Slot configure register for PGC CPUs */ /*! @{ */ #define GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT15_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT15_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT15_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT15_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT15_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT15_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT15_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT15_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name SLT16_CFG - Slot configure register for PGC CPUs */ /*! @{ */ #define GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT16_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT16_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT16_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT16_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT16_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT16_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT16_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT16_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name SLT17_CFG - Slot configure register for PGC CPUs */ /*! @{ */ #define GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT17_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT17_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT17_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT17_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT17_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT17_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT17_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT17_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name SLT18_CFG - Slot configure register for PGC CPUs */ /*! @{ */ #define GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT18_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT18_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT18_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT18_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT18_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT18_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT18_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT18_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name SLT19_CFG - Slot configure register for PGC CPUs */ /*! @{ */ #define GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) #define GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) #define GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) #define GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) #define GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) #define GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) #define GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) #define GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) #define GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) #define GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) #define GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) #define GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) #define GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_MASK) #define GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) #define GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) #define GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_MASK) #define GPC_SLT19_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U) #define GPC_SLT19_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U) #define GPC_SLT19_CFG_NOC_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT19_CFG_NOC_PDN_SLOT_CONTROL_MASK) #define GPC_SLT19_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U) #define GPC_SLT19_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U) #define GPC_SLT19_CFG_NOC_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT19_CFG_NOC_PUP_SLOT_CONTROL_MASK) /*! @} */ /*! @name PU_PWRHSK - Power handshake register */ /*! @{ */ #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_MASK (0x1U) #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_SHIFT (0U) #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_SHIFT)) & \ GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_MASK) #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_MASK (0x2U) #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_SHIFT (1U) #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_SHIFT)) & \ GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_MASK) #define GPC_PU_PWRHSK_GPC_NOC2DDR_PWRDNREQN_MASK (0x4U) #define GPC_PU_PWRHSK_GPC_NOC2DDR_PWRDNREQN_SHIFT (2U) #define GPC_PU_PWRHSK_GPC_NOC2DDR_PWRDNREQN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2DDR_PWRDNREQN_SHIFT)) & \ GPC_PU_PWRHSK_GPC_NOC2DDR_PWRDNREQN_MASK) #define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN_MASK (0x8U) #define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN_SHIFT (3U) #define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN_SHIFT)) & \ GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN_MASK) #define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN_MASK (0x10U) #define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN_SHIFT (4U) #define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN_SHIFT)) & \ GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN_MASK) #define GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNREQN_MASK (0x20U) #define GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNREQN_SHIFT (5U) #define GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNREQN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNREQN_SHIFT)) & \ GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNREQN_MASK) #define GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNREQN_MASK (0x80U) #define GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNREQN_SHIFT (7U) #define GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNREQN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNREQN_SHIFT)) & \ GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNREQN_MASK) #define GPC_PU_PWRHSK_GPC_GPUPMIX2NOC_PWRDNREQN_MASK (0x200U) #define GPC_PU_PWRHSK_GPC_GPUPMIX2NOC_PWRDNREQN_SHIFT (9U) #define GPC_PU_PWRHSK_GPC_GPUPMIX2NOC_PWRDNREQN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_GPUPMIX2NOC_PWRDNREQN_SHIFT)) & \ GPC_PU_PWRHSK_GPC_GPUPMIX2NOC_PWRDNREQN_MASK) #define GPC_PU_PWRHSK_GPC_NOC2GPUPMIX_PWRDNREQN_MASK (0x800U) #define GPC_PU_PWRHSK_GPC_NOC2GPUPMIX_PWRDNREQN_SHIFT (11U) #define GPC_PU_PWRHSK_GPC_NOC2GPUPMIX_PWRDNREQN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2GPUPMIX_PWRDNREQN_SHIFT)) & \ GPC_PU_PWRHSK_GPC_NOC2GPUPMIX_PWRDNREQN_MASK) #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_MASK (0x10000U) #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_SHIFT (16U) #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_SHIFT)) & \ GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_MASK) #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_MASK (0x20000U) #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_SHIFT (17U) #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_SHIFT)) & \ GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_MASK) #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_MASK (0x40000U) #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_SHIFT (18U) #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_SHIFT)) & \ GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_MASK) #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_MASK (0x80000U) #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_SHIFT (19U) #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_SHIFT)) & \ GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_MASK) #define GPC_PU_PWRHSK_GPC_NOC2DDR1_PWRDNACKN_MASK (0x100000U) #define GPC_PU_PWRHSK_GPC_NOC2DDR1_PWRDNACKN_SHIFT (20U) #define GPC_PU_PWRHSK_GPC_NOC2DDR1_PWRDNACKN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2DDR1_PWRDNACKN_SHIFT)) & \ GPC_PU_PWRHSK_GPC_NOC2DDR1_PWRDNACKN_MASK) #define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNACKN_MASK (0x200000U) #define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNACKN_SHIFT (21U) #define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNACKN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNACKN_SHIFT)) & \ GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNACKN_MASK) #define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNACKN_MASK (0x400000U) #define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNACKN_SHIFT (22U) #define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNACKN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNACKN_SHIFT)) & \ GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNACKN_MASK) #define GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNACKN_MASK (0x800000U) #define GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNACKN_SHIFT (23U) #define GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNACKN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNACKN_SHIFT)) & \ GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNACKN_MASK) #define GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNACKN_MASK (0x2000000U) #define GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNACKN_SHIFT (25U) #define GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNACKN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNACKN_SHIFT)) & \ GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNACKN_MASK) #define GPC_PU_PWRHSK_GPC_GPUMIX2NOC_PWRDNACKN_MASK (0x8000000U) #define GPC_PU_PWRHSK_GPC_GPUMIX2NOC_PWRDNACKN_SHIFT (27U) #define GPC_PU_PWRHSK_GPC_GPUMIX2NOC_PWRDNACKN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_GPUMIX2NOC_PWRDNACKN_SHIFT)) & \ GPC_PU_PWRHSK_GPC_GPUMIX2NOC_PWRDNACKN_MASK) #define GPC_PU_PWRHSK_GPC_NOC2GPUMIX_PWRDNACKN_MASK (0x20000000U) #define GPC_PU_PWRHSK_GPC_NOC2GPUMIX_PWRDNACKN_SHIFT (29U) #define GPC_PU_PWRHSK_GPC_NOC2GPUMIX_PWRDNACKN(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2GPUMIX_PWRDNACKN_SHIFT)) & \ GPC_PU_PWRHSK_GPC_NOC2GPUMIX_PWRDNACKN_MASK) /*! @} */ /*! @name SLT_CFG_PU - Slot configure register for PGC PUs */ /*! @{ */ #define GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_MASK (0x4U) #define GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_SHIFT (2U) #define GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_MASK) #define GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_MASK (0x8U) #define GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_SHIFT (3U) #define GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_MASK) #define GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_MASK (0x40U) #define GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_SHIFT (6U) #define GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_MASK) #define GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_MASK (0x80U) #define GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_SHIFT (7U) #define GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_MASK) #define GPC_SLT_CFG_PU_M7_PDN_SLOT_CONTROL_MASK (0x1000U) #define GPC_SLT_CFG_PU_M7_PDN_SLOT_CONTROL_SHIFT (12U) #define GPC_SLT_CFG_PU_M7_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_M7_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT_CFG_PU_M7_PDN_SLOT_CONTROL_MASK) #define GPC_SLT_CFG_PU_M7_PUP_SLOT_CONTROL_MASK (0x2000U) #define GPC_SLT_CFG_PU_M7_PUP_SLOT_CONTROL_SHIFT (13U) #define GPC_SLT_CFG_PU_M7_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_M7_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT_CFG_PU_M7_PUP_SLOT_CONTROL_MASK) #define GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_MASK (0x4000U) #define GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_SHIFT (14U) #define GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_MASK) #define GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_MASK (0x8000U) #define GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_SHIFT (15U) #define GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_MASK) #define GPC_SLT_CFG_PU_GPUMIX_PDN_SLOT_CONTROL_MASK (0x40000U) #define GPC_SLT_CFG_PU_GPUMIX_PDN_SLOT_CONTROL_SHIFT (18U) #define GPC_SLT_CFG_PU_GPUMIX_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPUMIX_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT_CFG_PU_GPUMIX_PDN_SLOT_CONTROL_MASK) #define GPC_SLT_CFG_PU_GPUMIX_PUP_SLOT_CONTROL_MASK (0x80000U) #define GPC_SLT_CFG_PU_GPUMIX_PUP_SLOT_CONTROL_SHIFT (19U) #define GPC_SLT_CFG_PU_GPUMIX_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPUMIX_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT_CFG_PU_GPUMIX_PUP_SLOT_CONTROL_MASK) #define GPC_SLT_CFG_PU_DISPMIX_PDN_SLOT_CONTROL_MASK (0x1000000U) #define GPC_SLT_CFG_PU_DISPMIX_PDN_SLOT_CONTROL_SHIFT (24U) #define GPC_SLT_CFG_PU_DISPMIX_PDN_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DISPMIX_PDN_SLOT_CONTROL_SHIFT)) & \ GPC_SLT_CFG_PU_DISPMIX_PDN_SLOT_CONTROL_MASK) #define GPC_SLT_CFG_PU_DISPMIX_PUP_SLOT_CONTROL_MASK (0x2000000U) #define GPC_SLT_CFG_PU_DISPMIX_PUP_SLOT_CONTROL_SHIFT (25U) #define GPC_SLT_CFG_PU_DISPMIX_PUP_SLOT_CONTROL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DISPMIX_PUP_SLOT_CONTROL_SHIFT)) & \ GPC_SLT_CFG_PU_DISPMIX_PUP_SLOT_CONTROL_MASK) /*! @} */ /* The count of GPC_SLT_CFG_PU */ #define GPC_SLT_CFG_PU_COUNT (20U) /*! * @} */ /* end of group GPC_Register_Masks */ /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ #define GPC_BASE (0x303A0000u) /** Peripheral GPC base pointer */ #define GPC ((GPC_Type *)GPC_BASE) /** Array initializer of GPC peripheral base addresses */ #define GPC_BASE_ADDRS \ { \ GPC_BASE \ } /** Array initializer of GPC peripheral base pointers */ #define GPC_BASE_PTRS \ { \ GPC \ } /** Interrupt vectors for the GPC peripheral type */ #define GPC_IRQS \ { \ GPC_IRQn \ } /*! * @} */ /* end of group GPC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPC_PGC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPC_PGC_Peripheral_Access_Layer GPC_PGC Peripheral Access Layer * @{ */ /** GPC_PGC - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[2048]; struct { /* offset: 0x800, array step: 0x40 */ __IO uint32_t PGC_CTRL; /**< GPC PGC Control Register for PGC CPUs, array offset: 0x800, array step: 0x40 */ __IO uint32_t PGC_PUPSCR; /**< GPC PGC Up Sequence Control Register, array offset: 0x804, array step: 0x40 */ __IO uint32_t PGC_PDNSCR; /**< GPC PGC Down Sequence Control Register, array offset: 0x808, array step: 0x40 */ __IO uint32_t PGC_SR; /**< GPC PGC Status Register, array offset: 0x80C, array step: 0x40 */ uint8_t RESERVED_0[48]; } GPC_PGC_A53COREnCTRL[4]; __IO uint32_t A53SCU_CTRL; /**< GPC PGC Control Register for PGC CPUs, offset: 0x900 */ __IO uint32_t A53SCU_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x904 */ __IO uint32_t A53SCU_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x908 */ __IO uint32_t A53SCU_SR; /**< GPC PGC Status Register, offset: 0x90C */ __IO uint32_t A53SCU_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x910 */ uint8_t RESERVED_1[300]; __IO uint32_t NOC_MIX_CTRL; /**< GPC PGC Control Register for PGC MIX., offset: 0xA40 */ __IO uint32_t NOC_MIX_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0xA44 */ __IO uint32_t NOC_MIX_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0xA48 */ __IO uint32_t NOC_MIX_SR; /**< GPC PGC Status Register, offset: 0xA4C */ uint8_t RESERVED_2[432]; struct { /* offset: 0xC00, array step: 0x40 */ __IO uint32_t PU_CTRL; /**< GPC PGC Control Register for PGC PUs, array offset: 0xC00, array step: 0x40 */ __IO uint32_t PU_PUPSCR; /**< GPC PGC Up Sequence Control Register, array offset: 0xC04, array step: 0x40 */ __IO uint32_t PU_PDNSCR; /**< GPC PGC Down Sequence Control Register, array offset: 0xC08, array step: 0x40 */ __IO uint32_t PU_SR; /**< GPC PGC Status Register, array offset: 0xC0C, array step: 0x40 */ uint8_t RESERVED_0[48]; } GPC_PGC_CTRL[14]; } GPC_PGC_Type; /* ---------------------------------------------------------------------------- -- GPC_PGC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPC_PGC_Register_Masks GPC_PGC Register Masks * @{ */ /*! @name PGC_CTRL - GPC PGC Control Register for PGC CPUs */ /*! @{ */ #define GPC_PGC_PGC_CTRL_PCR_MASK (0x1U) #define GPC_PGC_PGC_CTRL_PCR_SHIFT (0U) /*! PCR * 0b0..Do not switch off power even if pdn_req is asserted. * 0b1..Switch off power when pdn_req is asserted. */ #define GPC_PGC_PGC_CTRL_PCR(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_PCR_SHIFT)) & GPC_PGC_PGC_CTRL_PCR_MASK) #define GPC_PGC_PGC_CTRL_L2RSTDIS_MASK (0x7EU) #define GPC_PGC_PGC_CTRL_L2RSTDIS_SHIFT (1U) #define GPC_PGC_PGC_CTRL_L2RSTDIS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PGC_CTRL_L2RSTDIS_MASK) #define GPC_PGC_PGC_CTRL_DFTRAM_TCD1_MASK (0x3F00U) #define GPC_PGC_PGC_CTRL_DFTRAM_TCD1_SHIFT (8U) #define GPC_PGC_PGC_CTRL_DFTRAM_TCD1(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PGC_CTRL_DFTRAM_TCD1_MASK) #define GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) #define GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) #define GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR_MASK) #define GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) #define GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) #define GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & \ GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) /*! @} */ /* The count of GPC_PGC_PGC_CTRL */ #define GPC_PGC_PGC_CTRL_COUNT (4U) /*! @name PGC_PUPSCR - GPC PGC Up Sequence Control Register */ /*! @{ */ #define GPC_PGC_PGC_PUPSCR_SW_MASK (0x3FU) #define GPC_PGC_PGC_PUPSCR_SW_SHIFT (0U) #define GPC_PGC_PGC_PUPSCR_SW(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_PUPSCR_SW_SHIFT)) & GPC_PGC_PGC_PUPSCR_SW_MASK) #define GPC_PGC_PGC_PUPSCR_SW2ISO_MASK (0x7FFF80U) #define GPC_PGC_PGC_PUPSCR_SW2ISO_SHIFT (7U) #define GPC_PGC_PGC_PUPSCR_SW2ISO(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PGC_PUPSCR_SW2ISO_MASK) /*! @} */ /* The count of GPC_PGC_PGC_PUPSCR */ #define GPC_PGC_PGC_PUPSCR_COUNT (4U) /*! @name PGC_PDNSCR - GPC PGC Down Sequence Control Register */ /*! @{ */ #define GPC_PGC_PGC_PDNSCR_ISO_MASK (0x3FU) #define GPC_PGC_PGC_PDNSCR_ISO_SHIFT (0U) #define GPC_PGC_PGC_PDNSCR_ISO(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_PDNSCR_ISO_SHIFT)) & GPC_PGC_PGC_PDNSCR_ISO_MASK) #define GPC_PGC_PGC_PDNSCR_ISO2SW_MASK (0x3F00U) #define GPC_PGC_PGC_PDNSCR_ISO2SW_SHIFT (8U) #define GPC_PGC_PGC_PDNSCR_ISO2SW(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PGC_PDNSCR_ISO2SW_MASK) /*! @} */ /* The count of GPC_PGC_PGC_PDNSCR */ #define GPC_PGC_PGC_PDNSCR_COUNT (4U) /*! @name PGC_SR - GPC PGC Status Register */ /*! @{ */ #define GPC_PGC_PGC_SR_PSR_MASK (0x1U) #define GPC_PGC_PGC_SR_PSR_SHIFT (0U) /*! PSR * 0b0..The target subsystem was not powered down for the previous power-down request. * 0b1..The target subsystem was powered down for the previous power-down request. */ #define GPC_PGC_PGC_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_PSR_SHIFT)) & GPC_PGC_PGC_SR_PSR_MASK) #define GPC_PGC_PGC_SR_L2RETN_FLAG_MASK (0x2U) #define GPC_PGC_PGC_SR_L2RETN_FLAG_SHIFT (1U) /*! L2RETN_FLAG * 0b0..A53 is not wakeup from L2 retention mode. * 0b1..A53 is wakeup from L2 retention mode. */ #define GPC_PGC_PGC_SR_L2RETN_FLAG(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PGC_SR_L2RETN_FLAG_MASK) #define GPC_PGC_PGC_SR_ALLOFF_FLAG_MASK (0x4U) #define GPC_PGC_PGC_SR_ALLOFF_FLAG_SHIFT (2U) /*! ALLOFF_FLAG * 0b0..A53 is not wakeup from ALL_OFF mode. * 0b1..A53 is wakeup from ALL_OFF mode. */ #define GPC_PGC_PGC_SR_ALLOFF_FLAG(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PGC_SR_ALLOFF_FLAG_MASK) #define GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL_MASK (0x78U) #define GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL_SHIFT (3U) /*! PUP_CLK_DIV_SEL * 0b0000..1 * 0b0001..1/2 count_clk * 0b0010..1/4 count_clk * 0b0011..1/8 count_clk * 0b0100..1/16 count_clk * 0b0101..1/32 count_clk * 0b0110..1/64 count_clk * 0b0111..1/128 count_clk * 0b1000..1/256 count_clk * 0b1001..1/512 count_clk * 0b1010..1/1024 count_clk * 0b1011..1/2056 count_clk * 0b1100..1/4096 count_clk * 0b1101..1/8192 count_clk * 0b1110..1/16384 count_clk * 0b1111..1/32768 count_clk */ #define GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL_MASK) #define GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) #define GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) #define GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & \ GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT_MASK) /*! @} */ /* The count of GPC_PGC_PGC_SR */ #define GPC_PGC_PGC_SR_COUNT (4U) /*! @name A53SCU_CTRL - GPC PGC Control Register for PGC CPUs */ /*! @{ */ #define GPC_PGC_A53SCU_CTRL_PCR_MASK (0x1U) #define GPC_PGC_A53SCU_CTRL_PCR_SHIFT (0U) /*! PCR * 0b0..Do not switch off power even if pdn_req is asserted. * 0b1..Switch off power when pdn_req is asserted. */ #define GPC_PGC_A53SCU_CTRL_PCR(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_PCR_SHIFT)) & GPC_PGC_A53SCU_CTRL_PCR_MASK) #define GPC_PGC_A53SCU_CTRL_L2RSTDIS_MASK (0x7EU) #define GPC_PGC_A53SCU_CTRL_L2RSTDIS_SHIFT (1U) #define GPC_PGC_A53SCU_CTRL_L2RSTDIS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53SCU_CTRL_L2RSTDIS_MASK) #define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_MASK (0x3F00U) #define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_SHIFT (8U) #define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_MASK) #define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) #define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) #define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_SHIFT)) & \ GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_MASK) #define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) #define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) #define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & \ GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) /*! @} */ /*! @name A53SCU_PUPSCR - GPC PGC Up Sequence Control Register */ /*! @{ */ #define GPC_PGC_A53SCU_PUPSCR_SW_MASK (0x3FU) #define GPC_PGC_A53SCU_PUPSCR_SW_SHIFT (0U) #define GPC_PGC_A53SCU_PUPSCR_SW(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_SW_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_SW_MASK) #define GPC_PGC_A53SCU_PUPSCR_SW2ISO_MASK (0x7FFF80U) #define GPC_PGC_A53SCU_PUPSCR_SW2ISO_SHIFT (7U) #define GPC_PGC_A53SCU_PUPSCR_SW2ISO(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_SW2ISO_MASK) /*! @} */ /*! @name A53SCU_PDNSCR - GPC PGC Down Sequence Control Register */ /*! @{ */ #define GPC_PGC_A53SCU_PDNSCR_ISO_MASK (0x3FU) #define GPC_PGC_A53SCU_PDNSCR_ISO_SHIFT (0U) #define GPC_PGC_A53SCU_PDNSCR_ISO(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_ISO_MASK) #define GPC_PGC_A53SCU_PDNSCR_ISO2SW_MASK (0x3F00U) #define GPC_PGC_A53SCU_PDNSCR_ISO2SW_SHIFT (8U) #define GPC_PGC_A53SCU_PDNSCR_ISO2SW(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_ISO2SW_MASK) /*! @} */ /*! @name A53SCU_SR - GPC PGC Status Register */ /*! @{ */ #define GPC_PGC_A53SCU_SR_PSR_MASK (0x1U) #define GPC_PGC_A53SCU_SR_PSR_SHIFT (0U) /*! PSR * 0b0..The target subsystem was not powered down for the previous power-down request. * 0b1..The target subsystem was powered down for the previous power-down request. */ #define GPC_PGC_A53SCU_SR_PSR(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_PSR_SHIFT)) & GPC_PGC_A53SCU_SR_PSR_MASK) #define GPC_PGC_A53SCU_SR_L2RETN_FLAG_MASK (0x2U) #define GPC_PGC_A53SCU_SR_L2RETN_FLAG_SHIFT (1U) /*! L2RETN_FLAG * 0b0..A53 is not wakeup from L2 retention mode. * 0b1..A53 is wakeup from L2 retention mode. */ #define GPC_PGC_A53SCU_SR_L2RETN_FLAG(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53SCU_SR_L2RETN_FLAG_MASK) #define GPC_PGC_A53SCU_SR_ALLOFF_FLAG_MASK (0x4U) #define GPC_PGC_A53SCU_SR_ALLOFF_FLAG_SHIFT (2U) /*! ALLOFF_FLAG * 0b0..A53 is not wakeup from ALL_OFF mode. * 0b1..A53 is wakeup from ALL_OFF mode. */ #define GPC_PGC_A53SCU_SR_ALLOFF_FLAG(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53SCU_SR_ALLOFF_FLAG_MASK) #define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_MASK (0x78U) #define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_SHIFT (3U) /*! PUP_CLK_DIV_SEL * 0b0000..1 * 0b0001..1/2 count_clk * 0b0010..1/4 count_clk * 0b0011..1/8 count_clk * 0b0100..1/16 count_clk * 0b0101..1/32 count_clk * 0b0110..1/64 count_clk * 0b0111..1/128 count_clk * 0b1000..1/256 count_clk * 0b1001..1/512 count_clk * 0b1010..1/1024 count_clk * 0b1011..1/2056 count_clk * 0b1100..1/4096 count_clk * 0b1101..1/8192 count_clk * 0b1110..1/16384 count_clk * 0b1111..1/32768 count_clk */ #define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_MASK) #define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) #define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) #define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & \ GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_MASK) /*! @} */ /*! @name A53SCU_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ /*! @{ */ #define GPC_PGC_A53SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2_MASK (0x3FFU) #define GPC_PGC_A53SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2_SHIFT (0U) #define GPC_PGC_A53SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2_SHIFT)) & \ GPC_PGC_A53SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2_MASK) #define GPC_PGC_A53SCU_AUXSW_L2RETN_RTC1_TMC_TMR_MASK (0xFFC00U) #define GPC_PGC_A53SCU_AUXSW_L2RETN_RTC1_TMC_TMR_SHIFT (10U) #define GPC_PGC_A53SCU_AUXSW_L2RETN_RTC1_TMC_TMR(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_AUXSW_L2RETN_RTC1_TMC_TMR_SHIFT)) & \ GPC_PGC_A53SCU_AUXSW_L2RETN_RTC1_TMC_TMR_MASK) #define GPC_PGC_A53SCU_AUXSW_MEMPWR_TRC1_TMC_MASK (0x3FF00000U) #define GPC_PGC_A53SCU_AUXSW_MEMPWR_TRC1_TMC_SHIFT (20U) #define GPC_PGC_A53SCU_AUXSW_MEMPWR_TRC1_TMC(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_AUXSW_MEMPWR_TRC1_TMC_SHIFT)) & \ GPC_PGC_A53SCU_AUXSW_MEMPWR_TRC1_TMC_MASK) /*! @} */ /*! @name NOC_MIX_CTRL - GPC PGC Control Register for PGC MIX. */ /*! @{ */ #define GPC_PGC_NOC_MIX_CTRL_MIX_PCR_MASK (0x1U) #define GPC_PGC_NOC_MIX_CTRL_MIX_PCR_SHIFT (0U) /*! MIX_PCR * 0b0..Do not switch off power even if pdn_req is asserted. * 0b1..Switch off power when pdn_req is asserted. */ #define GPC_PGC_NOC_MIX_CTRL_MIX_PCR(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_MIX_PCR_SHIFT)) & GPC_PGC_NOC_MIX_CTRL_MIX_PCR_MASK) #define GPC_PGC_NOC_MIX_CTRL_L2RSTDIS_MASK (0x7EU) #define GPC_PGC_NOC_MIX_CTRL_L2RSTDIS_SHIFT (1U) #define GPC_PGC_NOC_MIX_CTRL_L2RSTDIS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_NOC_MIX_CTRL_L2RSTDIS_MASK) #define GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1_MASK (0x3F00U) #define GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1_SHIFT (8U) #define GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1_MASK) #define GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) #define GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) #define GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR_SHIFT)) & \ GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR_MASK) #define GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) #define GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) #define GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & \ GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) /*! @} */ /*! @name NOC_MIX_PUPSCR - GPC PGC Up Sequence Control Register */ /*! @{ */ #define GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) #define GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) #define GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & \ GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) #define GPC_PGC_NOC_MIX_PUPSCR_SW2ISO_MASK (0x7FFF80U) #define GPC_PGC_NOC_MIX_PUPSCR_SW2ISO_SHIFT (7U) #define GPC_PGC_NOC_MIX_PUPSCR_SW2ISO(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_NOC_MIX_PUPSCR_SW2ISO_MASK) /*! @} */ /*! @name NOC_MIX_PDNSCR - GPC PGC Down Sequence Control Register */ /*! @{ */ #define GPC_PGC_NOC_MIX_PDNSCR_ISO_MASK (0x3FU) #define GPC_PGC_NOC_MIX_PDNSCR_ISO_SHIFT (0U) #define GPC_PGC_NOC_MIX_PDNSCR_ISO(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_PDNSCR_ISO_SHIFT)) & GPC_PGC_NOC_MIX_PDNSCR_ISO_MASK) #define GPC_PGC_NOC_MIX_PDNSCR_ISO2SW_MASK (0x3F00U) #define GPC_PGC_NOC_MIX_PDNSCR_ISO2SW_SHIFT (8U) #define GPC_PGC_NOC_MIX_PDNSCR_ISO2SW(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_NOC_MIX_PDNSCR_ISO2SW_MASK) /*! @} */ /*! @name NOC_MIX_SR - GPC PGC Status Register */ /*! @{ */ #define GPC_PGC_NOC_MIX_SR_PSR_MASK (0x1U) #define GPC_PGC_NOC_MIX_SR_PSR_SHIFT (0U) /*! PSR * 0b0..The target subsystem was not powered down for the previous power-down request. * 0b1..The target subsystem was powered down for the previous power-down request. */ #define GPC_PGC_NOC_MIX_SR_PSR(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_PSR_SHIFT)) & GPC_PGC_NOC_MIX_SR_PSR_MASK) #define GPC_PGC_NOC_MIX_SR_L2RETN_FLAG_MASK (0x2U) #define GPC_PGC_NOC_MIX_SR_L2RETN_FLAG_SHIFT (1U) /*! L2RETN_FLAG * 0b0..A53 is not wakeup from L2 retention mode. * 0b1..A53 is wakeup from L2 retention mode. */ #define GPC_PGC_NOC_MIX_SR_L2RETN_FLAG(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_NOC_MIX_SR_L2RETN_FLAG_MASK) #define GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG_MASK (0x4U) #define GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG_SHIFT (2U) /*! ALLOFF_FLAG * 0b0..A53 is not wakeup from ALL_OFF mode. * 0b1..A53 is wakeup from ALL_OFF mode. */ #define GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG_MASK) #define GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL_MASK (0x78U) #define GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL_SHIFT (3U) /*! PUP_CLK_DIV_SEL * 0b0000..1 * 0b0001..1/2 count_clk * 0b0010..1/4 count_clk * 0b0011..1/8 count_clk * 0b0100..1/16 count_clk * 0b0101..1/32 count_clk * 0b0110..1/64 count_clk * 0b0111..1/128 count_clk * 0b1000..1/256 count_clk * 0b1001..1/512 count_clk * 0b1010..1/1024 count_clk * 0b1011..1/2056 count_clk * 0b1100..1/4096 count_clk * 0b1101..1/8192 count_clk * 0b1110..1/16384 count_clk * 0b1111..1/32768 count_clk */ #define GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL_SHIFT)) & \ GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL_MASK) #define GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) #define GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) #define GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & \ GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT_MASK) /*! @} */ /*! @name PU_CTRL - GPC PGC Control Register for PGC PUs */ /*! @{ */ #define GPC_PGC_PU_CTRL_PCR_MASK (0x1U) #define GPC_PGC_PU_CTRL_PCR_SHIFT (0U) /*! PCR * 0b0..Do not switch off power even if pdn_req is asserted. * 0b1..Switch off power when pdn_req is asserted. */ #define GPC_PGC_PU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_PCR_SHIFT)) & GPC_PGC_PU_CTRL_PCR_MASK) #define GPC_PGC_PU_CTRL_L2RSTDIS_MASK (0x7EU) #define GPC_PGC_PU_CTRL_L2RSTDIS_SHIFT (1U) #define GPC_PGC_PU_CTRL_L2RSTDIS(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU_CTRL_L2RSTDIS_MASK) #define GPC_PGC_PU_CTRL_DFTRAM_TCD1_MASK (0x3F00U) #define GPC_PGC_PU_CTRL_DFTRAM_TCD1_SHIFT (8U) #define GPC_PGC_PU_CTRL_DFTRAM_TCD1(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU_CTRL_DFTRAM_TCD1_MASK) #define GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) #define GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) #define GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR_MASK) #define GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) #define GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) #define GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & \ GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) /*! @} */ /* The count of GPC_PGC_PU_CTRL */ #define GPC_PGC_PU_CTRL_COUNT (14U) /*! @name PU_PUPSCR - GPC PGC Up Sequence Control Register */ /*! @{ */ #define GPC_PGC_PU_PUPSCR_SW_MASK (0x3FU) #define GPC_PGC_PU_PUPSCR_SW_SHIFT (0U) #define GPC_PGC_PU_PUPSCR_SW(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_PUPSCR_SW_SHIFT)) & GPC_PGC_PU_PUPSCR_SW_MASK) #define GPC_PGC_PU_PUPSCR_SW2ISO_MASK (0x7FFF80U) #define GPC_PGC_PU_PUPSCR_SW2ISO_SHIFT (7U) #define GPC_PGC_PU_PUPSCR_SW2ISO(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU_PUPSCR_SW2ISO_MASK) /*! @} */ /* The count of GPC_PGC_PU_PUPSCR */ #define GPC_PGC_PU_PUPSCR_COUNT (14U) /*! @name PU_PDNSCR - GPC PGC Down Sequence Control Register */ /*! @{ */ #define GPC_PGC_PU_PDNSCR_ISO_MASK (0x3FU) #define GPC_PGC_PU_PDNSCR_ISO_SHIFT (0U) #define GPC_PGC_PU_PDNSCR_ISO(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU_PDNSCR_ISO_MASK) #define GPC_PGC_PU_PDNSCR_ISO2SW_MASK (0x3F00U) #define GPC_PGC_PU_PDNSCR_ISO2SW_SHIFT (8U) #define GPC_PGC_PU_PDNSCR_ISO2SW(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU_PDNSCR_ISO2SW_MASK) /*! @} */ /* The count of GPC_PGC_PU_PDNSCR */ #define GPC_PGC_PU_PDNSCR_COUNT (14U) /*! @name PU_SR - GPC PGC Status Register */ /*! @{ */ #define GPC_PGC_PU_SR_PSR_MASK (0x1U) #define GPC_PGC_PU_SR_PSR_SHIFT (0U) /*! PSR * 0b0..The target subsystem was not powered down for the previous power-down request. * 0b1..The target subsystem was powered down for the previous power-down request. */ #define GPC_PGC_PU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_PSR_SHIFT)) & GPC_PGC_PU_SR_PSR_MASK) #define GPC_PGC_PU_SR_L2RETN_FLAG_MASK (0x2U) #define GPC_PGC_PU_SR_L2RETN_FLAG_SHIFT (1U) /*! L2RETN_FLAG * 0b0..A53 is not wakeup from L2 retention mode. * 0b1..A53 is wakeup from L2 retention mode. */ #define GPC_PGC_PU_SR_L2RETN_FLAG(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU_SR_L2RETN_FLAG_MASK) #define GPC_PGC_PU_SR_ALLOFF_FLAG_MASK (0x4U) #define GPC_PGC_PU_SR_ALLOFF_FLAG_SHIFT (2U) /*! ALLOFF_FLAG * 0b0..A53 is not wakeup from ALL_OFF mode. * 0b1..A53 is wakeup from ALL_OFF mode. */ #define GPC_PGC_PU_SR_ALLOFF_FLAG(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU_SR_ALLOFF_FLAG_MASK) #define GPC_PGC_PU_SR_PUP_CLK_DIV_SEL_MASK (0x78U) #define GPC_PGC_PU_SR_PUP_CLK_DIV_SEL_SHIFT (3U) /*! PUP_CLK_DIV_SEL * 0b0000..1 * 0b0001..1/2 count_clk * 0b0010..1/4 count_clk * 0b0011..1/8 count_clk * 0b0100..1/16 count_clk * 0b0101..1/32 count_clk * 0b0110..1/64 count_clk * 0b0111..1/128 count_clk * 0b1000..1/256 count_clk * 0b1001..1/512 count_clk * 0b1010..1/1024 count_clk * 0b1011..1/2056 count_clk * 0b1100..1/4096 count_clk * 0b1101..1/8192 count_clk * 0b1110..1/16384 count_clk * 0b1111..1/32768 count_clk */ #define GPC_PGC_PU_SR_PUP_CLK_DIV_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU_SR_PUP_CLK_DIV_SEL_MASK) #define GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) #define GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) #define GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & \ GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT_MASK) /*! @} */ /* The count of GPC_PGC_PU_SR */ #define GPC_PGC_PU_SR_COUNT (14U) /*! * @} */ /* end of group GPC_PGC_Register_Masks */ /* GPC_PGC - Peripheral instance base addresses */ /** Peripheral GPC_PGC base address */ #define GPC_PGC_BASE (0x303A0000u) /** Peripheral GPC_PGC base pointer */ #define GPC_PGC ((GPC_PGC_Type *)GPC_PGC_BASE) /** Array initializer of GPC_PGC peripheral base addresses */ #define GPC_PGC_BASE_ADDRS \ { \ GPC_PGC_BASE \ } /** Array initializer of GPC_PGC peripheral base pointers */ #define GPC_PGC_BASE_PTRS \ { \ GPC_PGC \ } /*! * @} */ /* end of group GPC_PGC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPIO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer * @{ */ /** GPIO - Register Layout Typedef */ typedef struct { __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */ __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */ __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */ __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */ __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ } GPIO_Type; /* ---------------------------------------------------------------------------- -- GPIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Register_Masks GPIO Register Masks * @{ */ /*! @name DR - GPIO data register */ /*! @{ */ #define GPIO_DR_DR_MASK (0xFFFFFFFFU) #define GPIO_DR_DR_SHIFT (0U) #define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) /*! @} */ /*! @name GDIR - GPIO direction register */ /*! @{ */ #define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) #define GPIO_GDIR_GDIR_SHIFT (0U) /*! GDIR * 0b00000000000000000000000000000000..GPIO is configured as input. * 0b00000000000000000000000000000001..GPIO is configured as output. */ #define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) /*! @} */ /*! @name PSR - GPIO pad status register */ /*! @{ */ #define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) #define GPIO_PSR_PSR_SHIFT (0U) #define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) /*! @} */ /*! @name ICR1 - GPIO interrupt configuration register1 */ /*! @{ */ #define GPIO_ICR1_ICR0_MASK (0x3U) #define GPIO_ICR1_ICR0_SHIFT (0U) /*! ICR0 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) #define GPIO_ICR1_ICR1_MASK (0xCU) #define GPIO_ICR1_ICR1_SHIFT (2U) /*! ICR1 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) #define GPIO_ICR1_ICR2_MASK (0x30U) #define GPIO_ICR1_ICR2_SHIFT (4U) /*! ICR2 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) #define GPIO_ICR1_ICR3_MASK (0xC0U) #define GPIO_ICR1_ICR3_SHIFT (6U) /*! ICR3 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) #define GPIO_ICR1_ICR4_MASK (0x300U) #define GPIO_ICR1_ICR4_SHIFT (8U) /*! ICR4 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) #define GPIO_ICR1_ICR5_MASK (0xC00U) #define GPIO_ICR1_ICR5_SHIFT (10U) /*! ICR5 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) #define GPIO_ICR1_ICR6_MASK (0x3000U) #define GPIO_ICR1_ICR6_SHIFT (12U) /*! ICR6 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) #define GPIO_ICR1_ICR7_MASK (0xC000U) #define GPIO_ICR1_ICR7_SHIFT (14U) /*! ICR7 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) #define GPIO_ICR1_ICR8_MASK (0x30000U) #define GPIO_ICR1_ICR8_SHIFT (16U) /*! ICR8 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) #define GPIO_ICR1_ICR9_MASK (0xC0000U) #define GPIO_ICR1_ICR9_SHIFT (18U) /*! ICR9 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) #define GPIO_ICR1_ICR10_MASK (0x300000U) #define GPIO_ICR1_ICR10_SHIFT (20U) /*! ICR10 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) #define GPIO_ICR1_ICR11_MASK (0xC00000U) #define GPIO_ICR1_ICR11_SHIFT (22U) /*! ICR11 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) #define GPIO_ICR1_ICR12_MASK (0x3000000U) #define GPIO_ICR1_ICR12_SHIFT (24U) /*! ICR12 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) #define GPIO_ICR1_ICR13_MASK (0xC000000U) #define GPIO_ICR1_ICR13_SHIFT (26U) /*! ICR13 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) #define GPIO_ICR1_ICR14_MASK (0x30000000U) #define GPIO_ICR1_ICR14_SHIFT (28U) /*! ICR14 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) #define GPIO_ICR1_ICR15_MASK (0xC0000000U) #define GPIO_ICR1_ICR15_SHIFT (30U) /*! ICR15 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) /*! @} */ /*! @name ICR2 - GPIO interrupt configuration register2 */ /*! @{ */ #define GPIO_ICR2_ICR16_MASK (0x3U) #define GPIO_ICR2_ICR16_SHIFT (0U) /*! ICR16 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) #define GPIO_ICR2_ICR17_MASK (0xCU) #define GPIO_ICR2_ICR17_SHIFT (2U) /*! ICR17 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) #define GPIO_ICR2_ICR18_MASK (0x30U) #define GPIO_ICR2_ICR18_SHIFT (4U) /*! ICR18 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) #define GPIO_ICR2_ICR19_MASK (0xC0U) #define GPIO_ICR2_ICR19_SHIFT (6U) /*! ICR19 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) #define GPIO_ICR2_ICR20_MASK (0x300U) #define GPIO_ICR2_ICR20_SHIFT (8U) /*! ICR20 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) #define GPIO_ICR2_ICR21_MASK (0xC00U) #define GPIO_ICR2_ICR21_SHIFT (10U) /*! ICR21 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) #define GPIO_ICR2_ICR22_MASK (0x3000U) #define GPIO_ICR2_ICR22_SHIFT (12U) /*! ICR22 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) #define GPIO_ICR2_ICR23_MASK (0xC000U) #define GPIO_ICR2_ICR23_SHIFT (14U) /*! ICR23 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) #define GPIO_ICR2_ICR24_MASK (0x30000U) #define GPIO_ICR2_ICR24_SHIFT (16U) /*! ICR24 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) #define GPIO_ICR2_ICR25_MASK (0xC0000U) #define GPIO_ICR2_ICR25_SHIFT (18U) /*! ICR25 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) #define GPIO_ICR2_ICR26_MASK (0x300000U) #define GPIO_ICR2_ICR26_SHIFT (20U) /*! ICR26 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) #define GPIO_ICR2_ICR27_MASK (0xC00000U) #define GPIO_ICR2_ICR27_SHIFT (22U) /*! ICR27 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) #define GPIO_ICR2_ICR28_MASK (0x3000000U) #define GPIO_ICR2_ICR28_SHIFT (24U) /*! ICR28 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) #define GPIO_ICR2_ICR29_MASK (0xC000000U) #define GPIO_ICR2_ICR29_SHIFT (26U) /*! ICR29 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) #define GPIO_ICR2_ICR30_MASK (0x30000000U) #define GPIO_ICR2_ICR30_SHIFT (28U) /*! ICR30 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) #define GPIO_ICR2_ICR31_MASK (0xC0000000U) #define GPIO_ICR2_ICR31_SHIFT (30U) /*! ICR31 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) /*! @} */ /*! @name IMR - GPIO interrupt mask register */ /*! @{ */ #define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) #define GPIO_IMR_IMR_SHIFT (0U) /*! IMR * 0b00000000000000000000000000000000..Interrupt n is disabled. * 0b00000000000000000000000000000001..Interrupt n is enabled. */ #define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) /*! @} */ /*! @name ISR - GPIO interrupt status register */ /*! @{ */ #define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) #define GPIO_ISR_ISR_SHIFT (0U) #define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) /*! @} */ /*! @name EDGE_SEL - GPIO edge select register */ /*! @{ */ #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) /*! @} */ /*! * @} */ /* end of group GPIO_Register_Masks */ /* GPIO - Peripheral instance base addresses */ /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x30200000u) /** Peripheral GPIO1 base pointer */ #define GPIO1 ((GPIO_Type *)GPIO1_BASE) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x30210000u) /** Peripheral GPIO2 base pointer */ #define GPIO2 ((GPIO_Type *)GPIO2_BASE) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x30220000u) /** Peripheral GPIO3 base pointer */ #define GPIO3 ((GPIO_Type *)GPIO3_BASE) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x30230000u) /** Peripheral GPIO4 base pointer */ #define GPIO4 ((GPIO_Type *)GPIO4_BASE) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x30240000u) /** Peripheral GPIO5 base pointer */ #define GPIO5 ((GPIO_Type *)GPIO5_BASE) /** Array initializer of GPIO peripheral base addresses */ #define GPIO_BASE_ADDRS \ { \ 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE \ } /** Array initializer of GPIO peripheral base pointers */ #define GPIO_BASE_PTRS \ { \ (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 \ } /** Interrupt vectors for the GPIO peripheral type */ #define GPIO_IRQS \ { \ NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, \ GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, \ NotAvail_IRQn \ } #define GPIO_COMBINED_LOW_IRQS \ { \ NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, \ GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn \ } #define GPIO_COMBINED_HIGH_IRQS \ { \ NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, \ GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn \ } /*! * @} */ /* end of group GPIO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPMI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer * @{ */ /** GPMI - Register Layout Typedef */ typedef struct { __IO uint32_t CTRL0; /**< GPMI Control Register 0 Description, offset: 0x0 */ __IO uint32_t CTRL0_SET; /**< GPMI Control Register 0 Description, offset: 0x4 */ __IO uint32_t CTRL0_CLR; /**< GPMI Control Register 0 Description, offset: 0x8 */ __IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset: 0xC */ __IO uint32_t COMPARE; /**< GPMI Compare Register Description, offset: 0x10 */ uint8_t RESERVED_0[12]; __IO uint32_t ECCCTRL; /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */ __IO uint32_t ECCCTRL_SET; /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */ __IO uint32_t ECCCTRL_CLR; /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */ __IO uint32_t ECCCTRL_TOG; /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */ __IO uint32_t ECCCOUNT; /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */ uint8_t RESERVED_1[12]; __IO uint32_t PAYLOAD; /**< GPMI Payload Address Register Description, offset: 0x40 */ uint8_t RESERVED_2[12]; __IO uint32_t AUXILIARY; /**< GPMI Auxiliary Address Register Description, offset: 0x50 */ uint8_t RESERVED_3[12]; __IO uint32_t CTRL1; /**< GPMI Control Register 1 Description, offset: 0x60 */ __IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset: 0x64 */ __IO uint32_t CTRL1_CLR; /**< GPMI Control Register 1 Description, offset: 0x68 */ __IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset: 0x6C */ __IO uint32_t TIMING0; /**< GPMI Timing Register 0 Description, offset: 0x70 */ uint8_t RESERVED_4[12]; __IO uint32_t TIMING1; /**< GPMI Timing Register 1 Description, offset: 0x80 */ uint8_t RESERVED_5[12]; __IO uint32_t TIMING2; /**< GPMI Timing Register 2 Description, offset: 0x90 */ uint8_t RESERVED_6[12]; __IO uint32_t DATA; /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */ uint8_t RESERVED_7[12]; __I uint32_t STAT; /**< GPMI Status Register Description, offset: 0xB0 */ uint8_t RESERVED_8[12]; __I uint32_t DEBUGr; /**< GPMI Debug Information Register Description, offset: 0xC0 */ uint8_t RESERVED_9[12]; __I uint32_t VERSION; /**< GPMI Version Register Description, offset: 0xD0 */ uint8_t RESERVED_10[12]; __IO uint32_t DEBUG2; /**< GPMI Debug2 Information Register Description, offset: 0xE0 */ uint8_t RESERVED_11[12]; __I uint32_t DEBUG3; /**< GPMI Debug3 Information Register Description, offset: 0xF0 */ uint8_t RESERVED_12[12]; __IO uint32_t READ_DDR_DLL_CTRL; /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */ uint8_t RESERVED_13[12]; __IO uint32_t WRITE_DDR_DLL_CTRL; /**< GPMI Double Rate Write DLL Control Register Description, offset: 0x110 */ uint8_t RESERVED_14[12]; __I uint32_t READ_DDR_DLL_STS; /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */ uint8_t RESERVED_15[12]; __I uint32_t WRITE_DDR_DLL_STS; /**< GPMI Double Rate Write DLL Status Register Description, offset: 0x130 */ } GPMI_Type; /* ---------------------------------------------------------------------------- -- GPMI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPMI_Register_Masks GPMI Register Masks * @{ */ /*! @name CTRL0 - GPMI Control Register 0 Description */ /*! @{ */ #define GPMI_CTRL0_XFER_COUNT_MASK (0xFFFFU) #define GPMI_CTRL0_XFER_COUNT_SHIFT (0U) #define GPMI_CTRL0_XFER_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_XFER_COUNT_SHIFT)) & GPMI_CTRL0_XFER_COUNT_MASK) #define GPMI_CTRL0_ADDRESS_INCREMENT_MASK (0x10000U) #define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT (16U) /*! ADDRESS_INCREMENT * 0b0..Address does not increment. * 0b1..Increment address. */ #define GPMI_CTRL0_ADDRESS_INCREMENT(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_ADDRESS_INCREMENT_MASK) #define GPMI_CTRL0_ADDRESS_MASK (0xE0000U) #define GPMI_CTRL0_ADDRESS_SHIFT (17U) #define GPMI_CTRL0_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_SHIFT)) & GPMI_CTRL0_ADDRESS_MASK) #define GPMI_CTRL0_CS_MASK (0x700000U) #define GPMI_CTRL0_CS_SHIFT (20U) #define GPMI_CTRL0_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CS_SHIFT)) & GPMI_CTRL0_CS_MASK) #define GPMI_CTRL0_WORD_LENGTH_MASK (0x800000U) #define GPMI_CTRL0_WORD_LENGTH_SHIFT (23U) /*! WORD_LENGTH * 0b0..Reserved. * 0b1..8-bit Data Bus mode. */ #define GPMI_CTRL0_WORD_LENGTH(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_WORD_LENGTH_MASK) #define GPMI_CTRL0_COMMAND_MODE_MASK (0x3000000U) #define GPMI_CTRL0_COMMAND_MODE_SHIFT (24U) /*! COMMAND_MODE * 0b00..Write mode. * 0b01..Read Mode. * 0b10..Read and Compare Mode (setting sense flop). * 0b11..Wait for Ready. */ #define GPMI_CTRL0_COMMAND_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_COMMAND_MODE_MASK) #define GPMI_CTRL0_UDMA_MASK (0x4000000U) #define GPMI_CTRL0_UDMA_SHIFT (26U) /*! UDMA * 0b0..Use ATA-PIO mode on the external bus. * 0b1..Use ATA-Ultra DMA mode on the external bus. */ #define GPMI_CTRL0_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_UDMA_SHIFT)) & GPMI_CTRL0_UDMA_MASK) #define GPMI_CTRL0_LOCK_CS_MASK (0x8000000U) #define GPMI_CTRL0_LOCK_CS_SHIFT (27U) #define GPMI_CTRL0_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_LOCK_CS_SHIFT)) & GPMI_CTRL0_LOCK_CS_MASK) #define GPMI_CTRL0_DEV_IRQ_EN_MASK (0x10000000U) #define GPMI_CTRL0_DEV_IRQ_EN_SHIFT (28U) #define GPMI_CTRL0_DEV_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_DEV_IRQ_EN_MASK) #define GPMI_CTRL0_RUN_MASK (0x20000000U) #define GPMI_CTRL0_RUN_SHIFT (29U) #define GPMI_CTRL0_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_RUN_SHIFT)) & GPMI_CTRL0_RUN_MASK) #define GPMI_CTRL0_CLKGATE_MASK (0x40000000U) #define GPMI_CTRL0_CLKGATE_SHIFT (30U) #define GPMI_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLKGATE_SHIFT)) & GPMI_CTRL0_CLKGATE_MASK) #define GPMI_CTRL0_SFTRST_MASK (0x80000000U) #define GPMI_CTRL0_SFTRST_SHIFT (31U) #define GPMI_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SFTRST_SHIFT)) & GPMI_CTRL0_SFTRST_MASK) /*! @} */ /*! @name CTRL0_SET - GPMI Control Register 0 Description */ /*! @{ */ #define GPMI_CTRL0_SET_XFER_COUNT_MASK (0xFFFFU) #define GPMI_CTRL0_SET_XFER_COUNT_SHIFT (0U) #define GPMI_CTRL0_SET_XFER_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_XFER_COUNT_SHIFT)) & GPMI_CTRL0_SET_XFER_COUNT_MASK) #define GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK (0x10000U) #define GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT (16U) /*! ADDRESS_INCREMENT * 0b0..Address does not increment. * 0b1..Increment address. */ #define GPMI_CTRL0_SET_ADDRESS_INCREMENT(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK) #define GPMI_CTRL0_SET_ADDRESS_MASK (0xE0000U) #define GPMI_CTRL0_SET_ADDRESS_SHIFT (17U) #define GPMI_CTRL0_SET_ADDRESS(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_MASK) #define GPMI_CTRL0_SET_CS_MASK (0x700000U) #define GPMI_CTRL0_SET_CS_SHIFT (20U) #define GPMI_CTRL0_SET_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CS_SHIFT)) & GPMI_CTRL0_SET_CS_MASK) #define GPMI_CTRL0_SET_WORD_LENGTH_MASK (0x800000U) #define GPMI_CTRL0_SET_WORD_LENGTH_SHIFT (23U) /*! WORD_LENGTH * 0b0..Reserved. * 0b1..8-bit Data Bus mode. */ #define GPMI_CTRL0_SET_WORD_LENGTH(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_SET_WORD_LENGTH_MASK) #define GPMI_CTRL0_SET_COMMAND_MODE_MASK (0x3000000U) #define GPMI_CTRL0_SET_COMMAND_MODE_SHIFT (24U) /*! COMMAND_MODE * 0b00..Write mode. * 0b01..Read Mode. * 0b10..Read and Compare Mode (setting sense flop). * 0b11..Wait for Ready. */ #define GPMI_CTRL0_SET_COMMAND_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_SET_COMMAND_MODE_MASK) #define GPMI_CTRL0_SET_UDMA_MASK (0x4000000U) #define GPMI_CTRL0_SET_UDMA_SHIFT (26U) /*! UDMA * 0b0..Use ATA-PIO mode on the external bus. * 0b1..Use ATA-Ultra DMA mode on the external bus. */ #define GPMI_CTRL0_SET_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_UDMA_SHIFT)) & GPMI_CTRL0_SET_UDMA_MASK) #define GPMI_CTRL0_SET_LOCK_CS_MASK (0x8000000U) #define GPMI_CTRL0_SET_LOCK_CS_SHIFT (27U) #define GPMI_CTRL0_SET_LOCK_CS(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_LOCK_CS_SHIFT)) & GPMI_CTRL0_SET_LOCK_CS_MASK) #define GPMI_CTRL0_SET_DEV_IRQ_EN_MASK (0x10000000U) #define GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT (28U) #define GPMI_CTRL0_SET_DEV_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_SET_DEV_IRQ_EN_MASK) #define GPMI_CTRL0_SET_RUN_MASK (0x20000000U) #define GPMI_CTRL0_SET_RUN_SHIFT (29U) #define GPMI_CTRL0_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_RUN_SHIFT)) & GPMI_CTRL0_SET_RUN_MASK) #define GPMI_CTRL0_SET_CLKGATE_MASK (0x40000000U) #define GPMI_CTRL0_SET_CLKGATE_SHIFT (30U) #define GPMI_CTRL0_SET_CLKGATE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CLKGATE_SHIFT)) & GPMI_CTRL0_SET_CLKGATE_MASK) #define GPMI_CTRL0_SET_SFTRST_MASK (0x80000000U) #define GPMI_CTRL0_SET_SFTRST_SHIFT (31U) #define GPMI_CTRL0_SET_SFTRST(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_SFTRST_SHIFT)) & GPMI_CTRL0_SET_SFTRST_MASK) /*! @} */ /*! @name CTRL0_CLR - GPMI Control Register 0 Description */ /*! @{ */ #define GPMI_CTRL0_CLR_XFER_COUNT_MASK (0xFFFFU) #define GPMI_CTRL0_CLR_XFER_COUNT_SHIFT (0U) #define GPMI_CTRL0_CLR_XFER_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_XFER_COUNT_SHIFT)) & GPMI_CTRL0_CLR_XFER_COUNT_MASK) #define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK (0x10000U) #define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT (16U) /*! ADDRESS_INCREMENT * 0b0..Address does not increment. * 0b1..Increment address. */ #define GPMI_CTRL0_CLR_ADDRESS_INCREMENT(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK) #define GPMI_CTRL0_CLR_ADDRESS_MASK (0xE0000U) #define GPMI_CTRL0_CLR_ADDRESS_SHIFT (17U) #define GPMI_CTRL0_CLR_ADDRESS(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_MASK) #define GPMI_CTRL0_CLR_CS_MASK (0x700000U) #define GPMI_CTRL0_CLR_CS_SHIFT (20U) #define GPMI_CTRL0_CLR_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CS_SHIFT)) & GPMI_CTRL0_CLR_CS_MASK) #define GPMI_CTRL0_CLR_WORD_LENGTH_MASK (0x800000U) #define GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT (23U) /*! WORD_LENGTH * 0b0..Reserved. * 0b1..8-bit Data Bus mode. */ #define GPMI_CTRL0_CLR_WORD_LENGTH(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_CLR_WORD_LENGTH_MASK) #define GPMI_CTRL0_CLR_COMMAND_MODE_MASK (0x3000000U) #define GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT (24U) /*! COMMAND_MODE * 0b00..Write mode. * 0b01..Read Mode. * 0b10..Read and Compare Mode (setting sense flop). * 0b11..Wait for Ready. */ #define GPMI_CTRL0_CLR_COMMAND_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_CLR_COMMAND_MODE_MASK) #define GPMI_CTRL0_CLR_UDMA_MASK (0x4000000U) #define GPMI_CTRL0_CLR_UDMA_SHIFT (26U) /*! UDMA * 0b0..Use ATA-PIO mode on the external bus. * 0b1..Use ATA-Ultra DMA mode on the external bus. */ #define GPMI_CTRL0_CLR_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_UDMA_SHIFT)) & GPMI_CTRL0_CLR_UDMA_MASK) #define GPMI_CTRL0_CLR_LOCK_CS_MASK (0x8000000U) #define GPMI_CTRL0_CLR_LOCK_CS_SHIFT (27U) #define GPMI_CTRL0_CLR_LOCK_CS(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_LOCK_CS_SHIFT)) & GPMI_CTRL0_CLR_LOCK_CS_MASK) #define GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK (0x10000000U) #define GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT (28U) #define GPMI_CTRL0_CLR_DEV_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK) #define GPMI_CTRL0_CLR_RUN_MASK (0x20000000U) #define GPMI_CTRL0_CLR_RUN_SHIFT (29U) #define GPMI_CTRL0_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_RUN_SHIFT)) & GPMI_CTRL0_CLR_RUN_MASK) #define GPMI_CTRL0_CLR_CLKGATE_MASK (0x40000000U) #define GPMI_CTRL0_CLR_CLKGATE_SHIFT (30U) #define GPMI_CTRL0_CLR_CLKGATE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CLKGATE_SHIFT)) & GPMI_CTRL0_CLR_CLKGATE_MASK) #define GPMI_CTRL0_CLR_SFTRST_MASK (0x80000000U) #define GPMI_CTRL0_CLR_SFTRST_SHIFT (31U) #define GPMI_CTRL0_CLR_SFTRST(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_SFTRST_SHIFT)) & GPMI_CTRL0_CLR_SFTRST_MASK) /*! @} */ /*! @name CTRL0_TOG - GPMI Control Register 0 Description */ /*! @{ */ #define GPMI_CTRL0_TOG_XFER_COUNT_MASK (0xFFFFU) #define GPMI_CTRL0_TOG_XFER_COUNT_SHIFT (0U) #define GPMI_CTRL0_TOG_XFER_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_XFER_COUNT_SHIFT)) & GPMI_CTRL0_TOG_XFER_COUNT_MASK) #define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK (0x10000U) #define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT (16U) /*! ADDRESS_INCREMENT * 0b0..Address does not increment. * 0b1..Increment address. */ #define GPMI_CTRL0_TOG_ADDRESS_INCREMENT(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK) #define GPMI_CTRL0_TOG_ADDRESS_MASK (0xE0000U) #define GPMI_CTRL0_TOG_ADDRESS_SHIFT (17U) #define GPMI_CTRL0_TOG_ADDRESS(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_MASK) #define GPMI_CTRL0_TOG_CS_MASK (0x700000U) #define GPMI_CTRL0_TOG_CS_SHIFT (20U) #define GPMI_CTRL0_TOG_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CS_SHIFT)) & GPMI_CTRL0_TOG_CS_MASK) #define GPMI_CTRL0_TOG_WORD_LENGTH_MASK (0x800000U) #define GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT (23U) /*! WORD_LENGTH * 0b0..Reserved. * 0b1..8-bit Data Bus mode. */ #define GPMI_CTRL0_TOG_WORD_LENGTH(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_TOG_WORD_LENGTH_MASK) #define GPMI_CTRL0_TOG_COMMAND_MODE_MASK (0x3000000U) #define GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT (24U) /*! COMMAND_MODE * 0b00..Write mode. * 0b01..Read Mode. * 0b10..Read and Compare Mode (setting sense flop). * 0b11..Wait for Ready. */ #define GPMI_CTRL0_TOG_COMMAND_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_TOG_COMMAND_MODE_MASK) #define GPMI_CTRL0_TOG_UDMA_MASK (0x4000000U) #define GPMI_CTRL0_TOG_UDMA_SHIFT (26U) /*! UDMA * 0b0..Use ATA-PIO mode on the external bus. * 0b1..Use ATA-Ultra DMA mode on the external bus. */ #define GPMI_CTRL0_TOG_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_UDMA_SHIFT)) & GPMI_CTRL0_TOG_UDMA_MASK) #define GPMI_CTRL0_TOG_LOCK_CS_MASK (0x8000000U) #define GPMI_CTRL0_TOG_LOCK_CS_SHIFT (27U) #define GPMI_CTRL0_TOG_LOCK_CS(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_LOCK_CS_SHIFT)) & GPMI_CTRL0_TOG_LOCK_CS_MASK) #define GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK (0x10000000U) #define GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT (28U) #define GPMI_CTRL0_TOG_DEV_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK) #define GPMI_CTRL0_TOG_RUN_MASK (0x20000000U) #define GPMI_CTRL0_TOG_RUN_SHIFT (29U) #define GPMI_CTRL0_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_RUN_SHIFT)) & GPMI_CTRL0_TOG_RUN_MASK) #define GPMI_CTRL0_TOG_CLKGATE_MASK (0x40000000U) #define GPMI_CTRL0_TOG_CLKGATE_SHIFT (30U) #define GPMI_CTRL0_TOG_CLKGATE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CLKGATE_SHIFT)) & GPMI_CTRL0_TOG_CLKGATE_MASK) #define GPMI_CTRL0_TOG_SFTRST_MASK (0x80000000U) #define GPMI_CTRL0_TOG_SFTRST_SHIFT (31U) #define GPMI_CTRL0_TOG_SFTRST(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_SFTRST_SHIFT)) & GPMI_CTRL0_TOG_SFTRST_MASK) /*! @} */ /*! @name COMPARE - GPMI Compare Register Description */ /*! @{ */ #define GPMI_COMPARE_REFERENCE_MASK (0xFFFFU) #define GPMI_COMPARE_REFERENCE_SHIFT (0U) #define GPMI_COMPARE_REFERENCE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_REFERENCE_SHIFT)) & GPMI_COMPARE_REFERENCE_MASK) #define GPMI_COMPARE_MASK_MASK (0xFFFF0000U) #define GPMI_COMPARE_MASK_SHIFT (16U) #define GPMI_COMPARE_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_MASK_SHIFT)) & GPMI_COMPARE_MASK_MASK) /*! @} */ /*! @name ECCCTRL - GPMI Integrated ECC Control Register Description */ /*! @{ */ #define GPMI_ECCCTRL_BUFFER_MASK_MASK (0x1FFU) #define GPMI_ECCCTRL_BUFFER_MASK_SHIFT (0U) #define GPMI_ECCCTRL_BUFFER_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_BUFFER_MASK_MASK) #define GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK (0x600U) #define GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT (9U) /*! RANDOMIZER_TYPE * 0b00..Type 0 * 0b01..Type 1 */ #define GPMI_ECCCTRL_RANDOMIZER_TYPE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK) #define GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK (0x800U) #define GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT (11U) /*! RANDOMIZER_ENABLE * 0b0..disable * 0b1..enable */ #define GPMI_ECCCTRL_RANDOMIZER_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK) #define GPMI_ECCCTRL_ENABLE_ECC_MASK (0x1000U) #define GPMI_ECCCTRL_ENABLE_ECC_SHIFT (12U) #define GPMI_ECCCTRL_ENABLE_ECC(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_ENABLE_ECC_MASK) #define GPMI_ECCCTRL_ECC_CMD_MASK (0x6000U) #define GPMI_ECCCTRL_ECC_CMD_SHIFT (13U) #define GPMI_ECCCTRL_ECC_CMD(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_ECC_CMD_MASK) #define GPMI_ECCCTRL_RSVD2_MASK (0x8000U) #define GPMI_ECCCTRL_RSVD2_SHIFT (15U) #define GPMI_ECCCTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD2_SHIFT)) & GPMI_ECCCTRL_RSVD2_MASK) #define GPMI_ECCCTRL_HANDLE_MASK (0xFFFF0000U) #define GPMI_ECCCTRL_HANDLE_SHIFT (16U) #define GPMI_ECCCTRL_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_HANDLE_SHIFT)) & GPMI_ECCCTRL_HANDLE_MASK) /*! @} */ /*! @name ECCCTRL_SET - GPMI Integrated ECC Control Register Description */ /*! @{ */ #define GPMI_ECCCTRL_SET_BUFFER_MASK_MASK (0x1FFU) #define GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT (0U) #define GPMI_ECCCTRL_SET_BUFFER_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_SET_BUFFER_MASK_MASK) #define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_MASK (0x600U) #define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_SHIFT (9U) /*! RANDOMIZER_TYPE * 0b00..Type 0 * 0b01..Type 1 */ #define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_MASK) #define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_MASK (0x800U) #define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_SHIFT (11U) /*! RANDOMIZER_ENABLE * 0b0..disable * 0b1..enable */ #define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_SHIFT)) & \ GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_MASK) #define GPMI_ECCCTRL_SET_ENABLE_ECC_MASK (0x1000U) #define GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT (12U) #define GPMI_ECCCTRL_SET_ENABLE_ECC(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_SET_ENABLE_ECC_MASK) #define GPMI_ECCCTRL_SET_ECC_CMD_MASK (0x6000U) #define GPMI_ECCCTRL_SET_ECC_CMD_SHIFT (13U) #define GPMI_ECCCTRL_SET_ECC_CMD(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_SET_ECC_CMD_MASK) #define GPMI_ECCCTRL_SET_RSVD2_MASK (0x8000U) #define GPMI_ECCCTRL_SET_RSVD2_SHIFT (15U) #define GPMI_ECCCTRL_SET_RSVD2(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RSVD2_SHIFT)) & GPMI_ECCCTRL_SET_RSVD2_MASK) #define GPMI_ECCCTRL_SET_HANDLE_MASK (0xFFFF0000U) #define GPMI_ECCCTRL_SET_HANDLE_SHIFT (16U) #define GPMI_ECCCTRL_SET_HANDLE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_HANDLE_SHIFT)) & GPMI_ECCCTRL_SET_HANDLE_MASK) /*! @} */ /*! @name ECCCTRL_CLR - GPMI Integrated ECC Control Register Description */ /*! @{ */ #define GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK (0x1FFU) #define GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT (0U) #define GPMI_ECCCTRL_CLR_BUFFER_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK) #define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_MASK (0x600U) #define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_SHIFT (9U) /*! RANDOMIZER_TYPE * 0b00..Type 0 * 0b01..Type 1 */ #define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_MASK) #define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_MASK (0x800U) #define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_SHIFT (11U) /*! RANDOMIZER_ENABLE * 0b0..disable * 0b1..enable */ #define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_SHIFT)) & \ GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_MASK) #define GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK (0x1000U) #define GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT (12U) #define GPMI_ECCCTRL_CLR_ENABLE_ECC(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK) #define GPMI_ECCCTRL_CLR_ECC_CMD_MASK (0x6000U) #define GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT (13U) #define GPMI_ECCCTRL_CLR_ECC_CMD(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_CLR_ECC_CMD_MASK) #define GPMI_ECCCTRL_CLR_RSVD2_MASK (0x8000U) #define GPMI_ECCCTRL_CLR_RSVD2_SHIFT (15U) #define GPMI_ECCCTRL_CLR_RSVD2(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RSVD2_SHIFT)) & GPMI_ECCCTRL_CLR_RSVD2_MASK) #define GPMI_ECCCTRL_CLR_HANDLE_MASK (0xFFFF0000U) #define GPMI_ECCCTRL_CLR_HANDLE_SHIFT (16U) #define GPMI_ECCCTRL_CLR_HANDLE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_HANDLE_SHIFT)) & GPMI_ECCCTRL_CLR_HANDLE_MASK) /*! @} */ /*! @name ECCCTRL_TOG - GPMI Integrated ECC Control Register Description */ /*! @{ */ #define GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK (0x1FFU) #define GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT (0U) #define GPMI_ECCCTRL_TOG_BUFFER_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK) #define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_MASK (0x600U) #define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_SHIFT (9U) /*! RANDOMIZER_TYPE * 0b00..Type 0 * 0b01..Type 1 */ #define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_MASK) #define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_MASK (0x800U) #define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_SHIFT (11U) /*! RANDOMIZER_ENABLE * 0b0..disable * 0b1..enable */ #define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_SHIFT)) & \ GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_MASK) #define GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK (0x1000U) #define GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT (12U) #define GPMI_ECCCTRL_TOG_ENABLE_ECC(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK) #define GPMI_ECCCTRL_TOG_ECC_CMD_MASK (0x6000U) #define GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT (13U) #define GPMI_ECCCTRL_TOG_ECC_CMD(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_TOG_ECC_CMD_MASK) #define GPMI_ECCCTRL_TOG_RSVD2_MASK (0x8000U) #define GPMI_ECCCTRL_TOG_RSVD2_SHIFT (15U) #define GPMI_ECCCTRL_TOG_RSVD2(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RSVD2_SHIFT)) & GPMI_ECCCTRL_TOG_RSVD2_MASK) #define GPMI_ECCCTRL_TOG_HANDLE_MASK (0xFFFF0000U) #define GPMI_ECCCTRL_TOG_HANDLE_SHIFT (16U) #define GPMI_ECCCTRL_TOG_HANDLE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_HANDLE_SHIFT)) & GPMI_ECCCTRL_TOG_HANDLE_MASK) /*! @} */ /*! @name ECCCOUNT - GPMI Integrated ECC Transfer Count Register Description */ /*! @{ */ #define GPMI_ECCCOUNT_COUNT_MASK (0xFFFFU) #define GPMI_ECCCOUNT_COUNT_SHIFT (0U) #define GPMI_ECCCOUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_COUNT_SHIFT)) & GPMI_ECCCOUNT_COUNT_MASK) #define GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK (0xFF0000U) #define GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT (16U) #define GPMI_ECCCOUNT_RANDOMIZER_PAGE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT)) & GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK) /*! @} */ /*! @name PAYLOAD - GPMI Payload Address Register Description */ /*! @{ */ #define GPMI_PAYLOAD_RSVD0_MASK (0x3U) #define GPMI_PAYLOAD_RSVD0_SHIFT (0U) #define GPMI_PAYLOAD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_RSVD0_SHIFT)) & GPMI_PAYLOAD_RSVD0_MASK) #define GPMI_PAYLOAD_ADDRESS_MASK (0xFFFFFFFCU) #define GPMI_PAYLOAD_ADDRESS_SHIFT (2U) #define GPMI_PAYLOAD_ADDRESS(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_ADDRESS_SHIFT)) & GPMI_PAYLOAD_ADDRESS_MASK) /*! @} */ /*! @name AUXILIARY - GPMI Auxiliary Address Register Description */ /*! @{ */ #define GPMI_AUXILIARY_RSVD0_MASK (0x3U) #define GPMI_AUXILIARY_RSVD0_SHIFT (0U) #define GPMI_AUXILIARY_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_RSVD0_SHIFT)) & GPMI_AUXILIARY_RSVD0_MASK) #define GPMI_AUXILIARY_ADDRESS_MASK (0xFFFFFFFCU) #define GPMI_AUXILIARY_ADDRESS_SHIFT (2U) #define GPMI_AUXILIARY_ADDRESS(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_ADDRESS_SHIFT)) & GPMI_AUXILIARY_ADDRESS_MASK) /*! @} */ /*! @name CTRL1 - GPMI Control Register 1 Description */ /*! @{ */ #define GPMI_CTRL1_GPMI_MODE_MASK (0x1U) #define GPMI_CTRL1_GPMI_MODE_SHIFT (0U) /*! GPMI_MODE * 0b0..NAND mode. * 0b1..ATA mode. */ #define GPMI_CTRL1_GPMI_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_MODE_SHIFT)) & GPMI_CTRL1_GPMI_MODE_MASK) #define GPMI_CTRL1_CAMERA_MODE_MASK (0x2U) #define GPMI_CTRL1_CAMERA_MODE_SHIFT (1U) #define GPMI_CTRL1_CAMERA_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CAMERA_MODE_MASK) #define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK (0x4U) #define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT (2U) /*! ATA_IRQRDY_POLARITY * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. */ #define GPMI_CTRL1_ATA_IRQRDY_POLARITY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK) #define GPMI_CTRL1_DEV_RESET_MASK (0x8U) #define GPMI_CTRL1_DEV_RESET_SHIFT (3U) /*! DEV_RESET * 0b0..NANDF_WP_B pin is held low (asserted). * 0b1..NANDF_WP_B pin is held high (de-asserted). */ #define GPMI_CTRL1_DEV_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_RESET_SHIFT)) & GPMI_CTRL1_DEV_RESET_MASK) #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & \ GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK) #define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK (0x80U) #define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT (7U) #define GPMI_CTRL1_ABORT_WAIT_REQUEST(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK) #define GPMI_CTRL1_BURST_EN_MASK (0x100U) #define GPMI_CTRL1_BURST_EN_SHIFT (8U) #define GPMI_CTRL1_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BURST_EN_SHIFT)) & GPMI_CTRL1_BURST_EN_MASK) #define GPMI_CTRL1_TIMEOUT_IRQ_MASK (0x200U) #define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT (9U) #define GPMI_CTRL1_TIMEOUT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_MASK) #define GPMI_CTRL1_DEV_IRQ_MASK (0x400U) #define GPMI_CTRL1_DEV_IRQ_SHIFT (10U) #define GPMI_CTRL1_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_IRQ_SHIFT)) & GPMI_CTRL1_DEV_IRQ_MASK) #define GPMI_CTRL1_DMA2ECC_MODE_MASK (0x800U) #define GPMI_CTRL1_DMA2ECC_MODE_SHIFT (11U) #define GPMI_CTRL1_DMA2ECC_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_DMA2ECC_MODE_MASK) #define GPMI_CTRL1_RDN_DELAY_MASK (0xF000U) #define GPMI_CTRL1_RDN_DELAY_SHIFT (12U) #define GPMI_CTRL1_RDN_DELAY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RDN_DELAY_SHIFT)) & GPMI_CTRL1_RDN_DELAY_MASK) #define GPMI_CTRL1_HALF_PERIOD_MASK (0x10000U) #define GPMI_CTRL1_HALF_PERIOD_SHIFT (16U) #define GPMI_CTRL1_HALF_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_HALF_PERIOD_MASK) #define GPMI_CTRL1_DLL_ENABLE_MASK (0x20000U) #define GPMI_CTRL1_DLL_ENABLE_SHIFT (17U) #define GPMI_CTRL1_DLL_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_DLL_ENABLE_MASK) #define GPMI_CTRL1_BCH_MODE_MASK (0x40000U) #define GPMI_CTRL1_BCH_MODE_SHIFT (18U) #define GPMI_CTRL1_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BCH_MODE_SHIFT)) & GPMI_CTRL1_BCH_MODE_MASK) #define GPMI_CTRL1_GANGED_RDYBUSY_MASK (0x80000U) #define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT (19U) #define GPMI_CTRL1_GANGED_RDYBUSY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_GANGED_RDYBUSY_MASK) #define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK (0x100000U) #define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT (20U) #define GPMI_CTRL1_TIMEOUT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK) #define GPMI_CTRL1_TEST_TRIGGER_MASK (0x200000U) #define GPMI_CTRL1_TEST_TRIGGER_SHIFT (21U) /*! TEST_TRIGGER * 0b0..Disable * 0b1..Enable */ #define GPMI_CTRL1_TEST_TRIGGER(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TEST_TRIGGER_MASK) #define GPMI_CTRL1_WRN_DLY_SEL_MASK (0xC00000U) #define GPMI_CTRL1_WRN_DLY_SEL_SHIFT (22U) #define GPMI_CTRL1_WRN_DLY_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_WRN_DLY_SEL_MASK) #define GPMI_CTRL1_DECOUPLE_CS_MASK (0x1000000U) #define GPMI_CTRL1_DECOUPLE_CS_SHIFT (24U) #define GPMI_CTRL1_DECOUPLE_CS(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_DECOUPLE_CS_MASK) #define GPMI_CTRL1_SSYNCMODE_MASK (0x2000000U) #define GPMI_CTRL1_SSYNCMODE_SHIFT (25U) #define GPMI_CTRL1_SSYNCMODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SSYNCMODE_MASK) #define GPMI_CTRL1_UPDATE_CS_MASK (0x4000000U) #define GPMI_CTRL1_UPDATE_CS_SHIFT (26U) #define GPMI_CTRL1_UPDATE_CS(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_UPDATE_CS_SHIFT)) & GPMI_CTRL1_UPDATE_CS_MASK) #define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK (0x8000000U) #define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT (27U) /*! GPMI_CLK_DIV2_EN * 0b0..internal factor-2 clock divider is disabled * 0b1..internal factor-2 clock divider is enabled. */ #define GPMI_CTRL1_GPMI_CLK_DIV2_EN(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK) #define GPMI_CTRL1_TOGGLE_MODE_MASK (0x10000000U) #define GPMI_CTRL1_TOGGLE_MODE_SHIFT (28U) #define GPMI_CTRL1_TOGGLE_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOGGLE_MODE_MASK) #define GPMI_CTRL1_WRITE_CLK_STOP_MASK (0x20000000U) #define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT (29U) #define GPMI_CTRL1_WRITE_CLK_STOP(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_WRITE_CLK_STOP_MASK) #define GPMI_CTRL1_SSYNC_CLK_STOP_MASK (0x40000000U) #define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT (30U) #define GPMI_CTRL1_SSYNC_CLK_STOP(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SSYNC_CLK_STOP_MASK) #define GPMI_CTRL1_DEV_CLK_STOP_MASK (0x80000000U) #define GPMI_CTRL1_DEV_CLK_STOP_SHIFT (31U) #define GPMI_CTRL1_DEV_CLK_STOP(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_DEV_CLK_STOP_MASK) /*! @} */ /*! @name CTRL1_SET - GPMI Control Register 1 Description */ /*! @{ */ #define GPMI_CTRL1_SET_GPMI_MODE_MASK (0x1U) #define GPMI_CTRL1_SET_GPMI_MODE_SHIFT (0U) /*! GPMI_MODE * 0b0..NAND mode. * 0b1..ATA mode. */ #define GPMI_CTRL1_SET_GPMI_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_MODE_SHIFT)) & GPMI_CTRL1_SET_GPMI_MODE_MASK) #define GPMI_CTRL1_SET_CAMERA_MODE_MASK (0x2U) #define GPMI_CTRL1_SET_CAMERA_MODE_SHIFT (1U) #define GPMI_CTRL1_SET_CAMERA_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_SET_CAMERA_MODE_MASK) #define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK (0x4U) #define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT (2U) /*! ATA_IRQRDY_POLARITY * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. */ #define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT)) & \ GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK) #define GPMI_CTRL1_SET_DEV_RESET_MASK (0x8U) #define GPMI_CTRL1_SET_DEV_RESET_SHIFT (3U) /*! DEV_RESET * 0b0..NANDF_WP_B pin is held low (asserted). * 0b1..NANDF_WP_B pin is held high (de-asserted). */ #define GPMI_CTRL1_SET_DEV_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_RESET_SHIFT)) & GPMI_CTRL1_SET_DEV_RESET_MASK) #define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) #define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) #define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & \ GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK) #define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK (0x80U) #define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT (7U) #define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK) #define GPMI_CTRL1_SET_BURST_EN_MASK (0x100U) #define GPMI_CTRL1_SET_BURST_EN_SHIFT (8U) #define GPMI_CTRL1_SET_BURST_EN(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BURST_EN_SHIFT)) & GPMI_CTRL1_SET_BURST_EN_MASK) #define GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK (0x200U) #define GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT (9U) #define GPMI_CTRL1_SET_TIMEOUT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK) #define GPMI_CTRL1_SET_DEV_IRQ_MASK (0x400U) #define GPMI_CTRL1_SET_DEV_IRQ_SHIFT (10U) #define GPMI_CTRL1_SET_DEV_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_IRQ_SHIFT)) & GPMI_CTRL1_SET_DEV_IRQ_MASK) #define GPMI_CTRL1_SET_DMA2ECC_MODE_MASK (0x800U) #define GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT (11U) #define GPMI_CTRL1_SET_DMA2ECC_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_SET_DMA2ECC_MODE_MASK) #define GPMI_CTRL1_SET_RDN_DELAY_MASK (0xF000U) #define GPMI_CTRL1_SET_RDN_DELAY_SHIFT (12U) #define GPMI_CTRL1_SET_RDN_DELAY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_RDN_DELAY_SHIFT)) & GPMI_CTRL1_SET_RDN_DELAY_MASK) #define GPMI_CTRL1_SET_HALF_PERIOD_MASK (0x10000U) #define GPMI_CTRL1_SET_HALF_PERIOD_SHIFT (16U) #define GPMI_CTRL1_SET_HALF_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_SET_HALF_PERIOD_MASK) #define GPMI_CTRL1_SET_DLL_ENABLE_MASK (0x20000U) #define GPMI_CTRL1_SET_DLL_ENABLE_SHIFT (17U) #define GPMI_CTRL1_SET_DLL_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_SET_DLL_ENABLE_MASK) #define GPMI_CTRL1_SET_BCH_MODE_MASK (0x40000U) #define GPMI_CTRL1_SET_BCH_MODE_SHIFT (18U) #define GPMI_CTRL1_SET_BCH_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BCH_MODE_SHIFT)) & GPMI_CTRL1_SET_BCH_MODE_MASK) #define GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK (0x80000U) #define GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT (19U) #define GPMI_CTRL1_SET_GANGED_RDYBUSY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK) #define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK (0x100000U) #define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT (20U) #define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK) #define GPMI_CTRL1_SET_TEST_TRIGGER_MASK (0x200000U) #define GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT (21U) /*! TEST_TRIGGER * 0b0..Disable * 0b1..Enable */ #define GPMI_CTRL1_SET_TEST_TRIGGER(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_SET_TEST_TRIGGER_MASK) #define GPMI_CTRL1_SET_WRN_DLY_SEL_MASK (0xC00000U) #define GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT (22U) #define GPMI_CTRL1_SET_WRN_DLY_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_SET_WRN_DLY_SEL_MASK) #define GPMI_CTRL1_SET_DECOUPLE_CS_MASK (0x1000000U) #define GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT (24U) #define GPMI_CTRL1_SET_DECOUPLE_CS(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_SET_DECOUPLE_CS_MASK) #define GPMI_CTRL1_SET_SSYNCMODE_MASK (0x2000000U) #define GPMI_CTRL1_SET_SSYNCMODE_SHIFT (25U) #define GPMI_CTRL1_SET_SSYNCMODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SET_SSYNCMODE_MASK) #define GPMI_CTRL1_SET_UPDATE_CS_MASK (0x4000000U) #define GPMI_CTRL1_SET_UPDATE_CS_SHIFT (26U) #define GPMI_CTRL1_SET_UPDATE_CS(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_UPDATE_CS_SHIFT)) & GPMI_CTRL1_SET_UPDATE_CS_MASK) #define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK (0x8000000U) #define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT (27U) /*! GPMI_CLK_DIV2_EN * 0b0..internal factor-2 clock divider is disabled * 0b1..internal factor-2 clock divider is enabled. */ #define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK) #define GPMI_CTRL1_SET_TOGGLE_MODE_MASK (0x10000000U) #define GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT (28U) #define GPMI_CTRL1_SET_TOGGLE_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_SET_TOGGLE_MODE_MASK) #define GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK (0x20000000U) #define GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT (29U) #define GPMI_CTRL1_SET_WRITE_CLK_STOP(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK) #define GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK (0x40000000U) #define GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT (30U) #define GPMI_CTRL1_SET_SSYNC_CLK_STOP(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK) #define GPMI_CTRL1_SET_DEV_CLK_STOP_MASK (0x80000000U) #define GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT (31U) #define GPMI_CTRL1_SET_DEV_CLK_STOP(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_DEV_CLK_STOP_MASK) /*! @} */ /*! @name CTRL1_CLR - GPMI Control Register 1 Description */ /*! @{ */ #define GPMI_CTRL1_CLR_GPMI_MODE_MASK (0x1U) #define GPMI_CTRL1_CLR_GPMI_MODE_SHIFT (0U) /*! GPMI_MODE * 0b0..NAND mode. * 0b1..ATA mode. */ #define GPMI_CTRL1_CLR_GPMI_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_MODE_SHIFT)) & GPMI_CTRL1_CLR_GPMI_MODE_MASK) #define GPMI_CTRL1_CLR_CAMERA_MODE_MASK (0x2U) #define GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT (1U) #define GPMI_CTRL1_CLR_CAMERA_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CLR_CAMERA_MODE_MASK) #define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK (0x4U) #define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT (2U) /*! ATA_IRQRDY_POLARITY * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. */ #define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT)) & \ GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK) #define GPMI_CTRL1_CLR_DEV_RESET_MASK (0x8U) #define GPMI_CTRL1_CLR_DEV_RESET_SHIFT (3U) /*! DEV_RESET * 0b0..NANDF_WP_B pin is held low (asserted). * 0b1..NANDF_WP_B pin is held high (de-asserted). */ #define GPMI_CTRL1_CLR_DEV_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_RESET_SHIFT)) & GPMI_CTRL1_CLR_DEV_RESET_MASK) #define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) #define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) #define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & \ GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK) #define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK (0x80U) #define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT (7U) #define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK) #define GPMI_CTRL1_CLR_BURST_EN_MASK (0x100U) #define GPMI_CTRL1_CLR_BURST_EN_SHIFT (8U) #define GPMI_CTRL1_CLR_BURST_EN(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BURST_EN_SHIFT)) & GPMI_CTRL1_CLR_BURST_EN_MASK) #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK (0x200U) #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT (9U) #define GPMI_CTRL1_CLR_TIMEOUT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK) #define GPMI_CTRL1_CLR_DEV_IRQ_MASK (0x400U) #define GPMI_CTRL1_CLR_DEV_IRQ_SHIFT (10U) #define GPMI_CTRL1_CLR_DEV_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_IRQ_SHIFT)) & GPMI_CTRL1_CLR_DEV_IRQ_MASK) #define GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK (0x800U) #define GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT (11U) #define GPMI_CTRL1_CLR_DMA2ECC_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK) #define GPMI_CTRL1_CLR_RDN_DELAY_MASK (0xF000U) #define GPMI_CTRL1_CLR_RDN_DELAY_SHIFT (12U) #define GPMI_CTRL1_CLR_RDN_DELAY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_RDN_DELAY_SHIFT)) & GPMI_CTRL1_CLR_RDN_DELAY_MASK) #define GPMI_CTRL1_CLR_HALF_PERIOD_MASK (0x10000U) #define GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT (16U) #define GPMI_CTRL1_CLR_HALF_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_CLR_HALF_PERIOD_MASK) #define GPMI_CTRL1_CLR_DLL_ENABLE_MASK (0x20000U) #define GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT (17U) #define GPMI_CTRL1_CLR_DLL_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_CLR_DLL_ENABLE_MASK) #define GPMI_CTRL1_CLR_BCH_MODE_MASK (0x40000U) #define GPMI_CTRL1_CLR_BCH_MODE_SHIFT (18U) #define GPMI_CTRL1_CLR_BCH_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BCH_MODE_SHIFT)) & GPMI_CTRL1_CLR_BCH_MODE_MASK) #define GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK (0x80000U) #define GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT (19U) #define GPMI_CTRL1_CLR_GANGED_RDYBUSY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK) #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK (0x100000U) #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT (20U) #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK) #define GPMI_CTRL1_CLR_TEST_TRIGGER_MASK (0x200000U) #define GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT (21U) /*! TEST_TRIGGER * 0b0..Disable * 0b1..Enable */ #define GPMI_CTRL1_CLR_TEST_TRIGGER(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_CLR_TEST_TRIGGER_MASK) #define GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK (0xC00000U) #define GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT (22U) #define GPMI_CTRL1_CLR_WRN_DLY_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK) #define GPMI_CTRL1_CLR_DECOUPLE_CS_MASK (0x1000000U) #define GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT (24U) #define GPMI_CTRL1_CLR_DECOUPLE_CS(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_CLR_DECOUPLE_CS_MASK) #define GPMI_CTRL1_CLR_SSYNCMODE_MASK (0x2000000U) #define GPMI_CTRL1_CLR_SSYNCMODE_SHIFT (25U) #define GPMI_CTRL1_CLR_SSYNCMODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNCMODE_SHIFT)) & GPMI_CTRL1_CLR_SSYNCMODE_MASK) #define GPMI_CTRL1_CLR_UPDATE_CS_MASK (0x4000000U) #define GPMI_CTRL1_CLR_UPDATE_CS_SHIFT (26U) #define GPMI_CTRL1_CLR_UPDATE_CS(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_UPDATE_CS_SHIFT)) & GPMI_CTRL1_CLR_UPDATE_CS_MASK) #define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK (0x8000000U) #define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT (27U) /*! GPMI_CLK_DIV2_EN * 0b0..internal factor-2 clock divider is disabled * 0b1..internal factor-2 clock divider is enabled. */ #define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK) #define GPMI_CTRL1_CLR_TOGGLE_MODE_MASK (0x10000000U) #define GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT (28U) #define GPMI_CTRL1_CLR_TOGGLE_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_CLR_TOGGLE_MODE_MASK) #define GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK (0x20000000U) #define GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT (29U) #define GPMI_CTRL1_CLR_WRITE_CLK_STOP(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK) #define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK (0x40000000U) #define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT (30U) #define GPMI_CTRL1_CLR_SSYNC_CLK_STOP(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK) #define GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK (0x80000000U) #define GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT (31U) #define GPMI_CTRL1_CLR_DEV_CLK_STOP(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK) /*! @} */ /*! @name CTRL1_TOG - GPMI Control Register 1 Description */ /*! @{ */ #define GPMI_CTRL1_TOG_GPMI_MODE_MASK (0x1U) #define GPMI_CTRL1_TOG_GPMI_MODE_SHIFT (0U) /*! GPMI_MODE * 0b0..NAND mode. * 0b1..ATA mode. */ #define GPMI_CTRL1_TOG_GPMI_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_MODE_SHIFT)) & GPMI_CTRL1_TOG_GPMI_MODE_MASK) #define GPMI_CTRL1_TOG_CAMERA_MODE_MASK (0x2U) #define GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT (1U) #define GPMI_CTRL1_TOG_CAMERA_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_TOG_CAMERA_MODE_MASK) #define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK (0x4U) #define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT (2U) /*! ATA_IRQRDY_POLARITY * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. */ #define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT)) & \ GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK) #define GPMI_CTRL1_TOG_DEV_RESET_MASK (0x8U) #define GPMI_CTRL1_TOG_DEV_RESET_SHIFT (3U) /*! DEV_RESET * 0b0..NANDF_WP_B pin is held low (asserted). * 0b1..NANDF_WP_B pin is held high (de-asserted). */ #define GPMI_CTRL1_TOG_DEV_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_RESET_SHIFT)) & GPMI_CTRL1_TOG_DEV_RESET_MASK) #define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) #define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) #define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & \ GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK) #define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK (0x80U) #define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT (7U) #define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK) #define GPMI_CTRL1_TOG_BURST_EN_MASK (0x100U) #define GPMI_CTRL1_TOG_BURST_EN_SHIFT (8U) #define GPMI_CTRL1_TOG_BURST_EN(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BURST_EN_SHIFT)) & GPMI_CTRL1_TOG_BURST_EN_MASK) #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK (0x200U) #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT (9U) #define GPMI_CTRL1_TOG_TIMEOUT_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK) #define GPMI_CTRL1_TOG_DEV_IRQ_MASK (0x400U) #define GPMI_CTRL1_TOG_DEV_IRQ_SHIFT (10U) #define GPMI_CTRL1_TOG_DEV_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_IRQ_SHIFT)) & GPMI_CTRL1_TOG_DEV_IRQ_MASK) #define GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK (0x800U) #define GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT (11U) #define GPMI_CTRL1_TOG_DMA2ECC_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK) #define GPMI_CTRL1_TOG_RDN_DELAY_MASK (0xF000U) #define GPMI_CTRL1_TOG_RDN_DELAY_SHIFT (12U) #define GPMI_CTRL1_TOG_RDN_DELAY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_RDN_DELAY_SHIFT)) & GPMI_CTRL1_TOG_RDN_DELAY_MASK) #define GPMI_CTRL1_TOG_HALF_PERIOD_MASK (0x10000U) #define GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT (16U) #define GPMI_CTRL1_TOG_HALF_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_TOG_HALF_PERIOD_MASK) #define GPMI_CTRL1_TOG_DLL_ENABLE_MASK (0x20000U) #define GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT (17U) #define GPMI_CTRL1_TOG_DLL_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_TOG_DLL_ENABLE_MASK) #define GPMI_CTRL1_TOG_BCH_MODE_MASK (0x40000U) #define GPMI_CTRL1_TOG_BCH_MODE_SHIFT (18U) #define GPMI_CTRL1_TOG_BCH_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BCH_MODE_SHIFT)) & GPMI_CTRL1_TOG_BCH_MODE_MASK) #define GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK (0x80000U) #define GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT (19U) #define GPMI_CTRL1_TOG_GANGED_RDYBUSY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK) #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK (0x100000U) #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT (20U) #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK) #define GPMI_CTRL1_TOG_TEST_TRIGGER_MASK (0x200000U) #define GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT (21U) /*! TEST_TRIGGER * 0b0..Disable * 0b1..Enable */ #define GPMI_CTRL1_TOG_TEST_TRIGGER(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TOG_TEST_TRIGGER_MASK) #define GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK (0xC00000U) #define GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT (22U) #define GPMI_CTRL1_TOG_WRN_DLY_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK) #define GPMI_CTRL1_TOG_DECOUPLE_CS_MASK (0x1000000U) #define GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT (24U) #define GPMI_CTRL1_TOG_DECOUPLE_CS(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_TOG_DECOUPLE_CS_MASK) #define GPMI_CTRL1_TOG_SSYNCMODE_MASK (0x2000000U) #define GPMI_CTRL1_TOG_SSYNCMODE_SHIFT (25U) #define GPMI_CTRL1_TOG_SSYNCMODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNCMODE_SHIFT)) & GPMI_CTRL1_TOG_SSYNCMODE_MASK) #define GPMI_CTRL1_TOG_UPDATE_CS_MASK (0x4000000U) #define GPMI_CTRL1_TOG_UPDATE_CS_SHIFT (26U) #define GPMI_CTRL1_TOG_UPDATE_CS(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_UPDATE_CS_SHIFT)) & GPMI_CTRL1_TOG_UPDATE_CS_MASK) #define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK (0x8000000U) #define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT (27U) /*! GPMI_CLK_DIV2_EN * 0b0..internal factor-2 clock divider is disabled * 0b1..internal factor-2 clock divider is enabled. */ #define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK) #define GPMI_CTRL1_TOG_TOGGLE_MODE_MASK (0x10000000U) #define GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT (28U) #define GPMI_CTRL1_TOG_TOGGLE_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOG_TOGGLE_MODE_MASK) #define GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK (0x20000000U) #define GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT (29U) #define GPMI_CTRL1_TOG_WRITE_CLK_STOP(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK) #define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK (0x40000000U) #define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT (30U) #define GPMI_CTRL1_TOG_SSYNC_CLK_STOP(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK) #define GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK (0x80000000U) #define GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT (31U) #define GPMI_CTRL1_TOG_DEV_CLK_STOP(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK) /*! @} */ /*! @name TIMING0 - GPMI Timing Register 0 Description */ /*! @{ */ #define GPMI_TIMING0_DATA_SETUP_MASK (0xFFU) #define GPMI_TIMING0_DATA_SETUP_SHIFT (0U) #define GPMI_TIMING0_DATA_SETUP(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_SETUP_SHIFT)) & GPMI_TIMING0_DATA_SETUP_MASK) #define GPMI_TIMING0_DATA_HOLD_MASK (0xFF00U) #define GPMI_TIMING0_DATA_HOLD_SHIFT (8U) #define GPMI_TIMING0_DATA_HOLD(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_HOLD_SHIFT)) & GPMI_TIMING0_DATA_HOLD_MASK) #define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xFF0000U) #define GPMI_TIMING0_ADDRESS_SETUP_SHIFT (16U) #define GPMI_TIMING0_ADDRESS_SETUP(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_ADDRESS_SETUP_SHIFT)) & GPMI_TIMING0_ADDRESS_SETUP_MASK) #define GPMI_TIMING0_RSVD1_MASK (0xFF000000U) #define GPMI_TIMING0_RSVD1_SHIFT (24U) #define GPMI_TIMING0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_RSVD1_SHIFT)) & GPMI_TIMING0_RSVD1_MASK) /*! @} */ /*! @name TIMING1 - GPMI Timing Register 1 Description */ /*! @{ */ #define GPMI_TIMING1_RSVD1_MASK (0xFFFFU) #define GPMI_TIMING1_RSVD1_SHIFT (0U) #define GPMI_TIMING1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_RSVD1_SHIFT)) & GPMI_TIMING1_RSVD1_MASK) #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xFFFF0000U) #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT (16U) #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT)) & GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK) /*! @} */ /*! @name TIMING2 - GPMI Timing Register 2 Description */ /*! @{ */ #define GPMI_TIMING2_DATA_PAUSE_MASK (0xFU) #define GPMI_TIMING2_DATA_PAUSE_SHIFT (0U) #define GPMI_TIMING2_DATA_PAUSE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_DATA_PAUSE_SHIFT)) & GPMI_TIMING2_DATA_PAUSE_MASK) #define GPMI_TIMING2_CMDADD_PAUSE_MASK (0xF0U) #define GPMI_TIMING2_CMDADD_PAUSE_SHIFT (4U) #define GPMI_TIMING2_CMDADD_PAUSE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CMDADD_PAUSE_SHIFT)) & GPMI_TIMING2_CMDADD_PAUSE_MASK) #define GPMI_TIMING2_POSTAMBLE_DELAY_MASK (0xF00U) #define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT (8U) #define GPMI_TIMING2_POSTAMBLE_DELAY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_POSTAMBLE_DELAY_MASK) #define GPMI_TIMING2_PREAMBLE_DELAY_MASK (0xF000U) #define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT (12U) #define GPMI_TIMING2_PREAMBLE_DELAY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_PREAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_PREAMBLE_DELAY_MASK) #define GPMI_TIMING2_CE_DELAY_MASK (0x1F0000U) #define GPMI_TIMING2_CE_DELAY_SHIFT (16U) #define GPMI_TIMING2_CE_DELAY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CE_DELAY_SHIFT)) & GPMI_TIMING2_CE_DELAY_MASK) #define GPMI_TIMING2_RSVD0_MASK (0xE00000U) #define GPMI_TIMING2_RSVD0_SHIFT (21U) #define GPMI_TIMING2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_RSVD0_SHIFT)) & GPMI_TIMING2_RSVD0_MASK) #define GPMI_TIMING2_READ_LATENCY_MASK (0x7000000U) #define GPMI_TIMING2_READ_LATENCY_SHIFT (24U) /*! READ_LATENCY * 0b000..READ LATENCY is 0 * 0b001..READ LATENCY is 1 * 0b010..READ LATENCY is 2 * 0b011..READ LATENCY is 3 * 0b100..READ LATENCY is 4 * 0b101..READ LATENCY is 5 */ #define GPMI_TIMING2_READ_LATENCY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_READ_LATENCY_SHIFT)) & GPMI_TIMING2_READ_LATENCY_MASK) #define GPMI_TIMING2_TCR_MASK (0x18000000U) #define GPMI_TIMING2_TCR_SHIFT (27U) #define GPMI_TIMING2_TCR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TCR_SHIFT)) & GPMI_TIMING2_TCR_MASK) #define GPMI_TIMING2_TRPSTH_MASK (0xE0000000U) #define GPMI_TIMING2_TRPSTH_SHIFT (29U) #define GPMI_TIMING2_TRPSTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TRPSTH_SHIFT)) & GPMI_TIMING2_TRPSTH_MASK) /*! @} */ /*! @name DATA - GPMI DMA Data Transfer Register Description */ /*! @{ */ #define GPMI_DATA_DATA_MASK (0xFFFFFFFFU) #define GPMI_DATA_DATA_SHIFT (0U) #define GPMI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DATA_DATA_SHIFT)) & GPMI_DATA_DATA_MASK) /*! @} */ /*! @name STAT - GPMI Status Register Description */ /*! @{ */ #define GPMI_STAT_PRESENT_MASK (0x1U) #define GPMI_STAT_PRESENT_SHIFT (0U) /*! PRESENT * 0b0..GPMI is not present in this product. * 0b1..GPMI is present is in this product. */ #define GPMI_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_PRESENT_SHIFT)) & GPMI_STAT_PRESENT_MASK) #define GPMI_STAT_FIFO_FULL_MASK (0x2U) #define GPMI_STAT_FIFO_FULL_SHIFT (1U) /*! FIFO_FULL * 0b0..FIFO is not full. * 0b1..FIFO is full. */ #define GPMI_STAT_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_FULL_SHIFT)) & GPMI_STAT_FIFO_FULL_MASK) #define GPMI_STAT_FIFO_EMPTY_MASK (0x4U) #define GPMI_STAT_FIFO_EMPTY_SHIFT (2U) /*! FIFO_EMPTY * 0b0..FIFO is not empty. * 0b1..FIFO is empty. */ #define GPMI_STAT_FIFO_EMPTY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_EMPTY_SHIFT)) & GPMI_STAT_FIFO_EMPTY_MASK) #define GPMI_STAT_INVALID_BUFFER_MASK_MASK (0x8U) #define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT (3U) /*! INVALID_BUFFER_MASK * 0b0..ECC Buffer Mask is not invalid. * 0b1..ECC Buffer Mask is invalid. */ #define GPMI_STAT_INVALID_BUFFER_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_INVALID_BUFFER_MASK_SHIFT)) & GPMI_STAT_INVALID_BUFFER_MASK_MASK) #define GPMI_STAT_ATA_IRQ_MASK (0x10U) #define GPMI_STAT_ATA_IRQ_SHIFT (4U) #define GPMI_STAT_ATA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_ATA_IRQ_SHIFT)) & GPMI_STAT_ATA_IRQ_MASK) #define GPMI_STAT_RSVD1_MASK (0xE0U) #define GPMI_STAT_RSVD1_SHIFT (5U) #define GPMI_STAT_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RSVD1_SHIFT)) & GPMI_STAT_RSVD1_MASK) #define GPMI_STAT_DEV0_ERROR_MASK (0x100U) #define GPMI_STAT_DEV0_ERROR_SHIFT (8U) /*! DEV0_ERROR * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 0. * 0b1..An Error has occurred on ATA/NAND Device accessed by */ #define GPMI_STAT_DEV0_ERROR(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV0_ERROR_SHIFT)) & GPMI_STAT_DEV0_ERROR_MASK) #define GPMI_STAT_DEV1_ERROR_MASK (0x200U) #define GPMI_STAT_DEV1_ERROR_SHIFT (9U) /*! DEV1_ERROR * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 1. * 0b1..An Error has occurred on ATA/NAND Device accessed by */ #define GPMI_STAT_DEV1_ERROR(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV1_ERROR_SHIFT)) & GPMI_STAT_DEV1_ERROR_MASK) #define GPMI_STAT_DEV2_ERROR_MASK (0x400U) #define GPMI_STAT_DEV2_ERROR_SHIFT (10U) /*! DEV2_ERROR * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 2. * 0b1..An Error has occurred on ATA/NAND Device accessed by */ #define GPMI_STAT_DEV2_ERROR(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV2_ERROR_SHIFT)) & GPMI_STAT_DEV2_ERROR_MASK) #define GPMI_STAT_DEV3_ERROR_MASK (0x800U) #define GPMI_STAT_DEV3_ERROR_SHIFT (11U) /*! DEV3_ERROR * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 3. * 0b1..An Error has occurred on ATA/NAND Device accessed by */ #define GPMI_STAT_DEV3_ERROR(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV3_ERROR_SHIFT)) & GPMI_STAT_DEV3_ERROR_MASK) #define GPMI_STAT_DEV4_ERROR_MASK (0x1000U) #define GPMI_STAT_DEV4_ERROR_SHIFT (12U) /*! DEV4_ERROR * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 4. * 0b1..An Error has occurred on ATA/NAND Device accessed by */ #define GPMI_STAT_DEV4_ERROR(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV4_ERROR_SHIFT)) & GPMI_STAT_DEV4_ERROR_MASK) #define GPMI_STAT_DEV5_ERROR_MASK (0x2000U) #define GPMI_STAT_DEV5_ERROR_SHIFT (13U) /*! DEV5_ERROR * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 5. * 0b1..An Error has occurred on ATA/NAND Device accessed by */ #define GPMI_STAT_DEV5_ERROR(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV5_ERROR_SHIFT)) & GPMI_STAT_DEV5_ERROR_MASK) #define GPMI_STAT_DEV6_ERROR_MASK (0x4000U) #define GPMI_STAT_DEV6_ERROR_SHIFT (14U) /*! DEV6_ERROR * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 6. * 0b1..An Error has occurred on ATA/NAND Device accessed by */ #define GPMI_STAT_DEV6_ERROR(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV6_ERROR_SHIFT)) & GPMI_STAT_DEV6_ERROR_MASK) #define GPMI_STAT_DEV7_ERROR_MASK (0x8000U) #define GPMI_STAT_DEV7_ERROR_SHIFT (15U) /*! DEV7_ERROR * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 7. * 0b1..An Error has occurred on ATA/NAND Device accessed by */ #define GPMI_STAT_DEV7_ERROR(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV7_ERROR_SHIFT)) & GPMI_STAT_DEV7_ERROR_MASK) #define GPMI_STAT_RDY_TIMEOUT_MASK (0xFF0000U) #define GPMI_STAT_RDY_TIMEOUT_SHIFT (16U) #define GPMI_STAT_RDY_TIMEOUT(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RDY_TIMEOUT_SHIFT)) & GPMI_STAT_RDY_TIMEOUT_MASK) #define GPMI_STAT_READY_BUSY_MASK (0xFF000000U) #define GPMI_STAT_READY_BUSY_SHIFT (24U) #define GPMI_STAT_READY_BUSY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_READY_BUSY_SHIFT)) & GPMI_STAT_READY_BUSY_MASK) /*! @} */ /*! @name DEBUG - GPMI Debug Information Register Description */ /*! @{ */ #define GPMI_DEBUG_CMD_END_MASK (0xFFU) #define GPMI_DEBUG_CMD_END_SHIFT (0U) #define GPMI_DEBUG_CMD_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_CMD_END_SHIFT)) & GPMI_DEBUG_CMD_END_MASK) #define GPMI_DEBUG_DMAREQ_MASK (0xFF00U) #define GPMI_DEBUG_DMAREQ_SHIFT (8U) #define GPMI_DEBUG_DMAREQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMAREQ_SHIFT)) & GPMI_DEBUG_DMAREQ_MASK) #define GPMI_DEBUG_DMA_SENSE_MASK (0xFF0000U) #define GPMI_DEBUG_DMA_SENSE_SHIFT (16U) #define GPMI_DEBUG_DMA_SENSE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMA_SENSE_SHIFT)) & GPMI_DEBUG_DMA_SENSE_MASK) #define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xFF000000U) #define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT (24U) #define GPMI_DEBUG_WAIT_FOR_READY_END(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT)) & GPMI_DEBUG_WAIT_FOR_READY_END_MASK) /*! @} */ /*! @name VERSION - GPMI Version Register Description */ /*! @{ */ #define GPMI_VERSION_STEP_MASK (0xFFFFU) #define GPMI_VERSION_STEP_SHIFT (0U) #define GPMI_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_STEP_SHIFT)) & GPMI_VERSION_STEP_MASK) #define GPMI_VERSION_MINOR_MASK (0xFF0000U) #define GPMI_VERSION_MINOR_SHIFT (16U) #define GPMI_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MINOR_SHIFT)) & GPMI_VERSION_MINOR_MASK) #define GPMI_VERSION_MAJOR_MASK (0xFF000000U) #define GPMI_VERSION_MAJOR_SHIFT (24U) #define GPMI_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MAJOR_SHIFT)) & GPMI_VERSION_MAJOR_MASK) /*! @} */ /*! @name DEBUG2 - GPMI Debug2 Information Register Description */ /*! @{ */ #define GPMI_DEBUG2_RDN_TAP_MASK (0x3FU) #define GPMI_DEBUG2_RDN_TAP_SHIFT (0U) #define GPMI_DEBUG2_RDN_TAP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RDN_TAP_SHIFT)) & GPMI_DEBUG2_RDN_TAP_MASK) #define GPMI_DEBUG2_UPDATE_WINDOW_MASK (0x40U) #define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT (6U) #define GPMI_DEBUG2_UPDATE_WINDOW(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UPDATE_WINDOW_SHIFT)) & GPMI_DEBUG2_UPDATE_WINDOW_MASK) #define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK (0x80U) #define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT (7U) #define GPMI_DEBUG2_VIEW_DELAYED_RDN(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT)) & GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK) #define GPMI_DEBUG2_SYND2GPMI_READY_MASK (0x100U) #define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT (8U) #define GPMI_DEBUG2_SYND2GPMI_READY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_READY_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_READY_MASK) #define GPMI_DEBUG2_SYND2GPMI_VALID_MASK (0x200U) #define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT (9U) #define GPMI_DEBUG2_SYND2GPMI_VALID(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_VALID_MASK) #define GPMI_DEBUG2_GPMI2SYND_READY_MASK (0x400U) #define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT (10U) #define GPMI_DEBUG2_GPMI2SYND_READY(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_READY_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_READY_MASK) #define GPMI_DEBUG2_GPMI2SYND_VALID_MASK (0x800U) #define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT (11U) #define GPMI_DEBUG2_GPMI2SYND_VALID(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_VALID_MASK) #define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xF000U) #define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT (12U) #define GPMI_DEBUG2_SYND2GPMI_BE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_BE_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_BE_MASK) #define GPMI_DEBUG2_MAIN_STATE_MASK (0xF0000U) #define GPMI_DEBUG2_MAIN_STATE_SHIFT (16U) #define GPMI_DEBUG2_MAIN_STATE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_MAIN_STATE_SHIFT)) & GPMI_DEBUG2_MAIN_STATE_MASK) #define GPMI_DEBUG2_PIN_STATE_MASK (0x700000U) #define GPMI_DEBUG2_PIN_STATE_SHIFT (20U) #define GPMI_DEBUG2_PIN_STATE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_PIN_STATE_SHIFT)) & GPMI_DEBUG2_PIN_STATE_MASK) #define GPMI_DEBUG2_BUSY_MASK (0x800000U) #define GPMI_DEBUG2_BUSY_SHIFT (23U) #define GPMI_DEBUG2_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_BUSY_SHIFT)) & GPMI_DEBUG2_BUSY_MASK) #define GPMI_DEBUG2_UDMA_STATE_MASK (0xF000000U) #define GPMI_DEBUG2_UDMA_STATE_SHIFT (24U) #define GPMI_DEBUG2_UDMA_STATE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UDMA_STATE_SHIFT)) & GPMI_DEBUG2_UDMA_STATE_MASK) #define GPMI_DEBUG2_RSVD1_MASK (0xF0000000U) #define GPMI_DEBUG2_RSVD1_SHIFT (28U) #define GPMI_DEBUG2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RSVD1_SHIFT)) & GPMI_DEBUG2_RSVD1_MASK) /*! @} */ /*! @name DEBUG3 - GPMI Debug3 Information Register Description */ /*! @{ */ #define GPMI_DEBUG3_DEV_WORD_CNTR_MASK (0xFFFFU) #define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT (0U) #define GPMI_DEBUG3_DEV_WORD_CNTR(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_DEV_WORD_CNTR_MASK) #define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xFFFF0000U) #define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT (16U) #define GPMI_DEBUG3_APB_WORD_CNTR(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_APB_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_APB_WORD_CNTR_MASK) /*! @} */ /*! @name READ_DDR_DLL_CTRL - GPMI Double Rate Read DLL Control Register Description */ /*! @{ */ #define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK (0x1U) #define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT (0U) #define GPMI_READ_DDR_DLL_CTRL_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK) #define GPMI_READ_DDR_DLL_CTRL_RESET_MASK (0x2U) #define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT (1U) #define GPMI_READ_DDR_DLL_CTRL_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RESET_MASK) #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & \ GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK) #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & \ GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U) #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U) #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & \ GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK) #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U) #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U) #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK) #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U) #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U) #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & \ GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK) #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U) #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U) #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & \ GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) #define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U) #define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT (18U) #define GPMI_READ_DDR_DLL_CTRL_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK) #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & \ GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & \ GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) /*! @} */ /*! @name WRITE_DDR_DLL_CTRL - GPMI Double Rate Write DLL Control Register Description */ /*! @{ */ #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK (0x1U) #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT (0U) #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK (0x2U) #define GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT (1U) #define GPMI_WRITE_DDR_DLL_CTRL_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & \ GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & \ GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U) #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U) #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & \ GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U) #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U) #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & \ GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & \ GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U) #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT (18U) #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & \ GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & \ GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) /*! @} */ /*! @name READ_DDR_DLL_STS - GPMI Double Rate Read DLL Status Register Description */ /*! @{ */ #define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK (0x1U) #define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT (0U) #define GPMI_READ_DDR_DLL_STS_SLV_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK) #define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU) #define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT (1U) #define GPMI_READ_DDR_DLL_STS_SLV_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK) #define GPMI_READ_DDR_DLL_STS_RSVD0_MASK (0xFE00U) #define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT (9U) #define GPMI_READ_DDR_DLL_STS_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD0_MASK) #define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK (0x10000U) #define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT (16U) #define GPMI_READ_DDR_DLL_STS_REF_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK) #define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U) #define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT (17U) #define GPMI_READ_DDR_DLL_STS_REF_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_SEL_MASK) #define GPMI_READ_DDR_DLL_STS_RSVD1_MASK (0xFE000000U) #define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT (25U) #define GPMI_READ_DDR_DLL_STS_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD1_MASK) /*! @} */ /*! @name WRITE_DDR_DLL_STS - GPMI Double Rate Write DLL Status Register Description */ /*! @{ */ #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK (0x1U) #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT (0U) #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK) #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU) #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT (1U) #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK) #define GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK (0xFE00U) #define GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT (9U) #define GPMI_WRITE_DDR_DLL_STS_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK) #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK (0x10000U) #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT (16U) #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK) #define GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U) #define GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT (17U) #define GPMI_WRITE_DDR_DLL_STS_REF_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK) #define GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK (0xFE000000U) #define GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT (25U) #define GPMI_WRITE_DDR_DLL_STS_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK) /*! @} */ /*! * @} */ /* end of group GPMI_Register_Masks */ /* GPMI - Peripheral instance base addresses */ /** Peripheral GPMI base address */ #define GPMI_BASE (0x33002000u) /** Peripheral GPMI base pointer */ #define GPMI ((GPMI_Type *)GPMI_BASE) /** Array initializer of GPMI peripheral base addresses */ #define GPMI_BASE_ADDRS \ { \ GPMI_BASE \ } /** Array initializer of GPMI peripheral base pointers */ #define GPMI_BASE_PTRS \ { \ GPMI \ } /*! * @} */ /* end of group GPMI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer * @{ */ /** GPT - Register Layout Typedef */ typedef struct { __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */ __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */ __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */ __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */ __IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */ __I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */ __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */ } GPT_Type; /* ---------------------------------------------------------------------------- -- GPT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPT_Register_Masks GPT Register Masks * @{ */ /*! @name CR - GPT Control Register */ /*! @{ */ #define GPT_CR_EN_MASK (0x1U) #define GPT_CR_EN_SHIFT (0U) /*! EN * 0b0..GPT is disabled. * 0b1..GPT is enabled. */ #define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) #define GPT_CR_ENMOD_MASK (0x2U) #define GPT_CR_ENMOD_SHIFT (1U) /*! ENMOD * 0b0..GPT counter will retain its value when it is disabled. * 0b1..GPT counter value is reset to 0 when it is disabled. */ #define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) #define GPT_CR_DBGEN_MASK (0x4U) #define GPT_CR_DBGEN_SHIFT (2U) /*! DBGEN * 0b0..GPT is disabled in debug mode. * 0b1..GPT is enabled in debug mode. */ #define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) #define GPT_CR_WAITEN_MASK (0x8U) #define GPT_CR_WAITEN_SHIFT (3U) /*! WAITEN * 0b0..GPT is disabled in wait mode. * 0b1..GPT is enabled in wait mode. */ #define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) #define GPT_CR_DOZEEN_MASK (0x10U) #define GPT_CR_DOZEEN_SHIFT (4U) /*! DOZEEN * 0b0..GPT is disabled in doze mode. * 0b1..GPT is enabled in doze mode. */ #define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) #define GPT_CR_STOPEN_MASK (0x20U) #define GPT_CR_STOPEN_SHIFT (5U) /*! STOPEN * 0b0..GPT is disabled in Stop mode. * 0b1..GPT is enabled in Stop mode. */ #define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) #define GPT_CR_CLKSRC_MASK (0x1C0U) #define GPT_CR_CLKSRC_SHIFT (6U) /*! CLKSRC * 0b000..No clock * 0b001..Peripheral Clock (ipg_clk) * 0b010..High Frequency Reference Clock (ipg_clk_highfreq) * 0b011..External Clock * 0b100..Low Frequency Reference Clock (ipg_clk_32k) * 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M) */ #define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) #define GPT_CR_FRR_MASK (0x200U) #define GPT_CR_FRR_SHIFT (9U) /*! FRR * 0b0..Restart mode * 0b1..Free-Run mode */ #define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) #define GPT_CR_EN_24M_MASK (0x400U) #define GPT_CR_EN_24M_SHIFT (10U) /*! EN_24M * 0b0..24M clock disabled * 0b1..24M clock enabled */ #define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) #define GPT_CR_SWR_MASK (0x8000U) #define GPT_CR_SWR_SHIFT (15U) /*! SWR * 0b0..GPT is not in reset state * 0b1..GPT is in reset state */ #define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) #define GPT_CR_IM1_MASK (0x30000U) #define GPT_CR_IM1_SHIFT (16U) #define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) #define GPT_CR_IM2_MASK (0xC0000U) #define GPT_CR_IM2_SHIFT (18U) /*! IM2 * 0b00..capture disabled * 0b01..capture on rising edge only * 0b10..capture on falling edge only * 0b11..capture on both edges */ #define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) #define GPT_CR_OM1_MASK (0x700000U) #define GPT_CR_OM1_SHIFT (20U) #define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) #define GPT_CR_OM2_MASK (0x3800000U) #define GPT_CR_OM2_SHIFT (23U) #define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) #define GPT_CR_OM3_MASK (0x1C000000U) #define GPT_CR_OM3_SHIFT (26U) /*! OM3 * 0b000..Output disconnected. No response on pin. * 0b001..Toggle output pin * 0b010..Clear output pin * 0b011..Set output pin * 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin. */ #define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) #define GPT_CR_FO1_MASK (0x20000000U) #define GPT_CR_FO1_SHIFT (29U) #define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) #define GPT_CR_FO2_MASK (0x40000000U) #define GPT_CR_FO2_SHIFT (30U) #define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) #define GPT_CR_FO3_MASK (0x80000000U) #define GPT_CR_FO3_SHIFT (31U) /*! FO3 * 0b0..Writing a 0 has no effect. * 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. */ #define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) /*! @} */ /*! @name PR - GPT Prescaler Register */ /*! @{ */ #define GPT_PR_PRESCALER_MASK (0xFFFU) #define GPT_PR_PRESCALER_SHIFT (0U) /*! PRESCALER * 0b000000000000..Divide by 1 * 0b000000000001..Divide by 2 * 0b111111111111..Divide by 4096 */ #define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) #define GPT_PR_PRESCALER24M_MASK (0xF000U) #define GPT_PR_PRESCALER24M_SHIFT (12U) /*! PRESCALER24M * 0b0000..Divide by 1 * 0b0001..Divide by 2 * 0b1111..Divide by 16 */ #define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) /*! @} */ /*! @name SR - GPT Status Register */ /*! @{ */ #define GPT_SR_OF1_MASK (0x1U) #define GPT_SR_OF1_SHIFT (0U) #define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) #define GPT_SR_OF2_MASK (0x2U) #define GPT_SR_OF2_SHIFT (1U) #define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) #define GPT_SR_OF3_MASK (0x4U) #define GPT_SR_OF3_SHIFT (2U) /*! OF3 * 0b0..Compare event has not occurred. * 0b1..Compare event has occurred. */ #define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) #define GPT_SR_IF1_MASK (0x8U) #define GPT_SR_IF1_SHIFT (3U) #define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) #define GPT_SR_IF2_MASK (0x10U) #define GPT_SR_IF2_SHIFT (4U) /*! IF2 * 0b0..Capture event has not occurred. * 0b1..Capture event has occurred. */ #define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) #define GPT_SR_ROV_MASK (0x20U) #define GPT_SR_ROV_SHIFT (5U) /*! ROV * 0b0..Rollover has not occurred. * 0b1..Rollover has occurred. */ #define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) /*! @} */ /*! @name IR - GPT Interrupt Register */ /*! @{ */ #define GPT_IR_OF1IE_MASK (0x1U) #define GPT_IR_OF1IE_SHIFT (0U) #define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) #define GPT_IR_OF2IE_MASK (0x2U) #define GPT_IR_OF2IE_SHIFT (1U) #define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) #define GPT_IR_OF3IE_MASK (0x4U) #define GPT_IR_OF3IE_SHIFT (2U) /*! OF3IE * 0b0..Output Compare Channel n interrupt is disabled. * 0b1..Output Compare Channel n interrupt is enabled. */ #define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) #define GPT_IR_IF1IE_MASK (0x8U) #define GPT_IR_IF1IE_SHIFT (3U) #define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) #define GPT_IR_IF2IE_MASK (0x10U) #define GPT_IR_IF2IE_SHIFT (4U) /*! IF2IE * 0b0..IF2IE Input Capture n Interrupt Enable is disabled. * 0b1..IF2IE Input Capture n Interrupt Enable is enabled. */ #define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) #define GPT_IR_ROVIE_MASK (0x20U) #define GPT_IR_ROVIE_SHIFT (5U) /*! ROVIE * 0b0..Rollover interrupt is disabled. * 0b1..Rollover interrupt enabled. */ #define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) /*! @} */ /*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */ /*! @{ */ #define GPT_OCR_COMP_MASK (0xFFFFFFFFU) #define GPT_OCR_COMP_SHIFT (0U) #define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) /*! @} */ /* The count of GPT_OCR */ #define GPT_OCR_COUNT (3U) /*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */ /*! @{ */ #define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) #define GPT_ICR_CAPT_SHIFT (0U) #define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) /*! @} */ /* The count of GPT_ICR */ #define GPT_ICR_COUNT (2U) /*! @name CNT - GPT Counter Register */ /*! @{ */ #define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) #define GPT_CNT_COUNT_SHIFT (0U) #define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) /*! @} */ /*! * @} */ /* end of group GPT_Register_Masks */ /* GPT - Peripheral instance base addresses */ /** Peripheral GPT1 base address */ #define GPT1_BASE (0x302D0000u) /** Peripheral GPT1 base pointer */ #define GPT1 ((GPT_Type *)GPT1_BASE) /** Peripheral GPT2 base address */ #define GPT2_BASE (0x302E0000u) /** Peripheral GPT2 base pointer */ #define GPT2 ((GPT_Type *)GPT2_BASE) /** Peripheral GPT3 base address */ #define GPT3_BASE (0x302F0000u) /** Peripheral GPT3 base pointer */ #define GPT3 ((GPT_Type *)GPT3_BASE) /** Peripheral GPT4 base address */ #define GPT4_BASE (0x30700000u) /** Peripheral GPT4 base pointer */ #define GPT4 ((GPT_Type *)GPT4_BASE) /** Peripheral GPT5 base address */ #define GPT5_BASE (0x306F0000u) /** Peripheral GPT5 base pointer */ #define GPT5 ((GPT_Type *)GPT5_BASE) /** Peripheral GPT6 base address */ #define GPT6_BASE (0x306E0000u) /** Peripheral GPT6 base pointer */ #define GPT6 ((GPT_Type *)GPT6_BASE) /** Array initializer of GPT peripheral base addresses */ #define GPT_BASE_ADDRS \ { \ 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE, GPT5_BASE, GPT6_BASE \ } /** Array initializer of GPT peripheral base pointers */ #define GPT_BASE_PTRS \ { \ (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6 \ } /** Interrupt vectors for the GPT peripheral type */ #define GPT_IRQS \ { \ NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn, GPT3_IRQn, GPT4_IRQn, GPT5_IRQn, GPT6_IRQn \ } /*! * @} */ /* end of group GPT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- I2C Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer * @{ */ /** I2C - Register Layout Typedef */ typedef struct { __IO uint16_t IADR; /**< I2C Address Register, offset: 0x0 */ uint8_t RESERVED_0[2]; __IO uint16_t IFDR; /**< I2C Frequency Divider Register, offset: 0x4 */ uint8_t RESERVED_1[2]; __IO uint16_t I2CR; /**< I2C Control Register, offset: 0x8 */ uint8_t RESERVED_2[2]; __IO uint16_t I2SR; /**< I2C Status Register, offset: 0xC */ uint8_t RESERVED_3[2]; __IO uint16_t I2DR; /**< I2C Data I/O Register, offset: 0x10 */ } I2C_Type; /* ---------------------------------------------------------------------------- -- I2C Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I2C_Register_Masks I2C Register Masks * @{ */ /*! @name IADR - I2C Address Register */ /*! @{ */ #define I2C_IADR_ADR_MASK (0xFEU) #define I2C_IADR_ADR_SHIFT (1U) #define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x)) << I2C_IADR_ADR_SHIFT)) & I2C_IADR_ADR_MASK) /*! @} */ /*! @name IFDR - I2C Frequency Divider Register */ /*! @{ */ #define I2C_IFDR_IC_MASK (0x3FU) #define I2C_IFDR_IC_SHIFT (0U) #define I2C_IFDR_IC(x) (((uint16_t)(((uint16_t)(x)) << I2C_IFDR_IC_SHIFT)) & I2C_IFDR_IC_MASK) /*! @} */ /*! @name I2CR - I2C Control Register */ /*! @{ */ #define I2C_I2CR_RSTA_MASK (0x4U) #define I2C_I2CR_RSTA_SHIFT (2U) /*! RSTA * 0b0..No repeat start * 0b1..Generates a Repeated Start condition */ #define I2C_I2CR_RSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_RSTA_SHIFT)) & I2C_I2CR_RSTA_MASK) #define I2C_I2CR_TXAK_MASK (0x8U) #define I2C_I2CR_TXAK_SHIFT (3U) /*! TXAK * 0b0..An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data. * 0b1..No acknowledge signal response is sent (that is, the acknowledge bit = 1). */ #define I2C_I2CR_TXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_TXAK_SHIFT)) & I2C_I2CR_TXAK_MASK) #define I2C_I2CR_MTX_MASK (0x10U) #define I2C_I2CR_MTX_SHIFT (4U) /*! MTX * 0b0..Receive.When a slave is addressed, the software should set MTX according to the slave read/write bit in * the I2C status register (I2C_I2SR[SRW]). * 0b1..Transmit.In Master mode, MTX should be set according to the type of transfer required. Therefore, for address * cycles, MTX is always 1. */ #define I2C_I2CR_MTX(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MTX_SHIFT)) & I2C_I2CR_MTX_MASK) #define I2C_I2CR_MSTA_MASK (0x20U) #define I2C_I2CR_MSTA_SHIFT (5U) /*! MSTA * 0b0..Slave mode. Changing MSTA from 1 to 0 generates a Stop and selects Slave mode. * 0b1..Master mode. Changing MSTA from 0 to 1 signals a Start on the bus and selects Master mode. */ #define I2C_I2CR_MSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MSTA_SHIFT)) & I2C_I2CR_MSTA_MASK) #define I2C_I2CR_IIEN_MASK (0x40U) #define I2C_I2CR_IIEN_SHIFT (6U) /*! IIEN * 0b0..I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an Interrupt condition * occurs. 0b1..I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set. */ #define I2C_I2CR_IIEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IIEN_SHIFT)) & I2C_I2CR_IIEN_MASK) #define I2C_I2CR_IEN_MASK (0x80U) #define I2C_I2CR_IEN_SHIFT (7U) /*! IEN * 0b0..The block is disabled, but registers can still be accessed. * 0b1..The I2C is enabled. This bit must be set before any other I2C_I2CR bits have an effect. */ #define I2C_I2CR_IEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IEN_SHIFT)) & I2C_I2CR_IEN_MASK) /*! @} */ /*! @name I2SR - I2C Status Register */ /*! @{ */ #define I2C_I2SR_RXAK_MASK (0x1U) #define I2C_I2SR_RXAK_SHIFT (0U) /*! RXAK * 0b0..An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus. * 0b1..A "No acknowledge" signal was detected at the ninth clock. */ #define I2C_I2SR_RXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_RXAK_SHIFT)) & I2C_I2SR_RXAK_MASK) #define I2C_I2SR_IIF_MASK (0x2U) #define I2C_I2SR_IIF_SHIFT (1U) /*! IIF * 0b0..No I2C interrupt pending. * 0b1..An interrupt is pending.This causes a processor interrupt request (if the interrupt enable is asserted * [IIEN = 1]). The interrupt is set when one of the following occurs: One byte transfer is completed (the * interrupt is set at the falling edge of the ninth clock). An address is received that matches its own specific * address in Slave Receive mode. Arbitration is lost. */ #define I2C_I2SR_IIF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IIF_SHIFT)) & I2C_I2SR_IIF_MASK) #define I2C_I2SR_SRW_MASK (0x4U) #define I2C_I2SR_SRW_SHIFT (2U) /*! SRW * 0b0..Slave receive, master writing to slave * 0b1..Slave transmit, master reading from slave */ #define I2C_I2SR_SRW(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_SRW_SHIFT)) & I2C_I2SR_SRW_MASK) #define I2C_I2SR_IAL_MASK (0x10U) #define I2C_I2SR_IAL_SHIFT (4U) /*! IAL * 0b0..No arbitration lost. * 0b1..Arbitration is lost. */ #define I2C_I2SR_IAL(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAL_SHIFT)) & I2C_I2SR_IAL_MASK) #define I2C_I2SR_IBB_MASK (0x20U) #define I2C_I2SR_IBB_SHIFT (5U) /*! IBB * 0b0..Bus is idle. If a Stop signal is detected, IBB is cleared. * 0b1..Bus is busy. When Start is detected, IBB is set. */ #define I2C_I2SR_IBB(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IBB_SHIFT)) & I2C_I2SR_IBB_MASK) #define I2C_I2SR_IAAS_MASK (0x40U) #define I2C_I2SR_IAAS_SHIFT (6U) /*! IAAS * 0b0..Not addressed * 0b1..Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address. */ #define I2C_I2SR_IAAS(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAAS_SHIFT)) & I2C_I2SR_IAAS_MASK) #define I2C_I2SR_ICF_MASK (0x80U) #define I2C_I2SR_ICF_SHIFT (7U) /*! ICF * 0b0..Transfer is in progress. * 0b1..Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte transfer. */ #define I2C_I2SR_ICF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_ICF_SHIFT)) & I2C_I2SR_ICF_MASK) /*! @} */ /*! @name I2DR - I2C Data I/O Register */ /*! @{ */ #define I2C_I2DR_DATA_MASK (0xFFU) #define I2C_I2DR_DATA_SHIFT (0U) #define I2C_I2DR_DATA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2DR_DATA_SHIFT)) & I2C_I2DR_DATA_MASK) /*! @} */ /*! * @} */ /* end of group I2C_Register_Masks */ /* I2C - Peripheral instance base addresses */ /** Peripheral I2C1 base address */ #define I2C1_BASE (0x30A20000u) /** Peripheral I2C1 base pointer */ #define I2C1 ((I2C_Type *)I2C1_BASE) /** Peripheral I2C2 base address */ #define I2C2_BASE (0x30A30000u) /** Peripheral I2C2 base pointer */ #define I2C2 ((I2C_Type *)I2C2_BASE) /** Peripheral I2C3 base address */ #define I2C3_BASE (0x30A40000u) /** Peripheral I2C3 base pointer */ #define I2C3 ((I2C_Type *)I2C3_BASE) /** Peripheral I2C4 base address */ #define I2C4_BASE (0x30A50000u) /** Peripheral I2C4 base pointer */ #define I2C4 ((I2C_Type *)I2C4_BASE) /** Array initializer of I2C peripheral base addresses */ #define I2C_BASE_ADDRS \ { \ 0u, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE \ } /** Array initializer of I2C peripheral base pointers */ #define I2C_BASE_PTRS \ { \ (I2C_Type *)0u, I2C1, I2C2, I2C3, I2C4 \ } /** Interrupt vectors for the I2C peripheral type */ #define I2C_IRQS \ { \ NotAvail_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn, I2C4_IRQn \ } /*! * @} */ /* end of group I2C_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- I2S Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer * @{ */ /** I2S - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */ __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */ __O uint32_t TDR[8]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ __I uint32_t TFR[8]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ uint8_t RESERVED_0[12]; __IO uint32_t TTCR; /**< SAI Transmit Timestamp Control Register, offset: 0x70 */ __I uint32_t TTSR; /**< SAI Transmit Timestamp Register, offset: 0x74 */ __I uint32_t TBCR; /**< SAI Transmit Bit Count Register, offset: 0x78 */ __I uint32_t TBCTR; /**< SAI Transmit Bit Count Timestamp Register, offset: 0x7C */ uint8_t RESERVED_1[8]; __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */ __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */ __I uint32_t RDR[8]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ __I uint32_t RFR[8]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ uint8_t RESERVED_2[12]; __IO uint32_t RTCR; /**< SAI Receive Timestamp Control Register, offset: 0xF0 */ __I uint32_t RTSR; /**< SAI Receive Timestamp Register, offset: 0xF4 */ __I uint32_t RBCR; /**< SAI Receive Bit Count Register, offset: 0xF8 */ __I uint32_t RBCTR; /**< SAI Receive Bit Count Timestamp Register, offset: 0xFC */ __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */ } I2S_Type; /* ---------------------------------------------------------------------------- -- I2S Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Register_Masks I2S Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define I2S_VERID_FEATURE_MASK (0xFFFFU) #define I2S_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Standard feature set. * 0b0000000000000010..Standard feature set with Timestamp Registers. */ #define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) #define I2S_VERID_MINOR_MASK (0xFF0000U) #define I2S_VERID_MINOR_SHIFT (16U) #define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) #define I2S_VERID_MAJOR_MASK (0xFF000000U) #define I2S_VERID_MAJOR_SHIFT (24U) #define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define I2S_PARAM_DATALINE_MASK (0xFU) #define I2S_PARAM_DATALINE_SHIFT (0U) #define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) #define I2S_PARAM_FIFO_MASK (0xF00U) #define I2S_PARAM_FIFO_SHIFT (8U) #define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) #define I2S_PARAM_FRAME_MASK (0xF0000U) #define I2S_PARAM_FRAME_SHIFT (16U) #define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) /*! @} */ /*! @name TCSR - SAI Transmit Control Register */ /*! @{ */ #define I2S_TCSR_FRDE_MASK (0x1U) #define I2S_TCSR_FRDE_SHIFT (0U) /*! FRDE - FIFO Request DMA Enable * 0b0..Disables the DMA request. * 0b1..Enables the DMA request. */ #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) #define I2S_TCSR_FWDE_MASK (0x2U) #define I2S_TCSR_FWDE_SHIFT (1U) /*! FWDE - FIFO Warning DMA Enable * 0b0..Disables the DMA request. * 0b1..Enables the DMA request. */ #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) #define I2S_TCSR_FRIE_MASK (0x100U) #define I2S_TCSR_FRIE_SHIFT (8U) /*! FRIE - FIFO Request Interrupt Enable * 0b0..Disables the interrupt. * 0b1..Enables the interrupt. */ #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) #define I2S_TCSR_FWIE_MASK (0x200U) #define I2S_TCSR_FWIE_SHIFT (9U) /*! FWIE - FIFO Warning Interrupt Enable * 0b0..Disables the interrupt. * 0b1..Enables the interrupt. */ #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) #define I2S_TCSR_FEIE_MASK (0x400U) #define I2S_TCSR_FEIE_SHIFT (10U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Disables the interrupt. * 0b1..Enables the interrupt. */ #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) #define I2S_TCSR_SEIE_MASK (0x800U) #define I2S_TCSR_SEIE_SHIFT (11U) /*! SEIE - Sync Error Interrupt Enable * 0b0..Disables interrupt. * 0b1..Enables interrupt. */ #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) #define I2S_TCSR_WSIE_MASK (0x1000U) #define I2S_TCSR_WSIE_SHIFT (12U) /*! WSIE - Word Start Interrupt Enable * 0b0..Disables interrupt. * 0b1..Enables interrupt. */ #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) #define I2S_TCSR_FRF_MASK (0x10000U) #define I2S_TCSR_FRF_SHIFT (16U) /*! FRF - FIFO Request Flag * 0b0..Transmit FIFO watermark has not been reached. * 0b1..Transmit FIFO watermark has been reached. */ #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) #define I2S_TCSR_FWF_MASK (0x20000U) #define I2S_TCSR_FWF_SHIFT (17U) /*! FWF - FIFO Warning Flag * 0b0..No enabled transmit FIFO is empty. * 0b1..Enabled transmit FIFO is empty. */ #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) #define I2S_TCSR_FEF_MASK (0x40000U) #define I2S_TCSR_FEF_SHIFT (18U) /*! FEF - FIFO Error Flag * 0b0..Transmit underrun not detected. * 0b1..Transmit underrun detected. */ #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) #define I2S_TCSR_SEF_MASK (0x80000U) #define I2S_TCSR_SEF_SHIFT (19U) /*! SEF - Sync Error Flag * 0b0..Sync error not detected. * 0b1..Frame sync error detected. */ #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) #define I2S_TCSR_WSF_MASK (0x100000U) #define I2S_TCSR_WSF_SHIFT (20U) /*! WSF - Word Start Flag * 0b0..Start of word not detected. * 0b1..Start of word detected. */ #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) #define I2S_TCSR_SR_MASK (0x1000000U) #define I2S_TCSR_SR_SHIFT (24U) /*! SR - Software Reset * 0b0..No effect. * 0b1..Software reset. */ #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) #define I2S_TCSR_FR_MASK (0x2000000U) #define I2S_TCSR_FR_SHIFT (25U) /*! FR - FIFO Reset * 0b0..No effect. * 0b1..FIFO reset. */ #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) #define I2S_TCSR_BCE_MASK (0x10000000U) #define I2S_TCSR_BCE_SHIFT (28U) /*! BCE - Bit Clock Enable * 0b0..Transmit bit clock is disabled. * 0b1..Transmit bit clock is enabled. */ #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) #define I2S_TCSR_DBGE_MASK (0x20000000U) #define I2S_TCSR_DBGE_SHIFT (29U) /*! DBGE - Debug Enable * 0b0..Transmitter is disabled in Debug mode, after completing the current frame. * 0b1..Transmitter is enabled in Debug mode. */ #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) #define I2S_TCSR_TE_MASK (0x80000000U) #define I2S_TCSR_TE_SHIFT (31U) /*! TE - Transmitter Enable * 0b0..Transmitter is disabled. * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. */ #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) /*! @} */ /*! @name TCR1 - SAI Transmit Configuration 1 Register */ /*! @{ */ #define I2S_TCR1_TFW_MASK (0x7FU) #define I2S_TCR1_TFW_SHIFT (0U) #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) /*! @} */ /*! @name TCR2 - SAI Transmit Configuration 2 Register */ /*! @{ */ #define I2S_TCR2_DIV_MASK (0xFFU) #define I2S_TCR2_DIV_SHIFT (0U) #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) #define I2S_TCR2_BYP_MASK (0x800000U) #define I2S_TCR2_BYP_SHIFT (23U) /*! BYP - Bit Clock Bypass * 0b0..Internal bit clock is generated from bit clock divider. * 0b1..Internal bit clock is divide by one of the audio master clock. */ #define I2S_TCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK) #define I2S_TCR2_BCD_MASK (0x1000000U) #define I2S_TCR2_BCD_SHIFT (24U) /*! BCD - Bit Clock Direction * 0b0..Bit clock is generated externally in Slave mode. * 0b1..Bit clock is generated internally in Master mode. */ #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) #define I2S_TCR2_BCP_MASK (0x2000000U) #define I2S_TCR2_BCP_SHIFT (25U) /*! BCP - Bit Clock Polarity * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. */ #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) #define I2S_TCR2_MSEL_MASK (0xC000000U) #define I2S_TCR2_MSEL_SHIFT (26U) /*! MSEL - MCLK Select * 0b00..Bus Clock selected. * 0b01..Master Clock (MCLK) 1 option selected. * 0b10..Master Clock (MCLK) 2 option selected. * 0b11..Master Clock (MCLK) 3 option selected. */ #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) #define I2S_TCR2_BCI_MASK (0x10000000U) #define I2S_TCR2_BCI_SHIFT (28U) /*! BCI - Bit Clock Input * 0b0..No effect. * 0b1..Internal logic is clocked as if bit clock was externally generated. */ #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) #define I2S_TCR2_BCS_MASK (0x20000000U) #define I2S_TCR2_BCS_SHIFT (29U) /*! BCS - Bit Clock Swap * 0b0..Use the normal bit clock source. * 0b1..Swap the bit clock source. */ #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) #define I2S_TCR2_SYNC_MASK (0xC0000000U) #define I2S_TCR2_SYNC_SHIFT (30U) /*! SYNC - Synchronous Mode * 0b00..Asynchronous mode. * 0b01..Synchronous with receiver. * 0b10..Reserved. * 0b11..Reserved. */ #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) /*! @} */ /*! @name TCR3 - SAI Transmit Configuration 3 Register */ /*! @{ */ #define I2S_TCR3_WDFL_MASK (0x1FU) #define I2S_TCR3_WDFL_SHIFT (0U) #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) #define I2S_TCR3_TCE_MASK (0xFF0000U) #define I2S_TCR3_TCE_SHIFT (16U) #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) #define I2S_TCR3_CFR_MASK (0xFF000000U) #define I2S_TCR3_CFR_SHIFT (24U) #define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) /*! @} */ /*! @name TCR4 - SAI Transmit Configuration 4 Register */ /*! @{ */ #define I2S_TCR4_FSD_MASK (0x1U) #define I2S_TCR4_FSD_SHIFT (0U) /*! FSD - Frame Sync Direction * 0b0..Frame sync is generated externally in Slave mode. * 0b1..Frame sync is generated internally in Master mode. */ #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) #define I2S_TCR4_FSP_MASK (0x2U) #define I2S_TCR4_FSP_SHIFT (1U) /*! FSP - Frame Sync Polarity * 0b0..Frame sync is active high. * 0b1..Frame sync is active low. */ #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) #define I2S_TCR4_ONDEM_MASK (0x4U) #define I2S_TCR4_ONDEM_SHIFT (2U) /*! ONDEM - On Demand Mode * 0b0..Internal frame sync is generated continuously. * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. */ #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) #define I2S_TCR4_FSE_MASK (0x8U) #define I2S_TCR4_FSE_SHIFT (3U) /*! FSE - Frame Sync Early * 0b0..Frame sync asserts with the first bit of the frame. * 0b1..Frame sync asserts one bit before the first bit of the frame. */ #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) #define I2S_TCR4_MF_MASK (0x10U) #define I2S_TCR4_MF_SHIFT (4U) /*! MF - MSB First * 0b0..LSB is transmitted first. * 0b1..MSB is transmitted first. */ #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) #define I2S_TCR4_CHMOD_MASK (0x20U) #define I2S_TCR4_CHMOD_SHIFT (5U) /*! CHMOD - Channel Mode * 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. * 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are * disabled. */ #define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) #define I2S_TCR4_SYWD_MASK (0x1F00U) #define I2S_TCR4_SYWD_SHIFT (8U) #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) #define I2S_TCR4_FRSZ_MASK (0x1F0000U) #define I2S_TCR4_FRSZ_SHIFT (16U) #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) #define I2S_TCR4_FPACK_MASK (0x3000000U) #define I2S_TCR4_FPACK_SHIFT (24U) /*! FPACK - FIFO Packing Mode * 0b00..FIFO packing is disabled * 0b01..Reserved * 0b10..8-bit FIFO packing is enabled * 0b11..16-bit FIFO packing is enabled */ #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) #define I2S_TCR4_FCOMB_MASK (0xC000000U) #define I2S_TCR4_FCOMB_SHIFT (26U) /*! FCOMB - FIFO Combine Mode * 0b00..FIFO combine mode disabled. * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers). * 0b10..FIFO combine mode enabled on FIFO writes (by software). * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). */ #define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) #define I2S_TCR4_FCONT_MASK (0x10000000U) #define I2S_TCR4_FCONT_SHIFT (28U) /*! FCONT - FIFO Continue on Error * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been * cleared. 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the * FIFO warning flag has been cleared. */ #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) /*! @} */ /*! @name TCR5 - SAI Transmit Configuration 5 Register */ /*! @{ */ #define I2S_TCR5_FBT_MASK (0x1F00U) #define I2S_TCR5_FBT_SHIFT (8U) #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) #define I2S_TCR5_W0W_MASK (0x1F0000U) #define I2S_TCR5_W0W_SHIFT (16U) #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) #define I2S_TCR5_WNW_MASK (0x1F000000U) #define I2S_TCR5_WNW_SHIFT (24U) #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) /*! @} */ /*! @name TDR - SAI Transmit Data Register */ /*! @{ */ #define I2S_TDR_TDR_MASK (0xFFFFFFFFU) #define I2S_TDR_TDR_SHIFT (0U) #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) /*! @} */ /* The count of I2S_TDR */ #define I2S_TDR_COUNT (8U) /*! @name TFR - SAI Transmit FIFO Register */ /*! @{ */ #define I2S_TFR_RFP_MASK (0xFFU) #define I2S_TFR_RFP_SHIFT (0U) #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) #define I2S_TFR_WFP_MASK (0xFF0000U) #define I2S_TFR_WFP_SHIFT (16U) #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) #define I2S_TFR_WCP_MASK (0x80000000U) #define I2S_TFR_WCP_SHIFT (31U) /*! WCP - Write Channel Pointer * 0b0..No effect. * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. */ #define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) /*! @} */ /* The count of I2S_TFR */ #define I2S_TFR_COUNT (8U) /*! @name TMR - SAI Transmit Mask Register */ /*! @{ */ #define I2S_TMR_TWM_MASK (0xFFFFFFFFU) #define I2S_TMR_TWM_SHIFT (0U) /*! TWM - Transmit Word Mask * 0b00000000000000000000000000000000..Word N is enabled. * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when * masked. */ #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) /*! @} */ /*! @name TTCR - SAI Transmit Timestamp Control Register */ /*! @{ */ #define I2S_TTCR_TSEN_MASK (0x1U) #define I2S_TTCR_TSEN_SHIFT (0U) /*! TSEN - Timestamp Enable * 0b0..Timestamp counter is disabled. * 0b1..Timestamp counter is enabled. */ #define I2S_TTCR_TSEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSEN_SHIFT)) & I2S_TTCR_TSEN_MASK) #define I2S_TTCR_TSINC_MASK (0x2U) #define I2S_TTCR_TSINC_SHIFT (1U) /*! TSINC - Timestamp Increment * 0b0..Timestamp counter starts to increment when enabled and the bit counter has incremented. * 0b1..Timestamp counter starts to increment when enabled. */ #define I2S_TTCR_TSINC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSINC_SHIFT)) & I2S_TTCR_TSINC_MASK) #define I2S_TTCR_RTSC_MASK (0x100U) #define I2S_TTCR_RTSC_SHIFT (8U) /*! RTSC - Reset Timestamp Counter * 0b0..Timestamp counter is not reset. * 0b1..Timestamp counter is reset. */ #define I2S_TTCR_RTSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_RTSC_SHIFT)) & I2S_TTCR_RTSC_MASK) #define I2S_TTCR_RBC_MASK (0x200U) #define I2S_TTCR_RBC_SHIFT (9U) /*! RBC - Reset Bit Counter * 0b0..Bit counter is not reset. * 0b1..Bit counter is reset. */ #define I2S_TTCR_RBC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_RBC_SHIFT)) & I2S_TTCR_RBC_MASK) /*! @} */ /*! @name TTSR - SAI Transmit Timestamp Register */ /*! @{ */ #define I2S_TTSR_TSC_MASK (0xFFFFFFFFU) #define I2S_TTSR_TSC_SHIFT (0U) #define I2S_TTSR_TSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTSR_TSC_SHIFT)) & I2S_TTSR_TSC_MASK) /*! @} */ /*! @name TBCR - SAI Transmit Bit Count Register */ /*! @{ */ #define I2S_TBCR_BCNT_MASK (0xFFFFFFFFU) #define I2S_TBCR_BCNT_SHIFT (0U) #define I2S_TBCR_BCNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TBCR_BCNT_SHIFT)) & I2S_TBCR_BCNT_MASK) /*! @} */ /*! @name TBCTR - SAI Transmit Bit Count Timestamp Register */ /*! @{ */ #define I2S_TBCTR_BCTS_MASK (0xFFFFFFFFU) #define I2S_TBCTR_BCTS_SHIFT (0U) #define I2S_TBCTR_BCTS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TBCTR_BCTS_SHIFT)) & I2S_TBCTR_BCTS_MASK) /*! @} */ /*! @name RCSR - SAI Receive Control Register */ /*! @{ */ #define I2S_RCSR_FRDE_MASK (0x1U) #define I2S_RCSR_FRDE_SHIFT (0U) /*! FRDE - FIFO Request DMA Enable * 0b0..Disables the DMA request. * 0b1..Enables the DMA request. */ #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) #define I2S_RCSR_FWDE_MASK (0x2U) #define I2S_RCSR_FWDE_SHIFT (1U) /*! FWDE - FIFO Warning DMA Enable * 0b0..Disables the DMA request. * 0b1..Enables the DMA request. */ #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) #define I2S_RCSR_FRIE_MASK (0x100U) #define I2S_RCSR_FRIE_SHIFT (8U) /*! FRIE - FIFO Request Interrupt Enable * 0b0..Disables the interrupt. * 0b1..Enables the interrupt. */ #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) #define I2S_RCSR_FWIE_MASK (0x200U) #define I2S_RCSR_FWIE_SHIFT (9U) /*! FWIE - FIFO Warning Interrupt Enable * 0b0..Disables the interrupt. * 0b1..Enables the interrupt. */ #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) #define I2S_RCSR_FEIE_MASK (0x400U) #define I2S_RCSR_FEIE_SHIFT (10U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Disables the interrupt. * 0b1..Enables the interrupt. */ #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) #define I2S_RCSR_SEIE_MASK (0x800U) #define I2S_RCSR_SEIE_SHIFT (11U) /*! SEIE - Sync Error Interrupt Enable * 0b0..Disables interrupt. * 0b1..Enables interrupt. */ #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) #define I2S_RCSR_WSIE_MASK (0x1000U) #define I2S_RCSR_WSIE_SHIFT (12U) /*! WSIE - Word Start Interrupt Enable * 0b0..Disables interrupt. * 0b1..Enables interrupt. */ #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) #define I2S_RCSR_FRF_MASK (0x10000U) #define I2S_RCSR_FRF_SHIFT (16U) /*! FRF - FIFO Request Flag * 0b0..Receive FIFO watermark not reached. * 0b1..Receive FIFO watermark has been reached. */ #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) #define I2S_RCSR_FWF_MASK (0x20000U) #define I2S_RCSR_FWF_SHIFT (17U) /*! FWF - FIFO Warning Flag * 0b0..No enabled receive FIFO is full. * 0b1..Enabled receive FIFO is full. */ #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) #define I2S_RCSR_FEF_MASK (0x40000U) #define I2S_RCSR_FEF_SHIFT (18U) /*! FEF - FIFO Error Flag * 0b0..Receive overflow not detected. * 0b1..Receive overflow detected. */ #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) #define I2S_RCSR_SEF_MASK (0x80000U) #define I2S_RCSR_SEF_SHIFT (19U) /*! SEF - Sync Error Flag * 0b0..Sync error not detected. * 0b1..Frame sync error detected. */ #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) #define I2S_RCSR_WSF_MASK (0x100000U) #define I2S_RCSR_WSF_SHIFT (20U) /*! WSF - Word Start Flag * 0b0..Start of word not detected. * 0b1..Start of word detected. */ #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) #define I2S_RCSR_SR_MASK (0x1000000U) #define I2S_RCSR_SR_SHIFT (24U) /*! SR - Software Reset * 0b0..No effect. * 0b1..Software reset. */ #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) #define I2S_RCSR_FR_MASK (0x2000000U) #define I2S_RCSR_FR_SHIFT (25U) /*! FR - FIFO Reset * 0b0..No effect. * 0b1..FIFO reset. */ #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) #define I2S_RCSR_BCE_MASK (0x10000000U) #define I2S_RCSR_BCE_SHIFT (28U) /*! BCE - Bit Clock Enable * 0b0..Receive bit clock is disabled. * 0b1..Receive bit clock is enabled. */ #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) #define I2S_RCSR_DBGE_MASK (0x20000000U) #define I2S_RCSR_DBGE_SHIFT (29U) /*! DBGE - Debug Enable * 0b0..Receiver is disabled in Debug mode, after completing the current frame. * 0b1..Receiver is enabled in Debug mode. */ #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) #define I2S_RCSR_RE_MASK (0x80000000U) #define I2S_RCSR_RE_SHIFT (31U) /*! RE - Receiver Enable * 0b0..Receiver is disabled. * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. */ #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) /*! @} */ /*! @name RCR1 - SAI Receive Configuration 1 Register */ /*! @{ */ #define I2S_RCR1_RFW_MASK (0x7FU) #define I2S_RCR1_RFW_SHIFT (0U) #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) /*! @} */ /*! @name RCR2 - SAI Receive Configuration 2 Register */ /*! @{ */ #define I2S_RCR2_DIV_MASK (0xFFU) #define I2S_RCR2_DIV_SHIFT (0U) #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) #define I2S_RCR2_BYP_MASK (0x800000U) #define I2S_RCR2_BYP_SHIFT (23U) /*! BYP - Bit Clock Bypass * 0b0..Internal bit clock is generated from bit clock divider. * 0b1..Internal bit clock is divide by one of the audio master clock. */ #define I2S_RCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK) #define I2S_RCR2_BCD_MASK (0x1000000U) #define I2S_RCR2_BCD_SHIFT (24U) /*! BCD - Bit Clock Direction * 0b0..Bit clock is generated externally in Slave mode. * 0b1..Bit clock is generated internally in Master mode. */ #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) #define I2S_RCR2_BCP_MASK (0x2000000U) #define I2S_RCR2_BCP_SHIFT (25U) /*! BCP - Bit Clock Polarity * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. */ #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) #define I2S_RCR2_MSEL_MASK (0xC000000U) #define I2S_RCR2_MSEL_SHIFT (26U) /*! MSEL - MCLK Select * 0b00..Bus Clock selected. * 0b01..Master Clock (MCLK) 1 option selected. * 0b10..Master Clock (MCLK) 2 option selected. * 0b11..Master Clock (MCLK) 3 option selected. */ #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) #define I2S_RCR2_BCI_MASK (0x10000000U) #define I2S_RCR2_BCI_SHIFT (28U) /*! BCI - Bit Clock Input * 0b0..No effect. * 0b1..Internal logic is clocked as if bit clock was externally generated. */ #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) #define I2S_RCR2_BCS_MASK (0x20000000U) #define I2S_RCR2_BCS_SHIFT (29U) /*! BCS - Bit Clock Swap * 0b0..Use the normal bit clock source. * 0b1..Swap the bit clock source. */ #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) #define I2S_RCR2_SYNC_MASK (0xC0000000U) #define I2S_RCR2_SYNC_SHIFT (30U) /*! SYNC - Synchronous Mode * 0b00..Asynchronous mode. * 0b01..Synchronous with transmitter. * 0b10..Reserved. * 0b11..Reserved. */ #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) /*! @} */ /*! @name RCR3 - SAI Receive Configuration 3 Register */ /*! @{ */ #define I2S_RCR3_WDFL_MASK (0x1FU) #define I2S_RCR3_WDFL_SHIFT (0U) #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) #define I2S_RCR3_RCE_MASK (0xFF0000U) #define I2S_RCR3_RCE_SHIFT (16U) #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) #define I2S_RCR3_CFR_MASK (0xFF000000U) #define I2S_RCR3_CFR_SHIFT (24U) #define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) /*! @} */ /*! @name RCR4 - SAI Receive Configuration 4 Register */ /*! @{ */ #define I2S_RCR4_FSD_MASK (0x1U) #define I2S_RCR4_FSD_SHIFT (0U) /*! FSD - Frame Sync Direction * 0b0..Frame Sync is generated externally in Slave mode. * 0b1..Frame Sync is generated internally in Master mode. */ #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) #define I2S_RCR4_FSP_MASK (0x2U) #define I2S_RCR4_FSP_SHIFT (1U) /*! FSP - Frame Sync Polarity * 0b0..Frame sync is active high. * 0b1..Frame sync is active low. */ #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) #define I2S_RCR4_ONDEM_MASK (0x4U) #define I2S_RCR4_ONDEM_SHIFT (2U) /*! ONDEM - On Demand Mode * 0b0..Internal frame sync is generated continuously. * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. */ #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) #define I2S_RCR4_FSE_MASK (0x8U) #define I2S_RCR4_FSE_SHIFT (3U) /*! FSE - Frame Sync Early * 0b0..Frame sync asserts with the first bit of the frame. * 0b1..Frame sync asserts one bit before the first bit of the frame. */ #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) #define I2S_RCR4_MF_MASK (0x10U) #define I2S_RCR4_MF_SHIFT (4U) /*! MF - MSB First * 0b0..LSB is received first. * 0b1..MSB is received first. */ #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) #define I2S_RCR4_SYWD_MASK (0x1F00U) #define I2S_RCR4_SYWD_SHIFT (8U) #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) #define I2S_RCR4_FRSZ_MASK (0x1F0000U) #define I2S_RCR4_FRSZ_SHIFT (16U) #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) #define I2S_RCR4_FPACK_MASK (0x3000000U) #define I2S_RCR4_FPACK_SHIFT (24U) /*! FPACK - FIFO Packing Mode * 0b00..FIFO packing is disabled * 0b01..Reserved. * 0b10..8-bit FIFO packing is enabled * 0b11..16-bit FIFO packing is enabled */ #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) #define I2S_RCR4_FCOMB_MASK (0xC000000U) #define I2S_RCR4_FCOMB_SHIFT (26U) /*! FCOMB - FIFO Combine Mode * 0b00..FIFO combine mode disabled. * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers). * 0b10..FIFO combine mode enabled on FIFO reads (by software). * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). */ #define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) #define I2S_RCR4_FCONT_MASK (0x10000000U) #define I2S_RCR4_FCONT_SHIFT (28U) /*! FCONT - FIFO Continue on Error * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been * cleared. 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the * FIFO warning flag has been cleared. */ #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) /*! @} */ /*! @name RCR5 - SAI Receive Configuration 5 Register */ /*! @{ */ #define I2S_RCR5_FBT_MASK (0x1F00U) #define I2S_RCR5_FBT_SHIFT (8U) #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) #define I2S_RCR5_W0W_MASK (0x1F0000U) #define I2S_RCR5_W0W_SHIFT (16U) #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) #define I2S_RCR5_WNW_MASK (0x1F000000U) #define I2S_RCR5_WNW_SHIFT (24U) #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) /*! @} */ /*! @name RDR - SAI Receive Data Register */ /*! @{ */ #define I2S_RDR_RDR_MASK (0xFFFFFFFFU) #define I2S_RDR_RDR_SHIFT (0U) #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) /*! @} */ /* The count of I2S_RDR */ #define I2S_RDR_COUNT (8U) /*! @name RFR - SAI Receive FIFO Register */ /*! @{ */ #define I2S_RFR_RFP_MASK (0xFFU) #define I2S_RFR_RFP_SHIFT (0U) #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) #define I2S_RFR_RCP_MASK (0x8000U) #define I2S_RFR_RCP_SHIFT (15U) /*! RCP - Receive Channel Pointer * 0b0..No effect. * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. */ #define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) #define I2S_RFR_WFP_MASK (0xFF0000U) #define I2S_RFR_WFP_SHIFT (16U) #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) /*! @} */ /* The count of I2S_RFR */ #define I2S_RFR_COUNT (8U) /*! @name RMR - SAI Receive Mask Register */ /*! @{ */ #define I2S_RMR_RWM_MASK (0xFFFFFFFFU) #define I2S_RMR_RWM_SHIFT (0U) /*! RWM - Receive Word Mask * 0b00000000000000000000000000000000..Word N is enabled. * 0b00000000000000000000000000000001..Word N is masked. */ #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) /*! @} */ /*! @name RTCR - SAI Receive Timestamp Control Register */ /*! @{ */ #define I2S_RTCR_TSEN_MASK (0x1U) #define I2S_RTCR_TSEN_SHIFT (0U) /*! TSEN - Timestamp Enable * 0b0..Timestamp counter is disabled. * 0b1..Timestamp counter is enabled. */ #define I2S_RTCR_TSEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSEN_SHIFT)) & I2S_RTCR_TSEN_MASK) #define I2S_RTCR_TSINC_MASK (0x2U) #define I2S_RTCR_TSINC_SHIFT (1U) /*! TSINC - Timestamp Increment * 0b0..Timestamp counter starts to increment when enabled and the bit counter has incremented. * 0b1..Timestamp counter starts to increment when enabled. */ #define I2S_RTCR_TSINC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSINC_SHIFT)) & I2S_RTCR_TSINC_MASK) #define I2S_RTCR_RTSC_MASK (0x100U) #define I2S_RTCR_RTSC_SHIFT (8U) /*! RTSC - Reset Timestamp Counter * 0b0..Timestamp counter is not reset. * 0b1..Timestamp counter is reset. */ #define I2S_RTCR_RTSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_RTSC_SHIFT)) & I2S_RTCR_RTSC_MASK) #define I2S_RTCR_RBC_MASK (0x200U) #define I2S_RTCR_RBC_SHIFT (9U) /*! RBC - Reset Bit Counter * 0b0..Bit counter is not reset. * 0b1..Bit counter is reset. */ #define I2S_RTCR_RBC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_RBC_SHIFT)) & I2S_RTCR_RBC_MASK) /*! @} */ /*! @name RTSR - SAI Receive Timestamp Register */ /*! @{ */ #define I2S_RTSR_TSC_MASK (0xFFFFFFFFU) #define I2S_RTSR_TSC_SHIFT (0U) #define I2S_RTSR_TSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTSR_TSC_SHIFT)) & I2S_RTSR_TSC_MASK) /*! @} */ /*! @name RBCR - SAI Receive Bit Count Register */ /*! @{ */ #define I2S_RBCR_BCNT_MASK (0xFFFFFFFFU) #define I2S_RBCR_BCNT_SHIFT (0U) #define I2S_RBCR_BCNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RBCR_BCNT_SHIFT)) & I2S_RBCR_BCNT_MASK) /*! @} */ /*! @name RBCTR - SAI Receive Bit Count Timestamp Register */ /*! @{ */ #define I2S_RBCTR_BCTS_MASK (0xFFFFFFFFU) #define I2S_RBCTR_BCTS_SHIFT (0U) #define I2S_RBCTR_BCTS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RBCTR_BCTS_SHIFT)) & I2S_RBCTR_BCTS_MASK) /*! @} */ /*! @name MCR - SAI MCLK Control Register */ /*! @{ */ #define I2S_MCR_DIV_MASK (0xFFU) #define I2S_MCR_DIV_SHIFT (0U) #define I2S_MCR_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIV_SHIFT)) & I2S_MCR_DIV_MASK) #define I2S_MCR_DIVEN_MASK (0x800000U) #define I2S_MCR_DIVEN_SHIFT (23U) /*! DIVEN - MCLK Post Divide Enable * 0b0..Output on MCLK signal pin is the audio master clock. * 0b1..Output on MCLK signal pin is a post-divided version of audio master clock. */ #define I2S_MCR_DIVEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIVEN_SHIFT)) & I2S_MCR_DIVEN_MASK) #define I2S_MCR_MOE_MASK (0x40000000U) #define I2S_MCR_MOE_SHIFT (30U) /*! MOE - MCLK Output Enable * 0b0..MCLK signal pin is an input. * 0b1..MCLK signal pin is an output. */ #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) /*! @} */ /*! * @} */ /* end of group I2S_Register_Masks */ /* I2S - Peripheral instance base addresses */ /** Peripheral I2S2 base address */ #define I2S2_BASE (0x30020000u) /** Peripheral I2S2 base pointer */ #define I2S2 ((I2S_Type *)I2S2_BASE) /** Peripheral I2S3 base address */ #define I2S3_BASE (0x30030000u) /** Peripheral I2S3 base pointer */ #define I2S3 ((I2S_Type *)I2S3_BASE) /** Peripheral I2S5 base address */ #define I2S5_BASE (0x30050000u) /** Peripheral I2S5 base pointer */ #define I2S5 ((I2S_Type *)I2S5_BASE) /** Peripheral I2S6 base address */ #define I2S6_BASE (0x30060000u) /** Peripheral I2S6 base pointer */ #define I2S6 ((I2S_Type *)I2S6_BASE) /** Peripheral I2S7 base address */ #define I2S7_BASE (0x300B0000u) /** Peripheral I2S7 base pointer */ #define I2S7 ((I2S_Type *)I2S7_BASE) /** Array initializer of I2S peripheral base addresses */ #define I2S_BASE_ADDRS \ { \ 0u, 0u, I2S2_BASE, I2S3_BASE, 0u, I2S5_BASE, I2S6_BASE, I2S7_BASE \ } /** Array initializer of I2S peripheral base pointers */ #define I2S_BASE_PTRS \ { \ (I2S_Type *)0u, (I2S_Type *)0u, I2S2, I2S3, (I2S_Type *)0u, I2S5, I2S6, I2S7 \ } /** Interrupt vectors for the I2S peripheral type */ #define I2S_RX_IRQS \ { \ NotAvail_IRQn, NotAvail_IRQn, I2S2_IRQn, I2S3_IRQn, NotAvail_IRQn, I2S56_IRQn, I2S56_IRQn, I2S7_IRQn \ } #define I2S_TX_IRQS \ { \ NotAvail_IRQn, NotAvail_IRQn, I2S2_IRQn, I2S3_IRQn, NotAvail_IRQn, I2S56_IRQn, I2S56_IRQn, I2S7_IRQn \ } /*! * @} */ /* end of group I2S_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IOMUXC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer * @{ */ /** IOMUXC - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[32]; __IO uint32_t SW_MUX_CTL_PAD[141]; /**< Pad Mux Register, array offset: 0x20, array step: 0x4 */ __IO uint32_t SW_PAD_CTL_PAD[154]; /**< Pad Control Register, array offset: 0x254, array step: 0x4 */ __IO uint32_t SELECT_INPUT[78]; /**< Select Input Register, array offset: 0x4BC, array step: 0x4 */ } IOMUXC_Type; /* ---------------------------------------------------------------------------- -- IOMUXC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks * @{ */ /*! @name SW_MUX_CTL_PAD - Pad Mux Register */ /*! @{ */ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U) #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) /*! MUX_MODE * 0b000..Select signal SRC_BOOT_MODE2 * 0b001..Select signal I2C1_SCL- Configure register IOMUXC_I2C1_SCL_SELECT_INPUTSelect Input Register for mode ALT1. */ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) /*! SION * 0b1..Force input path of pad BOOT_MODE2 * 0b0..Input Path is determined by functionality of the selected mux mode (regular). */ #define IOMUXC_SW_MUX_CTL_PAD_SION(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) /*! @} */ /* The count of IOMUXC_SW_MUX_CTL_PAD */ #define IOMUXC_SW_MUX_CTL_PAD_COUNT (141U) /*! @name SW_PAD_CTL_PAD - Pad Control Register */ /*! @{ */ #define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x7U) #define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (0U) /*! DSE - Drive Strength Field * 0b00x..Drive strength X1 * 0b01x..Drive strength X4 * 0b10x..Drive strength X2 * 0b11x..Drive strength X6 */ #define IOMUXC_SW_PAD_CTL_PAD_DSE(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) #define IOMUXC_SW_PAD_CTL_PAD_FSEL_MASK (0x18U) #define IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT (3U) /*! FSEL - Slew Rate Field * 0b0x..Select slow slew rate (IO.SR = 1) * 0b1x..Select fast slew rate (IO.SR = 0) */ #define IOMUXC_SW_PAD_CTL_PAD_FSEL(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_FSEL_MASK) #define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x20U) #define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (5U) /*! ODE - Open Drain Enable Field * 0b0..Disable open-drain mode * 0b1..Enable open-drain mode */ #define IOMUXC_SW_PAD_CTL_PAD_ODE(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) #define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x40U) #define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (6U) /*! PUE * 0b0..Select pull-down resistor, the resistor is enabled when IO.PE=1 * 0b1..Select pull-up resistor, the resistor is enabled when IO.PE=1 */ #define IOMUXC_SW_PAD_CTL_PAD_PUE(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK) #define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x80U) #define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (7U) /*! HYS - Hysteresis Enable Field * 0b0..Select CMOS input, IO.IS=0 * 0b1..Select schmitt input, IO.IS=1 */ #define IOMUXC_SW_PAD_CTL_PAD_HYS(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK) #define IOMUXC_SW_PAD_CTL_PAD_PE_MASK (0x100U) #define IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT (8U) /*! PE - Pull Resistors Enable Field * 0b0..Disable pull resistor, IO.PE=0 * 0b1..Enable pull resistor, IO.PE=1 */ #define IOMUXC_SW_PAD_CTL_PAD_PE(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PE_MASK) /*! @} */ /* The count of IOMUXC_SW_PAD_CTL_PAD */ #define IOMUXC_SW_PAD_CTL_PAD_COUNT (154U) /*! @name SELECT_INPUT - Select Input Register */ /*! @{ */ #define IOMUXC_SELECT_INPUT_DAISY_MASK \ (0xFU) /* Merged from fields with different position or width, of widths (1, 2, 3, 4), largest definition used */ #define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) /*! DAISY - Input Select (DAISY) Field * 0b0..Selecting ALT5 mode of pad GPIO1_IO05 for CCM_PMIC_READY. * 0b1..Selecting ALT5 mode of pad GPIO1_IO11 for CCM_PMIC_READY. */ #define IOMUXC_SELECT_INPUT_DAISY(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & \ IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3, 4), \ largest definition used */ /*! @} */ /* The count of IOMUXC_SELECT_INPUT */ #define IOMUXC_SELECT_INPUT_COUNT (78U) /*! * @} */ /* end of group IOMUXC_Register_Masks */ /* IOMUXC - Peripheral instance base addresses */ /** Peripheral IOMUXC base address */ #define IOMUXC_BASE (0x30330000u) /** Peripheral IOMUXC base pointer */ #define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) /** Array initializer of IOMUXC peripheral base addresses */ #define IOMUXC_BASE_ADDRS \ { \ IOMUXC_BASE \ } /** Array initializer of IOMUXC peripheral base pointers */ #define IOMUXC_BASE_PTRS \ { \ IOMUXC \ } /*! * @} */ /* end of group IOMUXC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IOMUXC_GPR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer * @{ */ /** IOMUXC_GPR - Register Layout Typedef */ typedef struct { uint32_t GPR0; /**< General Purpose Register 0, offset: 0x0 */ __IO uint32_t GPR1; /**< General Purpose Register 1, offset: 0x4 */ __IO uint32_t GPR2; /**< General Purpose Register 2, offset: 0x8 */ __IO uint32_t GPR3; /**< General Purpose Register 3, offset: 0xC */ __IO uint32_t GPR4; /**< General Purpose Register 4, offset: 0x10 */ __IO uint32_t GPR5; /**< General Purpose Register 5, offset: 0x14 */ __IO uint32_t GPR6; /**< General Purpose Register 6, offset: 0x18 */ __IO uint32_t GPR7; /**< General Purpose Register 7, offset: 0x1C */ __IO uint32_t GPR8; /**< General Purpose Register 8, offset: 0x20 */ uint32_t GPR9; /**< General Purpose Register 9, offset: 0x24 */ __IO uint32_t GPR10; /**< General Purpose Register 10, offset: 0x28 */ __IO uint32_t GPR11; /**< General Purpose Register 11, offset: 0x2C */ uint32_t GPR12; /**< General Purpose Register 12, offset: 0x30 */ __IO uint32_t GPR13; /**< General Purpose Register 13, offset: 0x34 */ uint32_t GPR14; /**< General Purpose Register 14, offset: 0x38 */ uint32_t GPR15; /**< General Purpose Register 15, offset: 0x3C */ uint32_t GPR16; /**< General Purpose Register 16, offset: 0x40 */ uint32_t GPR17; /**< General Purpose Register 17, offset: 0x44 */ uint32_t GPR18; /**< General Purpose Register 18, offset: 0x48 */ uint32_t GPR19; /**< General Purpose Register 19, offset: 0x4C */ __IO uint32_t GPR20; /**< General Purpose Register 20, offset: 0x50 */ __IO uint32_t GPR21; /**< General Purpose Register 21, offset: 0x54 */ __IO uint32_t GPR22; /**< General Purpose Register 22, offset: 0x58 */ uint32_t GPR[25]; /**< General Purpose Register, array offset: 0x5C, array step: 0x4 */ } IOMUXC_GPR_Type; /* ---------------------------------------------------------------------------- -- IOMUXC_GPR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks * @{ */ /*! @name GPR1 - General Purpose Register 1 */ /*! @{ */ #define IOMUXC_GPR_GPR1_GPR_IRQ_MASK (0x1000U) #define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT (12U) #define IOMUXC_GPR_GPR1_GPR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT)) & IOMUXC_GPR_GPR1_GPR_IRQ_MASK) #define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK (0x2000U) #define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT (13U) /*! GPR_ENET1_TX_CLK_SEL * 0b0..ENET_TD2.ALT1 is input, input data is used as ENET1_IPG_CLK_RMII. * 0b1..ENET_TD2.ALT1 is output, output data comes from CCM_ENET_REF_CLK_ROOT. */ #define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT)) & \ IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK) #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK (0x800000U) #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT (23U) #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT)) & \ IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK) #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK (0xF0000000U) #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT (28U) #define IOMUXC_GPR_GPR1_GPR_DBG_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT)) & IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK) /*! @} */ /*! @name GPR2 - General Purpose Register 2 */ /*! @{ */ #define IOMUXC_GPR_GPR2_GPR_SAI2_EXT_MCLK_EN_MASK (0x2U) #define IOMUXC_GPR_GPR2_GPR_SAI2_EXT_MCLK_EN_SHIFT (1U) /*! GPR_SAI2_EXT_MCLK_EN * 0b1..the corresponding pads are input. * 0b0..the corresponding pads are output. */ #define IOMUXC_GPR_GPR2_GPR_SAI2_EXT_MCLK_EN(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_GPR_SAI2_EXT_MCLK_EN_SHIFT)) & \ IOMUXC_GPR_GPR2_GPR_SAI2_EXT_MCLK_EN_MASK) #define IOMUXC_GPR_GPR2_GPR_SAI3_EXT_MCLK_EN_MASK (0x4U) #define IOMUXC_GPR_GPR2_GPR_SAI3_EXT_MCLK_EN_SHIFT (2U) /*! GPR_SAI3_EXT_MCLK_EN * 0b1..the corresponding pads are input. * 0b0..the corresponding pads are output. */ #define IOMUXC_GPR_GPR2_GPR_SAI3_EXT_MCLK_EN(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_GPR_SAI3_EXT_MCLK_EN_SHIFT)) & \ IOMUXC_GPR_GPR2_GPR_SAI3_EXT_MCLK_EN_MASK) #define IOMUXC_GPR_GPR2_GPR_SAI5_EXT_MCLK_EN_MASK (0x10U) #define IOMUXC_GPR_GPR2_GPR_SAI5_EXT_MCLK_EN_SHIFT (4U) /*! GPR_SAI5_EXT_MCLK_EN * 0b1..the corresponding pads are input. * 0b0..the corresponding pads are output. */ #define IOMUXC_GPR_GPR2_GPR_SAI5_EXT_MCLK_EN(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_GPR_SAI5_EXT_MCLK_EN_SHIFT)) & \ IOMUXC_GPR_GPR2_GPR_SAI5_EXT_MCLK_EN_MASK) #define IOMUXC_GPR_GPR2_GPR_SAI6_EXT_MCLK_EN_MASK (0x20U) #define IOMUXC_GPR_GPR2_GPR_SAI6_EXT_MCLK_EN_SHIFT (5U) /*! GPR_SAI6_EXT_MCLK_EN * 0b1..the corresponding pads are input. * 0b0..the corresponding pads are output. */ #define IOMUXC_GPR_GPR2_GPR_SAI6_EXT_MCLK_EN(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_GPR_SAI6_EXT_MCLK_EN_SHIFT)) & \ IOMUXC_GPR_GPR2_GPR_SAI6_EXT_MCLK_EN_MASK) #define IOMUXC_GPR_GPR2_GPR_SAI7_EXT_MCLK_EN_MASK (0x40U) #define IOMUXC_GPR_GPR2_GPR_SAI7_EXT_MCLK_EN_SHIFT (6U) /*! GPR_SAI7_EXT_MCLK_EN * 0b1..the corresponding pads are input. * 0b0..the corresponding pads are output. */ #define IOMUXC_GPR_GPR2_GPR_SAI7_EXT_MCLK_EN(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_GPR_SAI7_EXT_MCLK_EN_SHIFT)) & \ IOMUXC_GPR_GPR2_GPR_SAI7_EXT_MCLK_EN_MASK) #define IOMUXC_GPR_GPR2_GPR_GPT4_EXT_CLK_SEL_MASK (0xF00U) #define IOMUXC_GPR_GPR2_GPR_GPT4_EXT_CLK_SEL_SHIFT (8U) /*! GPR_GPT4_EXT_CLK_SEL * 0b0000..SAI7_TX_SYNC * 0b0001..SAI2_TX_SYNC * 0b0010..SAI3_TX_SYNC * 0b0011..Reserved * 0b0100..SAI5_TX_SYNC * 0b0101..SAI6_TX_SYNC * 0b0110..SAI7_RX_SYNC * 0b0111..SAI2_RX_SYNC * 0b1000..SAI3_RX_SYNC * 0b1001..Reserved * 0b1010..SAI5_RX_SYNC */ #define IOMUXC_GPR_GPR2_GPR_GPT4_EXT_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_GPR_GPT4_EXT_CLK_SEL_SHIFT)) & \ IOMUXC_GPR_GPR2_GPR_GPT4_EXT_CLK_SEL_MASK) #define IOMUXC_GPR_GPR2_GPR_GPT5_EXT_CLK_SEL_MASK (0xF000U) #define IOMUXC_GPR_GPR2_GPR_GPT5_EXT_CLK_SEL_SHIFT (12U) /*! GPR_GPT5_EXT_CLK_SEL * 0b0000..SAI7_TX_SYNC * 0b0001..SAI2_TX_SYNC * 0b0010..SAI3_TX_SYNC * 0b0011..Reserved * 0b0100..SAI5_TX_SYNC * 0b0101..SAI6_TX_SYNC * 0b0110..SAI7_RX_SYNC * 0b0111..SAI2_RX_SYNC * 0b1000..SAI3_RX_SYNC * 0b1001..Reserved * 0b1010..SAI5_RX_SYNC */ #define IOMUXC_GPR_GPR2_GPR_GPT5_EXT_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_GPR_GPT5_EXT_CLK_SEL_SHIFT)) & \ IOMUXC_GPR_GPR2_GPR_GPT5_EXT_CLK_SEL_MASK) #define IOMUXC_GPR_GPR2_GPR_GPT6_EXT_CLK_SEL_MASK (0xF0000U) #define IOMUXC_GPR_GPR2_GPR_GPT6_EXT_CLK_SEL_SHIFT (16U) /*! GPR_GPT6_EXT_CLK_SEL * 0b0000..SAI7_TX_SYNC * 0b0001..SAI2_TX_SYNC * 0b0010..SAI3_TX_SYNC * 0b0011..Reserved * 0b0100..SAI5_TX_SYNC * 0b0101..SAI6_TX_SYNC * 0b0110..SAI7_RX_SYNC * 0b0111..SAI2_RX_SYNC * 0b1000..SAI3_RX_SYNC * 0b1001..Reserved * 0b1010..SAI5_RX_SYNC */ #define IOMUXC_GPR_GPR2_GPR_GPT6_EXT_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_GPR_GPT6_EXT_CLK_SEL_SHIFT)) & \ IOMUXC_GPR_GPR2_GPR_GPT6_EXT_CLK_SEL_MASK) /*! @} */ /*! @name GPR3 - General Purpose Register 3 */ /*! @{ */ #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_MASK (0x1U) #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_SHIFT (0U) #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_SHIFT)) & \ IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_MASK) #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_MASK (0x2U) #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_SHIFT (1U) #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_SHIFT)) & \ IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_MASK) #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_MASK (0x4U) #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_SHIFT (2U) #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_SHIFT)) & \ IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_MASK) #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_MASK (0x8U) #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_SHIFT (3U) #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_SHIFT)) & \ IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_MASK) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_MASK (0x10U) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_SHIFT (4U) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_SHIFT)) & \ IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_MASK) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_MASK (0x20U) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_SHIFT (5U) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_SHIFT)) & \ IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_MASK) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_MASK (0x40U) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_SHIFT (6U) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_SHIFT)) & \ IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_MASK) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_MASK (0x80U) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_SHIFT (7U) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_SHIFT)) & \ IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_MASK) #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_pndg_MASK (0x10000U) #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_pndg_SHIFT (16U) #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_pndg(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_pndg_SHIFT)) & \ IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_pndg_MASK) #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_pndg_MASK (0x20000U) #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_pndg_SHIFT (17U) #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_pndg(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_pndg_SHIFT)) & \ IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_pndg_MASK) #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_pndg_MASK (0x40000U) #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_pndg_SHIFT (18U) #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_pndg(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_pndg_SHIFT)) & \ IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_pndg_MASK) #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_pndg_MASK (0x80000U) #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_pndg_SHIFT (19U) #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_pndg(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_pndg_SHIFT)) & \ IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_pndg_MASK) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_pndg_MASK (0x100000U) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_pndg_SHIFT (20U) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_pndg(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_pndg_SHIFT)) & \ IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_pndg_MASK) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_pndg_MASK (0x200000U) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_pndg_SHIFT (21U) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_pndg(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_pndg_SHIFT)) & \ IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_pndg_MASK) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_pndg_MASK (0x400000U) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_pndg_SHIFT (22U) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_pndg(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_pndg_SHIFT)) & \ IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_pndg_MASK) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_pndg_MASK (0x800000U) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_pndg_SHIFT (23U) #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_pndg(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_pndg_SHIFT)) & \ IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_pndg_MASK) /*! @} */ /*! @name GPR4 - General Purpose Register 4 */ /*! @{ */ #define IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP_MASK (0x1U) #define IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP_SHIFT (0U) #define IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP_SHIFT)) & \ IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP_MASK) #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK (0x8U) #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT (3U) #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT)) & \ IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK) #define IOMUXC_GPR_GPR4_GPR_SDMA2_IPG_STOP_MASK (0x10U) #define IOMUXC_GPR_GPR4_GPR_SDMA2_IPG_STOP_SHIFT (4U) #define IOMUXC_GPR_GPR4_GPR_SDMA2_IPG_STOP(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_SDMA2_IPG_STOP_SHIFT)) & \ IOMUXC_GPR_GPR4_GPR_SDMA2_IPG_STOP_MASK) #define IOMUXC_GPR_GPR4_GPR_SDMA3_IPG_STOP_MASK (0x1000U) #define IOMUXC_GPR_GPR4_GPR_SDMA3_IPG_STOP_SHIFT (12U) #define IOMUXC_GPR_GPR4_GPR_SDMA3_IPG_STOP(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_SDMA3_IPG_STOP_SHIFT)) & \ IOMUXC_GPR_GPR4_GPR_SDMA3_IPG_STOP_MASK) #define IOMUXC_GPR_GPR4_SDMA1_IPG_STOP_ACK_MASK (0x10000U) #define IOMUXC_GPR_GPR4_SDMA1_IPG_STOP_ACK_SHIFT (16U) #define IOMUXC_GPR_GPR4_SDMA1_IPG_STOP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SDMA1_IPG_STOP_ACK_SHIFT)) & \ IOMUXC_GPR_GPR4_SDMA1_IPG_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_SDMA3_IPG_STOP_ACK_MASK (0x40000U) #define IOMUXC_GPR_GPR4_SDMA3_IPG_STOP_ACK_SHIFT (18U) #define IOMUXC_GPR_GPR4_SDMA3_IPG_STOP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SDMA3_IPG_STOP_ACK_SHIFT)) & \ IOMUXC_GPR_GPR4_SDMA3_IPG_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_ENET1_IPG_STOP_ACK_MASK (0x80000U) #define IOMUXC_GPR_GPR4_ENET1_IPG_STOP_ACK_SHIFT (19U) #define IOMUXC_GPR_GPR4_ENET1_IPG_STOP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET1_IPG_STOP_ACK_SHIFT)) & \ IOMUXC_GPR_GPR4_ENET1_IPG_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_SDMA2_IPG_STOP_ACK_MASK (0x100000U) #define IOMUXC_GPR_GPR4_SDMA2_IPG_STOP_ACK_SHIFT (20U) #define IOMUXC_GPR_GPR4_SDMA2_IPG_STOP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SDMA2_IPG_STOP_ACK_SHIFT)) & \ IOMUXC_GPR_GPR4_SDMA2_IPG_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_SAI7_IPG_STOP_ACK_MASK (0x200000U) #define IOMUXC_GPR_GPR4_SAI7_IPG_STOP_ACK_SHIFT (21U) #define IOMUXC_GPR_GPR4_SAI7_IPG_STOP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI7_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI7_IPG_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_SAI2_IPG_STOP_ACK_MASK (0x400000U) #define IOMUXC_GPR_GPR4_SAI2_IPG_STOP_ACK_SHIFT (22U) #define IOMUXC_GPR_GPR4_SAI2_IPG_STOP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_IPG_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_SAI3_IPG_STOP_ACK_MASK (0x800000U) #define IOMUXC_GPR_GPR4_SAI3_IPG_STOP_ACK_SHIFT (23U) #define IOMUXC_GPR_GPR4_SAI3_IPG_STOP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_IPG_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_SAI5_IPG_STOP_ACK_MASK (0x2000000U) #define IOMUXC_GPR_GPR4_SAI5_IPG_STOP_ACK_SHIFT (25U) #define IOMUXC_GPR_GPR4_SAI5_IPG_STOP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI5_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI5_IPG_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_SAI6_IPG_STOP_ACK_MASK (0x4000000U) #define IOMUXC_GPR_GPR4_SAI6_IPG_STOP_ACK_SHIFT (26U) #define IOMUXC_GPR_GPR4_SAI6_IPG_STOP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI6_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI6_IPG_STOP_ACK_MASK) #define IOMUXC_GPR_GPR4_PDM_IPG_STOP_ACK_MASK (0x8000000U) #define IOMUXC_GPR_GPR4_PDM_IPG_STOP_ACK_SHIFT (27U) #define IOMUXC_GPR_GPR4_PDM_IPG_STOP_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PDM_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PDM_IPG_STOP_ACK_MASK) /*! @} */ /*! @name GPR5 - General Purpose Register 5 */ /*! @{ */ #define IOMUXC_GPR_GPR5_GPR_PDM_CLK_SEL_MASK (0xFU) #define IOMUXC_GPR_GPR5_GPR_PDM_CLK_SEL_SHIFT (0U) /*! GPR_PDM_CLK_SEL * 0b0000..normal clock. * 0b0001..32K clock. */ #define IOMUXC_GPR_GPR5_GPR_PDM_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_PDM_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPR_PDM_CLK_SEL_MASK) #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK (0x40U) #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT (6U) /*! GPR_WDOG1_MASK * 0b0..WDOG1 low will make the GPIO1_IO02.ALT5_OUT low. * 0b1..WDOG1 low will NOT impact the GPIO1_IO02.ALT5_OUT. */ #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK) #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK (0x80U) #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT (7U) /*! GPR_WDOG2_MASK * 0b0..WDOG2 low will make the GPIO1_IO02.ALT5_OUT low. * 0b1..WDOG2 low will NOT impact the GPIO1_IO02.ALT5_OUT. */ #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK) #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK (0x100000U) #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT (20U) /*! GPR_WDOG3_MASK * 0b0..WDOG3 low will make the GPIO1_IO02.ALT5_OUT low. * 0b1..WDOG3 low will NOT impact the GPIO1_IO02.ALT5_OUT. */ #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT)) & IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK) /*! @} */ /*! @name GPR6 - General Purpose Register 6 */ /*! @{ */ #define IOMUXC_GPR_GPR6_GPR_SAI7_SEL3_MASK (0x1FU) #define IOMUXC_GPR_GPR6_GPR_SAI7_SEL3_SHIFT (0U) #define IOMUXC_GPR_GPR6_GPR_SAI7_SEL3(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_GPR_SAI7_SEL3_SHIFT)) & IOMUXC_GPR_GPR6_GPR_SAI7_SEL3_MASK) #define IOMUXC_GPR_GPR6_GPR_SAI7_SEL1_MASK (0x20U) #define IOMUXC_GPR_GPR6_GPR_SAI7_SEL1_SHIFT (5U) #define IOMUXC_GPR_GPR6_GPR_SAI7_SEL1(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_GPR_SAI7_SEL1_SHIFT)) & IOMUXC_GPR_GPR6_GPR_SAI7_SEL1_MASK) #define IOMUXC_GPR_GPR6_GPR_SAI7_SEL2_MASK (0x1F00U) #define IOMUXC_GPR_GPR6_GPR_SAI7_SEL2_SHIFT (8U) #define IOMUXC_GPR_GPR6_GPR_SAI7_SEL2(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_GPR_SAI7_SEL2_SHIFT)) & IOMUXC_GPR_GPR6_GPR_SAI7_SEL2_MASK) #define IOMUXC_GPR_GPR6_GPR_SAI7_MCLK_OUT_SEL_MASK (0x2000U) #define IOMUXC_GPR_GPR6_GPR_SAI7_MCLK_OUT_SEL_SHIFT (13U) #define IOMUXC_GPR_GPR6_GPR_SAI7_MCLK_OUT_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_GPR_SAI7_MCLK_OUT_SEL_SHIFT)) & \ IOMUXC_GPR_GPR6_GPR_SAI7_MCLK_OUT_SEL_MASK) #define IOMUXC_GPR_GPR6_GPR_SAI2_SEL3_MASK (0x1F0000U) #define IOMUXC_GPR_GPR6_GPR_SAI2_SEL3_SHIFT (16U) /*! GPR_SAI2_SEL3 * 0b00000..SAI1_CLK_ROOT * 0b00001..SAI2_CLK_ROOT * 0b00010..SAI3_CLK_ROOT * 0b00011..SAI4_CLK_ROOT * 0b00100..SAI5_CLK_ROOT * 0b00101..SAI6_CLK_ROOT * 0b00110..SAI7_CLK_ROOT * 0b00111..Reserved * 0b01000..SAI2_MCLK * 0b01001..SAI3_MCLK * 0b01010..Reserved * 0b01011..SAI5_MCLK * 0b01100..SAI6_MCLK * 0b01101..SAI7_MCLK * 0b01110..SPDIF1_CLK_ROOT * 0b01111..Reserved * 0b10000..SPDIF1_EXTCLK * 0b10001..SPDIF1_SRCCLK * 0b10010..SPDIF1_OUTCLK * 0b10011..Reserved */ #define IOMUXC_GPR_GPR6_GPR_SAI2_SEL3(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_GPR_SAI2_SEL3_SHIFT)) & IOMUXC_GPR_GPR6_GPR_SAI2_SEL3_MASK) #define IOMUXC_GPR_GPR6_GPR_SAI2_SEL1_MASK (0x200000U) #define IOMUXC_GPR_GPR6_GPR_SAI2_SEL1_SHIFT (21U) #define IOMUXC_GPR_GPR6_GPR_SAI2_SEL1(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_GPR_SAI2_SEL1_SHIFT)) & IOMUXC_GPR_GPR6_GPR_SAI2_SEL1_MASK) #define IOMUXC_GPR_GPR6_GPR_SAI2_SEL2_MASK (0x1F000000U) #define IOMUXC_GPR_GPR6_GPR_SAI2_SEL2_SHIFT (24U) /*! GPR_SAI2_SEL2 * 0b00000..SAI1_CLK_ROOT * 0b00001..SAI2_CLK_ROOT * 0b00010..SAI3_CLK_ROOT * 0b00011..SAI4_CLK_ROOT * 0b00100..SAI5_CLK_ROOT * 0b00101..SAI6_CLK_ROOT * 0b00110..SAI7_CLK_ROOT * 0b00111..Reserved * 0b01000..SAI2_MCLK * 0b01001..SAI3_MCLK * 0b01010..Reserved * 0b01011..SAI5_MCLK * 0b01100..SAI6_MCLK * 0b01101..SAI7_MCLK * 0b01110..SPDIF1_CLK_ROOT * 0b01111..Reserved * 0b10000..SPDIF1_EXTCLK * 0b10001..SPDIF1_SRCCLK * 0b10010..SPDIF1_OUTCLK * 0b10011..Reserved */ #define IOMUXC_GPR_GPR6_GPR_SAI2_SEL2(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_GPR_SAI2_SEL2_SHIFT)) & IOMUXC_GPR_GPR6_GPR_SAI2_SEL2_MASK) #define IOMUXC_GPR_GPR6_GPR_SAI2_MCLK_OUT_SEL_MASK (0x20000000U) #define IOMUXC_GPR_GPR6_GPR_SAI2_MCLK_OUT_SEL_SHIFT (29U) #define IOMUXC_GPR_GPR6_GPR_SAI2_MCLK_OUT_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_GPR_SAI2_MCLK_OUT_SEL_SHIFT)) & \ IOMUXC_GPR_GPR6_GPR_SAI2_MCLK_OUT_SEL_MASK) /*! @} */ /*! @name GPR7 - General Purpose Register 7 */ /*! @{ */ #define IOMUXC_GPR_GPR7_GPR_SAI3_SEL3_MASK (0x1FU) #define IOMUXC_GPR_GPR7_GPR_SAI3_SEL3_SHIFT (0U) #define IOMUXC_GPR_GPR7_GPR_SAI3_SEL3(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GPR_SAI3_SEL3_SHIFT)) & IOMUXC_GPR_GPR7_GPR_SAI3_SEL3_MASK) #define IOMUXC_GPR_GPR7_GPR_SAI3_SEL1_MASK (0x20U) #define IOMUXC_GPR_GPR7_GPR_SAI3_SEL1_SHIFT (5U) #define IOMUXC_GPR_GPR7_GPR_SAI3_SEL1(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GPR_SAI3_SEL1_SHIFT)) & IOMUXC_GPR_GPR7_GPR_SAI3_SEL1_MASK) #define IOMUXC_GPR_GPR7_GPR_SAI3_SEL2_MASK (0x1F00U) #define IOMUXC_GPR_GPR7_GPR_SAI3_SEL2_SHIFT (8U) #define IOMUXC_GPR_GPR7_GPR_SAI3_SEL2(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GPR_SAI3_SEL2_SHIFT)) & IOMUXC_GPR_GPR7_GPR_SAI3_SEL2_MASK) #define IOMUXC_GPR_GPR7_GPR_SAI3_MCLK_OUT_SEL_MASK (0x2000U) #define IOMUXC_GPR_GPR7_GPR_SAI3_MCLK_OUT_SEL_SHIFT (13U) #define IOMUXC_GPR_GPR7_GPR_SAI3_MCLK_OUT_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GPR_SAI3_MCLK_OUT_SEL_SHIFT)) & \ IOMUXC_GPR_GPR7_GPR_SAI3_MCLK_OUT_SEL_MASK) /*! @} */ /*! @name GPR8 - General Purpose Register 8 */ /*! @{ */ #define IOMUXC_GPR_GPR8_GPR_SAI5_SEL3_MASK (0x1FU) #define IOMUXC_GPR_GPR8_GPR_SAI5_SEL3_SHIFT (0U) #define IOMUXC_GPR_GPR8_GPR_SAI5_SEL3(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_GPR_SAI5_SEL3_SHIFT)) & IOMUXC_GPR_GPR8_GPR_SAI5_SEL3_MASK) #define IOMUXC_GPR_GPR8_GPR_SAI5_SEL1_MASK (0x20U) #define IOMUXC_GPR_GPR8_GPR_SAI5_SEL1_SHIFT (5U) #define IOMUXC_GPR_GPR8_GPR_SAI5_SEL1(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_GPR_SAI5_SEL1_SHIFT)) & IOMUXC_GPR_GPR8_GPR_SAI5_SEL1_MASK) #define IOMUXC_GPR_GPR8_GPR_SAI5_SEL2_MASK (0x1F00U) #define IOMUXC_GPR_GPR8_GPR_SAI5_SEL2_SHIFT (8U) #define IOMUXC_GPR_GPR8_GPR_SAI5_SEL2(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_GPR_SAI5_SEL2_SHIFT)) & IOMUXC_GPR_GPR8_GPR_SAI5_SEL2_MASK) #define IOMUXC_GPR_GPR8_GPR_SAI5_MCLK_OUT_SEL_MASK (0x2000U) #define IOMUXC_GPR_GPR8_GPR_SAI5_MCLK_OUT_SEL_SHIFT (13U) #define IOMUXC_GPR_GPR8_GPR_SAI5_MCLK_OUT_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_GPR_SAI5_MCLK_OUT_SEL_SHIFT)) & \ IOMUXC_GPR_GPR8_GPR_SAI5_MCLK_OUT_SEL_MASK) #define IOMUXC_GPR_GPR8_GPR_SAI6_SEL3_MASK (0x1F0000U) #define IOMUXC_GPR_GPR8_GPR_SAI6_SEL3_SHIFT (16U) #define IOMUXC_GPR_GPR8_GPR_SAI6_SEL3(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_GPR_SAI6_SEL3_SHIFT)) & IOMUXC_GPR_GPR8_GPR_SAI6_SEL3_MASK) #define IOMUXC_GPR_GPR8_GPR_SAI6_SEL1_MASK (0x200000U) #define IOMUXC_GPR_GPR8_GPR_SAI6_SEL1_SHIFT (21U) #define IOMUXC_GPR_GPR8_GPR_SAI6_SEL1(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_GPR_SAI6_SEL1_SHIFT)) & IOMUXC_GPR_GPR8_GPR_SAI6_SEL1_MASK) #define IOMUXC_GPR_GPR8_GPR_SAI6_SEL2_MASK (0x1F000000U) #define IOMUXC_GPR_GPR8_GPR_SAI6_SEL2_SHIFT (24U) #define IOMUXC_GPR_GPR8_GPR_SAI6_SEL2(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_GPR_SAI6_SEL2_SHIFT)) & IOMUXC_GPR_GPR8_GPR_SAI6_SEL2_MASK) #define IOMUXC_GPR_GPR8_GPR_SAI6_MCLK_OUT_SEL_MASK (0x20000000U) #define IOMUXC_GPR_GPR8_GPR_SAI6_MCLK_OUT_SEL_SHIFT (29U) #define IOMUXC_GPR_GPR8_GPR_SAI6_MCLK_OUT_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_GPR_SAI6_MCLK_OUT_SEL_SHIFT)) & \ IOMUXC_GPR_GPR8_GPR_SAI6_MCLK_OUT_SEL_MASK) /*! @} */ /*! @name GPR10 - General Purpose Register 10 */ /*! @{ */ #define IOMUXC_GPR_GPR10_GPR_TZASC_EN_MASK (0x1U) #define IOMUXC_GPR_GPR10_GPR_TZASC_EN_SHIFT (0U) #define IOMUXC_GPR_GPR10_GPR_TZASC_EN(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_TZASC_EN_SHIFT)) & IOMUXC_GPR_GPR10_GPR_TZASC_EN_MASK) #define IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS_MASK (0x2U) #define IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS_SHIFT (1U) #define IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS_SHIFT)) & \ IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS_MASK) #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK (0x4U) #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT (2U) #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT)) & \ IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK) #define IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN_MASK (0x8U) #define IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN_SHIFT (3U) #define IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN_SHIFT)) & \ IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN_MASK) #define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN_MASK (0x10000U) #define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN_SHIFT (16U) #define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN_SHIFT)) & \ IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN_MASK) #define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS_MASK (0x20000U) #define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS_SHIFT (17U) #define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS_SHIFT)) & \ IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS_MASK) #define IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN_MASK (0x40000U) #define IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN_SHIFT (18U) #define IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN_SHIFT)) & \ IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN_MASK) #define IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN_MASK (0x80000U) #define IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN_SHIFT (19U) #define IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN_SHIFT)) & \ IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN_MASK) /*! @} */ /*! @name GPR11 - General Purpose Register 11 */ /*! @{ */ #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK (0x1U) #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT (0U) #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT)) & \ IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK) #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK (0xFEU) #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT (1U) #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT)) & \ IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK) #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK (0x400U) #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT (10U) #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT)) & \ IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK) #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK (0x3800U) #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT (11U) #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT)) & \ IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK) #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK (0x10000U) #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT (16U) #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT)) & \ IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK) #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK (0xFE0000U) #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT (17U) #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT)) & \ IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK) #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK (0x4000000U) #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT (26U) #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT)) & \ IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK) #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK (0x38000000U) #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT (27U) #define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT)) & \ IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK) /*! @} */ /*! @name GPR13 - General Purpose Register 13 */ /*! @{ */ #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK (0x1U) #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT (0U) #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT)) & \ IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK) #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK (0x2U) #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT (1U) #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT)) & \ IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK) /*! @} */ /*! @name GPR20 - General Purpose Register 20 */ /*! @{ */ #define IOMUXC_GPR_GPR20_SRAM_HSD_RAWLM_MASK (0x3U) #define IOMUXC_GPR_GPR20_SRAM_HSD_RAWLM_SHIFT (0U) /*! SRAM_HSD_RAWLM * 0b00..when supermix operates on 0.8V (default) * 0b00..when supermix operates on 0.9V */ #define IOMUXC_GPR_GPR20_SRAM_HSD_RAWLM(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_SRAM_HSD_RAWLM_SHIFT)) & IOMUXC_GPR_GPR20_SRAM_HSD_RAWLM_MASK) #define IOMUXC_GPR_GPR20_SRAM_HSD_RAWL_MASK (0x4U) #define IOMUXC_GPR_GPR20_SRAM_HSD_RAWL_SHIFT (2U) /*! SRAM_HSD_RAWL * 0b1..when supermix operates on 0.8V (default) * 0b0..when supermix operates on 0.9V */ #define IOMUXC_GPR_GPR20_SRAM_HSD_RAWL(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_SRAM_HSD_RAWL_SHIFT)) & IOMUXC_GPR_GPR20_SRAM_HSD_RAWL_MASK) #define IOMUXC_GPR_GPR20_SRAM_HSD_WABLM_MASK (0x18U) #define IOMUXC_GPR_GPR20_SRAM_HSD_WABLM_SHIFT (3U) /*! SRAM_HSD_WABLM * 0b01..when supermix operates on 0.8V (default) * 0b00..when supermix operates on 0.9V */ #define IOMUXC_GPR_GPR20_SRAM_HSD_WABLM(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_SRAM_HSD_WABLM_SHIFT)) & IOMUXC_GPR_GPR20_SRAM_HSD_WABLM_MASK) #define IOMUXC_GPR_GPR20_SRAM_HSD_WABL_MASK (0x20U) #define IOMUXC_GPR_GPR20_SRAM_HSD_WABL_SHIFT (5U) /*! SRAM_HSD_WABL * 0b1..when supermix operates on 0.8V (default) * 0b1..when supermix operates on 0.9V */ #define IOMUXC_GPR_GPR20_SRAM_HSD_WABL(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_SRAM_HSD_WABL_SHIFT)) & IOMUXC_GPR_GPR20_SRAM_HSD_WABL_MASK) /*! @} */ /*! @name GPR21 - General Purpose Register 21 */ /*! @{ */ #define IOMUXC_GPR_GPR21_CM7_INIT_VTOR_MASK (0xFFFFFF80U) #define IOMUXC_GPR_GPR21_CM7_INIT_VTOR_SHIFT (7U) #define IOMUXC_GPR_GPR21_CM7_INIT_VTOR(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR21_CM7_INIT_VTOR_MASK) /*! @} */ /*! @name GPR22 - General Purpose Register 22 */ /*! @{ */ #define IOMUXC_GPR_GPR22_CM7_CPUWAIT_MASK (0x1U) #define IOMUXC_GPR_GPR22_CM7_CPUWAIT_SHIFT (0U) #define IOMUXC_GPR_GPR22_CM7_CPUWAIT(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_CM7_CPUWAIT_SHIFT)) & IOMUXC_GPR_GPR22_CM7_CPUWAIT_MASK) #define IOMUXC_GPR_GPR22_CM7_HCLK_AUTO_GATE_EN_MASK (0x4U) #define IOMUXC_GPR_GPR22_CM7_HCLK_AUTO_GATE_EN_SHIFT (2U) /*! CM7_HCLK_AUTO_GATE_EN * 0b0..Disable. * 0b1..Enable. */ #define IOMUXC_GPR_GPR22_CM7_HCLK_AUTO_GATE_EN(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_CM7_HCLK_AUTO_GATE_EN_SHIFT)) & \ IOMUXC_GPR_GPR22_CM7_HCLK_AUTO_GATE_EN_MASK) #define IOMUXC_GPR_GPR22_CM7_HCLK_GATE_EN_MASK (0x8U) #define IOMUXC_GPR_GPR22_CM7_HCLK_GATE_EN_SHIFT (3U) /*! CM7_HCLK_GATE_EN * 0b0..Not Gated. * 0b1..Gated. */ #define IOMUXC_GPR_GPR22_CM7_HCLK_GATE_EN(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_CM7_HCLK_GATE_EN_SHIFT)) & IOMUXC_GPR_GPR22_CM7_HCLK_GATE_EN_MASK) #define IOMUXC_GPR_GPR22_CPU_STANDBYWFI_MASK (0xF0000U) #define IOMUXC_GPR_GPR22_CPU_STANDBYWFI_SHIFT (16U) #define IOMUXC_GPR_GPR22_CPU_STANDBYWFI(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_CPU_STANDBYWFI_SHIFT)) & IOMUXC_GPR_GPR22_CPU_STANDBYWFI_MASK) #define IOMUXC_GPR_GPR22_CPU_STANDBYWFE_MASK (0xF00000U) #define IOMUXC_GPR_GPR22_CPU_STANDBYWFE_SHIFT (20U) #define IOMUXC_GPR_GPR22_CPU_STANDBYWFE(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_CPU_STANDBYWFE_SHIFT)) & IOMUXC_GPR_GPR22_CPU_STANDBYWFE_MASK) #define IOMUXC_GPR_GPR22_CM7_AHBSRDY_MASK (0x40000000U) #define IOMUXC_GPR_GPR22_CM7_AHBSRDY_SHIFT (30U) /*! CM7_AHBSRDY * 0b0..AHBS is ready. * 0b1..AHBS is not ready. */ #define IOMUXC_GPR_GPR22_CM7_AHBSRDY(x) \ (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_CM7_AHBSRDY_SHIFT)) & IOMUXC_GPR_GPR22_CM7_AHBSRDY_MASK) /*! @} */ /* The count of IOMUXC_GPR_GPR */ #define IOMUXC_GPR_GPR_COUNT (25U) /*! * @} */ /* end of group IOMUXC_GPR_Register_Masks */ /* IOMUXC_GPR - Peripheral instance base addresses */ /** Peripheral IOMUXC_GPR base address */ #define IOMUXC_GPR_BASE (0x30340000u) /** Peripheral IOMUXC_GPR base pointer */ #define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) /** Array initializer of IOMUXC_GPR peripheral base addresses */ #define IOMUXC_GPR_BASE_ADDRS \ { \ IOMUXC_GPR_BASE \ } /** Array initializer of IOMUXC_GPR peripheral base pointers */ #define IOMUXC_GPR_BASE_PTRS \ { \ IOMUXC_GPR \ } /*! * @} */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ISI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ISI_Peripheral_Access_Layer ISI Peripheral Access Layer * @{ */ /** ISI - Register Layout Typedef */ typedef struct { __IO uint32_t CHNL_CTRL; /**< Channel Control Register, offset: 0x0 */ __IO uint32_t CHNL_IMG_CTRL; /**< Channel Image Control Register, offset: 0x4 */ __IO uint32_t CHNL_OUT_BUF_CTRL; /**< Channel Output Buffer Control Register, offset: 0x8 */ __IO uint32_t CHNL_IMG_CFG; /**< Channel Image Configuration, offset: 0xC */ __IO uint32_t CHNL_IER; /**< Channel Interrupt Enable Register, offset: 0x10 */ __IO uint32_t CHNL_STS; /**< Channel Status Register, offset: 0x14 */ __IO uint32_t CHNL_SCALE_FACTOR; /**< Channel Scale Factor Register, offset: 0x18 */ __IO uint32_t CHNL_SCALE_OFFSET; /**< Channel Scale Offset Register, offset: 0x1C */ __IO uint32_t CHNL_CROP_ULC; /**< Channel Crop Upper Left Corner Coordinate Register, offset: 0x20 */ __IO uint32_t CHNL_CROP_LRC; /**< Channel Crop Lower Right Corner Coordinate Register, offset: 0x24 */ __IO uint32_t CHNL_CSC_COEFF0; /**< Channel Color Space Conversion Coefficient Register 0, offset: 0x28 */ __IO uint32_t CHNL_CSC_COEFF1; /**< Channel Color Space Conversion Coefficient Register 1, offset: 0x2C */ __IO uint32_t CHNL_CSC_COEFF2; /**< Channel Color Space Conversion Coefficient Register 2, offset: 0x30 */ __IO uint32_t CHNL_CSC_COEFF3; /**< Channel Color Space Conversion Coefficient Register 3, offset: 0x34 */ __IO uint32_t CHNL_CSC_COEFF4; /**< Channel Color Space Conversion Coefficient Register 4, offset: 0x38 */ __IO uint32_t CHNL_CSC_COEFF5; /**< Channel Color Space Conversion Coefficient Register 5, offset: 0x3C */ __IO uint32_t CHNL_ROI_0_ALPHA; /**< Channel Alpha Value Register for Region of Interest 0, offset: 0x40 */ __IO uint32_t CHNL_ROI_0_ULC; /**< Channel Upper Left Coordinate Register for Region of Interest 0, offset: 0x44 */ __IO uint32_t CHNL_ROI_0_LRC; /**< Channel Lower Right Coordinate Register for Region of Interest 0, offset: 0x48 */ __IO uint32_t CHNL_ROI_1_ALPHA; /**< Channel Alpha Value Register for Region of Interest 1, offset: 0x4C */ __IO uint32_t CHNL_ROI_1_ULC; /**< Channel Upper Left Coordinate Register for Region of Interest 1, offset: 0x50 */ __IO uint32_t CHNL_ROI_1_LRC; /**< Channel Lower Right Coordinate Register for Region of Interest 1, offset: 0x54 */ __IO uint32_t CHNL_ROI_2_ALPHA; /**< Channel Alpha Value Register for Region of Interest 2, offset: 0x58 */ __IO uint32_t CHNL_ROI_2_ULC; /**< Channel Upper Left Coordinate Register for Region of Interest 2, offset: 0x5C */ __IO uint32_t CHNL_ROI_2_LRC; /**< Channel Lower Right Coordinate Register for Region of Interest 2, offset: 0x60 */ __IO uint32_t CHNL_ROI_3_ALPHA; /**< Channel Alpha Value Register for Region of Interest 3, offset: 0x64 */ __IO uint32_t CHNL_ROI_3_ULC; /**< Channel Upper Left Coordinate Register for Region of Interest 3, offset: 0x68 */ __IO uint32_t CHNL_ROI_3_LRC; /**< Channel Lower Right Coordinate Register for Region of Interest 3, offset: 0x6C */ __IO uint32_t CHNL_OUT_BUF1_ADDR_Y; /**< Channel RGB or Luma (Y) Output Buffer 1 Address, offset: 0x70 */ __IO uint32_t CHNL_OUT_BUF1_ADDR_U; /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address, offset: 0x74 */ __IO uint32_t CHNL_OUT_BUF1_ADDR_V; /**< Channel Chroma (V/Cr) Output Buffer 1 Address, offset: 0x78 */ __IO uint32_t CHNL_OUT_BUF_PITCH; /**< Channel Output Buffer Pitch, offset: 0x7C */ __IO uint32_t CHNL_IN_BUF_ADDR; /**< Channel Input Buffer Address, offset: 0x80 */ __IO uint32_t CHNL_IN_BUF_PITCH; /**< Channel Input Buffer Pitch, offset: 0x84 */ __IO uint32_t CHNL_MEM_RD_CTRL; /**< Channel Memory Read Control, offset: 0x88 */ __IO uint32_t CHNL_OUT_BUF2_ADDR_Y; /**< Channel RGB or Luma (Y) Output Buffer 2 Address, offset: 0x8C */ __IO uint32_t CHNL_OUT_BUF2_ADDR_U; /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address, offset: 0x90 */ __IO uint32_t CHNL_OUT_BUF2_ADDR_V; /**< Channel Chroma (V/Cr) Output Buffer 2 Address, offset: 0x94 */ __IO uint32_t CHNL_SCL_IMG_CFG; /**< Channel Scaled Image Configuration, offset: 0x98 */ __IO uint32_t CHNL_FLOW_CTRL; /**< Channel Flow Control Register, offset: 0x9C */ } ISI_Type; /* ---------------------------------------------------------------------------- -- ISI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ISI_Register_Masks ISI Register Masks * @{ */ /*! @name CHNL_CTRL - Channel Control Register */ /*! @{ */ #define ISI_CHNL_CTRL_SRC_MASK (0x7U) #define ISI_CHNL_CTRL_SRC_SHIFT (0U) /*! SRC - Input image source port selection * 0b000..Image will be sourced from input port 0 of the Pixel Link Crossbar * 0b001..Image will be sourced from input port 1 of the Pixel Link Crossbar * 0b010..Image will be sourced from input port 2 of the Pixel Link Crossbar * 0b011..Image will be sourced from input port 3 of the Pixel Link Crossbar * 0b100..Image will be sourced from input port 4 of the Pixel Link Crossbar * 0b101..Image will be sourced from input port 5 of the Pixel Link Crossbar (Input port 5 connected to AXI read) * 0b110..Reserved * 0b111..Reserved */ #define ISI_CHNL_CTRL_SRC(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_SHIFT)) & ISI_CHNL_CTRL_SRC_MASK) #define ISI_CHNL_CTRL_SRC_TYPE_MASK (0x10U) #define ISI_CHNL_CTRL_SRC_TYPE_SHIFT (4U) /*! SRC_TYPE - Type of selected input image source * 0b0..Image input source is Pixel Link * 0b1..Image input source is Memory */ #define ISI_CHNL_CTRL_SRC_TYPE(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_TYPE_SHIFT)) & ISI_CHNL_CTRL_SRC_TYPE_MASK) #define ISI_CHNL_CTRL_VC_ID_MASK (0xC0U) #define ISI_CHNL_CTRL_VC_ID_SHIFT (6U) /*! VC_ID - Virtual channel ID * 0b00..Virtual Channel 0 selected or no virtual channel used * 0b01..Virtual Channel 1 selected * 0b10..Virtual Channel 2 selected * 0b11..Virtual Channel 3 selected */ #define ISI_CHNL_CTRL_VC_ID(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_VC_ID_SHIFT)) & ISI_CHNL_CTRL_VC_ID_MASK) #define ISI_CHNL_CTRL_SEC_LB_SRC_MASK (0x700U) #define ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT (8U) #define ISI_CHNL_CTRL_SEC_LB_SRC(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT)) & ISI_CHNL_CTRL_SEC_LB_SRC_MASK) #define ISI_CHNL_CTRL_SW_RST_MASK (0x1000000U) #define ISI_CHNL_CTRL_SW_RST_SHIFT (24U) /*! SW_RST - Software reset bit * 0b0..No Reset * 0b1..Channel pipeline is under software reset */ #define ISI_CHNL_CTRL_SW_RST(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SW_RST_SHIFT)) & ISI_CHNL_CTRL_SW_RST_MASK) #define ISI_CHNL_CTRL_CHAIN_BUF_MASK (0x6000000U) #define ISI_CHNL_CTRL_CHAIN_BUF_SHIFT (25U) /*! CHAIN_BUF - Chain line buffer control * 0b00..No line buffers chained (supports 2048 or less horizontal resolution) * 0b01..2 line buffers chained (supports 4096 horizontal resolution). Line buffers of channels 'n' and 'n+1' are * chained. 0b10..4 line buffers chained (supports 8192 horizontal resolution). Line buffers of channels 'n', 'n+1', * 'n+2' and 'n+3' are chained. 0b11..Reserved for future use */ #define ISI_CHNL_CTRL_CHAIN_BUF(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHAIN_BUF_SHIFT)) & ISI_CHNL_CTRL_CHAIN_BUF_MASK) #define ISI_CHNL_CTRL_CHNL_BYPASS_MASK (0x20000000U) #define ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT (29U) /*! CHNL_BYPASS - Channel bypass enable * 0b0..Channel is not bypassed * 0b1..Channel is bypassed */ #define ISI_CHNL_CTRL_CHNL_BYPASS(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT)) & ISI_CHNL_CTRL_CHNL_BYPASS_MASK) #define ISI_CHNL_CTRL_CLK_EN_MASK (0x40000000U) #define ISI_CHNL_CTRL_CLK_EN_SHIFT (30U) /*! CLK_EN - Channel clock enable * 0b0..Channel processing clock is disabled * 0b1..Channel processing clock is enabled */ #define ISI_CHNL_CTRL_CLK_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CLK_EN_SHIFT)) & ISI_CHNL_CTRL_CLK_EN_MASK) #define ISI_CHNL_CTRL_CHNL_EN_MASK (0x80000000U) #define ISI_CHNL_CTRL_CHNL_EN_SHIFT (31U) /*! CHNL_EN - Enable channel processing * 0b0..Processing channel is disabled * 0b1..Processing channel is enabled */ #define ISI_CHNL_CTRL_CHNL_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_EN_SHIFT)) & ISI_CHNL_CTRL_CHNL_EN_MASK) /*! @} */ /*! @name CHNL_IMG_CTRL - Channel Image Control Register */ /*! @{ */ #define ISI_CHNL_IMG_CTRL_CSC_BYP_MASK (0x1U) #define ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT (0U) /*! CSC_BYP - Color Space Conversion bypass control * 0b0..CSC is operational * 0b1..CSC is bypassed */ #define ISI_CHNL_IMG_CTRL_CSC_BYP(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_BYP_MASK) #define ISI_CHNL_IMG_CTRL_CSC_MODE_MASK (0x6U) #define ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT (1U) /*! CSC_MODE - Color Space Conversion operating mode * 0b00..Convert from YUV to RGB * 0b01..Convert from YCbCr to RGB * 0b10..Convert from RGB to YUV * 0b11..Convert from RGB to YCbCr */ #define ISI_CHNL_IMG_CTRL_CSC_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_MODE_MASK) #define ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK (0x8U) #define ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT (3U) /*! YCBCR_MODE - YCbCr Mode * 0b0..YCbCr mode is disabled * 0b1..YCbCr mode is enabled */ #define ISI_CHNL_IMG_CTRL_YCBCR_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK) #define ISI_CHNL_IMG_CTRL_RSVD2_MASK (0x10U) #define ISI_CHNL_IMG_CTRL_RSVD2_SHIFT (4U) #define ISI_CHNL_IMG_CTRL_RSVD2(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_RSVD2_SHIFT)) & ISI_CHNL_IMG_CTRL_RSVD2_MASK) #define ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK (0x20U) #define ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT (5U) /*! HFLIP_EN - Horizontal flip control * 0b0..Horizantal image flip disabled * 0b1..Horizontal image flip enabled */ #define ISI_CHNL_IMG_CTRL_HFLIP_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK) #define ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK (0x40U) #define ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT (6U) /*! VFLIP_EN - Veritical flip control * 0b0..Vertical image flip disabled * 0b1..Vertical image flip enabled */ #define ISI_CHNL_IMG_CTRL_VFLIP_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK) #define ISI_CHNL_IMG_CTRL_CROP_EN_MASK (0x80U) #define ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT (7U) /*! CROP_EN - Output image cropping enable * 0b0..Image cropping is disabled * 0b1..Image cropping is enabled */ #define ISI_CHNL_IMG_CTRL_CROP_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_CROP_EN_MASK) #define ISI_CHNL_IMG_CTRL_DEC_Y_MASK (0x300U) #define ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT (8U) /*! DEC_Y - Vertical pre-decimation control * 0b00..Pre-decimation filter is disabled. Bilinear scaling filter is still operational. * 0b01..Decimate by 2 * 0b10..Decimate by 4 * 0b11..Decimate by 8 */ #define ISI_CHNL_IMG_CTRL_DEC_Y(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_Y_MASK) #define ISI_CHNL_IMG_CTRL_DEC_X_MASK (0xC00U) #define ISI_CHNL_IMG_CTRL_DEC_X_SHIFT (10U) /*! DEC_X - Horizontal pre-decimation control * 0b00..Pre-decimation filter is disabled. Bilinear scaling filter is still operational. * 0b01..Decimate by 2 * 0b10..Decimate by 4 * 0b11..Decimate by 8 */ #define ISI_CHNL_IMG_CTRL_DEC_X(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_X_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_X_MASK) #define ISI_CHNL_IMG_CTRL_DEINT_MASK (0x7000U) #define ISI_CHNL_IMG_CTRL_DEINT_SHIFT (12U) /*! DEINT - De-interlace control * 0b000, 0b001..No de-interlacing done * 0b010..Weave de-interlacing (Odd, Even) method used * 0b011..Weave de-interlacing (Even, Odd) method used * 0b100..Blending or linear interpolation (Odd + Even) de-interlacing method used * 0b101..Blending or linear interpolation (Even + Odd) de-interlacing method used * 0b110, 0b111..Line doubling de-interlacing method used. Both Odd and Even fields are doubled. */ #define ISI_CHNL_IMG_CTRL_DEINT(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEINT_SHIFT)) & ISI_CHNL_IMG_CTRL_DEINT_MASK) #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK (0x8000U) #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT (15U) /*! GBL_ALPHA_EN - Global alpha value insertion enable * 0b0..Global Alpha value insertion is disabled * 0b1..Global Alpha value insertion is enabled */ #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK) #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK (0xFF0000U) #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT (16U) /*! GBL_ALPHA_VAL - Global alpha value * 0b00000000-0b11111111..Alpha value to be inserted with all RGB pixels */ #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK) #define ISI_CHNL_IMG_CTRL_FORMAT_MASK (0x3F000000U) #define ISI_CHNL_IMG_CTRL_FORMAT_SHIFT (24U) /*! FORMAT - Output image format * 0b000000..RGBA8888 - RGB format with alpha in LSB; 8-bits per component. 'A' indicates alpha value. * 0b000001..ABGR8888 - BGR format with alpha in MSB; 8-bits per component. 'A' indicates alpha value. * 0b000010..ARGB8888 - RGB format with alpha in MSB; 8-bits per component. 'A' indicates alpha value. * 0b000011..RGBX888 - RGB format with 8-bits per color component (unpacked and MSB-alinged in 32-bit DWORD). 'X' * indicates the waste bits. 0b000100..XBGR888 - BGR format with 8-bits per color component (unpacked and LSB aligned in * 32-bit DWORD). 'X' indicates the waste bits. 0b000101..XRGB888 - RGB format with 8-bits per color component (unpacked * and LSB aligned in 32-bit DWORD). 'X' indicates the waste bits. 0b000110..RGB888P - RGB format with 8-bits per color * component (packed into 24-bits). No waste bits. 0b000111..BGR888P - BGR format with 8-bits per color component * (packed into 24-bits). No waste bits. 0b001000..A2BGR10 - BGR format with 2-bits alpha in MSB; 10-bits per color * component. 'A' indicates alpha value. 0b001001..A2RGB10 - RGB format with 2-bits alpha in MSB; 10-bits per color * component. 'A' indicates alpha value. 0b001010..RGB565 - RGB format with 5-bits of R, B; 6-bits of G (packed into * 16-bits WORD). No waste bits. 0b001011..RAW8 - 8-bit RAW data packed into 32-bit DWORD 0b001100..RAW10 - 10-bit RAW * data packed into 16-bit WORD with 6 LSBs waste bits 0b001101..RAW10P - 10-bit RAW data packed into 32-bit DWORD * 0b001110..RAW12 - 12-bit RAW data packed into 16-bit DWORD with 4 LSBs waste bits * 0b001111..RAW16 - 16-bit RAW data packed into 32-bit DWORD * 0b010000..YUV444_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes * 0b010001..YUV444_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes * 0b010010..YUV444_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes * 0b010011..YUV444_1P8 with 8-bits per color component; 1-plane YUV interleaved unpacked bytes (8 MSBs waste bits in * 32-bit DWORD) 0b010100..YUV444_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs * waste bits in 16-bit WORD) 0b010101..YUV444_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked * bytes (6 LSBs waste bits in 16-bit WORD) 0b010110..YUV444_3P10 with 10-bits per color component; 3-plane, * non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD) 0b010111..Reserved for future use * 0b011000..YUV444_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in * 32-bit DWORD) 0b011001..YUV444_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs * waste bits in 32-bit DWORD) 0b011010..YUV444_3P10P with 10-bits per color component; 3-plane, non-interleaved packed * bytes (2 MSBs waste bits in 32-bit DWORD) 0b011011..Reserved for future use 0b011100..YUV444_1P12 with 12-bits per * color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) 0b011101..YUV444_2P12 * with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) * 0b011110..YUV444_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits * in 16-bit WORD) 0b011111..Reserved for future use 0b100000..YUV422_1P8P with 8-bits per color component; 1-plane, YUV * interleaved packed bytes 0b100001..YUV422_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes * 0b100010..YUV422_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes * 0b100011..Reserved for future use * 0b100100..YUV422_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits * in 16-bit WORD) 0b100101..YUV422_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 * LSBs waste bits in 16-bit WORD) 0b100110..YUV422_3P10 with 10-bits per color component; 3-plane, non-interleaved * unpacked bytes (6 LSBs waste bits in 16-bit WORD) 0b100111..Reserved for future use 0b101000..YUV422_1P10P with * 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD) * 0b101001..YUV422_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in * 32-bit DWORD) 0b101010..YUV422_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs * waste bits in 32-bit DWORD) 0b101011..Reserved for future use 0b101100..YUV422_1P12 with 12-bits per color component; * 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) 0b101101..YUV422_2P12 with 12-bits per * color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) 0b101110..YUV422_3P12 with * 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) * 0b101111..Reserved for future use * 0b110000..Reserved for future use * 0b110001..YUV420_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes * 0b110010..YUV420_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes * 0b110011..Reserved for future use * 0b110100..Reserved for future use * 0b110101..YUV420_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in * 16-bit WORD) 0b110110..YUV420_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs * waste bits in 16-bit WORD) 0b110111..Reserved for future use 0b111000..Reserved for future use 0b111001..YUV420_2P10P * with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD) * 0b111010..YUV420_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in * 32-bit DWORD) 0b111011..Reserved for future use 0b111100..Reserved for future use 0b111101..YUV420_2P12 with 12-bits * per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) 0b111110..YUV420_3P12 * with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) * 0b111111..Reserved for future use */ #define ISI_CHNL_IMG_CTRL_FORMAT(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_FORMAT_SHIFT)) & ISI_CHNL_IMG_CTRL_FORMAT_MASK) #define ISI_CHNL_IMG_CTRL_RSVD0_MASK (0xC0000000U) #define ISI_CHNL_IMG_CTRL_RSVD0_SHIFT (30U) #define ISI_CHNL_IMG_CTRL_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_RSVD0_SHIFT)) & ISI_CHNL_IMG_CTRL_RSVD0_MASK) /*! @} */ /*! @name CHNL_OUT_BUF_CTRL - Channel Output Buffer Control Register */ /*! @{ */ #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_MASK (0xFU) #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_SHIFT (0U) /*! PANIC_SET_THD_Y - Overflow panic set threshold value for Y/RGB output buffer * 0b0000..No panic alert will be asserted * 0b0001-0b1111..Panic will assert when buffer is n * 6.25% full, where n = 1 to 15 */ #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_SHIFT)) & \ ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_MASK) #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_MASK (0xF00U) #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_SHIFT (8U) /*! PANIC_SET_THD_U - Overflow panic set threshold value for U output buffer * 0b0000..No panic alert will be asserted * 0b0001-0b1111..Panic will assert when buffer is n * 6.25% full, where n = 1 to 15 */ #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_SHIFT)) & \ ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_MASK) #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK (0x4000U) #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT (14U) #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT)) & \ ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK) #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK (0x8000U) #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT (15U) #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT)) & \ ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK) #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_MASK (0xF0000U) #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_SHIFT (16U) /*! PANIC_SET_THD_V - Overflow panic set threshold value for V output buffer * 0b0000..No panic alert will be asserted * 0b0001-0b1111..Panic will assert when buffer is n * 6.25% full, where n = 1 to 15 */ #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_SHIFT)) & \ ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_MASK) #define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_MASK (0x40000000U) #define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_SHIFT (30U) /*! MAX_WR_BEATS_UV - Maximum AXI write beats for U and V-buffers * 0b0..Maximum write beats per write request are 8 (i.e. 128 bytes) * 0b1..Maximum write beats per write request are 16 (i.e. 256 bytes) */ #define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_SHIFT)) & \ ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_MASK) #define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_MASK (0x80000000U) #define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_SHIFT (31U) /*! MAX_WR_BEATS_Y - Maximum AXI write beats for Y-buffer * 0b0..Maximum write beats per write request are 8 (i.e. 128 bytes) * 0b1..Maximum write beats per write request are 16 (i.e. 256 bytes) */ #define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_SHIFT)) & \ ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_MASK) /*! @} */ /*! @name CHNL_IMG_CFG - Channel Image Configuration */ /*! @{ */ #define ISI_CHNL_IMG_CFG_WIDTH_MASK (0x1FFFU) #define ISI_CHNL_IMG_CFG_WIDTH_SHIFT (0U) #define ISI_CHNL_IMG_CFG_WIDTH(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_IMG_CFG_WIDTH_MASK) #define ISI_CHNL_IMG_CFG_RSVD0_MASK (0xE000U) #define ISI_CHNL_IMG_CFG_RSVD0_SHIFT (13U) #define ISI_CHNL_IMG_CFG_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_RSVD0_SHIFT)) & ISI_CHNL_IMG_CFG_RSVD0_MASK) #define ISI_CHNL_IMG_CFG_HEIGHT_MASK (0x1FFF0000U) #define ISI_CHNL_IMG_CFG_HEIGHT_SHIFT (16U) #define ISI_CHNL_IMG_CFG_HEIGHT(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_IMG_CFG_HEIGHT_MASK) #define ISI_CHNL_IMG_CFG_RSVD1_MASK (0xE0000000U) #define ISI_CHNL_IMG_CFG_RSVD1_SHIFT (29U) #define ISI_CHNL_IMG_CFG_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_RSVD1_SHIFT)) & ISI_CHNL_IMG_CFG_RSVD1_MASK) /*! @} */ /*! @name CHNL_IER - Channel Interrupt Enable Register */ /*! @{ */ #define ISI_CHNL_IER_RSVD0_MASK (0xFFFFU) #define ISI_CHNL_IER_RSVD0_SHIFT (0U) #define ISI_CHNL_IER_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_RSVD0_SHIFT)) & ISI_CHNL_IER_RSVD0_MASK) #define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK (0x10000U) #define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT (16U) /*! LATE_VSYNC_ERR_EN - VSYNC timing (Late) error interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_LATE_VSYNC_ERR_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK) #define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK (0x20000U) #define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT (17U) /*! EARLY_VSYNC_ERR_EN - VSYNC timing (Early) error interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK) #define ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK (0x80000U) #define ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT (19U) /*! OFLW_Y_BUF_EN - Y output buffer overflow interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_OFLW_Y_BUF_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK) #define ISI_CHNL_IER_PANIC_Y_BUF_EN_MASK (0x100000U) #define ISI_CHNL_IER_PANIC_Y_BUF_EN_SHIFT (20U) /*! PANIC_Y_BUF_EN - Y output buffer potential overflow panic interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_PANIC_Y_BUF_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_Y_BUF_EN_MASK) #define ISI_CHNL_IER_OFLW_U_BUF_EN_MASK (0x200000U) #define ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT (21U) /*! OFLW_U_BUF_EN - U output buffer overflow interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_OFLW_U_BUF_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_U_BUF_EN_MASK) #define ISI_CHNL_IER_PANIC_U_BUF_EN_MASK (0x400000U) #define ISI_CHNL_IER_PANIC_U_BUF_EN_SHIFT (22U) /*! PANIC_U_BUF_EN - U output buffer potential overflow panic interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_PANIC_U_BUF_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_U_BUF_EN_MASK) #define ISI_CHNL_IER_OFLW_V_BUF_EN_MASK (0x800000U) #define ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT (23U) /*! OFLW_V_BUF_EN - V output buffer overflow interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_OFLW_V_BUF_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_V_BUF_EN_MASK) #define ISI_CHNL_IER_PANIC_V_BUF_EN_MASK (0x1000000U) #define ISI_CHNL_IER_PANIC_V_BUF_EN_SHIFT (24U) /*! PANIC_V_BUF_EN - V output buffer potential overflow panic interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_PANIC_V_BUF_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_V_BUF_EN_MASK) #define ISI_CHNL_IER_AXI_RD_ERR_EN_MASK (0x2000000U) #define ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT (25U) /*! AXI_RD_ERR_EN - AXI bus read error interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_AXI_RD_ERR_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT)) & ISI_CHNL_IER_AXI_RD_ERR_EN_MASK) #define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK (0x4000000U) #define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT (26U) /*! AXI_WR_ERR_Y_EN - AXI bus read error interrupt enable bit for Y/RGB data buffer * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_AXI_WR_ERR_Y_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK) #define ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK (0x8000000U) #define ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT (27U) /*! AXI_WR_ERR_U_EN - AXI bus read error interrupt enable bit for U data buffer * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_AXI_WR_ERR_U_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK) #define ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK (0x10000000U) #define ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT (28U) /*! AXI_WR_ERR_V_EN - AXI bus read error interrupt enable bit for V data buffer * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_AXI_WR_ERR_V_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK) #define ISI_CHNL_IER_FRM_RCVD_EN_MASK (0x20000000U) #define ISI_CHNL_IER_FRM_RCVD_EN_SHIFT (29U) /*! FRM_RCVD_EN - Frame received interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_FRM_RCVD_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_FRM_RCVD_EN_SHIFT)) & ISI_CHNL_IER_FRM_RCVD_EN_MASK) #define ISI_CHNL_IER_LINE_RCVD_EN_MASK (0x40000000U) #define ISI_CHNL_IER_LINE_RCVD_EN_SHIFT (30U) /*! LINE_RCVD_EN - Line received interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_LINE_RCVD_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LINE_RCVD_EN_SHIFT)) & ISI_CHNL_IER_LINE_RCVD_EN_MASK) #define ISI_CHNL_IER_MEM_RD_DONE_EN_MASK (0x80000000U) #define ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT (31U) /*! MEM_RD_DONE_EN - Memory read complete interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_MEM_RD_DONE_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT)) & ISI_CHNL_IER_MEM_RD_DONE_EN_MASK) /*! @} */ /*! @name CHNL_STS - Channel Status Register */ /*! @{ */ #define ISI_CHNL_STS_BUF1_ACTIVE_MASK (0x100U) #define ISI_CHNL_STS_BUF1_ACTIVE_SHIFT (8U) /*! BUF1_ACTIVE - Current frame being stored in Buffer 1 Address * 0b0..Buffer 1 Address inactive * 0b1..Buffer 1 Address in use */ #define ISI_CHNL_STS_BUF1_ACTIVE(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF1_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF1_ACTIVE_MASK) #define ISI_CHNL_STS_BUF2_ACTIVE_MASK (0x200U) #define ISI_CHNL_STS_BUF2_ACTIVE_SHIFT (9U) /*! BUF2_ACTIVE - Current frame being stored in Buffer 2 Address * 0b0..Buffer 2 Address inactive * 0b1..Buffer 2 Address in use */ #define ISI_CHNL_STS_BUF2_ACTIVE(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF2_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF2_ACTIVE_MASK) #define ISI_CHNL_STS_MEM_RD_OFLOW_MASK (0x400U) #define ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT (10U) /*! MEM_RD_OFLOW - Memory read FIFO overflow error status * 0b0..No overflow occurred during memory read * 0b1..FIFO overflow occurred during memory read */ #define ISI_CHNL_STS_MEM_RD_OFLOW(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT)) & ISI_CHNL_STS_MEM_RD_OFLOW_MASK) #define ISI_CHNL_STS_RSVD1_MASK (0xF800U) #define ISI_CHNL_STS_RSVD1_SHIFT (11U) #define ISI_CHNL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_RSVD1_SHIFT)) & ISI_CHNL_STS_RSVD1_MASK) #define ISI_CHNL_STS_LATE_VSYNC_ERR_MASK (0x10000U) #define ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT (16U) /*! LATE_VSYNC_ERR - VSYNC timing (Late) error interrupt flag * 0b0..No error * 0b1..VSYNC detected later than expected */ #define ISI_CHNL_STS_LATE_VSYNC_ERR(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_LATE_VSYNC_ERR_MASK) #define ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK (0x20000U) #define ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT (17U) /*! EARLY_VSYNC_ERR - VSYNC timing (Early) error interrupt flag * 0b0..No error * 0b1..VSYNC detected earlier than expected */ #define ISI_CHNL_STS_EARLY_VSYNC_ERR(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK) #define ISI_CHNL_STS_OFLW_Y_BUF_MASK (0x40000U) #define ISI_CHNL_STS_OFLW_Y_BUF_SHIFT (18U) /*! OFLW_Y_BUF - Overflow in Y/RGB output buffer interrupt flag * 0b0..No overflow * 0b1..Overflow has occured in the channel */ #define ISI_CHNL_STS_OFLW_Y_BUF(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_Y_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_Y_BUF_MASK) #define ISI_CHNL_STS_PANIC_Y_BUF_MASK (0x80000U) #define ISI_CHNL_STS_PANIC_Y_BUF_SHIFT (19U) /*! PANIC_Y_BUF - Y/RGB output buffer potential overflow panic alert interrupt flag * 0b0..Buffer has not crossed the panic threshold limit * 0b1..Panic threshold limit crossed. Software must take action. */ #define ISI_CHNL_STS_PANIC_Y_BUF(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_Y_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_Y_BUF_MASK) #define ISI_CHNL_STS_OFLW_U_BUF_MASK (0x100000U) #define ISI_CHNL_STS_OFLW_U_BUF_SHIFT (20U) /*! OFLW_U_BUF - Overflow in U output buffer interrupt flag * 0b0..No overflow * 0b1..Overflow has occured in the channel */ #define ISI_CHNL_STS_OFLW_U_BUF(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_U_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_U_BUF_MASK) #define ISI_CHNL_STS_PANIC_U_BUF_MASK (0x200000U) #define ISI_CHNL_STS_PANIC_U_BUF_SHIFT (21U) /*! PANIC_U_BUF - U output buffer potential overflow panic alert interrupt flag * 0b0..Buffer has not crossed the panic threshold limit * 0b1..Panic threshold limit crossed. Software must take action. */ #define ISI_CHNL_STS_PANIC_U_BUF(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_U_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_U_BUF_MASK) #define ISI_CHNL_STS_OFLW_V_BUF_MASK (0x400000U) #define ISI_CHNL_STS_OFLW_V_BUF_SHIFT (22U) /*! OFLW_V_BUF - Overflow in U output buffer interrupt flag * 0b0..No overflow * 0b1..Overflow has occured in the channel */ #define ISI_CHNL_STS_OFLW_V_BUF(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_V_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_V_BUF_MASK) #define ISI_CHNL_STS_PANIC_V_BUF_MASK (0x800000U) #define ISI_CHNL_STS_PANIC_V_BUF_SHIFT (23U) /*! PANIC_V_BUF - V output buffer potential overflow panic alert interrupt flag * 0b0..Buffer has not crossed the panic threshold limit * 0b1..Panic threshold limit crossed. Software must take action. */ #define ISI_CHNL_STS_PANIC_V_BUF(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_V_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_V_BUF_MASK) #define ISI_CHNL_STS_AXI_RD_ERR_MASK (0x2000000U) #define ISI_CHNL_STS_AXI_RD_ERR_SHIFT (25U) /*! AXI_RD_ERR - AXI Bus read error interrupt flag * 0b0..No error * 0b1..Error occured during read */ #define ISI_CHNL_STS_AXI_RD_ERR(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_RD_ERR_SHIFT)) & ISI_CHNL_STS_AXI_RD_ERR_MASK) #define ISI_CHNL_STS_AXI_WR_ERR_Y_MASK (0x4000000U) #define ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT (26U) /*! AXI_WR_ERR_Y - AXI Bus write error interrupt flag for Y/RGB data buffer * 0b0..No error * 0b1..Error occured during write */ #define ISI_CHNL_STS_AXI_WR_ERR_Y(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_Y_MASK) #define ISI_CHNL_STS_AXI_WR_ERR_U_MASK (0x8000000U) #define ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT (27U) /*! AXI_WR_ERR_U - AXI Bus write error interrupt flag for U data buffer * 0b0..No error * 0b1..Error occured during write */ #define ISI_CHNL_STS_AXI_WR_ERR_U(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_U_MASK) #define ISI_CHNL_STS_AXI_WR_ERR_V_MASK (0x10000000U) #define ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT (28U) /*! AXI_WR_ERR_V - AXI Bus write error interrupt flag for V data buffer * 0b0..No error * 0b1..Error occured during write */ #define ISI_CHNL_STS_AXI_WR_ERR_V(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_V_MASK) #define ISI_CHNL_STS_FRM_STRD_MASK (0x20000000U) #define ISI_CHNL_STS_FRM_STRD_SHIFT (29U) /*! FRM_STRD - Frame stored successfully interrupt flag * 0b0..No frame being received or in progress * 0b1..One full frame has been received and stored in memory */ #define ISI_CHNL_STS_FRM_STRD(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_FRM_STRD_SHIFT)) & ISI_CHNL_STS_FRM_STRD_MASK) #define ISI_CHNL_STS_LINE_STRD_MASK (0x40000000U) #define ISI_CHNL_STS_LINE_STRD_SHIFT (30U) /*! LINE_STRD - Line received and stored interrupt flag * 0b0..No new line received * 0b1..New line received and stored into memory */ #define ISI_CHNL_STS_LINE_STRD(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LINE_STRD_SHIFT)) & ISI_CHNL_STS_LINE_STRD_MASK) #define ISI_CHNL_STS_MEM_RD_DONE_MASK (0x80000000U) #define ISI_CHNL_STS_MEM_RD_DONE_SHIFT (31U) /*! MEM_RD_DONE - Memory read complete interrupt flag * 0b0..Image read from memory not complete or not started * 0b1..Image read from memory completed */ #define ISI_CHNL_STS_MEM_RD_DONE(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_DONE_SHIFT)) & ISI_CHNL_STS_MEM_RD_DONE_MASK) /*! @} */ /*! @name CHNL_SCALE_FACTOR - Channel Scale Factor Register */ /*! @{ */ #define ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK (0x3FFFU) #define ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT (0U) #define ISI_CHNL_SCALE_FACTOR_X_SCALE(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK) #define ISI_CHNL_SCALE_FACTOR_RSVD1_MASK (0xC000U) #define ISI_CHNL_SCALE_FACTOR_RSVD1_SHIFT (14U) #define ISI_CHNL_SCALE_FACTOR_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_RSVD1_SHIFT)) & ISI_CHNL_SCALE_FACTOR_RSVD1_MASK) #define ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK (0x3FFF0000U) #define ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT (16U) #define ISI_CHNL_SCALE_FACTOR_Y_SCALE(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK) #define ISI_CHNL_SCALE_FACTOR_RSVD0_MASK (0xC0000000U) #define ISI_CHNL_SCALE_FACTOR_RSVD0_SHIFT (30U) #define ISI_CHNL_SCALE_FACTOR_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_RSVD0_SHIFT)) & ISI_CHNL_SCALE_FACTOR_RSVD0_MASK) /*! @} */ /*! @name CHNL_SCALE_OFFSET - Channel Scale Offset Register */ /*! @{ */ #define ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK (0xFFFU) #define ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT (0U) #define ISI_CHNL_SCALE_OFFSET_X_OFFSET(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK) #define ISI_CHNL_SCALE_OFFSET_RSVD1_MASK (0xF000U) #define ISI_CHNL_SCALE_OFFSET_RSVD1_SHIFT (12U) #define ISI_CHNL_SCALE_OFFSET_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_RSVD1_SHIFT)) & ISI_CHNL_SCALE_OFFSET_RSVD1_MASK) #define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK (0xFFF0000U) #define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT (16U) #define ISI_CHNL_SCALE_OFFSET_Y_OFFSET(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK) #define ISI_CHNL_SCALE_OFFSET_RSVD0_MASK (0xF0000000U) #define ISI_CHNL_SCALE_OFFSET_RSVD0_SHIFT (28U) #define ISI_CHNL_SCALE_OFFSET_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_RSVD0_SHIFT)) & ISI_CHNL_SCALE_OFFSET_RSVD0_MASK) /*! @} */ /*! @name CHNL_CROP_ULC - Channel Crop Upper Left Corner Coordinate Register */ /*! @{ */ #define ISI_CHNL_CROP_ULC_Y_MASK (0xFFFU) #define ISI_CHNL_CROP_ULC_Y_SHIFT (0U) #define ISI_CHNL_CROP_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_Y_SHIFT)) & ISI_CHNL_CROP_ULC_Y_MASK) #define ISI_CHNL_CROP_ULC_RSVD1_MASK (0xF000U) #define ISI_CHNL_CROP_ULC_RSVD1_SHIFT (12U) #define ISI_CHNL_CROP_ULC_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_RSVD1_SHIFT)) & ISI_CHNL_CROP_ULC_RSVD1_MASK) #define ISI_CHNL_CROP_ULC_X_MASK (0xFFF0000U) #define ISI_CHNL_CROP_ULC_X_SHIFT (16U) #define ISI_CHNL_CROP_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_X_SHIFT)) & ISI_CHNL_CROP_ULC_X_MASK) #define ISI_CHNL_CROP_ULC_RSVD0_MASK (0xF0000000U) #define ISI_CHNL_CROP_ULC_RSVD0_SHIFT (28U) #define ISI_CHNL_CROP_ULC_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_RSVD0_SHIFT)) & ISI_CHNL_CROP_ULC_RSVD0_MASK) /*! @} */ /*! @name CHNL_CROP_LRC - Channel Crop Lower Right Corner Coordinate Register */ /*! @{ */ #define ISI_CHNL_CROP_LRC_Y_MASK (0xFFFU) #define ISI_CHNL_CROP_LRC_Y_SHIFT (0U) #define ISI_CHNL_CROP_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_Y_SHIFT)) & ISI_CHNL_CROP_LRC_Y_MASK) #define ISI_CHNL_CROP_LRC_RSVD1_MASK (0xF000U) #define ISI_CHNL_CROP_LRC_RSVD1_SHIFT (12U) #define ISI_CHNL_CROP_LRC_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_RSVD1_SHIFT)) & ISI_CHNL_CROP_LRC_RSVD1_MASK) #define ISI_CHNL_CROP_LRC_X_MASK (0xFFF0000U) #define ISI_CHNL_CROP_LRC_X_SHIFT (16U) #define ISI_CHNL_CROP_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_X_SHIFT)) & ISI_CHNL_CROP_LRC_X_MASK) #define ISI_CHNL_CROP_LRC_RSVD0_MASK (0xF0000000U) #define ISI_CHNL_CROP_LRC_RSVD0_SHIFT (28U) #define ISI_CHNL_CROP_LRC_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_RSVD0_SHIFT)) & ISI_CHNL_CROP_LRC_RSVD0_MASK) /*! @} */ /*! @name CHNL_CSC_COEFF0 - Channel Color Space Conversion Coefficient Register 0 */ /*! @{ */ #define ISI_CHNL_CSC_COEFF0_A1_MASK (0x7FFU) #define ISI_CHNL_CSC_COEFF0_A1_SHIFT (0U) #define ISI_CHNL_CSC_COEFF0_A1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A1_SHIFT)) & ISI_CHNL_CSC_COEFF0_A1_MASK) #define ISI_CHNL_CSC_COEFF0_RSVD1_MASK (0xF800U) #define ISI_CHNL_CSC_COEFF0_RSVD1_SHIFT (11U) #define ISI_CHNL_CSC_COEFF0_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF0_RSVD1_MASK) #define ISI_CHNL_CSC_COEFF0_A2_MASK (0x7FF0000U) #define ISI_CHNL_CSC_COEFF0_A2_SHIFT (16U) #define ISI_CHNL_CSC_COEFF0_A2(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A2_SHIFT)) & ISI_CHNL_CSC_COEFF0_A2_MASK) #define ISI_CHNL_CSC_COEFF0_RSVD0_MASK (0xF8000000U) #define ISI_CHNL_CSC_COEFF0_RSVD0_SHIFT (27U) #define ISI_CHNL_CSC_COEFF0_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF0_RSVD0_MASK) /*! @} */ /*! @name CHNL_CSC_COEFF1 - Channel Color Space Conversion Coefficient Register 1 */ /*! @{ */ #define ISI_CHNL_CSC_COEFF1_A3_MASK (0x7FFU) #define ISI_CHNL_CSC_COEFF1_A3_SHIFT (0U) #define ISI_CHNL_CSC_COEFF1_A3(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_A3_SHIFT)) & ISI_CHNL_CSC_COEFF1_A3_MASK) #define ISI_CHNL_CSC_COEFF1_RSVD1_MASK (0xF800U) #define ISI_CHNL_CSC_COEFF1_RSVD1_SHIFT (11U) #define ISI_CHNL_CSC_COEFF1_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF1_RSVD1_MASK) #define ISI_CHNL_CSC_COEFF1_B1_MASK (0x7FF0000U) #define ISI_CHNL_CSC_COEFF1_B1_SHIFT (16U) #define ISI_CHNL_CSC_COEFF1_B1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_B1_SHIFT)) & ISI_CHNL_CSC_COEFF1_B1_MASK) #define ISI_CHNL_CSC_COEFF1_RSVD0_MASK (0xF8000000U) #define ISI_CHNL_CSC_COEFF1_RSVD0_SHIFT (27U) #define ISI_CHNL_CSC_COEFF1_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF1_RSVD0_MASK) /*! @} */ /*! @name CHNL_CSC_COEFF2 - Channel Color Space Conversion Coefficient Register 2 */ /*! @{ */ #define ISI_CHNL_CSC_COEFF2_B2_MASK (0x7FFU) #define ISI_CHNL_CSC_COEFF2_B2_SHIFT (0U) #define ISI_CHNL_CSC_COEFF2_B2(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B2_SHIFT)) & ISI_CHNL_CSC_COEFF2_B2_MASK) #define ISI_CHNL_CSC_COEFF2_RSVD1_MASK (0xF800U) #define ISI_CHNL_CSC_COEFF2_RSVD1_SHIFT (11U) #define ISI_CHNL_CSC_COEFF2_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF2_RSVD1_MASK) #define ISI_CHNL_CSC_COEFF2_B3_MASK (0x7FF0000U) #define ISI_CHNL_CSC_COEFF2_B3_SHIFT (16U) #define ISI_CHNL_CSC_COEFF2_B3(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B3_SHIFT)) & ISI_CHNL_CSC_COEFF2_B3_MASK) #define ISI_CHNL_CSC_COEFF2_RSVD0_MASK (0xF8000000U) #define ISI_CHNL_CSC_COEFF2_RSVD0_SHIFT (27U) #define ISI_CHNL_CSC_COEFF2_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF2_RSVD0_MASK) /*! @} */ /*! @name CHNL_CSC_COEFF3 - Channel Color Space Conversion Coefficient Register 3 */ /*! @{ */ #define ISI_CHNL_CSC_COEFF3_C1_MASK (0x7FFU) #define ISI_CHNL_CSC_COEFF3_C1_SHIFT (0U) #define ISI_CHNL_CSC_COEFF3_C1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C1_SHIFT)) & ISI_CHNL_CSC_COEFF3_C1_MASK) #define ISI_CHNL_CSC_COEFF3_RSVD1_MASK (0xF800U) #define ISI_CHNL_CSC_COEFF3_RSVD1_SHIFT (11U) #define ISI_CHNL_CSC_COEFF3_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF3_RSVD1_MASK) #define ISI_CHNL_CSC_COEFF3_C2_MASK (0x7FF0000U) #define ISI_CHNL_CSC_COEFF3_C2_SHIFT (16U) #define ISI_CHNL_CSC_COEFF3_C2(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C2_SHIFT)) & ISI_CHNL_CSC_COEFF3_C2_MASK) #define ISI_CHNL_CSC_COEFF3_RSVD0_MASK (0xF8000000U) #define ISI_CHNL_CSC_COEFF3_RSVD0_SHIFT (27U) #define ISI_CHNL_CSC_COEFF3_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF3_RSVD0_MASK) /*! @} */ /*! @name CHNL_CSC_COEFF4 - Channel Color Space Conversion Coefficient Register 4 */ /*! @{ */ #define ISI_CHNL_CSC_COEFF4_C3_MASK (0x7FFU) #define ISI_CHNL_CSC_COEFF4_C3_SHIFT (0U) #define ISI_CHNL_CSC_COEFF4_C3(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_C3_SHIFT)) & ISI_CHNL_CSC_COEFF4_C3_MASK) #define ISI_CHNL_CSC_COEFF4_RSVD1_MASK (0xF800U) #define ISI_CHNL_CSC_COEFF4_RSVD1_SHIFT (11U) #define ISI_CHNL_CSC_COEFF4_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF4_RSVD1_MASK) #define ISI_CHNL_CSC_COEFF4_D1_MASK (0x1FF0000U) #define ISI_CHNL_CSC_COEFF4_D1_SHIFT (16U) #define ISI_CHNL_CSC_COEFF4_D1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_D1_SHIFT)) & ISI_CHNL_CSC_COEFF4_D1_MASK) #define ISI_CHNL_CSC_COEFF4_RSVD0_MASK (0xFE000000U) #define ISI_CHNL_CSC_COEFF4_RSVD0_SHIFT (25U) #define ISI_CHNL_CSC_COEFF4_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF4_RSVD0_MASK) /*! @} */ /*! @name CHNL_CSC_COEFF5 - Channel Color Space Conversion Coefficient Register 5 */ /*! @{ */ #define ISI_CHNL_CSC_COEFF5_D2_MASK (0x1FFU) #define ISI_CHNL_CSC_COEFF5_D2_SHIFT (0U) #define ISI_CHNL_CSC_COEFF5_D2(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D2_SHIFT)) & ISI_CHNL_CSC_COEFF5_D2_MASK) #define ISI_CHNL_CSC_COEFF5_RSVD1_MASK (0xFE00U) #define ISI_CHNL_CSC_COEFF5_RSVD1_SHIFT (9U) #define ISI_CHNL_CSC_COEFF5_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF5_RSVD1_MASK) #define ISI_CHNL_CSC_COEFF5_D3_MASK (0x1FF0000U) #define ISI_CHNL_CSC_COEFF5_D3_SHIFT (16U) #define ISI_CHNL_CSC_COEFF5_D3(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D3_SHIFT)) & ISI_CHNL_CSC_COEFF5_D3_MASK) #define ISI_CHNL_CSC_COEFF5_RSVD0_MASK (0xFE000000U) #define ISI_CHNL_CSC_COEFF5_RSVD0_SHIFT (25U) #define ISI_CHNL_CSC_COEFF5_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF5_RSVD0_MASK) /*! @} */ /*! @name CHNL_ROI_0_ALPHA - Channel Alpha Value Register for Region of Interest 0 */ /*! @{ */ #define ISI_CHNL_ROI_0_ALPHA_RSVD1_MASK (0xFFFFU) #define ISI_CHNL_ROI_0_ALPHA_RSVD1_SHIFT (0U) #define ISI_CHNL_ROI_0_ALPHA_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_RSVD1_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_RSVD1_MASK) #define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_MASK (0x10000U) #define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_SHIFT (16U) /*! ALPHA_EN - Alpha value insertion enable * 0b0..Alpha value insertion is disabled * 0b1..Alpha value insertion is enabled */ #define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_MASK) #define ISI_CHNL_ROI_0_ALPHA_RSVD0_MASK (0xFE0000U) #define ISI_CHNL_ROI_0_ALPHA_RSVD0_SHIFT (17U) #define ISI_CHNL_ROI_0_ALPHA_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_RSVD0_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_RSVD0_MASK) #define ISI_CHNL_ROI_0_ALPHA_ALPHA_MASK (0xFF000000U) #define ISI_CHNL_ROI_0_ALPHA_ALPHA_SHIFT (24U) #define ISI_CHNL_ROI_0_ALPHA_ALPHA(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_ALPHA_MASK) /*! @} */ /*! @name CHNL_ROI_0_ULC - Channel Upper Left Coordinate Register for Region of Interest 0 */ /*! @{ */ #define ISI_CHNL_ROI_0_ULC_Y_MASK (0xFFFU) #define ISI_CHNL_ROI_0_ULC_Y_SHIFT (0U) #define ISI_CHNL_ROI_0_ULC_Y(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_Y_SHIFT)) & ISI_CHNL_ROI_0_ULC_Y_MASK) #define ISI_CHNL_ROI_0_ULC_RSVD1_MASK (0xF000U) #define ISI_CHNL_ROI_0_ULC_RSVD1_SHIFT (12U) #define ISI_CHNL_ROI_0_ULC_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_RSVD1_SHIFT)) & ISI_CHNL_ROI_0_ULC_RSVD1_MASK) #define ISI_CHNL_ROI_0_ULC_X_MASK (0xFFF0000U) #define ISI_CHNL_ROI_0_ULC_X_SHIFT (16U) #define ISI_CHNL_ROI_0_ULC_X(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_X_SHIFT)) & ISI_CHNL_ROI_0_ULC_X_MASK) #define ISI_CHNL_ROI_0_ULC_RSVD0_MASK (0xF0000000U) #define ISI_CHNL_ROI_0_ULC_RSVD0_SHIFT (28U) #define ISI_CHNL_ROI_0_ULC_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_RSVD0_SHIFT)) & ISI_CHNL_ROI_0_ULC_RSVD0_MASK) /*! @} */ /*! @name CHNL_ROI_0_LRC - Channel Lower Right Coordinate Register for Region of Interest 0 */ /*! @{ */ #define ISI_CHNL_ROI_0_LRC_Y_MASK (0xFFFU) #define ISI_CHNL_ROI_0_LRC_Y_SHIFT (0U) #define ISI_CHNL_ROI_0_LRC_Y(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_Y_SHIFT)) & ISI_CHNL_ROI_0_LRC_Y_MASK) #define ISI_CHNL_ROI_0_LRC_RSVD1_MASK (0xF000U) #define ISI_CHNL_ROI_0_LRC_RSVD1_SHIFT (12U) #define ISI_CHNL_ROI_0_LRC_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_RSVD1_SHIFT)) & ISI_CHNL_ROI_0_LRC_RSVD1_MASK) #define ISI_CHNL_ROI_0_LRC_X_MASK (0xFFF0000U) #define ISI_CHNL_ROI_0_LRC_X_SHIFT (16U) #define ISI_CHNL_ROI_0_LRC_X(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_X_SHIFT)) & ISI_CHNL_ROI_0_LRC_X_MASK) #define ISI_CHNL_ROI_0_LRC_RSVD0_MASK (0xF0000000U) #define ISI_CHNL_ROI_0_LRC_RSVD0_SHIFT (28U) #define ISI_CHNL_ROI_0_LRC_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_RSVD0_SHIFT)) & ISI_CHNL_ROI_0_LRC_RSVD0_MASK) /*! @} */ /*! @name CHNL_ROI_1_ALPHA - Channel Alpha Value Register for Region of Interest 1 */ /*! @{ */ #define ISI_CHNL_ROI_1_ALPHA_RSVD1_MASK (0xFFFFU) #define ISI_CHNL_ROI_1_ALPHA_RSVD1_SHIFT (0U) #define ISI_CHNL_ROI_1_ALPHA_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_RSVD1_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_RSVD1_MASK) #define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_MASK (0x10000U) #define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_SHIFT (16U) /*! ALPHA_EN - Alpha value insertion enable * 0b0..Alpha value insertion is disabled * 0b1..Alpha value insertion is enabled */ #define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_MASK) #define ISI_CHNL_ROI_1_ALPHA_RSVD0_MASK (0xFE0000U) #define ISI_CHNL_ROI_1_ALPHA_RSVD0_SHIFT (17U) #define ISI_CHNL_ROI_1_ALPHA_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_RSVD0_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_RSVD0_MASK) #define ISI_CHNL_ROI_1_ALPHA_ALPHA_MASK (0xFF000000U) #define ISI_CHNL_ROI_1_ALPHA_ALPHA_SHIFT (24U) #define ISI_CHNL_ROI_1_ALPHA_ALPHA(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_ALPHA_MASK) /*! @} */ /*! @name CHNL_ROI_1_ULC - Channel Upper Left Coordinate Register for Region of Interest 1 */ /*! @{ */ #define ISI_CHNL_ROI_1_ULC_Y_MASK (0xFFFU) #define ISI_CHNL_ROI_1_ULC_Y_SHIFT (0U) #define ISI_CHNL_ROI_1_ULC_Y(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_Y_SHIFT)) & ISI_CHNL_ROI_1_ULC_Y_MASK) #define ISI_CHNL_ROI_1_ULC_RSVD1_MASK (0xF000U) #define ISI_CHNL_ROI_1_ULC_RSVD1_SHIFT (12U) #define ISI_CHNL_ROI_1_ULC_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_RSVD1_SHIFT)) & ISI_CHNL_ROI_1_ULC_RSVD1_MASK) #define ISI_CHNL_ROI_1_ULC_X_MASK (0xFFF0000U) #define ISI_CHNL_ROI_1_ULC_X_SHIFT (16U) #define ISI_CHNL_ROI_1_ULC_X(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_X_SHIFT)) & ISI_CHNL_ROI_1_ULC_X_MASK) #define ISI_CHNL_ROI_1_ULC_RSVD0_MASK (0xF0000000U) #define ISI_CHNL_ROI_1_ULC_RSVD0_SHIFT (28U) #define ISI_CHNL_ROI_1_ULC_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_RSVD0_SHIFT)) & ISI_CHNL_ROI_1_ULC_RSVD0_MASK) /*! @} */ /*! @name CHNL_ROI_1_LRC - Channel Lower Right Coordinate Register for Region of Interest 1 */ /*! @{ */ #define ISI_CHNL_ROI_1_LRC_Y_MASK (0xFFFU) #define ISI_CHNL_ROI_1_LRC_Y_SHIFT (0U) #define ISI_CHNL_ROI_1_LRC_Y(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_Y_SHIFT)) & ISI_CHNL_ROI_1_LRC_Y_MASK) #define ISI_CHNL_ROI_1_LRC_RSVD1_MASK (0xF000U) #define ISI_CHNL_ROI_1_LRC_RSVD1_SHIFT (12U) #define ISI_CHNL_ROI_1_LRC_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_RSVD1_SHIFT)) & ISI_CHNL_ROI_1_LRC_RSVD1_MASK) #define ISI_CHNL_ROI_1_LRC_X_MASK (0xFFF0000U) #define ISI_CHNL_ROI_1_LRC_X_SHIFT (16U) #define ISI_CHNL_ROI_1_LRC_X(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_X_SHIFT)) & ISI_CHNL_ROI_1_LRC_X_MASK) #define ISI_CHNL_ROI_1_LRC_RSVD0_MASK (0xF0000000U) #define ISI_CHNL_ROI_1_LRC_RSVD0_SHIFT (28U) #define ISI_CHNL_ROI_1_LRC_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_RSVD0_SHIFT)) & ISI_CHNL_ROI_1_LRC_RSVD0_MASK) /*! @} */ /*! @name CHNL_ROI_2_ALPHA - Channel Alpha Value Register for Region of Interest 2 */ /*! @{ */ #define ISI_CHNL_ROI_2_ALPHA_RSVD1_MASK (0xFFFFU) #define ISI_CHNL_ROI_2_ALPHA_RSVD1_SHIFT (0U) #define ISI_CHNL_ROI_2_ALPHA_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_RSVD1_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_RSVD1_MASK) #define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_MASK (0x10000U) #define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_SHIFT (16U) /*! ALPHA_EN - Alpha value insertion enable * 0b0..Alpha value insertion is disabled * 0b1..Alpha value insertion is enabled */ #define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_MASK) #define ISI_CHNL_ROI_2_ALPHA_RSVD0_MASK (0xFE0000U) #define ISI_CHNL_ROI_2_ALPHA_RSVD0_SHIFT (17U) #define ISI_CHNL_ROI_2_ALPHA_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_RSVD0_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_RSVD0_MASK) #define ISI_CHNL_ROI_2_ALPHA_ALPHA_MASK (0xFF000000U) #define ISI_CHNL_ROI_2_ALPHA_ALPHA_SHIFT (24U) #define ISI_CHNL_ROI_2_ALPHA_ALPHA(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_ALPHA_MASK) /*! @} */ /*! @name CHNL_ROI_2_ULC - Channel Upper Left Coordinate Register for Region of Interest 2 */ /*! @{ */ #define ISI_CHNL_ROI_2_ULC_Y_MASK (0xFFFU) #define ISI_CHNL_ROI_2_ULC_Y_SHIFT (0U) #define ISI_CHNL_ROI_2_ULC_Y(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_Y_SHIFT)) & ISI_CHNL_ROI_2_ULC_Y_MASK) #define ISI_CHNL_ROI_2_ULC_RSVD1_MASK (0xF000U) #define ISI_CHNL_ROI_2_ULC_RSVD1_SHIFT (12U) #define ISI_CHNL_ROI_2_ULC_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_RSVD1_SHIFT)) & ISI_CHNL_ROI_2_ULC_RSVD1_MASK) #define ISI_CHNL_ROI_2_ULC_X_MASK (0xFFF0000U) #define ISI_CHNL_ROI_2_ULC_X_SHIFT (16U) #define ISI_CHNL_ROI_2_ULC_X(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_X_SHIFT)) & ISI_CHNL_ROI_2_ULC_X_MASK) #define ISI_CHNL_ROI_2_ULC_RSVD0_MASK (0xF0000000U) #define ISI_CHNL_ROI_2_ULC_RSVD0_SHIFT (28U) #define ISI_CHNL_ROI_2_ULC_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_RSVD0_SHIFT)) & ISI_CHNL_ROI_2_ULC_RSVD0_MASK) /*! @} */ /*! @name CHNL_ROI_2_LRC - Channel Lower Right Coordinate Register for Region of Interest 2 */ /*! @{ */ #define ISI_CHNL_ROI_2_LRC_Y_MASK (0xFFFU) #define ISI_CHNL_ROI_2_LRC_Y_SHIFT (0U) #define ISI_CHNL_ROI_2_LRC_Y(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_Y_SHIFT)) & ISI_CHNL_ROI_2_LRC_Y_MASK) #define ISI_CHNL_ROI_2_LRC_RSVD1_MASK (0xF000U) #define ISI_CHNL_ROI_2_LRC_RSVD1_SHIFT (12U) #define ISI_CHNL_ROI_2_LRC_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_RSVD1_SHIFT)) & ISI_CHNL_ROI_2_LRC_RSVD1_MASK) #define ISI_CHNL_ROI_2_LRC_X_MASK (0xFFF0000U) #define ISI_CHNL_ROI_2_LRC_X_SHIFT (16U) #define ISI_CHNL_ROI_2_LRC_X(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_X_SHIFT)) & ISI_CHNL_ROI_2_LRC_X_MASK) #define ISI_CHNL_ROI_2_LRC_RSVD0_MASK (0xF0000000U) #define ISI_CHNL_ROI_2_LRC_RSVD0_SHIFT (28U) #define ISI_CHNL_ROI_2_LRC_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_RSVD0_SHIFT)) & ISI_CHNL_ROI_2_LRC_RSVD0_MASK) /*! @} */ /*! @name CHNL_ROI_3_ALPHA - Channel Alpha Value Register for Region of Interest 3 */ /*! @{ */ #define ISI_CHNL_ROI_3_ALPHA_RSVD1_MASK (0xFFFFU) #define ISI_CHNL_ROI_3_ALPHA_RSVD1_SHIFT (0U) #define ISI_CHNL_ROI_3_ALPHA_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_RSVD1_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_RSVD1_MASK) #define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_MASK (0x10000U) #define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_SHIFT (16U) /*! ALPHA_EN - Alpha value insertion enable * 0b0..Alpha value insertion is disabled * 0b1..Alpha value insertion is enabled */ #define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_MASK) #define ISI_CHNL_ROI_3_ALPHA_RSVD0_MASK (0xFE0000U) #define ISI_CHNL_ROI_3_ALPHA_RSVD0_SHIFT (17U) #define ISI_CHNL_ROI_3_ALPHA_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_RSVD0_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_RSVD0_MASK) #define ISI_CHNL_ROI_3_ALPHA_ALPHA_MASK (0xFF000000U) #define ISI_CHNL_ROI_3_ALPHA_ALPHA_SHIFT (24U) #define ISI_CHNL_ROI_3_ALPHA_ALPHA(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_ALPHA_MASK) /*! @} */ /*! @name CHNL_ROI_3_ULC - Channel Upper Left Coordinate Register for Region of Interest 3 */ /*! @{ */ #define ISI_CHNL_ROI_3_ULC_Y_MASK (0xFFFU) #define ISI_CHNL_ROI_3_ULC_Y_SHIFT (0U) #define ISI_CHNL_ROI_3_ULC_Y(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_Y_SHIFT)) & ISI_CHNL_ROI_3_ULC_Y_MASK) #define ISI_CHNL_ROI_3_ULC_RSVD1_MASK (0xF000U) #define ISI_CHNL_ROI_3_ULC_RSVD1_SHIFT (12U) #define ISI_CHNL_ROI_3_ULC_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_RSVD1_SHIFT)) & ISI_CHNL_ROI_3_ULC_RSVD1_MASK) #define ISI_CHNL_ROI_3_ULC_X_MASK (0xFFF0000U) #define ISI_CHNL_ROI_3_ULC_X_SHIFT (16U) #define ISI_CHNL_ROI_3_ULC_X(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_X_SHIFT)) & ISI_CHNL_ROI_3_ULC_X_MASK) #define ISI_CHNL_ROI_3_ULC_RSVD0_MASK (0xF0000000U) #define ISI_CHNL_ROI_3_ULC_RSVD0_SHIFT (28U) #define ISI_CHNL_ROI_3_ULC_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_RSVD0_SHIFT)) & ISI_CHNL_ROI_3_ULC_RSVD0_MASK) /*! @} */ /*! @name CHNL_ROI_3_LRC - Channel Lower Right Coordinate Register for Region of Interest 3 */ /*! @{ */ #define ISI_CHNL_ROI_3_LRC_Y_MASK (0xFFFU) #define ISI_CHNL_ROI_3_LRC_Y_SHIFT (0U) #define ISI_CHNL_ROI_3_LRC_Y(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_Y_SHIFT)) & ISI_CHNL_ROI_3_LRC_Y_MASK) #define ISI_CHNL_ROI_3_LRC_RSVD1_MASK (0xF000U) #define ISI_CHNL_ROI_3_LRC_RSVD1_SHIFT (12U) #define ISI_CHNL_ROI_3_LRC_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_RSVD1_SHIFT)) & ISI_CHNL_ROI_3_LRC_RSVD1_MASK) #define ISI_CHNL_ROI_3_LRC_X_MASK (0xFFF0000U) #define ISI_CHNL_ROI_3_LRC_X_SHIFT (16U) #define ISI_CHNL_ROI_3_LRC_X(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_X_SHIFT)) & ISI_CHNL_ROI_3_LRC_X_MASK) #define ISI_CHNL_ROI_3_LRC_RSVD0_MASK (0xF0000000U) #define ISI_CHNL_ROI_3_LRC_RSVD0_SHIFT (28U) #define ISI_CHNL_ROI_3_LRC_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_RSVD0_SHIFT)) & ISI_CHNL_ROI_3_LRC_RSVD0_MASK) /*! @} */ /*! @name CHNL_OUT_BUF1_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 1 Address */ /*! @{ */ #define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT (0U) #define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK) /*! @} */ /*! @name CHNL_OUT_BUF1_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */ /*! @{ */ #define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT (0U) #define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK) /*! @} */ /*! @name CHNL_OUT_BUF1_ADDR_V - Channel Chroma (V/Cr) Output Buffer 1 Address */ /*! @{ */ #define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT (0U) #define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK) /*! @} */ /*! @name CHNL_OUT_BUF_PITCH - Channel Output Buffer Pitch */ /*! @{ */ #define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK (0xFFFFU) #define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT (0U) #define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK) /*! @} */ /*! @name CHNL_IN_BUF_ADDR - Channel Input Buffer Address */ /*! @{ */ #define ISI_CHNL_IN_BUF_ADDR_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT (0U) #define ISI_CHNL_IN_BUF_ADDR_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT)) & ISI_CHNL_IN_BUF_ADDR_ADDR_MASK) /*! @} */ /*! @name CHNL_IN_BUF_PITCH - Channel Input Buffer Pitch */ /*! @{ */ #define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK (0xFFFFU) #define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT (0U) #define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK) #define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK (0xFFFF0000U) #define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT (16U) #define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK) /*! @} */ /*! @name CHNL_MEM_RD_CTRL - Channel Memory Read Control */ /*! @{ */ #define ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK (0x1U) #define ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT (0U) /*! READ_MEM - Initiate read from memory * 0b0..No reads from memory done * 0b1..Reads from memory initiated */ #define ISI_CHNL_MEM_RD_CTRL_READ_MEM(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK) #define ISI_CHNL_MEM_RD_CTRL_RSVD0_MASK (0xFFFFFFEU) #define ISI_CHNL_MEM_RD_CTRL_RSVD0_SHIFT (1U) #define ISI_CHNL_MEM_RD_CTRL_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_RSVD0_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_RSVD0_MASK) #define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK (0xF0000000U) #define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT (28U) /*! IMG_TYPE - Input image format * 0b0000..BGR8P - BGR format with 8-bits per color component (packed into 32-bit DWORD) * 0b0001..RGB8P - RGB format with 8-bits per color component (packed into 32-bit DWORD) * 0b0010..XRGB8 - RGB format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD) * 0b0011..RGBX8 - RGB format with 8-bits per color component (unpacked and MSBalinged in 32-bit DWORD) * 0b0100..XBGR8 - BGR format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD) * 0b0101..RGB565 - RGB format with 5-bits of R, B; 6-bits of G (packed into 32-bit DWORD) * 0b0110..A2BGR10 - BGR format with 2-bits alpha in MSB; 10-bits per color component * 0b0111..A2RGB10 - RGB format with 2-bits alpha in MSB; 10-bits per color component * 0b1000..YUV444_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes * 0b1001..YUV444_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in * 16-bit WORD) 0b1010..YUV444_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs * waste bits in 32-bit WORD) 0b1011..YUV444_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked * bytes (4 LSBs waste bits in 16-bit WORD) 0b1100..YUV444_1P8 with 8-bits per color component; 1-plane YUV interleaved * unpacked bytes (8 MSBs waste bits in 32-bit DWORD) 0b1101..YUV422_1P8P with 8-bits per color component; 1-plane YUV * interleaved packed bytes 0b1110..YUV422_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked * bytes (6 LSBs waste bits in 16-bit WORD) 0b1111..YUV422_1P12 with 12-bits per color component; 1-plane, YUV * interleaved packed bytes (4 MSBs waste bits in 16-bit WORD) */ #define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK) /*! @} */ /*! @name CHNL_OUT_BUF2_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 2 Address */ /*! @{ */ #define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT (0U) #define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK) /*! @} */ /*! @name CHNL_OUT_BUF2_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address */ /*! @{ */ #define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT (0U) #define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK) /*! @} */ /*! @name CHNL_OUT_BUF2_ADDR_V - Channel Chroma (V/Cr) Output Buffer 2 Address */ /*! @{ */ #define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT (0U) #define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK) /*! @} */ /*! @name CHNL_SCL_IMG_CFG - Channel Scaled Image Configuration */ /*! @{ */ #define ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK (0x1FFFU) #define ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT (0U) #define ISI_CHNL_SCL_IMG_CFG_WIDTH(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK) #define ISI_CHNL_SCL_IMG_CFG_RSVD0_MASK (0xE000U) #define ISI_CHNL_SCL_IMG_CFG_RSVD0_SHIFT (13U) #define ISI_CHNL_SCL_IMG_CFG_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_RSVD0_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_RSVD0_MASK) #define ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK (0x1FFF0000U) #define ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT (16U) #define ISI_CHNL_SCL_IMG_CFG_HEIGHT(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK) #define ISI_CHNL_SCL_IMG_CFG_RSVD1_MASK (0xE0000000U) #define ISI_CHNL_SCL_IMG_CFG_RSVD1_SHIFT (29U) #define ISI_CHNL_SCL_IMG_CFG_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_RSVD1_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_RSVD1_MASK) /*! @} */ /*! @name CHNL_FLOW_CTRL - Channel Flow Control Register */ /*! @{ */ #define ISI_CHNL_FLOW_CTRL_FC_DENOM_MASK (0xFFU) #define ISI_CHNL_FLOW_CTRL_FC_DENOM_SHIFT (0U) /*! FC_DENOM - Denominator value of fraction of usable bandwidth * 0b00000000..Invalid value. Flow control will be disabled. */ #define ISI_CHNL_FLOW_CTRL_FC_DENOM(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_FLOW_CTRL_FC_DENOM_SHIFT)) & ISI_CHNL_FLOW_CTRL_FC_DENOM_MASK) #define ISI_CHNL_FLOW_CTRL_FC_NUMER_MASK (0xFF0000U) #define ISI_CHNL_FLOW_CTRL_FC_NUMER_SHIFT (16U) /*! FC_NUMER - Numertor value of fraction of usable bandwidth * 0b00000000..Flow control is disabled. */ #define ISI_CHNL_FLOW_CTRL_FC_NUMER(x) \ (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_FLOW_CTRL_FC_NUMER_SHIFT)) & ISI_CHNL_FLOW_CTRL_FC_NUMER_MASK) /*! @} */ /*! * @} */ /* end of group ISI_Register_Masks */ /* ISI - Peripheral instance base addresses */ /** Peripheral ISI base address */ #define ISI_BASE (0x32E20000u) /** Peripheral ISI base pointer */ #define ISI ((ISI_Type *)ISI_BASE) /** Array initializer of ISI peripheral base addresses */ #define ISI_BASE_ADDRS \ { \ ISI_BASE \ } /** Array initializer of ISI peripheral base pointers */ #define ISI_BASE_PTRS \ { \ ISI \ } /*! * @} */ /* end of group ISI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LCDIF Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer * @{ */ /** LCDIF - Register Layout Typedef */ typedef struct { __IO uint32_t CTRL; /**< LCDIF General Control Register, offset: 0x0 */ __IO uint32_t CTRL_SET; /**< LCDIF General Control Register, offset: 0x4 */ __IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 */ __IO uint32_t CTRL_TOG; /**< LCDIF General Control Register, offset: 0xC */ __IO uint32_t CTRL1; /**< LCDIF General Control1 Register, offset: 0x10 */ __IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x14 */ __IO uint32_t CTRL1_CLR; /**< LCDIF General Control1 Register, offset: 0x18 */ __IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1C */ __IO uint32_t CTRL2; /**< LCDIF General Control2 Register, offset: 0x20 */ __IO uint32_t CTRL2_SET; /**< LCDIF General Control2 Register, offset: 0x24 */ __IO uint32_t CTRL2_CLR; /**< LCDIF General Control2 Register, offset: 0x28 */ __IO uint32_t CTRL2_TOG; /**< LCDIF General Control2 Register, offset: 0x2C */ __IO uint32_t TRANSFER_COUNT; /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ uint8_t RESERVED_0[12]; __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */ uint8_t RESERVED_1[12]; __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */ uint8_t RESERVED_2[12]; __IO uint32_t TIMING; /**< LCD Interface Timing Register, offset: 0x60 */ uint8_t RESERVED_3[12]; __IO uint32_t VDCTRL0; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ __IO uint32_t VDCTRL0_SET; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ __IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ __IO uint32_t VDCTRL0_TOG; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ __IO uint32_t VDCTRL1; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ uint8_t RESERVED_4[12]; __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */ uint8_t RESERVED_5[12]; __IO uint32_t VDCTRL3; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ uint8_t RESERVED_6[12]; __IO uint32_t VDCTRL4; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ uint8_t RESERVED_7[12]; __IO uint32_t DVICTRL0; /**< Digital Video Interface Control0 Register, offset: 0xC0 */ uint8_t RESERVED_8[12]; __IO uint32_t DVICTRL1; /**< Digital Video Interface Control1 Register, offset: 0xD0 */ uint8_t RESERVED_9[12]; __IO uint32_t DVICTRL2; /**< Digital Video Interface Control2 Register, offset: 0xE0 */ uint8_t RESERVED_10[12]; __IO uint32_t DVICTRL3; /**< Digital Video Interface Control3 Register, offset: 0xF0 */ uint8_t RESERVED_11[12]; __IO uint32_t DVICTRL4; /**< Digital Video Interface Control4 Register, offset: 0x100 */ uint8_t RESERVED_12[12]; __IO uint32_t CSC_COEFF0; /**< RGB to YCbCr 4:2:2 CSC Coefficient0 Register, offset: 0x110 */ uint8_t RESERVED_13[12]; __IO uint32_t CSC_COEFF1; /**< RGB to YCbCr 4:2:2 CSC Coefficient1 Register, offset: 0x120 */ uint8_t RESERVED_14[12]; __IO uint32_t CSC_COEFF2; /**< RGB to YCbCr 4:2:2 CSC Coefficent2 Register, offset: 0x130 */ uint8_t RESERVED_15[12]; __IO uint32_t CSC_COEFF3; /**< RGB to YCbCr 4:2:2 CSC Coefficient3 Register, offset: 0x140 */ uint8_t RESERVED_16[12]; __IO uint32_t CSC_COEFF4; /**< RGB to YCbCr 4:2:2 CSC Coefficient4 Register, offset: 0x150 */ uint8_t RESERVED_17[12]; __IO uint32_t CSC_OFFSET; /**< RGB to YCbCr 4:2:2 CSC Offset Register, offset: 0x160 */ uint8_t RESERVED_18[12]; __IO uint32_t CSC_LIMIT; /**< RGB to YCbCr 4:2:2 CSC Limit Register, offset: 0x170 */ uint8_t RESERVED_19[12]; __IO uint32_t DATA; /**< LCD Interface Data Register, offset: 0x180 */ uint8_t RESERVED_20[12]; __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */ uint8_t RESERVED_21[12]; __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */ uint8_t RESERVED_22[12]; __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ uint8_t RESERVED_23[76]; __IO uint32_t THRES; /**< LCDIF Threshold Register, offset: 0x200 */ uint8_t RESERVED_24[12]; __IO uint32_t AS_CTRL; /**< LCDIF AS Buffer Control Register, offset: 0x210 */ uint8_t RESERVED_25[12]; __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x220 */ uint8_t RESERVED_26[12]; __IO uint32_t AS_NEXT_BUF; /**< , offset: 0x230 */ uint8_t RESERVED_27[12]; __IO uint32_t AS_CLRKEYLOW; /**< LCDIF Overlay Color Key Low, offset: 0x240 */ uint8_t RESERVED_28[12]; __IO uint32_t AS_CLRKEYHIGH; /**< LCDIF Overlay Color Key High, offset: 0x250 */ uint8_t RESERVED_29[12]; __IO uint32_t SYNC_DELAY; /**< LCD working insync mode with CSI for VSYNC delay, offset: 0x260 */ uint8_t RESERVED_30[284]; __IO uint32_t PIGEONCTRL0; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x380 */ __IO uint32_t PIGEONCTRL0_SET; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x384 */ __IO uint32_t PIGEONCTRL0_CLR; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x388 */ __IO uint32_t PIGEONCTRL0_TOG; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x38C */ __IO uint32_t PIGEONCTRL1; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x390 */ __IO uint32_t PIGEONCTRL1_SET; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x394 */ __IO uint32_t PIGEONCTRL1_CLR; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x398 */ __IO uint32_t PIGEONCTRL1_TOG; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x39C */ __IO uint32_t PIGEONCTRL2; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A0 */ __IO uint32_t PIGEONCTRL2_SET; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A4 */ __IO uint32_t PIGEONCTRL2_CLR; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A8 */ __IO uint32_t PIGEONCTRL2_TOG; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3AC */ uint8_t RESERVED_31[1104]; struct { /* offset: 0x800, array step: 0x40 */ __IO uint32_t PIGEON_n_0; /**< Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40 */ uint8_t RESERVED_0[12]; __IO uint32_t PIGEON_n_1; /**< Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40 */ uint8_t RESERVED_1[12]; __IO uint32_t PIGEON_n_2; /**< Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40 */ uint8_t RESERVED_2[28]; } PIGEON_n[12]; } LCDIF_Type; /* ---------------------------------------------------------------------------- -- LCDIF Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LCDIF_Register_Masks LCDIF Register Masks * @{ */ /*! @name CTRL - LCDIF General Control Register */ /*! @{ */ #define LCDIF_CTRL_RUN_MASK (0x1U) #define LCDIF_CTRL_RUN_SHIFT (0U) #define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) #define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) /*! DATA_FORMAT_24_BIT * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in * each byte do not contain any useful data, and should be dropped. */ #define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) #define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) /*! DATA_FORMAT_18_BIT * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not * contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 * and lower 14 bits do not contain any useful data. */ #define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) #define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U) #define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK) #define LCDIF_CTRL_RSRVD0_MASK (0x10U) #define LCDIF_CTRL_RSRVD0_SHIFT (4U) #define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK) #define LCDIF_CTRL_MASTER_MASK (0x20U) #define LCDIF_CTRL_MASTER_SHIFT (5U) #define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK) #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U) #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U) #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK) #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK (0x80U) #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT (7U) #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK) #define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U) /*! WORD_LENGTH * 0b00..Input data is 16 bits per pixel. * 0b01..Input data is 8 bits wide. * 0b10..Input data is 18 bits per pixel. * 0b11..Input data is 24 bits per pixel. */ #define LCDIF_CTRL_WORD_LENGTH(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK) #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U) /*! LCD_DATABUS_WIDTH * 0b00..16-bit data bus mode. * 0b01..8-bit data bus mode. * 0b10..18-bit data bus mode. * 0b11..24-bit data bus mode. */ #define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK) #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U) /*! CSC_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U) /*! INPUT_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_DATA_SELECT_MASK (0x10000U) #define LCDIF_CTRL_DATA_SELECT_SHIFT (16U) /*! DATA_SELECT * 0b0..Command Mode. LCD_RS signal is Low. * 0b1..Data Mode. LCD_RS signal is High. */ #define LCDIF_CTRL_DATA_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SELECT_SHIFT)) & LCDIF_CTRL_DATA_SELECT_MASK) #define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U) #define LCDIF_CTRL_DOTCLK_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK) #define LCDIF_CTRL_VSYNC_MODE_MASK (0x40000U) #define LCDIF_CTRL_VSYNC_MODE_SHIFT (18U) #define LCDIF_CTRL_VSYNC_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_VSYNC_MODE_MASK) #define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U) #define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U) #define LCDIF_CTRL_BYPASS_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK) #define LCDIF_CTRL_DVI_MODE_MASK (0x100000U) #define LCDIF_CTRL_DVI_MODE_SHIFT (20U) #define LCDIF_CTRL_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DVI_MODE_SHIFT)) & LCDIF_CTRL_DVI_MODE_MASK) #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U) #define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U) #define LCDIF_CTRL_SHIFT_NUM_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK) #define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U) /*! DATA_SHIFT_DIR * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. */ #define LCDIF_CTRL_DATA_SHIFT_DIR(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK) #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK) #define LCDIF_CTRL_READ_WRITEB_MASK (0x10000000U) #define LCDIF_CTRL_READ_WRITEB_SHIFT (28U) #define LCDIF_CTRL_READ_WRITEB(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_READ_WRITEB_SHIFT)) & LCDIF_CTRL_READ_WRITEB_MASK) #define LCDIF_CTRL_YCBCR422_INPUT_MASK (0x20000000U) #define LCDIF_CTRL_YCBCR422_INPUT_SHIFT (29U) #define LCDIF_CTRL_YCBCR422_INPUT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_YCBCR422_INPUT_MASK) #define LCDIF_CTRL_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_CLKGATE_SHIFT (30U) #define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK) #define LCDIF_CTRL_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_SFTRST_SHIFT (31U) #define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) /*! @} */ /*! @name CTRL_SET - LCDIF General Control Register */ /*! @{ */ #define LCDIF_CTRL_SET_RUN_MASK (0x1U) #define LCDIF_CTRL_SET_RUN_SHIFT (0U) #define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) /*! DATA_FORMAT_24_BIT * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in * each byte do not contain any useful data, and should be dropped. */ #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) /*! DATA_FORMAT_18_BIT * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not * contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 * and lower 14 bits do not contain any useful data. */ #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U) #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK) #define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U) #define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U) #define LCDIF_CTRL_SET_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK) #define LCDIF_CTRL_SET_MASTER_MASK (0x20U) #define LCDIF_CTRL_SET_MASTER_SHIFT (5U) #define LCDIF_CTRL_SET_MASTER(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK) #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U) #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U) #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & \ LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK) #define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK (0x80U) #define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT (7U) #define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT)) & \ LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK) #define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U) /*! WORD_LENGTH * 0b00..Input data is 16 bits per pixel. * 0b01..Input data is 8 bits wide. * 0b10..Input data is 18 bits per pixel. * 0b11..Input data is 24 bits per pixel. */ #define LCDIF_CTRL_SET_WORD_LENGTH(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK) #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U) /*! LCD_DATABUS_WIDTH * 0b00..16-bit data bus mode. * 0b01..8-bit data bus mode. * 0b10..18-bit data bus mode. * 0b11..24-bit data bus mode. */ #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK) #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U) /*! CSC_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U) /*! INPUT_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_SET_DATA_SELECT_MASK (0x10000U) #define LCDIF_CTRL_SET_DATA_SELECT_SHIFT (16U) /*! DATA_SELECT * 0b0..Command Mode. LCD_RS signal is Low. * 0b1..Data Mode. LCD_RS signal is High. */ #define LCDIF_CTRL_SET_DATA_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SELECT_SHIFT)) & LCDIF_CTRL_SET_DATA_SELECT_MASK) #define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U) #define LCDIF_CTRL_SET_DOTCLK_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK) #define LCDIF_CTRL_SET_VSYNC_MODE_MASK (0x40000U) #define LCDIF_CTRL_SET_VSYNC_MODE_SHIFT (18U) #define LCDIF_CTRL_SET_VSYNC_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_SET_VSYNC_MODE_MASK) #define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U) #define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U) #define LCDIF_CTRL_SET_BYPASS_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK) #define LCDIF_CTRL_SET_DVI_MODE_MASK (0x100000U) #define LCDIF_CTRL_SET_DVI_MODE_SHIFT (20U) #define LCDIF_CTRL_SET_DVI_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DVI_MODE_SHIFT)) & LCDIF_CTRL_SET_DVI_MODE_MASK) #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U) #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U) #define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK) #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U) /*! DATA_SHIFT_DIR * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. */ #define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK) #define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) #define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) #define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT)) & \ LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK) #define LCDIF_CTRL_SET_READ_WRITEB_MASK (0x10000000U) #define LCDIF_CTRL_SET_READ_WRITEB_SHIFT (28U) #define LCDIF_CTRL_SET_READ_WRITEB(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_READ_WRITEB_SHIFT)) & LCDIF_CTRL_SET_READ_WRITEB_MASK) #define LCDIF_CTRL_SET_YCBCR422_INPUT_MASK (0x20000000U) #define LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT (29U) #define LCDIF_CTRL_SET_YCBCR422_INPUT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_SET_YCBCR422_INPUT_MASK) #define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U) #define LCDIF_CTRL_SET_CLKGATE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK) #define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_SET_SFTRST_SHIFT (31U) #define LCDIF_CTRL_SET_SFTRST(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) /*! @} */ /*! @name CTRL_CLR - LCDIF General Control Register */ /*! @{ */ #define LCDIF_CTRL_CLR_RUN_MASK (0x1U) #define LCDIF_CTRL_CLR_RUN_SHIFT (0U) #define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) /*! DATA_FORMAT_24_BIT * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in * each byte do not contain any useful data, and should be dropped. */ #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) /*! DATA_FORMAT_18_BIT * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not * contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 * and lower 14 bits do not contain any useful data. */ #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U) #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK) #define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U) #define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U) #define LCDIF_CTRL_CLR_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK) #define LCDIF_CTRL_CLR_MASTER_MASK (0x20U) #define LCDIF_CTRL_CLR_MASTER_SHIFT (5U) #define LCDIF_CTRL_CLR_MASTER(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK) #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U) #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U) #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & \ LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK) #define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK (0x80U) #define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT (7U) #define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT)) & \ LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK) #define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U) /*! WORD_LENGTH * 0b00..Input data is 16 bits per pixel. * 0b01..Input data is 8 bits wide. * 0b10..Input data is 18 bits per pixel. * 0b11..Input data is 24 bits per pixel. */ #define LCDIF_CTRL_CLR_WORD_LENGTH(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK) #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U) /*! LCD_DATABUS_WIDTH * 0b00..16-bit data bus mode. * 0b01..8-bit data bus mode. * 0b10..18-bit data bus mode. * 0b11..24-bit data bus mode. */ #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK) #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U) /*! CSC_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U) /*! INPUT_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_CLR_DATA_SELECT_MASK (0x10000U) #define LCDIF_CTRL_CLR_DATA_SELECT_SHIFT (16U) /*! DATA_SELECT * 0b0..Command Mode. LCD_RS signal is Low. * 0b1..Data Mode. LCD_RS signal is High. */ #define LCDIF_CTRL_CLR_DATA_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SELECT_SHIFT)) & LCDIF_CTRL_CLR_DATA_SELECT_MASK) #define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U) #define LCDIF_CTRL_CLR_DOTCLK_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK) #define LCDIF_CTRL_CLR_VSYNC_MODE_MASK (0x40000U) #define LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT (18U) #define LCDIF_CTRL_CLR_VSYNC_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_CLR_VSYNC_MODE_MASK) #define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U) #define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U) #define LCDIF_CTRL_CLR_BYPASS_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK) #define LCDIF_CTRL_CLR_DVI_MODE_MASK (0x100000U) #define LCDIF_CTRL_CLR_DVI_MODE_SHIFT (20U) #define LCDIF_CTRL_CLR_DVI_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DVI_MODE_SHIFT)) & LCDIF_CTRL_CLR_DVI_MODE_MASK) #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U) #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U) #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK) #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U) /*! DATA_SHIFT_DIR * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. */ #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK) #define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) #define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) #define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT)) & \ LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK) #define LCDIF_CTRL_CLR_READ_WRITEB_MASK (0x10000000U) #define LCDIF_CTRL_CLR_READ_WRITEB_SHIFT (28U) #define LCDIF_CTRL_CLR_READ_WRITEB(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_READ_WRITEB_SHIFT)) & LCDIF_CTRL_CLR_READ_WRITEB_MASK) #define LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK (0x20000000U) #define LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT (29U) #define LCDIF_CTRL_CLR_YCBCR422_INPUT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK) #define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U) #define LCDIF_CTRL_CLR_CLKGATE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK) #define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) #define LCDIF_CTRL_CLR_SFTRST(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) /*! @} */ /*! @name CTRL_TOG - LCDIF General Control Register */ /*! @{ */ #define LCDIF_CTRL_TOG_RUN_MASK (0x1U) #define LCDIF_CTRL_TOG_RUN_SHIFT (0U) #define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) /*! DATA_FORMAT_24_BIT * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in * each byte do not contain any useful data, and should be dropped. */ #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) /*! DATA_FORMAT_18_BIT * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not * contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 * and lower 14 bits do not contain any useful data. */ #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U) #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK) #define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U) #define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U) #define LCDIF_CTRL_TOG_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK) #define LCDIF_CTRL_TOG_MASTER_MASK (0x20U) #define LCDIF_CTRL_TOG_MASTER_SHIFT (5U) #define LCDIF_CTRL_TOG_MASTER(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK) #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U) #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U) #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & \ LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK) #define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK (0x80U) #define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT (7U) #define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT)) & \ LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK) #define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U) /*! WORD_LENGTH * 0b00..Input data is 16 bits per pixel. * 0b01..Input data is 8 bits wide. * 0b10..Input data is 18 bits per pixel. * 0b11..Input data is 24 bits per pixel. */ #define LCDIF_CTRL_TOG_WORD_LENGTH(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK) #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U) /*! LCD_DATABUS_WIDTH * 0b00..16-bit data bus mode. * 0b01..8-bit data bus mode. * 0b10..18-bit data bus mode. * 0b11..24-bit data bus mode. */ #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK) #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U) /*! CSC_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U) /*! INPUT_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_TOG_DATA_SELECT_MASK (0x10000U) #define LCDIF_CTRL_TOG_DATA_SELECT_SHIFT (16U) /*! DATA_SELECT * 0b0..Command Mode. LCD_RS signal is Low. * 0b1..Data Mode. LCD_RS signal is High. */ #define LCDIF_CTRL_TOG_DATA_SELECT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SELECT_SHIFT)) & LCDIF_CTRL_TOG_DATA_SELECT_MASK) #define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U) #define LCDIF_CTRL_TOG_DOTCLK_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK) #define LCDIF_CTRL_TOG_VSYNC_MODE_MASK (0x40000U) #define LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT (18U) #define LCDIF_CTRL_TOG_VSYNC_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_TOG_VSYNC_MODE_MASK) #define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U) #define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U) #define LCDIF_CTRL_TOG_BYPASS_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK) #define LCDIF_CTRL_TOG_DVI_MODE_MASK (0x100000U) #define LCDIF_CTRL_TOG_DVI_MODE_SHIFT (20U) #define LCDIF_CTRL_TOG_DVI_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DVI_MODE_SHIFT)) & LCDIF_CTRL_TOG_DVI_MODE_MASK) #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U) #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U) #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK) #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U) /*! DATA_SHIFT_DIR * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. */ #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK) #define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) #define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) #define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT)) & \ LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK) #define LCDIF_CTRL_TOG_READ_WRITEB_MASK (0x10000000U) #define LCDIF_CTRL_TOG_READ_WRITEB_SHIFT (28U) #define LCDIF_CTRL_TOG_READ_WRITEB(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_READ_WRITEB_SHIFT)) & LCDIF_CTRL_TOG_READ_WRITEB_MASK) #define LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK (0x20000000U) #define LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT (29U) #define LCDIF_CTRL_TOG_YCBCR422_INPUT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK) #define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U) #define LCDIF_CTRL_TOG_CLKGATE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK) #define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) #define LCDIF_CTRL_TOG_SFTRST(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) /*! @} */ /*! @name CTRL1 - LCDIF General Control1 Register */ /*! @{ */ #define LCDIF_CTRL1_RESET_MASK (0x1U) #define LCDIF_CTRL1_RESET_SHIFT (0U) /*! RESET * 0b0..LCD_RESET output signal is low. * 0b1..LCD_RESET output signal is high. */ #define LCDIF_CTRL1_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RESET_SHIFT)) & LCDIF_CTRL1_RESET_MASK) #define LCDIF_CTRL1_MODE86_MASK (0x2U) #define LCDIF_CTRL1_MODE86_SHIFT (1U) /*! MODE86 * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. */ #define LCDIF_CTRL1_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_MODE86_SHIFT)) & LCDIF_CTRL1_MODE86_MASK) #define LCDIF_CTRL1_BUSY_ENABLE_MASK (0x4U) #define LCDIF_CTRL1_BUSY_ENABLE_SHIFT (2U) /*! BUSY_ENABLE * 0b0..The busy signal from the LCD controller will be ignored. * 0b1..Enable the use of the busy signal from the LCD controller. */ #define LCDIF_CTRL1_BUSY_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_BUSY_ENABLE_MASK) #define LCDIF_CTRL1_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U) /*! VSYNC_EDGE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U) /*! CUR_FRAME_DONE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK) #define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U) /*! UNDERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_UNDERFLOW_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK) #define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U) /*! OVERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_OVERFLOW_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK) #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U) #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U) #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U) #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U) #define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U) #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U) #define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & \ LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK) #define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U) #define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U) #define LCDIF_CTRL1_FIFO_CLEAR(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK) #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & \ LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK) #define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U) #define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U) #define LCDIF_CTRL1_INTERLACE_FIELDS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK) #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U) #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK) #define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U) /*! BM_ERROR_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_BM_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK) #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U) #define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK) #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK (0x8000000U) #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT (27U) #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK) /*! @} */ /*! @name CTRL1_SET - LCDIF General Control1 Register */ /*! @{ */ #define LCDIF_CTRL1_SET_RESET_MASK (0x1U) #define LCDIF_CTRL1_SET_RESET_SHIFT (0U) /*! RESET * 0b0..LCD_RESET output signal is low. * 0b1..LCD_RESET output signal is high. */ #define LCDIF_CTRL1_SET_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RESET_SHIFT)) & LCDIF_CTRL1_SET_RESET_MASK) #define LCDIF_CTRL1_SET_MODE86_MASK (0x2U) #define LCDIF_CTRL1_SET_MODE86_SHIFT (1U) /*! MODE86 * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. */ #define LCDIF_CTRL1_SET_MODE86(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_MODE86_SHIFT)) & LCDIF_CTRL1_SET_MODE86_MASK) #define LCDIF_CTRL1_SET_BUSY_ENABLE_MASK (0x4U) #define LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT (2U) /*! BUSY_ENABLE * 0b0..The busy signal from the LCD controller will be ignored. * 0b1..Enable the use of the busy signal from the LCD controller. */ #define LCDIF_CTRL1_SET_BUSY_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_SET_BUSY_ENABLE_MASK) #define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_SET_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U) /*! VSYNC_EDGE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U) /*! CUR_FRAME_DONE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & \ LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U) /*! UNDERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U) /*! OVERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & \ LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U) #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U) #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & \ LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & \ LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK) #define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U) #define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U) #define LCDIF_CTRL1_SET_FIFO_CLEAR(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK) #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & \ LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK) #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U) #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U) #define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK) #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U) #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & \ LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U) /*! BM_ERROR_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK) #define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK (0x8000000U) #define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT (27U) #define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT)) & \ LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK) /*! @} */ /*! @name CTRL1_CLR - LCDIF General Control1 Register */ /*! @{ */ #define LCDIF_CTRL1_CLR_RESET_MASK (0x1U) #define LCDIF_CTRL1_CLR_RESET_SHIFT (0U) /*! RESET * 0b0..LCD_RESET output signal is low. * 0b1..LCD_RESET output signal is high. */ #define LCDIF_CTRL1_CLR_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RESET_SHIFT)) & LCDIF_CTRL1_CLR_RESET_MASK) #define LCDIF_CTRL1_CLR_MODE86_MASK (0x2U) #define LCDIF_CTRL1_CLR_MODE86_SHIFT (1U) /*! MODE86 * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. */ #define LCDIF_CTRL1_CLR_MODE86(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_MODE86_SHIFT)) & LCDIF_CTRL1_CLR_MODE86_MASK) #define LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK (0x4U) #define LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT (2U) /*! BUSY_ENABLE * 0b0..The busy signal from the LCD controller will be ignored. * 0b1..Enable the use of the busy signal from the LCD controller. */ #define LCDIF_CTRL1_CLR_BUSY_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK) #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_CLR_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U) /*! VSYNC_EDGE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U) /*! CUR_FRAME_DONE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & \ LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U) /*! UNDERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U) /*! OVERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & \ LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U) #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U) #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & \ LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & \ LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK) #define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U) #define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U) #define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK) #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & \ LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK) #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U) #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U) #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK) #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U) #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & \ LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U) /*! BM_ERROR_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK) #define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK (0x8000000U) #define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT (27U) #define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT)) & \ LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK) /*! @} */ /*! @name CTRL1_TOG - LCDIF General Control1 Register */ /*! @{ */ #define LCDIF_CTRL1_TOG_RESET_MASK (0x1U) #define LCDIF_CTRL1_TOG_RESET_SHIFT (0U) /*! RESET * 0b0..LCD_RESET output signal is low. * 0b1..LCD_RESET output signal is high. */ #define LCDIF_CTRL1_TOG_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RESET_SHIFT)) & LCDIF_CTRL1_TOG_RESET_MASK) #define LCDIF_CTRL1_TOG_MODE86_MASK (0x2U) #define LCDIF_CTRL1_TOG_MODE86_SHIFT (1U) /*! MODE86 * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. */ #define LCDIF_CTRL1_TOG_MODE86(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_MODE86_SHIFT)) & LCDIF_CTRL1_TOG_MODE86_MASK) #define LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK (0x4U) #define LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT (2U) /*! BUSY_ENABLE * 0b0..The busy signal from the LCD controller will be ignored. * 0b1..Enable the use of the busy signal from the LCD controller. */ #define LCDIF_CTRL1_TOG_BUSY_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK) #define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_TOG_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U) /*! VSYNC_EDGE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U) /*! CUR_FRAME_DONE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & \ LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U) /*! UNDERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U) /*! OVERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & \ LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U) #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U) #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & \ LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & \ LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK) #define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U) #define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U) #define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK) #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & \ LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK) #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U) #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U) #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK) #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U) #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & \ LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U) /*! BM_ERROR_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK) #define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK (0x8000000U) #define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT (27U) #define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT)) & \ LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK) /*! @} */ /*! @name CTRL2 - LCDIF General Control2 Register */ /*! @{ */ #define LCDIF_CTRL2_RSRVD0_MASK (0x1U) #define LCDIF_CTRL2_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0xEU) #define LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT (1U) #define LCDIF_CTRL2_INITIAL_DUMMY_READ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK) #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & \ LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK) #define LCDIF_CTRL2_RSRVD1_MASK (0x80U) #define LCDIF_CTRL2_RSRVD1_SHIFT (7U) #define LCDIF_CTRL2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD1_SHIFT)) & LCDIF_CTRL2_RSRVD1_MASK) #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK (0x100U) #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT (8U) #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK) #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & \ LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) #define LCDIF_CTRL2_READ_PACK_DIR_MASK (0x400U) #define LCDIF_CTRL2_READ_PACK_DIR_SHIFT (10U) #define LCDIF_CTRL2_READ_PACK_DIR(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_READ_PACK_DIR_MASK) #define LCDIF_CTRL2_RSRVD2_MASK (0x800U) #define LCDIF_CTRL2_RSRVD2_SHIFT (11U) #define LCDIF_CTRL2_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD2_SHIFT)) & LCDIF_CTRL2_RSRVD2_MASK) #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U) /*! EVEN_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) #define LCDIF_CTRL2_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK) #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U) /*! ODD_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_ODD_LINE_PATTERN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) #define LCDIF_CTRL2_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_RSRVD4_SHIFT (19U) #define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK) #define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U) #define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U) #define LCDIF_CTRL2_BURST_LEN_8(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK) #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U) /*! OUTSTANDING_REQS * 0b000..REQ_1 * 0b001..REQ_2 * 0b010..REQ_4 * 0b011..REQ_8 * 0b100..REQ_16 */ #define LCDIF_CTRL2_OUTSTANDING_REQS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK) #define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) /*! @} */ /*! @name CTRL2_SET - LCDIF General Control2 Register */ /*! @{ */ #define LCDIF_CTRL2_SET_RSRVD0_MASK (0x1U) #define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_SET_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK (0xEU) #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT (1U) #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT)) & \ LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK) #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & \ LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK) #define LCDIF_CTRL2_SET_RSRVD1_MASK (0x80U) #define LCDIF_CTRL2_SET_RSRVD1_SHIFT (7U) #define LCDIF_CTRL2_SET_RSRVD1(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD1_SHIFT)) & LCDIF_CTRL2_SET_RSRVD1_MASK) #define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK (0x100U) #define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT (8U) #define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT)) & \ LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK) #define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) #define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) #define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & \ LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) #define LCDIF_CTRL2_SET_READ_PACK_DIR_MASK (0x400U) #define LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT (10U) #define LCDIF_CTRL2_SET_READ_PACK_DIR(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_SET_READ_PACK_DIR_MASK) #define LCDIF_CTRL2_SET_RSRVD2_MASK (0x800U) #define LCDIF_CTRL2_SET_RSRVD2_SHIFT (11U) #define LCDIF_CTRL2_SET_RSRVD2(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD2_SHIFT)) & LCDIF_CTRL2_SET_RSRVD2_MASK) #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U) /*! EVEN_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) #define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_SET_RSRVD3(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK) #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U) /*! ODD_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) #define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U) #define LCDIF_CTRL2_SET_RSRVD4(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK) #define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U) #define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U) #define LCDIF_CTRL2_SET_BURST_LEN_8(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK) #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U) /*! OUTSTANDING_REQS * 0b000..REQ_1 * 0b001..REQ_2 * 0b010..REQ_4 * 0b011..REQ_8 * 0b100..REQ_16 */ #define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) #define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_SET_RSRVD5(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) /*! @} */ /*! @name CTRL2_CLR - LCDIF General Control2 Register */ /*! @{ */ #define LCDIF_CTRL2_CLR_RSRVD0_MASK (0x1U) #define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_CLR_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK (0xEU) #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT (1U) #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT)) & \ LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK) #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & \ LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK) #define LCDIF_CTRL2_CLR_RSRVD1_MASK (0x80U) #define LCDIF_CTRL2_CLR_RSRVD1_SHIFT (7U) #define LCDIF_CTRL2_CLR_RSRVD1(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD1_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD1_MASK) #define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK (0x100U) #define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT (8U) #define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT)) & \ LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK) #define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) #define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) #define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & \ LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) #define LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK (0x400U) #define LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT (10U) #define LCDIF_CTRL2_CLR_READ_PACK_DIR(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK) #define LCDIF_CTRL2_CLR_RSRVD2_MASK (0x800U) #define LCDIF_CTRL2_CLR_RSRVD2_SHIFT (11U) #define LCDIF_CTRL2_CLR_RSRVD2(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD2_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD2_MASK) #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U) /*! EVEN_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) #define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_CLR_RSRVD3(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK) #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U) /*! ODD_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) #define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U) #define LCDIF_CTRL2_CLR_RSRVD4(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK) #define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U) #define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U) #define LCDIF_CTRL2_CLR_BURST_LEN_8(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK) #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U) /*! OUTSTANDING_REQS * 0b000..REQ_1 * 0b001..REQ_2 * 0b010..REQ_4 * 0b011..REQ_8 * 0b100..REQ_16 */ #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) #define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_CLR_RSRVD5(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) /*! @} */ /*! @name CTRL2_TOG - LCDIF General Control2 Register */ /*! @{ */ #define LCDIF_CTRL2_TOG_RSRVD0_MASK (0x1U) #define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_TOG_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK (0xEU) #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT (1U) #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT)) & \ LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK) #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & \ LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK) #define LCDIF_CTRL2_TOG_RSRVD1_MASK (0x80U) #define LCDIF_CTRL2_TOG_RSRVD1_SHIFT (7U) #define LCDIF_CTRL2_TOG_RSRVD1(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD1_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD1_MASK) #define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK (0x100U) #define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT (8U) #define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT)) & \ LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK) #define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) #define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) #define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & \ LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) #define LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK (0x400U) #define LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT (10U) #define LCDIF_CTRL2_TOG_READ_PACK_DIR(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK) #define LCDIF_CTRL2_TOG_RSRVD2_MASK (0x800U) #define LCDIF_CTRL2_TOG_RSRVD2_SHIFT (11U) #define LCDIF_CTRL2_TOG_RSRVD2(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD2_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD2_MASK) #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U) /*! EVEN_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) #define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_TOG_RSRVD3(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK) #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U) /*! ODD_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) #define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U) #define LCDIF_CTRL2_TOG_RSRVD4(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK) #define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U) #define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U) #define LCDIF_CTRL2_TOG_BURST_LEN_8(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK) #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U) /*! OUTSTANDING_REQS * 0b000..REQ_1 * 0b001..REQ_2 * 0b010..REQ_4 * 0b011..REQ_8 * 0b100..REQ_16 */ #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_TOG_RSRVD5(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) /*! @} */ /*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */ /*! @{ */ #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU) #define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) #define LCDIF_TRANSFER_COUNT_H_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U) #define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) #define LCDIF_TRANSFER_COUNT_V_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) /*! @} */ /*! @name CUR_BUF - LCD Interface Current Buffer Address Register */ /*! @{ */ #define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_CUR_BUF_ADDR_SHIFT (0U) #define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) /*! @} */ /*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */ /*! @{ */ #define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_NEXT_BUF_ADDR_SHIFT (0U) #define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) /*! @} */ /*! @name TIMING - LCD Interface Timing Register */ /*! @{ */ #define LCDIF_TIMING_DATA_SETUP_MASK (0xFFU) #define LCDIF_TIMING_DATA_SETUP_SHIFT (0U) #define LCDIF_TIMING_DATA_SETUP(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_SETUP_SHIFT)) & LCDIF_TIMING_DATA_SETUP_MASK) #define LCDIF_TIMING_DATA_HOLD_MASK (0xFF00U) #define LCDIF_TIMING_DATA_HOLD_SHIFT (8U) #define LCDIF_TIMING_DATA_HOLD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_HOLD_SHIFT)) & LCDIF_TIMING_DATA_HOLD_MASK) #define LCDIF_TIMING_CMD_SETUP_MASK (0xFF0000U) #define LCDIF_TIMING_CMD_SETUP_SHIFT (16U) #define LCDIF_TIMING_CMD_SETUP(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_SETUP_SHIFT)) & LCDIF_TIMING_CMD_SETUP_MASK) #define LCDIF_TIMING_CMD_HOLD_MASK (0xFF000000U) #define LCDIF_TIMING_CMD_HOLD_SHIFT (24U) #define LCDIF_TIMING_CMD_HOLD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_HOLD_SHIFT)) & LCDIF_TIMING_CMD_HOLD_MASK) /*! @} */ /*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ /*! @{ */ #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) #define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U) #define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U) #define LCDIF_VDCTRL0_HALF_LINE_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK) #define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U) #define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U) #define LCDIF_VDCTRL0_HALF_LINE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & \ LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK) #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U) #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U) #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK) #define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U) #define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U) #define LCDIF_VDCTRL0_RSRVD1(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK) #define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U) #define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U) #define LCDIF_VDCTRL0_ENABLE_POL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK) #define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U) #define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U) #define LCDIF_VDCTRL0_DOTCLK_POL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK) #define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U) #define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U) #define LCDIF_VDCTRL0_HSYNC_POL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK) #define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U) #define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U) #define LCDIF_VDCTRL0_VSYNC_POL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK) #define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U) #define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U) #define LCDIF_VDCTRL0_ENABLE_PRESENT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK) #define LCDIF_VDCTRL0_VSYNC_OEB_MASK (0x20000000U) #define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT (29U) /*! VSYNC_OEB * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. */ #define LCDIF_VDCTRL0_VSYNC_OEB(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK) #define LCDIF_VDCTRL0_RSRVD2_MASK (0xC0000000U) #define LCDIF_VDCTRL0_RSRVD2_SHIFT (30U) #define LCDIF_VDCTRL0_RSRVD2(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) /*! @} */ /*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ /*! @{ */ #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & \ LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U) #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U) #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK) #define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U) #define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U) #define LCDIF_VDCTRL0_SET_HALF_LINE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & \ LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK) #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U) #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U) #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & \ LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK) #define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U) #define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U) #define LCDIF_VDCTRL0_SET_RSRVD1(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK) #define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U) #define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U) #define LCDIF_VDCTRL0_SET_ENABLE_POL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK) #define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U) #define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U) #define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK) #define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U) #define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U) #define LCDIF_VDCTRL0_SET_HSYNC_POL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK) #define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U) #define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U) #define LCDIF_VDCTRL0_SET_VSYNC_POL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK) #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U) #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U) #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK) #define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK (0x20000000U) #define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT (29U) /*! VSYNC_OEB * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. */ #define LCDIF_VDCTRL0_SET_VSYNC_OEB(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK) #define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xC0000000U) #define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (30U) #define LCDIF_VDCTRL0_SET_RSRVD2(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) /*! @} */ /*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ /*! @{ */ #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & \ LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U) #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U) #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK) #define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U) #define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U) #define LCDIF_VDCTRL0_CLR_HALF_LINE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & \ LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK) #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U) #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U) #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & \ LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK) #define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U) #define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U) #define LCDIF_VDCTRL0_CLR_RSRVD1(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK) #define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U) #define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U) #define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK) #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U) #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U) #define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK) #define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U) #define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U) #define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK) #define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U) #define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U) #define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK) #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U) #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U) #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK) #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK (0x20000000U) #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT (29U) /*! VSYNC_OEB * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. */ #define LCDIF_VDCTRL0_CLR_VSYNC_OEB(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK) #define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xC0000000U) #define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (30U) #define LCDIF_VDCTRL0_CLR_RSRVD2(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) /*! @} */ /*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ /*! @{ */ #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & \ LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U) #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U) #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK) #define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U) #define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U) #define LCDIF_VDCTRL0_TOG_HALF_LINE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & \ LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK) #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U) #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U) #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & \ LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK) #define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U) #define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U) #define LCDIF_VDCTRL0_TOG_RSRVD1(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK) #define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U) #define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U) #define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK) #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U) #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U) #define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK) #define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U) #define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U) #define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK) #define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U) #define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U) #define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK) #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U) #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U) #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK) #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK (0x20000000U) #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT (29U) /*! VSYNC_OEB * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. */ #define LCDIF_VDCTRL0_TOG_VSYNC_OEB(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK) #define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xC0000000U) #define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (30U) #define LCDIF_VDCTRL0_TOG_RSRVD2(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) /*! @} */ /*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */ /*! @{ */ #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU) #define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) #define LCDIF_VDCTRL1_VSYNC_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) /*! @} */ /*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */ /*! @{ */ #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU) #define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) #define LCDIF_VDCTRL2_HSYNC_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) /*! @} */ /*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */ /*! @{ */ #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU) #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U) #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U) #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) #define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U) #define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U) #define LCDIF_VDCTRL3_VSYNC_ONLY(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK) #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U) #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U) #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK) #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) #define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) #define LCDIF_VDCTRL3_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) /*! @} */ /*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */ /*! @{ */ #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU) #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & \ LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U) #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U) #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK) #define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U) #define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U) #define LCDIF_VDCTRL4_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK) #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U) #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) /*! @} */ /*! @name DVICTRL0 - Digital Video Interface Control0 Register */ /*! @{ */ #define LCDIF_DVICTRL0_H_BLANKING_CNT_MASK (0xFFFU) #define LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT (0U) #define LCDIF_DVICTRL0_H_BLANKING_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT)) & LCDIF_DVICTRL0_H_BLANKING_CNT_MASK) #define LCDIF_DVICTRL0_RSRVD0_MASK (0xF000U) #define LCDIF_DVICTRL0_RSRVD0_SHIFT (12U) #define LCDIF_DVICTRL0_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD0_SHIFT)) & LCDIF_DVICTRL0_RSRVD0_MASK) #define LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK (0xFFF0000U) #define LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT (16U) #define LCDIF_DVICTRL0_H_ACTIVE_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT)) & LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK) #define LCDIF_DVICTRL0_RSRVD1_MASK (0xF0000000U) #define LCDIF_DVICTRL0_RSRVD1_SHIFT (28U) #define LCDIF_DVICTRL0_RSRVD1(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD1_SHIFT)) & LCDIF_DVICTRL0_RSRVD1_MASK) /*! @} */ /*! @name DVICTRL1 - Digital Video Interface Control1 Register */ /*! @{ */ #define LCDIF_DVICTRL1_F2_START_LINE_MASK (0x3FFU) #define LCDIF_DVICTRL1_F2_START_LINE_SHIFT (0U) #define LCDIF_DVICTRL1_F2_START_LINE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F2_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F2_START_LINE_MASK) #define LCDIF_DVICTRL1_F1_END_LINE_MASK (0xFFC00U) #define LCDIF_DVICTRL1_F1_END_LINE_SHIFT (10U) #define LCDIF_DVICTRL1_F1_END_LINE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_END_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_END_LINE_MASK) #define LCDIF_DVICTRL1_F1_START_LINE_MASK (0x3FF00000U) #define LCDIF_DVICTRL1_F1_START_LINE_SHIFT (20U) #define LCDIF_DVICTRL1_F1_START_LINE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_START_LINE_MASK) #define LCDIF_DVICTRL1_RSRVD0_MASK (0xC0000000U) #define LCDIF_DVICTRL1_RSRVD0_SHIFT (30U) #define LCDIF_DVICTRL1_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_RSRVD0_SHIFT)) & LCDIF_DVICTRL1_RSRVD0_MASK) /*! @} */ /*! @name DVICTRL2 - Digital Video Interface Control2 Register */ /*! @{ */ #define LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK (0x3FFU) #define LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT (0U) #define LCDIF_DVICTRL2_V1_BLANK_END_LINE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK) #define LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK (0xFFC00U) #define LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT (10U) #define LCDIF_DVICTRL2_V1_BLANK_START_LINE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT)) & \ LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK) #define LCDIF_DVICTRL2_F2_END_LINE_MASK (0x3FF00000U) #define LCDIF_DVICTRL2_F2_END_LINE_SHIFT (20U) #define LCDIF_DVICTRL2_F2_END_LINE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_F2_END_LINE_SHIFT)) & LCDIF_DVICTRL2_F2_END_LINE_MASK) #define LCDIF_DVICTRL2_RSRVD0_MASK (0xC0000000U) #define LCDIF_DVICTRL2_RSRVD0_SHIFT (30U) #define LCDIF_DVICTRL2_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_RSRVD0_SHIFT)) & LCDIF_DVICTRL2_RSRVD0_MASK) /*! @} */ /*! @name DVICTRL3 - Digital Video Interface Control3 Register */ /*! @{ */ #define LCDIF_DVICTRL3_V_LINES_CNT_MASK (0x3FFU) #define LCDIF_DVICTRL3_V_LINES_CNT_SHIFT (0U) #define LCDIF_DVICTRL3_V_LINES_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V_LINES_CNT_SHIFT)) & LCDIF_DVICTRL3_V_LINES_CNT_MASK) #define LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK (0xFFC00U) #define LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT (10U) #define LCDIF_DVICTRL3_V2_BLANK_END_LINE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK) #define LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK (0x3FF00000U) #define LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT (20U) #define LCDIF_DVICTRL3_V2_BLANK_START_LINE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT)) & \ LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK) #define LCDIF_DVICTRL3_RSRVD0_MASK (0xC0000000U) #define LCDIF_DVICTRL3_RSRVD0_SHIFT (30U) #define LCDIF_DVICTRL3_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_RSRVD0_SHIFT)) & LCDIF_DVICTRL3_RSRVD0_MASK) /*! @} */ /*! @name DVICTRL4 - Digital Video Interface Control4 Register */ /*! @{ */ #define LCDIF_DVICTRL4_H_FILL_CNT_MASK (0xFFU) #define LCDIF_DVICTRL4_H_FILL_CNT_SHIFT (0U) #define LCDIF_DVICTRL4_H_FILL_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_H_FILL_CNT_SHIFT)) & LCDIF_DVICTRL4_H_FILL_CNT_MASK) #define LCDIF_DVICTRL4_CR_FILL_VALUE_MASK (0xFF00U) #define LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT (8U) #define LCDIF_DVICTRL4_CR_FILL_VALUE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CR_FILL_VALUE_MASK) #define LCDIF_DVICTRL4_CB_FILL_VALUE_MASK (0xFF0000U) #define LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT (16U) #define LCDIF_DVICTRL4_CB_FILL_VALUE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CB_FILL_VALUE_MASK) #define LCDIF_DVICTRL4_Y_FILL_VALUE_MASK (0xFF000000U) #define LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT (24U) #define LCDIF_DVICTRL4_Y_FILL_VALUE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_Y_FILL_VALUE_MASK) /*! @} */ /*! @name CSC_COEFF0 - RGB to YCbCr 4:2:2 CSC Coefficient0 Register */ /*! @{ */ #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK (0x3U) #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT (0U) /*! CSC_SUBSAMPLE_FILTER * 0b00..No filtering, simply keep every chroma value for samples numbered 2n and discard chroma values associated with * all samples numbered 2n+1. 0b01..Reserved 0b10..Chroma samples numbered 2n and 2n+1 are averaged (weights 1/2, 1/2) * and that chroma value replaces the two chroma values at 2n and 2n+1. This chroma now exists horizontally halfway * between the two luma samples. 0b11..Chroma samples numbered 2n-1, 2n, and 2n+1 are averaged (weights 1/4, 1/2, 1/4) * and that chroma value exists at the same site as the luma sample numbered 2n and the chroma samples at 2n+1 are * discarded. */ #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT)) & \ LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK) #define LCDIF_CSC_COEFF0_RSRVD0_MASK (0xFFFCU) #define LCDIF_CSC_COEFF0_RSRVD0_SHIFT (2U) #define LCDIF_CSC_COEFF0_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD0_MASK) #define LCDIF_CSC_COEFF0_C0_MASK (0x3FF0000U) #define LCDIF_CSC_COEFF0_C0_SHIFT (16U) #define LCDIF_CSC_COEFF0_C0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_C0_SHIFT)) & LCDIF_CSC_COEFF0_C0_MASK) #define LCDIF_CSC_COEFF0_RSRVD1_MASK (0xFC000000U) #define LCDIF_CSC_COEFF0_RSRVD1_SHIFT (26U) #define LCDIF_CSC_COEFF0_RSRVD1(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD1_MASK) /*! @} */ /*! @name CSC_COEFF1 - RGB to YCbCr 4:2:2 CSC Coefficient1 Register */ /*! @{ */ #define LCDIF_CSC_COEFF1_C1_MASK (0x3FFU) #define LCDIF_CSC_COEFF1_C1_SHIFT (0U) #define LCDIF_CSC_COEFF1_C1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C1_SHIFT)) & LCDIF_CSC_COEFF1_C1_MASK) #define LCDIF_CSC_COEFF1_RSRVD0_MASK (0xFC00U) #define LCDIF_CSC_COEFF1_RSRVD0_SHIFT (10U) #define LCDIF_CSC_COEFF1_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD0_MASK) #define LCDIF_CSC_COEFF1_C2_MASK (0x3FF0000U) #define LCDIF_CSC_COEFF1_C2_SHIFT (16U) #define LCDIF_CSC_COEFF1_C2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C2_SHIFT)) & LCDIF_CSC_COEFF1_C2_MASK) #define LCDIF_CSC_COEFF1_RSRVD1_MASK (0xFC000000U) #define LCDIF_CSC_COEFF1_RSRVD1_SHIFT (26U) #define LCDIF_CSC_COEFF1_RSRVD1(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD1_MASK) /*! @} */ /*! @name CSC_COEFF2 - RGB to YCbCr 4:2:2 CSC Coefficent2 Register */ /*! @{ */ #define LCDIF_CSC_COEFF2_C3_MASK (0x3FFU) #define LCDIF_CSC_COEFF2_C3_SHIFT (0U) #define LCDIF_CSC_COEFF2_C3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C3_SHIFT)) & LCDIF_CSC_COEFF2_C3_MASK) #define LCDIF_CSC_COEFF2_RSRVD0_MASK (0xFC00U) #define LCDIF_CSC_COEFF2_RSRVD0_SHIFT (10U) #define LCDIF_CSC_COEFF2_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD0_MASK) #define LCDIF_CSC_COEFF2_C4_MASK (0x3FF0000U) #define LCDIF_CSC_COEFF2_C4_SHIFT (16U) #define LCDIF_CSC_COEFF2_C4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C4_SHIFT)) & LCDIF_CSC_COEFF2_C4_MASK) #define LCDIF_CSC_COEFF2_RSRVD1_MASK (0xFC000000U) #define LCDIF_CSC_COEFF2_RSRVD1_SHIFT (26U) #define LCDIF_CSC_COEFF2_RSRVD1(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD1_MASK) /*! @} */ /*! @name CSC_COEFF3 - RGB to YCbCr 4:2:2 CSC Coefficient3 Register */ /*! @{ */ #define LCDIF_CSC_COEFF3_C5_MASK (0x3FFU) #define LCDIF_CSC_COEFF3_C5_SHIFT (0U) #define LCDIF_CSC_COEFF3_C5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C5_SHIFT)) & LCDIF_CSC_COEFF3_C5_MASK) #define LCDIF_CSC_COEFF3_RSRVD0_MASK (0xFC00U) #define LCDIF_CSC_COEFF3_RSRVD0_SHIFT (10U) #define LCDIF_CSC_COEFF3_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD0_MASK) #define LCDIF_CSC_COEFF3_C6_MASK (0x3FF0000U) #define LCDIF_CSC_COEFF3_C6_SHIFT (16U) #define LCDIF_CSC_COEFF3_C6(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C6_SHIFT)) & LCDIF_CSC_COEFF3_C6_MASK) #define LCDIF_CSC_COEFF3_RSRVD1_MASK (0xFC000000U) #define LCDIF_CSC_COEFF3_RSRVD1_SHIFT (26U) #define LCDIF_CSC_COEFF3_RSRVD1(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD1_MASK) /*! @} */ /*! @name CSC_COEFF4 - RGB to YCbCr 4:2:2 CSC Coefficient4 Register */ /*! @{ */ #define LCDIF_CSC_COEFF4_C7_MASK (0x3FFU) #define LCDIF_CSC_COEFF4_C7_SHIFT (0U) #define LCDIF_CSC_COEFF4_C7(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C7_SHIFT)) & LCDIF_CSC_COEFF4_C7_MASK) #define LCDIF_CSC_COEFF4_RSRVD0_MASK (0xFC00U) #define LCDIF_CSC_COEFF4_RSRVD0_SHIFT (10U) #define LCDIF_CSC_COEFF4_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD0_MASK) #define LCDIF_CSC_COEFF4_C8_MASK (0x3FF0000U) #define LCDIF_CSC_COEFF4_C8_SHIFT (16U) #define LCDIF_CSC_COEFF4_C8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C8_SHIFT)) & LCDIF_CSC_COEFF4_C8_MASK) #define LCDIF_CSC_COEFF4_RSRVD1_MASK (0xFC000000U) #define LCDIF_CSC_COEFF4_RSRVD1_SHIFT (26U) #define LCDIF_CSC_COEFF4_RSRVD1(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD1_MASK) /*! @} */ /*! @name CSC_OFFSET - RGB to YCbCr 4:2:2 CSC Offset Register */ /*! @{ */ #define LCDIF_CSC_OFFSET_Y_OFFSET_MASK (0x1FFU) #define LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT (0U) #define LCDIF_CSC_OFFSET_Y_OFFSET(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_Y_OFFSET_MASK) #define LCDIF_CSC_OFFSET_RSRVD0_MASK (0xFE00U) #define LCDIF_CSC_OFFSET_RSRVD0_SHIFT (9U) #define LCDIF_CSC_OFFSET_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD0_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD0_MASK) #define LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK (0x1FF0000U) #define LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT (16U) #define LCDIF_CSC_OFFSET_CBCR_OFFSET(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK) #define LCDIF_CSC_OFFSET_RSRVD1_MASK (0xFE000000U) #define LCDIF_CSC_OFFSET_RSRVD1_SHIFT (25U) #define LCDIF_CSC_OFFSET_RSRVD1(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD1_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD1_MASK) /*! @} */ /*! @name CSC_LIMIT - RGB to YCbCr 4:2:2 CSC Limit Register */ /*! @{ */ #define LCDIF_CSC_LIMIT_Y_MAX_MASK (0xFFU) #define LCDIF_CSC_LIMIT_Y_MAX_SHIFT (0U) #define LCDIF_CSC_LIMIT_Y_MAX(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MAX_SHIFT)) & LCDIF_CSC_LIMIT_Y_MAX_MASK) #define LCDIF_CSC_LIMIT_Y_MIN_MASK (0xFF00U) #define LCDIF_CSC_LIMIT_Y_MIN_SHIFT (8U) #define LCDIF_CSC_LIMIT_Y_MIN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MIN_SHIFT)) & LCDIF_CSC_LIMIT_Y_MIN_MASK) #define LCDIF_CSC_LIMIT_CBCR_MAX_MASK (0xFF0000U) #define LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT (16U) #define LCDIF_CSC_LIMIT_CBCR_MAX(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MAX_MASK) #define LCDIF_CSC_LIMIT_CBCR_MIN_MASK (0xFF000000U) #define LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT (24U) #define LCDIF_CSC_LIMIT_CBCR_MIN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MIN_MASK) /*! @} */ /*! @name DATA - LCD Interface Data Register */ /*! @{ */ #define LCDIF_DATA_DATA_ZERO_MASK (0xFFU) #define LCDIF_DATA_DATA_ZERO_SHIFT (0U) #define LCDIF_DATA_DATA_ZERO(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ZERO_SHIFT)) & LCDIF_DATA_DATA_ZERO_MASK) #define LCDIF_DATA_DATA_ONE_MASK (0xFF00U) #define LCDIF_DATA_DATA_ONE_SHIFT (8U) #define LCDIF_DATA_DATA_ONE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ONE_SHIFT)) & LCDIF_DATA_DATA_ONE_MASK) #define LCDIF_DATA_DATA_TWO_MASK (0xFF0000U) #define LCDIF_DATA_DATA_TWO_SHIFT (16U) #define LCDIF_DATA_DATA_TWO(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_TWO_SHIFT)) & LCDIF_DATA_DATA_TWO_MASK) #define LCDIF_DATA_DATA_THREE_MASK (0xFF000000U) #define LCDIF_DATA_DATA_THREE_SHIFT (24U) #define LCDIF_DATA_DATA_THREE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_THREE_SHIFT)) & LCDIF_DATA_DATA_THREE_MASK) /*! @} */ /*! @name BM_ERROR_STAT - Bus Master Error Status Register */ /*! @{ */ #define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) #define LCDIF_BM_ERROR_STAT_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) /*! @} */ /*! @name CRC_STAT - CRC Status Register */ /*! @{ */ #define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU) #define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) #define LCDIF_CRC_STAT_CRC_VALUE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) /*! @} */ /*! @name STAT - LCD Interface Status Register */ /*! @{ */ #define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU) #define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) #define LCDIF_STAT_LFIFO_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) #define LCDIF_STAT_RSRVD0_MASK (0xFFFE00U) #define LCDIF_STAT_RSRVD0_SHIFT (9U) #define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK) #define LCDIF_STAT_DVI_CURRENT_FIELD_MASK (0x1000000U) #define LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT (24U) #define LCDIF_STAT_DVI_CURRENT_FIELD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT)) & LCDIF_STAT_DVI_CURRENT_FIELD_MASK) #define LCDIF_STAT_BUSY_MASK (0x2000000U) #define LCDIF_STAT_BUSY_SHIFT (25U) #define LCDIF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_BUSY_SHIFT)) & LCDIF_STAT_BUSY_MASK) #define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U) #define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U) #define LCDIF_STAT_TXFIFO_EMPTY(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK) #define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U) #define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U) #define LCDIF_STAT_TXFIFO_FULL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK) #define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U) #define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U) #define LCDIF_STAT_LFIFO_EMPTY(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK) #define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U) #define LCDIF_STAT_LFIFO_FULL_SHIFT (29U) #define LCDIF_STAT_LFIFO_FULL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK) #define LCDIF_STAT_PRESENT_MASK (0x80000000U) #define LCDIF_STAT_PRESENT_SHIFT (31U) #define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) /*! @} */ /*! @name THRES - LCDIF Threshold Register */ /*! @{ */ #define LCDIF_THRES_PANIC_MASK (0x1FFU) #define LCDIF_THRES_PANIC_SHIFT (0U) #define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK) #define LCDIF_THRES_RSRVD1_MASK (0xFE00U) #define LCDIF_THRES_RSRVD1_SHIFT (9U) #define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK) #define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U) #define LCDIF_THRES_FASTCLOCK_SHIFT (16U) #define LCDIF_THRES_FASTCLOCK(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK) #define LCDIF_THRES_RSRVD2_MASK (0xFE000000U) #define LCDIF_THRES_RSRVD2_SHIFT (25U) #define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK) /*! @} */ /*! @name AS_CTRL - LCDIF AS Buffer Control Register */ /*! @{ */ #define LCDIF_AS_CTRL_AS_ENABLE_MASK (0x1U) #define LCDIF_AS_CTRL_AS_ENABLE_SHIFT (0U) #define LCDIF_AS_CTRL_AS_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_AS_ENABLE_SHIFT)) & LCDIF_AS_CTRL_AS_ENABLE_MASK) #define LCDIF_AS_CTRL_ALPHA_CTRL_MASK (0x6U) #define LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT (1U) #define LCDIF_AS_CTRL_ALPHA_CTRL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT)) & LCDIF_AS_CTRL_ALPHA_CTRL_MASK) #define LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) #define LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) #define LCDIF_AS_CTRL_ENABLE_COLORKEY(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK) #define LCDIF_AS_CTRL_FORMAT_MASK (0xF0U) #define LCDIF_AS_CTRL_FORMAT_SHIFT (4U) #define LCDIF_AS_CTRL_FORMAT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_FORMAT_SHIFT)) & LCDIF_AS_CTRL_FORMAT_MASK) #define LCDIF_AS_CTRL_ALPHA_MASK (0xFF00U) #define LCDIF_AS_CTRL_ALPHA_SHIFT (8U) #define LCDIF_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_SHIFT)) & LCDIF_AS_CTRL_ALPHA_MASK) #define LCDIF_AS_CTRL_ROP_MASK (0xF0000U) #define LCDIF_AS_CTRL_ROP_SHIFT (16U) #define LCDIF_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ROP_SHIFT)) & LCDIF_AS_CTRL_ROP_MASK) #define LCDIF_AS_CTRL_ALPHA_INVERT_MASK (0x100000U) #define LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT (20U) #define LCDIF_AS_CTRL_ALPHA_INVERT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT)) & LCDIF_AS_CTRL_ALPHA_INVERT_MASK) #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK (0x600000U) #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT (21U) #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_AS_CTRL_PS_DISABLE_MASK (0x800000U) #define LCDIF_AS_CTRL_PS_DISABLE_SHIFT (23U) #define LCDIF_AS_CTRL_PS_DISABLE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_PS_DISABLE_SHIFT)) & LCDIF_AS_CTRL_PS_DISABLE_MASK) #define LCDIF_AS_CTRL_RVDS1_MASK (0x7000000U) #define LCDIF_AS_CTRL_RVDS1_SHIFT (24U) #define LCDIF_AS_CTRL_RVDS1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_RVDS1_SHIFT)) & LCDIF_AS_CTRL_RVDS1_MASK) #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK (0x8000000U) #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT (27U) #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK) #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK (0x10000000U) #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT (28U) #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK) #define LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK (0x20000000U) #define LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT (29U) #define LCDIF_AS_CTRL_CSI_VSYNC_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK) #define LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK (0x40000000U) #define LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT (30U) #define LCDIF_AS_CTRL_CSI_VSYNC_POL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK) #define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK (0x80000000U) #define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT (31U) #define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK) /*! @} */ /*! @name AS_BUF - Alpha Surface Buffer Pointer */ /*! @{ */ #define LCDIF_AS_BUF_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_AS_BUF_ADDR_SHIFT (0U) #define LCDIF_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_BUF_ADDR_SHIFT)) & LCDIF_AS_BUF_ADDR_MASK) /*! @} */ /*! @name AS_NEXT_BUF - */ /*! @{ */ #define LCDIF_AS_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_AS_NEXT_BUF_ADDR_SHIFT (0U) #define LCDIF_AS_NEXT_BUF_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_NEXT_BUF_ADDR_SHIFT)) & LCDIF_AS_NEXT_BUF_ADDR_MASK) /*! @} */ /*! @name AS_CLRKEYLOW - LCDIF Overlay Color Key Low */ /*! @{ */ #define LCDIF_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) #define LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT (0U) #define LCDIF_AS_CLRKEYLOW_PIXEL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYLOW_PIXEL_MASK) #define LCDIF_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) #define LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT (24U) #define LCDIF_AS_CLRKEYLOW_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYLOW_RSVD1_MASK) /*! @} */ /*! @name AS_CLRKEYHIGH - LCDIF Overlay Color Key High */ /*! @{ */ #define LCDIF_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) #define LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT (0U) #define LCDIF_AS_CLRKEYHIGH_PIXEL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYHIGH_PIXEL_MASK) #define LCDIF_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) #define LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT (24U) #define LCDIF_AS_CLRKEYHIGH_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYHIGH_RSVD1_MASK) /*! @} */ /*! @name SYNC_DELAY - LCD working insync mode with CSI for VSYNC delay */ /*! @{ */ #define LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK (0xFFFFU) #define LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT (0U) #define LCDIF_SYNC_DELAY_H_COUNT_DELAY(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK) #define LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK (0xFFFF0000U) #define LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT (16U) #define LCDIF_SYNC_DELAY_V_COUNT_DELAY(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK) /*! @} */ /*! @name PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register */ /*! @{ */ #define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL0_FD_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK) #define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U) #define LCDIF_PIGEONCTRL0_LD_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK) /*! @} */ /*! @name PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register */ /*! @{ */ #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK) #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U) #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK) /*! @} */ /*! @name PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register */ /*! @{ */ #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK) #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U) #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK) /*! @} */ /*! @name PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register */ /*! @{ */ #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK) #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U) #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK) /*! @} */ /*! @name PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register */ /*! @{ */ #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & \ LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK) #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U) #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & \ LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK) /*! @} */ /*! @name PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register */ /*! @{ */ #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & \ LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & \ LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK) /*! @} */ /*! @name PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register */ /*! @{ */ #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & \ LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & \ LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK) /*! @} */ /*! @name PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register */ /*! @{ */ #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & \ LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & \ LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK) /*! @} */ /*! @name PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register */ /*! @{ */ #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U) #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U) #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK) #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U) #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U) #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK) /*! @} */ /*! @name PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register */ /*! @{ */ #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U) #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U) #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & \ LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK) #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U) #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U) #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & \ LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK) /*! @} */ /*! @name PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register */ /*! @{ */ #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & \ LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & \ LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK) /*! @} */ /*! @name PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register */ /*! @{ */ #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & \ LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & \ LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK) /*! @} */ /*! @name PIGEON_n_0 - Panel Interface Signal Generator Register */ /*! @{ */ #define LCDIF_PIGEON_n_0_EN_MASK (0x1U) #define LCDIF_PIGEON_n_0_EN_SHIFT (0U) #define LCDIF_PIGEON_n_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_0_EN_SHIFT)) & LCDIF_PIGEON_n_0_EN_MASK) #define LCDIF_PIGEON_n_0_POL_MASK (0x2U) #define LCDIF_PIGEON_n_0_POL_SHIFT (1U) /*! POL * 0b0..Normal Signal (Active high) * 0b1..Inverted signal (Active low) */ #define LCDIF_PIGEON_n_0_POL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_0_POL_SHIFT)) & LCDIF_PIGEON_n_0_POL_MASK) #define LCDIF_PIGEON_n_0_INC_SEL_MASK (0xCU) #define LCDIF_PIGEON_n_0_INC_SEL_SHIFT (2U) /*! INC_SEL * 0b00..pclk * 0b01..Line start pulse * 0b10..Frame start pulse * 0b11..Use another signal as tick event */ #define LCDIF_PIGEON_n_0_INC_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_n_0_INC_SEL_MASK) #define LCDIF_PIGEON_n_0_OFFSET_MASK (0xF0U) #define LCDIF_PIGEON_n_0_OFFSET_SHIFT (4U) #define LCDIF_PIGEON_n_0_OFFSET(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_0_OFFSET_SHIFT)) & LCDIF_PIGEON_n_0_OFFSET_MASK) #define LCDIF_PIGEON_n_0_MASK_CNT_SEL_MASK (0xF00U) #define LCDIF_PIGEON_n_0_MASK_CNT_SEL_SHIFT (8U) /*! MASK_CNT_SEL * 0b0000..pclk counter within one hscan state * 0b0001..pclk cycle within one hscan state * 0b0010..line counter within one vscan state * 0b0011..line cycle within one vscan state * 0b0100..frame counter * 0b0101..frame cycle * 0b0110..horizontal counter (pclk counter within one line ) * 0b0111..vertical counter (line counter within one frame) */ #define LCDIF_PIGEON_n_0_MASK_CNT_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_n_0_MASK_CNT_SEL_MASK) #define LCDIF_PIGEON_n_0_MASK_CNT_MASK (0xFFF000U) #define LCDIF_PIGEON_n_0_MASK_CNT_SHIFT (12U) #define LCDIF_PIGEON_n_0_MASK_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_n_0_MASK_CNT_MASK) #define LCDIF_PIGEON_n_0_STATE_MASK_MASK (0xFF000000U) #define LCDIF_PIGEON_n_0_STATE_MASK_SHIFT (24U) /*! STATE_MASK * 0b00000001..FRAME SYNC * 0b00000010..FRAME BEGIN * 0b00000100..FRAME DATA * 0b00001000..FRAME END * 0b00010000..LINE SYNC * 0b00100000..LINE BEGIN * 0b01000000..LINE DATA * 0b10000000..LINE END */ #define LCDIF_PIGEON_n_0_STATE_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_n_0_STATE_MASK_MASK) /*! @} */ /* The count of LCDIF_PIGEON_n_0 */ #define LCDIF_PIGEON_n_0_COUNT (12U) /*! @name PIGEON_n_1 - Panel Interface Signal Generator Register */ /*! @{ */ #define LCDIF_PIGEON_n_1_SET_CNT_MASK (0xFFFFU) #define LCDIF_PIGEON_n_1_SET_CNT_SHIFT (0U) /*! SET_CNT * 0b0000000000000000..Start as active */ #define LCDIF_PIGEON_n_1_SET_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_n_1_SET_CNT_MASK) #define LCDIF_PIGEON_n_1_CLR_CNT_MASK (0xFFFF0000U) #define LCDIF_PIGEON_n_1_CLR_CNT_SHIFT (16U) /*! CLR_CNT * 0b0000000000000000..Keep active until mask off */ #define LCDIF_PIGEON_n_1_CLR_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_n_1_CLR_CNT_MASK) /*! @} */ /* The count of LCDIF_PIGEON_n_1 */ #define LCDIF_PIGEON_n_1_COUNT (12U) /*! @name PIGEON_n_2 - Panel Interface Signal Generator Register */ /*! @{ */ #define LCDIF_PIGEON_n_2_SIG_LOGIC_MASK (0xFU) #define LCDIF_PIGEON_n_2_SIG_LOGIC_SHIFT (0U) /*! SIG_LOGIC * 0b0000..No logic operation * 0b0001..sigout = sig_another AND this_sig * 0b0010..sigout = sig_another OR this_sig * 0b0011..mask = sig_another AND other_masks */ #define LCDIF_PIGEON_n_2_SIG_LOGIC(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_n_2_SIG_LOGIC_MASK) #define LCDIF_PIGEON_n_2_SIG_ANOTHER_MASK (0x1F0U) #define LCDIF_PIGEON_n_2_SIG_ANOTHER_SHIFT (4U) /*! SIG_ANOTHER * 0b00000..Keep active until mask off */ #define LCDIF_PIGEON_n_2_SIG_ANOTHER(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_n_2_SIG_ANOTHER_MASK) #define LCDIF_PIGEON_n_2_RSVD_MASK (0xFFFFFE00U) #define LCDIF_PIGEON_n_2_RSVD_SHIFT (9U) #define LCDIF_PIGEON_n_2_RSVD(x) \ (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_2_RSVD_SHIFT)) & LCDIF_PIGEON_n_2_RSVD_MASK) /*! @} */ /* The count of LCDIF_PIGEON_n_2 */ #define LCDIF_PIGEON_n_2_COUNT (12U) /*! * @} */ /* end of group LCDIF_Register_Masks */ /* LCDIF - Peripheral instance base addresses */ /** Peripheral LCDIF base address */ #define LCDIF_BASE (0x32E00000u) /** Peripheral LCDIF base pointer */ #define LCDIF ((LCDIF_Type *)LCDIF_BASE) /** Array initializer of LCDIF peripheral base addresses */ #define LCDIF_BASE_ADDRS \ { \ LCDIF_BASE \ } /** Array initializer of LCDIF peripheral base pointers */ #define LCDIF_BASE_PTRS \ { \ LCDIF \ } /*! * @} */ /* end of group LCDIF_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MIPI_CSI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_CSI_Peripheral_Access_Layer MIPI_CSI Peripheral Access Layer * @{ */ /** MIPI_CSI - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t CSIS_COMMON_CTRL; /**< CSIS Common Control Register, offset: 0x4 */ __IO uint32_t CSIS_CLOCK_CTRL; /**< CSIS Clock Control Register, offset: 0x8 */ uint8_t RESERVED_1[4]; __IO uint32_t INTERRUPT_MASK_0; /**< Interrupt mask register 0, offset: 0x10 */ __IO uint32_t INTERRUPT_SOURCE_0; /**< Interrupt source register 0, offset: 0x14 */ __IO uint32_t INTERRUPT_MASK_1; /**< Interrupt mask register 1, offset: 0x18 */ __IO uint32_t INTERRUPT_SOURCE_1; /**< Interrupt source register 1, offset: 0x1C */ __IO uint32_t DPHY_STATUS; /**< D-PHY status register, offset: 0x20 */ __IO uint32_t DPHY_COMMON_CTRL; /**< D-PHY common control register, offset: 0x24 */ uint8_t RESERVED_2[8]; __IO uint32_t DPHY_MASTER_SLAVE_CTRL_LOW; /**< D-PHY Master and Slave Control register Low, offset: 0x30 */ __IO uint32_t DPHY_MASTER_SLAVE_CTRL_HIGH; /**< D-PHY Master and Slave Control register HIGH, offset: 0x34 */ __IO uint32_t DPHY_SLAVE_CTRL_LOW; /**< D-PHY Slave Control register Low, offset: 0x38 */ __IO uint32_t DPHY_SLAVE_CTRL_HIGH; /**< D-PHY Slave Control register HIGH, offset: 0x3C */ struct { /* offset: 0x40, array step: 0x10 */ __IO uint32_t ISP_CONFIG; /**< ISP Configuration Register, array offset: 0x40, array step: 0x10 */ __IO uint32_t ISP_RESOLUTION; /**< ISP Resolution Register, array offset: 0x44, array step: 0x10 */ __IO uint32_t ISP_SYNC; /**< ISP SYNC Register, array offset: 0x48, array step: 0x10 */ uint8_t RESERVED_0[4]; } ISP_CONFIGn[4]; struct { /* offset: 0x80, array step: 0x10 */ __I uint32_t SHADOW_CONFIG; /**< Shadow Configuration Register, array offset: 0x80, array step: 0x10 */ __I uint32_t SHADOW_RESOLUTION; /**< Shadow Resolution Register, array offset: 0x84, array step: 0x10 */ __I uint32_t SHADOW_SYNC; /**< Shadow SYNC Register, array offset: 0x88, array step: 0x10 */ uint8_t RESERVED_0[4]; } SHADOW_CONFIGn[4]; uint8_t RESERVED_3[64]; __IO uint32_t FRAME_COUNTER[4]; /**< Frame Counter, array offset: 0x100, array step: 0x4 */ __IO uint32_t LINE_INTERRUPT_RATIO[4]; /**< Line Interrupt Ratio, array offset: 0x110, array step: 0x4 */ } MIPI_CSI_Type; /* ---------------------------------------------------------------------------- -- MIPI_CSI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_CSI_Register_Masks MIPI_CSI Register Masks * @{ */ /*! @name CSIS_COMMON_CTRL - CSIS Common Control Register */ /*! @{ */ #define MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN_MASK (0x1U) #define MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN_SHIFT (0U) /*! CSI_EN * 0b0..Disable * 0b1..Enable */ #define MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN_SHIFT)) & MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN_MASK) #define MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET_MASK (0x2U) #define MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET_SHIFT (1U) /*! SW_RESET - Software reset * 0b0..Ready * 0b1..Reset */ #define MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET_SHIFT)) & \ MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET_MASK) #define MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER_MASK (0x300U) #define MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER_SHIFT (8U) /*! LANE_NUMBER * 0b00..1 data lane * 0b01..2 data lane * 0b10..3 data lane * 0b11..4 data lane */ #define MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER_SHIFT)) & \ MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER_MASK) #define MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW_MASK (0xF0000U) #define MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW_SHIFT (16U) #define MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW_SHIFT)) & \ MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW_MASK) /*! @} */ /*! @name CSIS_CLOCK_CTRL - CSIS Clock Control Register */ /*! @{ */ #define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN_MASK (0xF0U) #define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN_SHIFT (4U) /*! CLKGATE_EN * 0b0000..Pixel clock is always alive * 0b0001..Pixel clock is alive during the interval of frame [7] CH3 [6] CH2 [5] CH1 [4] CH0 (Refer 2.9) */ #define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN_SHIFT)) & \ MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN_MASK) #define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL_MASK (0xFFFF0000U) #define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL_SHIFT (16U) #define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL_SHIFT)) & \ MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL_MASK) /*! @} */ /*! @name INTERRUPT_MASK_0 - Interrupt mask register 0 */ /*! @{ */ #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID_MASK (0x1U) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID_SHIFT (0U) /*! MSK_ERR_ID - Unknown ID error * 0b0..Disable (masked) * 0b1..Enable (unmasked) */ #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID_SHIFT)) & \ MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID_MASK) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC_MASK (0x2U) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC_SHIFT (1U) /*! MSK_ERR_CRC - CRC error * 0b0..Disable (masked) * 0b1..Enable (unmasked) */ #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC_SHIFT)) & \ MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC_MASK) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC_MASK (0x4U) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC_SHIFT (2U) /*! MSK_ERR_ECC - ECC error * 0b0..Disable (masked) * 0b1..Enable (unmasked) */ #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC_SHIFT)) & \ MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC_MASK) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG_MASK (0x8U) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG_SHIFT (3U) /*! MSK_ERR_WRONG_CFG - Wrong configuration * 0b0..Disable (masked) * 0b1..Enable (unmasked) */ #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG_SHIFT)) & \ MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG_MASK) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER_MASK (0x10U) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER_SHIFT (4U) /*! MSK_ERR_OVER - Image FIFO overflow interrupt * 0b0..Disable (masked) * 0b1..Enable (unmasked) */ #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER_SHIFT)) & \ MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER_MASK) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE_MASK (0xF00U) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE_SHIFT (8U) /*! MSK_ERR_LOST_FE - Lost of Frame End packet, [CH3,CH2,CH1,CH0] * 0b0000..Disable (masked) * 0b0001..Enable (unmasked) */ #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE_SHIFT)) & \ MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE_MASK) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS_MASK (0xF000U) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS_SHIFT (12U) /*! MSK_ERR_LOST_FS - Lost of Frame Start packet, [CH3,CH2,CH1,CH0] * 0b0000..Disable (masked) * 0b0001..Enable (unmasked) */ #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS_SHIFT)) & \ MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS_MASK) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS_MASK (0xF0000U) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS_SHIFT (16U) /*! MSK_ERR_SOT_HS - Start of transmission error [Lane3, Lane2, Lane1, Lane0] * 0b0000..Disable (masked) * 0b0001..Enable (unmasked) */ #define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS_SHIFT)) & \ MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS_MASK) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND_MASK (0xF00000U) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND_SHIFT (20U) /*! MSK_FRAMEEND - FE packet is received, [CH3,CH2,CH1,CH0] * 0b0000..Disable (masked) * 0b0001..Enable (unmasked) */ #define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND_SHIFT)) & \ MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND_MASK) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART_MASK (0xF000000U) #define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART_SHIFT (24U) /*! MSK_FRAMESTART - FS packet is received, [CH3,CH2,CH1,CH0] * 0b0000..Disable (masked) * 0b0001..Enable (unmasked) */ #define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART_SHIFT)) & \ MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART_MASK) /*! @} */ /*! @name INTERRUPT_SOURCE_0 - Interrupt source register 0 */ /*! @{ */ #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID_MASK (0x1U) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID_SHIFT (0U) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID_SHIFT)) & \ MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID_MASK) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC_MASK (0x2U) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC_SHIFT (1U) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC_SHIFT)) & \ MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC_MASK) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC_MASK (0x4U) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC_SHIFT (2U) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC_SHIFT)) & \ MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC_MASK) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG_MASK (0x8U) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG_SHIFT (3U) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG_SHIFT)) & \ MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG_MASK) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER_MASK (0x10U) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER_SHIFT (4U) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER_SHIFT)) & \ MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER_MASK) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE_MASK (0xF00U) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE_SHIFT (8U) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE_SHIFT)) & \ MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE_MASK) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS_MASK (0xF000U) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS_SHIFT (12U) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS_SHIFT)) & \ MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS_MASK) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS_MASK (0xF0000U) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS_SHIFT (16U) #define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS_SHIFT)) & \ MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS_MASK) #define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END_MASK (0xF00000U) #define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END_SHIFT (20U) #define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END_SHIFT)) & \ MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END_MASK) #define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START_MASK (0xF000000U) #define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START_SHIFT (24U) #define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START_SHIFT)) & \ MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START_MASK) /*! @} */ /*! @name INTERRUPT_MASK_1 - Interrupt mask register 1 */ /*! @{ */ #define MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END_MASK (0xFU) #define MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END_SHIFT (0U) #define MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END_SHIFT)) & \ MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END_MASK) /*! @} */ /*! @name INTERRUPT_SOURCE_1 - Interrupt source register 1 */ /*! @{ */ #define MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END_MASK (0xFU) #define MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END_SHIFT (0U) #define MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END_SHIFT)) & \ MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END_MASK) /*! @} */ /*! @name DPHY_STATUS - D-PHY status register */ /*! @{ */ #define MIPI_CSI_DPHY_STATUS_STOPSTATECLK_MASK (0x1U) #define MIPI_CSI_DPHY_STATUS_STOPSTATECLK_SHIFT (0U) /*! STOPSTATECLK * 0b0..Not Stop state * 0b1..Stop state */ #define MIPI_CSI_DPHY_STATUS_STOPSTATECLK(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_STATUS_STOPSTATECLK_SHIFT)) & MIPI_CSI_DPHY_STATUS_STOPSTATECLK_MASK) #define MIPI_CSI_DPHY_STATUS_ULPSCLK_MASK (0x2U) #define MIPI_CSI_DPHY_STATUS_ULPSCLK_SHIFT (1U) /*! ULPSCLK * 0b0..Not ULPS * 0b1..ULPS */ #define MIPI_CSI_DPHY_STATUS_ULPSCLK(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_STATUS_ULPSCLK_SHIFT)) & MIPI_CSI_DPHY_STATUS_ULPSCLK_MASK) #define MIPI_CSI_DPHY_STATUS_STOPSTATEDAT_MASK (0xF0U) #define MIPI_CSI_DPHY_STATUS_STOPSTATEDAT_SHIFT (4U) /*! STOPSTATEDAT - Data lane [3:0] is in Stop State * 0b0000..Not Stop state * 0b0001..Stop state */ #define MIPI_CSI_DPHY_STATUS_STOPSTATEDAT(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_STATUS_STOPSTATEDAT_SHIFT)) & MIPI_CSI_DPHY_STATUS_STOPSTATEDAT_MASK) #define MIPI_CSI_DPHY_STATUS_ULPSDAT_MASK (0xF00U) #define MIPI_CSI_DPHY_STATUS_ULPSDAT_SHIFT (8U) /*! ULPSDAT - Data lane [3:0] is in ULPS * 0b0000..Not ULPS * 0b0001..ULPS */ #define MIPI_CSI_DPHY_STATUS_ULPSDAT(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_STATUS_ULPSDAT_SHIFT)) & MIPI_CSI_DPHY_STATUS_ULPSDAT_MASK) /*! @} */ /*! @name DPHY_COMMON_CTRL - D-PHY common control register */ /*! @{ */ #define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK_MASK (0x1U) #define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK_SHIFT (0U) /*! ENABLE_CLK * 0b0..Disable * 0b1..Enable */ #define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK_SHIFT)) & \ MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK_MASK) #define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT_MASK (0x1EU) #define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT_SHIFT (1U) /*! ENABLE_DAT - D-PHY enable * 0b0000..Disable * 0b0001..Enable */ #define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT_SHIFT)) & \ MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT_MASK) #define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT_MASK (0x20U) #define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT_SHIFT (5U) /*! S_DPDN_SWAP_DAT - Swapping Dp and Dn channel of data lanes. * 0b0..Default * 0b1..Swapped */ #define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT_SHIFT)) & \ MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT_MASK) #define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK_MASK (0x40U) #define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK_SHIFT (6U) /*! S_DPDN_SWAP_CLK * 0b0..Default * 0b1..Swapped */ #define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK_SHIFT)) & \ MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK_MASK) #define MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL_MASK (0xC00000U) #define MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL_SHIFT (22U) #define MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL_SHIFT)) & \ MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL_MASK) #define MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE_MASK (0xFF000000U) #define MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE_SHIFT (24U) #define MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE_SHIFT)) & \ MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE_MASK) /*! @} */ /*! @name DPHY_MASTER_SLAVE_CTRL_LOW - D-PHY Master and Slave Control register Low */ /*! @{ */ #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL_MASK (0xFFFFFFFFU) #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL_SHIFT (0U) #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL_SHIFT)) & \ MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL_MASK) /*! @} */ /*! @name DPHY_MASTER_SLAVE_CTRL_HIGH - D-PHY Master and Slave Control register HIGH */ /*! @{ */ #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_B_DPHYCTRL_MASK (0xFFFFFFFFU) #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_B_DPHYCTRL_SHIFT (0U) #define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_B_DPHYCTRL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_B_DPHYCTRL_SHIFT)) & \ MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_B_DPHYCTRL_MASK) /*! @} */ /*! @name DPHY_SLAVE_CTRL_LOW - D-PHY Slave Control register Low */ /*! @{ */ #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_S_DPHYCTRL_MASK (0xFFFFFFFFU) #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_S_DPHYCTRL_SHIFT (0U) #define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_S_DPHYCTRL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_S_DPHYCTRL_SHIFT)) & \ MIPI_CSI_DPHY_SLAVE_CTRL_LOW_S_DPHYCTRL_MASK) /*! @} */ /*! @name DPHY_SLAVE_CTRL_HIGH - D-PHY Slave Control register HIGH */ /*! @{ */ #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_S_DPHYCTRL_MASK (0xFFFFFFFFU) #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_S_DPHYCTRL_SHIFT (0U) #define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_S_DPHYCTRL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_S_DPHYCTRL_SHIFT)) & \ MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_S_DPHYCTRL_MASK) /*! @} */ /*! @name ISP_CONFIG - ISP Configuration Register */ /*! @{ */ #define MIPI_CSI_ISP_CONFIG_DATAFORMAT_MASK (0xFCU) #define MIPI_CSI_ISP_CONFIG_DATAFORMAT_SHIFT (2U) #define MIPI_CSI_ISP_CONFIG_DATAFORMAT(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_CONFIG_DATAFORMAT_SHIFT)) & MIPI_CSI_ISP_CONFIG_DATAFORMAT_MASK) #define MIPI_CSI_ISP_CONFIG_RGB_SWAP_MASK (0x400U) #define MIPI_CSI_ISP_CONFIG_RGB_SWAP_SHIFT (10U) /*! RGB_SWAP * 0b0..MSB is R and LSB is B * 0b1..MSB is B and LSB is R (swapped) */ #define MIPI_CSI_ISP_CONFIG_RGB_SWAP(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_CONFIG_RGB_SWAP_SHIFT)) & MIPI_CSI_ISP_CONFIG_RGB_SWAP_MASK) #define MIPI_CSI_ISP_CONFIG_PARALLEL_MASK (0x800U) #define MIPI_CSI_ISP_CONFIG_PARALLEL_SHIFT (11U) /*! PARALLEL - Output bus width of CH0 is 32 bits. * 0b0..Normal output * 0b1..32bit data alignment */ #define MIPI_CSI_ISP_CONFIG_PARALLEL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_CONFIG_PARALLEL_SHIFT)) & MIPI_CSI_ISP_CONFIG_PARALLEL_MASK) #define MIPI_CSI_ISP_CONFIG_PIXEL_MODE_MASK (0x3000U) #define MIPI_CSI_ISP_CONFIG_PIXEL_MODE_SHIFT (12U) #define MIPI_CSI_ISP_CONFIG_PIXEL_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_CONFIG_PIXEL_MODE_SHIFT)) & MIPI_CSI_ISP_CONFIG_PIXEL_MODE_MASK) /*! @} */ /* The count of MIPI_CSI_ISP_CONFIG */ #define MIPI_CSI_ISP_CONFIG_COUNT (4U) /*! @name ISP_RESOLUTION - ISP Resolution Register */ /*! @{ */ #define MIPI_CSI_ISP_RESOLUTION_HRESOL_MASK (0xFFFFU) #define MIPI_CSI_ISP_RESOLUTION_HRESOL_SHIFT (0U) #define MIPI_CSI_ISP_RESOLUTION_HRESOL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_RESOLUTION_HRESOL_SHIFT)) & MIPI_CSI_ISP_RESOLUTION_HRESOL_MASK) #define MIPI_CSI_ISP_RESOLUTION_VRESOL_MASK (0xFFFF0000U) #define MIPI_CSI_ISP_RESOLUTION_VRESOL_SHIFT (16U) #define MIPI_CSI_ISP_RESOLUTION_VRESOL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_RESOLUTION_VRESOL_SHIFT)) & MIPI_CSI_ISP_RESOLUTION_VRESOL_MASK) /*! @} */ /* The count of MIPI_CSI_ISP_RESOLUTION */ #define MIPI_CSI_ISP_RESOLUTION_COUNT (4U) /*! @name ISP_SYNC - ISP SYNC Register */ /*! @{ */ #define MIPI_CSI_ISP_SYNC_HSYNC_LINTV_MASK (0xFC0000U) #define MIPI_CSI_ISP_SYNC_HSYNC_LINTV_SHIFT (18U) #define MIPI_CSI_ISP_SYNC_HSYNC_LINTV(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_SYNC_HSYNC_LINTV_SHIFT)) & MIPI_CSI_ISP_SYNC_HSYNC_LINTV_MASK) /*! @} */ /* The count of MIPI_CSI_ISP_SYNC */ #define MIPI_CSI_ISP_SYNC_COUNT (4U) /*! @name SHADOW_CONFIG - Shadow Configuration Register */ /*! @{ */ #define MIPI_CSI_SHADOW_CONFIG_VIRTUAL_CHANNEL_MASK (0x3U) #define MIPI_CSI_SHADOW_CONFIG_VIRTUAL_CHANNEL_SHIFT (0U) #define MIPI_CSI_SHADOW_CONFIG_VIRTUAL_CHANNEL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_CONFIG_VIRTUAL_CHANNEL_SHIFT)) & \ MIPI_CSI_SHADOW_CONFIG_VIRTUAL_CHANNEL_MASK) #define MIPI_CSI_SHADOW_CONFIG_DATAFORMAT_MASK (0xFCU) #define MIPI_CSI_SHADOW_CONFIG_DATAFORMAT_SHIFT (2U) #define MIPI_CSI_SHADOW_CONFIG_DATAFORMAT(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_CONFIG_DATAFORMAT_SHIFT)) & MIPI_CSI_SHADOW_CONFIG_DATAFORMAT_MASK) #define MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW_MASK (0x400U) #define MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW_SHIFT (10U) #define MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW_SHIFT)) & \ MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW_MASK) #define MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW_MASK (0x800U) #define MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW_SHIFT (11U) #define MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW_SHIFT)) & \ MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW_MASK) #define MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE_MASK (0x3000U) #define MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE_SHIFT (12U) #define MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE_SHIFT)) & MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE_MASK) /*! @} */ /* The count of MIPI_CSI_SHADOW_CONFIG */ #define MIPI_CSI_SHADOW_CONFIG_COUNT (4U) /*! @name SHADOW_RESOLUTION - Shadow Resolution Register */ /*! @{ */ #define MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW_MASK (0xFFFFU) #define MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW_SHIFT (0U) #define MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW_SHIFT)) & \ MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW_MASK) #define MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW_MASK (0xFFFF0000U) #define MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW_SHIFT (16U) #define MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW_SHIFT)) & \ MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW_MASK) /*! @} */ /* The count of MIPI_CSI_SHADOW_RESOLUTION */ #define MIPI_CSI_SHADOW_RESOLUTION_COUNT (4U) /*! @name SHADOW_SYNC - Shadow SYNC Register */ /*! @{ */ #define MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW_MASK (0xFC0000U) #define MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW_SHIFT (18U) #define MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW_SHIFT)) & \ MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW_MASK) /*! @} */ /* The count of MIPI_CSI_SHADOW_SYNC */ #define MIPI_CSI_SHADOW_SYNC_COUNT (4U) /*! @name FRAME_COUNTER - Frame Counter */ /*! @{ */ #define MIPI_CSI_FRAME_COUNTER_FRM_CNT_MASK (0xFFFFFFFFU) #define MIPI_CSI_FRAME_COUNTER_FRM_CNT_SHIFT (0U) #define MIPI_CSI_FRAME_COUNTER_FRM_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_FRAME_COUNTER_FRM_CNT_SHIFT)) & MIPI_CSI_FRAME_COUNTER_FRM_CNT_MASK) /*! @} */ /* The count of MIPI_CSI_FRAME_COUNTER */ #define MIPI_CSI_FRAME_COUNTER_COUNT (4U) /*! @name LINE_INTERRUPT_RATIO - Line Interrupt Ratio */ /*! @{ */ #define MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR_MASK (0xFFFFFFFFU) #define MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR_SHIFT (0U) #define MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR_SHIFT)) & \ MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR_MASK) /*! @} */ /* The count of MIPI_CSI_LINE_INTERRUPT_RATIO */ #define MIPI_CSI_LINE_INTERRUPT_RATIO_COUNT (4U) /*! * @} */ /* end of group MIPI_CSI_Register_Masks */ /* MIPI_CSI - Peripheral instance base addresses */ /** Peripheral MIPI_CSI base address */ #define MIPI_CSI_BASE (0x32E30000u) /** Peripheral MIPI_CSI base pointer */ #define MIPI_CSI ((MIPI_CSI_Type *)MIPI_CSI_BASE) /** Array initializer of MIPI_CSI peripheral base addresses */ #define MIPI_CSI_BASE_ADDRS \ { \ MIPI_CSI_BASE \ } /** Array initializer of MIPI_CSI peripheral base pointers */ #define MIPI_CSI_BASE_PTRS \ { \ MIPI_CSI \ } /*! * @} */ /* end of group MIPI_CSI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MIPI_DSI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_DSI_Peripheral_Access_Layer MIPI_DSI Peripheral Access Layer * @{ */ /** MIPI_DSI - Register Layout Typedef */ typedef struct { __I uint32_t DSI_VERSION; /**< Specifies the DSI version register., offset: 0x0 */ __I uint32_t DSI_STATUS; /**< Specifies the status register., offset: 0x4 */ __I uint32_t DSI_RGB_STATUS; /**< Specifies the RGB FSM status register., offset: 0x8 */ __IO uint32_t DSI_SWRST; /**< Specifies the software reset register., offset: 0xC */ __IO uint32_t DSI_CLKCTRL; /**< Specifies the clock control register., offset: 0x10 */ __IO uint32_t DSI_TIMEOUT; /**< Specifies the time out register., offset: 0x14 */ __IO uint32_t DSI_CONFIG; /**< Specifies the configuration register., offset: 0x18 */ __IO uint32_t DSI_ESCMODE; /**< Specifies the escape mode register., offset: 0x1C */ __IO uint32_t DSI_MDRESOL; /**< Specifies the main display image resolution register., offset: 0x20 */ __IO uint32_t DSI_MVPORCH; /**< Specifies the main display Vporch register., offset: 0x24 */ __IO uint32_t DSI_MHPORCH; /**< Specifies the main display Hporch register., offset: 0x28 */ __IO uint32_t DSI_MSYNC; /**< Specifies the main display Sync Area register., offset: 0x2C */ __IO uint32_t DSI_SDRESOL; /**< Specifies the sub display image resolution register., offset: 0x30 */ __IO uint32_t DSI_INTSRC; /**< Specifies the interrupt source register., offset: 0x34 */ __IO uint32_t DSI_INTMSK; /**< Specifies the interrupt mask register., offset: 0x38 */ __O uint32_t DSI_PKTHDR; /**< Specifies the packet header FIFO register., offset: 0x3C */ __O uint32_t DSI_PAYLOAD; /**< Specifies the payload FIFO register., offset: 0x40 */ __I uint32_t DSI_RXFIFO; /**< Specifies the read FIFO register., offset: 0x44 */ __IO uint32_t DSI_FIFOTHLD; /**< Specifies the FIFO threshold level register., offset: 0x48 */ __IO uint32_t DSI_FIFOCTRL; /**< Specifies the FIFO status and control register., offset: 0x4C */ __IO uint32_t DSI_MEMACCHR; /**< Specifies the FIFO memory AC characteristic register., offset: 0x50 */ uint8_t RESERVED_0[36]; __IO uint32_t DSI_MULTI_PKT; /**< Specifies the Multi Packet, Packet Go register., offset: 0x78 */ uint8_t RESERVED_1[20]; __IO uint32_t DSI_PLLCTRL_1G; /**< Specifies the 1Gbps D-PHY PLL control register., offset: 0x90 */ __IO uint32_t DSI_PLLCTRL; /**< Specifies the PLL control register., offset: 0x94 */ __IO uint32_t DSI_PLLCTRL1; /**< Specifies the PLL control register 1., offset: 0x98 */ __IO uint32_t DSI_PLLCTRL2; /**< Specifies the PLL control register 2., offset: 0x9C */ __IO uint32_t DSI_PLLTMR; /**< Specifies the PLL timer register., offset: 0xA0 */ __IO uint32_t DSI_PHYCTRL_B1; /**< Specifies the D-PHY control register 1., offset: 0xA4 */ __IO uint32_t DSI_PHYCTRL_B2; /**< Specifies the D-PHY control register 2., offset: 0xA8 */ __IO uint32_t DSI_PHYCTRL_M1; /**< Specifies the D-PHY control register 1., offset: 0xAC */ __IO uint32_t DSI_PHYCTRL_M2; /**< Specifies the D-PHY control register 2., offset: 0xB0 */ __IO uint32_t DSI_PHYTIMING; /**< Specifies the D-PHY timing register., offset: 0xB4 */ __IO uint32_t DSI_PHYTIMING1; /**< Specifies the D-PHY timing register 1., offset: 0xB8 */ __IO uint32_t DSI_PHYTIMING2; /**< Specifies the D-PHY timing register 2., offset: 0xBC */ } MIPI_DSI_Type; /* ---------------------------------------------------------------------------- -- MIPI_DSI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_DSI_Register_Masks MIPI_DSI Register Masks * @{ */ /*! @name DSI_VERSION - Specifies the DSI version register. */ /*! @{ */ #define MIPI_DSI_DSI_VERSION_Version_MASK (0xFFFFFFFFU) #define MIPI_DSI_DSI_VERSION_Version_SHIFT (0U) #define MIPI_DSI_DSI_VERSION_Version(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_VERSION_Version_SHIFT)) & MIPI_DSI_DSI_VERSION_Version_MASK) /*! @} */ /*! @name DSI_STATUS - Specifies the status register. */ /*! @{ */ #define MIPI_DSI_DSI_STATUS_StopstateDat_MASK (0xFU) #define MIPI_DSI_DSI_STATUS_StopstateDat_SHIFT (0U) #define MIPI_DSI_DSI_STATUS_StopstateDat(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_StopstateDat_SHIFT)) & MIPI_DSI_DSI_STATUS_StopstateDat_MASK) #define MIPI_DSI_DSI_STATUS_UlpsDat_MASK (0xF0U) #define MIPI_DSI_DSI_STATUS_UlpsDat_SHIFT (4U) #define MIPI_DSI_DSI_STATUS_UlpsDat(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_UlpsDat_SHIFT)) & MIPI_DSI_DSI_STATUS_UlpsDat_MASK) #define MIPI_DSI_DSI_STATUS_StopstateClk_MASK (0x100U) #define MIPI_DSI_DSI_STATUS_StopstateClk_SHIFT (8U) #define MIPI_DSI_DSI_STATUS_StopstateClk(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_StopstateClk_SHIFT)) & MIPI_DSI_DSI_STATUS_StopstateClk_MASK) #define MIPI_DSI_DSI_STATUS_UlpsClk_MASK (0x200U) #define MIPI_DSI_DSI_STATUS_UlpsClk_SHIFT (9U) #define MIPI_DSI_DSI_STATUS_UlpsClk(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_UlpsClk_SHIFT)) & MIPI_DSI_DSI_STATUS_UlpsClk_MASK) #define MIPI_DSI_DSI_STATUS_TxReadyHsClk_MASK (0x400U) #define MIPI_DSI_DSI_STATUS_TxReadyHsClk_SHIFT (10U) #define MIPI_DSI_DSI_STATUS_TxReadyHsClk(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_TxReadyHsClk_SHIFT)) & MIPI_DSI_DSI_STATUS_TxReadyHsClk_MASK) #define MIPI_DSI_DSI_STATUS_Direction_MASK (0x10000U) #define MIPI_DSI_DSI_STATUS_Direction_SHIFT (16U) #define MIPI_DSI_DSI_STATUS_Direction(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_Direction_SHIFT)) & MIPI_DSI_DSI_STATUS_Direction_MASK) #define MIPI_DSI_DSI_STATUS_SwRstRls_MASK (0x100000U) #define MIPI_DSI_DSI_STATUS_SwRstRls_SHIFT (20U) #define MIPI_DSI_DSI_STATUS_SwRstRls(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_SwRstRls_SHIFT)) & MIPI_DSI_DSI_STATUS_SwRstRls_MASK) #define MIPI_DSI_DSI_STATUS_PllStable_MASK (0x80000000U) #define MIPI_DSI_DSI_STATUS_PllStable_SHIFT (31U) #define MIPI_DSI_DSI_STATUS_PllStable(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_PllStable_SHIFT)) & MIPI_DSI_DSI_STATUS_PllStable_MASK) /*! @} */ /*! @name DSI_RGB_STATUS - Specifies the RGB FSM status register. */ /*! @{ */ #define MIPI_DSI_DSI_RGB_STATUS_RGBstate_MASK (0x1FFFU) #define MIPI_DSI_DSI_RGB_STATUS_RGBstate_SHIFT (0U) #define MIPI_DSI_DSI_RGB_STATUS_RGBstate(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_RGB_STATUS_RGBstate_SHIFT)) & MIPI_DSI_DSI_RGB_STATUS_RGBstate_MASK) #define MIPI_DSI_DSI_RGB_STATUS_CmdMode_InSel_MASK (0x80000000U) #define MIPI_DSI_DSI_RGB_STATUS_CmdMode_InSel_SHIFT (31U) #define MIPI_DSI_DSI_RGB_STATUS_CmdMode_InSel(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_RGB_STATUS_CmdMode_InSel_SHIFT)) & \ MIPI_DSI_DSI_RGB_STATUS_CmdMode_InSel_MASK) /*! @} */ /*! @name DSI_SWRST - Specifies the software reset register. */ /*! @{ */ #define MIPI_DSI_DSI_SWRST_SwRst_MASK (0x1U) #define MIPI_DSI_DSI_SWRST_SwRst_SHIFT (0U) #define MIPI_DSI_DSI_SWRST_SwRst(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SWRST_SwRst_SHIFT)) & MIPI_DSI_DSI_SWRST_SwRst_MASK) #define MIPI_DSI_DSI_SWRST_FuncRst_MASK (0x10000U) #define MIPI_DSI_DSI_SWRST_FuncRst_SHIFT (16U) #define MIPI_DSI_DSI_SWRST_FuncRst(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SWRST_FuncRst_SHIFT)) & MIPI_DSI_DSI_SWRST_FuncRst_MASK) /*! @} */ /*! @name DSI_CLKCTRL - Specifies the clock control register. */ /*! @{ */ #define MIPI_DSI_DSI_CLKCTRL_EscPrescaler_MASK (0xFFFFU) #define MIPI_DSI_DSI_CLKCTRL_EscPrescaler_SHIFT (0U) #define MIPI_DSI_DSI_CLKCTRL_EscPrescaler(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_EscPrescaler_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_EscPrescaler_MASK) #define MIPI_DSI_DSI_CLKCTRL_LaneEscClkEn_MASK (0xF80000U) #define MIPI_DSI_DSI_CLKCTRL_LaneEscClkEn_SHIFT (19U) #define MIPI_DSI_DSI_CLKCTRL_LaneEscClkEn(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_LaneEscClkEn_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_LaneEscClkEn_MASK) #define MIPI_DSI_DSI_CLKCTRL_ByteClkEn_MASK (0x1000000U) #define MIPI_DSI_DSI_CLKCTRL_ByteClkEn_SHIFT (24U) #define MIPI_DSI_DSI_CLKCTRL_ByteClkEn(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_ByteClkEn_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_ByteClkEn_MASK) #define MIPI_DSI_DSI_CLKCTRL_ByteClkSrc_MASK (0x6000000U) #define MIPI_DSI_DSI_CLKCTRL_ByteClkSrc_SHIFT (25U) #define MIPI_DSI_DSI_CLKCTRL_ByteClkSrc(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_ByteClkSrc_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_ByteClkSrc_MASK) #define MIPI_DSI_DSI_CLKCTRL_PLLBypass_MASK (0x8000000U) #define MIPI_DSI_DSI_CLKCTRL_PLLBypass_SHIFT (27U) #define MIPI_DSI_DSI_CLKCTRL_PLLBypass(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_PLLBypass_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_PLLBypass_MASK) #define MIPI_DSI_DSI_CLKCTRL_EscClkEn_MASK (0x10000000U) #define MIPI_DSI_DSI_CLKCTRL_EscClkEn_SHIFT (28U) #define MIPI_DSI_DSI_CLKCTRL_EscClkEn(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_EscClkEn_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_EscClkEn_MASK) #define MIPI_DSI_DSI_CLKCTRL_Dphy_sel_MASK (0x20000000U) #define MIPI_DSI_DSI_CLKCTRL_Dphy_sel_SHIFT (29U) #define MIPI_DSI_DSI_CLKCTRL_Dphy_sel(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_Dphy_sel_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_Dphy_sel_MASK) #define MIPI_DSI_DSI_CLKCTRL_TxRequestHsClk_MASK (0x80000000U) #define MIPI_DSI_DSI_CLKCTRL_TxRequestHsClk_SHIFT (31U) #define MIPI_DSI_DSI_CLKCTRL_TxRequestHsClk(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_TxRequestHsClk_SHIFT)) & \ MIPI_DSI_DSI_CLKCTRL_TxRequestHsClk_MASK) /*! @} */ /*! @name DSI_TIMEOUT - Specifies the time out register. */ /*! @{ */ #define MIPI_DSI_DSI_TIMEOUT_LpdrTout_MASK (0xFFFFU) #define MIPI_DSI_DSI_TIMEOUT_LpdrTout_SHIFT (0U) #define MIPI_DSI_DSI_TIMEOUT_LpdrTout(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_TIMEOUT_LpdrTout_SHIFT)) & MIPI_DSI_DSI_TIMEOUT_LpdrTout_MASK) #define MIPI_DSI_DSI_TIMEOUT_BtaTout_MASK (0xFF0000U) #define MIPI_DSI_DSI_TIMEOUT_BtaTout_SHIFT (16U) #define MIPI_DSI_DSI_TIMEOUT_BtaTout(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_TIMEOUT_BtaTout_SHIFT)) & MIPI_DSI_DSI_TIMEOUT_BtaTout_MASK) /*! @} */ /*! @name DSI_CONFIG - Specifies the configuration register. */ /*! @{ */ #define MIPI_DSI_DSI_CONFIG_LaneEn_MASK (0x1FU) #define MIPI_DSI_DSI_CONFIG_LaneEn_SHIFT (0U) #define MIPI_DSI_DSI_CONFIG_LaneEn(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_LaneEn_SHIFT)) & MIPI_DSI_DSI_CONFIG_LaneEn_MASK) #define MIPI_DSI_DSI_CONFIG_NumOfDatLane_MASK (0x60U) #define MIPI_DSI_DSI_CONFIG_NumOfDatLane_SHIFT (5U) #define MIPI_DSI_DSI_CONFIG_NumOfDatLane(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_NumOfDatLane_SHIFT)) & MIPI_DSI_DSI_CONFIG_NumOfDatLane_MASK) #define MIPI_DSI_DSI_CONFIG_SubPixFormat_MASK (0x700U) #define MIPI_DSI_DSI_CONFIG_SubPixFormat_SHIFT (8U) #define MIPI_DSI_DSI_CONFIG_SubPixFormat(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_SubPixFormat_SHIFT)) & MIPI_DSI_DSI_CONFIG_SubPixFormat_MASK) #define MIPI_DSI_DSI_CONFIG_MainPixFormat_MASK (0x7000U) #define MIPI_DSI_DSI_CONFIG_MainPixFormat_SHIFT (12U) #define MIPI_DSI_DSI_CONFIG_MainPixFormat(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_MainPixFormat_SHIFT)) & MIPI_DSI_DSI_CONFIG_MainPixFormat_MASK) #define MIPI_DSI_DSI_CONFIG_SubVc_MASK (0x30000U) #define MIPI_DSI_DSI_CONFIG_SubVc_SHIFT (16U) #define MIPI_DSI_DSI_CONFIG_SubVc(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_SubVc_SHIFT)) & MIPI_DSI_DSI_CONFIG_SubVc_MASK) #define MIPI_DSI_DSI_CONFIG_MainVc_MASK (0xC0000U) #define MIPI_DSI_DSI_CONFIG_MainVc_SHIFT (18U) #define MIPI_DSI_DSI_CONFIG_MainVc(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_MainVc_SHIFT)) & MIPI_DSI_DSI_CONFIG_MainVc_MASK) #define MIPI_DSI_DSI_CONFIG_HsaDisableMode_MASK (0x100000U) #define MIPI_DSI_DSI_CONFIG_HsaDisableMode_SHIFT (20U) #define MIPI_DSI_DSI_CONFIG_HsaDisableMode(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_HsaDisableMode_SHIFT)) & \ MIPI_DSI_DSI_CONFIG_HsaDisableMode_MASK) #define MIPI_DSI_DSI_CONFIG_HbpDisableMode_MASK (0x200000U) #define MIPI_DSI_DSI_CONFIG_HbpDisableMode_SHIFT (21U) #define MIPI_DSI_DSI_CONFIG_HbpDisableMode(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_HbpDisableMode_SHIFT)) & \ MIPI_DSI_DSI_CONFIG_HbpDisableMode_MASK) #define MIPI_DSI_DSI_CONFIG_HfpDisableMode_MASK (0x400000U) #define MIPI_DSI_DSI_CONFIG_HfpDisableMode_SHIFT (22U) #define MIPI_DSI_DSI_CONFIG_HfpDisableMode(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_HfpDisableMode_SHIFT)) & \ MIPI_DSI_DSI_CONFIG_HfpDisableMode_MASK) #define MIPI_DSI_DSI_CONFIG_HseDisableMode_MASK (0x800000U) #define MIPI_DSI_DSI_CONFIG_HseDisableMode_SHIFT (23U) #define MIPI_DSI_DSI_CONFIG_HseDisableMode(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_HseDisableMode_SHIFT)) & \ MIPI_DSI_DSI_CONFIG_HseDisableMode_MASK) #define MIPI_DSI_DSI_CONFIG_AutoMode_MASK (0x1000000U) #define MIPI_DSI_DSI_CONFIG_AutoMode_SHIFT (24U) #define MIPI_DSI_DSI_CONFIG_AutoMode(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_AutoMode_SHIFT)) & MIPI_DSI_DSI_CONFIG_AutoMode_MASK) #define MIPI_DSI_DSI_CONFIG_VideoMode_MASK (0x2000000U) #define MIPI_DSI_DSI_CONFIG_VideoMode_SHIFT (25U) #define MIPI_DSI_DSI_CONFIG_VideoMode(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_VideoMode_SHIFT)) & MIPI_DSI_DSI_CONFIG_VideoMode_MASK) #define MIPI_DSI_DSI_CONFIG_BurstMode_MASK (0x4000000U) #define MIPI_DSI_DSI_CONFIG_BurstMode_SHIFT (26U) #define MIPI_DSI_DSI_CONFIG_BurstMode(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_BurstMode_SHIFT)) & MIPI_DSI_DSI_CONFIG_BurstMode_MASK) #define MIPI_DSI_DSI_CONFIG_SyncInform_MASK (0x8000000U) #define MIPI_DSI_DSI_CONFIG_SyncInform_SHIFT (27U) #define MIPI_DSI_DSI_CONFIG_SyncInform(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_SyncInform_SHIFT)) & MIPI_DSI_DSI_CONFIG_SyncInform_MASK) #define MIPI_DSI_DSI_CONFIG_EoT_r03_MASK (0x10000000U) #define MIPI_DSI_DSI_CONFIG_EoT_r03_SHIFT (28U) #define MIPI_DSI_DSI_CONFIG_EoT_r03(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_EoT_r03_SHIFT)) & MIPI_DSI_DSI_CONFIG_EoT_r03_MASK) #define MIPI_DSI_DSI_CONFIG_Mflush_VS_MASK (0x20000000U) #define MIPI_DSI_DSI_CONFIG_Mflush_VS_SHIFT (29U) #define MIPI_DSI_DSI_CONFIG_Mflush_VS(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_Mflush_VS_SHIFT)) & MIPI_DSI_DSI_CONFIG_Mflush_VS_MASK) #define MIPI_DSI_DSI_CONFIG_Clklane_Stop_Start_MASK (0x40000000U) #define MIPI_DSI_DSI_CONFIG_Clklane_Stop_Start_SHIFT (30U) #define MIPI_DSI_DSI_CONFIG_Clklane_Stop_Start(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_Clklane_Stop_Start_SHIFT)) & \ MIPI_DSI_DSI_CONFIG_Clklane_Stop_Start_MASK) #define MIPI_DSI_DSI_CONFIG_Non_Continuous_clock_lane_MASK (0x80000000U) #define MIPI_DSI_DSI_CONFIG_Non_Continuous_clock_lane_SHIFT (31U) #define MIPI_DSI_DSI_CONFIG_Non_Continuous_clock_lane(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_Non_Continuous_clock_lane_SHIFT)) & \ MIPI_DSI_DSI_CONFIG_Non_Continuous_clock_lane_MASK) /*! @} */ /*! @name DSI_ESCMODE - Specifies the escape mode register. */ /*! @{ */ #define MIPI_DSI_DSI_ESCMODE_TxUlpsClkExit_MASK (0x1U) #define MIPI_DSI_DSI_ESCMODE_TxUlpsClkExit_SHIFT (0U) #define MIPI_DSI_DSI_ESCMODE_TxUlpsClkExit(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TxUlpsClkExit_SHIFT)) & \ MIPI_DSI_DSI_ESCMODE_TxUlpsClkExit_MASK) #define MIPI_DSI_DSI_ESCMODE_TxUlpsClk_MASK (0x2U) #define MIPI_DSI_DSI_ESCMODE_TxUlpsClk_SHIFT (1U) #define MIPI_DSI_DSI_ESCMODE_TxUlpsClk(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TxUlpsClk_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TxUlpsClk_MASK) #define MIPI_DSI_DSI_ESCMODE_TxUlpsExit_MASK (0x4U) #define MIPI_DSI_DSI_ESCMODE_TxUlpsExit_SHIFT (2U) #define MIPI_DSI_DSI_ESCMODE_TxUlpsExit(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TxUlpsExit_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TxUlpsExit_MASK) #define MIPI_DSI_DSI_ESCMODE_TxUlpsDat_MASK (0x8U) #define MIPI_DSI_DSI_ESCMODE_TxUlpsDat_SHIFT (3U) #define MIPI_DSI_DSI_ESCMODE_TxUlpsDat(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TxUlpsDat_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TxUlpsDat_MASK) #define MIPI_DSI_DSI_ESCMODE_TxTriggerRst_MASK (0x10U) #define MIPI_DSI_DSI_ESCMODE_TxTriggerRst_SHIFT (4U) #define MIPI_DSI_DSI_ESCMODE_TxTriggerRst(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TxTriggerRst_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TxTriggerRst_MASK) #define MIPI_DSI_DSI_ESCMODE_TxLpdt_MASK (0x40U) #define MIPI_DSI_DSI_ESCMODE_TxLpdt_SHIFT (6U) #define MIPI_DSI_DSI_ESCMODE_TxLpdt(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TxLpdt_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TxLpdt_MASK) #define MIPI_DSI_DSI_ESCMODE_CmdLpdt_MASK (0x80U) #define MIPI_DSI_DSI_ESCMODE_CmdLpdt_SHIFT (7U) #define MIPI_DSI_DSI_ESCMODE_CmdLpdt(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_CmdLpdt_SHIFT)) & MIPI_DSI_DSI_ESCMODE_CmdLpdt_MASK) #define MIPI_DSI_DSI_ESCMODE_ForceBta_MASK (0x10000U) #define MIPI_DSI_DSI_ESCMODE_ForceBta_SHIFT (16U) #define MIPI_DSI_DSI_ESCMODE_ForceBta(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_ForceBta_SHIFT)) & MIPI_DSI_DSI_ESCMODE_ForceBta_MASK) #define MIPI_DSI_DSI_ESCMODE_ForceStopstate__MASK (0x100000U) #define MIPI_DSI_DSI_ESCMODE_ForceStopstate__SHIFT (20U) #define MIPI_DSI_DSI_ESCMODE_ForceStopstate_(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_ForceStopstate__SHIFT)) & \ MIPI_DSI_DSI_ESCMODE_ForceStopstate__MASK) #define MIPI_DSI_DSI_ESCMODE_STOPstate_Cnt_MASK (0xFFE00000U) #define MIPI_DSI_DSI_ESCMODE_STOPstate_Cnt_SHIFT (21U) #define MIPI_DSI_DSI_ESCMODE_STOPstate_Cnt(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_STOPstate_Cnt_SHIFT)) & \ MIPI_DSI_DSI_ESCMODE_STOPstate_Cnt_MASK) /*! @} */ /*! @name DSI_MDRESOL - Specifies the main display image resolution register. */ /*! @{ */ #define MIPI_DSI_DSI_MDRESOL_MainHResol_MASK (0xFFFU) #define MIPI_DSI_DSI_MDRESOL_MainHResol_SHIFT (0U) #define MIPI_DSI_DSI_MDRESOL_MainHResol(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MDRESOL_MainHResol_SHIFT)) & MIPI_DSI_DSI_MDRESOL_MainHResol_MASK) #define MIPI_DSI_DSI_MDRESOL_MainVResol_MASK (0xFFF0000U) #define MIPI_DSI_DSI_MDRESOL_MainVResol_SHIFT (16U) #define MIPI_DSI_DSI_MDRESOL_MainVResol(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MDRESOL_MainVResol_SHIFT)) & MIPI_DSI_DSI_MDRESOL_MainVResol_MASK) #define MIPI_DSI_DSI_MDRESOL_MainStandby_MASK (0x80000000U) #define MIPI_DSI_DSI_MDRESOL_MainStandby_SHIFT (31U) #define MIPI_DSI_DSI_MDRESOL_MainStandby(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MDRESOL_MainStandby_SHIFT)) & MIPI_DSI_DSI_MDRESOL_MainStandby_MASK) /*! @} */ /*! @name DSI_MVPORCH - Specifies the main display Vporch register. */ /*! @{ */ #define MIPI_DSI_DSI_MVPORCH_MainVbp_MASK (0x7FFU) #define MIPI_DSI_DSI_MVPORCH_MainVbp_SHIFT (0U) #define MIPI_DSI_DSI_MVPORCH_MainVbp(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MVPORCH_MainVbp_SHIFT)) & MIPI_DSI_DSI_MVPORCH_MainVbp_MASK) #define MIPI_DSI_DSI_MVPORCH_StableVfp_MASK (0x7FF0000U) #define MIPI_DSI_DSI_MVPORCH_StableVfp_SHIFT (16U) #define MIPI_DSI_DSI_MVPORCH_StableVfp(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MVPORCH_StableVfp_SHIFT)) & MIPI_DSI_DSI_MVPORCH_StableVfp_MASK) #define MIPI_DSI_DSI_MVPORCH_CmdAllow_MASK (0xF0000000U) #define MIPI_DSI_DSI_MVPORCH_CmdAllow_SHIFT (28U) #define MIPI_DSI_DSI_MVPORCH_CmdAllow(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MVPORCH_CmdAllow_SHIFT)) & MIPI_DSI_DSI_MVPORCH_CmdAllow_MASK) /*! @} */ /*! @name DSI_MHPORCH - Specifies the main display Hporch register. */ /*! @{ */ #define MIPI_DSI_DSI_MHPORCH_MainHbp_MASK (0xFFFFU) #define MIPI_DSI_DSI_MHPORCH_MainHbp_SHIFT (0U) #define MIPI_DSI_DSI_MHPORCH_MainHbp(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MHPORCH_MainHbp_SHIFT)) & MIPI_DSI_DSI_MHPORCH_MainHbp_MASK) #define MIPI_DSI_DSI_MHPORCH_MainHfp_MASK (0xFFFF0000U) #define MIPI_DSI_DSI_MHPORCH_MainHfp_SHIFT (16U) #define MIPI_DSI_DSI_MHPORCH_MainHfp(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MHPORCH_MainHfp_SHIFT)) & MIPI_DSI_DSI_MHPORCH_MainHfp_MASK) /*! @} */ /*! @name DSI_MSYNC - Specifies the main display Sync Area register. */ /*! @{ */ #define MIPI_DSI_DSI_MSYNC_MainHsa_MASK (0xFFFFU) #define MIPI_DSI_DSI_MSYNC_MainHsa_SHIFT (0U) #define MIPI_DSI_DSI_MSYNC_MainHsa(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MSYNC_MainHsa_SHIFT)) & MIPI_DSI_DSI_MSYNC_MainHsa_MASK) #define MIPI_DSI_DSI_MSYNC_MainVsa_MASK (0xFFC00000U) #define MIPI_DSI_DSI_MSYNC_MainVsa_SHIFT (22U) #define MIPI_DSI_DSI_MSYNC_MainVsa(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MSYNC_MainVsa_SHIFT)) & MIPI_DSI_DSI_MSYNC_MainVsa_MASK) /*! @} */ /*! @name DSI_SDRESOL - Specifies the sub display image resolution register. */ /*! @{ */ #define MIPI_DSI_DSI_SDRESOL_SubHResol_MASK (0x7FFU) #define MIPI_DSI_DSI_SDRESOL_SubHResol_SHIFT (0U) #define MIPI_DSI_DSI_SDRESOL_SubHResol(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SDRESOL_SubHResol_SHIFT)) & MIPI_DSI_DSI_SDRESOL_SubHResol_MASK) #define MIPI_DSI_DSI_SDRESOL_SubVResol_MASK (0x7FF0000U) #define MIPI_DSI_DSI_SDRESOL_SubVResol_SHIFT (16U) #define MIPI_DSI_DSI_SDRESOL_SubVResol(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SDRESOL_SubVResol_SHIFT)) & MIPI_DSI_DSI_SDRESOL_SubVResol_MASK) #define MIPI_DSI_DSI_SDRESOL_SubStandby_MASK (0x80000000U) #define MIPI_DSI_DSI_SDRESOL_SubStandby_SHIFT (31U) #define MIPI_DSI_DSI_SDRESOL_SubStandby(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SDRESOL_SubStandby_SHIFT)) & MIPI_DSI_DSI_SDRESOL_SubStandby_MASK) /*! @} */ /*! @name DSI_INTSRC - Specifies the interrupt source register. */ /*! @{ */ #define MIPI_DSI_DSI_INTSRC_ErrContentLP1_MASK (0x1U) #define MIPI_DSI_DSI_INTSRC_ErrContentLP1_SHIFT (0U) #define MIPI_DSI_DSI_INTSRC_ErrContentLP1(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrContentLP1_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrContentLP1_MASK) #define MIPI_DSI_DSI_INTSRC_ErrContentLP0_MASK (0x2U) #define MIPI_DSI_DSI_INTSRC_ErrContentLP0_SHIFT (1U) #define MIPI_DSI_DSI_INTSRC_ErrContentLP0(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrContentLP0_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrContentLP0_MASK) #define MIPI_DSI_DSI_INTSRC_ErrControl0_MASK (0x4U) #define MIPI_DSI_DSI_INTSRC_ErrControl0_SHIFT (2U) #define MIPI_DSI_DSI_INTSRC_ErrControl0(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrControl0_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrControl0_MASK) #define MIPI_DSI_DSI_INTSRC_ErrControl1_MASK (0x8U) #define MIPI_DSI_DSI_INTSRC_ErrControl1_SHIFT (3U) #define MIPI_DSI_DSI_INTSRC_ErrControl1(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrControl1_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrControl1_MASK) #define MIPI_DSI_DSI_INTSRC_ErrControl2_MASK (0x10U) #define MIPI_DSI_DSI_INTSRC_ErrControl2_SHIFT (4U) #define MIPI_DSI_DSI_INTSRC_ErrControl2(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrControl2_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrControl2_MASK) #define MIPI_DSI_DSI_INTSRC_ErrControl3_MASK (0x20U) #define MIPI_DSI_DSI_INTSRC_ErrControl3_SHIFT (5U) #define MIPI_DSI_DSI_INTSRC_ErrControl3(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrControl3_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrControl3_MASK) #define MIPI_DSI_DSI_INTSRC_ErrSync0_MASK (0x40U) #define MIPI_DSI_DSI_INTSRC_ErrSync0_SHIFT (6U) #define MIPI_DSI_DSI_INTSRC_ErrSync0(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrSync0_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrSync0_MASK) #define MIPI_DSI_DSI_INTSRC_ErrSync1_MASK (0x80U) #define MIPI_DSI_DSI_INTSRC_ErrSync1_SHIFT (7U) #define MIPI_DSI_DSI_INTSRC_ErrSync1(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrSync1_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrSync1_MASK) #define MIPI_DSI_DSI_INTSRC_ErrSync2_MASK (0x100U) #define MIPI_DSI_DSI_INTSRC_ErrSync2_SHIFT (8U) #define MIPI_DSI_DSI_INTSRC_ErrSync2(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrSync2_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrSync2_MASK) #define MIPI_DSI_DSI_INTSRC_ErrSync3_MASK (0x200U) #define MIPI_DSI_DSI_INTSRC_ErrSync3_SHIFT (9U) #define MIPI_DSI_DSI_INTSRC_ErrSync3(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrSync3_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrSync3_MASK) #define MIPI_DSI_DSI_INTSRC_ErrEsc0_MASK (0x400U) #define MIPI_DSI_DSI_INTSRC_ErrEsc0_SHIFT (10U) #define MIPI_DSI_DSI_INTSRC_ErrEsc0(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrEsc0_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrEsc0_MASK) #define MIPI_DSI_DSI_INTSRC_ErrEsc1_MASK (0x800U) #define MIPI_DSI_DSI_INTSRC_ErrEsc1_SHIFT (11U) #define MIPI_DSI_DSI_INTSRC_ErrEsc1(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrEsc1_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrEsc1_MASK) #define MIPI_DSI_DSI_INTSRC_ErrEsc2_MASK (0x1000U) #define MIPI_DSI_DSI_INTSRC_ErrEsc2_SHIFT (12U) #define MIPI_DSI_DSI_INTSRC_ErrEsc2(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrEsc2_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrEsc2_MASK) #define MIPI_DSI_DSI_INTSRC_ErrEsc3_MASK (0x2000U) #define MIPI_DSI_DSI_INTSRC_ErrEsc3_SHIFT (13U) #define MIPI_DSI_DSI_INTSRC_ErrEsc3(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrEsc3_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrEsc3_MASK) #define MIPI_DSI_DSI_INTSRC_ErrRxCRC_MASK (0x4000U) #define MIPI_DSI_DSI_INTSRC_ErrRxCRC_SHIFT (14U) #define MIPI_DSI_DSI_INTSRC_ErrRxCRC(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrRxCRC_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrRxCRC_MASK) #define MIPI_DSI_DSI_INTSRC_ErrRxECC_MASK (0x8000U) #define MIPI_DSI_DSI_INTSRC_ErrRxECC_SHIFT (15U) #define MIPI_DSI_DSI_INTSRC_ErrRxECC(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrRxECC_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrRxECC_MASK) #define MIPI_DSI_DSI_INTSRC_RxAck_MASK (0x10000U) #define MIPI_DSI_DSI_INTSRC_RxAck_SHIFT (16U) #define MIPI_DSI_DSI_INTSRC_RxAck(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_RxAck_SHIFT)) & MIPI_DSI_DSI_INTSRC_RxAck_MASK) #define MIPI_DSI_DSI_INTSRC_RxTE_MASK (0x20000U) #define MIPI_DSI_DSI_INTSRC_RxTE_SHIFT (17U) #define MIPI_DSI_DSI_INTSRC_RxTE(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_RxTE_SHIFT)) & MIPI_DSI_DSI_INTSRC_RxTE_MASK) #define MIPI_DSI_DSI_INTSRC_RxDatDone_MASK (0x40000U) #define MIPI_DSI_DSI_INTSRC_RxDatDone_SHIFT (18U) #define MIPI_DSI_DSI_INTSRC_RxDatDone(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_RxDatDone_SHIFT)) & MIPI_DSI_DSI_INTSRC_RxDatDone_MASK) #define MIPI_DSI_DSI_INTSRC_TaTout_MASK (0x100000U) #define MIPI_DSI_DSI_INTSRC_TaTout_SHIFT (20U) #define MIPI_DSI_DSI_INTSRC_TaTout(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_TaTout_SHIFT)) & MIPI_DSI_DSI_INTSRC_TaTout_MASK) #define MIPI_DSI_DSI_INTSRC_LpdrTout_MASK (0x200000U) #define MIPI_DSI_DSI_INTSRC_LpdrTout_SHIFT (21U) #define MIPI_DSI_DSI_INTSRC_LpdrTout(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_LpdrTout_SHIFT)) & MIPI_DSI_DSI_INTSRC_LpdrTout_MASK) #define MIPI_DSI_DSI_INTSRC_FrameDone_MASK (0x1000000U) #define MIPI_DSI_DSI_INTSRC_FrameDone_SHIFT (24U) #define MIPI_DSI_DSI_INTSRC_FrameDone(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_FrameDone_SHIFT)) & MIPI_DSI_DSI_INTSRC_FrameDone_MASK) #define MIPI_DSI_DSI_INTSRC_BusTurnOver_MASK (0x2000000U) #define MIPI_DSI_DSI_INTSRC_BusTurnOver_SHIFT (25U) #define MIPI_DSI_DSI_INTSRC_BusTurnOver(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_BusTurnOver_SHIFT)) & MIPI_DSI_DSI_INTSRC_BusTurnOver_MASK) #define MIPI_DSI_DSI_INTSRC_SyncOverride_MASK (0x8000000U) #define MIPI_DSI_DSI_INTSRC_SyncOverride_SHIFT (27U) #define MIPI_DSI_DSI_INTSRC_SyncOverride(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_SyncOverride_SHIFT)) & MIPI_DSI_DSI_INTSRC_SyncOverride_MASK) #define MIPI_DSI_DSI_INTSRC_SFRPHFifoEmpty_MASK (0x10000000U) #define MIPI_DSI_DSI_INTSRC_SFRPHFifoEmpty_SHIFT (28U) #define MIPI_DSI_DSI_INTSRC_SFRPHFifoEmpty(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_SFRPHFifoEmpty_SHIFT)) & \ MIPI_DSI_DSI_INTSRC_SFRPHFifoEmpty_MASK) #define MIPI_DSI_DSI_INTSRC_SFRPLFifoEmpty_MASK (0x20000000U) #define MIPI_DSI_DSI_INTSRC_SFRPLFifoEmpty_SHIFT (29U) #define MIPI_DSI_DSI_INTSRC_SFRPLFifoEmpty(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_SFRPLFifoEmpty_SHIFT)) & \ MIPI_DSI_DSI_INTSRC_SFRPLFifoEmpty_MASK) #define MIPI_DSI_DSI_INTSRC_SwRstRelease_MASK (0x40000000U) #define MIPI_DSI_DSI_INTSRC_SwRstRelease_SHIFT (30U) #define MIPI_DSI_DSI_INTSRC_SwRstRelease(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_SwRstRelease_SHIFT)) & MIPI_DSI_DSI_INTSRC_SwRstRelease_MASK) #define MIPI_DSI_DSI_INTSRC_PllStable_MASK (0x80000000U) #define MIPI_DSI_DSI_INTSRC_PllStable_SHIFT (31U) #define MIPI_DSI_DSI_INTSRC_PllStable(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_PllStable_SHIFT)) & MIPI_DSI_DSI_INTSRC_PllStable_MASK) /*! @} */ /*! @name DSI_INTMSK - Specifies the interrupt mask register. */ /*! @{ */ #define MIPI_DSI_DSI_INTMSK_MskContentLP1_MASK (0x1U) #define MIPI_DSI_DSI_INTMSK_MskContentLP1_SHIFT (0U) #define MIPI_DSI_DSI_INTMSK_MskContentLP1(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskContentLP1_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskContentLP1_MASK) #define MIPI_DSI_DSI_INTMSK_MskContentLP0_MASK (0x2U) #define MIPI_DSI_DSI_INTMSK_MskContentLP0_SHIFT (1U) #define MIPI_DSI_DSI_INTMSK_MskContentLP0(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskContentLP0_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskContentLP0_MASK) #define MIPI_DSI_DSI_INTMSK_MskControl0_MASK (0x4U) #define MIPI_DSI_DSI_INTMSK_MskControl0_SHIFT (2U) #define MIPI_DSI_DSI_INTMSK_MskControl0(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskControl0_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskControl0_MASK) #define MIPI_DSI_DSI_INTMSK_MskControl1_MASK (0x8U) #define MIPI_DSI_DSI_INTMSK_MskControl1_SHIFT (3U) #define MIPI_DSI_DSI_INTMSK_MskControl1(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskControl1_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskControl1_MASK) #define MIPI_DSI_DSI_INTMSK_MskControl2_MASK (0x10U) #define MIPI_DSI_DSI_INTMSK_MskControl2_SHIFT (4U) #define MIPI_DSI_DSI_INTMSK_MskControl2(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskControl2_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskControl2_MASK) #define MIPI_DSI_DSI_INTMSK_MskControl3_MASK (0x20U) #define MIPI_DSI_DSI_INTMSK_MskControl3_SHIFT (5U) #define MIPI_DSI_DSI_INTMSK_MskControl3(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskControl3_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskControl3_MASK) #define MIPI_DSI_DSI_INTMSK_MskSync0_MASK (0x40U) #define MIPI_DSI_DSI_INTMSK_MskSync0_SHIFT (6U) #define MIPI_DSI_DSI_INTMSK_MskSync0(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskSync0_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskSync0_MASK) #define MIPI_DSI_DSI_INTMSK_MskSync1_MASK (0x80U) #define MIPI_DSI_DSI_INTMSK_MskSync1_SHIFT (7U) #define MIPI_DSI_DSI_INTMSK_MskSync1(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskSync1_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskSync1_MASK) #define MIPI_DSI_DSI_INTMSK_MskSync2_MASK (0x100U) #define MIPI_DSI_DSI_INTMSK_MskSync2_SHIFT (8U) #define MIPI_DSI_DSI_INTMSK_MskSync2(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskSync2_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskSync2_MASK) #define MIPI_DSI_DSI_INTMSK_MskSync3_MASK (0x200U) #define MIPI_DSI_DSI_INTMSK_MskSync3_SHIFT (9U) #define MIPI_DSI_DSI_INTMSK_MskSync3(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskSync3_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskSync3_MASK) #define MIPI_DSI_DSI_INTMSK_MskEsc0_MASK (0x400U) #define MIPI_DSI_DSI_INTMSK_MskEsc0_SHIFT (10U) #define MIPI_DSI_DSI_INTMSK_MskEsc0(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskEsc0_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskEsc0_MASK) #define MIPI_DSI_DSI_INTMSK_MskEsc1_MASK (0x800U) #define MIPI_DSI_DSI_INTMSK_MskEsc1_SHIFT (11U) #define MIPI_DSI_DSI_INTMSK_MskEsc1(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskEsc1_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskEsc1_MASK) #define MIPI_DSI_DSI_INTMSK_MskEsc2_MASK (0x1000U) #define MIPI_DSI_DSI_INTMSK_MskEsc2_SHIFT (12U) #define MIPI_DSI_DSI_INTMSK_MskEsc2(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskEsc2_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskEsc2_MASK) #define MIPI_DSI_DSI_INTMSK_MskEsc3_MASK (0x2000U) #define MIPI_DSI_DSI_INTMSK_MskEsc3_SHIFT (13U) #define MIPI_DSI_DSI_INTMSK_MskEsc3(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskEsc3_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskEsc3_MASK) #define MIPI_DSI_DSI_INTMSK_MskRxCRC_MASK (0x4000U) #define MIPI_DSI_DSI_INTMSK_MskRxCRC_SHIFT (14U) #define MIPI_DSI_DSI_INTMSK_MskRxCRC(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskRxCRC_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskRxCRC_MASK) #define MIPI_DSI_DSI_INTMSK_MskRxECC_MASK (0x8000U) #define MIPI_DSI_DSI_INTMSK_MskRxECC_SHIFT (15U) #define MIPI_DSI_DSI_INTMSK_MskRxECC(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskRxECC_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskRxECC_MASK) #define MIPI_DSI_DSI_INTMSK_MskRxAck_MASK (0x10000U) #define MIPI_DSI_DSI_INTMSK_MskRxAck_SHIFT (16U) #define MIPI_DSI_DSI_INTMSK_MskRxAck(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskRxAck_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskRxAck_MASK) #define MIPI_DSI_DSI_INTMSK_MskRxTE_MASK (0x20000U) #define MIPI_DSI_DSI_INTMSK_MskRxTE_SHIFT (17U) #define MIPI_DSI_DSI_INTMSK_MskRxTE(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskRxTE_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskRxTE_MASK) #define MIPI_DSI_DSI_INTMSK_MskRxDatDone_MASK (0x40000U) #define MIPI_DSI_DSI_INTMSK_MskRxDatDone_SHIFT (18U) #define MIPI_DSI_DSI_INTMSK_MskRxDatDone(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskRxDatDone_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskRxDatDone_MASK) #define MIPI_DSI_DSI_INTMSK_MskTaTout_MASK (0x100000U) #define MIPI_DSI_DSI_INTMSK_MskTaTout_SHIFT (20U) #define MIPI_DSI_DSI_INTMSK_MskTaTout(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskTaTout_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskTaTout_MASK) #define MIPI_DSI_DSI_INTMSK_MskLpdrTout_MASK (0x200000U) #define MIPI_DSI_DSI_INTMSK_MskLpdrTout_SHIFT (21U) #define MIPI_DSI_DSI_INTMSK_MskLpdrTout(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskLpdrTout_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskLpdrTout_MASK) #define MIPI_DSI_DSI_INTMSK_MskFrameDone_MASK (0x1000000U) #define MIPI_DSI_DSI_INTMSK_MskFrameDone_SHIFT (24U) #define MIPI_DSI_DSI_INTMSK_MskFrameDone(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskFrameDone_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskFrameDone_MASK) #define MIPI_DSI_DSI_INTMSK_MskBusTurnOver_MASK (0x2000000U) #define MIPI_DSI_DSI_INTMSK_MskBusTurnOver_SHIFT (25U) #define MIPI_DSI_DSI_INTMSK_MskBusTurnOver(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskBusTurnOver_SHIFT)) & \ MIPI_DSI_DSI_INTMSK_MskBusTurnOver_MASK) #define MIPI_DSI_DSI_INTMSK_MskSyncOverride_MASK (0x8000000U) #define MIPI_DSI_DSI_INTMSK_MskSyncOverride_SHIFT (27U) #define MIPI_DSI_DSI_INTMSK_MskSyncOverride(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskSyncOverride_SHIFT)) & \ MIPI_DSI_DSI_INTMSK_MskSyncOverride_MASK) #define MIPI_DSI_DSI_INTMSK_MskSFRPHFifoEmpty_MASK (0x10000000U) #define MIPI_DSI_DSI_INTMSK_MskSFRPHFifoEmpty_SHIFT (28U) #define MIPI_DSI_DSI_INTMSK_MskSFRPHFifoEmpty(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskSFRPHFifoEmpty_SHIFT)) & \ MIPI_DSI_DSI_INTMSK_MskSFRPHFifoEmpty_MASK) #define MIPI_DSI_DSI_INTMSK_MskSFRPLFifoEmpty_MASK (0x20000000U) #define MIPI_DSI_DSI_INTMSK_MskSFRPLFifoEmpty_SHIFT (29U) #define MIPI_DSI_DSI_INTMSK_MskSFRPLFifoEmpty(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskSFRPLFifoEmpty_SHIFT)) & \ MIPI_DSI_DSI_INTMSK_MskSFRPLFifoEmpty_MASK) #define MIPI_DSI_DSI_INTMSK_MskSwRstRelease_MASK (0x40000000U) #define MIPI_DSI_DSI_INTMSK_MskSwRstRelease_SHIFT (30U) #define MIPI_DSI_DSI_INTMSK_MskSwRstRelease(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskSwRstRelease_SHIFT)) & \ MIPI_DSI_DSI_INTMSK_MskSwRstRelease_MASK) #define MIPI_DSI_DSI_INTMSK_MskPllStable_MASK (0x80000000U) #define MIPI_DSI_DSI_INTMSK_MskPllStable_SHIFT (31U) #define MIPI_DSI_DSI_INTMSK_MskPllStable(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskPllStable_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskPllStable_MASK) /*! @} */ /*! @name DSI_PKTHDR - Specifies the packet header FIFO register. */ /*! @{ */ #define MIPI_DSI_DSI_PKTHDR_PacketHeader_MASK (0xFFFFFFU) #define MIPI_DSI_DSI_PKTHDR_PacketHeader_SHIFT (0U) #define MIPI_DSI_DSI_PKTHDR_PacketHeader(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PKTHDR_PacketHeader_SHIFT)) & MIPI_DSI_DSI_PKTHDR_PacketHeader_MASK) /*! @} */ /*! @name DSI_PAYLOAD - Specifies the payload FIFO register. */ /*! @{ */ #define MIPI_DSI_DSI_PAYLOAD_Payload_MASK (0xFFFFFFFFU) #define MIPI_DSI_DSI_PAYLOAD_Payload_SHIFT (0U) #define MIPI_DSI_DSI_PAYLOAD_Payload(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PAYLOAD_Payload_SHIFT)) & MIPI_DSI_DSI_PAYLOAD_Payload_MASK) /*! @} */ /*! @name DSI_RXFIFO - Specifies the read FIFO register. */ /*! @{ */ #define MIPI_DSI_DSI_RXFIFO_RxDat_MASK (0xFFFFFFFFU) #define MIPI_DSI_DSI_RXFIFO_RxDat_SHIFT (0U) #define MIPI_DSI_DSI_RXFIFO_RxDat(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_RXFIFO_RxDat_SHIFT)) & MIPI_DSI_DSI_RXFIFO_RxDat_MASK) /*! @} */ /*! @name DSI_FIFOTHLD - Specifies the FIFO threshold level register. */ /*! @{ */ #define MIPI_DSI_DSI_FIFOTHLD_WfullLevelSfr_MASK (0x1FFU) #define MIPI_DSI_DSI_FIFOTHLD_WfullLevelSfr_SHIFT (0U) #define MIPI_DSI_DSI_FIFOTHLD_WfullLevelSfr(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOTHLD_WfullLevelSfr_SHIFT)) & \ MIPI_DSI_DSI_FIFOTHLD_WfullLevelSfr_MASK) /*! @} */ /*! @name DSI_FIFOCTRL - Specifies the FIFO status and control register. */ /*! @{ */ #define MIPI_DSI_DSI_FIFOCTRL_nInitMain_MASK (0x1U) #define MIPI_DSI_DSI_FIFOCTRL_nInitMain_SHIFT (0U) #define MIPI_DSI_DSI_FIFOCTRL_nInitMain(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_nInitMain_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_nInitMain_MASK) #define MIPI_DSI_DSI_FIFOCTRL_nInitSub_MASK (0x2U) #define MIPI_DSI_DSI_FIFOCTRL_nInitSub_SHIFT (1U) #define MIPI_DSI_DSI_FIFOCTRL_nInitSub(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_nInitSub_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_nInitSub_MASK) #define MIPI_DSI_DSI_FIFOCTRL_nInitI80_MASK (0x4U) #define MIPI_DSI_DSI_FIFOCTRL_nInitI80_SHIFT (2U) #define MIPI_DSI_DSI_FIFOCTRL_nInitI80(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_nInitI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_nInitI80_MASK) #define MIPI_DSI_DSI_FIFOCTRL_nInitSfr_MASK (0x8U) #define MIPI_DSI_DSI_FIFOCTRL_nInitSfr_SHIFT (3U) #define MIPI_DSI_DSI_FIFOCTRL_nInitSfr(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_nInitSfr_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_nInitSfr_MASK) #define MIPI_DSI_DSI_FIFOCTRL_nInitRx_MASK (0x10U) #define MIPI_DSI_DSI_FIFOCTRL_nInitRx_SHIFT (4U) #define MIPI_DSI_DSI_FIFOCTRL_nInitRx(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_nInitRx_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_nInitRx_MASK) #define MIPI_DSI_DSI_FIFOCTRL_EmptyLMain_MASK (0x100U) #define MIPI_DSI_DSI_FIFOCTRL_EmptyLMain_SHIFT (8U) #define MIPI_DSI_DSI_FIFOCTRL_EmptyLMain(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EmptyLMain_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EmptyLMain_MASK) #define MIPI_DSI_DSI_FIFOCTRL_FullLMain_MASK (0x200U) #define MIPI_DSI_DSI_FIFOCTRL_FullLMain_SHIFT (9U) #define MIPI_DSI_DSI_FIFOCTRL_FullLMain(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FullLMain_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FullLMain_MASK) #define MIPI_DSI_DSI_FIFOCTRL_EmptyHMain_MASK (0x400U) #define MIPI_DSI_DSI_FIFOCTRL_EmptyHMain_SHIFT (10U) #define MIPI_DSI_DSI_FIFOCTRL_EmptyHMain(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EmptyHMain_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EmptyHMain_MASK) #define MIPI_DSI_DSI_FIFOCTRL_FullHMain_MASK (0x800U) #define MIPI_DSI_DSI_FIFOCTRL_FullHMain_SHIFT (11U) #define MIPI_DSI_DSI_FIFOCTRL_FullHMain(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FullHMain_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FullHMain_MASK) #define MIPI_DSI_DSI_FIFOCTRL_EmptyLSub_MASK (0x1000U) #define MIPI_DSI_DSI_FIFOCTRL_EmptyLSub_SHIFT (12U) #define MIPI_DSI_DSI_FIFOCTRL_EmptyLSub(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EmptyLSub_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EmptyLSub_MASK) #define MIPI_DSI_DSI_FIFOCTRL_FullLSub_MASK (0x2000U) #define MIPI_DSI_DSI_FIFOCTRL_FullLSub_SHIFT (13U) #define MIPI_DSI_DSI_FIFOCTRL_FullLSub(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FullLSub_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FullLSub_MASK) #define MIPI_DSI_DSI_FIFOCTRL_EmptyHSub_MASK (0x4000U) #define MIPI_DSI_DSI_FIFOCTRL_EmptyHSub_SHIFT (14U) #define MIPI_DSI_DSI_FIFOCTRL_EmptyHSub(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EmptyHSub_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EmptyHSub_MASK) #define MIPI_DSI_DSI_FIFOCTRL_FullHSub_MASK (0x8000U) #define MIPI_DSI_DSI_FIFOCTRL_FullHSub_SHIFT (15U) #define MIPI_DSI_DSI_FIFOCTRL_FullHSub(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FullHSub_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FullHSub_MASK) #define MIPI_DSI_DSI_FIFOCTRL_EmptyLI80_MASK (0x10000U) #define MIPI_DSI_DSI_FIFOCTRL_EmptyLI80_SHIFT (16U) #define MIPI_DSI_DSI_FIFOCTRL_EmptyLI80(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EmptyLI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EmptyLI80_MASK) #define MIPI_DSI_DSI_FIFOCTRL_FullLI80_MASK (0x20000U) #define MIPI_DSI_DSI_FIFOCTRL_FullLI80_SHIFT (17U) #define MIPI_DSI_DSI_FIFOCTRL_FullLI80(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FullLI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FullLI80_MASK) #define MIPI_DSI_DSI_FIFOCTRL_EmptyHI80_MASK (0x40000U) #define MIPI_DSI_DSI_FIFOCTRL_EmptyHI80_SHIFT (18U) #define MIPI_DSI_DSI_FIFOCTRL_EmptyHI80(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EmptyHI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EmptyHI80_MASK) #define MIPI_DSI_DSI_FIFOCTRL_FullHI80_MASK (0x80000U) #define MIPI_DSI_DSI_FIFOCTRL_FullHI80_SHIFT (19U) #define MIPI_DSI_DSI_FIFOCTRL_FullHI80(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FullHI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FullHI80_MASK) #define MIPI_DSI_DSI_FIFOCTRL_EmptyLSfr_MASK (0x100000U) #define MIPI_DSI_DSI_FIFOCTRL_EmptyLSfr_SHIFT (20U) #define MIPI_DSI_DSI_FIFOCTRL_EmptyLSfr(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EmptyLSfr_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EmptyLSfr_MASK) #define MIPI_DSI_DSI_FIFOCTRL_FullLSfr_MASK (0x200000U) #define MIPI_DSI_DSI_FIFOCTRL_FullLSfr_SHIFT (21U) #define MIPI_DSI_DSI_FIFOCTRL_FullLSfr(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FullLSfr_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FullLSfr_MASK) #define MIPI_DSI_DSI_FIFOCTRL_EmptyHSfr_MASK (0x400000U) #define MIPI_DSI_DSI_FIFOCTRL_EmptyHSfr_SHIFT (22U) #define MIPI_DSI_DSI_FIFOCTRL_EmptyHSfr(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EmptyHSfr_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EmptyHSfr_MASK) #define MIPI_DSI_DSI_FIFOCTRL_FullHSfr_MASK (0x800000U) #define MIPI_DSI_DSI_FIFOCTRL_FullHSfr_SHIFT (23U) #define MIPI_DSI_DSI_FIFOCTRL_FullHSfr(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FullHSfr_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FullHSfr_MASK) #define MIPI_DSI_DSI_FIFOCTRL_EmptyRx_MASK (0x1000000U) #define MIPI_DSI_DSI_FIFOCTRL_EmptyRx_SHIFT (24U) #define MIPI_DSI_DSI_FIFOCTRL_EmptyRx(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EmptyRx_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EmptyRx_MASK) #define MIPI_DSI_DSI_FIFOCTRL_FullRx_MASK (0x2000000U) #define MIPI_DSI_DSI_FIFOCTRL_FullRx_SHIFT (25U) #define MIPI_DSI_DSI_FIFOCTRL_FullRx(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FullRx_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FullRx_MASK) /*! @} */ /*! @name DSI_MEMACCHR - Specifies the FIFO memory AC characteristic register. */ /*! @{ */ #define MIPI_DSI_DSI_MEMACCHR_EMAA_MD_MASK (0x7U) #define MIPI_DSI_DSI_MEMACCHR_EMAA_MD_SHIFT (0U) #define MIPI_DSI_DSI_MEMACCHR_EMAA_MD(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_EMAA_MD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_EMAA_MD_MASK) #define MIPI_DSI_DSI_MEMACCHR_EMAB_MD_MASK (0x38U) #define MIPI_DSI_DSI_MEMACCHR_EMAB_MD_SHIFT (3U) #define MIPI_DSI_DSI_MEMACCHR_EMAB_MD(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_EMAB_MD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_EMAB_MD_MASK) #define MIPI_DSI_DSI_MEMACCHR_RETN_MD_MASK (0x40U) #define MIPI_DSI_DSI_MEMACCHR_RETN_MD_SHIFT (6U) #define MIPI_DSI_DSI_MEMACCHR_RETN_MD(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_RETN_MD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_RETN_MD_MASK) #define MIPI_DSI_DSI_MEMACCHR_PGEN_MD_MASK (0x80U) #define MIPI_DSI_DSI_MEMACCHR_PGEN_MD_SHIFT (7U) #define MIPI_DSI_DSI_MEMACCHR_PGEN_MD(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_PGEN_MD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_PGEN_MD_MASK) #define MIPI_DSI_DSI_MEMACCHR_EMAA_SD_MASK (0x700U) #define MIPI_DSI_DSI_MEMACCHR_EMAA_SD_SHIFT (8U) #define MIPI_DSI_DSI_MEMACCHR_EMAA_SD(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_EMAA_SD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_EMAA_SD_MASK) #define MIPI_DSI_DSI_MEMACCHR_EMAB_SD_MASK (0x3800U) #define MIPI_DSI_DSI_MEMACCHR_EMAB_SD_SHIFT (11U) #define MIPI_DSI_DSI_MEMACCHR_EMAB_SD(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_EMAB_SD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_EMAB_SD_MASK) #define MIPI_DSI_DSI_MEMACCHR_RETN_SD_MASK (0x4000U) #define MIPI_DSI_DSI_MEMACCHR_RETN_SD_SHIFT (14U) #define MIPI_DSI_DSI_MEMACCHR_RETN_SD(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_RETN_SD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_RETN_SD_MASK) #define MIPI_DSI_DSI_MEMACCHR_PGEN_SD_MASK (0x8000U) #define MIPI_DSI_DSI_MEMACCHR_PGEN_SD_SHIFT (15U) #define MIPI_DSI_DSI_MEMACCHR_PGEN_SD(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_PGEN_SD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_PGEN_SD_MASK) /*! @} */ /*! @name DSI_MULTI_PKT - Specifies the Multi Packet, Packet Go register. */ /*! @{ */ #define MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_Cnt_Ref_MASK (0xFFFFU) #define MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_Cnt_Ref_SHIFT (0U) #define MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_Cnt_Ref(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_Cnt_Ref_SHIFT)) & \ MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_Cnt_Ref_MASK) #define MIPI_DSI_DSI_MULTI_PKT_PKT_Send_Cnt_Ref_MASK (0xFFF0000U) #define MIPI_DSI_DSI_MULTI_PKT_PKT_Send_Cnt_Ref_SHIFT (16U) #define MIPI_DSI_DSI_MULTI_PKT_PKT_Send_Cnt_Ref(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_PKT_Send_Cnt_Ref_SHIFT)) & \ MIPI_DSI_DSI_MULTI_PKT_PKT_Send_Cnt_Ref_MASK) #define MIPI_DSI_DSI_MULTI_PKT_PKT_Go_Rdy_MASK (0x10000000U) #define MIPI_DSI_DSI_MULTI_PKT_PKT_Go_Rdy_SHIFT (28U) #define MIPI_DSI_DSI_MULTI_PKT_PKT_Go_Rdy(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_PKT_Go_Rdy_SHIFT)) & MIPI_DSI_DSI_MULTI_PKT_PKT_Go_Rdy_MASK) #define MIPI_DSI_DSI_MULTI_PKT_PKT_Go_EN_MASK (0x20000000U) #define MIPI_DSI_DSI_MULTI_PKT_PKT_Go_EN_SHIFT (29U) #define MIPI_DSI_DSI_MULTI_PKT_PKT_Go_EN(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_PKT_Go_EN_SHIFT)) & MIPI_DSI_DSI_MULTI_PKT_PKT_Go_EN_MASK) #define MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_EN_MASK (0x40000000U) #define MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_EN_SHIFT (30U) #define MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_EN(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_EN_SHIFT)) & \ MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_EN_MASK) /*! @} */ /*! @name DSI_PLLCTRL_1G - Specifies the 1Gbps D-PHY PLL control register. */ /*! @{ */ #define MIPI_DSI_DSI_PLLCTRL_1G_PRPRCtlClk_MASK (0x7U) #define MIPI_DSI_DSI_PLLCTRL_1G_PRPRCtlClk_SHIFT (0U) #define MIPI_DSI_DSI_PLLCTRL_1G_PRPRCtlClk(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_1G_PRPRCtlClk_SHIFT)) & \ MIPI_DSI_DSI_PLLCTRL_1G_PRPRCtlClk_MASK) #define MIPI_DSI_DSI_PLLCTRL_1G_PREPRCtl_MASK (0x70U) #define MIPI_DSI_DSI_PLLCTRL_1G_PREPRCtl_SHIFT (4U) #define MIPI_DSI_DSI_PLLCTRL_1G_PREPRCtl(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_1G_PREPRCtl_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_1G_PREPRCtl_MASK) #define MIPI_DSI_DSI_PLLCTRL_1G_Freq_Band_MASK (0xF00U) #define MIPI_DSI_DSI_PLLCTRL_1G_Freq_Band_SHIFT (8U) #define MIPI_DSI_DSI_PLLCTRL_1G_Freq_Band(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_1G_Freq_Band_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_1G_Freq_Band_MASK) #define MIPI_DSI_DSI_PLLCTRL_1G_HSzeroCtl_MASK (0xF000U) #define MIPI_DSI_DSI_PLLCTRL_1G_HSzeroCtl_SHIFT (12U) #define MIPI_DSI_DSI_PLLCTRL_1G_HSzeroCtl(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_1G_HSzeroCtl_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_1G_HSzeroCtl_MASK) /*! @} */ /*! @name DSI_PLLCTRL - Specifies the PLL control register. */ /*! @{ */ #define MIPI_DSI_DSI_PLLCTRL_PMS_MASK (0xFFFFEU) #define MIPI_DSI_DSI_PLLCTRL_PMS_SHIFT (1U) #define MIPI_DSI_DSI_PLLCTRL_PMS(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_PMS_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_PMS_MASK) #define MIPI_DSI_DSI_PLLCTRL_PllEn_MASK (0x800000U) #define MIPI_DSI_DSI_PLLCTRL_PllEn_SHIFT (23U) #define MIPI_DSI_DSI_PLLCTRL_PllEn(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_PllEn_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_PllEn_MASK) #define MIPI_DSI_DSI_PLLCTRL_DpDnSwap_DAT_MASK (0x1000000U) #define MIPI_DSI_DSI_PLLCTRL_DpDnSwap_DAT_SHIFT (24U) #define MIPI_DSI_DSI_PLLCTRL_DpDnSwap_DAT(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_DpDnSwap_DAT_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_DpDnSwap_DAT_MASK) #define MIPI_DSI_DSI_PLLCTRL_DpDnSwap_CLK_MASK (0x2000000U) #define MIPI_DSI_DSI_PLLCTRL_DpDnSwap_CLK_SHIFT (25U) #define MIPI_DSI_DSI_PLLCTRL_DpDnSwap_CLK(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_DpDnSwap_CLK_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_DpDnSwap_CLK_MASK) /*! @} */ /*! @name DSI_PLLCTRL1 - Specifies the PLL control register 1. */ /*! @{ */ #define MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0_MASK (0xFFFFFFFFU) #define MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0_SHIFT (0U) #define MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0_SHIFT)) & MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0_MASK) /*! @} */ /*! @name DSI_PLLCTRL2 - Specifies the PLL control register 2. */ /*! @{ */ #define MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1_MASK (0xFFU) #define MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1_SHIFT (0U) #define MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1_SHIFT)) & MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1_MASK) /*! @} */ /*! @name DSI_PLLTMR - Specifies the PLL timer register. */ /*! @{ */ #define MIPI_DSI_DSI_PLLTMR_PllTimer_MASK (0xFFFFFFFFU) #define MIPI_DSI_DSI_PLLTMR_PllTimer_SHIFT (0U) #define MIPI_DSI_DSI_PLLTMR_PllTimer(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLTMR_PllTimer_SHIFT)) & MIPI_DSI_DSI_PLLTMR_PllTimer_MASK) /*! @} */ /*! @name DSI_PHYCTRL_B1 - Specifies the D-PHY control register 1. */ /*! @{ */ #define MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0_MASK (0xFFFFFFFFU) #define MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0_SHIFT (0U) #define MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0_SHIFT)) & \ MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0_MASK) /*! @} */ /*! @name DSI_PHYCTRL_B2 - Specifies the D-PHY control register 2. */ /*! @{ */ #define MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1_MASK (0xFFFFFFFFU) #define MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1_SHIFT (0U) #define MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1_SHIFT)) & \ MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1_MASK) /*! @} */ /*! @name DSI_PHYCTRL_M1 - Specifies the D-PHY control register 1. */ /*! @{ */ #define MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0_MASK (0xFFFFFFFFU) #define MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0_SHIFT (0U) #define MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0_SHIFT)) & \ MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0_MASK) /*! @} */ /*! @name DSI_PHYCTRL_M2 - Specifies the D-PHY control register 2. */ /*! @{ */ #define MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1_MASK (0xFFFFFFFFU) #define MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1_SHIFT (0U) #define MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1_SHIFT)) & \ MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1_MASK) /*! @} */ /*! @name DSI_PHYTIMING - Specifies the D-PHY timing register. */ /*! @{ */ #define MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL_MASK (0xFFU) #define MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL_SHIFT (0U) #define MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL_SHIFT)) & \ MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL_MASK) #define MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL_MASK (0xFF00U) #define MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL_SHIFT (8U) #define MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL_MASK) /*! @} */ /*! @name DSI_PHYTIMING1 - Specifies the D-PHY timing register 1. */ /*! @{ */ #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL_MASK (0xFFU) #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL_SHIFT (0U) #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL_SHIFT)) & \ MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL_MASK) #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL_MASK (0xFF00U) #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL_SHIFT (8U) #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL_SHIFT)) & \ MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL_MASK) #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL_MASK (0xFF0000U) #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL_SHIFT (16U) #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL_SHIFT)) & \ MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL_MASK) #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL_MASK (0xFF000000U) #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL_SHIFT (24U) #define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL_SHIFT)) & \ MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL_MASK) /*! @} */ /*! @name DSI_PHYTIMING2 - Specifies the D-PHY timing register 2. */ /*! @{ */ #define MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL_MASK (0xFFU) #define MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL_SHIFT (0U) #define MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL_SHIFT)) & \ MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL_MASK) #define MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL_MASK (0xFF00U) #define MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL_SHIFT (8U) #define MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL_SHIFT)) & \ MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL_MASK) #define MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL_MASK (0xFF0000U) #define MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL_SHIFT (16U) #define MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL(x) \ (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL_SHIFT)) & \ MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL_MASK) /*! @} */ /*! * @} */ /* end of group MIPI_DSI_Register_Masks */ /* MIPI_DSI - Peripheral instance base addresses */ /** Peripheral MIPI_DSI base address */ #define MIPI_DSI_BASE (0x32E10000u) /** Peripheral MIPI_DSI base pointer */ #define MIPI_DSI ((MIPI_DSI_Type *)MIPI_DSI_BASE) /** Array initializer of MIPI_DSI peripheral base addresses */ #define MIPI_DSI_BASE_ADDRS \ { \ MIPI_DSI_BASE \ } /** Array initializer of MIPI_DSI peripheral base pointers */ #define MIPI_DSI_BASE_PTRS \ { \ MIPI_DSI \ } /*! * @} */ /* end of group MIPI_DSI_Peripheral_Access_Layer */ /*! * @brief Power mode on the other side definition. */ typedef enum _mu_power_mode { kMU_PowerModeRun = 0x00U, /*!< Run mode. */ kMU_PowerModeWait = 0x01U, /*!< WAIT mode. */ kMU_PowerModeStop = 0x03U, /*!< STOP mode. */ } mu_power_mode_t; /* ---------------------------------------------------------------------------- -- MU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer * @{ */ /** MU - Register Layout Typedef */ typedef struct { __IO uint32_t TR[4]; /**< Processor B Transmit Register 0..Processor B Transmit Register 3, array offset: 0x0, array step: 0x4 */ __I uint32_t RR[4]; /**< Processor B Receive Register 0..Processor B Receive Register 3, array offset: 0x10, array step: 0x4 */ __IO uint32_t SR; /**< Processor B Status Register, offset: 0x20 */ __IO uint32_t CR; /**< Processor B Control Register, offset: 0x24 */ } MU_Type; /* ---------------------------------------------------------------------------- -- MU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MU_Register_Masks MU Register Masks * @{ */ /*! @name TR - Processor B Transmit Register 0..Processor B Transmit Register 3 */ /*! @{ */ #define MU_TR_BTR0_MASK (0xFFFFFFFFU) #define MU_TR_BTR0_SHIFT (0U) #define MU_TR_BTR0(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR0_SHIFT)) & MU_TR_BTR0_MASK) #define MU_TR_BTR1_MASK (0xFFFFFFFFU) #define MU_TR_BTR1_SHIFT (0U) #define MU_TR_BTR1(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR1_SHIFT)) & MU_TR_BTR1_MASK) #define MU_TR_BTR2_MASK (0xFFFFFFFFU) #define MU_TR_BTR2_SHIFT (0U) #define MU_TR_BTR2(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK) #define MU_TR_BTR3_MASK (0xFFFFFFFFU) #define MU_TR_BTR3_SHIFT (0U) #define MU_TR_BTR3(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR3_SHIFT)) & MU_TR_BTR3_MASK) /*! @} */ /* The count of MU_TR */ #define MU_TR_COUNT (4U) /*! @name RR - Processor B Receive Register 0..Processor B Receive Register 3 */ /*! @{ */ #define MU_RR_BRR0_MASK (0xFFFFFFFFU) #define MU_RR_BRR0_SHIFT (0U) #define MU_RR_BRR0(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR0_SHIFT)) & MU_RR_BRR0_MASK) #define MU_RR_BRR1_MASK (0xFFFFFFFFU) #define MU_RR_BRR1_SHIFT (0U) #define MU_RR_BRR1(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR1_SHIFT)) & MU_RR_BRR1_MASK) #define MU_RR_BRR2_MASK (0xFFFFFFFFU) #define MU_RR_BRR2_SHIFT (0U) #define MU_RR_BRR2(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR2_SHIFT)) & MU_RR_BRR2_MASK) #define MU_RR_BRR3_MASK (0xFFFFFFFFU) #define MU_RR_BRR3_SHIFT (0U) #define MU_RR_BRR3(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR3_SHIFT)) & MU_RR_BRR3_MASK) /*! @} */ /* The count of MU_RR */ #define MU_RR_COUNT (4U) /*! @name SR - Processor B Status Register */ /*! @{ */ #define MU_SR_Fn_MASK (0x7U) #define MU_SR_Fn_SHIFT (0U) /*! Fn * 0b000..ABFn bit in ACR register is written 0 (default). * 0b001..ABFn bit in ACR register is written 1. */ #define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK) #define MU_SR_EP_MASK (0x10U) #define MU_SR_EP_SHIFT (4U) /*! EP * 0b0..The Processor B-side event is not pending (default). * 0b1..The Processor B-side event is pending. */ #define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK) #define MU_SR_APM_MASK (0x60U) #define MU_SR_APM_SHIFT (5U) /*! APM * 0b00..The System is in Run Mode. * 0b01..The System is in WAIT Mode. * 0b10..Reserved. * 0b11..The System is in STOP Mode. */ #define MU_SR_APM(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_APM_SHIFT)) & MU_SR_APM_MASK) #define MU_SR_ARS_MASK (0x80U) #define MU_SR_ARS_SHIFT (7U) /*! ARS * 0b0..The Processor A or the Processor A-side of the MU is not in reset. * 0b1..The Processor A or the Processor A-side of the MU is in reset. */ #define MU_SR_ARS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_ARS_SHIFT)) & MU_SR_ARS_MASK) #define MU_SR_FUP_MASK (0x100U) #define MU_SR_FUP_SHIFT (8U) /*! FUP * 0b0..No flags updated, initiated by the Processor B, in progress (default) * 0b1..Processor B initiated flags update, processing */ #define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK) #define MU_SR_TEn_MASK (0xF00000U) #define MU_SR_TEn_SHIFT (20U) /*! TEn * 0b0000..BTRn register is not empty. * 0b0001..BTRn register is empty (default). */ #define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK) #define MU_SR_RFn_MASK (0xF000000U) #define MU_SR_RFn_SHIFT (24U) /*! RFn * 0b0000..BRRn register is not full (default). * 0b0001..BRRn register has received data from ATRn register and is ready to be read by the Processor B. */ #define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK) #define MU_SR_GIPn_MASK (0xF0000000U) #define MU_SR_GIPn_SHIFT (28U) /*! GIPn * 0b0000..Processor B general purpose interrupt n is not pending. (default) * 0b0001..Processor B general purpose interrupt n is pending. */ #define MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK) /*! @} */ /*! @name CR - Processor B Control Register */ /*! @{ */ #define MU_CR_BAFn_MASK (0x7U) #define MU_CR_BAFn_SHIFT (0U) /*! BAFn * 0b000..Clears the Fn bit in the ASR register. * 0b001..Sets the Fn bit in the ASR register. */ #define MU_CR_BAFn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_BAFn_SHIFT)) & MU_CR_BAFn_MASK) #define MU_CR_HRM_MASK (0x10U) #define MU_CR_HRM_SHIFT (4U) /*! HRM * 0b0..BHR bit in ACR is not masked, enables the hardware reset to the Processor B (default after hardware reset). * 0b1..BHR bit in ACR is masked, disables the hardware reset request to the Processor B. */ #define MU_CR_HRM(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_HRM_SHIFT)) & MU_CR_HRM_MASK) #define MU_CR_GIRn_MASK (0xF0000U) #define MU_CR_GIRn_SHIFT (16U) /*! GIRn * 0b0000..Processor B General Interrupt n is not requested to the Processor A (default). * 0b0001..Processor B General Interrupt n is requested to the Processor A. */ #define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK) #define MU_CR_TIEn_MASK (0xF00000U) #define MU_CR_TIEn_SHIFT (20U) /*! TIEn * 0b0000..Disables Processor B Transmit Interrupt n. (default) * 0b0001..Enables Processor B Transmit Interrupt n. */ #define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK) #define MU_CR_RIEn_MASK (0xF000000U) #define MU_CR_RIEn_SHIFT (24U) /*! RIEn * 0b0000..Disables Processor B Receive Interrupt n. (default) * 0b0001..Enables Processor B Receive Interrupt n. */ #define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK) #define MU_CR_GIEn_MASK (0xF0000000U) #define MU_CR_GIEn_SHIFT (28U) /*! GIEn * 0b0000..Disables Processor B General Interrupt n. (default) * 0b0001..Enables Processor B General Interrupt n. */ #define MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK) /*! @} */ /*! * @} */ /* end of group MU_Register_Masks */ /* MU - Peripheral instance base addresses */ /** Peripheral MUB base address */ #define MUB_BASE (0x30AB0000u) /** Peripheral MUB base pointer */ #define MUB ((MU_Type *)MUB_BASE) /** Array initializer of MU peripheral base addresses */ #define MU_BASE_ADDRS \ { \ MUB_BASE \ } /** Array initializer of MU peripheral base pointers */ #define MU_BASE_PTRS \ { \ MUB \ } /** Interrupt vectors for the MU peripheral type */ #define MU_IRQS \ { \ MU_M7_IRQn \ } /* Backward compatibility */ #define MU_SR_PM_MASK MU_SR_APM_MASK #define MU_SR_PM_SHIFT MU_SR_APM_SHIFT #define MU_SR_PM(x) MU_SR_APM(x) #define MU_SR_RS_MASK MU_SR_ARS_MASK #define MU_SR_RS_SHIFT MU_SR_ARS_SHIFT #define MU_SR_RS(x) MU_SR_ARS(x) #define MU_CR_Fn_MASK MU_CR_BAFn_MASK #define MU_CR_Fn_SHIFT MU_CR_BAFn_SHIFT #define MU_CR_Fn(x) MU_CR_BAFn(x) /*! * @} */ /* end of group MU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- OCOTP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer * @{ */ /** OCOTP - Register Layout Typedef */ typedef struct { __IO uint32_t HW_OCOTP_CTRL; /**< OTP Controller Control Register, offset: 0x0 */ __IO uint32_t HW_OCOTP_CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */ __IO uint32_t HW_OCOTP_CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */ __IO uint32_t HW_OCOTP_CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */ __IO uint32_t HW_OCOTP_TIMING; /**< OTP Controller Timing Register, offset: 0x10 */ uint8_t RESERVED_0[12]; __IO uint32_t HW_OCOTP_DATA; /**< OTP Controller Write Data Register, offset: 0x20 */ uint8_t RESERVED_1[12]; __IO uint32_t HW_OCOTP_READ_CTRL; /**< OTP Controller Write Data Register, offset: 0x30 */ uint8_t RESERVED_2[12]; __IO uint32_t HW_OCOTP_READ_FUSE_DATA; /**< OTP Controller Read Data Register, offset: 0x40 */ uint8_t RESERVED_3[12]; __IO uint32_t HW_OCOTP_SW_STICKY; /**< Sticky bit Register, offset: 0x50 */ uint8_t RESERVED_4[12]; __IO uint32_t HW_OCOTP_SCS; /**< Software Controllable Signals Register, offset: 0x60 */ __IO uint32_t HW_OCOTP_SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */ __IO uint32_t HW_OCOTP_SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */ __IO uint32_t HW_OCOTP_SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */ uint8_t RESERVED_5[32]; __I uint32_t HW_OCOTP_VERSION; /**< OTP Controller Version Register, offset: 0x90 */ uint8_t RESERVED_6[876]; __I uint32_t HW_OCOTP_LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */ uint8_t RESERVED_7[12]; __IO uint32_t HW_OCOTP_TESTER0; /**< Value of OTP Bank0 Word1 (Tester Info.), offset: 0x410 */ uint8_t RESERVED_8[12]; __IO uint32_t HW_OCOTP_TESTER1; /**< Value of OTP Bank0 Word2 (tester Info.), offset: 0x420 */ uint8_t RESERVED_9[12]; __IO uint32_t HW_OCOTP_TESTER2; /**< Value of OTP Bank0 Word3 (Tester Info.), offset: 0x430 */ uint8_t RESERVED_10[12]; __IO uint32_t HW_OCOTP_TESTER3; /**< Value of OTP Bank1 Word0 (Tester Info.), offset: 0x440 */ uint8_t RESERVED_11[12]; __IO uint32_t HW_OCOTP_TESTER4; /**< Value of OTP Bank1 Word1 (Tester Info.), offset: 0x450 */ uint8_t RESERVED_12[12]; __IO uint32_t HW_OCOTP_TESTER5; /**< Value of OTP Bank1 Word2 (Tester Info.), offset: 0x460 */ uint8_t RESERVED_13[12]; __IO uint32_t HW_OCOTP_BOOT_CFG0; /**< Value of OTP Bank1 Word3 (Boot Configuration Info.), offset: 0x470 */ uint8_t RESERVED_14[12]; __IO uint32_t HW_OCOTP_BOOT_CFG1; /**< Value of OTP Bank2 Word0 (Boot Configuration Info.), offset: 0x480 */ uint8_t RESERVED_15[12]; __IO uint32_t HW_OCOTP_BOOT_CFG2; /**< Value of OTP Bank2 Word1 (Boot Configuration Info.), offset: 0x490 */ uint8_t RESERVED_16[12]; __IO uint32_t HW_OCOTP_BOOT_CFG3; /**< Value of OTP Bank2 Word2 (Boot Configuration Info.), offset: 0x4A0 */ uint8_t RESERVED_17[12]; __IO uint32_t HW_OCOTP_BOOT_CFG4; /**< Value of OTP Bank2 Word3 (BOOT Configuration Info.), offset: 0x4B0 */ uint8_t RESERVED_18[12]; __IO uint32_t HW_OCOTP_MEM_TRIM0; /**< Value of OTP Bank3 Word0 (Memory Related Info.), offset: 0x4C0 */ uint8_t RESERVED_19[12]; __IO uint32_t HW_OCOTP_MEM_TRIM1; /**< Value of OTP Bank3 Word1 (Memory Related Info.), offset: 0x4D0 */ uint8_t RESERVED_20[12]; __IO uint32_t HW_OCOTP_ANA0; /**< Value of OTP Bank3 Word2 (Analog Info.), offset: 0x4E0 */ uint8_t RESERVED_21[12]; __IO uint32_t HW_OCOTP_ANA1; /**< Value of OTP Bank3 Word3 (Analog Info.), offset: 0x4F0 */ uint8_t RESERVED_22[140]; __IO uint32_t HW_OCOTP_SRK0; /**< Shadow Register for OTP Bank6 Word0 (SRK Hash), offset: 0x580 */ uint8_t RESERVED_23[12]; __IO uint32_t HW_OCOTP_SRK1; /**< Shadow Register for OTP Bank6 Word1 (SRK Hash), offset: 0x590 */ uint8_t RESERVED_24[12]; __IO uint32_t HW_OCOTP_SRK2; /**< Shadow Register for OTP Bank6 Word2 (SRK Hash), offset: 0x5A0 */ uint8_t RESERVED_25[12]; __IO uint32_t HW_OCOTP_SRK3; /**< Shadow Register for OTP Bank6 Word3 (SRK Hash), offset: 0x5B0 */ uint8_t RESERVED_26[12]; __IO uint32_t HW_OCOTP_SRK4; /**< Shadow Register for OTP Bank7 Word0 (SRK Hash), offset: 0x5C0 */ uint8_t RESERVED_27[12]; __IO uint32_t HW_OCOTP_SRK5; /**< Shadow Register for OTP Bank7 Word1 (SRK Hash), offset: 0x5D0 */ uint8_t RESERVED_28[12]; __IO uint32_t HW_OCOTP_SRK6; /**< Shadow Register for OTP Bank7 Word2 (SRK Hash), offset: 0x5E0 */ uint8_t RESERVED_29[12]; __IO uint32_t HW_OCOTP_SRK7; /**< Shadow Register for OTP Bank7 Word3 (SRK Hash), offset: 0x5F0 */ uint8_t RESERVED_30[12]; __IO uint32_t HW_OCOTP_SJC_RESP0; /**< Value of OTP Bank8 Word0 (Secure JTAG Response Field), offset: 0x600 */ uint8_t RESERVED_31[12]; __IO uint32_t HW_OCOTP_SJC_RESP1; /**< Value of OTP Bank8 Word1 (Secure JTAG Response Field), offset: 0x610 */ uint8_t RESERVED_32[12]; __IO uint32_t HW_OCOTP_USB_ID; /**< Value of OTP Bank8 Word2 (USB ID info), offset: 0x620 */ uint8_t RESERVED_33[12]; __IO uint32_t HW_OCOTP_FIELD_RETURN; /**< Value of OTP Bank5 Word6 (Field Return), offset: 0x630 */ uint8_t RESERVED_34[12]; __IO uint32_t HW_OCOTP_MAC_ADDR0; /**< Value of OTP Bank9 Word0 (MAC Address), offset: 0x640 */ uint8_t RESERVED_35[12]; __IO uint32_t HW_OCOTP_MAC_ADDR1; /**< Value of OTP Bank9 Word1 (MAC Address), offset: 0x650 */ uint8_t RESERVED_36[12]; __IO uint32_t HW_OCOTP_MAC_ADDR2; /**< Value of OTP Bank9 Word2 (MAC Address), offset: 0x660 */ uint8_t RESERVED_37[12]; __IO uint32_t HW_OCOTP_SRK_REVOKE; /**< Value of OTP Bank9 Word3 (SRK Revoke), offset: 0x670 */ uint8_t RESERVED_38[12]; __IO uint32_t HW_OCOTP_MAU_KEY0; /**< Shadow Register for OTP Bank10 Word0 (MAU Key), offset: 0x680 */ uint8_t RESERVED_39[12]; __IO uint32_t HW_OCOTP_MAU_KEY1; /**< Shadow Register for OTP Bank10 Word1 (MAU Key), offset: 0x690 */ uint8_t RESERVED_40[12]; __IO uint32_t HW_OCOTP_MAU_KEY2; /**< Shadow Register for OTP Bank10 Word2 (MAU Key), offset: 0x6A0 */ uint8_t RESERVED_41[12]; __IO uint32_t HW_OCOTP_MAU_KEY3; /**< Shadow Register for OTP Bank10 Word3 (MAU Key), offset: 0x6B0 */ uint8_t RESERVED_42[12]; __IO uint32_t HW_OCOTP_MAU_KEY4; /**< Shadow Register for OTP Bank11 Word0 (MAU Key), offset: 0x6C0 */ uint8_t RESERVED_43[12]; __IO uint32_t HW_OCOTP_MAU_KEY5; /**< Shadow Register for OTP Bank11 Word1 (MAU Key), offset: 0x6D0 */ uint8_t RESERVED_44[12]; __IO uint32_t HW_OCOTP_MAU_KEY6; /**< Shadow Register for OTP Bank11 Word2 (MAU Key), offset: 0x6E0 */ uint8_t RESERVED_45[12]; __IO uint32_t HW_OCOTP_MAU_KEY7; /**< Shadow Register for OTP Bank11 Word3 (MAU Key), offset: 0x6F0 */ uint8_t RESERVED_46[140]; __IO uint32_t HW_OCOTP_GP10; /**< Value of OTP Bank14 Word0 (), offset: 0x780 */ uint8_t RESERVED_47[12]; __IO uint32_t HW_OCOTP_GP11; /**< Value of OTP Bank14 Word1 (), offset: 0x790 */ uint8_t RESERVED_48[12]; __IO uint32_t HW_OCOTP_GP20; /**< Value of OTP Bank14 Word2 (), offset: 0x7A0 */ uint8_t RESERVED_49[12]; __IO uint32_t HW_OCOTP_GP21; /**< Value of OTP Bank14 Word3 (), offset: 0x7B0 */ } OCOTP_Type; /* ---------------------------------------------------------------------------- -- OCOTP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup OCOTP_Register_Masks OCOTP Register Masks * @{ */ /*! @name HW_OCOTP_CTRL - OTP Controller Control Register */ /*! @{ */ #define OCOTP_HW_OCOTP_CTRL_ADDR_MASK (0xFFU) #define OCOTP_HW_OCOTP_CTRL_ADDR_SHIFT (0U) #define OCOTP_HW_OCOTP_CTRL_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_ADDR_MASK) #define OCOTP_HW_OCOTP_CTRL_BUSY_MASK (0x100U) #define OCOTP_HW_OCOTP_CTRL_BUSY_SHIFT (8U) #define OCOTP_HW_OCOTP_CTRL_BUSY(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_HW_OCOTP_CTRL_BUSY_MASK) #define OCOTP_HW_OCOTP_CTRL_ERROR_MASK (0x200U) #define OCOTP_HW_OCOTP_CTRL_ERROR_SHIFT (9U) #define OCOTP_HW_OCOTP_CTRL_ERROR(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_ERROR_MASK) #define OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U) #define OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U) #define OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & \ OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS_MASK) #define OCOTP_HW_OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) #define OCOTP_HW_OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) #define OCOTP_HW_OCOTP_CTRL_WR_UNLOCK(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_HW_OCOTP_CTRL_WR_UNLOCK_MASK) /*! @} */ /*! @name HW_OCOTP_CTRL_SET - OTP Controller Control Register */ /*! @{ */ #define OCOTP_HW_OCOTP_CTRL_SET_ADDR_MASK (0xFFU) #define OCOTP_HW_OCOTP_CTRL_SET_ADDR_SHIFT (0U) #define OCOTP_HW_OCOTP_CTRL_SET_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_SET_ADDR_MASK) #define OCOTP_HW_OCOTP_CTRL_SET_BUSY_MASK (0x100U) #define OCOTP_HW_OCOTP_CTRL_SET_BUSY_SHIFT (8U) #define OCOTP_HW_OCOTP_CTRL_SET_BUSY(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_HW_OCOTP_CTRL_SET_BUSY_MASK) #define OCOTP_HW_OCOTP_CTRL_SET_ERROR_MASK (0x200U) #define OCOTP_HW_OCOTP_CTRL_SET_ERROR_SHIFT (9U) #define OCOTP_HW_OCOTP_CTRL_SET_ERROR(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_SET_ERROR_MASK) #define OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U) #define OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U) #define OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & \ OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK) #define OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) #define OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) #define OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK_MASK) /*! @} */ /*! @name HW_OCOTP_CTRL_CLR - OTP Controller Control Register */ /*! @{ */ #define OCOTP_HW_OCOTP_CTRL_CLR_ADDR_MASK (0xFFU) #define OCOTP_HW_OCOTP_CTRL_CLR_ADDR_SHIFT (0U) #define OCOTP_HW_OCOTP_CTRL_CLR_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_CLR_ADDR_MASK) #define OCOTP_HW_OCOTP_CTRL_CLR_BUSY_MASK (0x100U) #define OCOTP_HW_OCOTP_CTRL_CLR_BUSY_SHIFT (8U) #define OCOTP_HW_OCOTP_CTRL_CLR_BUSY(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_HW_OCOTP_CTRL_CLR_BUSY_MASK) #define OCOTP_HW_OCOTP_CTRL_CLR_ERROR_MASK (0x200U) #define OCOTP_HW_OCOTP_CTRL_CLR_ERROR_SHIFT (9U) #define OCOTP_HW_OCOTP_CTRL_CLR_ERROR(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_CLR_ERROR_MASK) #define OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U) #define OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U) #define OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & \ OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK) #define OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) #define OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) #define OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK_MASK) /*! @} */ /*! @name HW_OCOTP_CTRL_TOG - OTP Controller Control Register */ /*! @{ */ #define OCOTP_HW_OCOTP_CTRL_TOG_ADDR_MASK (0xFFU) #define OCOTP_HW_OCOTP_CTRL_TOG_ADDR_SHIFT (0U) #define OCOTP_HW_OCOTP_CTRL_TOG_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_TOG_ADDR_MASK) #define OCOTP_HW_OCOTP_CTRL_TOG_BUSY_MASK (0x100U) #define OCOTP_HW_OCOTP_CTRL_TOG_BUSY_SHIFT (8U) #define OCOTP_HW_OCOTP_CTRL_TOG_BUSY(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_HW_OCOTP_CTRL_TOG_BUSY_MASK) #define OCOTP_HW_OCOTP_CTRL_TOG_ERROR_MASK (0x200U) #define OCOTP_HW_OCOTP_CTRL_TOG_ERROR_SHIFT (9U) #define OCOTP_HW_OCOTP_CTRL_TOG_ERROR(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_TOG_ERROR_MASK) #define OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U) #define OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U) #define OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & \ OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK) #define OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) #define OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) #define OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK_MASK) /*! @} */ /*! @name HW_OCOTP_TIMING - OTP Controller Timing Register */ /*! @{ */ #define OCOTP_HW_OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU) #define OCOTP_HW_OCOTP_TIMING_STROBE_PROG_SHIFT (0U) #define OCOTP_HW_OCOTP_TIMING_STROBE_PROG(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_HW_OCOTP_TIMING_STROBE_PROG_MASK) #define OCOTP_HW_OCOTP_TIMING_RELAX_MASK (0xF000U) #define OCOTP_HW_OCOTP_TIMING_RELAX_SHIFT (12U) #define OCOTP_HW_OCOTP_TIMING_RELAX(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_HW_OCOTP_TIMING_RELAX_MASK) #define OCOTP_HW_OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U) #define OCOTP_HW_OCOTP_TIMING_STROBE_READ_SHIFT (16U) #define OCOTP_HW_OCOTP_TIMING_STROBE_READ(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_HW_OCOTP_TIMING_STROBE_READ_MASK) #define OCOTP_HW_OCOTP_TIMING_WAIT_MASK (0xFC00000U) #define OCOTP_HW_OCOTP_TIMING_WAIT_SHIFT (22U) #define OCOTP_HW_OCOTP_TIMING_WAIT(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_HW_OCOTP_TIMING_WAIT_MASK) #define OCOTP_HW_OCOTP_TIMING_RSRVD0_MASK (0xF0000000U) #define OCOTP_HW_OCOTP_TIMING_RSRVD0_SHIFT (28U) #define OCOTP_HW_OCOTP_TIMING_RSRVD0(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TIMING_RSRVD0_SHIFT)) & OCOTP_HW_OCOTP_TIMING_RSRVD0_MASK) /*! @} */ /*! @name HW_OCOTP_DATA - OTP Controller Write Data Register */ /*! @{ */ #define OCOTP_HW_OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_DATA_DATA_SHIFT (0U) #define OCOTP_HW_OCOTP_DATA_DATA(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_DATA_DATA_SHIFT)) & OCOTP_HW_OCOTP_DATA_DATA_MASK) /*! @} */ /*! @name HW_OCOTP_READ_CTRL - OTP Controller Write Data Register */ /*! @{ */ #define OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) #define OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) #define OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & \ OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE_MASK) #define OCOTP_HW_OCOTP_READ_CTRL_RSVD0_MASK (0xFFFFFFFEU) #define OCOTP_HW_OCOTP_READ_CTRL_RSVD0_SHIFT (1U) #define OCOTP_HW_OCOTP_READ_CTRL_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_READ_CTRL_RSVD0_SHIFT)) & OCOTP_HW_OCOTP_READ_CTRL_RSVD0_MASK) /*! @} */ /*! @name HW_OCOTP_READ_FUSE_DATA - OTP Controller Read Data Register */ /*! @{ */ #define OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) #define OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & \ OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA_MASK) /*! @} */ /*! @name HW_OCOTP_SW_STICKY - Sticky bit Register */ /*! @{ */ #define OCOTP_HW_OCOTP_SW_STICKY_RSVD0_MASK (0x1U) #define OCOTP_HW_OCOTP_SW_STICKY_RSVD0_SHIFT (0U) #define OCOTP_HW_OCOTP_SW_STICKY_RSVD0(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_RSVD0_SHIFT)) & OCOTP_HW_OCOTP_SW_STICKY_RSVD0_MASK) #define OCOTP_HW_OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U) #define OCOTP_HW_OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U) #define OCOTP_HW_OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & \ OCOTP_HW_OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK) #define OCOTP_HW_OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U) #define OCOTP_HW_OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U) #define OCOTP_HW_OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & \ OCOTP_HW_OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK) #define OCOTP_HW_OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U) #define OCOTP_HW_OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U) #define OCOTP_HW_OCOTP_SW_STICKY_BLOCK_ROM_PART(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & \ OCOTP_HW_OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK) #define OCOTP_HW_OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U) #define OCOTP_HW_OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U) #define OCOTP_HW_OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & \ OCOTP_HW_OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK) #define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_MASK (0x20U) #define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_SHIFT (5U) #define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_SHIFT)) & \ OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_MASK) #define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_MASK (0x40U) #define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_SHIFT (6U) #define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_SHIFT)) & \ OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_MASK) #define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_MASK (0x80U) #define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_SHIFT (7U) #define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_SHIFT)) & \ OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_MASK) #define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_MASK (0x100U) #define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_SHIFT (8U) #define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_SHIFT)) & \ OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_MASK) #define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_MASK (0x200U) #define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_SHIFT (9U) #define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_SHIFT)) & \ OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_MASK) #define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_MASK (0x400U) #define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_SHIFT (10U) #define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_SHIFT)) & \ OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_MASK) #define OCOTP_HW_OCOTP_SW_STICKY_RSVD1_MASK (0xFFFFF800U) #define OCOTP_HW_OCOTP_SW_STICKY_RSVD1_SHIFT (11U) #define OCOTP_HW_OCOTP_SW_STICKY_RSVD1(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_RSVD1_SHIFT)) & OCOTP_HW_OCOTP_SW_STICKY_RSVD1_MASK) /*! @} */ /*! @name HW_OCOTP_SCS - Software Controllable Signals Register */ /*! @{ */ #define OCOTP_HW_OCOTP_SCS_HAB_JDE_MASK (0x1U) #define OCOTP_HW_OCOTP_SCS_HAB_JDE_SHIFT (0U) #define OCOTP_HW_OCOTP_SCS_HAB_JDE(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_HW_OCOTP_SCS_HAB_JDE_MASK) #define OCOTP_HW_OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU) #define OCOTP_HW_OCOTP_SCS_SPARE_SHIFT (1U) #define OCOTP_HW_OCOTP_SCS_SPARE(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_SPARE_SHIFT)) & OCOTP_HW_OCOTP_SCS_SPARE_MASK) #define OCOTP_HW_OCOTP_SCS_LOCK_MASK (0x80000000U) #define OCOTP_HW_OCOTP_SCS_LOCK_SHIFT (31U) #define OCOTP_HW_OCOTP_SCS_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_LOCK_SHIFT)) & OCOTP_HW_OCOTP_SCS_LOCK_MASK) /*! @} */ /*! @name HW_OCOTP_SCS_SET - Software Controllable Signals Register */ /*! @{ */ #define OCOTP_HW_OCOTP_SCS_SET_HAB_JDE_MASK (0x1U) #define OCOTP_HW_OCOTP_SCS_SET_HAB_JDE_SHIFT (0U) #define OCOTP_HW_OCOTP_SCS_SET_HAB_JDE(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_HW_OCOTP_SCS_SET_HAB_JDE_MASK) #define OCOTP_HW_OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU) #define OCOTP_HW_OCOTP_SCS_SET_SPARE_SHIFT (1U) #define OCOTP_HW_OCOTP_SCS_SET_SPARE(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_HW_OCOTP_SCS_SET_SPARE_MASK) #define OCOTP_HW_OCOTP_SCS_SET_LOCK_MASK (0x80000000U) #define OCOTP_HW_OCOTP_SCS_SET_LOCK_SHIFT (31U) #define OCOTP_HW_OCOTP_SCS_SET_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_HW_OCOTP_SCS_SET_LOCK_MASK) /*! @} */ /*! @name HW_OCOTP_SCS_CLR - Software Controllable Signals Register */ /*! @{ */ #define OCOTP_HW_OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U) #define OCOTP_HW_OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U) #define OCOTP_HW_OCOTP_SCS_CLR_HAB_JDE(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_HW_OCOTP_SCS_CLR_HAB_JDE_MASK) #define OCOTP_HW_OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU) #define OCOTP_HW_OCOTP_SCS_CLR_SPARE_SHIFT (1U) #define OCOTP_HW_OCOTP_SCS_CLR_SPARE(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_HW_OCOTP_SCS_CLR_SPARE_MASK) #define OCOTP_HW_OCOTP_SCS_CLR_LOCK_MASK (0x80000000U) #define OCOTP_HW_OCOTP_SCS_CLR_LOCK_SHIFT (31U) #define OCOTP_HW_OCOTP_SCS_CLR_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_HW_OCOTP_SCS_CLR_LOCK_MASK) /*! @} */ /*! @name HW_OCOTP_SCS_TOG - Software Controllable Signals Register */ /*! @{ */ #define OCOTP_HW_OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U) #define OCOTP_HW_OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U) #define OCOTP_HW_OCOTP_SCS_TOG_HAB_JDE(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_HW_OCOTP_SCS_TOG_HAB_JDE_MASK) #define OCOTP_HW_OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU) #define OCOTP_HW_OCOTP_SCS_TOG_SPARE_SHIFT (1U) #define OCOTP_HW_OCOTP_SCS_TOG_SPARE(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_HW_OCOTP_SCS_TOG_SPARE_MASK) #define OCOTP_HW_OCOTP_SCS_TOG_LOCK_MASK (0x80000000U) #define OCOTP_HW_OCOTP_SCS_TOG_LOCK_SHIFT (31U) #define OCOTP_HW_OCOTP_SCS_TOG_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_HW_OCOTP_SCS_TOG_LOCK_MASK) /*! @} */ /*! @name HW_OCOTP_VERSION - OTP Controller Version Register */ /*! @{ */ #define OCOTP_HW_OCOTP_VERSION_STEP_MASK (0xFFFFU) #define OCOTP_HW_OCOTP_VERSION_STEP_SHIFT (0U) #define OCOTP_HW_OCOTP_VERSION_STEP(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_VERSION_STEP_SHIFT)) & OCOTP_HW_OCOTP_VERSION_STEP_MASK) #define OCOTP_HW_OCOTP_VERSION_MINOR_MASK (0xFF0000U) #define OCOTP_HW_OCOTP_VERSION_MINOR_SHIFT (16U) #define OCOTP_HW_OCOTP_VERSION_MINOR(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_HW_OCOTP_VERSION_MINOR_MASK) #define OCOTP_HW_OCOTP_VERSION_MAJOR_MASK (0xFF000000U) #define OCOTP_HW_OCOTP_VERSION_MAJOR_SHIFT (24U) #define OCOTP_HW_OCOTP_VERSION_MAJOR(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_HW_OCOTP_VERSION_MAJOR_MASK) /*! @} */ /*! @name HW_OCOTP_LOCK - Value of OTP Bank0 Word0 (Lock controls) */ /*! @{ */ #define OCOTP_HW_OCOTP_LOCK_TESTER_MASK (0x3U) #define OCOTP_HW_OCOTP_LOCK_TESTER_SHIFT (0U) #define OCOTP_HW_OCOTP_LOCK_TESTER(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_HW_OCOTP_LOCK_TESTER_MASK) #define OCOTP_HW_OCOTP_LOCK_BOOT_CFG_MASK (0xCU) #define OCOTP_HW_OCOTP_LOCK_BOOT_CFG_SHIFT (2U) #define OCOTP_HW_OCOTP_LOCK_BOOT_CFG(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_HW_OCOTP_LOCK_BOOT_CFG_MASK) #define OCOTP_HW_OCOTP_LOCK_SRK_MASK (0x200U) #define OCOTP_HW_OCOTP_LOCK_SRK_SHIFT (9U) #define OCOTP_HW_OCOTP_LOCK_SRK(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_SRK_SHIFT)) & OCOTP_HW_OCOTP_LOCK_SRK_MASK) #define OCOTP_HW_OCOTP_LOCK_SJC_RESP_MASK (0x400U) #define OCOTP_HW_OCOTP_LOCK_SJC_RESP_SHIFT (10U) #define OCOTP_HW_OCOTP_LOCK_SJC_RESP(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_HW_OCOTP_LOCK_SJC_RESP_MASK) #define OCOTP_HW_OCOTP_LOCK_USB_ID_MASK (0x3000U) #define OCOTP_HW_OCOTP_LOCK_USB_ID_SHIFT (12U) #define OCOTP_HW_OCOTP_LOCK_USB_ID(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_USB_ID_SHIFT)) & OCOTP_HW_OCOTP_LOCK_USB_ID_MASK) #define OCOTP_HW_OCOTP_LOCK_MAC_ADDR_MASK (0xC000U) #define OCOTP_HW_OCOTP_LOCK_MAC_ADDR_SHIFT (14U) #define OCOTP_HW_OCOTP_LOCK_MAC_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_HW_OCOTP_LOCK_MAC_ADDR_MASK) #define OCOTP_HW_OCOTP_LOCK_GP1_MASK (0x300000U) #define OCOTP_HW_OCOTP_LOCK_GP1_SHIFT (20U) #define OCOTP_HW_OCOTP_LOCK_GP1(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_GP1_SHIFT)) & OCOTP_HW_OCOTP_LOCK_GP1_MASK) #define OCOTP_HW_OCOTP_LOCK_GP2_MASK (0xC00000U) #define OCOTP_HW_OCOTP_LOCK_GP2_SHIFT (22U) #define OCOTP_HW_OCOTP_LOCK_GP2(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_GP2_SHIFT)) & OCOTP_HW_OCOTP_LOCK_GP2_MASK) /*! @} */ /*! @name HW_OCOTP_TESTER0 - Value of OTP Bank0 Word1 (Tester Info.) */ /*! @{ */ #define OCOTP_HW_OCOTP_TESTER0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_TESTER0_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_TESTER0_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TESTER0_BITS_SHIFT)) & OCOTP_HW_OCOTP_TESTER0_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_TESTER1 - Value of OTP Bank0 Word2 (tester Info.) */ /*! @{ */ #define OCOTP_HW_OCOTP_TESTER1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_TESTER1_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_TESTER1_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TESTER1_BITS_SHIFT)) & OCOTP_HW_OCOTP_TESTER1_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_TESTER2 - Value of OTP Bank0 Word3 (Tester Info.) */ /*! @{ */ #define OCOTP_HW_OCOTP_TESTER2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_TESTER2_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_TESTER2_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TESTER2_BITS_SHIFT)) & OCOTP_HW_OCOTP_TESTER2_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_TESTER3 - Value of OTP Bank1 Word0 (Tester Info.) */ /*! @{ */ #define OCOTP_HW_OCOTP_TESTER3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_TESTER3_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_TESTER3_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TESTER3_BITS_SHIFT)) & OCOTP_HW_OCOTP_TESTER3_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_TESTER4 - Value of OTP Bank1 Word1 (Tester Info.) */ /*! @{ */ #define OCOTP_HW_OCOTP_TESTER4_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_TESTER4_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_TESTER4_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TESTER4_BITS_SHIFT)) & OCOTP_HW_OCOTP_TESTER4_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_TESTER5 - Value of OTP Bank1 Word2 (Tester Info.) */ /*! @{ */ #define OCOTP_HW_OCOTP_TESTER5_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_TESTER5_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_TESTER5_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TESTER5_BITS_SHIFT)) & OCOTP_HW_OCOTP_TESTER5_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_BOOT_CFG0 - Value of OTP Bank1 Word3 (Boot Configuration Info.) */ /*! @{ */ #define OCOTP_HW_OCOTP_BOOT_CFG0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_BOOT_CFG0_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_BOOT_CFG0_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG0_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG0_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_BOOT_CFG1 - Value of OTP Bank2 Word0 (Boot Configuration Info.) */ /*! @{ */ #define OCOTP_HW_OCOTP_BOOT_CFG1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_BOOT_CFG1_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_BOOT_CFG1_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG1_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG1_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_BOOT_CFG2 - Value of OTP Bank2 Word1 (Boot Configuration Info.) */ /*! @{ */ #define OCOTP_HW_OCOTP_BOOT_CFG2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_BOOT_CFG2_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_BOOT_CFG2_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG2_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG2_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_BOOT_CFG3 - Value of OTP Bank2 Word2 (Boot Configuration Info.) */ /*! @{ */ #define OCOTP_HW_OCOTP_BOOT_CFG3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_BOOT_CFG3_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_BOOT_CFG3_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG3_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG3_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_BOOT_CFG4 - Value of OTP Bank2 Word3 (BOOT Configuration Info.) */ /*! @{ */ #define OCOTP_HW_OCOTP_BOOT_CFG4_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_BOOT_CFG4_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_BOOT_CFG4_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG4_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG4_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_MEM_TRIM0 - Value of OTP Bank3 Word0 (Memory Related Info.) */ /*! @{ */ #define OCOTP_HW_OCOTP_MEM_TRIM0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_MEM_TRIM0_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_MEM_TRIM0_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MEM_TRIM0_BITS_SHIFT)) & OCOTP_HW_OCOTP_MEM_TRIM0_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_MEM_TRIM1 - Value of OTP Bank3 Word1 (Memory Related Info.) */ /*! @{ */ #define OCOTP_HW_OCOTP_MEM_TRIM1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_MEM_TRIM1_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_MEM_TRIM1_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MEM_TRIM1_BITS_SHIFT)) & OCOTP_HW_OCOTP_MEM_TRIM1_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_ANA0 - Value of OTP Bank3 Word2 (Analog Info.) */ /*! @{ */ #define OCOTP_HW_OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_ANA0_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_ANA0_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_ANA0_BITS_SHIFT)) & OCOTP_HW_OCOTP_ANA0_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_ANA1 - Value of OTP Bank3 Word3 (Analog Info.) */ /*! @{ */ #define OCOTP_HW_OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_ANA1_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_ANA1_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_ANA1_BITS_SHIFT)) & OCOTP_HW_OCOTP_ANA1_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_SRK0 - Shadow Register for OTP Bank6 Word0 (SRK Hash) */ /*! @{ */ #define OCOTP_HW_OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_SRK0_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_SRK0_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SRK0_BITS_SHIFT)) & OCOTP_HW_OCOTP_SRK0_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_SRK1 - Shadow Register for OTP Bank6 Word1 (SRK Hash) */ /*! @{ */ #define OCOTP_HW_OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_SRK1_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_SRK1_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SRK1_BITS_SHIFT)) & OCOTP_HW_OCOTP_SRK1_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_SRK2 - Shadow Register for OTP Bank6 Word2 (SRK Hash) */ /*! @{ */ #define OCOTP_HW_OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_SRK2_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_SRK2_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SRK2_BITS_SHIFT)) & OCOTP_HW_OCOTP_SRK2_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_SRK3 - Shadow Register for OTP Bank6 Word3 (SRK Hash) */ /*! @{ */ #define OCOTP_HW_OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_SRK3_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_SRK3_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SRK3_BITS_SHIFT)) & OCOTP_HW_OCOTP_SRK3_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_SRK4 - Shadow Register for OTP Bank7 Word0 (SRK Hash) */ /*! @{ */ #define OCOTP_HW_OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_SRK4_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_SRK4_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SRK4_BITS_SHIFT)) & OCOTP_HW_OCOTP_SRK4_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_SRK5 - Shadow Register for OTP Bank7 Word1 (SRK Hash) */ /*! @{ */ #define OCOTP_HW_OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_SRK5_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_SRK5_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SRK5_BITS_SHIFT)) & OCOTP_HW_OCOTP_SRK5_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_SRK6 - Shadow Register for OTP Bank7 Word2 (SRK Hash) */ /*! @{ */ #define OCOTP_HW_OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_SRK6_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_SRK6_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SRK6_BITS_SHIFT)) & OCOTP_HW_OCOTP_SRK6_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_SRK7 - Shadow Register for OTP Bank7 Word3 (SRK Hash) */ /*! @{ */ #define OCOTP_HW_OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_SRK7_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_SRK7_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SRK7_BITS_SHIFT)) & OCOTP_HW_OCOTP_SRK7_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_SJC_RESP0 - Value of OTP Bank8 Word0 (Secure JTAG Response Field) */ /*! @{ */ #define OCOTP_HW_OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_SJC_RESP0_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_SJC_RESP0_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_HW_OCOTP_SJC_RESP0_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_SJC_RESP1 - Value of OTP Bank8 Word1 (Secure JTAG Response Field) */ /*! @{ */ #define OCOTP_HW_OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_SJC_RESP1_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_SJC_RESP1_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_HW_OCOTP_SJC_RESP1_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_USB_ID - Value of OTP Bank8 Word2 (USB ID info) */ /*! @{ */ #define OCOTP_HW_OCOTP_USB_ID_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_USB_ID_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_USB_ID_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_USB_ID_BITS_SHIFT)) & OCOTP_HW_OCOTP_USB_ID_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_FIELD_RETURN - Value of OTP Bank5 Word6 (Field Return) */ /*! @{ */ #define OCOTP_HW_OCOTP_FIELD_RETURN_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_FIELD_RETURN_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_FIELD_RETURN_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_FIELD_RETURN_BITS_SHIFT)) & OCOTP_HW_OCOTP_FIELD_RETURN_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_MAC_ADDR0 - Value of OTP Bank9 Word0 (MAC Address) */ /*! @{ */ #define OCOTP_HW_OCOTP_MAC_ADDR0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_MAC_ADDR0_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_MAC_ADDR0_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAC_ADDR0_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAC_ADDR0_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_MAC_ADDR1 - Value of OTP Bank9 Word1 (MAC Address) */ /*! @{ */ #define OCOTP_HW_OCOTP_MAC_ADDR1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_MAC_ADDR1_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_MAC_ADDR1_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAC_ADDR1_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAC_ADDR1_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_MAC_ADDR2 - Value of OTP Bank9 Word2 (MAC Address) */ /*! @{ */ #define OCOTP_HW_OCOTP_MAC_ADDR2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_MAC_ADDR2_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_MAC_ADDR2_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAC_ADDR2_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAC_ADDR2_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_SRK_REVOKE - Value of OTP Bank9 Word3 (SRK Revoke) */ /*! @{ */ #define OCOTP_HW_OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_SRK_REVOKE_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_SRK_REVOKE_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_HW_OCOTP_SRK_REVOKE_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_MAU_KEY0 - Shadow Register for OTP Bank10 Word0 (MAU Key) */ /*! @{ */ #define OCOTP_HW_OCOTP_MAU_KEY0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_MAU_KEY0_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_MAU_KEY0_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAU_KEY0_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAU_KEY0_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_MAU_KEY1 - Shadow Register for OTP Bank10 Word1 (MAU Key) */ /*! @{ */ #define OCOTP_HW_OCOTP_MAU_KEY1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_MAU_KEY1_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_MAU_KEY1_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAU_KEY1_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAU_KEY1_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_MAU_KEY2 - Shadow Register for OTP Bank10 Word2 (MAU Key) */ /*! @{ */ #define OCOTP_HW_OCOTP_MAU_KEY2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_MAU_KEY2_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_MAU_KEY2_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAU_KEY2_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAU_KEY2_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_MAU_KEY3 - Shadow Register for OTP Bank10 Word3 (MAU Key) */ /*! @{ */ #define OCOTP_HW_OCOTP_MAU_KEY3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_MAU_KEY3_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_MAU_KEY3_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAU_KEY3_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAU_KEY3_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_MAU_KEY4 - Shadow Register for OTP Bank11 Word0 (MAU Key) */ /*! @{ */ #define OCOTP_HW_OCOTP_MAU_KEY4_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_MAU_KEY4_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_MAU_KEY4_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAU_KEY4_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAU_KEY4_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_MAU_KEY5 - Shadow Register for OTP Bank11 Word1 (MAU Key) */ /*! @{ */ #define OCOTP_HW_OCOTP_MAU_KEY5_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_MAU_KEY5_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_MAU_KEY5_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAU_KEY5_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAU_KEY5_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_MAU_KEY6 - Shadow Register for OTP Bank11 Word2 (MAU Key) */ /*! @{ */ #define OCOTP_HW_OCOTP_MAU_KEY6_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_MAU_KEY6_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_MAU_KEY6_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAU_KEY6_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAU_KEY6_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_MAU_KEY7 - Shadow Register for OTP Bank11 Word3 (MAU Key) */ /*! @{ */ #define OCOTP_HW_OCOTP_MAU_KEY7_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_MAU_KEY7_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_MAU_KEY7_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAU_KEY7_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAU_KEY7_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP10 - Value of OTP Bank14 Word0 () */ /*! @{ */ #define OCOTP_HW_OCOTP_GP10_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_GP10_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_GP10_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_GP10_BITS_SHIFT)) & OCOTP_HW_OCOTP_GP10_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP11 - Value of OTP Bank14 Word1 () */ /*! @{ */ #define OCOTP_HW_OCOTP_GP11_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_GP11_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_GP11_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_GP11_BITS_SHIFT)) & OCOTP_HW_OCOTP_GP11_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP20 - Value of OTP Bank14 Word2 () */ /*! @{ */ #define OCOTP_HW_OCOTP_GP20_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_GP20_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_GP20_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_GP20_BITS_SHIFT)) & OCOTP_HW_OCOTP_GP20_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP21 - Value of OTP Bank14 Word3 () */ /*! @{ */ #define OCOTP_HW_OCOTP_GP21_BITS_MASK (0xFFFFFFFFU) #define OCOTP_HW_OCOTP_GP21_BITS_SHIFT (0U) #define OCOTP_HW_OCOTP_GP21_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_GP21_BITS_SHIFT)) & OCOTP_HW_OCOTP_GP21_BITS_MASK) /*! @} */ /*! * @} */ /* end of group OCOTP_Register_Masks */ /* OCOTP - Peripheral instance base addresses */ /** Peripheral OCOTP base address */ #define OCOTP_BASE (0x30350000u) /** Peripheral OCOTP base pointer */ #define OCOTP ((OCOTP_Type *)OCOTP_BASE) /** Array initializer of OCOTP peripheral base addresses */ #define OCOTP_BASE_ADDRS \ { \ OCOTP_BASE \ } /** Array initializer of OCOTP peripheral base pointers */ #define OCOTP_BASE_PTRS \ { \ OCOTP \ } /*! * @} */ /* end of group OCOTP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PDM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer * @{ */ /** PDM - Register Layout Typedef */ typedef struct { __IO uint32_t CTRL_1; /**< MICFIL Control register 1, offset: 0x0 */ __IO uint32_t CTRL_2; /**< MICFIL Control register 2, offset: 0x4 */ __IO uint32_t STAT; /**< MICFIL Status register, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t FIFO_CTRL; /**< MICFIL FIFO Control register, offset: 0x10 */ __IO uint32_t FIFO_STAT; /**< MICFIL FIFO Status register, offset: 0x14 */ uint8_t RESERVED_1[12]; __I uint32_t DATACH[8]; /**< MICFIL Output Result Register, array offset: 0x24, array step: 0x4 */ uint8_t RESERVED_2[32]; __IO uint32_t DC_CTRL; /**< MICFIL DC Remover Control register, offset: 0x64 */ uint8_t RESERVED_3[12]; __IO uint32_t OUT_CTRL; /**< MICFIL Output Control register, offset: 0x74 */ uint8_t RESERVED_4[4]; __IO uint32_t OUT_STAT; /**< MICFIL Output Status register, offset: 0x7C */ uint8_t RESERVED_5[16]; __IO uint32_t VAD0_CTRL_1; /**< Voice Activity Detector 0 Control register, offset: 0x90 */ __IO uint32_t VAD0_CTRL_2; /**< Voice Activity Detector 0 Control register, offset: 0x94 */ __IO uint32_t VAD0_STAT; /**< Voice Activity Detector 0 Status register, offset: 0x98 */ __IO uint32_t VAD0_SCONFIG; /**< Voice Activity Detector 0 Signal Configuration, offset: 0x9C */ __IO uint32_t VAD0_NCONFIG; /**< Voice Activity Detector 0 Noise Configuration, offset: 0xA0 */ __I uint32_t VAD0_NDATA; /**< Voice Activity Detector 0 Noise Data, offset: 0xA4 */ __IO uint32_t VAD0_ZCD; /**< Voice Activity Detector 0 Zero-Crossing Detector, offset: 0xA8 */ } PDM_Type; /* ---------------------------------------------------------------------------- -- PDM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PDM_Register_Masks PDM Register Masks * @{ */ /*! @name CTRL_1 - MICFIL Control register 1 */ /*! @{ */ #define PDM_CTRL_1_CH0EN_MASK (0x1U) #define PDM_CTRL_1_CH0EN_SHIFT (0U) /*! CH0EN - Channel 0 Enable * 0b0..Channel 0 disabled * 0b1..Channel 0 enabled */ #define PDM_CTRL_1_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK) #define PDM_CTRL_1_CH1EN_MASK (0x2U) #define PDM_CTRL_1_CH1EN_SHIFT (1U) /*! CH1EN - Channel 1 Enable * 0b0..Channel 1 disabled * 0b1..Channel 1 enabled */ #define PDM_CTRL_1_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK) #define PDM_CTRL_1_CH2EN_MASK (0x4U) #define PDM_CTRL_1_CH2EN_SHIFT (2U) /*! CH2EN - Channel 2 Enable * 0b0..Channel 2 enabled * 0b1..Channel 2 disabled */ #define PDM_CTRL_1_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK) #define PDM_CTRL_1_CH3EN_MASK (0x8U) #define PDM_CTRL_1_CH3EN_SHIFT (3U) /*! CH3EN - Channel 3 Enable * 0b0..Channel 3 disabled * 0b1..Channel 3 enabled */ #define PDM_CTRL_1_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK) #define PDM_CTRL_1_CH4EN_MASK (0x10U) #define PDM_CTRL_1_CH4EN_SHIFT (4U) /*! CH4EN - Channel 4 Enable * 0b0..Channel 4 disabled * 0b1..Channel 4 enabled */ #define PDM_CTRL_1_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK) #define PDM_CTRL_1_CH5EN_MASK (0x20U) #define PDM_CTRL_1_CH5EN_SHIFT (5U) /*! CH5EN - Channel 5 Enable * 0b0..Channel 5 disabled * 0b1..Channel 5 enabled */ #define PDM_CTRL_1_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK) #define PDM_CTRL_1_CH6EN_MASK (0x40U) #define PDM_CTRL_1_CH6EN_SHIFT (6U) /*! CH6EN - Channel 6 Enable * 0b0..Channel 6 disabled * 0b1..Channel 6 enabled */ #define PDM_CTRL_1_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK) #define PDM_CTRL_1_CH7EN_MASK (0x80U) #define PDM_CTRL_1_CH7EN_SHIFT (7U) /*! CH7EN - Channel 7 Enable * 0b0..Channel 7 disabled * 0b1..Channel 7 enabled */ #define PDM_CTRL_1_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK) #define PDM_CTRL_1_ERREN_MASK (0x800000U) #define PDM_CTRL_1_ERREN_SHIFT (23U) /*! ERREN - Error Interruption Enable * 0b0..Error Interrupts disabled * 0b1..Error Interrupts enabled */ #define PDM_CTRL_1_ERREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK) #define PDM_CTRL_1_DISEL_MASK (0x3000000U) #define PDM_CTRL_1_DISEL_SHIFT (24U) /*! DISEL - DMA Interrupt Selection * 0b00..DMA and interrupt requests disabled * 0b01..DMA requests enabled * 0b10..Interrupt requests enabled * 0b11..Reserved */ #define PDM_CTRL_1_DISEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK) #define PDM_CTRL_1_DBGE_MASK (0x4000000U) #define PDM_CTRL_1_DBGE_SHIFT (26U) /*! DBGE - Module Enable in Debug * 0b0..PDM Interface is disabled in debug mode, after completing the current frame. * 0b1..PDM Interface is enabled in debug mode. */ #define PDM_CTRL_1_DBGE(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK) #define PDM_CTRL_1_SRES_MASK (0x8000000U) #define PDM_CTRL_1_SRES_SHIFT (27U) /*! SRES - Software-reset bit * 0b0..No action * 0b1..Software reset */ #define PDM_CTRL_1_SRES(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK) #define PDM_CTRL_1_DBG_MASK (0x10000000U) #define PDM_CTRL_1_DBG_SHIFT (28U) /*! DBG - Debug Mode * 0b0..PDM Interface is in Normal Mode. * 0b1..PDM Interface is in Debug Mode. */ #define PDM_CTRL_1_DBG(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK) #define PDM_CTRL_1_PDMIEN_MASK (0x20000000U) #define PDM_CTRL_1_PDMIEN_SHIFT (29U) /*! PDMIEN - PDM Inteface Enable * 0b0..PDM Interface disabled * 0b1..PDM Interface enabled. */ #define PDM_CTRL_1_PDMIEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK) #define PDM_CTRL_1_DOZEN_MASK (0x40000000U) #define PDM_CTRL_1_DOZEN_SHIFT (30U) /*! DOZEN - DOZE enable * 0b0..DOZE enable bit is not asserted * 0b1..DOZE enable bit is asserted */ #define PDM_CTRL_1_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK) #define PDM_CTRL_1_MDIS_MASK (0x80000000U) #define PDM_CTRL_1_MDIS_SHIFT (31U) /*! MDIS - Module Disable * 0b0..Normal Mode * 0b1..Disable/Low Leakage Mode */ #define PDM_CTRL_1_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK) /*! @} */ /*! @name CTRL_2 - MICFIL Control register 2 */ /*! @{ */ #define PDM_CTRL_2_CLKDIV_MASK (0xFFU) #define PDM_CTRL_2_CLKDIV_SHIFT (0U) #define PDM_CTRL_2_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK) #define PDM_CTRL_2_CICOSR_MASK (0xF0000U) #define PDM_CTRL_2_CICOSR_SHIFT (16U) #define PDM_CTRL_2_CICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK) #define PDM_CTRL_2_QSEL_MASK (0xE000000U) #define PDM_CTRL_2_QSEL_SHIFT (25U) /*! QSEL - Quality Select * 0b001..High quality mode. * 0b000..Medium quality mode. * 0b111..Low quality mode. * 0b110..Very low quality 0 mode. * 0b101..Very low quality 1 mode. * 0b100..Very low quality 2 mode. */ #define PDM_CTRL_2_QSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK) /*! @} */ /*! @name STAT - MICFIL Status register */ /*! @{ */ #define PDM_STAT_CH0F_MASK (0x1U) #define PDM_STAT_CH0F_SHIFT (0U) /*! CH0F - Channel 0 Output Data Flag * 0b0..Chanel's FIFO did not reach the number of elements configured in watermark bit-field. * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field. */ #define PDM_STAT_CH0F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK) #define PDM_STAT_CH1F_MASK (0x2U) #define PDM_STAT_CH1F_SHIFT (1U) /*! CH1F - Channel 1 Output Data Flag * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field. * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field. */ #define PDM_STAT_CH1F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK) #define PDM_STAT_CH2F_MASK (0x4U) #define PDM_STAT_CH2F_SHIFT (2U) /*! CH2F - Channel 2 Output Data Flag * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field. * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field. */ #define PDM_STAT_CH2F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK) #define PDM_STAT_CH3F_MASK (0x8U) #define PDM_STAT_CH3F_SHIFT (3U) /*! CH3F - Channel 3 Output Data Flag * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field. * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field. */ #define PDM_STAT_CH3F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK) #define PDM_STAT_CH4F_MASK (0x10U) #define PDM_STAT_CH4F_SHIFT (4U) /*! CH4F - Channel 4 Output Data Flag * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field. * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field. */ #define PDM_STAT_CH4F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK) #define PDM_STAT_CH5F_MASK (0x20U) #define PDM_STAT_CH5F_SHIFT (5U) /*! CH5F - Channel 5 Output Data Flag * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field. * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field. */ #define PDM_STAT_CH5F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK) #define PDM_STAT_CH6F_MASK (0x40U) #define PDM_STAT_CH6F_SHIFT (6U) /*! CH6F - Channel 6 Output Data Flag * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field. * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field. */ #define PDM_STAT_CH6F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK) #define PDM_STAT_CH7F_MASK (0x80U) #define PDM_STAT_CH7F_SHIFT (7U) /*! CH7F - Channel 7 Output Data Flag * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field. * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field. */ #define PDM_STAT_CH7F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK) #define PDM_STAT_LOWFREQF_MASK (0x20000000U) #define PDM_STAT_LOWFREQF_SHIFT (29U) /*! LOWFREQF - Low Frequency Flag * 0b0..CLKDIV value is OK. * 0b1..CLKDIV value is too low. */ #define PDM_STAT_LOWFREQF(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK) #define PDM_STAT_FIR_RDY_MASK (0x40000000U) #define PDM_STAT_FIR_RDY_SHIFT (30U) /*! FIR_RDY - FIR Filter Data Ready * 0b0..FIR Filter data not reliable. * 0b1..FIR Filter data reliable. */ #define PDM_STAT_FIR_RDY(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK) #define PDM_STAT_BSY_FIL_MASK (0x80000000U) #define PDM_STAT_BSY_FIL_SHIFT (31U) /*! BSY_FIL - Decimation Filter Busy Flag * 0b1..At least one Decimation Filter channel is running. * 0b0..All Decimation Filters are stopped. */ #define PDM_STAT_BSY_FIL(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK) /*! @} */ /*! @name FIFO_CTRL - MICFIL FIFO Control register */ /*! @{ */ #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) #define PDM_FIFO_CTRL_FIFOWMK_SHIFT (0U) #define PDM_FIFO_CTRL_FIFOWMK(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK) /*! @} */ /*! @name FIFO_STAT - MICFIL FIFO Status register */ /*! @{ */ #define PDM_FIFO_STAT_FIFOOVF0_MASK (0x1U) #define PDM_FIFO_STAT_FIFOOVF0_SHIFT (0U) /*! FIFOOVF0 - FIFO Overflow Exception flag for channel 0 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF0(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK) #define PDM_FIFO_STAT_FIFOOVF1_MASK (0x2U) #define PDM_FIFO_STAT_FIFOOVF1_SHIFT (1U) /*! FIFOOVF1 - FIFO Overflow Exception flag for channel 1 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF1(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK) #define PDM_FIFO_STAT_FIFOOVF2_MASK (0x4U) #define PDM_FIFO_STAT_FIFOOVF2_SHIFT (2U) /*! FIFOOVF2 - FIFO Overflow Exception flag for channel 2 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF2(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK) #define PDM_FIFO_STAT_FIFOOVF3_MASK (0x8U) #define PDM_FIFO_STAT_FIFOOVF3_SHIFT (3U) /*! FIFOOVF3 - FIFO Overflow Exception flag for channel 3 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF3(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK) #define PDM_FIFO_STAT_FIFOOVF4_MASK (0x10U) #define PDM_FIFO_STAT_FIFOOVF4_SHIFT (4U) /*! FIFOOVF4 - FIFO Overflow Exception flag for channel 4 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF4(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK) #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) #define PDM_FIFO_STAT_FIFOOVF5_SHIFT (5U) /*! FIFOOVF5 - FIFO Overflow Exception flag for channel 5 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF5(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK) #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) #define PDM_FIFO_STAT_FIFOOVF6_SHIFT (6U) /*! FIFOOVF6 - FIFO Overflow Exception flag for channel 6 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF6(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK) #define PDM_FIFO_STAT_FIFOOVF7_MASK (0x80U) #define PDM_FIFO_STAT_FIFOOVF7_SHIFT (7U) /*! FIFOOVF7 - FIFO Overflow Exception flag for channel 7 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF7(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK) #define PDM_FIFO_STAT_FIFOUND0_MASK (0x100U) #define PDM_FIFO_STAT_FIFOUND0_SHIFT (8U) /*! FIFOUND0 - FIFO Underflow Exception flag for channel 0 * 0b0..No exception by FIFO Underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND0(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK) #define PDM_FIFO_STAT_FIFOUND1_MASK (0x200U) #define PDM_FIFO_STAT_FIFOUND1_SHIFT (9U) /*! FIFOUND1 - FIFO Underflow Exception flag for channel 1 * 0b0..No exception by FIFO Underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND1(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK) #define PDM_FIFO_STAT_FIFOUND2_MASK (0x400U) #define PDM_FIFO_STAT_FIFOUND2_SHIFT (10U) /*! FIFOUND2 - FIFO Underflow Exception flag for channel 2 * 0b0..No exception by FIFO Underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND2(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK) #define PDM_FIFO_STAT_FIFOUND3_MASK (0x800U) #define PDM_FIFO_STAT_FIFOUND3_SHIFT (11U) /*! FIFOUND3 - FIFO Underflow Exception flag for channel 3 * 0b0..No exception by FIFO Underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND3(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK) #define PDM_FIFO_STAT_FIFOUND4_MASK (0x1000U) #define PDM_FIFO_STAT_FIFOUND4_SHIFT (12U) /*! FIFOUND4 - FIFO Underflow Exception flag for channel 4 * 0b0..No exception by FIFO Underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND4(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK) #define PDM_FIFO_STAT_FIFOUND5_MASK (0x2000U) #define PDM_FIFO_STAT_FIFOUND5_SHIFT (13U) /*! FIFOUND5 - FIFO Underflow Exception flag for channel 5 * 0b0..No exception by FIFO Underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND5(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK) #define PDM_FIFO_STAT_FIFOUND6_MASK (0x4000U) #define PDM_FIFO_STAT_FIFOUND6_SHIFT (14U) /*! FIFOUND6 - FIFO Underflow Exception flag for channel 6 * 0b0..No exception by FIFO Underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND6(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK) #define PDM_FIFO_STAT_FIFOUND7_MASK (0x8000U) #define PDM_FIFO_STAT_FIFOUND7_SHIFT (15U) /*! FIFOUND7 - FIFO Underflow Exception flag for channel 7 * 0b0..No exception by FIFO Underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND7(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK) /*! @} */ /*! @name DATACH - MICFIL Output Result Register */ /*! @{ */ #define PDM_DATACH_DATA_MASK (0xFFFFU) #define PDM_DATACH_DATA_SHIFT (0U) #define PDM_DATACH_DATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK) /*! @} */ /* The count of PDM_DATACH */ #define PDM_DATACH_COUNT (8U) /*! @name DC_CTRL - MICFIL DC Remover Control register */ /*! @{ */ #define PDM_DC_CTRL_DCCONFIG0_MASK (0x3U) #define PDM_DC_CTRL_DCCONFIG0_SHIFT (0U) /*! DCCONFIG0 - Channel 0 DC Remover Configuration * 0b11..DC Remover is bypassed. * 0b00..DC Remover cut-off at 21Hz. * 0b01..DC Remover cut-off at 83Hz. * 0b10..DC Remover cut-off at 152Hz. */ #define PDM_DC_CTRL_DCCONFIG0(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK) #define PDM_DC_CTRL_DCCONFIG1_MASK (0xCU) #define PDM_DC_CTRL_DCCONFIG1_SHIFT (2U) /*! DCCONFIG1 - Channel 1 DC Remover Configuration * 0b11..DC Remover is bypassed. * 0b00..DC Remover cut-off at 21Hz. * 0b01..DC Remover cut-off at 83Hz. * 0b10..DC Remover cut-off at 152Hz. */ #define PDM_DC_CTRL_DCCONFIG1(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK) #define PDM_DC_CTRL_DCCONFIG2_MASK (0x30U) #define PDM_DC_CTRL_DCCONFIG2_SHIFT (4U) /*! DCCONFIG2 - Channel 2 DC Remover Configuration * 0b11..DC Remover is bypassed. * 0b00..DC Remover cut-off at 21Hz. * 0b01..DC Remover cut-off at 83Hz. * 0b10..DC Remover cut-off at 152Hz. */ #define PDM_DC_CTRL_DCCONFIG2(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK) #define PDM_DC_CTRL_DCCONFIG3_MASK (0xC0U) #define PDM_DC_CTRL_DCCONFIG3_SHIFT (6U) /*! DCCONFIG3 - Channel 3 DC Remover Configuration * 0b11..DC Remover is bypassed. * 0b00..DC Remover cut-off at 21Hz. * 0b01..DC Remover cut-off at 83Hz. * 0b10..DC Remover cut-off at 152Hz. */ #define PDM_DC_CTRL_DCCONFIG3(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK) #define PDM_DC_CTRL_DCCONFIG4_MASK (0x300U) #define PDM_DC_CTRL_DCCONFIG4_SHIFT (8U) /*! DCCONFIG4 - Channel 4 DC Remover Configuration * 0b11..DC Remover is bypassed. * 0b00..DC Remover cut-off at 21Hz. * 0b01..DC Remover cut-off at 83Hz. * 0b10..DC Remover cut-off at 152Hz. */ #define PDM_DC_CTRL_DCCONFIG4(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK) #define PDM_DC_CTRL_DCCONFIG5_MASK (0xC00U) #define PDM_DC_CTRL_DCCONFIG5_SHIFT (10U) /*! DCCONFIG5 - Channel 5 DC Remover Configuration * 0b11..DC Remover is bypassed. * 0b00..DC Remover cut-off at 21Hz. * 0b01..DC Remover cut-off at 83Hz. * 0b10..DC Remover cut-off at 152Hz. */ #define PDM_DC_CTRL_DCCONFIG5(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK) #define PDM_DC_CTRL_DCCONFIG6_MASK (0x3000U) #define PDM_DC_CTRL_DCCONFIG6_SHIFT (12U) /*! DCCONFIG6 - Channel 6 DC Remover Configuration * 0b11..DC Remover is bypassed. * 0b00..DC Remover cut-off at 21Hz. * 0b01..DC Remover cut-off at 83Hz. * 0b10..DC Remover cut-off at 152Hz. */ #define PDM_DC_CTRL_DCCONFIG6(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK) #define PDM_DC_CTRL_DCCONFIG7_MASK (0xC000U) #define PDM_DC_CTRL_DCCONFIG7_SHIFT (14U) /*! DCCONFIG7 - Channel 7 DC Remover Configuration * 0b11..DC Remover is bypassed. * 0b00..DC Remover cut-off at 21Hz. * 0b01..DC Remover cut-off at 83Hz. * 0b10..DC Remover cut-off at 152Hz. */ #define PDM_DC_CTRL_DCCONFIG7(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK) /*! @} */ /*! @name OUT_CTRL - MICFIL Output Control register */ /*! @{ */ #define PDM_OUT_CTRL_OUTGAIN0_MASK (0xFU) #define PDM_OUT_CTRL_OUTGAIN0_SHIFT (0U) #define PDM_OUT_CTRL_OUTGAIN0(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_CTRL_OUTGAIN0_SHIFT)) & PDM_OUT_CTRL_OUTGAIN0_MASK) #define PDM_OUT_CTRL_OUTGAIN1_MASK (0xF0U) #define PDM_OUT_CTRL_OUTGAIN1_SHIFT (4U) #define PDM_OUT_CTRL_OUTGAIN1(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_CTRL_OUTGAIN1_SHIFT)) & PDM_OUT_CTRL_OUTGAIN1_MASK) #define PDM_OUT_CTRL_OUTGAIN2_MASK (0xF00U) #define PDM_OUT_CTRL_OUTGAIN2_SHIFT (8U) #define PDM_OUT_CTRL_OUTGAIN2(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_CTRL_OUTGAIN2_SHIFT)) & PDM_OUT_CTRL_OUTGAIN2_MASK) #define PDM_OUT_CTRL_OUTGAIN3_MASK (0xF000U) #define PDM_OUT_CTRL_OUTGAIN3_SHIFT (12U) #define PDM_OUT_CTRL_OUTGAIN3(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_CTRL_OUTGAIN3_SHIFT)) & PDM_OUT_CTRL_OUTGAIN3_MASK) #define PDM_OUT_CTRL_OUTGAIN4_MASK (0xF0000U) #define PDM_OUT_CTRL_OUTGAIN4_SHIFT (16U) #define PDM_OUT_CTRL_OUTGAIN4(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_CTRL_OUTGAIN4_SHIFT)) & PDM_OUT_CTRL_OUTGAIN4_MASK) #define PDM_OUT_CTRL_OUTGAIN5_MASK (0xF00000U) #define PDM_OUT_CTRL_OUTGAIN5_SHIFT (20U) #define PDM_OUT_CTRL_OUTGAIN5(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_CTRL_OUTGAIN5_SHIFT)) & PDM_OUT_CTRL_OUTGAIN5_MASK) #define PDM_OUT_CTRL_OUTGAIN6_MASK (0xF000000U) #define PDM_OUT_CTRL_OUTGAIN6_SHIFT (24U) #define PDM_OUT_CTRL_OUTGAIN6(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_CTRL_OUTGAIN6_SHIFT)) & PDM_OUT_CTRL_OUTGAIN6_MASK) #define PDM_OUT_CTRL_OUTGAIN7_MASK (0xF0000000U) #define PDM_OUT_CTRL_OUTGAIN7_SHIFT (28U) #define PDM_OUT_CTRL_OUTGAIN7(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_CTRL_OUTGAIN7_SHIFT)) & PDM_OUT_CTRL_OUTGAIN7_MASK) /*! @} */ /*! @name OUT_STAT - MICFIL Output Status register */ /*! @{ */ #define PDM_OUT_STAT_OUTOVF0_MASK (0x1U) #define PDM_OUT_STAT_OUTOVF0_SHIFT (0U) /*! OUTOVF0 - Channel 0 Output Overflow Flag * 0b0..No exception by output overflow. * 0b1..Exception by output overflow. */ #define PDM_OUT_STAT_OUTOVF0(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTOVF0_SHIFT)) & PDM_OUT_STAT_OUTOVF0_MASK) #define PDM_OUT_STAT_OUTOVF1_MASK (0x2U) #define PDM_OUT_STAT_OUTOVF1_SHIFT (1U) /*! OUTOVF1 - Channel 1 Output Overflow Flag * 0b0..No exception by output overflow. * 0b1..Exception by output overflow. */ #define PDM_OUT_STAT_OUTOVF1(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTOVF1_SHIFT)) & PDM_OUT_STAT_OUTOVF1_MASK) #define PDM_OUT_STAT_OUTOVF2_MASK (0x4U) #define PDM_OUT_STAT_OUTOVF2_SHIFT (2U) /*! OUTOVF2 - Channel 2 Output Overflow Flag * 0b0..No exception by output overflow. * 0b1..Exception by output overflow. */ #define PDM_OUT_STAT_OUTOVF2(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTOVF2_SHIFT)) & PDM_OUT_STAT_OUTOVF2_MASK) #define PDM_OUT_STAT_OUTOVF3_MASK (0x8U) #define PDM_OUT_STAT_OUTOVF3_SHIFT (3U) /*! OUTOVF3 - Channel 3 Output Overflow Flag * 0b0..No exception by output overflow. * 0b1..Exception by output overflow. */ #define PDM_OUT_STAT_OUTOVF3(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTOVF3_SHIFT)) & PDM_OUT_STAT_OUTOVF3_MASK) #define PDM_OUT_STAT_OUTOVF4_MASK (0x10U) #define PDM_OUT_STAT_OUTOVF4_SHIFT (4U) /*! OUTOVF4 - Channel 4 Output Overflow Flag * 0b0..No exception by output overflow. * 0b1..Exception by output overflow. */ #define PDM_OUT_STAT_OUTOVF4(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTOVF4_SHIFT)) & PDM_OUT_STAT_OUTOVF4_MASK) #define PDM_OUT_STAT_OUTOVF5_MASK (0x20U) #define PDM_OUT_STAT_OUTOVF5_SHIFT (5U) /*! OUTOVF5 - Channel 5 Output Overflow Flag * 0b0..No exception by output overflow. * 0b1..Exception by output overflow. */ #define PDM_OUT_STAT_OUTOVF5(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTOVF5_SHIFT)) & PDM_OUT_STAT_OUTOVF5_MASK) #define PDM_OUT_STAT_OUTOVF6_MASK (0x40U) #define PDM_OUT_STAT_OUTOVF6_SHIFT (6U) /*! OUTOVF6 - Channel 6 Output Overflow Flag * 0b0..No exception by output overflow. * 0b1..Exception by output overflow. */ #define PDM_OUT_STAT_OUTOVF6(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTOVF6_SHIFT)) & PDM_OUT_STAT_OUTOVF6_MASK) #define PDM_OUT_STAT_OUTOVF7_MASK (0x80U) #define PDM_OUT_STAT_OUTOVF7_SHIFT (7U) /*! OUTOVF7 - Channel 7 Output Overflow Flag * 0b0..No exception by output overflow. * 0b1..Exception by output overflow. */ #define PDM_OUT_STAT_OUTOVF7(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTOVF7_SHIFT)) & PDM_OUT_STAT_OUTOVF7_MASK) #define PDM_OUT_STAT_OUTUNF0_MASK (0x10000U) #define PDM_OUT_STAT_OUTUNF0_SHIFT (16U) /*! OUTUNF0 - Channel 0 Output Underflow Flag * 0b0..No exception by output underflow. * 0b1..Exception by output underflow. */ #define PDM_OUT_STAT_OUTUNF0(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTUNF0_SHIFT)) & PDM_OUT_STAT_OUTUNF0_MASK) #define PDM_OUT_STAT_OUTUNF1_MASK (0x20000U) #define PDM_OUT_STAT_OUTUNF1_SHIFT (17U) /*! OUTUNF1 - Channel 1 Output Underflow Flag * 0b0..No exception by output underflow. * 0b1..Exception by output underflow. */ #define PDM_OUT_STAT_OUTUNF1(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTUNF1_SHIFT)) & PDM_OUT_STAT_OUTUNF1_MASK) #define PDM_OUT_STAT_OUTUNF2_MASK (0x40000U) #define PDM_OUT_STAT_OUTUNF2_SHIFT (18U) /*! OUTUNF2 - Channel 2 Output Underflow Flag * 0b0..No exception by output underflow. * 0b1..Exception by output underflow. */ #define PDM_OUT_STAT_OUTUNF2(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTUNF2_SHIFT)) & PDM_OUT_STAT_OUTUNF2_MASK) #define PDM_OUT_STAT_OUTUNF3_MASK (0x80000U) #define PDM_OUT_STAT_OUTUNF3_SHIFT (19U) /*! OUTUNF3 - Channel 3 Output Underflow Flag * 0b0..No exception by output underflow. * 0b1..Exception by output underflow. */ #define PDM_OUT_STAT_OUTUNF3(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTUNF3_SHIFT)) & PDM_OUT_STAT_OUTUNF3_MASK) #define PDM_OUT_STAT_OUTUNF4_MASK (0x100000U) #define PDM_OUT_STAT_OUTUNF4_SHIFT (20U) /*! OUTUNF4 - Channel 4 Output Underflow Flag * 0b0..No exception by output underflow. * 0b1..Exception by output underflow. */ #define PDM_OUT_STAT_OUTUNF4(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTUNF4_SHIFT)) & PDM_OUT_STAT_OUTUNF4_MASK) #define PDM_OUT_STAT_OUTUNF5_MASK (0x200000U) #define PDM_OUT_STAT_OUTUNF5_SHIFT (21U) /*! OUTUNF5 - Channel 5 Output Underflow Flag * 0b0..No exception by output underflow. * 0b1..Exception by output underflow. */ #define PDM_OUT_STAT_OUTUNF5(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTUNF5_SHIFT)) & PDM_OUT_STAT_OUTUNF5_MASK) #define PDM_OUT_STAT_OUTUNF6_MASK (0x400000U) #define PDM_OUT_STAT_OUTUNF6_SHIFT (22U) /*! OUTUNF6 - Channel 6 Output Underflow Flag * 0b0..No exception by output underflow. * 0b1..Exception by output underflow. */ #define PDM_OUT_STAT_OUTUNF6(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTUNF6_SHIFT)) & PDM_OUT_STAT_OUTUNF6_MASK) #define PDM_OUT_STAT_OUTUNF7_MASK (0x800000U) #define PDM_OUT_STAT_OUTUNF7_SHIFT (23U) /*! OUTUNF7 - Channel 7 Output Underflow Flag * 0b0..No exception by output underflow. * 0b1..Exception by output underflow. */ #define PDM_OUT_STAT_OUTUNF7(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTUNF7_SHIFT)) & PDM_OUT_STAT_OUTUNF7_MASK) /*! @} */ /*! @name VAD0_CTRL_1 - Voice Activity Detector 0 Control register */ /*! @{ */ #define PDM_VAD0_CTRL_1_VADEN_MASK (0x1U) #define PDM_VAD0_CTRL_1_VADEN_SHIFT (0U) /*! VADEN - Voice Activity Detector Enable * 0b0..The HWVAD is disabled. * 0b1..The HWVAD is enabled. */ #define PDM_VAD0_CTRL_1_VADEN(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK) #define PDM_VAD0_CTRL_1_VADRST_MASK (0x2U) #define PDM_VAD0_CTRL_1_VADRST_SHIFT (1U) #define PDM_VAD0_CTRL_1_VADRST(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK) #define PDM_VAD0_CTRL_1_VADIE_MASK (0x4U) #define PDM_VAD0_CTRL_1_VADIE_SHIFT (2U) /*! VADIE - Voice Activity Detector Interruption Enable * 0b0..HWVAD Interrupts disabled * 0b1..HWVAD Interrupts enabled */ #define PDM_VAD0_CTRL_1_VADIE(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK) #define PDM_VAD0_CTRL_1_VADERIE_MASK (0x8U) #define PDM_VAD0_CTRL_1_VADERIE_SHIFT (3U) /*! VADERIE - Voice Activity Detector Error Interruption Enable * 0b0..HWVAD Error Interrupts disabled * 0b1..HWVAD Error Interrupts enabled */ #define PDM_VAD0_CTRL_1_VADERIE(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK) #define PDM_VAD0_CTRL_1_VADST10_MASK (0x10U) #define PDM_VAD0_CTRL_1_VADST10_SHIFT (4U) /*! VADST10 - Voice Activity Detector Internal Filters Initialization * 0b0..Normal operation. * 0b1..Filters are initialized. */ #define PDM_VAD0_CTRL_1_VADST10(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK) #define PDM_VAD0_CTRL_1_VADINITT_MASK (0x1F00U) #define PDM_VAD0_CTRL_1_VADINITT_SHIFT (8U) #define PDM_VAD0_CTRL_1_VADINITT(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK) #define PDM_VAD0_CTRL_1_VADCICOSR_MASK (0xF0000U) #define PDM_VAD0_CTRL_1_VADCICOSR_SHIFT (16U) #define PDM_VAD0_CTRL_1_VADCICOSR(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK) #define PDM_VAD0_CTRL_1_VADCHSEL_MASK (0x7000000U) #define PDM_VAD0_CTRL_1_VADCHSEL_SHIFT (24U) #define PDM_VAD0_CTRL_1_VADCHSEL(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK) /*! @} */ /*! @name VAD0_CTRL_2 - Voice Activity Detector 0 Control register */ /*! @{ */ #define PDM_VAD0_CTRL_2_VADHPF_MASK (0x3U) #define PDM_VAD0_CTRL_2_VADHPF_SHIFT (0U) /*! VADHPF - Voice Activity Detector High-Pass Filter * 0b00..Filter bypassed. * 0b01..Cut-off frequency at 1750Hz. * 0b10..Cut-off frequency at 215Hz. * 0b11..Cut-off frequency at 102Hz. */ #define PDM_VAD0_CTRL_2_VADHPF(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK) #define PDM_VAD0_CTRL_2_VADINPGAIN_MASK (0xF00U) #define PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT (8U) #define PDM_VAD0_CTRL_2_VADINPGAIN(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK) #define PDM_VAD0_CTRL_2_VADFRAMET_MASK (0x3F0000U) #define PDM_VAD0_CTRL_2_VADFRAMET_SHIFT (16U) #define PDM_VAD0_CTRL_2_VADFRAMET(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK) #define PDM_VAD0_CTRL_2_VADFOUTDIS_MASK (0x10000000U) #define PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT (28U) /*! VADFOUTDIS - Voice Activity Detector Force Output Disable * 0b0..Output is enabled. * 0b1..Output is disabled. */ #define PDM_VAD0_CTRL_2_VADFOUTDIS(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK) #define PDM_VAD0_CTRL_2_VADPREFEN_MASK (0x40000000U) #define PDM_VAD0_CTRL_2_VADPREFEN_SHIFT (30U) /*! VADPREFEN - Voice Activity Detector Pre Filter Enable * 0b0..Pre-filter is bypassed. * 0b1..Pre-filter is enabled. */ #define PDM_VAD0_CTRL_2_VADPREFEN(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK) #define PDM_VAD0_CTRL_2_VADFRENDIS_MASK (0x80000000U) #define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT (31U) /*! VADFRENDIS - Voice Activity Detector Frame Energy Disable * 0b1..Frame energy calculus disabled. * 0b0..Frame energy calculus enabled. */ #define PDM_VAD0_CTRL_2_VADFRENDIS(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK) /*! @} */ /*! @name VAD0_STAT - Voice Activity Detector 0 Status register */ /*! @{ */ #define PDM_VAD0_STAT_VADIF_MASK (0x1U) #define PDM_VAD0_STAT_VADIF_SHIFT (0U) /*! VADIF - Voice Activity Detector Interrupt Flag * 0b0..Voice activity has not been detected by the HWVAD. * 0b1..Voice activity has been detected by the HWVAD. */ #define PDM_VAD0_STAT_VADIF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK) #define PDM_VAD0_STAT_VADEF_MASK (0x8000U) #define PDM_VAD0_STAT_VADEF_SHIFT (15U) /*! VADEF - Voice Activity Detector Event Flag * 0b0..Voice activity has not been detected by the HWVAD. * 0b1..Voice activity has been detected by the HWVAD. */ #define PDM_VAD0_STAT_VADEF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADEF_SHIFT)) & PDM_VAD0_STAT_VADEF_MASK) #define PDM_VAD0_STAT_VADINSATF_MASK (0x10000U) #define PDM_VAD0_STAT_VADINSATF_SHIFT (16U) /*! VADINSATF - Voice Activity Detector Input Saturation Flag * 0b0..No exception by HWVAD input saturation. * 0b1..Exception by HWVAD input saturation. */ #define PDM_VAD0_STAT_VADINSATF(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK) #define PDM_VAD0_STAT_VADINITF_MASK (0x80000000U) #define PDM_VAD0_STAT_VADINITF_SHIFT (31U) /*! VADINITF - Voice Activity Detector Initialization Flag * 0b0..HWVAD is not being initialized. * 0b1..HWVAD is being initialized. */ #define PDM_VAD0_STAT_VADINITF(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK) /*! @} */ /*! @name VAD0_SCONFIG - Voice Activity Detector 0 Signal Configuration */ /*! @{ */ #define PDM_VAD0_SCONFIG_VADSGAIN_MASK (0xFU) #define PDM_VAD0_SCONFIG_VADSGAIN_SHIFT (0U) #define PDM_VAD0_SCONFIG_VADSGAIN(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK) #define PDM_VAD0_SCONFIG_VADSMAXEN_MASK (0x40000000U) #define PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT (30U) /*! VADSMAXEN - Voice Activity Detector Signal Maximum Enable * 0b0..Maximum block is bypassed. * 0b1..Maximum block is enabled. */ #define PDM_VAD0_SCONFIG_VADSMAXEN(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK) #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) #define PDM_VAD0_SCONFIG_VADSFILEN_SHIFT (31U) /*! VADSFILEN - Voice Activity Detector Signal Filter Enable * 0b0..Signal filter is disabled. * 0b1..Signal filter is enabled. */ #define PDM_VAD0_SCONFIG_VADSFILEN(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK) /*! @} */ /*! @name VAD0_NCONFIG - Voice Activity Detector 0 Noise Configuration */ /*! @{ */ #define PDM_VAD0_NCONFIG_VADNGAIN_MASK (0xFU) #define PDM_VAD0_NCONFIG_VADNGAIN_SHIFT (0U) #define PDM_VAD0_NCONFIG_VADNGAIN(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK) #define PDM_VAD0_NCONFIG_VADNFILADJ_MASK (0x1F00U) #define PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT (8U) #define PDM_VAD0_NCONFIG_VADNFILADJ(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK) #define PDM_VAD0_NCONFIG_VADNOREN_MASK (0x10000000U) #define PDM_VAD0_NCONFIG_VADNOREN_SHIFT (28U) /*! VADNOREN - Voice Activity Detector Noise OR Enable * 0b0..Noise input is not decimated. * 0b1..Noise input is decimated. */ #define PDM_VAD0_NCONFIG_VADNOREN(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK) #define PDM_VAD0_NCONFIG_VADNDECEN_MASK (0x20000000U) #define PDM_VAD0_NCONFIG_VADNDECEN_SHIFT (29U) /*! VADNDECEN - Voice Activity Detector Noise Decimation Enable * 0b0..Noise input is not decimated. * 0b1..Noise input is decimated. */ #define PDM_VAD0_NCONFIG_VADNDECEN(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK) #define PDM_VAD0_NCONFIG_VADNMINEN_MASK (0x40000000U) #define PDM_VAD0_NCONFIG_VADNMINEN_SHIFT (30U) /*! VADNMINEN - Voice Activity Detector Noise Minimum Enable * 0b0..Minimum block is bypassed. * 0b1..Minimum block is enabled. */ #define PDM_VAD0_NCONFIG_VADNMINEN(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK) #define PDM_VAD0_NCONFIG_VADNFILAUTO_MASK (0x80000000U) #define PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT (31U) /*! VADNFILAUTO - Voice Activity Detector Noise Filter Auto * 0b0..Noise filter is always enabled. * 0b1..Noise filter is enabled/disabled based on voice activity information. */ #define PDM_VAD0_NCONFIG_VADNFILAUTO(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK) /*! @} */ /*! @name VAD0_NDATA - Voice Activity Detector 0 Noise Data */ /*! @{ */ #define PDM_VAD0_NDATA_VADNDATA_MASK (0xFFFFU) #define PDM_VAD0_NDATA_VADNDATA_SHIFT (0U) #define PDM_VAD0_NDATA_VADNDATA(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK) /*! @} */ /*! @name VAD0_ZCD - Voice Activity Detector 0 Zero-Crossing Detector */ /*! @{ */ #define PDM_VAD0_ZCD_VADZCDEN_MASK (0x1U) #define PDM_VAD0_ZCD_VADZCDEN_SHIFT (0U) /*! VADZCDEN - Zero-Crossing Detector Enable * 0b0..The ZCD is disabled. * 0b1..The ZCD is enabled. */ #define PDM_VAD0_ZCD_VADZCDEN(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK) #define PDM_VAD0_ZCD_VADZCDAUTO_MASK (0x4U) #define PDM_VAD0_ZCD_VADZCDAUTO_SHIFT (2U) /*! VADZCDAUTO - Zero-Crossing Detector Automatic Threshold * 0b0..The ZCD threshold is not estimated automatically, * 0b1..The ZCD threshold is estimated automatically. */ #define PDM_VAD0_ZCD_VADZCDAUTO(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK) #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) #define PDM_VAD0_ZCD_VADZCDAND_SHIFT (4U) /*! VADZCDAND - Zero-Crossing Detector AND Behavior * 0b0..The ZCD result is OR'ed with the energy-based detection. * 0b1..The ZCD result is AND'ed with the energy-based detection. */ #define PDM_VAD0_ZCD_VADZCDAND(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK) #define PDM_VAD0_ZCD_VADZCDADJ_MASK (0xF00U) #define PDM_VAD0_ZCD_VADZCDADJ_SHIFT (8U) #define PDM_VAD0_ZCD_VADZCDADJ(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK) #define PDM_VAD0_ZCD_VADZCDTH_MASK (0x3FF0000U) #define PDM_VAD0_ZCD_VADZCDTH_SHIFT (16U) #define PDM_VAD0_ZCD_VADZCDTH(x) \ (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK) /*! @} */ /*! * @} */ /* end of group PDM_Register_Masks */ /* PDM - Peripheral instance base addresses */ /** Peripheral PDM base address */ #define PDM_BASE (0x30080000u) /** Peripheral PDM base pointer */ #define PDM ((PDM_Type *)PDM_BASE) /** Array initializer of PDM peripheral base addresses */ #define PDM_BASE_ADDRS \ { \ PDM_BASE \ } /** Array initializer of PDM peripheral base pointers */ #define PDM_BASE_PTRS \ { \ PDM \ } /*! * @} */ /* end of group PDM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PWM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer * @{ */ /** PWM - Register Layout Typedef */ typedef struct { __IO uint32_t PWMCR; /**< PWM Control Register, offset: 0x0 */ __IO uint32_t PWMSR; /**< PWM Status Register, offset: 0x4 */ __IO uint32_t PWMIR; /**< PWM Interrupt Register, offset: 0x8 */ __IO uint32_t PWMSAR; /**< PWM Sample Register, offset: 0xC */ __IO uint32_t PWMPR; /**< PWM Period Register, offset: 0x10 */ __I uint32_t PWMCNR; /**< PWM Counter Register, offset: 0x14 */ } PWM_Type; /* ---------------------------------------------------------------------------- -- PWM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PWM_Register_Masks PWM Register Masks * @{ */ /*! @name PWMCR - PWM Control Register */ /*! @{ */ #define PWM_PWMCR_EN_MASK (0x1U) #define PWM_PWMCR_EN_SHIFT (0U) /*! EN * 0b0..PWM disabled * 0b1..PWM enabled */ #define PWM_PWMCR_EN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_EN_SHIFT)) & PWM_PWMCR_EN_MASK) #define PWM_PWMCR_REPEAT_MASK (0x6U) #define PWM_PWMCR_REPEAT_SHIFT (1U) /*! REPEAT * 0b00..Use each sample once * 0b01..Use each sample twice * 0b10..Use each sample four times * 0b11..Use each sample eight times */ #define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_REPEAT_SHIFT)) & PWM_PWMCR_REPEAT_MASK) #define PWM_PWMCR_SWR_MASK (0x8U) #define PWM_PWMCR_SWR_SHIFT (3U) /*! SWR * 0b0..PWM is out of reset * 0b1..PWM is undergoing reset */ #define PWM_PWMCR_SWR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_SWR_SHIFT)) & PWM_PWMCR_SWR_MASK) #define PWM_PWMCR_PRESCALER_MASK (0xFFF0U) #define PWM_PWMCR_PRESCALER_SHIFT (4U) /*! PRESCALER * 0b000000000000..Divide by 1 * 0b000000000001..Divide by 2 * 0b111111111111..Divide by 4096 */ #define PWM_PWMCR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_PRESCALER_SHIFT)) & PWM_PWMCR_PRESCALER_MASK) #define PWM_PWMCR_CLKSRC_MASK (0x30000U) #define PWM_PWMCR_CLKSRC_SHIFT (16U) /*! CLKSRC * 0b00..Clock is off * 0b01..ipg_clk * 0b10..ipg_clk_highfreq * 0b11..ipg_clk_32k */ #define PWM_PWMCR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_CLKSRC_SHIFT)) & PWM_PWMCR_CLKSRC_MASK) #define PWM_PWMCR_POUTC_MASK (0xC0000U) #define PWM_PWMCR_POUTC_SHIFT (18U) /*! POUTC * 0b00..Output pin is set at rollover and cleared at comparison * 0b01..Output pin is cleared at rollover and set at comparison * 0b10..PWM output is disconnected * 0b11..PWM output is disconnected */ #define PWM_PWMCR_POUTC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_POUTC_SHIFT)) & PWM_PWMCR_POUTC_MASK) #define PWM_PWMCR_HCTR_MASK (0x100000U) #define PWM_PWMCR_HCTR_SHIFT (20U) /*! HCTR * 0b0..Half word swapping does not take place * 0b1..Half words from write data bus are swapped */ #define PWM_PWMCR_HCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_HCTR_SHIFT)) & PWM_PWMCR_HCTR_MASK) #define PWM_PWMCR_BCTR_MASK (0x200000U) #define PWM_PWMCR_BCTR_SHIFT (21U) /*! BCTR * 0b0..byte ordering remains the same * 0b1..byte ordering is reversed */ #define PWM_PWMCR_BCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_BCTR_SHIFT)) & PWM_PWMCR_BCTR_MASK) #define PWM_PWMCR_DBGEN_MASK (0x400000U) #define PWM_PWMCR_DBGEN_SHIFT (22U) /*! DBGEN * 0b0..Inactive in debug mode * 0b1..Active in debug mode */ #define PWM_PWMCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DBGEN_SHIFT)) & PWM_PWMCR_DBGEN_MASK) #define PWM_PWMCR_WAITEN_MASK (0x800000U) #define PWM_PWMCR_WAITEN_SHIFT (23U) /*! WAITEN * 0b0..Inactive in wait mode * 0b1..Active in wait mode */ #define PWM_PWMCR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_WAITEN_SHIFT)) & PWM_PWMCR_WAITEN_MASK) #define PWM_PWMCR_DOZEN_MASK (0x1000000U) #define PWM_PWMCR_DOZEN_SHIFT (24U) /*! DOZEN * 0b0..Inactive in doze mode * 0b1..Active in doze mode */ #define PWM_PWMCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DOZEN_SHIFT)) & PWM_PWMCR_DOZEN_MASK) #define PWM_PWMCR_STOPEN_MASK (0x2000000U) #define PWM_PWMCR_STOPEN_SHIFT (25U) /*! STOPEN * 0b0..Inactive in stop mode * 0b1..Active in stop mode */ #define PWM_PWMCR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_STOPEN_SHIFT)) & PWM_PWMCR_STOPEN_MASK) #define PWM_PWMCR_FWM_MASK (0xC000000U) #define PWM_PWMCR_FWM_SHIFT (26U) /*! FWM * 0b00..FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO * 0b01..FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO * 0b10..FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO * 0b11..FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO */ #define PWM_PWMCR_FWM(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_FWM_SHIFT)) & PWM_PWMCR_FWM_MASK) /*! @} */ /*! @name PWMSR - PWM Status Register */ /*! @{ */ #define PWM_PWMSR_FIFOAV_MASK (0x7U) #define PWM_PWMSR_FIFOAV_SHIFT (0U) /*! FIFOAV * 0b000..No data available * 0b001..1 word of data in FIFO * 0b010..2 words of data in FIFO * 0b011..3 words of data in FIFO * 0b100..4 words of data in FIFO * 0b101..unused * 0b110..unused * 0b111..unused */ #define PWM_PWMSR_FIFOAV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FIFOAV_SHIFT)) & PWM_PWMSR_FIFOAV_MASK) #define PWM_PWMSR_FE_MASK (0x8U) #define PWM_PWMSR_FE_SHIFT (3U) /*! FE * 0b0..Data level is above water mark * 0b1..When the data level falls below the mark set by FWM field */ #define PWM_PWMSR_FE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FE_SHIFT)) & PWM_PWMSR_FE_MASK) #define PWM_PWMSR_ROV_MASK (0x10U) #define PWM_PWMSR_ROV_SHIFT (4U) /*! ROV * 0b0..Roll-over event not occurred * 0b1..Roll-over event occurred */ #define PWM_PWMSR_ROV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_ROV_SHIFT)) & PWM_PWMSR_ROV_MASK) #define PWM_PWMSR_CMP_MASK (0x20U) #define PWM_PWMSR_CMP_SHIFT (5U) /*! CMP * 0b0..Compare event not occurred * 0b1..Compare event occurred */ #define PWM_PWMSR_CMP(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_CMP_SHIFT)) & PWM_PWMSR_CMP_MASK) #define PWM_PWMSR_FWE_MASK (0x40U) #define PWM_PWMSR_FWE_SHIFT (6U) /*! FWE * 0b0..FIFO write error not occurred * 0b1..FIFO write error occurred */ #define PWM_PWMSR_FWE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FWE_SHIFT)) & PWM_PWMSR_FWE_MASK) /*! @} */ /*! @name PWMIR - PWM Interrupt Register */ /*! @{ */ #define PWM_PWMIR_FIE_MASK (0x1U) #define PWM_PWMIR_FIE_SHIFT (0U) /*! FIE * 0b0..FIFO Empty interrupt disabled * 0b1..FIFO Empty interrupt enabled */ #define PWM_PWMIR_FIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_FIE_SHIFT)) & PWM_PWMIR_FIE_MASK) #define PWM_PWMIR_RIE_MASK (0x2U) #define PWM_PWMIR_RIE_SHIFT (1U) /*! RIE * 0b0..Roll-over interrupt not enabled * 0b1..Roll-over Interrupt enabled */ #define PWM_PWMIR_RIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_RIE_SHIFT)) & PWM_PWMIR_RIE_MASK) #define PWM_PWMIR_CIE_MASK (0x4U) #define PWM_PWMIR_CIE_SHIFT (2U) /*! CIE * 0b0..Compare Interrupt not enabled * 0b1..Compare Interrupt enabled */ #define PWM_PWMIR_CIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_CIE_SHIFT)) & PWM_PWMIR_CIE_MASK) /*! @} */ /*! @name PWMSAR - PWM Sample Register */ /*! @{ */ #define PWM_PWMSAR_SAMPLE_MASK (0xFFFFU) #define PWM_PWMSAR_SAMPLE_SHIFT (0U) #define PWM_PWMSAR_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSAR_SAMPLE_SHIFT)) & PWM_PWMSAR_SAMPLE_MASK) /*! @} */ /*! @name PWMPR - PWM Period Register */ /*! @{ */ #define PWM_PWMPR_PERIOD_MASK (0xFFFFU) #define PWM_PWMPR_PERIOD_SHIFT (0U) #define PWM_PWMPR_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMPR_PERIOD_SHIFT)) & PWM_PWMPR_PERIOD_MASK) /*! @} */ /*! @name PWMCNR - PWM Counter Register */ /*! @{ */ #define PWM_PWMCNR_COUNT_MASK (0xFFFFU) #define PWM_PWMCNR_COUNT_SHIFT (0U) #define PWM_PWMCNR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCNR_COUNT_SHIFT)) & PWM_PWMCNR_COUNT_MASK) /*! @} */ /*! * @} */ /* end of group PWM_Register_Masks */ /* PWM - Peripheral instance base addresses */ /** Peripheral PWM1 base address */ #define PWM1_BASE (0x30660000u) /** Peripheral PWM1 base pointer */ #define PWM1 ((PWM_Type *)PWM1_BASE) /** Peripheral PWM2 base address */ #define PWM2_BASE (0x30670000u) /** Peripheral PWM2 base pointer */ #define PWM2 ((PWM_Type *)PWM2_BASE) /** Peripheral PWM3 base address */ #define PWM3_BASE (0x30680000u) /** Peripheral PWM3 base pointer */ #define PWM3 ((PWM_Type *)PWM3_BASE) /** Peripheral PWM4 base address */ #define PWM4_BASE (0x30690000u) /** Peripheral PWM4 base pointer */ #define PWM4 ((PWM_Type *)PWM4_BASE) /** Array initializer of PWM peripheral base addresses */ #define PWM_BASE_ADDRS \ { \ 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE \ } /** Array initializer of PWM peripheral base pointers */ #define PWM_BASE_PTRS \ { \ (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 \ } /** Interrupt vectors for the PWM peripheral type */ #define PWM_IRQS \ { \ NotAvail_IRQn, PWM1_IRQn, PWM2_IRQn, PWM3_IRQn, PWM4_IRQn \ } /*! * @} */ /* end of group PWM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- RDC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup RDC_Peripheral_Access_Layer RDC Peripheral Access Layer * @{ */ /** RDC - Register Layout Typedef */ typedef struct { __I uint32_t VIR; /**< Version Information, offset: 0x0 */ uint8_t RESERVED_0[32]; __IO uint32_t STAT; /**< Status, offset: 0x24 */ __IO uint32_t INTCTRL; /**< Interrupt and Control, offset: 0x28 */ __IO uint32_t INTSTAT; /**< Interrupt Status, offset: 0x2C */ uint8_t RESERVED_1[464]; __IO uint32_t MDA[27]; /**< Master Domain Assignment, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_2[404]; __IO uint32_t PDAP[118]; /**< Peripheral Domain Access Permissions, array offset: 0x400, array step: 0x4 */ uint8_t RESERVED_3[552]; struct { /* offset: 0x800, array step: 0x10 */ __IO uint32_t MRSA; /**< Memory Region Start Address, array offset: 0x800, array step: 0x10 */ __IO uint32_t MREA; /**< Memory Region End Address, array offset: 0x804, array step: 0x10 */ __IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, array step: 0x10 */ __IO uint32_t MRVS; /**< Memory Region Violation Status, array offset: 0x80C, array step: 0x10 */ } MR[52]; } RDC_Type; /* ---------------------------------------------------------------------------- -- RDC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RDC_Register_Masks RDC Register Masks * @{ */ /*! @name VIR - Version Information */ /*! @{ */ #define RDC_VIR_NDID_MASK (0xFU) #define RDC_VIR_NDID_SHIFT (0U) #define RDC_VIR_NDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NDID_SHIFT)) & RDC_VIR_NDID_MASK) #define RDC_VIR_NMSTR_MASK (0xFF0U) #define RDC_VIR_NMSTR_SHIFT (4U) #define RDC_VIR_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NMSTR_SHIFT)) & RDC_VIR_NMSTR_MASK) #define RDC_VIR_NPER_MASK (0xFF000U) #define RDC_VIR_NPER_SHIFT (12U) #define RDC_VIR_NPER(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NPER_SHIFT)) & RDC_VIR_NPER_MASK) #define RDC_VIR_NRGN_MASK (0xFF00000U) #define RDC_VIR_NRGN_SHIFT (20U) #define RDC_VIR_NRGN(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NRGN_SHIFT)) & RDC_VIR_NRGN_MASK) /*! @} */ /*! @name STAT - Status */ /*! @{ */ #define RDC_STAT_DID_MASK (0xFU) #define RDC_STAT_DID_SHIFT (0U) #define RDC_STAT_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_DID_SHIFT)) & RDC_STAT_DID_MASK) #define RDC_STAT_PDS_MASK (0x100U) #define RDC_STAT_PDS_SHIFT (8U) /*! PDS - Power Domain Status * 0b0..Power Down Domain is OFF * 0b1..Power Down Domain is ON */ #define RDC_STAT_PDS(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_PDS_SHIFT)) & RDC_STAT_PDS_MASK) /*! @} */ /*! @name INTCTRL - Interrupt and Control */ /*! @{ */ #define RDC_INTCTRL_RCI_EN_MASK (0x1U) #define RDC_INTCTRL_RCI_EN_SHIFT (0U) /*! RCI_EN - Restoration Complete Interrupt * 0b0..Interrupt Disabled * 0b1..Interrupt Enabled */ #define RDC_INTCTRL_RCI_EN(x) (((uint32_t)(((uint32_t)(x)) << RDC_INTCTRL_RCI_EN_SHIFT)) & RDC_INTCTRL_RCI_EN_MASK) /*! @} */ /*! @name INTSTAT - Interrupt Status */ /*! @{ */ #define RDC_INTSTAT_INT_MASK (0x1U) #define RDC_INTSTAT_INT_SHIFT (0U) /*! INT - Interrupt Status * 0b0..No Interrupt Pending * 0b1..Interrupt Pending */ #define RDC_INTSTAT_INT(x) (((uint32_t)(((uint32_t)(x)) << RDC_INTSTAT_INT_SHIFT)) & RDC_INTSTAT_INT_MASK) /*! @} */ /*! @name MDA - Master Domain Assignment */ /*! @{ */ #define RDC_MDA_DID_MASK (0x3U) #define RDC_MDA_DID_SHIFT (0U) /*! DID - Domain ID * 0b00..Master assigned to Processing Domain 0 * 0b01..Master assigned to Processing Domain 1 * 0b10..Master assigned to Processing Domain 2 * 0b11..Master assigned to Processing Domain 3 */ #define RDC_MDA_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_DID_SHIFT)) & RDC_MDA_DID_MASK) #define RDC_MDA_LCK_MASK (0x80000000U) #define RDC_MDA_LCK_SHIFT (31U) /*! LCK * 0b0..Not Locked * 0b1..Locked */ #define RDC_MDA_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_LCK_SHIFT)) & RDC_MDA_LCK_MASK) /*! @} */ /* The count of RDC_MDA */ #define RDC_MDA_COUNT (27U) /*! @name PDAP - Peripheral Domain Access Permissions */ /*! @{ */ #define RDC_PDAP_D0W_MASK (0x1U) #define RDC_PDAP_D0W_SHIFT (0U) /*! D0W - Domain 0 Write Access * 0b0..No Write Access * 0b1..Write Access Allowed */ #define RDC_PDAP_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0W_SHIFT)) & RDC_PDAP_D0W_MASK) #define RDC_PDAP_D0R_MASK (0x2U) #define RDC_PDAP_D0R_SHIFT (1U) /*! D0R - Domain 0 Read Access * 0b0..No Read Access * 0b1..Read Access Allowed */ #define RDC_PDAP_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0R_SHIFT)) & RDC_PDAP_D0R_MASK) #define RDC_PDAP_D1W_MASK (0x4U) #define RDC_PDAP_D1W_SHIFT (2U) /*! D1W - Domain 1 Write Access * 0b0..No Write Access * 0b1..Write Access Allowed */ #define RDC_PDAP_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1W_SHIFT)) & RDC_PDAP_D1W_MASK) #define RDC_PDAP_D1R_MASK (0x8U) #define RDC_PDAP_D1R_SHIFT (3U) /*! D1R - Domain 1 Read Access * 0b0..No Read Access * 0b1..Read Access Allowed */ #define RDC_PDAP_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1R_SHIFT)) & RDC_PDAP_D1R_MASK) #define RDC_PDAP_D2W_MASK (0x10U) #define RDC_PDAP_D2W_SHIFT (4U) /*! D2W - Domain 2 Write Access * 0b0..No Write Access * 0b1..Write Access Allowed */ #define RDC_PDAP_D2W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D2W_SHIFT)) & RDC_PDAP_D2W_MASK) #define RDC_PDAP_D2R_MASK (0x20U) #define RDC_PDAP_D2R_SHIFT (5U) /*! D2R - Domain 2 Read Access * 0b0..No Read Access * 0b1..Read Access Allowed */ #define RDC_PDAP_D2R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D2R_SHIFT)) & RDC_PDAP_D2R_MASK) #define RDC_PDAP_D3W_MASK (0x40U) #define RDC_PDAP_D3W_SHIFT (6U) /*! D3W - Domain 3 Write Access * 0b0..No Write Access * 0b1..Write Access Allowed */ #define RDC_PDAP_D3W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D3W_SHIFT)) & RDC_PDAP_D3W_MASK) #define RDC_PDAP_D3R_MASK (0x80U) #define RDC_PDAP_D3R_SHIFT (7U) /*! D3R - Domain 3 Read Access * 0b0..No Read Access * 0b1..Read Access Allowed */ #define RDC_PDAP_D3R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D3R_SHIFT)) & RDC_PDAP_D3R_MASK) #define RDC_PDAP_SREQ_MASK (0x40000000U) #define RDC_PDAP_SREQ_SHIFT (30U) /*! SREQ - Semaphore Required * 0b0..Semaphores have no effect * 0b1..Semaphores are enforced */ #define RDC_PDAP_SREQ(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_SREQ_SHIFT)) & RDC_PDAP_SREQ_MASK) #define RDC_PDAP_LCK_MASK (0x80000000U) #define RDC_PDAP_LCK_SHIFT (31U) /*! LCK - Peripheral Permissions Lock * 0b0..Not Locked * 0b1..Locked */ #define RDC_PDAP_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_LCK_SHIFT)) & RDC_PDAP_LCK_MASK) /*! @} */ /* The count of RDC_PDAP */ #define RDC_PDAP_COUNT (118U) /*! @name MRSA - Memory Region Start Address */ /*! @{ */ #define RDC_MRSA_SADR_MASK (0xFFFFFF80U) #define RDC_MRSA_SADR_SHIFT (7U) #define RDC_MRSA_SADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRSA_SADR_SHIFT)) & RDC_MRSA_SADR_MASK) /*! @} */ /* The count of RDC_MRSA */ #define RDC_MRSA_COUNT (52U) /*! @name MREA - Memory Region End Address */ /*! @{ */ #define RDC_MREA_EADR_MASK (0xFFFFFF80U) #define RDC_MREA_EADR_SHIFT (7U) #define RDC_MREA_EADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MREA_EADR_SHIFT)) & RDC_MREA_EADR_MASK) /*! @} */ /* The count of RDC_MREA */ #define RDC_MREA_COUNT (52U) /*! @name MRC - Memory Region Control */ /*! @{ */ #define RDC_MRC_D0W_MASK (0x1U) #define RDC_MRC_D0W_SHIFT (0U) /*! D0W - Domain 0 Write Access to Region * 0b0..Processing Domain 0 does not have Write access to the memory region * 0b1..Processing Domain 0 has Write access to the memory region */ #define RDC_MRC_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0W_SHIFT)) & RDC_MRC_D0W_MASK) #define RDC_MRC_D0R_MASK (0x2U) #define RDC_MRC_D0R_SHIFT (1U) /*! D0R - Domain 0 Read Access to Region * 0b0..Processing Domain 0 does not have Read access to the memory region * 0b1..Processing Domain 0 has Read access to the memory region */ #define RDC_MRC_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0R_SHIFT)) & RDC_MRC_D0R_MASK) #define RDC_MRC_D1W_MASK (0x4U) #define RDC_MRC_D1W_SHIFT (2U) /*! D1W - Domain 1 Write Access to Region * 0b0..Processing Domain 1 does not have Write access to the memory region * 0b1..Processing Domain 1 has Write access to the memory region */ #define RDC_MRC_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1W_SHIFT)) & RDC_MRC_D1W_MASK) #define RDC_MRC_D1R_MASK (0x8U) #define RDC_MRC_D1R_SHIFT (3U) /*! D1R - Domain 1 Read Access to Region * 0b0..Processing Domain 1 does not have Read access to the memory region * 0b1..Processing Domain 1 has Read access to the memory region */ #define RDC_MRC_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1R_SHIFT)) & RDC_MRC_D1R_MASK) #define RDC_MRC_D2W_MASK (0x10U) #define RDC_MRC_D2W_SHIFT (4U) /*! D2W - Domain 2 Write Access to Region * 0b0..Processing Domain 2 does not have Write access to the memory region * 0b1..Processing Domain 2 has Write access to the memory region */ #define RDC_MRC_D2W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D2W_SHIFT)) & RDC_MRC_D2W_MASK) #define RDC_MRC_D2R_MASK (0x20U) #define RDC_MRC_D2R_SHIFT (5U) /*! D2R - Domain 2 Read Access to Region * 0b0..Processing Domain 2 does not have Read access to the memory region * 0b1..Processing Domain 2 has Read access to the memory region */ #define RDC_MRC_D2R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D2R_SHIFT)) & RDC_MRC_D2R_MASK) #define RDC_MRC_D3W_MASK (0x40U) #define RDC_MRC_D3W_SHIFT (6U) /*! D3W - Domain 3 Write Access to Region * 0b0..Processing Domain 3 does not have Write access to the memory region * 0b1..Processing Domain 3 has Read access to the memory region */ #define RDC_MRC_D3W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D3W_SHIFT)) & RDC_MRC_D3W_MASK) #define RDC_MRC_D3R_MASK (0x80U) #define RDC_MRC_D3R_SHIFT (7U) /*! D3R - Domain 3 Read Access to Region * 0b0..Processing Domain 3 does not have Read access to the memory region * 0b1..Processing Domain 3 has Read access to the memory region */ #define RDC_MRC_D3R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D3R_SHIFT)) & RDC_MRC_D3R_MASK) #define RDC_MRC_ENA_MASK (0x40000000U) #define RDC_MRC_ENA_SHIFT (30U) /*! ENA - Region Enable * 0b0..Memory region is not defined or restricted. * 0b1..Memory boundaries, domain permissions and controls are in effect. */ #define RDC_MRC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_ENA_SHIFT)) & RDC_MRC_ENA_MASK) #define RDC_MRC_LCK_MASK (0x80000000U) #define RDC_MRC_LCK_SHIFT (31U) /*! LCK - Region Lock * 0b0..No Lock. All fields in this register may be modified. * 0b1..Locked. No fields in this register may be modified except ENA, which may be set but not cleared. */ #define RDC_MRC_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_LCK_SHIFT)) & RDC_MRC_LCK_MASK) /*! @} */ /* The count of RDC_MRC */ #define RDC_MRC_COUNT (52U) /*! @name MRVS - Memory Region Violation Status */ /*! @{ */ #define RDC_MRVS_VDID_MASK (0x3U) #define RDC_MRVS_VDID_SHIFT (0U) /*! VDID - Violating Domain ID * 0b00..Processing Domain 0 * 0b01..Processing Domain 1 * 0b10..Processing Domain 2 * 0b11..Processing Domain 3 */ #define RDC_MRVS_VDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VDID_SHIFT)) & RDC_MRVS_VDID_MASK) #define RDC_MRVS_AD_MASK (0x10U) #define RDC_MRVS_AD_SHIFT (4U) #define RDC_MRVS_AD(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_AD_SHIFT)) & RDC_MRVS_AD_MASK) #define RDC_MRVS_VADR_MASK (0xFFFFFFE0U) #define RDC_MRVS_VADR_SHIFT (5U) #define RDC_MRVS_VADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VADR_SHIFT)) & RDC_MRVS_VADR_MASK) /*! @} */ /* The count of RDC_MRVS */ #define RDC_MRVS_COUNT (52U) /*! * @} */ /* end of group RDC_Register_Masks */ /* RDC - Peripheral instance base addresses */ /** Peripheral RDC base address */ #define RDC_BASE (0x303D0000u) /** Peripheral RDC base pointer */ #define RDC ((RDC_Type *)RDC_BASE) /** Array initializer of RDC peripheral base addresses */ #define RDC_BASE_ADDRS \ { \ RDC_BASE \ } /** Array initializer of RDC peripheral base pointers */ #define RDC_BASE_PTRS \ { \ RDC \ } /** Interrupt vectors for the RDC peripheral type */ #define RDC_IRQS \ { \ RDC_IRQn \ } /*! * @} */ /* end of group RDC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- RDC_SEMAPHORE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup RDC_SEMAPHORE_Peripheral_Access_Layer RDC_SEMAPHORE Peripheral Access Layer * @{ */ /** RDC_SEMAPHORE - Register Layout Typedef */ typedef struct { __IO uint8_t GATE0; /**< Gate Register, offset: 0x0 */ __IO uint8_t GATE1; /**< Gate Register, offset: 0x1 */ __IO uint8_t GATE2; /**< Gate Register, offset: 0x2 */ __IO uint8_t GATE3; /**< Gate Register, offset: 0x3 */ __IO uint8_t GATE4; /**< Gate Register, offset: 0x4 */ __IO uint8_t GATE5; /**< Gate Register, offset: 0x5 */ __IO uint8_t GATE6; /**< Gate Register, offset: 0x6 */ __IO uint8_t GATE7; /**< Gate Register, offset: 0x7 */ __IO uint8_t GATE8; /**< Gate Register, offset: 0x8 */ __IO uint8_t GATE9; /**< Gate Register, offset: 0x9 */ __IO uint8_t GATE10; /**< Gate Register, offset: 0xA */ __IO uint8_t GATE11; /**< Gate Register, offset: 0xB */ __IO uint8_t GATE12; /**< Gate Register, offset: 0xC */ __IO uint8_t GATE13; /**< Gate Register, offset: 0xD */ __IO uint8_t GATE14; /**< Gate Register, offset: 0xE */ __IO uint8_t GATE15; /**< Gate Register, offset: 0xF */ __IO uint8_t GATE16; /**< Gate Register, offset: 0x10 */ __IO uint8_t GATE17; /**< Gate Register, offset: 0x11 */ __IO uint8_t GATE18; /**< Gate Register, offset: 0x12 */ __IO uint8_t GATE19; /**< Gate Register, offset: 0x13 */ __IO uint8_t GATE20; /**< Gate Register, offset: 0x14 */ __IO uint8_t GATE21; /**< Gate Register, offset: 0x15 */ __IO uint8_t GATE22; /**< Gate Register, offset: 0x16 */ __IO uint8_t GATE23; /**< Gate Register, offset: 0x17 */ __IO uint8_t GATE24; /**< Gate Register, offset: 0x18 */ __IO uint8_t GATE25; /**< Gate Register, offset: 0x19 */ __IO uint8_t GATE26; /**< Gate Register, offset: 0x1A */ __IO uint8_t GATE27; /**< Gate Register, offset: 0x1B */ __IO uint8_t GATE28; /**< Gate Register, offset: 0x1C */ __IO uint8_t GATE29; /**< Gate Register, offset: 0x1D */ __IO uint8_t GATE30; /**< Gate Register, offset: 0x1E */ __IO uint8_t GATE31; /**< Gate Register, offset: 0x1F */ __IO uint8_t GATE32; /**< Gate Register, offset: 0x20 */ __IO uint8_t GATE33; /**< Gate Register, offset: 0x21 */ __IO uint8_t GATE34; /**< Gate Register, offset: 0x22 */ __IO uint8_t GATE35; /**< Gate Register, offset: 0x23 */ __IO uint8_t GATE36; /**< Gate Register, offset: 0x24 */ __IO uint8_t GATE37; /**< Gate Register, offset: 0x25 */ __IO uint8_t GATE38; /**< Gate Register, offset: 0x26 */ __IO uint8_t GATE39; /**< Gate Register, offset: 0x27 */ __IO uint8_t GATE40; /**< Gate Register, offset: 0x28 */ __IO uint8_t GATE41; /**< Gate Register, offset: 0x29 */ __IO uint8_t GATE42; /**< Gate Register, offset: 0x2A */ __IO uint8_t GATE43; /**< Gate Register, offset: 0x2B */ __IO uint8_t GATE44; /**< Gate Register, offset: 0x2C */ __IO uint8_t GATE45; /**< Gate Register, offset: 0x2D */ __IO uint8_t GATE46; /**< Gate Register, offset: 0x2E */ __IO uint8_t GATE47; /**< Gate Register, offset: 0x2F */ __IO uint8_t GATE48; /**< Gate Register, offset: 0x30 */ __IO uint8_t GATE49; /**< Gate Register, offset: 0x31 */ __IO uint8_t GATE50; /**< Gate Register, offset: 0x32 */ __IO uint8_t GATE51; /**< Gate Register, offset: 0x33 */ __IO uint8_t GATE52; /**< Gate Register, offset: 0x34 */ __IO uint8_t GATE53; /**< Gate Register, offset: 0x35 */ __IO uint8_t GATE54; /**< Gate Register, offset: 0x36 */ __IO uint8_t GATE55; /**< Gate Register, offset: 0x37 */ __IO uint8_t GATE56; /**< Gate Register, offset: 0x38 */ __IO uint8_t GATE57; /**< Gate Register, offset: 0x39 */ __IO uint8_t GATE58; /**< Gate Register, offset: 0x3A */ __IO uint8_t GATE59; /**< Gate Register, offset: 0x3B */ __IO uint8_t GATE60; /**< Gate Register, offset: 0x3C */ __IO uint8_t GATE61; /**< Gate Register, offset: 0x3D */ __IO uint8_t GATE62; /**< Gate Register, offset: 0x3E */ __IO uint8_t GATE63; /**< Gate Register, offset: 0x3F */ union { /* offset: 0x40 */ __IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x40 */ __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */ }; } RDC_SEMAPHORE_Type; /* ---------------------------------------------------------------------------- -- RDC_SEMAPHORE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks * @{ */ /*! @name GATE0 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE0_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE0_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE0_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE0_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE0_GTFSM_MASK) #define RDC_SEMAPHORE_GATE0_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE0_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE0_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE0_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE0_LDOM_MASK) /*! @} */ /*! @name GATE1 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE1_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE1_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE1_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE1_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE1_GTFSM_MASK) #define RDC_SEMAPHORE_GATE1_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE1_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE1_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE1_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE1_LDOM_MASK) /*! @} */ /*! @name GATE2 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE2_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE2_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE2_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE2_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE2_GTFSM_MASK) #define RDC_SEMAPHORE_GATE2_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE2_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE2_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE2_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE2_LDOM_MASK) /*! @} */ /*! @name GATE3 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE3_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE3_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE3_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE3_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE3_GTFSM_MASK) #define RDC_SEMAPHORE_GATE3_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE3_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE3_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE3_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE3_LDOM_MASK) /*! @} */ /*! @name GATE4 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE4_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE4_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE4_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE4_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE4_GTFSM_MASK) #define RDC_SEMAPHORE_GATE4_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE4_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE4_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE4_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE4_LDOM_MASK) /*! @} */ /*! @name GATE5 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE5_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE5_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE5_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE5_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE5_GTFSM_MASK) #define RDC_SEMAPHORE_GATE5_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE5_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE5_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE5_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE5_LDOM_MASK) /*! @} */ /*! @name GATE6 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE6_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE6_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE6_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE6_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE6_GTFSM_MASK) #define RDC_SEMAPHORE_GATE6_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE6_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE6_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE6_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE6_LDOM_MASK) /*! @} */ /*! @name GATE7 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE7_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE7_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE7_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE7_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE7_GTFSM_MASK) #define RDC_SEMAPHORE_GATE7_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE7_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE7_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE7_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE7_LDOM_MASK) /*! @} */ /*! @name GATE8 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE8_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE8_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE8_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE8_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE8_GTFSM_MASK) #define RDC_SEMAPHORE_GATE8_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE8_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE8_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE8_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE8_LDOM_MASK) /*! @} */ /*! @name GATE9 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE9_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE9_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE9_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE9_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE9_GTFSM_MASK) #define RDC_SEMAPHORE_GATE9_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE9_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE9_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE9_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE9_LDOM_MASK) /*! @} */ /*! @name GATE10 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE10_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE10_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE10_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE10_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE10_GTFSM_MASK) #define RDC_SEMAPHORE_GATE10_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE10_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE10_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE10_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE10_LDOM_MASK) /*! @} */ /*! @name GATE11 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE11_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE11_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE11_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE11_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE11_GTFSM_MASK) #define RDC_SEMAPHORE_GATE11_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE11_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE11_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE11_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE11_LDOM_MASK) /*! @} */ /*! @name GATE12 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE12_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE12_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE12_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE12_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE12_GTFSM_MASK) #define RDC_SEMAPHORE_GATE12_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE12_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE12_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE12_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE12_LDOM_MASK) /*! @} */ /*! @name GATE13 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE13_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE13_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE13_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE13_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE13_GTFSM_MASK) #define RDC_SEMAPHORE_GATE13_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE13_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE13_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE13_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE13_LDOM_MASK) /*! @} */ /*! @name GATE14 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE14_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE14_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE14_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE14_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE14_GTFSM_MASK) #define RDC_SEMAPHORE_GATE14_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE14_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE14_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE14_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE14_LDOM_MASK) /*! @} */ /*! @name GATE15 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE15_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE15_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE15_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE15_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE15_GTFSM_MASK) #define RDC_SEMAPHORE_GATE15_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE15_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE15_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE15_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE15_LDOM_MASK) /*! @} */ /*! @name GATE16 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE16_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE16_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE16_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE16_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE16_GTFSM_MASK) #define RDC_SEMAPHORE_GATE16_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE16_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE16_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE16_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE16_LDOM_MASK) /*! @} */ /*! @name GATE17 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE17_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE17_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE17_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE17_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE17_GTFSM_MASK) #define RDC_SEMAPHORE_GATE17_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE17_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE17_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE17_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE17_LDOM_MASK) /*! @} */ /*! @name GATE18 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE18_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE18_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE18_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE18_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE18_GTFSM_MASK) #define RDC_SEMAPHORE_GATE18_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE18_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE18_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE18_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE18_LDOM_MASK) /*! @} */ /*! @name GATE19 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE19_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE19_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE19_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE19_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE19_GTFSM_MASK) #define RDC_SEMAPHORE_GATE19_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE19_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE19_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE19_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE19_LDOM_MASK) /*! @} */ /*! @name GATE20 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE20_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE20_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE20_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE20_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE20_GTFSM_MASK) #define RDC_SEMAPHORE_GATE20_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE20_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE20_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE20_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE20_LDOM_MASK) /*! @} */ /*! @name GATE21 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE21_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE21_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE21_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE21_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE21_GTFSM_MASK) #define RDC_SEMAPHORE_GATE21_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE21_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE21_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE21_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE21_LDOM_MASK) /*! @} */ /*! @name GATE22 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE22_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE22_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE22_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE22_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE22_GTFSM_MASK) #define RDC_SEMAPHORE_GATE22_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE22_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE22_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE22_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE22_LDOM_MASK) /*! @} */ /*! @name GATE23 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE23_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE23_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE23_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE23_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE23_GTFSM_MASK) #define RDC_SEMAPHORE_GATE23_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE23_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE23_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE23_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE23_LDOM_MASK) /*! @} */ /*! @name GATE24 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE24_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE24_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE24_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE24_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE24_GTFSM_MASK) #define RDC_SEMAPHORE_GATE24_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE24_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE24_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE24_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE24_LDOM_MASK) /*! @} */ /*! @name GATE25 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE25_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE25_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE25_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE25_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE25_GTFSM_MASK) #define RDC_SEMAPHORE_GATE25_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE25_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE25_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE25_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE25_LDOM_MASK) /*! @} */ /*! @name GATE26 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE26_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE26_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE26_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE26_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE26_GTFSM_MASK) #define RDC_SEMAPHORE_GATE26_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE26_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE26_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE26_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE26_LDOM_MASK) /*! @} */ /*! @name GATE27 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE27_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE27_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE27_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE27_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE27_GTFSM_MASK) #define RDC_SEMAPHORE_GATE27_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE27_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE27_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE27_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE27_LDOM_MASK) /*! @} */ /*! @name GATE28 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE28_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE28_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE28_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE28_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE28_GTFSM_MASK) #define RDC_SEMAPHORE_GATE28_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE28_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE28_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE28_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE28_LDOM_MASK) /*! @} */ /*! @name GATE29 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE29_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE29_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE29_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE29_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE29_GTFSM_MASK) #define RDC_SEMAPHORE_GATE29_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE29_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE29_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE29_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE29_LDOM_MASK) /*! @} */ /*! @name GATE30 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE30_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE30_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE30_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE30_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE30_GTFSM_MASK) #define RDC_SEMAPHORE_GATE30_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE30_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE30_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE30_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE30_LDOM_MASK) /*! @} */ /*! @name GATE31 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE31_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE31_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE31_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE31_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE31_GTFSM_MASK) #define RDC_SEMAPHORE_GATE31_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE31_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE31_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE31_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE31_LDOM_MASK) /*! @} */ /*! @name GATE32 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE32_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE32_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE32_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE32_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE32_GTFSM_MASK) #define RDC_SEMAPHORE_GATE32_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE32_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE32_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE32_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE32_LDOM_MASK) /*! @} */ /*! @name GATE33 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE33_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE33_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE33_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE33_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE33_GTFSM_MASK) #define RDC_SEMAPHORE_GATE33_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE33_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE33_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE33_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE33_LDOM_MASK) /*! @} */ /*! @name GATE34 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE34_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE34_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE34_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE34_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE34_GTFSM_MASK) #define RDC_SEMAPHORE_GATE34_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE34_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE34_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE34_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE34_LDOM_MASK) /*! @} */ /*! @name GATE35 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE35_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE35_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE35_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE35_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE35_GTFSM_MASK) #define RDC_SEMAPHORE_GATE35_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE35_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE35_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE35_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE35_LDOM_MASK) /*! @} */ /*! @name GATE36 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE36_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE36_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE36_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE36_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE36_GTFSM_MASK) #define RDC_SEMAPHORE_GATE36_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE36_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE36_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE36_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE36_LDOM_MASK) /*! @} */ /*! @name GATE37 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE37_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE37_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE37_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE37_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE37_GTFSM_MASK) #define RDC_SEMAPHORE_GATE37_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE37_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE37_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE37_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE37_LDOM_MASK) /*! @} */ /*! @name GATE38 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE38_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE38_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE38_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE38_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE38_GTFSM_MASK) #define RDC_SEMAPHORE_GATE38_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE38_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE38_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE38_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE38_LDOM_MASK) /*! @} */ /*! @name GATE39 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE39_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE39_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE39_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE39_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE39_GTFSM_MASK) #define RDC_SEMAPHORE_GATE39_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE39_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE39_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE39_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE39_LDOM_MASK) /*! @} */ /*! @name GATE40 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE40_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE40_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE40_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE40_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE40_GTFSM_MASK) #define RDC_SEMAPHORE_GATE40_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE40_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE40_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE40_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE40_LDOM_MASK) /*! @} */ /*! @name GATE41 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE41_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE41_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE41_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE41_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE41_GTFSM_MASK) #define RDC_SEMAPHORE_GATE41_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE41_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE41_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE41_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE41_LDOM_MASK) /*! @} */ /*! @name GATE42 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE42_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE42_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE42_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE42_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE42_GTFSM_MASK) #define RDC_SEMAPHORE_GATE42_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE42_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE42_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE42_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE42_LDOM_MASK) /*! @} */ /*! @name GATE43 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE43_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE43_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE43_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE43_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE43_GTFSM_MASK) #define RDC_SEMAPHORE_GATE43_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE43_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE43_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE43_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE43_LDOM_MASK) /*! @} */ /*! @name GATE44 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE44_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE44_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE44_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE44_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE44_GTFSM_MASK) #define RDC_SEMAPHORE_GATE44_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE44_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE44_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE44_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE44_LDOM_MASK) /*! @} */ /*! @name GATE45 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE45_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE45_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE45_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE45_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE45_GTFSM_MASK) #define RDC_SEMAPHORE_GATE45_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE45_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE45_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE45_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE45_LDOM_MASK) /*! @} */ /*! @name GATE46 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE46_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE46_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE46_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE46_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE46_GTFSM_MASK) #define RDC_SEMAPHORE_GATE46_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE46_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE46_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE46_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE46_LDOM_MASK) /*! @} */ /*! @name GATE47 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE47_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE47_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE47_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE47_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE47_GTFSM_MASK) #define RDC_SEMAPHORE_GATE47_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE47_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE47_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE47_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE47_LDOM_MASK) /*! @} */ /*! @name GATE48 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE48_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE48_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE48_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE48_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE48_GTFSM_MASK) #define RDC_SEMAPHORE_GATE48_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE48_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE48_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE48_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE48_LDOM_MASK) /*! @} */ /*! @name GATE49 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE49_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE49_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE49_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE49_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE49_GTFSM_MASK) #define RDC_SEMAPHORE_GATE49_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE49_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE49_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE49_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE49_LDOM_MASK) /*! @} */ /*! @name GATE50 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE50_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE50_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE50_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE50_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE50_GTFSM_MASK) #define RDC_SEMAPHORE_GATE50_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE50_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE50_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE50_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE50_LDOM_MASK) /*! @} */ /*! @name GATE51 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE51_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE51_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE51_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE51_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE51_GTFSM_MASK) #define RDC_SEMAPHORE_GATE51_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE51_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE51_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE51_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE51_LDOM_MASK) /*! @} */ /*! @name GATE52 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE52_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE52_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE52_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE52_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE52_GTFSM_MASK) #define RDC_SEMAPHORE_GATE52_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE52_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE52_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE52_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE52_LDOM_MASK) /*! @} */ /*! @name GATE53 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE53_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE53_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE53_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE53_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE53_GTFSM_MASK) #define RDC_SEMAPHORE_GATE53_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE53_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE53_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE53_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE53_LDOM_MASK) /*! @} */ /*! @name GATE54 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE54_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE54_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE54_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE54_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE54_GTFSM_MASK) #define RDC_SEMAPHORE_GATE54_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE54_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE54_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE54_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE54_LDOM_MASK) /*! @} */ /*! @name GATE55 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE55_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE55_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE55_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE55_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE55_GTFSM_MASK) #define RDC_SEMAPHORE_GATE55_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE55_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE55_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE55_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE55_LDOM_MASK) /*! @} */ /*! @name GATE56 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE56_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE56_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE56_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE56_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE56_GTFSM_MASK) #define RDC_SEMAPHORE_GATE56_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE56_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE56_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE56_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE56_LDOM_MASK) /*! @} */ /*! @name GATE57 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE57_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE57_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE57_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE57_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE57_GTFSM_MASK) #define RDC_SEMAPHORE_GATE57_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE57_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE57_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE57_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE57_LDOM_MASK) /*! @} */ /*! @name GATE58 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE58_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE58_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE58_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE58_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE58_GTFSM_MASK) #define RDC_SEMAPHORE_GATE58_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE58_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE58_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE58_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE58_LDOM_MASK) /*! @} */ /*! @name GATE59 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE59_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE59_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE59_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE59_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE59_GTFSM_MASK) #define RDC_SEMAPHORE_GATE59_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE59_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE59_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE59_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE59_LDOM_MASK) /*! @} */ /*! @name GATE60 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE60_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE60_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE60_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE60_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE60_GTFSM_MASK) #define RDC_SEMAPHORE_GATE60_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE60_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE60_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE60_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE60_LDOM_MASK) /*! @} */ /*! @name GATE61 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE61_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE61_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE61_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE61_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE61_GTFSM_MASK) #define RDC_SEMAPHORE_GATE61_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE61_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE61_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE61_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE61_LDOM_MASK) /*! @} */ /*! @name GATE62 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE62_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE62_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE62_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE62_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE62_GTFSM_MASK) #define RDC_SEMAPHORE_GATE62_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE62_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE62_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE62_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE62_LDOM_MASK) /*! @} */ /*! @name GATE63 - Gate Register */ /*! @{ */ #define RDC_SEMAPHORE_GATE63_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE63_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b0000..The gate is unlocked (free). * 0b0001..The gate has been locked by processor with master_index = 0. * 0b0010..The gate has been locked by processor with master_index = 1. * 0b0011..The gate has been locked by processor with master_index = 2. * 0b0100..The gate has been locked by processor with master_index = 3. * 0b0101..The gate has been locked by processor with master_index = 4. * 0b0110..The gate has been locked by processor with master_index = 5. * 0b0111..The gate has been locked by processor with master_index = 6. * 0b1000..The gate has been locked by processor with master_index = 7. * 0b1001..The gate has been locked by processor with master_index = 8. * 0b1010..The gate has been locked by processor with master_index = 9. * 0b1011..The gate has been locked by processor with master_index = 10. * 0b1100..The gate has been locked by processor with master_index = 11. * 0b1101..The gate has been locked by processor with master_index = 12. * 0b1110..The gate has been locked by processor with master_index = 13. * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE63_GTFSM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE63_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE63_GTFSM_MASK) #define RDC_SEMAPHORE_GATE63_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE63_LDOM_SHIFT (4U) /*! LDOM * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) * 0b01..The gate has been locked by domain 1. * 0b10..The gate has been locked by domain 2. * 0b11..The gate has been locked by domain 3. */ #define RDC_SEMAPHORE_GATE63_LDOM(x) \ (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE63_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE63_LDOM_MASK) /*! @} */ /*! @name RSTGT_R - Reset Gate Read */ /*! @{ */ #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK (0xFU) #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT (0U) #define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x) \ (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK) #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK (0x30U) #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT (4U) /*! RSTGSM * 0b00..Idle, waiting for the first data pattern write. * 0b01..Waiting for the second data pattern write. * 0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, * this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists * for only one clock cycle. Software will never be able to observe this state. * 0b11..This state encoding is never used and therefore reserved. */ #define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x) \ (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK) #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK (0xFF00U) #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT (8U) #define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x) \ (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK) /*! @} */ /*! @name RSTGT_W - Reset Gate Write */ /*! @{ */ #define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK (0xFFU) #define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT (0U) #define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) \ (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK) #define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK (0xFF00U) #define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT (8U) #define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) \ (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK) /*! @} */ /*! * @} */ /* end of group RDC_SEMAPHORE_Register_Masks */ /* RDC_SEMAPHORE - Peripheral instance base addresses */ /** Peripheral RDC_SEMAPHORE1 base address */ #define RDC_SEMAPHORE1_BASE (0x303B0000u) /** Peripheral RDC_SEMAPHORE1 base pointer */ #define RDC_SEMAPHORE1 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE1_BASE) /** Peripheral RDC_SEMAPHORE2 base address */ #define RDC_SEMAPHORE2_BASE (0x303C0000u) /** Peripheral RDC_SEMAPHORE2 base pointer */ #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE) /** Array initializer of RDC_SEMAPHORE peripheral base addresses */ #define RDC_SEMAPHORE_BASE_ADDRS \ { \ 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE \ } /** Array initializer of RDC_SEMAPHORE peripheral base pointers */ #define RDC_SEMAPHORE_BASE_PTRS \ { \ (RDC_SEMAPHORE_Type *)0u, RDC_SEMAPHORE1, RDC_SEMAPHORE2 \ } /*! * @} */ /* end of group RDC_SEMAPHORE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SDMAARM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SDMAARM_Peripheral_Access_Layer SDMAARM Peripheral Access Layer * @{ */ /** SDMAARM - Register Layout Typedef */ typedef struct { __IO uint32_t MC0PTR; /**< Arm platform Channel 0 Pointer, offset: 0x0 */ __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */ __IO uint32_t STOP_STAT; /**< Channel Stop/Channel Status, offset: 0x8 */ __IO uint32_t HSTART; /**< Channel Start, offset: 0xC */ __IO uint32_t EVTOVR; /**< Channel Event Override, offset: 0x10 */ __IO uint32_t DSPOVR; /**< Channel BP Override, offset: 0x14 */ __IO uint32_t HOSTOVR; /**< Channel Arm platform Override, offset: 0x18 */ __IO uint32_t EVTPEND; /**< Channel Event Pending, offset: 0x1C */ uint8_t RESERVED_0[4]; __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ __I uint32_t EVTERR; /**< DMA Request Error Register, offset: 0x28 */ __IO uint32_t INTRMASK; /**< Channel Arm platform Interrupt Mask, offset: 0x2C */ __I uint32_t PSW; /**< Schedule Status, offset: 0x30 */ __I uint32_t EVTERRDBG; /**< DMA Request Error Register, offset: 0x34 */ __IO uint32_t CONFIG; /**< Configuration Register, offset: 0x38 */ __IO uint32_t SDMA_LOCK; /**< SDMA LOCK, offset: 0x3C */ __IO uint32_t ONCE_ENB; /**< OnCE Enable, offset: 0x40 */ __IO uint32_t ONCE_DATA; /**< OnCE Data Register, offset: 0x44 */ __IO uint32_t ONCE_INSTR; /**< OnCE Instruction Register, offset: 0x48 */ __I uint32_t ONCE_STAT; /**< OnCE Status Register, offset: 0x4C */ __IO uint32_t ONCE_CMD; /**< OnCE Command Register, offset: 0x50 */ uint8_t RESERVED_1[4]; __IO uint32_t ILLINSTADDR; /**< Illegal Instruction Trap Address, offset: 0x58 */ __IO uint32_t CHN0ADDR; /**< Channel 0 Boot Address, offset: 0x5C */ __I uint32_t EVT_MIRROR; /**< DMA Requests, offset: 0x60 */ __I uint32_t EVT_MIRROR2; /**< DMA Requests 2, offset: 0x64 */ uint8_t RESERVED_2[8]; __IO uint32_t XTRIG_CONF1; /**< Cross-Trigger Events Configuration Register 1, offset: 0x70 */ __IO uint32_t XTRIG_CONF2; /**< Cross-Trigger Events Configuration Register 2, offset: 0x74 */ uint8_t RESERVED_3[136]; __IO uint32_t SDMA_CHNPRI[32]; /**< Channel Priority Registers, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_4[128]; __IO uint32_t CHNENBL[48]; /**< Channel Enable RAM, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_5[3392]; __IO uint32_t DONE0_CONFIG; /**< SDMA DONE0 Configuration, offset: 0x1000 */ __IO uint32_t DONE1_CONFIG; /**< SDMA DONE1 Configuration, offset: 0x1004 */ } SDMAARM_Type; /* ---------------------------------------------------------------------------- -- SDMAARM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks * @{ */ /*! @name MC0PTR - Arm platform Channel 0 Pointer */ /*! @{ */ #define SDMAARM_MC0PTR_MC0PTR_MASK (0xFFFFFFFFU) #define SDMAARM_MC0PTR_MC0PTR_SHIFT (0U) #define SDMAARM_MC0PTR_MC0PTR(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_MC0PTR_MC0PTR_SHIFT)) & SDMAARM_MC0PTR_MC0PTR_MASK) /*! @} */ /*! @name INTR - Channel Interrupts */ /*! @{ */ #define SDMAARM_INTR_HI_MASK (0xFFFFFFFFU) #define SDMAARM_INTR_HI_SHIFT (0U) #define SDMAARM_INTR_HI(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTR_HI_SHIFT)) & SDMAARM_INTR_HI_MASK) /*! @} */ /*! @name STOP_STAT - Channel Stop/Channel Status */ /*! @{ */ #define SDMAARM_STOP_STAT_HE_MASK (0xFFFFFFFFU) #define SDMAARM_STOP_STAT_HE_SHIFT (0U) #define SDMAARM_STOP_STAT_HE(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_STOP_STAT_HE_SHIFT)) & SDMAARM_STOP_STAT_HE_MASK) /*! @} */ /*! @name HSTART - Channel Start */ /*! @{ */ #define SDMAARM_HSTART_HSTART_HE_MASK (0xFFFFFFFFU) #define SDMAARM_HSTART_HSTART_HE_SHIFT (0U) #define SDMAARM_HSTART_HSTART_HE(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_HSTART_HSTART_HE_SHIFT)) & SDMAARM_HSTART_HSTART_HE_MASK) /*! @} */ /*! @name EVTOVR - Channel Event Override */ /*! @{ */ #define SDMAARM_EVTOVR_EO_MASK (0xFFFFFFFFU) #define SDMAARM_EVTOVR_EO_SHIFT (0U) #define SDMAARM_EVTOVR_EO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTOVR_EO_SHIFT)) & SDMAARM_EVTOVR_EO_MASK) /*! @} */ /*! @name DSPOVR - Channel BP Override */ /*! @{ */ #define SDMAARM_DSPOVR_DO_MASK (0xFFFFFFFFU) #define SDMAARM_DSPOVR_DO_SHIFT (0U) /*! DO * 0b00000000000000000000000000000000..- Reserved * 0b00000000000000000000000000000001..- Reset value. */ #define SDMAARM_DSPOVR_DO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DSPOVR_DO_SHIFT)) & SDMAARM_DSPOVR_DO_MASK) /*! @} */ /*! @name HOSTOVR - Channel Arm platform Override */ /*! @{ */ #define SDMAARM_HOSTOVR_HO_MASK (0xFFFFFFFFU) #define SDMAARM_HOSTOVR_HO_SHIFT (0U) #define SDMAARM_HOSTOVR_HO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_HOSTOVR_HO_SHIFT)) & SDMAARM_HOSTOVR_HO_MASK) /*! @} */ /*! @name EVTPEND - Channel Event Pending */ /*! @{ */ #define SDMAARM_EVTPEND_EP_MASK (0xFFFFFFFFU) #define SDMAARM_EVTPEND_EP_SHIFT (0U) #define SDMAARM_EVTPEND_EP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTPEND_EP_SHIFT)) & SDMAARM_EVTPEND_EP_MASK) /*! @} */ /*! @name RESET - Reset Register */ /*! @{ */ #define SDMAARM_RESET_RESET_MASK (0x1U) #define SDMAARM_RESET_RESET_SHIFT (0U) #define SDMAARM_RESET_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESET_SHIFT)) & SDMAARM_RESET_RESET_MASK) #define SDMAARM_RESET_RESCHED_MASK (0x2U) #define SDMAARM_RESET_RESCHED_SHIFT (1U) #define SDMAARM_RESET_RESCHED(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESCHED_SHIFT)) & SDMAARM_RESET_RESCHED_MASK) /*! @} */ /*! @name EVTERR - DMA Request Error Register */ /*! @{ */ #define SDMAARM_EVTERR_CHNERR_MASK (0xFFFFFFFFU) #define SDMAARM_EVTERR_CHNERR_SHIFT (0U) #define SDMAARM_EVTERR_CHNERR(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERR_CHNERR_SHIFT)) & SDMAARM_EVTERR_CHNERR_MASK) /*! @} */ /*! @name INTRMASK - Channel Arm platform Interrupt Mask */ /*! @{ */ #define SDMAARM_INTRMASK_HIMASK_MASK (0xFFFFFFFFU) #define SDMAARM_INTRMASK_HIMASK_SHIFT (0U) #define SDMAARM_INTRMASK_HIMASK(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTRMASK_HIMASK_SHIFT)) & SDMAARM_INTRMASK_HIMASK_MASK) /*! @} */ /*! @name PSW - Schedule Status */ /*! @{ */ #define SDMAARM_PSW_CCR_MASK (0xFU) #define SDMAARM_PSW_CCR_SHIFT (0U) #define SDMAARM_PSW_CCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCR_SHIFT)) & SDMAARM_PSW_CCR_MASK) #define SDMAARM_PSW_CCP_MASK (0xF0U) #define SDMAARM_PSW_CCP_SHIFT (4U) /*! CCP * 0b0000..No running channel * 0b0001..Active channel priority */ #define SDMAARM_PSW_CCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCP_SHIFT)) & SDMAARM_PSW_CCP_MASK) #define SDMAARM_PSW_NCR_MASK (0x1F00U) #define SDMAARM_PSW_NCR_SHIFT (8U) #define SDMAARM_PSW_NCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCR_SHIFT)) & SDMAARM_PSW_NCR_MASK) #define SDMAARM_PSW_NCP_MASK (0xE000U) #define SDMAARM_PSW_NCP_SHIFT (13U) /*! NCP * 0b000..No running channel * 0b001..Active channel priority */ #define SDMAARM_PSW_NCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCP_SHIFT)) & SDMAARM_PSW_NCP_MASK) /*! @} */ /*! @name EVTERRDBG - DMA Request Error Register */ /*! @{ */ #define SDMAARM_EVTERRDBG_CHNERR_MASK (0xFFFFFFFFU) #define SDMAARM_EVTERRDBG_CHNERR_SHIFT (0U) #define SDMAARM_EVTERRDBG_CHNERR(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERRDBG_CHNERR_SHIFT)) & SDMAARM_EVTERRDBG_CHNERR_MASK) /*! @} */ /*! @name CONFIG - Configuration Register */ /*! @{ */ #define SDMAARM_CONFIG_CSM_MASK (0x3U) #define SDMAARM_CONFIG_CSM_SHIFT (0U) /*! CSM * 0b00..static * 0b01..dynamic low power * 0b10..dynamic with no loop * 0b11..dynamic */ #define SDMAARM_CONFIG_CSM(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_CSM_SHIFT)) & SDMAARM_CONFIG_CSM_MASK) #define SDMAARM_CONFIG_ACR_MASK (0x10U) #define SDMAARM_CONFIG_ACR_SHIFT (4U) /*! ACR * 0b0..Arm platform DMA interface frequency equals twice core frequency * 0b1..Arm platform DMA interface frequency equals core frequency */ #define SDMAARM_CONFIG_ACR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_ACR_SHIFT)) & SDMAARM_CONFIG_ACR_MASK) #define SDMAARM_CONFIG_RTDOBS_MASK (0x800U) #define SDMAARM_CONFIG_RTDOBS_SHIFT (11U) /*! RTDOBS * 0b0..RTD pins disabled * 0b1..RTD pins enabled */ #define SDMAARM_CONFIG_RTDOBS(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_RTDOBS_SHIFT)) & SDMAARM_CONFIG_RTDOBS_MASK) #define SDMAARM_CONFIG_DSPDMA_MASK (0x1000U) #define SDMAARM_CONFIG_DSPDMA_SHIFT (12U) /*! DSPDMA * 0b0..- Reset Value * 0b1..- Reserved */ #define SDMAARM_CONFIG_DSPDMA(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_DSPDMA_SHIFT)) & SDMAARM_CONFIG_DSPDMA_MASK) /*! @} */ /*! @name SDMA_LOCK - SDMA LOCK */ /*! @{ */ #define SDMAARM_SDMA_LOCK_LOCK_MASK (0x1U) #define SDMAARM_SDMA_LOCK_LOCK_SHIFT (0U) /*! LOCK * 0b0..LOCK disengaged. * 0b1..LOCK enabled. */ #define SDMAARM_SDMA_LOCK_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_LOCK_SHIFT)) & SDMAARM_SDMA_LOCK_LOCK_MASK) #define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK (0x2U) #define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT (1U) /*! SRESET_LOCK_CLR * 0b0..Software Reset does not clear the LOCK bit. * 0b1..Software Reset clears the LOCK bit. */ #define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT)) & SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK) /*! @} */ /*! @name ONCE_ENB - OnCE Enable */ /*! @{ */ #define SDMAARM_ONCE_ENB_ENB_MASK (0x1U) #define SDMAARM_ONCE_ENB_ENB_SHIFT (0U) #define SDMAARM_ONCE_ENB_ENB(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_ENB_ENB_SHIFT)) & SDMAARM_ONCE_ENB_ENB_MASK) /*! @} */ /*! @name ONCE_DATA - OnCE Data Register */ /*! @{ */ #define SDMAARM_ONCE_DATA_DATA_MASK (0xFFFFFFFFU) #define SDMAARM_ONCE_DATA_DATA_SHIFT (0U) #define SDMAARM_ONCE_DATA_DATA(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_DATA_DATA_SHIFT)) & SDMAARM_ONCE_DATA_DATA_MASK) /*! @} */ /*! @name ONCE_INSTR - OnCE Instruction Register */ /*! @{ */ #define SDMAARM_ONCE_INSTR_INSTR_MASK (0xFFFFU) #define SDMAARM_ONCE_INSTR_INSTR_SHIFT (0U) #define SDMAARM_ONCE_INSTR_INSTR(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_INSTR_INSTR_SHIFT)) & SDMAARM_ONCE_INSTR_INSTR_MASK) /*! @} */ /*! @name ONCE_STAT - OnCE Status Register */ /*! @{ */ #define SDMAARM_ONCE_STAT_ECDR_MASK (0x7U) #define SDMAARM_ONCE_STAT_ECDR_SHIFT (0U) /*! ECDR * 0b000..1 matched addra_cond * 0b001..1 matched addrb_cond * 0b010..1 matched data_cond */ #define SDMAARM_ONCE_STAT_ECDR(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ECDR_SHIFT)) & SDMAARM_ONCE_STAT_ECDR_MASK) #define SDMAARM_ONCE_STAT_MST_MASK (0x80U) #define SDMAARM_ONCE_STAT_MST_SHIFT (7U) /*! MST * 0b0..The JTAG interface controls the OnCE. * 0b1..The Arm platform peripheral interface controls the OnCE. */ #define SDMAARM_ONCE_STAT_MST(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_MST_SHIFT)) & SDMAARM_ONCE_STAT_MST_MASK) #define SDMAARM_ONCE_STAT_SWB_MASK (0x100U) #define SDMAARM_ONCE_STAT_SWB_SHIFT (8U) #define SDMAARM_ONCE_STAT_SWB(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_SWB_SHIFT)) & SDMAARM_ONCE_STAT_SWB_MASK) #define SDMAARM_ONCE_STAT_ODR_MASK (0x200U) #define SDMAARM_ONCE_STAT_ODR_SHIFT (9U) #define SDMAARM_ONCE_STAT_ODR(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ODR_SHIFT)) & SDMAARM_ONCE_STAT_ODR_MASK) #define SDMAARM_ONCE_STAT_EDR_MASK (0x400U) #define SDMAARM_ONCE_STAT_EDR_SHIFT (10U) #define SDMAARM_ONCE_STAT_EDR(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_EDR_SHIFT)) & SDMAARM_ONCE_STAT_EDR_MASK) #define SDMAARM_ONCE_STAT_RCV_MASK (0x800U) #define SDMAARM_ONCE_STAT_RCV_SHIFT (11U) #define SDMAARM_ONCE_STAT_RCV(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_RCV_SHIFT)) & SDMAARM_ONCE_STAT_RCV_MASK) #define SDMAARM_ONCE_STAT_PST_MASK (0xF000U) #define SDMAARM_ONCE_STAT_PST_SHIFT (12U) /*! PST * 0b0000..Program * 0b0001..Data * 0b0010..Change of Flow * 0b0011..Change of Flow in Loop * 0b0100..Debug * 0b0101..Functional Unit * 0b0110..Sleep * 0b0111..Save * 0b1000..Program in Sleep * 0b1001..Data in Sleep * 0b0010..Change of Flow in Sleep * 0b0011..Change Flow in Loop in Sleep * 0b1100..Debug in Sleep * 0b1101..Functional Unit in Sleep * 0b1110..Sleep after Reset * 0b1111..Restore */ #define SDMAARM_ONCE_STAT_PST(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_PST_SHIFT)) & SDMAARM_ONCE_STAT_PST_MASK) /*! @} */ /*! @name ONCE_CMD - OnCE Command Register */ /*! @{ */ #define SDMAARM_ONCE_CMD_CMD_MASK (0xFU) #define SDMAARM_ONCE_CMD_CMD_SHIFT (0U) /*! CMD * 0b0000..rstatus * 0b0001..dmov * 0b0010..exec_once * 0b0011..run_core * 0b0100..exec_core * 0b0101..debug_rqst * 0b0110..rbuffer */ #define SDMAARM_ONCE_CMD_CMD(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_CMD_CMD_SHIFT)) & SDMAARM_ONCE_CMD_CMD_MASK) /*! @} */ /*! @name ILLINSTADDR - Illegal Instruction Trap Address */ /*! @{ */ #define SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK (0x3FFFU) #define SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT (0U) #define SDMAARM_ILLINSTADDR_ILLINSTADDR(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT)) & SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK) /*! @} */ /*! @name CHN0ADDR - Channel 0 Boot Address */ /*! @{ */ #define SDMAARM_CHN0ADDR_CHN0ADDR_MASK (0x3FFFU) #define SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT (0U) #define SDMAARM_CHN0ADDR_CHN0ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT)) & SDMAARM_CHN0ADDR_CHN0ADDR_MASK) #define SDMAARM_CHN0ADDR_SMSZ_MASK (0x4000U) #define SDMAARM_CHN0ADDR_SMSZ_SHIFT (14U) /*! SMSZ * 0b0..24 words per context * 0b1..32 words per context */ #define SDMAARM_CHN0ADDR_SMSZ(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_SMSZ_SHIFT)) & SDMAARM_CHN0ADDR_SMSZ_MASK) /*! @} */ /*! @name EVT_MIRROR - DMA Requests */ /*! @{ */ #define SDMAARM_EVT_MIRROR_EVENTS_MASK (0xFFFFFFFFU) #define SDMAARM_EVT_MIRROR_EVENTS_SHIFT (0U) /*! EVENTS * 0b00000000000000000000000000000000..DMA request event not pending * 0b00000000000000000000000000000001..DMA request event pending */ #define SDMAARM_EVT_MIRROR_EVENTS(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR_EVENTS_MASK) /*! @} */ /*! @name EVT_MIRROR2 - DMA Requests 2 */ /*! @{ */ #define SDMAARM_EVT_MIRROR2_EVENTS_MASK (0xFFFFU) #define SDMAARM_EVT_MIRROR2_EVENTS_SHIFT (0U) /*! EVENTS * 0b0000000000000000..- DMA request event not pending */ #define SDMAARM_EVT_MIRROR2_EVENTS(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR2_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR2_EVENTS_MASK) /*! @} */ /*! @name XTRIG_CONF1 - Cross-Trigger Events Configuration Register 1 */ /*! @{ */ #define SDMAARM_XTRIG_CONF1_NUM0_MASK (0x3FU) #define SDMAARM_XTRIG_CONF1_NUM0_SHIFT (0U) #define SDMAARM_XTRIG_CONF1_NUM0(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM0_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM0_MASK) #define SDMAARM_XTRIG_CONF1_CNF0_MASK (0x40U) #define SDMAARM_XTRIG_CONF1_CNF0_SHIFT (6U) /*! CNF0 * 0b0..channel * 0b1..DMA request */ #define SDMAARM_XTRIG_CONF1_CNF0(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF0_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF0_MASK) #define SDMAARM_XTRIG_CONF1_NUM1_MASK (0x3F00U) #define SDMAARM_XTRIG_CONF1_NUM1_SHIFT (8U) #define SDMAARM_XTRIG_CONF1_NUM1(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM1_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM1_MASK) #define SDMAARM_XTRIG_CONF1_CNF1_MASK (0x4000U) #define SDMAARM_XTRIG_CONF1_CNF1_SHIFT (14U) /*! CNF1 * 0b0..channel * 0b1..DMA request */ #define SDMAARM_XTRIG_CONF1_CNF1(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF1_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF1_MASK) #define SDMAARM_XTRIG_CONF1_NUM2_MASK (0x3F0000U) #define SDMAARM_XTRIG_CONF1_NUM2_SHIFT (16U) #define SDMAARM_XTRIG_CONF1_NUM2(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM2_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM2_MASK) #define SDMAARM_XTRIG_CONF1_CNF2_MASK (0x400000U) #define SDMAARM_XTRIG_CONF1_CNF2_SHIFT (22U) /*! CNF2 * 0b0..channel * 0b1..DMA request */ #define SDMAARM_XTRIG_CONF1_CNF2(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF2_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF2_MASK) #define SDMAARM_XTRIG_CONF1_NUM3_MASK (0x3F000000U) #define SDMAARM_XTRIG_CONF1_NUM3_SHIFT (24U) #define SDMAARM_XTRIG_CONF1_NUM3(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM3_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM3_MASK) #define SDMAARM_XTRIG_CONF1_CNF3_MASK (0x40000000U) #define SDMAARM_XTRIG_CONF1_CNF3_SHIFT (30U) /*! CNF3 * 0b0..channel * 0b1..DMA request */ #define SDMAARM_XTRIG_CONF1_CNF3(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF3_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF3_MASK) /*! @} */ /*! @name XTRIG_CONF2 - Cross-Trigger Events Configuration Register 2 */ /*! @{ */ #define SDMAARM_XTRIG_CONF2_NUM4_MASK (0x3FU) #define SDMAARM_XTRIG_CONF2_NUM4_SHIFT (0U) #define SDMAARM_XTRIG_CONF2_NUM4(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM4_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM4_MASK) #define SDMAARM_XTRIG_CONF2_CNF4_MASK (0x40U) #define SDMAARM_XTRIG_CONF2_CNF4_SHIFT (6U) /*! CNF4 * 0b0..channel * 0b1..DMA request */ #define SDMAARM_XTRIG_CONF2_CNF4(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF4_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF4_MASK) #define SDMAARM_XTRIG_CONF2_NUM5_MASK (0x3F00U) #define SDMAARM_XTRIG_CONF2_NUM5_SHIFT (8U) #define SDMAARM_XTRIG_CONF2_NUM5(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM5_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM5_MASK) #define SDMAARM_XTRIG_CONF2_CNF5_MASK (0x4000U) #define SDMAARM_XTRIG_CONF2_CNF5_SHIFT (14U) /*! CNF5 * 0b0..channel * 0b1..DMA request */ #define SDMAARM_XTRIG_CONF2_CNF5(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF5_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF5_MASK) #define SDMAARM_XTRIG_CONF2_NUM6_MASK (0x3F0000U) #define SDMAARM_XTRIG_CONF2_NUM6_SHIFT (16U) #define SDMAARM_XTRIG_CONF2_NUM6(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM6_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM6_MASK) #define SDMAARM_XTRIG_CONF2_CNF6_MASK (0x400000U) #define SDMAARM_XTRIG_CONF2_CNF6_SHIFT (22U) /*! CNF6 * 0b0..channel * 0b1..DMA request */ #define SDMAARM_XTRIG_CONF2_CNF6(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF6_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF6_MASK) #define SDMAARM_XTRIG_CONF2_NUM7_MASK (0x3F000000U) #define SDMAARM_XTRIG_CONF2_NUM7_SHIFT (24U) #define SDMAARM_XTRIG_CONF2_NUM7(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM7_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM7_MASK) #define SDMAARM_XTRIG_CONF2_CNF7_MASK (0x40000000U) #define SDMAARM_XTRIG_CONF2_CNF7_SHIFT (30U) /*! CNF7 * 0b0..channel * 0b1..DMA request */ #define SDMAARM_XTRIG_CONF2_CNF7(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF7_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF7_MASK) /*! @} */ /*! @name SDMA_CHNPRI - Channel Priority Registers */ /*! @{ */ #define SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK (0x7U) #define SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT (0U) #define SDMAARM_SDMA_CHNPRI_CHNPRIn(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT)) & SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK) /*! @} */ /* The count of SDMAARM_SDMA_CHNPRI */ #define SDMAARM_SDMA_CHNPRI_COUNT (32U) /*! @name CHNENBL - Channel Enable RAM */ /*! @{ */ #define SDMAARM_CHNENBL_ENBLn_MASK (0xFFFFFFFFU) #define SDMAARM_CHNENBL_ENBLn_SHIFT (0U) #define SDMAARM_CHNENBL_ENBLn(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHNENBL_ENBLn_SHIFT)) & SDMAARM_CHNENBL_ENBLn_MASK) /*! @} */ /* The count of SDMAARM_CHNENBL */ #define SDMAARM_CHNENBL_COUNT (48U) /*! @name DONE0_CONFIG - SDMA DONE0 Configuration */ /*! @{ */ #define SDMAARM_DONE0_CONFIG_CH_SEL0_MASK (0x1FU) #define SDMAARM_DONE0_CONFIG_CH_SEL0_SHIFT (0U) #define SDMAARM_DONE0_CONFIG_CH_SEL0(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_CH_SEL0_SHIFT)) & SDMAARM_DONE0_CONFIG_CH_SEL0_MASK) #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS0_MASK (0x40U) #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS0_SHIFT (6U) /*! SW_DONE_DIS0 * 0b0..Enable * 0b1..Disable */ #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS0(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_SW_DONE_DIS0_SHIFT)) & SDMAARM_DONE0_CONFIG_SW_DONE_DIS0_MASK) #define SDMAARM_DONE0_CONFIG_DONE_SEL0_MASK (0x80U) #define SDMAARM_DONE0_CONFIG_DONE_SEL0_SHIFT (7U) /*! DONE_SEL0 * 0b0..HW * 0b1..SW */ #define SDMAARM_DONE0_CONFIG_DONE_SEL0(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_DONE_SEL0_SHIFT)) & SDMAARM_DONE0_CONFIG_DONE_SEL0_MASK) #define SDMAARM_DONE0_CONFIG_CH_SEL1_MASK (0x1F00U) #define SDMAARM_DONE0_CONFIG_CH_SEL1_SHIFT (8U) #define SDMAARM_DONE0_CONFIG_CH_SEL1(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_CH_SEL1_SHIFT)) & SDMAARM_DONE0_CONFIG_CH_SEL1_MASK) #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS1_MASK (0x4000U) #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS1_SHIFT (14U) /*! SW_DONE_DIS1 * 0b0..Enable * 0b1..Disable */ #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS1(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_SW_DONE_DIS1_SHIFT)) & SDMAARM_DONE0_CONFIG_SW_DONE_DIS1_MASK) #define SDMAARM_DONE0_CONFIG_DONE_SEL1_MASK (0x8000U) #define SDMAARM_DONE0_CONFIG_DONE_SEL1_SHIFT (15U) /*! DONE_SEL1 * 0b0..HW * 0b1..SW */ #define SDMAARM_DONE0_CONFIG_DONE_SEL1(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_DONE_SEL1_SHIFT)) & SDMAARM_DONE0_CONFIG_DONE_SEL1_MASK) #define SDMAARM_DONE0_CONFIG_CH_SEL2_MASK (0x1F0000U) #define SDMAARM_DONE0_CONFIG_CH_SEL2_SHIFT (16U) #define SDMAARM_DONE0_CONFIG_CH_SEL2(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_CH_SEL2_SHIFT)) & SDMAARM_DONE0_CONFIG_CH_SEL2_MASK) #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS2_MASK (0x400000U) #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS2_SHIFT (22U) /*! SW_DONE_DIS2 * 0b0..Enable * 0b1..Disable */ #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS2(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_SW_DONE_DIS2_SHIFT)) & SDMAARM_DONE0_CONFIG_SW_DONE_DIS2_MASK) #define SDMAARM_DONE0_CONFIG_DONE_SEL2_MASK (0x800000U) #define SDMAARM_DONE0_CONFIG_DONE_SEL2_SHIFT (23U) /*! DONE_SEL2 * 0b0..HW * 0b1..SW */ #define SDMAARM_DONE0_CONFIG_DONE_SEL2(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_DONE_SEL2_SHIFT)) & SDMAARM_DONE0_CONFIG_DONE_SEL2_MASK) #define SDMAARM_DONE0_CONFIG_CH_SEL3_MASK (0x1F000000U) #define SDMAARM_DONE0_CONFIG_CH_SEL3_SHIFT (24U) #define SDMAARM_DONE0_CONFIG_CH_SEL3(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_CH_SEL3_SHIFT)) & SDMAARM_DONE0_CONFIG_CH_SEL3_MASK) #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS3_MASK (0x40000000U) #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS3_SHIFT (30U) /*! SW_DONE_DIS3 * 0b0..Enable * 0b1..Disable */ #define SDMAARM_DONE0_CONFIG_SW_DONE_DIS3(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_SW_DONE_DIS3_SHIFT)) & SDMAARM_DONE0_CONFIG_SW_DONE_DIS3_MASK) #define SDMAARM_DONE0_CONFIG_DONE_SEL3_MASK (0x80000000U) #define SDMAARM_DONE0_CONFIG_DONE_SEL3_SHIFT (31U) /*! DONE_SEL3 * 0b0..HW * 0b1..SW */ #define SDMAARM_DONE0_CONFIG_DONE_SEL3(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_DONE_SEL3_SHIFT)) & SDMAARM_DONE0_CONFIG_DONE_SEL3_MASK) /*! @} */ /*! @name DONE1_CONFIG - SDMA DONE1 Configuration */ /*! @{ */ #define SDMAARM_DONE1_CONFIG_CH_SEL4_MASK (0x1FU) #define SDMAARM_DONE1_CONFIG_CH_SEL4_SHIFT (0U) #define SDMAARM_DONE1_CONFIG_CH_SEL4(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_CH_SEL4_SHIFT)) & SDMAARM_DONE1_CONFIG_CH_SEL4_MASK) #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS4_MASK (0x40U) #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS4_SHIFT (6U) /*! SW_DONE_DIS4 * 0b0..Enable * 0b1..Disable */ #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS4(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_SW_DONE_DIS4_SHIFT)) & SDMAARM_DONE1_CONFIG_SW_DONE_DIS4_MASK) #define SDMAARM_DONE1_CONFIG_DONE_SEL4_MASK (0x80U) #define SDMAARM_DONE1_CONFIG_DONE_SEL4_SHIFT (7U) /*! DONE_SEL4 * 0b0..HW * 0b1..SW */ #define SDMAARM_DONE1_CONFIG_DONE_SEL4(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_DONE_SEL4_SHIFT)) & SDMAARM_DONE1_CONFIG_DONE_SEL4_MASK) #define SDMAARM_DONE1_CONFIG_CH_SEL5_MASK (0x1F00U) #define SDMAARM_DONE1_CONFIG_CH_SEL5_SHIFT (8U) #define SDMAARM_DONE1_CONFIG_CH_SEL5(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_CH_SEL5_SHIFT)) & SDMAARM_DONE1_CONFIG_CH_SEL5_MASK) #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS5_MASK (0x4000U) #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS5_SHIFT (14U) /*! SW_DONE_DIS5 * 0b0..Enable * 0b1..Disable */ #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS5(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_SW_DONE_DIS5_SHIFT)) & SDMAARM_DONE1_CONFIG_SW_DONE_DIS5_MASK) #define SDMAARM_DONE1_CONFIG_DONE_SEL5_MASK (0x8000U) #define SDMAARM_DONE1_CONFIG_DONE_SEL5_SHIFT (15U) /*! DONE_SEL5 * 0b0..HW * 0b1..SW */ #define SDMAARM_DONE1_CONFIG_DONE_SEL5(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_DONE_SEL5_SHIFT)) & SDMAARM_DONE1_CONFIG_DONE_SEL5_MASK) #define SDMAARM_DONE1_CONFIG_CH_SEL6_MASK (0x1F0000U) #define SDMAARM_DONE1_CONFIG_CH_SEL6_SHIFT (16U) #define SDMAARM_DONE1_CONFIG_CH_SEL6(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_CH_SEL6_SHIFT)) & SDMAARM_DONE1_CONFIG_CH_SEL6_MASK) #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS6_MASK (0x400000U) #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS6_SHIFT (22U) /*! SW_DONE_DIS6 * 0b0..Enable * 0b1..Disable */ #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS6(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_SW_DONE_DIS6_SHIFT)) & SDMAARM_DONE1_CONFIG_SW_DONE_DIS6_MASK) #define SDMAARM_DONE1_CONFIG_DONE_SEL6_MASK (0x800000U) #define SDMAARM_DONE1_CONFIG_DONE_SEL6_SHIFT (23U) /*! DONE_SEL6 * 0b0..HW * 0b1..SW */ #define SDMAARM_DONE1_CONFIG_DONE_SEL6(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_DONE_SEL6_SHIFT)) & SDMAARM_DONE1_CONFIG_DONE_SEL6_MASK) #define SDMAARM_DONE1_CONFIG_CH_SEL7_MASK (0x1F000000U) #define SDMAARM_DONE1_CONFIG_CH_SEL7_SHIFT (24U) #define SDMAARM_DONE1_CONFIG_CH_SEL7(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_CH_SEL7_SHIFT)) & SDMAARM_DONE1_CONFIG_CH_SEL7_MASK) #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS7_MASK (0x40000000U) #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS7_SHIFT (30U) /*! SW_DONE_DIS7 * 0b0..Enable * 0b1..Disable */ #define SDMAARM_DONE1_CONFIG_SW_DONE_DIS7(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_SW_DONE_DIS7_SHIFT)) & SDMAARM_DONE1_CONFIG_SW_DONE_DIS7_MASK) #define SDMAARM_DONE1_CONFIG_DONE_SEL7_MASK (0x80000000U) #define SDMAARM_DONE1_CONFIG_DONE_SEL7_SHIFT (31U) /*! DONE_SEL7 * 0b0..HW * 0b1..SW */ #define SDMAARM_DONE1_CONFIG_DONE_SEL7(x) \ (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_DONE_SEL7_SHIFT)) & SDMAARM_DONE1_CONFIG_DONE_SEL7_MASK) /*! @} */ /*! * @} */ /* end of group SDMAARM_Register_Masks */ /* SDMAARM - Peripheral instance base addresses */ /** Peripheral SDMAARM1 base address */ #define SDMAARM1_BASE (0x30BD0000u) /** Peripheral SDMAARM1 base pointer */ #define SDMAARM1 ((SDMAARM_Type *)SDMAARM1_BASE) /** Peripheral SDMAARM2 base address */ #define SDMAARM2_BASE (0x302C0000u) /** Peripheral SDMAARM2 base pointer */ #define SDMAARM2 ((SDMAARM_Type *)SDMAARM2_BASE) /** Peripheral SDMAARM3 base address */ #define SDMAARM3_BASE (0x302B0000u) /** Peripheral SDMAARM3 base pointer */ #define SDMAARM3 ((SDMAARM_Type *)SDMAARM3_BASE) /** Array initializer of SDMAARM peripheral base addresses */ #define SDMAARM_BASE_ADDRS \ { \ SDMAARM1_BASE, SDMAARM2_BASE, SDMAARM3_BASE \ } /** Array initializer of SDMAARM peripheral base pointers */ #define SDMAARM_BASE_PTRS \ { \ SDMAARM1, SDMAARM2, SDMAARM3 \ } /** Interrupt vectors for the SDMAARM peripheral type */ #define SDMAARM_IRQS \ { \ SDMA1_IRQn, SDMA2_IRQn, SDMA3_IRQn \ } /*! * @} */ /* end of group SDMAARM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SEMA4 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SEMA4_Peripheral_Access_Layer SEMA4 Peripheral Access Layer * @{ */ /** SEMA4 - Register Layout Typedef */ typedef struct { __IO uint8_t Gate00; /**< Semaphores Gate 0 Register, offset: 0x0 */ __IO uint8_t Gate01; /**< Semaphores Gate 1 Register, offset: 0x1 */ __IO uint8_t Gate02; /**< Semaphores Gate 2 Register, offset: 0x2 */ __IO uint8_t Gate03; /**< Semaphores Gate 3 Register, offset: 0x3 */ __IO uint8_t Gate04; /**< Semaphores Gate 4 Register, offset: 0x4 */ __IO uint8_t Gate05; /**< Semaphores Gate 5 Register, offset: 0x5 */ __IO uint8_t Gate06; /**< Semaphores Gate 6 Register, offset: 0x6 */ __IO uint8_t Gate07; /**< Semaphores Gate 7 Register, offset: 0x7 */ __IO uint8_t Gate08; /**< Semaphores Gate 8 Register, offset: 0x8 */ __IO uint8_t Gate09; /**< Semaphores Gate 9 Register, offset: 0x9 */ __IO uint8_t Gate10; /**< Semaphores Gate 10 Register, offset: 0xA */ __IO uint8_t Gate11; /**< Semaphores Gate 11 Register, offset: 0xB */ __IO uint8_t Gate12; /**< Semaphores Gate 12 Register, offset: 0xC */ __IO uint8_t Gate13; /**< Semaphores Gate 13 Register, offset: 0xD */ __IO uint8_t Gate14; /**< Semaphores Gate 14 Register, offset: 0xE */ __IO uint8_t Gate15; /**< Semaphores Gate 15 Register, offset: 0xF */ uint8_t RESERVED_0[48]; struct { /* offset: 0x40, array step: 0x8 */ __IO uint16_t CPINE; /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */ uint8_t RESERVED_0[6]; } CPINE[2]; uint8_t RESERVED_1[48]; struct { /* offset: 0x80, array step: 0x8 */ __I uint16_t CPNTF; /**< Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8 */ uint8_t RESERVED_0[6]; } CPNTF[2]; uint8_t RESERVED_2[112]; __IO uint16_t RSTGT; /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */ uint8_t RESERVED_3[2]; __IO uint16_t RSTNTF; /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */ } SEMA4_Type; /* ---------------------------------------------------------------------------- -- SEMA4 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks * @{ */ /*! @name Gate00 - Semaphores Gate 0 Register */ /*! @{ */ #define SEMA4_Gate00_GTFSM_MASK (0x3U) #define SEMA4_Gate00_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b00..The gate is unlocked (free). * 0b01..The gate has been locked by processor 0. * 0b10..The gate has been locked by processor 1. * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no * operation" and do not affect the gate state machine. */ #define SEMA4_Gate00_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate00_GTFSM_SHIFT)) & SEMA4_Gate00_GTFSM_MASK) /*! @} */ /*! @name Gate01 - Semaphores Gate 1 Register */ /*! @{ */ #define SEMA4_Gate01_GTFSM_MASK (0x3U) #define SEMA4_Gate01_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b00..The gate is unlocked (free). * 0b01..The gate has been locked by processor 0. * 0b10..The gate has been locked by processor 1. * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no * operation" and do not affect the gate state machine. */ #define SEMA4_Gate01_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate01_GTFSM_SHIFT)) & SEMA4_Gate01_GTFSM_MASK) /*! @} */ /*! @name Gate02 - Semaphores Gate 2 Register */ /*! @{ */ #define SEMA4_Gate02_GTFSM_MASK (0x3U) #define SEMA4_Gate02_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b00..The gate is unlocked (free). * 0b01..The gate has been locked by processor 0. * 0b10..The gate has been locked by processor 1. * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no * operation" and do not affect the gate state machine. */ #define SEMA4_Gate02_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate02_GTFSM_SHIFT)) & SEMA4_Gate02_GTFSM_MASK) /*! @} */ /*! @name Gate03 - Semaphores Gate 3 Register */ /*! @{ */ #define SEMA4_Gate03_GTFSM_MASK (0x3U) #define SEMA4_Gate03_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b00..The gate is unlocked (free). * 0b01..The gate has been locked by processor 0. * 0b10..The gate has been locked by processor 1. * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no * operation" and do not affect the gate state machine. */ #define SEMA4_Gate03_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate03_GTFSM_SHIFT)) & SEMA4_Gate03_GTFSM_MASK) /*! @} */ /*! @name Gate04 - Semaphores Gate 4 Register */ /*! @{ */ #define SEMA4_Gate04_GTFSM_MASK (0x3U) #define SEMA4_Gate04_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b00..The gate is unlocked (free). * 0b01..The gate has been locked by processor 0. * 0b10..The gate has been locked by processor 1. * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no * operation" and do not affect the gate state machine. */ #define SEMA4_Gate04_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate04_GTFSM_SHIFT)) & SEMA4_Gate04_GTFSM_MASK) /*! @} */ /*! @name Gate05 - Semaphores Gate 5 Register */ /*! @{ */ #define SEMA4_Gate05_GTFSM_MASK (0x3U) #define SEMA4_Gate05_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b00..The gate is unlocked (free). * 0b01..The gate has been locked by processor 0. * 0b10..The gate has been locked by processor 1. * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no * operation" and do not affect the gate state machine. */ #define SEMA4_Gate05_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate05_GTFSM_SHIFT)) & SEMA4_Gate05_GTFSM_MASK) /*! @} */ /*! @name Gate06 - Semaphores Gate 6 Register */ /*! @{ */ #define SEMA4_Gate06_GTFSM_MASK (0x3U) #define SEMA4_Gate06_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b00..The gate is unlocked (free). * 0b01..The gate has been locked by processor 0. * 0b10..The gate has been locked by processor 1. * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no * operation" and do not affect the gate state machine. */ #define SEMA4_Gate06_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate06_GTFSM_SHIFT)) & SEMA4_Gate06_GTFSM_MASK) /*! @} */ /*! @name Gate07 - Semaphores Gate 7 Register */ /*! @{ */ #define SEMA4_Gate07_GTFSM_MASK (0x3U) #define SEMA4_Gate07_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b00..The gate is unlocked (free). * 0b01..The gate has been locked by processor 0. * 0b10..The gate has been locked by processor 1. * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no * operation" and do not affect the gate state machine. */ #define SEMA4_Gate07_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate07_GTFSM_SHIFT)) & SEMA4_Gate07_GTFSM_MASK) /*! @} */ /*! @name Gate08 - Semaphores Gate 8 Register */ /*! @{ */ #define SEMA4_Gate08_GTFSM_MASK (0x3U) #define SEMA4_Gate08_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b00..The gate is unlocked (free). * 0b01..The gate has been locked by processor 0. * 0b10..The gate has been locked by processor 1. * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no * operation" and do not affect the gate state machine. */ #define SEMA4_Gate08_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate08_GTFSM_SHIFT)) & SEMA4_Gate08_GTFSM_MASK) /*! @} */ /*! @name Gate09 - Semaphores Gate 9 Register */ /*! @{ */ #define SEMA4_Gate09_GTFSM_MASK (0x3U) #define SEMA4_Gate09_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b00..The gate is unlocked (free). * 0b01..The gate has been locked by processor 0. * 0b10..The gate has been locked by processor 1. * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no * operation" and do not affect the gate state machine. */ #define SEMA4_Gate09_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate09_GTFSM_SHIFT)) & SEMA4_Gate09_GTFSM_MASK) /*! @} */ /*! @name Gate10 - Semaphores Gate 10 Register */ /*! @{ */ #define SEMA4_Gate10_GTFSM_MASK (0x3U) #define SEMA4_Gate10_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b00..The gate is unlocked (free). * 0b01..The gate has been locked by processor 0. * 0b10..The gate has been locked by processor 1. * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no * operation" and do not affect the gate state machine. */ #define SEMA4_Gate10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate10_GTFSM_SHIFT)) & SEMA4_Gate10_GTFSM_MASK) /*! @} */ /*! @name Gate11 - Semaphores Gate 11 Register */ /*! @{ */ #define SEMA4_Gate11_GTFSM_MASK (0x3U) #define SEMA4_Gate11_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b00..The gate is unlocked (free). * 0b01..The gate has been locked by processor 0. * 0b10..The gate has been locked by processor 1. * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no * operation" and do not affect the gate state machine. */ #define SEMA4_Gate11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate11_GTFSM_SHIFT)) & SEMA4_Gate11_GTFSM_MASK) /*! @} */ /*! @name Gate12 - Semaphores Gate 12 Register */ /*! @{ */ #define SEMA4_Gate12_GTFSM_MASK (0x3U) #define SEMA4_Gate12_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b00..The gate is unlocked (free). * 0b01..The gate has been locked by processor 0. * 0b10..The gate has been locked by processor 1. * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no * operation" and do not affect the gate state machine. */ #define SEMA4_Gate12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate12_GTFSM_SHIFT)) & SEMA4_Gate12_GTFSM_MASK) /*! @} */ /*! @name Gate13 - Semaphores Gate 13 Register */ /*! @{ */ #define SEMA4_Gate13_GTFSM_MASK (0x3U) #define SEMA4_Gate13_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b00..The gate is unlocked (free). * 0b01..The gate has been locked by processor 0. * 0b10..The gate has been locked by processor 1. * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no * operation" and do not affect the gate state machine. */ #define SEMA4_Gate13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate13_GTFSM_SHIFT)) & SEMA4_Gate13_GTFSM_MASK) /*! @} */ /*! @name Gate14 - Semaphores Gate 14 Register */ /*! @{ */ #define SEMA4_Gate14_GTFSM_MASK (0x3U) #define SEMA4_Gate14_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b00..The gate is unlocked (free). * 0b01..The gate has been locked by processor 0. * 0b10..The gate has been locked by processor 1. * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no * operation" and do not affect the gate state machine. */ #define SEMA4_Gate14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate14_GTFSM_SHIFT)) & SEMA4_Gate14_GTFSM_MASK) /*! @} */ /*! @name Gate15 - Semaphores Gate 15 Register */ /*! @{ */ #define SEMA4_Gate15_GTFSM_MASK (0x3U) #define SEMA4_Gate15_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. * 0b00..The gate is unlocked (free). * 0b01..The gate has been locked by processor 0. * 0b10..The gate has been locked by processor 1. * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no * operation" and do not affect the gate state machine. */ #define SEMA4_Gate15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate15_GTFSM_SHIFT)) & SEMA4_Gate15_GTFSM_MASK) /*! @} */ /*! @name CPINE - Semaphores Processor n IRQ Notification Enable */ /*! @{ */ #define SEMA4_CPINE_INE7_MASK (0x1U) #define SEMA4_CPINE_INE7_SHIFT (0U) /*! INE7 - Interrupt Request Notification Enable 7. This field is a bitmap to enable the generation * of an interrupt notification from a failed attempt to lock gate 7. * 0b0..The generation of the notification interrupt is disabled. * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_SHIFT)) & SEMA4_CPINE_INE7_MASK) #define SEMA4_CPINE_INE6_MASK (0x2U) #define SEMA4_CPINE_INE6_SHIFT (1U) /*! INE6 - Interrupt Request Notification Enable 6. This field is a bitmap to enable the generation * of an interrupt notification from a failed attempt to lock gate 6. * 0b0..The generation of the notification interrupt is disabled. * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_SHIFT)) & SEMA4_CPINE_INE6_MASK) #define SEMA4_CPINE_INE5_MASK (0x4U) #define SEMA4_CPINE_INE5_SHIFT (2U) /*! INE5 - Interrupt Request Notification Enable 5. This field is a bitmap to enable the generation * of an interrupt notification from a failed attempt to lock gate 5. * 0b0..The generation of the notification interrupt is disabled. * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_SHIFT)) & SEMA4_CPINE_INE5_MASK) #define SEMA4_CPINE_INE4_MASK (0x8U) #define SEMA4_CPINE_INE4_SHIFT (3U) /*! INE4 - Interrupt Request Notification Enable 4. This field is a bitmap to enable the generation * of an interrupt notification from a failed attempt to lock gate 4. * 0b0..The generation of the notification interrupt is disabled. * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_SHIFT)) & SEMA4_CPINE_INE4_MASK) #define SEMA4_CPINE_INE3_MASK (0x10U) #define SEMA4_CPINE_INE3_SHIFT (4U) /*! INE3 * 0b0..The generation of the notification interrupt is disabled. * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_SHIFT)) & SEMA4_CPINE_INE3_MASK) #define SEMA4_CPINE_INE2_MASK (0x20U) #define SEMA4_CPINE_INE2_SHIFT (5U) /*! INE2 * 0b0..The generation of the notification interrupt is disabled. * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_SHIFT)) & SEMA4_CPINE_INE2_MASK) #define SEMA4_CPINE_INE1_MASK (0x40U) #define SEMA4_CPINE_INE1_SHIFT (6U) /*! INE1 * 0b0..The generation of the notification interrupt is disabled. * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_SHIFT)) & SEMA4_CPINE_INE1_MASK) #define SEMA4_CPINE_INE0_MASK (0x80U) #define SEMA4_CPINE_INE0_SHIFT (7U) /*! INE0 * 0b0..The generation of the notification interrupt is disabled. * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_SHIFT)) & SEMA4_CPINE_INE0_MASK) #define SEMA4_CPINE_INE15_MASK (0x100U) #define SEMA4_CPINE_INE15_SHIFT (8U) /*! INE15 - Interrupt Request Notification Enable 15. This field is a bitmap to enable the * generation of an interrupt notification from a failed attempt to lock gate 15. * 0b0..The generation of the notification interrupt is disabled. * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_SHIFT)) & SEMA4_CPINE_INE15_MASK) #define SEMA4_CPINE_INE14_MASK (0x200U) #define SEMA4_CPINE_INE14_SHIFT (9U) /*! INE14 - Interrupt Request Notification Enable 14. This field is a bitmap to enable the * generation of an interrupt notification from a failed attempt to lock gate 14. * 0b0..The generation of the notification interrupt is disabled. * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_SHIFT)) & SEMA4_CPINE_INE14_MASK) #define SEMA4_CPINE_INE13_MASK (0x400U) #define SEMA4_CPINE_INE13_SHIFT (10U) /*! INE13 - Interrupt Request Notification Enable 13. This field is a bitmap to enable the * generation of an interrupt notification from a failed attempt to lock gate 13. * 0b0..The generation of the notification interrupt is disabled. * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_SHIFT)) & SEMA4_CPINE_INE13_MASK) #define SEMA4_CPINE_INE12_MASK (0x800U) #define SEMA4_CPINE_INE12_SHIFT (11U) /*! INE12 - Interrupt Request Notification Enable 12. This field is a bitmap to enable the * generation of an interrupt notification from a failed attempt to lock gate 12. * 0b0..The generation of the notification interrupt is disabled. * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_SHIFT)) & SEMA4_CPINE_INE12_MASK) #define SEMA4_CPINE_INE11_MASK (0x1000U) #define SEMA4_CPINE_INE11_SHIFT (12U) /*! INE11 - Interrupt Request Notification Enable 11. This field is a bitmap to enable the * generation of an interrupt notification from a failed attempt to lock gate 11. * 0b0..The generation of the notification interrupt is disabled. * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_SHIFT)) & SEMA4_CPINE_INE11_MASK) #define SEMA4_CPINE_INE10_MASK (0x2000U) #define SEMA4_CPINE_INE10_SHIFT (13U) /*! INE10 - Interrupt Request Notification Enable 10. This field is a bitmap to enable the * generation of an interrupt notification from a failed attempt to lock gate 10. * 0b0..The generation of the notification interrupt is disabled. * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_SHIFT)) & SEMA4_CPINE_INE10_MASK) #define SEMA4_CPINE_INE9_MASK (0x4000U) #define SEMA4_CPINE_INE9_SHIFT (14U) /*! INE9 - Interrupt Request Notification Enable 9. This field is a bitmap to enable the generation * of an interrupt notification from a failed attempt to lock gate 9. * 0b0..The generation of the notification interrupt is disabled. * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_SHIFT)) & SEMA4_CPINE_INE9_MASK) #define SEMA4_CPINE_INE8_MASK (0x8000U) #define SEMA4_CPINE_INE8_SHIFT (15U) /*! INE8 - Interrupt Request Notification Enable 8. This field is a bitmap to enable the generation * of an interrupt notification from a failed attempt to lock gate 8. * 0b0..The generation of the notification interrupt is disabled. * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_SHIFT)) & SEMA4_CPINE_INE8_MASK) /*! @} */ /* The count of SEMA4_CPINE */ #define SEMA4_CPINE_COUNT (2U) /*! @name CPNTF - Semaphores Processor n IRQ Notification */ /*! @{ */ #define SEMA4_CPNTF_GN7_MASK (0x1U) #define SEMA4_CPNTF_GN7_SHIFT (0U) #define SEMA4_CPNTF_GN7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN7_SHIFT)) & SEMA4_CPNTF_GN7_MASK) #define SEMA4_CPNTF_GN6_MASK (0x2U) #define SEMA4_CPNTF_GN6_SHIFT (1U) #define SEMA4_CPNTF_GN6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN6_SHIFT)) & SEMA4_CPNTF_GN6_MASK) #define SEMA4_CPNTF_GN5_MASK (0x4U) #define SEMA4_CPNTF_GN5_SHIFT (2U) #define SEMA4_CPNTF_GN5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN5_SHIFT)) & SEMA4_CPNTF_GN5_MASK) #define SEMA4_CPNTF_GN4_MASK (0x8U) #define SEMA4_CPNTF_GN4_SHIFT (3U) #define SEMA4_CPNTF_GN4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN4_SHIFT)) & SEMA4_CPNTF_GN4_MASK) #define SEMA4_CPNTF_GN3_MASK (0x10U) #define SEMA4_CPNTF_GN3_SHIFT (4U) #define SEMA4_CPNTF_GN3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN3_SHIFT)) & SEMA4_CPNTF_GN3_MASK) #define SEMA4_CPNTF_GN2_MASK (0x20U) #define SEMA4_CPNTF_GN2_SHIFT (5U) #define SEMA4_CPNTF_GN2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN2_SHIFT)) & SEMA4_CPNTF_GN2_MASK) #define SEMA4_CPNTF_GN1_MASK (0x40U) #define SEMA4_CPNTF_GN1_SHIFT (6U) #define SEMA4_CPNTF_GN1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN1_SHIFT)) & SEMA4_CPNTF_GN1_MASK) #define SEMA4_CPNTF_GN0_MASK (0x80U) #define SEMA4_CPNTF_GN0_SHIFT (7U) #define SEMA4_CPNTF_GN0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN0_SHIFT)) & SEMA4_CPNTF_GN0_MASK) #define SEMA4_CPNTF_GN15_MASK (0x100U) #define SEMA4_CPNTF_GN15_SHIFT (8U) #define SEMA4_CPNTF_GN15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN15_SHIFT)) & SEMA4_CPNTF_GN15_MASK) #define SEMA4_CPNTF_GN14_MASK (0x200U) #define SEMA4_CPNTF_GN14_SHIFT (9U) #define SEMA4_CPNTF_GN14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN14_SHIFT)) & SEMA4_CPNTF_GN14_MASK) #define SEMA4_CPNTF_GN13_MASK (0x400U) #define SEMA4_CPNTF_GN13_SHIFT (10U) #define SEMA4_CPNTF_GN13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN13_SHIFT)) & SEMA4_CPNTF_GN13_MASK) #define SEMA4_CPNTF_GN12_MASK (0x800U) #define SEMA4_CPNTF_GN12_SHIFT (11U) #define SEMA4_CPNTF_GN12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN12_SHIFT)) & SEMA4_CPNTF_GN12_MASK) #define SEMA4_CPNTF_GN11_MASK (0x1000U) #define SEMA4_CPNTF_GN11_SHIFT (12U) #define SEMA4_CPNTF_GN11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN11_SHIFT)) & SEMA4_CPNTF_GN11_MASK) #define SEMA4_CPNTF_GN10_MASK (0x2000U) #define SEMA4_CPNTF_GN10_SHIFT (13U) #define SEMA4_CPNTF_GN10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN10_SHIFT)) & SEMA4_CPNTF_GN10_MASK) #define SEMA4_CPNTF_GN9_MASK (0x4000U) #define SEMA4_CPNTF_GN9_SHIFT (14U) #define SEMA4_CPNTF_GN9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN9_SHIFT)) & SEMA4_CPNTF_GN9_MASK) #define SEMA4_CPNTF_GN8_MASK (0x8000U) #define SEMA4_CPNTF_GN8_SHIFT (15U) #define SEMA4_CPNTF_GN8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN8_SHIFT)) & SEMA4_CPNTF_GN8_MASK) /*! @} */ /* The count of SEMA4_CPNTF */ #define SEMA4_CPNTF_COUNT (2U) /*! @name RSTGT - Semaphores (Secure) Reset Gate n */ /*! @{ */ #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK (0xFFU) #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT (0U) #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x) \ (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT)) & SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK) #define SEMA4_RSTGT_RSTGTN_MASK (0xFF00U) #define SEMA4_RSTGT_RSTGTN_SHIFT (8U) #define SEMA4_RSTGT_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGTN_SHIFT)) & SEMA4_RSTGT_RSTGTN_MASK) /*! @} */ /*! @name RSTNTF - Semaphores (Secure) Reset IRQ Notification */ /*! @{ */ #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK (0xFFU) #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT (0U) #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x) \ (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT)) & SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK) #define SEMA4_RSTNTF_RSTNTN_MASK (0xFF00U) #define SEMA4_RSTNTF_RSTNTN_SHIFT (8U) #define SEMA4_RSTNTF_RSTNTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNTN_SHIFT)) & SEMA4_RSTNTF_RSTNTN_MASK) /*! @} */ /*! * @} */ /* end of group SEMA4_Register_Masks */ /* SEMA4 - Peripheral instance base addresses */ /** Peripheral SEMA4 base address */ #define SEMA4_BASE (0x30AC0000u) /** Peripheral SEMA4 base pointer */ #define SEMA4 ((SEMA4_Type *)SEMA4_BASE) /** Array initializer of SEMA4 peripheral base addresses */ #define SEMA4_BASE_ADDRS \ { \ SEMA4_BASE \ } /** Array initializer of SEMA4 peripheral base pointers */ #define SEMA4_BASE_PTRS \ { \ SEMA4 \ } /*! * @} */ /* end of group SEMA4_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SNVS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer * @{ */ /** SNVS - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */ __IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */ uint8_t RESERVED_1[8]; __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ uint8_t RESERVED_2[12]; __IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */ __IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */ __IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */ __IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */ __IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */ __IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */ uint8_t RESERVED_3[16]; __IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */ uint8_t RESERVED_4[12]; __IO uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */ __IO uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */ __IO uint32_t LPPGDR; /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */ __IO uint32_t LPGPR0_LEGACY_ALIAS; /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */ uint8_t RESERVED_5[36]; __IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */ uint8_t RESERVED_6[96]; __IO uint32_t LPGPR[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_7[2792]; __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ } SNVS_Type; /* ---------------------------------------------------------------------------- -- SNVS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SNVS_Register_Masks SNVS Register Masks * @{ */ /*! @name HPCOMR - SNVS_HP Command Register */ /*! @{ */ #define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) #define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) #define SNVS_HPCOMR_NPSWA_EN(x) \ (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) /*! @} */ /*! @name HPCR - SNVS_HP Control Register */ /*! @{ */ #define SNVS_HPCR_RTC_EN_MASK (0x1U) #define SNVS_HPCR_RTC_EN_SHIFT (0U) /*! RTC_EN * 0b0..RTC is disabled * 0b1..RTC is enabled */ #define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) #define SNVS_HPCR_HPTA_EN_MASK (0x2U) #define SNVS_HPCR_HPTA_EN_SHIFT (1U) /*! HPTA_EN * 0b0..HP Time Alarm Interrupt is disabled * 0b1..HP Time Alarm Interrupt is enabled */ #define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) #define SNVS_HPCR_HPCALB_EN_MASK (0x100U) #define SNVS_HPCR_HPCALB_EN_SHIFT (8U) /*! HPCALB_EN * 0b0..HP Timer calibration disabled * 0b1..HP Timer calibration enabled */ #define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) #define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) #define SNVS_HPCR_HPCALB_VAL_SHIFT (10U) /*! HPCALB_VAL * 0b00000..+0 counts per each 32768 ticks of the counter * 0b00001..+1 counts per each 32768 ticks of the counter * 0b00010..+2 counts per each 32768 ticks of the counter * 0b01111..+15 counts per each 32768 ticks of the counter * 0b10000..-16 counts per each 32768 ticks of the counter * 0b10001..-15 counts per each 32768 ticks of the counter * 0b11110..-2 counts per each 32768 ticks of the counter * 0b11111..-1 counts per each 32768 ticks of the counter */ #define SNVS_HPCR_HPCALB_VAL(x) \ (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) /*! @} */ /*! @name HPSR - SNVS_HP Status Register */ /*! @{ */ #define SNVS_HPSR_HPTA_MASK (0x1U) #define SNVS_HPSR_HPTA_SHIFT (0U) /*! HPTA * 0b0..No time alarm interrupt occurred. * 0b1..A time alarm interrupt occurred. */ #define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK) #define SNVS_HPSR_LPDIS_MASK (0x10U) #define SNVS_HPSR_LPDIS_SHIFT (4U) #define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK) /*! @} */ /*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */ /*! @{ */ #define SNVS_HPRTCMR_RTC_MASK (0x7FFFU) #define SNVS_HPRTCMR_RTC_SHIFT (0U) #define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) /*! @} */ /*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */ /*! @{ */ #define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) #define SNVS_HPRTCLR_RTC_SHIFT (0U) #define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) /*! @} */ /*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ /*! @{ */ #define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU) #define SNVS_HPTAMR_HPTA_MS_SHIFT (0U) #define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK) /*! @} */ /*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ /*! @{ */ #define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU) #define SNVS_HPTALR_HPTA_LS_SHIFT (0U) #define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK) /*! @} */ /*! @name LPLR - SNVS_LP Lock Register */ /*! @{ */ #define SNVS_LPLR_MC_HL_MASK (0x10U) #define SNVS_LPLR_MC_HL_SHIFT (4U) /*! MC_HL * 0b0..Write access (increment) is allowed. * 0b1..Write access (increment) is not allowed. */ #define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) #define SNVS_LPLR_GPR_HL_MASK (0x20U) #define SNVS_LPLR_GPR_HL_SHIFT (5U) /*! GPR_HL * 0b0..Write access is allowed. * 0b1..Write access is not allowed. */ #define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) /*! @} */ /*! @name LPCR - SNVS_LP Control Register */ /*! @{ */ #define SNVS_LPCR_MC_ENV_MASK (0x4U) #define SNVS_LPCR_MC_ENV_SHIFT (2U) /*! MC_ENV * 0b0..MC is disabled or invalid. * 0b1..MC is enabled and valid. */ #define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) /*! @} */ /*! @name LPSR - SNVS_LP Status Register */ /*! @{ */ #define SNVS_LPSR_MCR_MASK (0x4U) #define SNVS_LPSR_MCR_SHIFT (2U) /*! MCR * 0b0..MC has not reached its maximum value. * 0b1..MC has reached its maximum value. */ #define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) /*! @} */ /*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ /*! @{ */ #define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) #define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) #define SNVS_LPSMCMR_MON_COUNTER(x) \ (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) #define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) #define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) #define SNVS_LPSMCMR_MC_ERA_BITS(x) \ (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) /*! @} */ /*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ /*! @{ */ #define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) #define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) #define SNVS_LPSMCLR_MON_COUNTER(x) \ (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) /*! @} */ /*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */ /*! @{ */ #define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU) #define SNVS_LPPGDR_PGD_SHIFT (0U) #define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK) /*! @} */ /*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */ /*! @{ */ #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU) #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U) #define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) \ (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK) /*! @} */ /*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */ /*! @{ */ #define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU) #define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U) #define SNVS_LPGPR_ALIAS_GPR(x) \ (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK) /*! @} */ /* The count of SNVS_LPGPR_ALIAS */ #define SNVS_LPGPR_ALIAS_COUNT (4U) /*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 3 */ /*! @{ */ #define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) #define SNVS_LPGPR_GPR_SHIFT (0U) #define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) /*! @} */ /* The count of SNVS_LPGPR */ #define SNVS_LPGPR_COUNT (4U) /*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ /*! @{ */ #define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) #define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) #define SNVS_HPVIDR1_MINOR_REV(x) \ (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) #define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U) #define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U) #define SNVS_HPVIDR1_MAJOR_REV(x) \ (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK) #define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) #define SNVS_HPVIDR1_IP_ID_SHIFT (16U) #define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) /*! @} */ /*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ /*! @{ */ #define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) #define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) #define SNVS_HPVIDR2_CONFIG_OPT(x) \ (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) #define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U) #define SNVS_HPVIDR2_ECO_REV_SHIFT (8U) #define SNVS_HPVIDR2_ECO_REV(x) \ (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK) #define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U) #define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U) #define SNVS_HPVIDR2_INTG_OPT(x) \ (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK) #define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) #define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) #define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) /*! @} */ /*! * @} */ /* end of group SNVS_Register_Masks */ /* SNVS - Peripheral instance base addresses */ /** Peripheral SNVS base address */ #define SNVS_BASE (0x30370000u) /** Peripheral SNVS base pointer */ #define SNVS ((SNVS_Type *)SNVS_BASE) /** Array initializer of SNVS peripheral base addresses */ #define SNVS_BASE_ADDRS \ { \ SNVS_BASE \ } /** Array initializer of SNVS peripheral base pointers */ #define SNVS_BASE_PTRS \ { \ SNVS \ } /*! * @} */ /* end of group SNVS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SPBA Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SPBA_Peripheral_Access_Layer SPBA Peripheral Access Layer * @{ */ /** SPBA - Register Layout Typedef */ typedef struct { __IO uint32_t PRR[32]; /**< Peripheral Rights Register, array offset: 0x0, array step: 0x4 */ } SPBA_Type; /* ---------------------------------------------------------------------------- -- SPBA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SPBA_Register_Masks SPBA Register Masks * @{ */ /*! @name PRR - Peripheral Rights Register */ /*! @{ */ #define SPBA_PRR_RARA_MASK (0x1U) #define SPBA_PRR_RARA_SHIFT (0U) /*! RARA * 0b0..Access to peripheral is not allowed. * 0b1..Access to peripheral is granted. */ #define SPBA_PRR_RARA(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARA_SHIFT)) & SPBA_PRR_RARA_MASK) #define SPBA_PRR_RARB_MASK (0x2U) #define SPBA_PRR_RARB_SHIFT (1U) /*! RARB * 0b0..Access to peripheral is not allowed. * 0b1..Access to peripheral is granted. */ #define SPBA_PRR_RARB(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARB_SHIFT)) & SPBA_PRR_RARB_MASK) #define SPBA_PRR_RARC_MASK (0x4U) #define SPBA_PRR_RARC_SHIFT (2U) /*! RARC * 0b0..Access to peripheral is not allowed. * 0b1..Access to peripheral is granted. */ #define SPBA_PRR_RARC(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARC_SHIFT)) & SPBA_PRR_RARC_MASK) #define SPBA_PRR_ROI_MASK (0x30000U) #define SPBA_PRR_ROI_SHIFT (16U) /*! ROI * 0b00..Unowned resource. * 0b01..The resource is owned by master A port. * 0b10..The resource is owned by master B port. * 0b11..The resource is owned by master C port. */ #define SPBA_PRR_ROI(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_ROI_SHIFT)) & SPBA_PRR_ROI_MASK) #define SPBA_PRR_RMO_MASK (0xC0000000U) #define SPBA_PRR_RMO_SHIFT (30U) /*! RMO * 0b00..The resource is unowned. * 0b01..Reserved. * 0b10..The resource is owned by another master. * 0b11..The resource is owned by the requesting master. */ #define SPBA_PRR_RMO(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RMO_SHIFT)) & SPBA_PRR_RMO_MASK) /*! @} */ /* The count of SPBA_PRR */ #define SPBA_PRR_COUNT (32U) /*! * @} */ /* end of group SPBA_Register_Masks */ /* SPBA - Peripheral instance base addresses */ /** Peripheral SPBA1 base address */ #define SPBA1_BASE (0x308F0000u) /** Peripheral SPBA1 base pointer */ #define SPBA1 ((SPBA_Type *)SPBA1_BASE) /** Peripheral SPBA2 base address */ #define SPBA2_BASE (0x300F0000u) /** Peripheral SPBA2 base pointer */ #define SPBA2 ((SPBA_Type *)SPBA2_BASE) /** Array initializer of SPBA peripheral base addresses */ #define SPBA_BASE_ADDRS \ { \ SPBA1_BASE, SPBA2_BASE \ } /** Array initializer of SPBA peripheral base pointers */ #define SPBA_BASE_PTRS \ { \ SPBA1, SPBA2 \ } /*! * @} */ /* end of group SPBA_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SPDIF Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer * @{ */ /** SPDIF - Register Layout Typedef */ typedef struct { __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ __IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */ __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ __IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */ union { /* offset: 0x10 */ __O uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */ __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ }; __I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */ __I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */ __I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */ __I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */ __I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */ __I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */ __O uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */ __O uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */ __IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */ __IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */ uint8_t RESERVED_0[8]; __I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */ uint8_t RESERVED_1[8]; __IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */ } SPDIF_Type; /* ---------------------------------------------------------------------------- -- SPDIF Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SPDIF_Register_Masks SPDIF Register Masks * @{ */ /*! @name SCR - SPDIF Configuration Register */ /*! @{ */ #define SPDIF_SCR_USrc_Sel_MASK (0x3U) #define SPDIF_SCR_USrc_Sel_SHIFT (0U) /*! USrc_Sel - USrc_Sel * 0b00..No embedded U channel * 0b01..U channel from SPDIF receive block (CD mode) * 0b10..Reserved * 0b11..U channel from on chip transmitter */ #define SPDIF_SCR_USrc_Sel(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USrc_Sel_SHIFT)) & SPDIF_SCR_USrc_Sel_MASK) #define SPDIF_SCR_TxSel_MASK (0x1CU) #define SPDIF_SCR_TxSel_SHIFT (2U) /*! TxSel - TxSel * 0b000..Off and output 0 * 0b001..Feed-through SPDIFIN * 0b101..Tx Normal operation */ #define SPDIF_SCR_TxSel(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TxSel_SHIFT)) & SPDIF_SCR_TxSel_MASK) #define SPDIF_SCR_ValCtrl_MASK (0x20U) #define SPDIF_SCR_ValCtrl_SHIFT (5U) /*! ValCtrl - ValCtrl * 0b0..Outgoing Validity always set * 0b1..Outgoing Validity always clear */ #define SPDIF_SCR_ValCtrl(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_ValCtrl_SHIFT)) & SPDIF_SCR_ValCtrl_MASK) #define SPDIF_SCR_DMA_TX_En_MASK (0x100U) #define SPDIF_SCR_DMA_TX_En_SHIFT (8U) #define SPDIF_SCR_DMA_TX_En(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_En_SHIFT)) & SPDIF_SCR_DMA_TX_En_MASK) #define SPDIF_SCR_DMA_Rx_En_MASK (0x200U) #define SPDIF_SCR_DMA_Rx_En_SHIFT (9U) #define SPDIF_SCR_DMA_Rx_En(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_Rx_En_SHIFT)) & SPDIF_SCR_DMA_Rx_En_MASK) #define SPDIF_SCR_TxFIFO_Ctrl_MASK (0xC00U) #define SPDIF_SCR_TxFIFO_Ctrl_SHIFT (10U) /*! TxFIFO_Ctrl - TxFIFO_Ctrl * 0b00..Send out digital zero on SPDIF Tx * 0b01..Tx Normal operation * 0b10..Reset to 1 sample remaining * 0b11..Reserved */ #define SPDIF_SCR_TxFIFO_Ctrl(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TxFIFO_Ctrl_SHIFT)) & SPDIF_SCR_TxFIFO_Ctrl_MASK) #define SPDIF_SCR_soft_reset_MASK (0x1000U) #define SPDIF_SCR_soft_reset_SHIFT (12U) #define SPDIF_SCR_soft_reset(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_soft_reset_SHIFT)) & SPDIF_SCR_soft_reset_MASK) #define SPDIF_SCR_LOW_POWER_MASK (0x2000U) #define SPDIF_SCR_LOW_POWER_SHIFT (13U) #define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) #define SPDIF_SCR_RAW_CAPTURE_MODE_MASK (0x4000U) #define SPDIF_SCR_RAW_CAPTURE_MODE_SHIFT (14U) #define SPDIF_SCR_RAW_CAPTURE_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RAW_CAPTURE_MODE_SHIFT)) & SPDIF_SCR_RAW_CAPTURE_MODE_MASK) #define SPDIF_SCR_TxFIFOEmpty_Sel_MASK (0x18000U) #define SPDIF_SCR_TxFIFOEmpty_Sel_SHIFT (15U) /*! TxFIFOEmpty_Sel - TxFIFOEmpty_Sel * 0b00..Empty interrupt if 0 sample in Tx left and right FIFOs * 0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs * 0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs * 0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs */ #define SPDIF_SCR_TxFIFOEmpty_Sel(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TxFIFOEmpty_Sel_SHIFT)) & SPDIF_SCR_TxFIFOEmpty_Sel_MASK) #define SPDIF_SCR_TxAutoSync_MASK (0x20000U) #define SPDIF_SCR_TxAutoSync_SHIFT (17U) /*! TxAutoSync - TxAutoSync * 0b0..Tx FIFO auto sync off * 0b1..Tx FIFO auto sync on */ #define SPDIF_SCR_TxAutoSync(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TxAutoSync_SHIFT)) & SPDIF_SCR_TxAutoSync_MASK) #define SPDIF_SCR_RxAutoSync_MASK (0x40000U) #define SPDIF_SCR_RxAutoSync_SHIFT (18U) /*! RxAutoSync - RxAutoSync * 0b0..Rx FIFO auto sync off * 0b1..RxFIFO auto sync on */ #define SPDIF_SCR_RxAutoSync(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RxAutoSync_SHIFT)) & SPDIF_SCR_RxAutoSync_MASK) #define SPDIF_SCR_RxFIFOFull_Sel_MASK (0x180000U) #define SPDIF_SCR_RxFIFOFull_Sel_SHIFT (19U) /*! RxFIFOFull_Sel - RxFIFOFull_Sel * 0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs * 0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs * 0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs * 0b11..Full interrupt if at least 16 sample in Rx left and right FIFO */ #define SPDIF_SCR_RxFIFOFull_Sel(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RxFIFOFull_Sel_SHIFT)) & SPDIF_SCR_RxFIFOFull_Sel_MASK) #define SPDIF_SCR_RxFIFO_Rst_MASK (0x200000U) #define SPDIF_SCR_RxFIFO_Rst_SHIFT (21U) /*! RxFIFO_Rst - RxFIFO_Rst * 0b0..Normal operation * 0b1..Reset register to 1 sample remaining */ #define SPDIF_SCR_RxFIFO_Rst(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RxFIFO_Rst_SHIFT)) & SPDIF_SCR_RxFIFO_Rst_MASK) #define SPDIF_SCR_RxFIFO_Off_On_MASK (0x400000U) #define SPDIF_SCR_RxFIFO_Off_On_SHIFT (22U) /*! RxFIFO_Off_On - RxFIFO_Off_On * 0b0..SPDIF Rx FIFO is on * 0b1..SPDIF Rx FIFO is off. Does not accept data from interface */ #define SPDIF_SCR_RxFIFO_Off_On(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RxFIFO_Off_On_SHIFT)) & SPDIF_SCR_RxFIFO_Off_On_MASK) #define SPDIF_SCR_RxFIFO_Ctrl_MASK (0x800000U) #define SPDIF_SCR_RxFIFO_Ctrl_SHIFT (23U) /*! RxFIFO_Ctrl - RxFIFO_Ctrl * 0b0..Normal operation * 0b1..Always read zero from Rx data register */ #define SPDIF_SCR_RxFIFO_Ctrl(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RxFIFO_Ctrl_SHIFT)) & SPDIF_SCR_RxFIFO_Ctrl_MASK) /*! @} */ /*! @name SRCD - CDText Control Register */ /*! @{ */ #define SPDIF_SRCD_USyncMode_MASK (0x2U) #define SPDIF_SRCD_USyncMode_SHIFT (1U) /*! USyncMode - USyncMode * 0b0..Non-CD data * 0b1..CD user channel subcode */ #define SPDIF_SRCD_USyncMode(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USyncMode_SHIFT)) & SPDIF_SRCD_USyncMode_MASK) /*! @} */ /*! @name SRPC - PhaseConfig Register */ /*! @{ */ #define SPDIF_SRPC_GainSel_MASK (0x38U) #define SPDIF_SRPC_GainSel_SHIFT (3U) /*! GainSel - GainSel * 0b000..24*(2**10) * 0b001..16*(2**10) * 0b010..12*(2**10) * 0b011..8*(2**10) * 0b100..6*(2**10) * 0b101..4*(2**10) * 0b110..3*(2**10) */ #define SPDIF_SRPC_GainSel(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GainSel_SHIFT)) & SPDIF_SRPC_GainSel_MASK) #define SPDIF_SRPC_LOCK_MASK (0x40U) #define SPDIF_SRPC_LOCK_SHIFT (6U) #define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) #define SPDIF_SRPC_ClkSrc_Sel_MASK (0x780U) #define SPDIF_SRPC_ClkSrc_Sel_SHIFT (7U) /*! ClkSrc_Sel - ClkSrc_Sel * 0b0000..Clock Selection from Audio Clock Mux (ACM) */ #define SPDIF_SRPC_ClkSrc_Sel(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_ClkSrc_Sel_SHIFT)) & SPDIF_SRPC_ClkSrc_Sel_MASK) /*! @} */ /*! @name SIE - InterruptEn Register */ /*! @{ */ #define SPDIF_SIE_RxFIFOFul_MASK (0x1U) #define SPDIF_SIE_RxFIFOFul_SHIFT (0U) #define SPDIF_SIE_RxFIFOFul(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RxFIFOFul_SHIFT)) & SPDIF_SIE_RxFIFOFul_MASK) #define SPDIF_SIE_TxEm_MASK (0x2U) #define SPDIF_SIE_TxEm_SHIFT (1U) #define SPDIF_SIE_TxEm(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TxEm_SHIFT)) & SPDIF_SIE_TxEm_MASK) #define SPDIF_SIE_LockLoss_MASK (0x4U) #define SPDIF_SIE_LockLoss_SHIFT (2U) #define SPDIF_SIE_LockLoss(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LockLoss_SHIFT)) & SPDIF_SIE_LockLoss_MASK) #define SPDIF_SIE_RxFIFOResyn_MASK (0x8U) #define SPDIF_SIE_RxFIFOResyn_SHIFT (3U) #define SPDIF_SIE_RxFIFOResyn(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RxFIFOResyn_SHIFT)) & SPDIF_SIE_RxFIFOResyn_MASK) #define SPDIF_SIE_RxFIFOUnOv_MASK (0x10U) #define SPDIF_SIE_RxFIFOUnOv_SHIFT (4U) #define SPDIF_SIE_RxFIFOUnOv(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RxFIFOUnOv_SHIFT)) & SPDIF_SIE_RxFIFOUnOv_MASK) #define SPDIF_SIE_UQErr_MASK (0x20U) #define SPDIF_SIE_UQErr_SHIFT (5U) #define SPDIF_SIE_UQErr(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQErr_SHIFT)) & SPDIF_SIE_UQErr_MASK) #define SPDIF_SIE_UQSync_MASK (0x40U) #define SPDIF_SIE_UQSync_SHIFT (6U) #define SPDIF_SIE_UQSync(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSync_SHIFT)) & SPDIF_SIE_UQSync_MASK) #define SPDIF_SIE_QRxOv_MASK (0x80U) #define SPDIF_SIE_QRxOv_SHIFT (7U) #define SPDIF_SIE_QRxOv(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRxOv_SHIFT)) & SPDIF_SIE_QRxOv_MASK) #define SPDIF_SIE_QRxFul_MASK (0x100U) #define SPDIF_SIE_QRxFul_SHIFT (8U) #define SPDIF_SIE_QRxFul(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRxFul_SHIFT)) & SPDIF_SIE_QRxFul_MASK) #define SPDIF_SIE_URxOv_MASK (0x200U) #define SPDIF_SIE_URxOv_SHIFT (9U) #define SPDIF_SIE_URxOv(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URxOv_SHIFT)) & SPDIF_SIE_URxOv_MASK) #define SPDIF_SIE_URxFul_MASK (0x400U) #define SPDIF_SIE_URxFul_SHIFT (10U) #define SPDIF_SIE_URxFul(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URxFul_SHIFT)) & SPDIF_SIE_URxFul_MASK) #define SPDIF_SIE_BitErr_MASK (0x4000U) #define SPDIF_SIE_BitErr_SHIFT (14U) #define SPDIF_SIE_BitErr(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BitErr_SHIFT)) & SPDIF_SIE_BitErr_MASK) #define SPDIF_SIE_SymErr_MASK (0x8000U) #define SPDIF_SIE_SymErr_SHIFT (15U) #define SPDIF_SIE_SymErr(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SymErr_SHIFT)) & SPDIF_SIE_SymErr_MASK) #define SPDIF_SIE_ValNoGood_MASK (0x10000U) #define SPDIF_SIE_ValNoGood_SHIFT (16U) #define SPDIF_SIE_ValNoGood(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_ValNoGood_SHIFT)) & SPDIF_SIE_ValNoGood_MASK) #define SPDIF_SIE_CNew_MASK (0x20000U) #define SPDIF_SIE_CNew_SHIFT (17U) #define SPDIF_SIE_CNew(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNew_SHIFT)) & SPDIF_SIE_CNew_MASK) #define SPDIF_SIE_TxResyn_MASK (0x40000U) #define SPDIF_SIE_TxResyn_SHIFT (18U) #define SPDIF_SIE_TxResyn(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TxResyn_SHIFT)) & SPDIF_SIE_TxResyn_MASK) #define SPDIF_SIE_TxUnOv_MASK (0x80000U) #define SPDIF_SIE_TxUnOv_SHIFT (19U) #define SPDIF_SIE_TxUnOv(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TxUnOv_SHIFT)) & SPDIF_SIE_TxUnOv_MASK) #define SPDIF_SIE_Lock_MASK (0x100000U) #define SPDIF_SIE_Lock_SHIFT (20U) #define SPDIF_SIE_Lock(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_Lock_SHIFT)) & SPDIF_SIE_Lock_MASK) /*! @} */ /*! @name SIC - InterruptClear Register */ /*! @{ */ #define SPDIF_SIC_LockLoss_MASK (0x4U) #define SPDIF_SIC_LockLoss_SHIFT (2U) #define SPDIF_SIC_LockLoss(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LockLoss_SHIFT)) & SPDIF_SIC_LockLoss_MASK) #define SPDIF_SIC_RxFIFOResyn_MASK (0x8U) #define SPDIF_SIC_RxFIFOResyn_SHIFT (3U) #define SPDIF_SIC_RxFIFOResyn(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RxFIFOResyn_SHIFT)) & SPDIF_SIC_RxFIFOResyn_MASK) #define SPDIF_SIC_RxFIFOUnOv_MASK (0x10U) #define SPDIF_SIC_RxFIFOUnOv_SHIFT (4U) #define SPDIF_SIC_RxFIFOUnOv(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RxFIFOUnOv_SHIFT)) & SPDIF_SIC_RxFIFOUnOv_MASK) #define SPDIF_SIC_UQErr_MASK (0x20U) #define SPDIF_SIC_UQErr_SHIFT (5U) #define SPDIF_SIC_UQErr(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQErr_SHIFT)) & SPDIF_SIC_UQErr_MASK) #define SPDIF_SIC_UQSync_MASK (0x40U) #define SPDIF_SIC_UQSync_SHIFT (6U) #define SPDIF_SIC_UQSync(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSync_SHIFT)) & SPDIF_SIC_UQSync_MASK) #define SPDIF_SIC_QRxOv_MASK (0x80U) #define SPDIF_SIC_QRxOv_SHIFT (7U) #define SPDIF_SIC_QRxOv(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRxOv_SHIFT)) & SPDIF_SIC_QRxOv_MASK) #define SPDIF_SIC_URxOv_MASK (0x200U) #define SPDIF_SIC_URxOv_SHIFT (9U) #define SPDIF_SIC_URxOv(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URxOv_SHIFT)) & SPDIF_SIC_URxOv_MASK) #define SPDIF_SIC_BitErr_MASK (0x4000U) #define SPDIF_SIC_BitErr_SHIFT (14U) #define SPDIF_SIC_BitErr(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BitErr_SHIFT)) & SPDIF_SIC_BitErr_MASK) #define SPDIF_SIC_SymErr_MASK (0x8000U) #define SPDIF_SIC_SymErr_SHIFT (15U) #define SPDIF_SIC_SymErr(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SymErr_SHIFT)) & SPDIF_SIC_SymErr_MASK) #define SPDIF_SIC_ValNoGood_MASK (0x10000U) #define SPDIF_SIC_ValNoGood_SHIFT (16U) #define SPDIF_SIC_ValNoGood(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_ValNoGood_SHIFT)) & SPDIF_SIC_ValNoGood_MASK) #define SPDIF_SIC_CNew_MASK (0x20000U) #define SPDIF_SIC_CNew_SHIFT (17U) #define SPDIF_SIC_CNew(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNew_SHIFT)) & SPDIF_SIC_CNew_MASK) #define SPDIF_SIC_TxResyn_MASK (0x40000U) #define SPDIF_SIC_TxResyn_SHIFT (18U) #define SPDIF_SIC_TxResyn(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TxResyn_SHIFT)) & SPDIF_SIC_TxResyn_MASK) #define SPDIF_SIC_TxUnOv_MASK (0x80000U) #define SPDIF_SIC_TxUnOv_SHIFT (19U) #define SPDIF_SIC_TxUnOv(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TxUnOv_SHIFT)) & SPDIF_SIC_TxUnOv_MASK) #define SPDIF_SIC_Lock_MASK (0x100000U) #define SPDIF_SIC_Lock_SHIFT (20U) #define SPDIF_SIC_Lock(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_Lock_SHIFT)) & SPDIF_SIC_Lock_MASK) /*! @} */ /*! @name SIS - InterruptStat Register */ /*! @{ */ #define SPDIF_SIS_RxFIFOFul_MASK (0x1U) #define SPDIF_SIS_RxFIFOFul_SHIFT (0U) #define SPDIF_SIS_RxFIFOFul(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RxFIFOFul_SHIFT)) & SPDIF_SIS_RxFIFOFul_MASK) #define SPDIF_SIS_TxEm_MASK (0x2U) #define SPDIF_SIS_TxEm_SHIFT (1U) #define SPDIF_SIS_TxEm(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TxEm_SHIFT)) & SPDIF_SIS_TxEm_MASK) #define SPDIF_SIS_LockLoss_MASK (0x4U) #define SPDIF_SIS_LockLoss_SHIFT (2U) #define SPDIF_SIS_LockLoss(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LockLoss_SHIFT)) & SPDIF_SIS_LockLoss_MASK) #define SPDIF_SIS_RxFIFOResyn_MASK (0x8U) #define SPDIF_SIS_RxFIFOResyn_SHIFT (3U) #define SPDIF_SIS_RxFIFOResyn(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RxFIFOResyn_SHIFT)) & SPDIF_SIS_RxFIFOResyn_MASK) #define SPDIF_SIS_RxFIFOUnOv_MASK (0x10U) #define SPDIF_SIS_RxFIFOUnOv_SHIFT (4U) #define SPDIF_SIS_RxFIFOUnOv(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RxFIFOUnOv_SHIFT)) & SPDIF_SIS_RxFIFOUnOv_MASK) #define SPDIF_SIS_UQErr_MASK (0x20U) #define SPDIF_SIS_UQErr_SHIFT (5U) #define SPDIF_SIS_UQErr(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQErr_SHIFT)) & SPDIF_SIS_UQErr_MASK) #define SPDIF_SIS_UQSync_MASK (0x40U) #define SPDIF_SIS_UQSync_SHIFT (6U) #define SPDIF_SIS_UQSync(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSync_SHIFT)) & SPDIF_SIS_UQSync_MASK) #define SPDIF_SIS_QRxOv_MASK (0x80U) #define SPDIF_SIS_QRxOv_SHIFT (7U) #define SPDIF_SIS_QRxOv(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRxOv_SHIFT)) & SPDIF_SIS_QRxOv_MASK) #define SPDIF_SIS_QRxFul_MASK (0x100U) #define SPDIF_SIS_QRxFul_SHIFT (8U) #define SPDIF_SIS_QRxFul(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRxFul_SHIFT)) & SPDIF_SIS_QRxFul_MASK) #define SPDIF_SIS_URxOv_MASK (0x200U) #define SPDIF_SIS_URxOv_SHIFT (9U) #define SPDIF_SIS_URxOv(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URxOv_SHIFT)) & SPDIF_SIS_URxOv_MASK) #define SPDIF_SIS_URxFul_MASK (0x400U) #define SPDIF_SIS_URxFul_SHIFT (10U) #define SPDIF_SIS_URxFul(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URxFul_SHIFT)) & SPDIF_SIS_URxFul_MASK) #define SPDIF_SIS_BitErr_MASK (0x4000U) #define SPDIF_SIS_BitErr_SHIFT (14U) #define SPDIF_SIS_BitErr(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BitErr_SHIFT)) & SPDIF_SIS_BitErr_MASK) #define SPDIF_SIS_SymErr_MASK (0x8000U) #define SPDIF_SIS_SymErr_SHIFT (15U) #define SPDIF_SIS_SymErr(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SymErr_SHIFT)) & SPDIF_SIS_SymErr_MASK) #define SPDIF_SIS_ValNoGood_MASK (0x10000U) #define SPDIF_SIS_ValNoGood_SHIFT (16U) #define SPDIF_SIS_ValNoGood(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_ValNoGood_SHIFT)) & SPDIF_SIS_ValNoGood_MASK) #define SPDIF_SIS_CNew_MASK (0x20000U) #define SPDIF_SIS_CNew_SHIFT (17U) #define SPDIF_SIS_CNew(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNew_SHIFT)) & SPDIF_SIS_CNew_MASK) #define SPDIF_SIS_TxResyn_MASK (0x40000U) #define SPDIF_SIS_TxResyn_SHIFT (18U) #define SPDIF_SIS_TxResyn(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TxResyn_SHIFT)) & SPDIF_SIS_TxResyn_MASK) #define SPDIF_SIS_TxUnOv_MASK (0x80000U) #define SPDIF_SIS_TxUnOv_SHIFT (19U) #define SPDIF_SIS_TxUnOv(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TxUnOv_SHIFT)) & SPDIF_SIS_TxUnOv_MASK) #define SPDIF_SIS_Lock_MASK (0x100000U) #define SPDIF_SIS_Lock_SHIFT (20U) #define SPDIF_SIS_Lock(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_Lock_SHIFT)) & SPDIF_SIS_Lock_MASK) /*! @} */ /*! @name SRL - SPDIFRxLeft Register */ /*! @{ */ #define SPDIF_SRL_RxDataLeft_MASK (0xFFFFFFU) #define SPDIF_SRL_RxDataLeft_SHIFT (0U) #define SPDIF_SRL_RxDataLeft(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RxDataLeft_SHIFT)) & SPDIF_SRL_RxDataLeft_MASK) /*! @} */ /*! @name SRR - SPDIFRxRight Register */ /*! @{ */ #define SPDIF_SRR_RxDataRight_MASK (0xFFFFFFU) #define SPDIF_SRR_RxDataRight_SHIFT (0U) #define SPDIF_SRR_RxDataRight(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RxDataRight_SHIFT)) & SPDIF_SRR_RxDataRight_MASK) /*! @} */ /*! @name SRCSH - SPDIFRxCChannel_h Register */ /*! @{ */ #define SPDIF_SRCSH_RxCChannel_h_MASK (0xFFFFFFU) #define SPDIF_SRCSH_RxCChannel_h_SHIFT (0U) #define SPDIF_SRCSH_RxCChannel_h(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RxCChannel_h_SHIFT)) & SPDIF_SRCSH_RxCChannel_h_MASK) /*! @} */ /*! @name SRCSL - SPDIFRxCChannel_l Register */ /*! @{ */ #define SPDIF_SRCSL_RxCChannel_l_MASK (0xFFFFFFU) #define SPDIF_SRCSL_RxCChannel_l_SHIFT (0U) #define SPDIF_SRCSL_RxCChannel_l(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RxCChannel_l_SHIFT)) & SPDIF_SRCSL_RxCChannel_l_MASK) /*! @} */ /*! @name SRU - UchannelRx Register */ /*! @{ */ #define SPDIF_SRU_RxUChannel_MASK (0xFFFFFFU) #define SPDIF_SRU_RxUChannel_SHIFT (0U) #define SPDIF_SRU_RxUChannel(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RxUChannel_SHIFT)) & SPDIF_SRU_RxUChannel_MASK) /*! @} */ /*! @name SRQ - QchannelRx Register */ /*! @{ */ #define SPDIF_SRQ_RxQChannel_MASK (0xFFFFFFU) #define SPDIF_SRQ_RxQChannel_SHIFT (0U) #define SPDIF_SRQ_RxQChannel(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RxQChannel_SHIFT)) & SPDIF_SRQ_RxQChannel_MASK) /*! @} */ /*! @name STL - SPDIFTxLeft Register */ /*! @{ */ #define SPDIF_STL_TxDataLeft_MASK (0xFFFFFFU) #define SPDIF_STL_TxDataLeft_SHIFT (0U) #define SPDIF_STL_TxDataLeft(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TxDataLeft_SHIFT)) & SPDIF_STL_TxDataLeft_MASK) /*! @} */ /*! @name STR - SPDIFTxRight Register */ /*! @{ */ #define SPDIF_STR_TxDataRight_MASK (0xFFFFFFU) #define SPDIF_STR_TxDataRight_SHIFT (0U) #define SPDIF_STR_TxDataRight(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TxDataRight_SHIFT)) & SPDIF_STR_TxDataRight_MASK) /*! @} */ /*! @name STCSCH - SPDIFTxCChannelCons_h Register */ /*! @{ */ #define SPDIF_STCSCH_TxCChannelCons_h_MASK (0xFFFFFFU) #define SPDIF_STCSCH_TxCChannelCons_h_SHIFT (0U) #define SPDIF_STCSCH_TxCChannelCons_h(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TxCChannelCons_h_SHIFT)) & SPDIF_STCSCH_TxCChannelCons_h_MASK) /*! @} */ /*! @name STCSCL - SPDIFTxCChannelCons_l Register */ /*! @{ */ #define SPDIF_STCSCL_TxCChannelCons_l_MASK (0xFFFFFFU) #define SPDIF_STCSCL_TxCChannelCons_l_SHIFT (0U) #define SPDIF_STCSCL_TxCChannelCons_l(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TxCChannelCons_l_SHIFT)) & SPDIF_STCSCL_TxCChannelCons_l_MASK) /*! @} */ /*! @name SRFM - FreqMeas Register */ /*! @{ */ #define SPDIF_SRFM_FreqMeas_MASK (0xFFFFFFU) #define SPDIF_SRFM_FreqMeas_SHIFT (0U) #define SPDIF_SRFM_FreqMeas(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FreqMeas_SHIFT)) & SPDIF_SRFM_FreqMeas_MASK) /*! @} */ /*! @name STC - SPDIFTxClk Register */ /*! @{ */ #define SPDIF_STC_TxClk_DF_MASK (0x7FU) #define SPDIF_STC_TxClk_DF_SHIFT (0U) /*! TxClk_DF - TxClk_DF * 0b0000000..divider factor is 1 * 0b0000001..divider factor is 2 * 0b1111111..divider factor is 128 */ #define SPDIF_STC_TxClk_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TxClk_DF_SHIFT)) & SPDIF_STC_TxClk_DF_MASK) #define SPDIF_STC_tx_all_clk_en_MASK (0x80U) #define SPDIF_STC_tx_all_clk_en_SHIFT (7U) /*! tx_all_clk_en - tx_all_clk_en * 0b0..disable transfer clock. * 0b1..enable transfer clock. */ #define SPDIF_STC_tx_all_clk_en(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_tx_all_clk_en_SHIFT)) & SPDIF_STC_tx_all_clk_en_MASK) #define SPDIF_STC_TxClk_Source_MASK (0x700U) #define SPDIF_STC_TxClk_Source_SHIFT (8U) /*! TxClk_Source - TxClk_Source * 0b000..Clock Selection from Audio Clock Mux (ACM) */ #define SPDIF_STC_TxClk_Source(x) \ (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TxClk_Source_SHIFT)) & SPDIF_STC_TxClk_Source_MASK) #define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) #define SPDIF_STC_SYSCLK_DF_SHIFT (11U) /*! SYSCLK_DF - SYSCLK_DF * 0b000000000..no clock signal * 0b000000001..divider factor is 2 * 0b111111111..divider factor is 512 */ #define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) /*! @} */ /*! * @} */ /* end of group SPDIF_Register_Masks */ /* SPDIF - Peripheral instance base addresses */ /** Peripheral SPDIF1 base address */ #define SPDIF1_BASE (0x30090000u) /** Peripheral SPDIF1 base pointer */ #define SPDIF1 ((SPDIF_Type *)SPDIF1_BASE) /** Peripheral SPDIF2 base address */ #define SPDIF2_BASE (0x300A0000u) /** Peripheral SPDIF2 base pointer */ #define SPDIF2 ((SPDIF_Type *)SPDIF2_BASE) /** Array initializer of SPDIF peripheral base addresses */ #define SPDIF_BASE_ADDRS \ { \ SPDIF1_BASE, SPDIF2_BASE \ } /** Array initializer of SPDIF peripheral base pointers */ #define SPDIF_BASE_PTRS \ { \ SPDIF1, SPDIF2 \ } /*! * @} */ /* end of group SPDIF_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SRC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer * @{ */ /** SRC - Register Layout Typedef */ typedef struct { __IO uint32_t SCR; /**< SRC Reset Control Register, offset: 0x0 */ __IO uint32_t A53RCR0; /**< A53 Reset Control Register, offset: 0x4 */ __IO uint32_t A53RCR1; /**< A53 Reset Control Register, offset: 0x8 */ __IO uint32_t M7RCR; /**< M7 Reset Control Register, offset: 0xC */ uint8_t RESERVED_0[16]; __IO uint32_t USBOPHY1_RCR; /**< USB OTG PHY1 Reset Control Register, offset: 0x20 */ uint8_t RESERVED_1[4]; __IO uint32_t MIPIPHY_RCR; /**< MIPI PHY Reset Control Register, offset: 0x28 */ uint8_t RESERVED_2[8]; __IO uint32_t DISP_RCR; /**< DISPLAY Reset Control Register, offset: 0x34 */ uint8_t RESERVED_3[8]; __IO uint32_t GPU_RCR; /**< GPU Reset Control Register, offset: 0x40 */ uint8_t RESERVED_4[20]; __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x58 */ __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x5C */ uint8_t RESERVED_5[8]; __IO uint32_t SISR; /**< SRC Interrupt Status Register, offset: 0x68 */ __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */ __I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x70 */ __IO uint32_t GPR1; /**< SRC General Purpose Register 1, offset: 0x74 */ __IO uint32_t GPR2; /**< SRC General Purpose Register 2, offset: 0x78 */ __IO uint32_t GPR3; /**< SRC General Purpose Register 3, offset: 0x7C */ __IO uint32_t GPR4; /**< SRC General Purpose Register 4, offset: 0x80 */ __IO uint32_t GPR5; /**< SRC General Purpose Register 5, offset: 0x84 */ __IO uint32_t GPR6; /**< SRC General Purpose Register 6, offset: 0x88 */ __IO uint32_t GPR7; /**< SRC General Purpose Register 7, offset: 0x8C */ __IO uint32_t GPR8; /**< SRC General Purpose Register 8, offset: 0x90 */ uint32_t GPR9; /**< SRC General Purpose Register 9, offset: 0x94 */ uint32_t GPR10; /**< SRC General Purpose Register 10, offset: 0x98 */ uint8_t RESERVED_6[3940]; __IO uint32_t DDRC_RCR; /**< SRC DDR Controller Reset Control Register, offset: 0x1000 */ } SRC_Type; /* ---------------------------------------------------------------------------- -- SRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SRC_Register_Masks SRC Register Masks * @{ */ /*! @name SCR - SRC Reset Control Register */ /*! @{ */ #define SRC_SCR_MASK_TEMPSENSE_RESET_MASK (0xF0U) #define SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT (4U) /*! MASK_TEMPSENSE_RESET * 0b0101..tempsense_reset is masked * 0b1010..tempsense_reset is not masked */ #define SRC_SCR_MASK_TEMPSENSE_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT)) & SRC_SCR_MASK_TEMPSENSE_RESET_MASK) #define SRC_SCR_DOMAIN0_MASK (0x1000000U) #define SRC_SCR_DOMAIN0_SHIFT (24U) /*! DOMAIN0 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. * 0b1..This register is assigned to domain0. The master from domain3 can write to this register */ #define SRC_SCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN0_SHIFT)) & SRC_SCR_DOMAIN0_MASK) #define SRC_SCR_DOMAIN1_MASK (0x2000000U) #define SRC_SCR_DOMAIN1_SHIFT (25U) /*! DOMAIN1 * 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register. * 0b1..This register is assigned to domain1. The master from domain1 can write to this register */ #define SRC_SCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN1_SHIFT)) & SRC_SCR_DOMAIN1_MASK) #define SRC_SCR_DOMAIN2_MASK (0x4000000U) #define SRC_SCR_DOMAIN2_SHIFT (26U) /*! DOMAIN2 * 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register. * 0b1..This register is assigned to domain2. The master from domain2 can write to this register */ #define SRC_SCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN2_SHIFT)) & SRC_SCR_DOMAIN2_MASK) #define SRC_SCR_DOMAIN3_MASK (0x8000000U) #define SRC_SCR_DOMAIN3_SHIFT (27U) /*! DOMAIN3 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. * 0b1..This register is assigned to domain3. The master from domain3 can write to this register */ #define SRC_SCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN3_SHIFT)) & SRC_SCR_DOMAIN3_MASK) #define SRC_SCR_LOCK_MASK (0x40000000U) #define SRC_SCR_LOCK_SHIFT (30U) /*! LOCK * 0b0..[31] and [27:24] bits can be modified * 0b1..[31] and [27:24] bits cannot be modified */ #define SRC_SCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_LOCK_SHIFT)) & SRC_SCR_LOCK_MASK) #define SRC_SCR_DOM_EN_MASK (0x80000000U) #define SRC_SCR_DOM_EN_SHIFT (31U) /*! DOM_EN * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by * the masters from the domains specified in [27:24] area. */ #define SRC_SCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOM_EN_SHIFT)) & SRC_SCR_DOM_EN_MASK) /*! @} */ /*! @name A53RCR0 - A53 Reset Control Register */ /*! @{ */ #define SRC_A53RCR0_A53_CORE_POR_RESET0_MASK (0x1U) #define SRC_A53RCR0_A53_CORE_POR_RESET0_SHIFT (0U) /*! A53_CORE_POR_RESET0 * 0b0..do not assert core0 reset * 0b1..assert core0 reset */ #define SRC_A53RCR0_A53_CORE_POR_RESET0(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET0_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET0_MASK) #define SRC_A53RCR0_A53_CORE_POR_RESET1_MASK (0x2U) #define SRC_A53RCR0_A53_CORE_POR_RESET1_SHIFT (1U) /*! A53_CORE_POR_RESET1 * 0b0..do not assert core1 reset * 0b1..assert core1 reset */ #define SRC_A53RCR0_A53_CORE_POR_RESET1(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET1_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET1_MASK) #define SRC_A53RCR0_A53_CORE_POR_RESET2_MASK (0x4U) #define SRC_A53RCR0_A53_CORE_POR_RESET2_SHIFT (2U) /*! A53_CORE_POR_RESET2 * 0b0..do not assert core2 reset * 0b1..assert core2 reset */ #define SRC_A53RCR0_A53_CORE_POR_RESET2(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET2_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET2_MASK) #define SRC_A53RCR0_A53_CORE_POR_RESET3_MASK (0x8U) #define SRC_A53RCR0_A53_CORE_POR_RESET3_SHIFT (3U) /*! A53_CORE_POR_RESET3 * 0b0..do not assert core3 reset * 0b1..assert core3 reset */ #define SRC_A53RCR0_A53_CORE_POR_RESET3(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET3_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET3_MASK) #define SRC_A53RCR0_A53_CORE_RESET0_MASK (0x10U) #define SRC_A53RCR0_A53_CORE_RESET0_SHIFT (4U) /*! A53_CORE_RESET0 * 0b0..do not assert core0 reset * 0b1..assert core0 reset */ #define SRC_A53RCR0_A53_CORE_RESET0(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET0_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET0_MASK) #define SRC_A53RCR0_A53_CORE_RESET1_MASK (0x20U) #define SRC_A53RCR0_A53_CORE_RESET1_SHIFT (5U) /*! A53_CORE_RESET1 * 0b0..do not assert core1 reset * 0b1..assert core1 reset */ #define SRC_A53RCR0_A53_CORE_RESET1(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET1_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET1_MASK) #define SRC_A53RCR0_A53_CORE_RESET2_MASK (0x40U) #define SRC_A53RCR0_A53_CORE_RESET2_SHIFT (6U) /*! A53_CORE_RESET2 * 0b0..do not assert core2 reset * 0b1..assert core2 reset */ #define SRC_A53RCR0_A53_CORE_RESET2(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET2_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET2_MASK) #define SRC_A53RCR0_A53_CORE_RESET3_MASK (0x80U) #define SRC_A53RCR0_A53_CORE_RESET3_SHIFT (7U) /*! A53_CORE_RESET3 * 0b0..do not assert core3 reset * 0b1..assert core3 reset */ #define SRC_A53RCR0_A53_CORE_RESET3(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET3_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET3_MASK) #define SRC_A53RCR0_A53_DBG_RESET0_MASK (0x100U) #define SRC_A53RCR0_A53_DBG_RESET0_SHIFT (8U) /*! A53_DBG_RESET0 * 0b0..do not assert core0 debug reset * 0b1..assert core0 debug reset */ #define SRC_A53RCR0_A53_DBG_RESET0(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET0_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET0_MASK) #define SRC_A53RCR0_A53_DBG_RESET1_MASK (0x200U) #define SRC_A53RCR0_A53_DBG_RESET1_SHIFT (9U) /*! A53_DBG_RESET1 * 0b0..do not assert core1 debug reset * 0b1..assert core1 debug reset */ #define SRC_A53RCR0_A53_DBG_RESET1(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET1_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET1_MASK) #define SRC_A53RCR0_A53_DBG_RESET2_MASK (0x400U) #define SRC_A53RCR0_A53_DBG_RESET2_SHIFT (10U) /*! A53_DBG_RESET2 * 0b0..do not assert core2 debug reset * 0b1..assert core2 debug reset */ #define SRC_A53RCR0_A53_DBG_RESET2(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET2_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET2_MASK) #define SRC_A53RCR0_A53_DBG_RESET3_MASK (0x800U) #define SRC_A53RCR0_A53_DBG_RESET3_SHIFT (11U) /*! A53_DBG_RESET3 * 0b0..do not assert core3 debug reset * 0b1..assert core3 debug reset */ #define SRC_A53RCR0_A53_DBG_RESET3(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET3_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET3_MASK) #define SRC_A53RCR0_A53_ETM_RESET0_MASK (0x1000U) #define SRC_A53RCR0_A53_ETM_RESET0_SHIFT (12U) /*! A53_ETM_RESET0 * 0b0..do not assert core0 ETM reset * 0b1..assert core0 ETM reset */ #define SRC_A53RCR0_A53_ETM_RESET0(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET0_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET0_MASK) #define SRC_A53RCR0_A53_ETM_RESET1_MASK (0x2000U) #define SRC_A53RCR0_A53_ETM_RESET1_SHIFT (13U) /*! A53_ETM_RESET1 * 0b0..do not assert core1 ETM reset * 0b1..assert core1 ETM reset */ #define SRC_A53RCR0_A53_ETM_RESET1(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET1_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET1_MASK) #define SRC_A53RCR0_A53_ETM_RESET2_MASK (0x4000U) #define SRC_A53RCR0_A53_ETM_RESET2_SHIFT (14U) /*! A53_ETM_RESET2 * 0b0..do not assert core2 ETM reset * 0b1..assert core2 ETM reset */ #define SRC_A53RCR0_A53_ETM_RESET2(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET2_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET2_MASK) #define SRC_A53RCR0_A53_ETM_RESET3_MASK (0x8000U) #define SRC_A53RCR0_A53_ETM_RESET3_SHIFT (15U) /*! A53_ETM_RESET3 * 0b0..do not assert core3 ETM reset * 0b1..assert core3 ETM reset */ #define SRC_A53RCR0_A53_ETM_RESET3(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET3_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET3_MASK) #define SRC_A53RCR0_MASK_WDOG1_RST_MASK (0xF0000U) #define SRC_A53RCR0_MASK_WDOG1_RST_SHIFT (16U) /*! MASK_WDOG1_RST * 0b0101..wdog1_rst_b is masked * 0b1010..wdog1_rst_b is not masked */ #define SRC_A53RCR0_MASK_WDOG1_RST(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_MASK_WDOG1_RST_SHIFT)) & SRC_A53RCR0_MASK_WDOG1_RST_MASK) #define SRC_A53RCR0_A53_SOC_DBG_RESET_MASK (0x100000U) #define SRC_A53RCR0_A53_SOC_DBG_RESET_SHIFT (20U) /*! A53_SOC_DBG_RESET * 0b0..do not assert system level debug reset * 0b1..assert system level debug reset */ #define SRC_A53RCR0_A53_SOC_DBG_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_SOC_DBG_RESET_SHIFT)) & SRC_A53RCR0_A53_SOC_DBG_RESET_MASK) #define SRC_A53RCR0_A53_L2RESET_MASK (0x200000U) #define SRC_A53RCR0_A53_L2RESET_SHIFT (21U) /*! A53_L2RESET * 0b0..do not assert SCU reset * 0b1..assert SCU reset */ #define SRC_A53RCR0_A53_L2RESET(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_L2RESET_SHIFT)) & SRC_A53RCR0_A53_L2RESET_MASK) #define SRC_A53RCR0_DOMAIN0_MASK (0x1000000U) #define SRC_A53RCR0_DOMAIN0_SHIFT (24U) /*! DOMAIN0 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. * 0b1..This register is assigned to domain0. The master from domain3 can write to this register */ #define SRC_A53RCR0_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN0_SHIFT)) & SRC_A53RCR0_DOMAIN0_MASK) #define SRC_A53RCR0_DOMAIN1_MASK (0x2000000U) #define SRC_A53RCR0_DOMAIN1_SHIFT (25U) /*! DOMAIN1 * 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register. * 0b1..This register is assigned to domain1. The master from domain1 can write to this register */ #define SRC_A53RCR0_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN1_SHIFT)) & SRC_A53RCR0_DOMAIN1_MASK) #define SRC_A53RCR0_DOMAIN2_MASK (0x4000000U) #define SRC_A53RCR0_DOMAIN2_SHIFT (26U) /*! DOMAIN2 * 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register. * 0b1..This register is assigned to domain2. The master from domain2 can write to this register */ #define SRC_A53RCR0_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN2_SHIFT)) & SRC_A53RCR0_DOMAIN2_MASK) #define SRC_A53RCR0_DOMAIN3_MASK (0x8000000U) #define SRC_A53RCR0_DOMAIN3_SHIFT (27U) /*! DOMAIN3 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. * 0b1..This register is assigned to domain3. The master from domain3 can write to this register */ #define SRC_A53RCR0_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN3_SHIFT)) & SRC_A53RCR0_DOMAIN3_MASK) #define SRC_A53RCR0_LOCK_MASK (0x40000000U) #define SRC_A53RCR0_LOCK_SHIFT (30U) /*! LOCK * 0b0..[31] and [27:24] bits can be modified * 0b1..[31] and [27:24] bits cannot be modified */ #define SRC_A53RCR0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_LOCK_SHIFT)) & SRC_A53RCR0_LOCK_MASK) #define SRC_A53RCR0_DOM_EN_MASK (0x80000000U) #define SRC_A53RCR0_DOM_EN_SHIFT (31U) /*! DOM_EN * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by * the masters from the domains specified in [27:24] area. */ #define SRC_A53RCR0_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOM_EN_SHIFT)) & SRC_A53RCR0_DOM_EN_MASK) /*! @} */ /*! @name A53RCR1 - A53 Reset Control Register */ /*! @{ */ #define SRC_A53RCR1_A53_CORE0_ENABLE_MASK (0x1U) #define SRC_A53RCR1_A53_CORE0_ENABLE_SHIFT (0U) #define SRC_A53RCR1_A53_CORE0_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE0_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE0_ENABLE_MASK) #define SRC_A53RCR1_A53_CORE1_ENABLE_MASK (0x2U) #define SRC_A53RCR1_A53_CORE1_ENABLE_SHIFT (1U) /*! A53_CORE1_ENABLE * 0b0..core1 is disabled * 0b1..core1 is enabled */ #define SRC_A53RCR1_A53_CORE1_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE1_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE1_ENABLE_MASK) #define SRC_A53RCR1_A53_CORE2_ENABLE_MASK (0x4U) #define SRC_A53RCR1_A53_CORE2_ENABLE_SHIFT (2U) /*! A53_CORE2_ENABLE * 0b0..core2 is disabled * 0b1..core2 is enabled */ #define SRC_A53RCR1_A53_CORE2_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE2_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE2_ENABLE_MASK) #define SRC_A53RCR1_A53_CORE3_ENABLE_MASK (0x8U) #define SRC_A53RCR1_A53_CORE3_ENABLE_SHIFT (3U) /*! A53_CORE3_ENABLE * 0b0..core3 is disabled * 0b1..core3 is enabled */ #define SRC_A53RCR1_A53_CORE3_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE3_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE3_ENABLE_MASK) #define SRC_A53RCR1_A53_RST_SLOW_MASK (0x70U) #define SRC_A53RCR1_A53_RST_SLOW_SHIFT (4U) #define SRC_A53RCR1_A53_RST_SLOW(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_RST_SLOW_SHIFT)) & SRC_A53RCR1_A53_RST_SLOW_MASK) #define SRC_A53RCR1_DOMAIN0_MASK (0x1000000U) #define SRC_A53RCR1_DOMAIN0_SHIFT (24U) /*! DOMAIN0 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. * 0b1..This register is assigned to domain0. The master from domain3 can write to this register */ #define SRC_A53RCR1_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN0_SHIFT)) & SRC_A53RCR1_DOMAIN0_MASK) #define SRC_A53RCR1_DOMAIN1_MASK (0x2000000U) #define SRC_A53RCR1_DOMAIN1_SHIFT (25U) /*! DOMAIN1 * 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register. * 0b1..This register is assigned to domain1. The master from domain1 can write to this register */ #define SRC_A53RCR1_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN1_SHIFT)) & SRC_A53RCR1_DOMAIN1_MASK) #define SRC_A53RCR1_DOMAIN2_MASK (0x4000000U) #define SRC_A53RCR1_DOMAIN2_SHIFT (26U) /*! DOMAIN2 * 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register. * 0b1..This register is assigned to domain2. The master from domain2 can write to this register */ #define SRC_A53RCR1_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN2_SHIFT)) & SRC_A53RCR1_DOMAIN2_MASK) #define SRC_A53RCR1_DOMAIN3_MASK (0x8000000U) #define SRC_A53RCR1_DOMAIN3_SHIFT (27U) /*! DOMAIN3 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. * 0b1..This register is assigned to domain3. The master from domain3 can write to this register */ #define SRC_A53RCR1_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN3_SHIFT)) & SRC_A53RCR1_DOMAIN3_MASK) #define SRC_A53RCR1_LOCK_MASK (0x40000000U) #define SRC_A53RCR1_LOCK_SHIFT (30U) /*! LOCK * 0b0..[31] and [27:24] bits can be modified * 0b1..[31] and [27:24] bits cannot be modified */ #define SRC_A53RCR1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_LOCK_SHIFT)) & SRC_A53RCR1_LOCK_MASK) #define SRC_A53RCR1_DOM_EN_MASK (0x80000000U) #define SRC_A53RCR1_DOM_EN_SHIFT (31U) /*! DOM_EN * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by * the masters from the domains specified in [27:24] area. */ #define SRC_A53RCR1_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOM_EN_SHIFT)) & SRC_A53RCR1_DOM_EN_MASK) /*! @} */ /*! @name M7RCR - M7 Reset Control Register */ /*! @{ */ #define SRC_M7RCR_SW_M7C_NON_SCLR_RST_MASK (0x1U) #define SRC_M7RCR_SW_M7C_NON_SCLR_RST_SHIFT (0U) /*! SW_M7C_NON_SCLR_RST * 0b0..do not assert M7 core reset * 0b1..assert M7 core reset */ #define SRC_M7RCR_SW_M7C_NON_SCLR_RST(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_SW_M7C_NON_SCLR_RST_SHIFT)) & SRC_M7RCR_SW_M7C_NON_SCLR_RST_MASK) #define SRC_M7RCR_SW_M7C_RST_MASK (0x2U) #define SRC_M7RCR_SW_M7C_RST_SHIFT (1U) /*! SW_M7C_RST * 0b0..do not assert M7 core reset * 0b1..assert M7 core reset */ #define SRC_M7RCR_SW_M7C_RST(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_SW_M7C_RST_SHIFT)) & SRC_M7RCR_SW_M7C_RST_MASK) #define SRC_M7RCR_ENABLE_M7_MASK (0x8U) #define SRC_M7RCR_ENABLE_M7_SHIFT (3U) /*! ENABLE_M7 * 0b0..M7 is disabled * 0b1..M7 is enabled */ #define SRC_M7RCR_ENABLE_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_ENABLE_M7_SHIFT)) & SRC_M7RCR_ENABLE_M7_MASK) #define SRC_M7RCR_MASK_WDOG3_RST_MASK (0xF0U) #define SRC_M7RCR_MASK_WDOG3_RST_SHIFT (4U) /*! MASK_WDOG3_RST * 0b0101..wdog3_rst_b is masked * 0b1010..wdog3_rst_b is not masked */ #define SRC_M7RCR_MASK_WDOG3_RST(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_MASK_WDOG3_RST_SHIFT)) & SRC_M7RCR_MASK_WDOG3_RST_MASK) #define SRC_M7RCR_WDOG3_RST_OPTION_M7_MASK (0x100U) #define SRC_M7RCR_WDOG3_RST_OPTION_M7_SHIFT (8U) /*! WDOG3_RST_OPTION_M7 * 0b0..wdgo3_rst_b Reset M7 core only * 0b1..Reset both M7 core and platform */ #define SRC_M7RCR_WDOG3_RST_OPTION_M7(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_WDOG3_RST_OPTION_M7_SHIFT)) & SRC_M7RCR_WDOG3_RST_OPTION_M7_MASK) #define SRC_M7RCR_WDOG3_RST_OPTION_MASK (0x200U) #define SRC_M7RCR_WDOG3_RST_OPTION_SHIFT (9U) /*! WDOG3_RST_OPTION * 0b0..Wdog3_rst_b asserts M7 reset * 0b1..Wdog3_rst_b asserts global reset */ #define SRC_M7RCR_WDOG3_RST_OPTION(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_WDOG3_RST_OPTION_SHIFT)) & SRC_M7RCR_WDOG3_RST_OPTION_MASK) #define SRC_M7RCR_DOMAIN0_MASK (0x1000000U) #define SRC_M7RCR_DOMAIN0_SHIFT (24U) /*! DOMAIN0 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. * 0b1..This register is assigned to domain0. The master from domain3 can write to this register */ #define SRC_M7RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOMAIN0_SHIFT)) & SRC_M7RCR_DOMAIN0_MASK) #define SRC_M7RCR_DOMAIN1_MASK (0x2000000U) #define SRC_M7RCR_DOMAIN1_SHIFT (25U) /*! DOMAIN1 * 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register. * 0b1..This register is assigned to domain1. The master from domain1 can write to this register */ #define SRC_M7RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOMAIN1_SHIFT)) & SRC_M7RCR_DOMAIN1_MASK) #define SRC_M7RCR_DOMAIN2_MASK (0x4000000U) #define SRC_M7RCR_DOMAIN2_SHIFT (26U) /*! DOMAIN2 * 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register. * 0b1..This register is assigned to domain2. The master from domain2 can write to this register */ #define SRC_M7RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOMAIN2_SHIFT)) & SRC_M7RCR_DOMAIN2_MASK) #define SRC_M7RCR_DOMAIN3_MASK (0x8000000U) #define SRC_M7RCR_DOMAIN3_SHIFT (27U) /*! DOMAIN3 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. * 0b1..This register is assigned to domain3. The master from domain3 can write to this register */ #define SRC_M7RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOMAIN3_SHIFT)) & SRC_M7RCR_DOMAIN3_MASK) #define SRC_M7RCR_LOCK_MASK (0x40000000U) #define SRC_M7RCR_LOCK_SHIFT (30U) /*! LOCK * 0b0..[31] and [27:24] bits can be modified * 0b1..[31] and [27:24] bits cannot be modified */ #define SRC_M7RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_LOCK_SHIFT)) & SRC_M7RCR_LOCK_MASK) #define SRC_M7RCR_DOM_EN_MASK (0x80000000U) #define SRC_M7RCR_DOM_EN_SHIFT (31U) /*! DOM_EN * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by * the masters from the domains specified in [27:24] area. */ #define SRC_M7RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOM_EN_SHIFT)) & SRC_M7RCR_DOM_EN_MASK) /*! @} */ /*! @name USBOPHY1_RCR - USB OTG PHY1 Reset Control Register */ /*! @{ */ #define SRC_USBOPHY1_RCR_OTG1_PHY_RESET_MASK (0x1U) #define SRC_USBOPHY1_RCR_OTG1_PHY_RESET_SHIFT (0U) /*! OTG1_PHY_RESET * 0b0..Don't reset USB OTG1 PHY * 0b1..Reset USB OTG1 PHY */ #define SRC_USBOPHY1_RCR_OTG1_PHY_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_OTG1_PHY_RESET_SHIFT)) & SRC_USBOPHY1_RCR_OTG1_PHY_RESET_MASK) #define SRC_USBOPHY1_RCR_DOMAIN0_MASK (0x1000000U) #define SRC_USBOPHY1_RCR_DOMAIN0_SHIFT (24U) /*! DOMAIN0 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. * 0b1..This register is assigned to domain0. The master from domain3 can write to this register */ #define SRC_USBOPHY1_RCR_DOMAIN0(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN0_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN0_MASK) #define SRC_USBOPHY1_RCR_DOMAIN1_MASK (0x2000000U) #define SRC_USBOPHY1_RCR_DOMAIN1_SHIFT (25U) /*! DOMAIN1 * 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register. * 0b1..This register is assigned to domain1. The master from domain1 can write to this register */ #define SRC_USBOPHY1_RCR_DOMAIN1(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN1_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN1_MASK) #define SRC_USBOPHY1_RCR_DOMAIN2_MASK (0x4000000U) #define SRC_USBOPHY1_RCR_DOMAIN2_SHIFT (26U) /*! DOMAIN2 * 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register. * 0b1..This register is assigned to domain2. The master from domain2 can write to this register */ #define SRC_USBOPHY1_RCR_DOMAIN2(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN2_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN2_MASK) #define SRC_USBOPHY1_RCR_DOMAIN3_MASK (0x8000000U) #define SRC_USBOPHY1_RCR_DOMAIN3_SHIFT (27U) /*! DOMAIN3 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. * 0b1..This register is assigned to domain3. The master from domain3 can write to this register */ #define SRC_USBOPHY1_RCR_DOMAIN3(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN3_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN3_MASK) #define SRC_USBOPHY1_RCR_LOCK_MASK (0x40000000U) #define SRC_USBOPHY1_RCR_LOCK_SHIFT (30U) /*! LOCK * 0b0..[31] and [27:24] bits can be modified * 0b1..[31] and [27:24] bits cannot be modified */ #define SRC_USBOPHY1_RCR_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_LOCK_SHIFT)) & SRC_USBOPHY1_RCR_LOCK_MASK) #define SRC_USBOPHY1_RCR_DOM_EN_MASK (0x80000000U) #define SRC_USBOPHY1_RCR_DOM_EN_SHIFT (31U) /*! DOM_EN * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by * the masters from the domains specified in [27:24] area. */ #define SRC_USBOPHY1_RCR_DOM_EN(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOM_EN_SHIFT)) & SRC_USBOPHY1_RCR_DOM_EN_MASK) /*! @} */ /*! @name MIPIPHY_RCR - MIPI PHY Reset Control Register */ /*! @{ */ #define SRC_MIPIPHY_RCR_DOMAIN0_MASK (0x1000000U) #define SRC_MIPIPHY_RCR_DOMAIN0_SHIFT (24U) /*! DOMAIN0 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. * 0b1..This register is assigned to domain0. The master from domain3 can write to this register */ #define SRC_MIPIPHY_RCR_DOMAIN0(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN0_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN0_MASK) #define SRC_MIPIPHY_RCR_DOMAIN1_MASK (0x2000000U) #define SRC_MIPIPHY_RCR_DOMAIN1_SHIFT (25U) /*! DOMAIN1 * 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register. * 0b1..This register is assigned to domain1. The master from domain1 can write to this register */ #define SRC_MIPIPHY_RCR_DOMAIN1(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN1_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN1_MASK) #define SRC_MIPIPHY_RCR_DOMAIN2_MASK (0x4000000U) #define SRC_MIPIPHY_RCR_DOMAIN2_SHIFT (26U) /*! DOMAIN2 * 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register. * 0b1..This register is assigned to domain2. The master from domain2 can write to this register */ #define SRC_MIPIPHY_RCR_DOMAIN2(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN2_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN2_MASK) #define SRC_MIPIPHY_RCR_DOMAIN3_MASK (0x8000000U) #define SRC_MIPIPHY_RCR_DOMAIN3_SHIFT (27U) /*! DOMAIN3 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. * 0b1..This register is assigned to domain3. The master from domain3 can write to this register */ #define SRC_MIPIPHY_RCR_DOMAIN3(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN3_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN3_MASK) #define SRC_MIPIPHY_RCR_LOCK_MASK (0x40000000U) #define SRC_MIPIPHY_RCR_LOCK_SHIFT (30U) /*! LOCK * 0b0..[31] and [27:24] bits can be modified * 0b1..[31] and [27:24] bits cannot be modified */ #define SRC_MIPIPHY_RCR_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_LOCK_SHIFT)) & SRC_MIPIPHY_RCR_LOCK_MASK) #define SRC_MIPIPHY_RCR_DOM_EN_MASK (0x80000000U) #define SRC_MIPIPHY_RCR_DOM_EN_SHIFT (31U) /*! DOM_EN * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by * the masters from the domains specified in [27:24] area. */ #define SRC_MIPIPHY_RCR_DOM_EN(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOM_EN_SHIFT)) & SRC_MIPIPHY_RCR_DOM_EN_MASK) /*! @} */ /*! @name DISP_RCR - DISPLAY Reset Control Register */ /*! @{ */ #define SRC_DISP_RCR_DISP_RESET_MASK (0x1U) #define SRC_DISP_RCR_DISP_RESET_SHIFT (0U) /*! DISP_RESET * 0b0..Don't reset dispmix * 0b1..Reset dispmix */ #define SRC_DISP_RCR_DISP_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DISP_RESET_SHIFT)) & SRC_DISP_RCR_DISP_RESET_MASK) #define SRC_DISP_RCR_DOMAIN0_MASK (0x1000000U) #define SRC_DISP_RCR_DOMAIN0_SHIFT (24U) /*! DOMAIN0 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. * 0b1..This register is assigned to domain0. The master from domain3 can write to this register */ #define SRC_DISP_RCR_DOMAIN0(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN0_SHIFT)) & SRC_DISP_RCR_DOMAIN0_MASK) #define SRC_DISP_RCR_DOMAIN1_MASK (0x2000000U) #define SRC_DISP_RCR_DOMAIN1_SHIFT (25U) /*! DOMAIN1 * 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register. * 0b1..This register is assigned to domain1. The master from domain1 can write to this register */ #define SRC_DISP_RCR_DOMAIN1(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN1_SHIFT)) & SRC_DISP_RCR_DOMAIN1_MASK) #define SRC_DISP_RCR_DOMAIN2_MASK (0x4000000U) #define SRC_DISP_RCR_DOMAIN2_SHIFT (26U) /*! DOMAIN2 * 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register. * 0b1..This register is assigned to domain2. The master from domain2 can write to this register */ #define SRC_DISP_RCR_DOMAIN2(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN2_SHIFT)) & SRC_DISP_RCR_DOMAIN2_MASK) #define SRC_DISP_RCR_DOMAIN3_MASK (0x8000000U) #define SRC_DISP_RCR_DOMAIN3_SHIFT (27U) /*! DOMAIN3 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. * 0b1..This register is assigned to domain3. The master from domain3 can write to this register */ #define SRC_DISP_RCR_DOMAIN3(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN3_SHIFT)) & SRC_DISP_RCR_DOMAIN3_MASK) #define SRC_DISP_RCR_LOCK_MASK (0x40000000U) #define SRC_DISP_RCR_LOCK_SHIFT (30U) /*! LOCK * 0b0..[31] and [27:24] bits can be modified * 0b1..[31] and [27:24] bits cannot be modified */ #define SRC_DISP_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_LOCK_SHIFT)) & SRC_DISP_RCR_LOCK_MASK) #define SRC_DISP_RCR_DOM_EN_MASK (0x80000000U) #define SRC_DISP_RCR_DOM_EN_SHIFT (31U) /*! DOM_EN * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by * the masters from the domains specified in [27:24] area. */ #define SRC_DISP_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOM_EN_SHIFT)) & SRC_DISP_RCR_DOM_EN_MASK) /*! @} */ /*! @name GPU_RCR - GPU Reset Control Register */ /*! @{ */ #define SRC_GPU_RCR_GPU_RESET_MASK (0x1U) #define SRC_GPU_RCR_GPU_RESET_SHIFT (0U) #define SRC_GPU_RCR_GPU_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_GPU_RESET_SHIFT)) & SRC_GPU_RCR_GPU_RESET_MASK) #define SRC_GPU_RCR_DOMAIN0_MASK (0x1000000U) #define SRC_GPU_RCR_DOMAIN0_SHIFT (24U) /*! DOMAIN0 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. * 0b1..This register is assigned to domain0. The master from domain3 can write to this register */ #define SRC_GPU_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN0_SHIFT)) & SRC_GPU_RCR_DOMAIN0_MASK) #define SRC_GPU_RCR_DOMAIN1_MASK (0x2000000U) #define SRC_GPU_RCR_DOMAIN1_SHIFT (25U) /*! DOMAIN1 * 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register. * 0b1..This register is assigned to domain1. The master from domain1 can write to this register */ #define SRC_GPU_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN1_SHIFT)) & SRC_GPU_RCR_DOMAIN1_MASK) #define SRC_GPU_RCR_DOMAIN2_MASK (0x4000000U) #define SRC_GPU_RCR_DOMAIN2_SHIFT (26U) /*! DOMAIN2 * 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register. * 0b1..This register is assigned to domain2. The master from domain2 can write to this register */ #define SRC_GPU_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN2_SHIFT)) & SRC_GPU_RCR_DOMAIN2_MASK) #define SRC_GPU_RCR_DOMAIN3_MASK (0x8000000U) #define SRC_GPU_RCR_DOMAIN3_SHIFT (27U) /*! DOMAIN3 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. * 0b1..This register is assigned to domain3. The master from domain3 can write to this register */ #define SRC_GPU_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN3_SHIFT)) & SRC_GPU_RCR_DOMAIN3_MASK) #define SRC_GPU_RCR_LOCK_MASK (0x40000000U) #define SRC_GPU_RCR_LOCK_SHIFT (30U) /*! LOCK * 0b0..[31] and [27:24] bits can be modified * 0b1..[31] and [27:24] bits cannot be modified */ #define SRC_GPU_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_LOCK_SHIFT)) & SRC_GPU_RCR_LOCK_MASK) #define SRC_GPU_RCR_DOM_EN_MASK (0x80000000U) #define SRC_GPU_RCR_DOM_EN_SHIFT (31U) /*! DOM_EN * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by * the masters from the domains specified in [27:24] area. */ #define SRC_GPU_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOM_EN_SHIFT)) & SRC_GPU_RCR_DOM_EN_MASK) /*! @} */ /*! @name SBMR1 - SRC Boot Mode Register 1 */ /*! @{ */ #define SRC_SBMR1_BOOT_CFG_MASK (0xFFFFFU) #define SRC_SBMR1_BOOT_CFG_SHIFT (0U) #define SRC_SBMR1_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG_SHIFT)) & SRC_SBMR1_BOOT_CFG_MASK) /*! @} */ /*! @name SRSR - SRC Reset Status Register */ /*! @{ */ #define SRC_SRSR_ipp_reset_b_MASK (0x1U) #define SRC_SRSR_ipp_reset_b_SHIFT (0U) /*! ipp_reset_b * 0b0..Reset is not a result of ipp_reset_b pin. * 0b1..Reset is a result of ipp_reset_b pin. */ #define SRC_SRSR_ipp_reset_b(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_ipp_reset_b_SHIFT)) & SRC_SRSR_ipp_reset_b_MASK) #define SRC_SRSR_csu_reset_b_MASK (0x4U) #define SRC_SRSR_csu_reset_b_SHIFT (2U) /*! csu_reset_b * 0b0..Reset is not a result of the csu_reset_b event. * 0b1..Reset is a result of the csu_reset_b event. */ #define SRC_SRSR_csu_reset_b(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_csu_reset_b_SHIFT)) & SRC_SRSR_csu_reset_b_MASK) #define SRC_SRSR_ipp_user_reset_b_MASK (0x8U) #define SRC_SRSR_ipp_user_reset_b_SHIFT (3U) /*! ipp_user_reset_b * 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. * 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event. */ #define SRC_SRSR_ipp_user_reset_b(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_ipp_user_reset_b_SHIFT)) & SRC_SRSR_ipp_user_reset_b_MASK) #define SRC_SRSR_wdog1_rst_b_MASK (0x10U) #define SRC_SRSR_wdog1_rst_b_SHIFT (4U) /*! wdog1_rst_b * 0b0..Reset is not a result of the watchdog1 time-out event. * 0b1..Reset is a result of the watchdog1 time-out event. */ #define SRC_SRSR_wdog1_rst_b(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_wdog1_rst_b_SHIFT)) & SRC_SRSR_wdog1_rst_b_MASK) #define SRC_SRSR_jtag_rst_b_MASK (0x20U) #define SRC_SRSR_jtag_rst_b_SHIFT (5U) /*! jtag_rst_b * 0b0..Reset is not a result of HIGH-Z reset from JTAG. * 0b1..Reset is a result of HIGH-Z reset from JTAG. */ #define SRC_SRSR_jtag_rst_b(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_jtag_rst_b_SHIFT)) & SRC_SRSR_jtag_rst_b_MASK) #define SRC_SRSR_jtag_sw_rst_MASK (0x40U) #define SRC_SRSR_jtag_sw_rst_SHIFT (6U) /*! jtag_sw_rst * 0b0..Reset is not a result of software reset from JTAG. * 0b1..Reset is a result of software reset from JTAG. */ #define SRC_SRSR_jtag_sw_rst(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_jtag_sw_rst_SHIFT)) & SRC_SRSR_jtag_sw_rst_MASK) #define SRC_SRSR_wdog3_rst_b_MASK (0x80U) #define SRC_SRSR_wdog3_rst_b_SHIFT (7U) /*! wdog3_rst_b * 0b0..Reset is not a result of the watchdog3 time-out event. * 0b1..Reset is a result of the watchdog3 time-out event. */ #define SRC_SRSR_wdog3_rst_b(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_wdog3_rst_b_SHIFT)) & SRC_SRSR_wdog3_rst_b_MASK) #define SRC_SRSR_wdog2_rst_b_MASK (0x100U) #define SRC_SRSR_wdog2_rst_b_SHIFT (8U) /*! wdog2_rst_b * 0b0..Reset is not a result of the watchdog4 time-out event. * 0b1..Reset is a result of the watchdog4 time-out event. */ #define SRC_SRSR_wdog2_rst_b(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_wdog2_rst_b_SHIFT)) & SRC_SRSR_wdog2_rst_b_MASK) #define SRC_SRSR_tempsense_rst_b_MASK (0x200U) #define SRC_SRSR_tempsense_rst_b_SHIFT (9U) /*! tempsense_rst_b * 0b0..Reset is not a result of software reset from Temperature Sensor. * 0b1..Reset is a result of software reset from Temperature Sensor. */ #define SRC_SRSR_tempsense_rst_b(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_tempsense_rst_b_SHIFT)) & SRC_SRSR_tempsense_rst_b_MASK) /*! @} */ /*! @name SISR - SRC Interrupt Status Register */ /*! @{ */ #define SRC_SISR_OTGPHY1_PASSED_RESET_MASK (0x4U) #define SRC_SISR_OTGPHY1_PASSED_RESET_SHIFT (2U) /*! OTGPHY1_PASSED_RESET * 0b0..Interrupt generated not due to OTG PHY1 passed reset * 0b1..Interrupt generated due to OTG PHY1 passed reset */ #define SRC_SISR_OTGPHY1_PASSED_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SISR_OTGPHY1_PASSED_RESET_SHIFT)) & SRC_SISR_OTGPHY1_PASSED_RESET_MASK) #define SRC_SISR_DISPLAY_PASSED_RESET_MASK (0x80U) #define SRC_SISR_DISPLAY_PASSED_RESET_SHIFT (7U) /*! DISPLAY_PASSED_RESET * 0b0..Interrupt generated not due to DISPLAY passed reset * 0b1..Interrupt generated due to DISPLAY passed reset */ #define SRC_SISR_DISPLAY_PASSED_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SISR_DISPLAY_PASSED_RESET_SHIFT)) & SRC_SISR_DISPLAY_PASSED_RESET_MASK) #define SRC_SISR_M7_PASSED_RESET_MASK (0x100U) #define SRC_SISR_M7_PASSED_RESET_SHIFT (8U) /*! M7_PASSED_RESET * 0b0..interrupt generated not due to m7 reset * 0b1..interrupt generated due to m7 reset */ #define SRC_SISR_M7_PASSED_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SISR_M7_PASSED_RESET_SHIFT)) & SRC_SISR_M7_PASSED_RESET_MASK) #define SRC_SISR_GPU_PASSED_RESET_MASK (0x400U) #define SRC_SISR_GPU_PASSED_RESET_SHIFT (10U) /*! GPU_PASSED_RESET * 0b0..interrupt generated not due to GPU reset * 0b1..interrupt generated due to GPU reset */ #define SRC_SISR_GPU_PASSED_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SISR_GPU_PASSED_RESET_SHIFT)) & SRC_SISR_GPU_PASSED_RESET_MASK) /*! @} */ /*! @name SIMR - SRC Interrupt Mask Register */ /*! @{ */ #define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_MASK (0x4U) #define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_SHIFT (2U) /*! MASK_OTGPHY1_PASSED_RESET * 0b0..do not mask interrupt due to OTG PHY1 passed reset - interrupt will be created * 0b1..mask interrupt due to OTG PHY1 passed reset */ #define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_SHIFT)) & \ SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_MASK) #define SRC_SIMR_MASK_DISPLAY_PASSED_RESET_MASK (0x80U) #define SRC_SIMR_MASK_DISPLAY_PASSED_RESET_SHIFT (7U) /*! MASK_DISPLAY_PASSED_RESET * 0b0..do not mask interrupt due to display passed reset - interrupt will be created * 0b1..mask interrupt due to display passed reset */ #define SRC_SIMR_MASK_DISPLAY_PASSED_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_DISPLAY_PASSED_RESET_SHIFT)) & \ SRC_SIMR_MASK_DISPLAY_PASSED_RESET_MASK) #define SRC_SIMR_MASK_M7_PASSED_RESET_MASK (0x100U) #define SRC_SIMR_MASK_M7_PASSED_RESET_SHIFT (8U) /*! MASK_M7_PASSED_RESET * 0b0..do not mask interrupt due to m7 passed reset - interrupt will be created * 0b1..mask interrupt due to m7 passed reset */ #define SRC_SIMR_MASK_M7_PASSED_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_M7_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_M7_PASSED_RESET_MASK) #define SRC_SIMR_MASK_GPU_PASSED_RESET_MASK (0x400U) #define SRC_SIMR_MASK_GPU_PASSED_RESET_SHIFT (10U) /*! MASK_GPU_PASSED_RESET * 0b0..do not mask interrupt due to GPU passed reset - interrupt will be created * 0b1..mask interrupt due to GPU passed reset */ #define SRC_SIMR_MASK_GPU_PASSED_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_GPU_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_GPU_PASSED_RESET_MASK) /*! @} */ /*! @name SBMR2 - SRC Boot Mode Register 2 */ /*! @{ */ #define SRC_SBMR2_SEC_CONFIG_MASK (0x3U) #define SRC_SBMR2_SEC_CONFIG_SHIFT (0U) #define SRC_SBMR2_SEC_CONFIG(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) #define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U) #define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U) #define SRC_SBMR2_DIR_BT_DIS(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK) #define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U) #define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U) #define SRC_SBMR2_BT_FUSE_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK) #define SRC_SBMR2_FORCE_COLD_BOOT_MASK (0xE0U) #define SRC_SBMR2_FORCE_COLD_BOOT_SHIFT (5U) #define SRC_SBMR2_FORCE_COLD_BOOT(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_FORCE_COLD_BOOT_SHIFT)) & SRC_SBMR2_FORCE_COLD_BOOT_MASK) #define SRC_SBMR2_IPP_BOOT_MODE_MASK (0x3F000000U) #define SRC_SBMR2_IPP_BOOT_MODE_SHIFT (24U) #define SRC_SBMR2_IPP_BOOT_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_IPP_BOOT_MODE_SHIFT)) & SRC_SBMR2_IPP_BOOT_MODE_MASK) /*! @} */ /*! @name GPR1 - SRC General Purpose Register 1 */ /*! @{ */ #define SRC_GPR1_C0_START_ADDRH_MASK (0xFFFFU) #define SRC_GPR1_C0_START_ADDRH_SHIFT (0U) #define SRC_GPR1_C0_START_ADDRH(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_GPR1_C0_START_ADDRH_SHIFT)) & SRC_GPR1_C0_START_ADDRH_MASK) /*! @} */ /*! @name GPR2 - SRC General Purpose Register 2 */ /*! @{ */ #define SRC_GPR2_C0_START_ADDRL_MASK (0x3FFFFFU) #define SRC_GPR2_C0_START_ADDRL_SHIFT (0U) #define SRC_GPR2_C0_START_ADDRL(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_GPR2_C0_START_ADDRL_SHIFT)) & SRC_GPR2_C0_START_ADDRL_MASK) /*! @} */ /*! @name GPR3 - SRC General Purpose Register 3 */ /*! @{ */ #define SRC_GPR3_C1_START_ADDRH_MASK (0xFFFFU) #define SRC_GPR3_C1_START_ADDRH_SHIFT (0U) #define SRC_GPR3_C1_START_ADDRH(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_GPR3_C1_START_ADDRH_SHIFT)) & SRC_GPR3_C1_START_ADDRH_MASK) /*! @} */ /*! @name GPR4 - SRC General Purpose Register 4 */ /*! @{ */ #define SRC_GPR4_C1_START_ADDRL_MASK (0x3FFFFFU) #define SRC_GPR4_C1_START_ADDRL_SHIFT (0U) #define SRC_GPR4_C1_START_ADDRL(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_GPR4_C1_START_ADDRL_SHIFT)) & SRC_GPR4_C1_START_ADDRL_MASK) /*! @} */ /*! @name GPR5 - SRC General Purpose Register 5 */ /*! @{ */ #define SRC_GPR5_C2_START_ADDRH_MASK (0xFFFFU) #define SRC_GPR5_C2_START_ADDRH_SHIFT (0U) #define SRC_GPR5_C2_START_ADDRH(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_GPR5_C2_START_ADDRH_SHIFT)) & SRC_GPR5_C2_START_ADDRH_MASK) /*! @} */ /*! @name GPR6 - SRC General Purpose Register 6 */ /*! @{ */ #define SRC_GPR6_C2_START_ADDRL_MASK (0x3FFFFFU) #define SRC_GPR6_C2_START_ADDRL_SHIFT (0U) #define SRC_GPR6_C2_START_ADDRL(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_GPR6_C2_START_ADDRL_SHIFT)) & SRC_GPR6_C2_START_ADDRL_MASK) /*! @} */ /*! @name GPR7 - SRC General Purpose Register 7 */ /*! @{ */ #define SRC_GPR7_C3_START_ADDRH_MASK (0xFFFFU) #define SRC_GPR7_C3_START_ADDRH_SHIFT (0U) #define SRC_GPR7_C3_START_ADDRH(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_GPR7_C3_START_ADDRH_SHIFT)) & SRC_GPR7_C3_START_ADDRH_MASK) /*! @} */ /*! @name GPR8 - SRC General Purpose Register 8 */ /*! @{ */ #define SRC_GPR8_C3_START_ADDRL_MASK (0x3FFFFFU) #define SRC_GPR8_C3_START_ADDRL_SHIFT (0U) #define SRC_GPR8_C3_START_ADDRL(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_GPR8_C3_START_ADDRL_SHIFT)) & SRC_GPR8_C3_START_ADDRL_MASK) /*! @} */ /*! @name DDRC_RCR - SRC DDR Controller Reset Control Register */ /*! @{ */ #define SRC_DDRC_RCR_DDRC1_PRST_MASK (0x1U) #define SRC_DDRC_RCR_DDRC1_PRST_SHIFT (0U) /*! DDRC1_PRST * 0b0..De-assert DDR Controller preset and DDR PHY reset reset * 0b1..Assert DDR Controller preset and DDR PHY reset */ #define SRC_DDRC_RCR_DDRC1_PRST(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PRST_SHIFT)) & SRC_DDRC_RCR_DDRC1_PRST_MASK) #define SRC_DDRC_RCR_DDRC1_CORE_RST_MASK (0x2U) #define SRC_DDRC_RCR_DDRC1_CORE_RST_SHIFT (1U) /*! DDRC1_CORE_RST * 0b0..De-assert DDR controller aresetn and core_ddrc_rstn * 0b1..Assert DDR Controller preset and DDR PHY reset */ #define SRC_DDRC_RCR_DDRC1_CORE_RST(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_CORE_RST_SHIFT)) & SRC_DDRC_RCR_DDRC1_CORE_RST_MASK) #define SRC_DDRC_RCR_DDRC1_PHY_RESET_MASK (0x4U) #define SRC_DDRC_RCR_DDRC1_PHY_RESET_SHIFT (2U) /*! DDRC1_PHY_RESET * 0b0..De-assert DDR controller * 0b1..Assert DDR Controller */ #define SRC_DDRC_RCR_DDRC1_PHY_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PHY_RESET_SHIFT)) & SRC_DDRC_RCR_DDRC1_PHY_RESET_MASK) #define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_MASK (0x8U) #define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_SHIFT (3U) /*! DDRC1_PHY_PWROKIN * 0b0..De-assert DDR controller * 0b1..Assert DDR Controller */ #define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_SHIFT)) & SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_MASK) #define SRC_DDRC_RCR_DDRC1_SYS_RST_MASK (0x10U) #define SRC_DDRC_RCR_DDRC1_SYS_RST_SHIFT (4U) #define SRC_DDRC_RCR_DDRC1_SYS_RST(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_SYS_RST_SHIFT)) & SRC_DDRC_RCR_DDRC1_SYS_RST_MASK) #define SRC_DDRC_RCR_DDRC1_PHY_WRST_MASK (0x20U) #define SRC_DDRC_RCR_DDRC1_PHY_WRST_SHIFT (5U) #define SRC_DDRC_RCR_DDRC1_PHY_WRST(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PHY_WRST_SHIFT)) & SRC_DDRC_RCR_DDRC1_PHY_WRST_MASK) #define SRC_DDRC_RCR_DOMAIN0_MASK (0x1000000U) #define SRC_DDRC_RCR_DOMAIN0_SHIFT (24U) /*! DOMAIN0 * 0b0..This register is not assigned to domain0. The master from domain0 cannot write to this register. * 0b1..This register is assigned to domain0. The master from domain0 can write to this register */ #define SRC_DDRC_RCR_DOMAIN0(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN0_SHIFT)) & SRC_DDRC_RCR_DOMAIN0_MASK) #define SRC_DDRC_RCR_DOMAIN1_MASK (0x2000000U) #define SRC_DDRC_RCR_DOMAIN1_SHIFT (25U) /*! DOMAIN1 * 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register. * 0b1..This register is assigned to domain1. The master from domain1 can write to this register */ #define SRC_DDRC_RCR_DOMAIN1(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN1_SHIFT)) & SRC_DDRC_RCR_DOMAIN1_MASK) #define SRC_DDRC_RCR_DOMAIN2_MASK (0x4000000U) #define SRC_DDRC_RCR_DOMAIN2_SHIFT (26U) /*! DOMAIN2 * 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register. * 0b1..This register is assigned to domain2. The master from domain2 can write to this register */ #define SRC_DDRC_RCR_DOMAIN2(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN2_SHIFT)) & SRC_DDRC_RCR_DOMAIN2_MASK) #define SRC_DDRC_RCR_DOMAIN3_MASK (0x8000000U) #define SRC_DDRC_RCR_DOMAIN3_SHIFT (27U) /*! DOMAIN3 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. * 0b1..This register is assigned to domain3. The master from domain3 can write to this register */ #define SRC_DDRC_RCR_DOMAIN3(x) \ (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN3_SHIFT)) & SRC_DDRC_RCR_DOMAIN3_MASK) #define SRC_DDRC_RCR_LOCK_MASK (0x40000000U) #define SRC_DDRC_RCR_LOCK_SHIFT (30U) /*! LOCK * 0b0..[31] and [27:24] bits can be modified * 0b1..[31] and [27:24] bits cannot be modified */ #define SRC_DDRC_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_LOCK_SHIFT)) & SRC_DDRC_RCR_LOCK_MASK) #define SRC_DDRC_RCR_DOM_EN_MASK (0x80000000U) #define SRC_DDRC_RCR_DOM_EN_SHIFT (31U) /*! DOM_EN * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by * the masters from the domains specified in [27:24] area. */ #define SRC_DDRC_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOM_EN_SHIFT)) & SRC_DDRC_RCR_DOM_EN_MASK) /*! @} */ /*! * @} */ /* end of group SRC_Register_Masks */ /* SRC - Peripheral instance base addresses */ /** Peripheral SRC base address */ #define SRC_BASE (0x30390000u) /** Peripheral SRC base pointer */ #define SRC ((SRC_Type *)SRC_BASE) /** Array initializer of SRC peripheral base addresses */ #define SRC_BASE_ADDRS \ { \ SRC_BASE \ } /** Array initializer of SRC peripheral base pointers */ #define SRC_BASE_PTRS \ { \ SRC \ } /*! * @} */ /* end of group SRC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- TMU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup TMU_Peripheral_Access_Layer TMU Peripheral Access Layer * @{ */ /** TMU - Register Layout Typedef */ typedef struct { __IO uint32_t TER; /**< TMU Enable Register, offset: 0x0 */ __I uint32_t TSR; /**< TMU Status register, offset: 0x4 */ __IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ __IO uint32_t TIDR; /**< TMU Interrupt Detect register, offset: 0xC */ __IO uint32_t TMHTITR; /**< TMU Monitor High Temperature Immediate Threshold register, offset: 0x10 */ __IO uint32_t TMHTATR; /**< TMU Monitor High Temperature Average threshold register, offset: 0x14 */ __IO uint32_t TMHTACTR; /**< TMU Monitor High Temperature Average Critical Threshold register, offset: 0x18 */ __I uint32_t TSCR; /**< TMU Sensor Calibration register, offset: 0x1C */ __I uint32_t TRITSR; /**< TMU Report Immediate Temperature Site register n, offset: 0x20 */ __I uint32_t TRATSR; /**< TMU Report Average Temperature Site register n, offset: 0x24 */ } TMU_Type; /* ---------------------------------------------------------------------------- -- TMU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup TMU_Register_Masks TMU Register Masks * @{ */ /*! @name TER - TMU Enable Register */ /*! @{ */ #define TMU_TER_ALPF_MASK (0x3U) #define TMU_TER_ALPF_SHIFT (0U) /*! ALPF * 0b00..1.0 * 0b01..0.5 * 0b10..0.25 * 0b11..0.125 */ #define TMU_TER_ALPF(x) (((uint32_t)(((uint32_t)(x)) << TMU_TER_ALPF_SHIFT)) & TMU_TER_ALPF_MASK) #define TMU_TER_EN_MASK (0x80000000U) #define TMU_TER_EN_SHIFT (31U) /*! EN * 0b0..No monitoring * 0b1..Enable monitoring */ #define TMU_TER_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TER_EN_SHIFT)) & TMU_TER_EN_MASK) /*! @} */ /*! @name TSR - TMU Status register */ /*! @{ */ #define TMU_TSR_TB_MASK (0x80000000U) #define TMU_TSR_TB_SHIFT (31U) /*! TB * 0b0..TMU idle. * 0b1..TMU busy. In monitoring mode this indicates a temperature measurement is pending. In calibration mode, * sensor result has not yet been determined based on last given ambient temperature. */ #define TMU_TSR_TB(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_TB_SHIFT)) & TMU_TSR_TB_MASK) /*! @} */ /*! @name TIER - TMU Interrupt Enable register */ /*! @{ */ #define TMU_TIER_ATCTEIE_MASK (0x20000000U) #define TMU_TIER_ATCTEIE_SHIFT (29U) /*! ATCTEIE * 0b0..Disabled. * 0b1..Interrupt enabled. Generate an interrupt if TIDR[ATCTE] is set. Write 1 to this bit will clear bit TIDR[ATCTE]. */ #define TMU_TIER_ATCTEIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ATCTEIE_SHIFT)) & TMU_TIER_ATCTEIE_MASK) #define TMU_TIER_ATTEIE_MASK (0x40000000U) #define TMU_TIER_ATTEIE_SHIFT (30U) /*! ATTEIE * 0b0..Disabled. * 0b1..Interrupt enabled. Generate an interrupt if TIDR[ATTE] is set. Write 1 to this bit will clear bit TIDR[ATTE]. */ #define TMU_TIER_ATTEIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ATTEIE_SHIFT)) & TMU_TIER_ATTEIE_MASK) #define TMU_TIER_ITTEIE_MASK (0x80000000U) #define TMU_TIER_ITTEIE_SHIFT (31U) /*! ITTEIE * 0b0..Disabled. * 0b1..Interrupt enabled. Generate an interrupt if TIDR[ITTE] is set. Write 1 to this bit will clear bit TIDR[ITTE]. */ #define TMU_TIER_ITTEIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ITTEIE_SHIFT)) & TMU_TIER_ITTEIE_MASK) /*! @} */ /*! @name TIDR - TMU Interrupt Detect register */ /*! @{ */ #define TMU_TIDR_ATCTE_MASK (0x10000000U) #define TMU_TIDR_ATCTE_SHIFT (28U) /*! ATCTE * 0b0..No threshold exceeded. * 0b1..Average temperature critical threshold, as defined by TMHTACTR, has been exceeded. */ #define TMU_TIDR_ATCTE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ATCTE_SHIFT)) & TMU_TIDR_ATCTE_MASK) #define TMU_TIDR_ATTE_MASK (0x20000000U) #define TMU_TIDR_ATTE_SHIFT (29U) /*! ATTE * 0b0..No threshold exceeded. * 0b1..Average temperature threshold, as defined by TMHTATR, has been exceeded. */ #define TMU_TIDR_ATTE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ATTE_SHIFT)) & TMU_TIDR_ATTE_MASK) #define TMU_TIDR_ITTE_MASK (0x40000000U) #define TMU_TIDR_ITTE_SHIFT (30U) /*! ITTE * 0b0..No threshold exceeded. * 0b1..Immediate temperature threshold, as defined by TMHTITR, has been exceeded. This includes an out-of-range * measured temperature above 125degree C. */ #define TMU_TIDR_ITTE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ITTE_SHIFT)) & TMU_TIDR_ITTE_MASK) /*! @} */ /*! @name TMHTITR - TMU Monitor High Temperature Immediate Threshold register */ /*! @{ */ #define TMU_TMHTITR_TEMP_MASK (0xFFU) #define TMU_TMHTITR_TEMP_SHIFT (0U) #define TMU_TMHTITR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_TEMP_SHIFT)) & TMU_TMHTITR_TEMP_MASK) #define TMU_TMHTITR_EN_MASK (0x80000000U) #define TMU_TMHTITR_EN_SHIFT (31U) /*! EN * 0b0..Disabled. * 0b1..Threshold enabled. */ #define TMU_TMHTITR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_EN_SHIFT)) & TMU_TMHTITR_EN_MASK) /*! @} */ /*! @name TMHTATR - TMU Monitor High Temperature Average threshold register */ /*! @{ */ #define TMU_TMHTATR_TEMP_MASK (0xFFU) #define TMU_TMHTATR_TEMP_SHIFT (0U) #define TMU_TMHTATR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_TEMP_SHIFT)) & TMU_TMHTATR_TEMP_MASK) #define TMU_TMHTATR_EN_MASK (0x80000000U) #define TMU_TMHTATR_EN_SHIFT (31U) /*! EN * 0b0..Disabled. * 0b1..Threshold enabled. */ #define TMU_TMHTATR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_EN_SHIFT)) & TMU_TMHTATR_EN_MASK) /*! @} */ /*! @name TMHTACTR - TMU Monitor High Temperature Average Critical Threshold register */ /*! @{ */ #define TMU_TMHTACTR_TEMP_MASK (0xFFU) #define TMU_TMHTACTR_TEMP_SHIFT (0U) #define TMU_TMHTACTR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_TEMP_SHIFT)) & TMU_TMHTACTR_TEMP_MASK) #define TMU_TMHTACTR_EN_MASK (0x80000000U) #define TMU_TMHTACTR_EN_SHIFT (31U) /*! EN * 0b0..Disabled. * 0b1..Threshold enabled. */ #define TMU_TMHTACTR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_EN_SHIFT)) & TMU_TMHTACTR_EN_MASK) /*! @} */ /*! @name TSCR - TMU Sensor Calibration register */ /*! @{ */ #define TMU_TSCR_SENSOR_MASK (0xFFU) #define TMU_TSCR_SENSOR_SHIFT (0U) #define TMU_TSCR_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSCR_SENSOR_SHIFT)) & TMU_TSCR_SENSOR_MASK) #define TMU_TSCR_BSR_MASK (0x80000000U) #define TMU_TSCR_BSR_SHIFT (31U) #define TMU_TSCR_BSR(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSCR_BSR_SHIFT)) & TMU_TSCR_BSR_MASK) /*! @} */ /*! @name TRITSR - TMU Report Immediate Temperature Site register n */ /*! @{ */ #define TMU_TRITSR_TEMP_MASK (0xFFU) #define TMU_TRITSR_TEMP_SHIFT (0U) #define TMU_TRITSR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_TEMP_SHIFT)) & TMU_TRITSR_TEMP_MASK) #define TMU_TRITSR_V_MASK (0x80000000U) #define TMU_TRITSR_V_SHIFT (31U) /*! V * 0b0..Not valid. Temperature out of sensor range or first measurement still pending. * 0b1..Valid. */ #define TMU_TRITSR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_V_SHIFT)) & TMU_TRITSR_V_MASK) /*! @} */ /*! @name TRATSR - TMU Report Average Temperature Site register n */ /*! @{ */ #define TMU_TRATSR_TEMP_MASK (0xFFU) #define TMU_TRATSR_TEMP_SHIFT (0U) #define TMU_TRATSR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_TEMP_SHIFT)) & TMU_TRATSR_TEMP_MASK) #define TMU_TRATSR_V_MASK (0x80000000U) #define TMU_TRATSR_V_SHIFT (31U) /*! V * 0b0..Not valid. Temperature out of sensor range or first measurement still pending. * 0b1..Valid. */ #define TMU_TRATSR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_V_SHIFT)) & TMU_TRATSR_V_MASK) /*! @} */ /*! * @} */ /* end of group TMU_Register_Masks */ /* TMU - Peripheral instance base addresses */ /** Peripheral TMU base address */ #define TMU_BASE (0x30260000u) /** Peripheral TMU base pointer */ #define TMU ((TMU_Type *)TMU_BASE) /** Array initializer of TMU peripheral base addresses */ #define TMU_BASE_ADDRS \ { \ TMU_BASE \ } /** Array initializer of TMU peripheral base pointers */ #define TMU_BASE_PTRS \ { \ TMU \ } /*! * @} */ /* end of group TMU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- UART Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer * @{ */ /** UART - Register Layout Typedef */ typedef struct { __I uint32_t URXD; /**< UART Receiver Register, offset: 0x0 */ uint8_t RESERVED_0[60]; __O uint32_t UTXD; /**< UART Transmitter Register, offset: 0x40 */ uint8_t RESERVED_1[60]; __IO uint32_t UCR1; /**< UART Control Register 1, offset: 0x80 */ __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ __IO uint32_t UCR3; /**< UART Control Register 3, offset: 0x88 */ __IO uint32_t UCR4; /**< UART Control Register 4, offset: 0x8C */ __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ __IO uint32_t USR1; /**< UART Status Register 1, offset: 0x94 */ __IO uint32_t USR2; /**< UART Status Register 2, offset: 0x98 */ __IO uint32_t UESC; /**< UART Escape Character Register, offset: 0x9C */ __IO uint32_t UTIM; /**< UART Escape Timer Register, offset: 0xA0 */ __IO uint32_t UBIR; /**< UART BRM Incremental Register, offset: 0xA4 */ __IO uint32_t UBMR; /**< UART BRM Modulator Register, offset: 0xA8 */ __I uint32_t UBRC; /**< UART Baud Rate Count Register, offset: 0xAC */ __IO uint32_t ONEMS; /**< UART One Millisecond Register, offset: 0xB0 */ __IO uint32_t UTS; /**< UART Test Register, offset: 0xB4 */ __IO uint32_t UMCR; /**< UART RS-485 Mode Control Register, offset: 0xB8 */ } UART_Type; /* ---------------------------------------------------------------------------- -- UART Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup UART_Register_Masks UART Register Masks * @{ */ /*! @name URXD - UART Receiver Register */ /*! @{ */ #define UART_URXD_RX_DATA_MASK (0xFFU) #define UART_URXD_RX_DATA_SHIFT (0U) #define UART_URXD_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_RX_DATA_SHIFT)) & UART_URXD_RX_DATA_MASK) #define UART_URXD_PRERR_MASK (0x400U) #define UART_URXD_PRERR_SHIFT (10U) /*! PRERR * 0b0..= No parity error was detected for data in the RX_DATA field * 0b1..= A parity error was detected for data in the RX_DATA field */ #define UART_URXD_PRERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_PRERR_SHIFT)) & UART_URXD_PRERR_MASK) #define UART_URXD_BRK_MASK (0x800U) #define UART_URXD_BRK_SHIFT (11U) /*! BRK * 0b0..The current character is not a BREAK character * 0b1..The current character is a BREAK character */ #define UART_URXD_BRK(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_BRK_SHIFT)) & UART_URXD_BRK_MASK) #define UART_URXD_FRMERR_MASK (0x1000U) #define UART_URXD_FRMERR_SHIFT (12U) /*! FRMERR * 0b0..The current character has no framing error * 0b1..The current character has a framing error */ #define UART_URXD_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_FRMERR_SHIFT)) & UART_URXD_FRMERR_MASK) #define UART_URXD_OVRRUN_MASK (0x2000U) #define UART_URXD_OVRRUN_SHIFT (13U) /*! OVRRUN * 0b0..No RxFIFO overrun was detected * 0b1..A RxFIFO overrun was detected */ #define UART_URXD_OVRRUN(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_OVRRUN_SHIFT)) & UART_URXD_OVRRUN_MASK) #define UART_URXD_ERR_MASK (0x4000U) #define UART_URXD_ERR_SHIFT (14U) /*! ERR * 0b0..No error status was detected * 0b1..An error status was detected */ #define UART_URXD_ERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_ERR_SHIFT)) & UART_URXD_ERR_MASK) #define UART_URXD_CHARRDY_MASK (0x8000U) #define UART_URXD_CHARRDY_SHIFT (15U) /*! CHARRDY * 0b0..Character in RX_DATA field and associated flags are invalid. * 0b1..Character in RX_DATA field and associated flags valid and ready for reading. */ #define UART_URXD_CHARRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_CHARRDY_SHIFT)) & UART_URXD_CHARRDY_MASK) /*! @} */ /*! @name UTXD - UART Transmitter Register */ /*! @{ */ #define UART_UTXD_TX_DATA_MASK (0xFFU) #define UART_UTXD_TX_DATA_SHIFT (0U) #define UART_UTXD_TX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_UTXD_TX_DATA_SHIFT)) & UART_UTXD_TX_DATA_MASK) /*! @} */ /*! @name UCR1 - UART Control Register 1 */ /*! @{ */ #define UART_UCR1_UARTEN_MASK (0x1U) #define UART_UCR1_UARTEN_SHIFT (0U) /*! UARTEN * 0b0..Disable the UART * 0b1..Enable the UART */ #define UART_UCR1_UARTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_UARTEN_SHIFT)) & UART_UCR1_UARTEN_MASK) #define UART_UCR1_DOZE_MASK (0x2U) #define UART_UCR1_DOZE_SHIFT (1U) /*! DOZE * 0b0..The UART is enabled when in DOZE state * 0b1..The UART is disabled when in DOZE state */ #define UART_UCR1_DOZE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_DOZE_SHIFT)) & UART_UCR1_DOZE_MASK) #define UART_UCR1_ATDMAEN_MASK (0x4U) #define UART_UCR1_ATDMAEN_SHIFT (2U) /*! ATDMAEN * 0b0..Disable AGTIM DMA request * 0b1..Enable AGTIM DMA request */ #define UART_UCR1_ATDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ATDMAEN_SHIFT)) & UART_UCR1_ATDMAEN_MASK) #define UART_UCR1_TXDMAEN_MASK (0x8U) #define UART_UCR1_TXDMAEN_SHIFT (3U) /*! TXDMAEN * 0b0..Disable transmit DMA request * 0b1..Enable transmit DMA request */ #define UART_UCR1_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXDMAEN_SHIFT)) & UART_UCR1_TXDMAEN_MASK) #define UART_UCR1_SNDBRK_MASK (0x10U) #define UART_UCR1_SNDBRK_SHIFT (4U) /*! SNDBRK * 0b0..Do not send a BREAK character * 0b1..Send a BREAK character (continuous 0s) */ #define UART_UCR1_SNDBRK(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_SNDBRK_SHIFT)) & UART_UCR1_SNDBRK_MASK) #define UART_UCR1_RTSDEN_MASK (0x20U) #define UART_UCR1_RTSDEN_SHIFT (5U) /*! RTSDEN * 0b0..Disable RTSD interrupt * 0b1..Enable RTSD interrupt */ #define UART_UCR1_RTSDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RTSDEN_SHIFT)) & UART_UCR1_RTSDEN_MASK) #define UART_UCR1_TXMPTYEN_MASK (0x40U) #define UART_UCR1_TXMPTYEN_SHIFT (6U) /*! TXMPTYEN * 0b0..Disable the transmitter FIFO empty interrupt * 0b1..Enable the transmitter FIFO empty interrupt */ #define UART_UCR1_TXMPTYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXMPTYEN_SHIFT)) & UART_UCR1_TXMPTYEN_MASK) #define UART_UCR1_IREN_MASK (0x80U) #define UART_UCR1_IREN_SHIFT (7U) /*! IREN * 0b0..Disable the IR interface * 0b1..Enable the IR interface */ #define UART_UCR1_IREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IREN_SHIFT)) & UART_UCR1_IREN_MASK) #define UART_UCR1_RXDMAEN_MASK (0x100U) #define UART_UCR1_RXDMAEN_SHIFT (8U) /*! RXDMAEN * 0b0..Disable DMA request * 0b1..Enable DMA request */ #define UART_UCR1_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RXDMAEN_SHIFT)) & UART_UCR1_RXDMAEN_MASK) #define UART_UCR1_RRDYEN_MASK (0x200U) #define UART_UCR1_RRDYEN_SHIFT (9U) /*! RRDYEN * 0b0..Disables the RRDY interrupt * 0b1..Enables the RRDY interrupt */ #define UART_UCR1_RRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RRDYEN_SHIFT)) & UART_UCR1_RRDYEN_MASK) #define UART_UCR1_ICD_MASK (0xC00U) #define UART_UCR1_ICD_SHIFT (10U) /*! ICD * 0b00..Idle for more than 4 frames * 0b01..Idle for more than 8 frames * 0b10..Idle for more than 16 frames * 0b11..Idle for more than 32 frames */ #define UART_UCR1_ICD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ICD_SHIFT)) & UART_UCR1_ICD_MASK) #define UART_UCR1_IDEN_MASK (0x1000U) #define UART_UCR1_IDEN_SHIFT (12U) /*! IDEN * 0b0..Disable the IDLE interrupt * 0b1..Enable the IDLE interrupt */ #define UART_UCR1_IDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IDEN_SHIFT)) & UART_UCR1_IDEN_MASK) #define UART_UCR1_TRDYEN_MASK (0x2000U) #define UART_UCR1_TRDYEN_SHIFT (13U) /*! TRDYEN * 0b0..Disable the transmitter ready interrupt * 0b1..Enable the transmitter ready interrupt */ #define UART_UCR1_TRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TRDYEN_SHIFT)) & UART_UCR1_TRDYEN_MASK) #define UART_UCR1_ADBR_MASK (0x4000U) #define UART_UCR1_ADBR_SHIFT (14U) /*! ADBR * 0b0..Disable automatic detection of baud rate * 0b1..Enable automatic detection of baud rate */ #define UART_UCR1_ADBR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADBR_SHIFT)) & UART_UCR1_ADBR_MASK) #define UART_UCR1_ADEN_MASK (0x8000U) #define UART_UCR1_ADEN_SHIFT (15U) /*! ADEN * 0b0..Disable the automatic baud rate detection interrupt * 0b1..Enable the automatic baud rate detection interrupt */ #define UART_UCR1_ADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADEN_SHIFT)) & UART_UCR1_ADEN_MASK) /*! @} */ /*! @name UCR2 - UART Control Register 2 */ /*! @{ */ #define UART_UCR2_SRST_MASK (0x1U) #define UART_UCR2_SRST_SHIFT (0U) /*! SRST * 0b0..Reset the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD * and UTS[6-3]. 0b1..No reset */ #define UART_UCR2_SRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_SRST_SHIFT)) & UART_UCR2_SRST_MASK) #define UART_UCR2_RXEN_MASK (0x2U) #define UART_UCR2_RXEN_SHIFT (1U) /*! RXEN * 0b0..Disable the receiver * 0b1..Enable the receiver */ #define UART_UCR2_RXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RXEN_SHIFT)) & UART_UCR2_RXEN_MASK) #define UART_UCR2_TXEN_MASK (0x4U) #define UART_UCR2_TXEN_SHIFT (2U) /*! TXEN * 0b0..Disable the transmitter * 0b1..Enable the transmitter */ #define UART_UCR2_TXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_TXEN_SHIFT)) & UART_UCR2_TXEN_MASK) #define UART_UCR2_ATEN_MASK (0x8U) #define UART_UCR2_ATEN_SHIFT (3U) /*! ATEN * 0b0..AGTIM interrupt disabled * 0b1..AGTIM interrupt enabled */ #define UART_UCR2_ATEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ATEN_SHIFT)) & UART_UCR2_ATEN_MASK) #define UART_UCR2_RTSEN_MASK (0x10U) #define UART_UCR2_RTSEN_SHIFT (4U) /*! RTSEN * 0b0..Disable request to send interrupt * 0b1..Enable request to send interrupt */ #define UART_UCR2_RTSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTSEN_SHIFT)) & UART_UCR2_RTSEN_MASK) #define UART_UCR2_WS_MASK (0x20U) #define UART_UCR2_WS_SHIFT (5U) /*! WS * 0b0..7-bit transmit and receive character length (not including START, STOP or PARITY bits) * 0b1..8-bit transmit and receive character length (not including START, STOP or PARITY bits) */ #define UART_UCR2_WS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_WS_SHIFT)) & UART_UCR2_WS_MASK) #define UART_UCR2_STPB_MASK (0x40U) #define UART_UCR2_STPB_SHIFT (6U) /*! STPB * 0b0..The transmitter sends 1 stop bit. The receiver expects 1 or more stop bits. * 0b1..The transmitter sends 2 stop bits. The receiver expects 2 or more stop bits. */ #define UART_UCR2_STPB(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_STPB_SHIFT)) & UART_UCR2_STPB_MASK) #define UART_UCR2_PROE_MASK (0x80U) #define UART_UCR2_PROE_SHIFT (7U) /*! PROE * 0b0..Even parity * 0b1..Odd parity */ #define UART_UCR2_PROE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PROE_SHIFT)) & UART_UCR2_PROE_MASK) #define UART_UCR2_PREN_MASK (0x100U) #define UART_UCR2_PREN_SHIFT (8U) /*! PREN * 0b0..Disable parity generator and checker * 0b1..Enable parity generator and checker */ #define UART_UCR2_PREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PREN_SHIFT)) & UART_UCR2_PREN_MASK) #define UART_UCR2_RTEC_MASK (0x600U) #define UART_UCR2_RTEC_SHIFT (9U) /*! RTEC * 0b00..Trigger interrupt on a rising edge * 0b01..Trigger interrupt on a falling edge * 0b1x..Trigger interrupt on any edge */ #define UART_UCR2_RTEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTEC_SHIFT)) & UART_UCR2_RTEC_MASK) #define UART_UCR2_ESCEN_MASK (0x800U) #define UART_UCR2_ESCEN_SHIFT (11U) /*! ESCEN * 0b0..Disable escape sequence detection * 0b1..Enable escape sequence detection */ #define UART_UCR2_ESCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCEN_SHIFT)) & UART_UCR2_ESCEN_MASK) #define UART_UCR2_CTS_MASK (0x1000U) #define UART_UCR2_CTS_SHIFT (12U) /*! CTS * 0b0..The CTS_B pin is high (inactive) * 0b1..The CTS_B pin is low (active) */ #define UART_UCR2_CTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTS_SHIFT)) & UART_UCR2_CTS_MASK) #define UART_UCR2_CTSC_MASK (0x2000U) #define UART_UCR2_CTSC_SHIFT (13U) /*! CTSC * 0b0..The CTS_B pin is controlled by the CTS bit * 0b1..The CTS_B pin is controlled by the receiver */ #define UART_UCR2_CTSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTSC_SHIFT)) & UART_UCR2_CTSC_MASK) #define UART_UCR2_IRTS_MASK (0x4000U) #define UART_UCR2_IRTS_SHIFT (14U) /*! IRTS * 0b0..Transmit only when the RTS pin is asserted * 0b1..Ignore the RTS pin */ #define UART_UCR2_IRTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_IRTS_SHIFT)) & UART_UCR2_IRTS_MASK) #define UART_UCR2_ESCI_MASK (0x8000U) #define UART_UCR2_ESCI_SHIFT (15U) /*! ESCI * 0b0..Disable the escape sequence interrupt * 0b1..Enable the escape sequence interrupt */ #define UART_UCR2_ESCI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCI_SHIFT)) & UART_UCR2_ESCI_MASK) /*! @} */ /*! @name UCR3 - UART Control Register 3 */ /*! @{ */ #define UART_UCR3_ACIEN_MASK (0x1U) #define UART_UCR3_ACIEN_SHIFT (0U) /*! ACIEN * 0b0..ACST interrupt disabled * 0b1..ACST interrupt enabled */ #define UART_UCR3_ACIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ACIEN_SHIFT)) & UART_UCR3_ACIEN_MASK) #define UART_UCR3_INVT_MASK (0x2U) #define UART_UCR3_INVT_SHIFT (1U) /*! INVT * 0b0..TXD is not inverted * 0b1..TXD is inverted * 0b0..TXD Active low transmission * 0b1..TXD Active high transmission */ #define UART_UCR3_INVT(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_INVT_SHIFT)) & UART_UCR3_INVT_MASK) #define UART_UCR3_RXDMUXSEL_MASK (0x4U) #define UART_UCR3_RXDMUXSEL_SHIFT (2U) #define UART_UCR3_RXDMUXSEL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDMUXSEL_SHIFT)) & UART_UCR3_RXDMUXSEL_MASK) #define UART_UCR3_DTRDEN_MASK (0x8U) #define UART_UCR3_DTRDEN_SHIFT (3U) #define UART_UCR3_DTRDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTRDEN_SHIFT)) & UART_UCR3_DTRDEN_MASK) #define UART_UCR3_AWAKEN_MASK (0x10U) #define UART_UCR3_AWAKEN_SHIFT (4U) /*! AWAKEN * 0b0..Disable the AWAKE interrupt * 0b1..Enable the AWAKE interrupt */ #define UART_UCR3_AWAKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AWAKEN_SHIFT)) & UART_UCR3_AWAKEN_MASK) #define UART_UCR3_AIRINTEN_MASK (0x20U) #define UART_UCR3_AIRINTEN_SHIFT (5U) /*! AIRINTEN * 0b0..Disable the AIRINT interrupt * 0b1..Enable the AIRINT interrupt */ #define UART_UCR3_AIRINTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AIRINTEN_SHIFT)) & UART_UCR3_AIRINTEN_MASK) #define UART_UCR3_RXDSEN_MASK (0x40U) #define UART_UCR3_RXDSEN_SHIFT (6U) /*! RXDSEN * 0b0..Disable the RXDS interrupt * 0b1..Enable the RXDS interrupt */ #define UART_UCR3_RXDSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDSEN_SHIFT)) & UART_UCR3_RXDSEN_MASK) #define UART_UCR3_ADNIMP_MASK (0x80U) #define UART_UCR3_ADNIMP_SHIFT (7U) /*! ADNIMP * 0b0..Autobaud detection new features selected * 0b1..Keep old autobaud detection mechanism */ #define UART_UCR3_ADNIMP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ADNIMP_SHIFT)) & UART_UCR3_ADNIMP_MASK) #define UART_UCR3_RI_MASK (0x100U) #define UART_UCR3_RI_SHIFT (8U) #define UART_UCR3_RI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RI_SHIFT)) & UART_UCR3_RI_MASK) #define UART_UCR3_DCD_MASK (0x200U) #define UART_UCR3_DCD_SHIFT (9U) #define UART_UCR3_DCD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DCD_SHIFT)) & UART_UCR3_DCD_MASK) #define UART_UCR3_DSR_MASK (0x400U) #define UART_UCR3_DSR_SHIFT (10U) #define UART_UCR3_DSR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DSR_SHIFT)) & UART_UCR3_DSR_MASK) #define UART_UCR3_FRAERREN_MASK (0x800U) #define UART_UCR3_FRAERREN_SHIFT (11U) /*! FRAERREN * 0b0..Disable the frame error interrupt * 0b1..Enable the frame error interrupt */ #define UART_UCR3_FRAERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_FRAERREN_SHIFT)) & UART_UCR3_FRAERREN_MASK) #define UART_UCR3_PARERREN_MASK (0x1000U) #define UART_UCR3_PARERREN_SHIFT (12U) /*! PARERREN * 0b0..Disable the parity error interrupt * 0b1..Enable the parity error interrupt */ #define UART_UCR3_PARERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_PARERREN_SHIFT)) & UART_UCR3_PARERREN_MASK) #define UART_UCR3_DTREN_MASK (0x2000U) #define UART_UCR3_DTREN_SHIFT (13U) #define UART_UCR3_DTREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTREN_SHIFT)) & UART_UCR3_DTREN_MASK) #define UART_UCR3_DPEC_MASK (0xC000U) #define UART_UCR3_DPEC_SHIFT (14U) #define UART_UCR3_DPEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DPEC_SHIFT)) & UART_UCR3_DPEC_MASK) /*! @} */ /*! @name UCR4 - UART Control Register 4 */ /*! @{ */ #define UART_UCR4_DREN_MASK (0x1U) #define UART_UCR4_DREN_SHIFT (0U) /*! DREN * 0b0..Disable RDR interrupt * 0b1..Enable RDR interrupt */ #define UART_UCR4_DREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_DREN_SHIFT)) & UART_UCR4_DREN_MASK) #define UART_UCR4_OREN_MASK (0x2U) #define UART_UCR4_OREN_SHIFT (1U) /*! OREN * 0b0..Disable ORE interrupt * 0b1..Enable ORE interrupt */ #define UART_UCR4_OREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_OREN_SHIFT)) & UART_UCR4_OREN_MASK) #define UART_UCR4_BKEN_MASK (0x4U) #define UART_UCR4_BKEN_SHIFT (2U) /*! BKEN * 0b0..Disable the BRCD interrupt * 0b1..Enable the BRCD interrupt */ #define UART_UCR4_BKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_BKEN_SHIFT)) & UART_UCR4_BKEN_MASK) #define UART_UCR4_TCEN_MASK (0x8U) #define UART_UCR4_TCEN_SHIFT (3U) /*! TCEN * 0b0..Disable TXDC interrupt * 0b1..Enable TXDC interrupt */ #define UART_UCR4_TCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_TCEN_SHIFT)) & UART_UCR4_TCEN_MASK) #define UART_UCR4_LPBYP_MASK (0x10U) #define UART_UCR4_LPBYP_SHIFT (4U) /*! LPBYP * 0b0..Low power features enabled * 0b1..Low power features disabled */ #define UART_UCR4_LPBYP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_LPBYP_SHIFT)) & UART_UCR4_LPBYP_MASK) #define UART_UCR4_IRSC_MASK (0x20U) #define UART_UCR4_IRSC_SHIFT (5U) /*! IRSC * 0b0..The vote logic uses the sampling clock (16x baud rate) for normal operation * 0b1..The vote logic uses the UART reference clock */ #define UART_UCR4_IRSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IRSC_SHIFT)) & UART_UCR4_IRSC_MASK) #define UART_UCR4_IDDMAEN_MASK (0x40U) #define UART_UCR4_IDDMAEN_SHIFT (6U) /*! IDDMAEN * 0b0..DMA IDLE interrupt disabled * 0b1..DMA IDLE interrupt enabled */ #define UART_UCR4_IDDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IDDMAEN_SHIFT)) & UART_UCR4_IDDMAEN_MASK) #define UART_UCR4_WKEN_MASK (0x80U) #define UART_UCR4_WKEN_SHIFT (7U) /*! WKEN * 0b0..Disable the WAKE interrupt * 0b1..Enable the WAKE interrupt */ #define UART_UCR4_WKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_WKEN_SHIFT)) & UART_UCR4_WKEN_MASK) #define UART_UCR4_ENIRI_MASK (0x100U) #define UART_UCR4_ENIRI_SHIFT (8U) /*! ENIRI * 0b0..Serial infrared Interrupt disabled * 0b1..Serial infrared Interrupt enabled */ #define UART_UCR4_ENIRI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_ENIRI_SHIFT)) & UART_UCR4_ENIRI_MASK) #define UART_UCR4_INVR_MASK (0x200U) #define UART_UCR4_INVR_SHIFT (9U) /*! INVR * 0b0..RXD input is not inverted * 0b1..RXD input is inverted * 0b0..RXD active low detection * 0b1..RXD active high detection */ #define UART_UCR4_INVR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_INVR_SHIFT)) & UART_UCR4_INVR_MASK) #define UART_UCR4_CTSTL_MASK (0xFC00U) #define UART_UCR4_CTSTL_SHIFT (10U) /*! CTSTL * 0b000000..0 characters received * 0b000001..1 characters in the RxFIFO * 0b100000..32 characters in the RxFIFO (maximum) */ #define UART_UCR4_CTSTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_CTSTL_SHIFT)) & UART_UCR4_CTSTL_MASK) /*! @} */ /*! @name UFCR - UART FIFO Control Register */ /*! @{ */ #define UART_UFCR_RXTL_MASK (0x3FU) #define UART_UFCR_RXTL_SHIFT (0U) /*! RXTL * 0b000000..0 characters received * 0b000001..RxFIFO has 1 character * 0b011111..RxFIFO has 31 characters * 0b100000..RxFIFO has 32 characters (maximum) */ #define UART_UFCR_RXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RXTL_SHIFT)) & UART_UFCR_RXTL_MASK) #define UART_UFCR_DCEDTE_MASK (0x40U) #define UART_UFCR_DCEDTE_SHIFT (6U) /*! DCEDTE * 0b0..DCE mode selected * 0b1..DTE mode selected */ #define UART_UFCR_DCEDTE(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_DCEDTE_SHIFT)) & UART_UFCR_DCEDTE_MASK) #define UART_UFCR_RFDIV_MASK (0x380U) #define UART_UFCR_RFDIV_SHIFT (7U) /*! RFDIV * 0b000..Divide input clock by 6 * 0b001..Divide input clock by 5 * 0b010..Divide input clock by 4 * 0b011..Divide input clock by 3 * 0b100..Divide input clock by 2 * 0b101..Divide input clock by 1 * 0b110..Divide input clock by 7 * 0b111..Reserved */ #define UART_UFCR_RFDIV(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RFDIV_SHIFT)) & UART_UFCR_RFDIV_MASK) #define UART_UFCR_TXTL_MASK (0xFC00U) #define UART_UFCR_TXTL_SHIFT (10U) /*! TXTL * 0b000000..Reserved * 0b000001..Reserved * 0b000010..TxFIFO has 2 or fewer characters * 0b011111..TxFIFO has 31 or fewer characters * 0b100000..TxFIFO has 32 characters (maximum) */ #define UART_UFCR_TXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_TXTL_SHIFT)) & UART_UFCR_TXTL_MASK) /*! @} */ /*! @name USR1 - UART Status Register 1 */ /*! @{ */ #define UART_USR1_SAD_MASK (0x8U) #define UART_USR1_SAD_SHIFT (3U) /*! SAD * 0b0..No slave address detected * 0b1..Slave address detected */ #define UART_USR1_SAD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_SAD_SHIFT)) & UART_USR1_SAD_MASK) #define UART_USR1_AWAKE_MASK (0x10U) #define UART_USR1_AWAKE_SHIFT (4U) /*! AWAKE * 0b0..No falling edge was detected on the RXD Serial pin * 0b1..A falling edge was detected on the RXD Serial pin */ #define UART_USR1_AWAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AWAKE_SHIFT)) & UART_USR1_AWAKE_MASK) #define UART_USR1_AIRINT_MASK (0x20U) #define UART_USR1_AIRINT_SHIFT (5U) /*! AIRINT * 0b0..No pulse was detected on the RXD IrDA pin * 0b1..A pulse was detected on the RXD IrDA pin */ #define UART_USR1_AIRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AIRINT_SHIFT)) & UART_USR1_AIRINT_MASK) #define UART_USR1_RXDS_MASK (0x40U) #define UART_USR1_RXDS_SHIFT (6U) /*! RXDS * 0b0..Receive in progress * 0b1..Receiver is IDLE */ #define UART_USR1_RXDS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RXDS_SHIFT)) & UART_USR1_RXDS_MASK) #define UART_USR1_DTRD_MASK (0x80U) #define UART_USR1_DTRD_SHIFT (7U) #define UART_USR1_DTRD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_DTRD_SHIFT)) & UART_USR1_DTRD_MASK) #define UART_USR1_AGTIM_MASK (0x100U) #define UART_USR1_AGTIM_SHIFT (8U) /*! AGTIM * 0b0..AGTIM is not active * 0b1..AGTIM is active (write 1 to clear) */ #define UART_USR1_AGTIM(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AGTIM_SHIFT)) & UART_USR1_AGTIM_MASK) #define UART_USR1_RRDY_MASK (0x200U) #define UART_USR1_RRDY_SHIFT (9U) /*! RRDY * 0b0..No character ready * 0b1..Character(s) ready (interrupt posted) */ #define UART_USR1_RRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RRDY_SHIFT)) & UART_USR1_RRDY_MASK) #define UART_USR1_FRAMERR_MASK (0x400U) #define UART_USR1_FRAMERR_SHIFT (10U) /*! FRAMERR * 0b0..No frame error detected * 0b1..Frame error detected (write 1 to clear) */ #define UART_USR1_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_FRAMERR_SHIFT)) & UART_USR1_FRAMERR_MASK) #define UART_USR1_ESCF_MASK (0x800U) #define UART_USR1_ESCF_SHIFT (11U) /*! ESCF * 0b0..No escape sequence detected * 0b1..Escape sequence detected (write 1 to clear). */ #define UART_USR1_ESCF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_ESCF_SHIFT)) & UART_USR1_ESCF_MASK) #define UART_USR1_RTSD_MASK (0x1000U) #define UART_USR1_RTSD_SHIFT (12U) /*! RTSD * 0b0..RTS_B pin did not change state since last cleared * 0b1..RTS_B pin changed state (write 1 to clear) */ #define UART_USR1_RTSD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSD_SHIFT)) & UART_USR1_RTSD_MASK) #define UART_USR1_TRDY_MASK (0x2000U) #define UART_USR1_TRDY_SHIFT (13U) /*! TRDY * 0b0..The transmitter does not require data * 0b1..The transmitter requires data (interrupt posted) */ #define UART_USR1_TRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_TRDY_SHIFT)) & UART_USR1_TRDY_MASK) #define UART_USR1_RTSS_MASK (0x4000U) #define UART_USR1_RTSS_SHIFT (14U) /*! RTSS * 0b0..The RTS_B module input is high (inactive) * 0b1..The RTS_B module input is low (active) */ #define UART_USR1_RTSS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSS_SHIFT)) & UART_USR1_RTSS_MASK) #define UART_USR1_PARITYERR_MASK (0x8000U) #define UART_USR1_PARITYERR_SHIFT (15U) /*! PARITYERR * 0b0..No parity error detected * 0b1..Parity error detected (write 1 to clear) */ #define UART_USR1_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_PARITYERR_SHIFT)) & UART_USR1_PARITYERR_MASK) /*! @} */ /*! @name USR2 - UART Status Register 2 */ /*! @{ */ #define UART_USR2_RDR_MASK (0x1U) #define UART_USR2_RDR_SHIFT (0U) /*! RDR * 0b0..No receive data ready * 0b1..Receive data ready */ #define UART_USR2_RDR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RDR_SHIFT)) & UART_USR2_RDR_MASK) #define UART_USR2_ORE_MASK (0x2U) #define UART_USR2_ORE_SHIFT (1U) /*! ORE * 0b0..No overrun error * 0b1..Overrun error (write 1 to clear) */ #define UART_USR2_ORE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ORE_SHIFT)) & UART_USR2_ORE_MASK) #define UART_USR2_BRCD_MASK (0x4U) #define UART_USR2_BRCD_SHIFT (2U) /*! BRCD * 0b0..No BREAK condition was detected * 0b1..A BREAK condition was detected (write 1 to clear) */ #define UART_USR2_BRCD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_BRCD_SHIFT)) & UART_USR2_BRCD_MASK) #define UART_USR2_TXDC_MASK (0x8U) #define UART_USR2_TXDC_SHIFT (3U) /*! TXDC * 0b0..Transmit is incomplete * 0b1..Transmit is complete */ #define UART_USR2_TXDC(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXDC_SHIFT)) & UART_USR2_TXDC_MASK) #define UART_USR2_RTSF_MASK (0x10U) #define UART_USR2_RTSF_SHIFT (4U) /*! RTSF * 0b0..Programmed edge not detected on RTS_B * 0b1..Programmed edge detected on RTS_B (write 1 to clear) */ #define UART_USR2_RTSF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RTSF_SHIFT)) & UART_USR2_RTSF_MASK) #define UART_USR2_DCDIN_MASK (0x20U) #define UART_USR2_DCDIN_SHIFT (5U) #define UART_USR2_DCDIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDIN_SHIFT)) & UART_USR2_DCDIN_MASK) #define UART_USR2_DCDDELT_MASK (0x40U) #define UART_USR2_DCDDELT_SHIFT (6U) #define UART_USR2_DCDDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDDELT_SHIFT)) & UART_USR2_DCDDELT_MASK) #define UART_USR2_WAKE_MASK (0x80U) #define UART_USR2_WAKE_SHIFT (7U) /*! WAKE * 0b0..start bit not detected * 0b1..start bit detected (write 1 to clear) */ #define UART_USR2_WAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_WAKE_SHIFT)) & UART_USR2_WAKE_MASK) #define UART_USR2_IRINT_MASK (0x100U) #define UART_USR2_IRINT_SHIFT (8U) /*! IRINT * 0b0..no edge detected * 0b1..valid edge detected (write 1 to clear) */ #define UART_USR2_IRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IRINT_SHIFT)) & UART_USR2_IRINT_MASK) #define UART_USR2_RIIN_MASK (0x200U) #define UART_USR2_RIIN_SHIFT (9U) #define UART_USR2_RIIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIIN_SHIFT)) & UART_USR2_RIIN_MASK) #define UART_USR2_RIDELT_MASK (0x400U) #define UART_USR2_RIDELT_SHIFT (10U) #define UART_USR2_RIDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIDELT_SHIFT)) & UART_USR2_RIDELT_MASK) #define UART_USR2_ACST_MASK (0x800U) #define UART_USR2_ACST_SHIFT (11U) /*! ACST * 0b0..Measurement of bit length not finished (in autobaud) * 0b1..Measurement of bit length finished (in autobaud). (write 1 to clear) */ #define UART_USR2_ACST(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ACST_SHIFT)) & UART_USR2_ACST_MASK) #define UART_USR2_IDLE_MASK (0x1000U) #define UART_USR2_IDLE_SHIFT (12U) /*! IDLE * 0b0..No idle condition detected * 0b1..Idle condition detected (write 1 to clear) */ #define UART_USR2_IDLE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IDLE_SHIFT)) & UART_USR2_IDLE_MASK) #define UART_USR2_DTRF_MASK (0x2000U) #define UART_USR2_DTRF_SHIFT (13U) #define UART_USR2_DTRF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DTRF_SHIFT)) & UART_USR2_DTRF_MASK) #define UART_USR2_TXFE_MASK (0x4000U) #define UART_USR2_TXFE_SHIFT (14U) /*! TXFE * 0b0..The transmit buffer (TxFIFO) is not empty * 0b1..The transmit buffer (TxFIFO) is empty */ #define UART_USR2_TXFE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXFE_SHIFT)) & UART_USR2_TXFE_MASK) #define UART_USR2_ADET_MASK (0x8000U) #define UART_USR2_ADET_SHIFT (15U) /*! ADET * 0b0..ASCII "A" or "a" was not received * 0b1..ASCII "A" or "a" was received (write 1 to clear) */ #define UART_USR2_ADET(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ADET_SHIFT)) & UART_USR2_ADET_MASK) /*! @} */ /*! @name UESC - UART Escape Character Register */ /*! @{ */ #define UART_UESC_ESC_CHAR_MASK (0xFFU) #define UART_UESC_ESC_CHAR_SHIFT (0U) #define UART_UESC_ESC_CHAR(x) (((uint32_t)(((uint32_t)(x)) << UART_UESC_ESC_CHAR_SHIFT)) & UART_UESC_ESC_CHAR_MASK) /*! @} */ /*! @name UTIM - UART Escape Timer Register */ /*! @{ */ #define UART_UTIM_TIM_MASK (0xFFFU) #define UART_UTIM_TIM_SHIFT (0U) #define UART_UTIM_TIM(x) (((uint32_t)(((uint32_t)(x)) << UART_UTIM_TIM_SHIFT)) & UART_UTIM_TIM_MASK) /*! @} */ /*! @name UBIR - UART BRM Incremental Register */ /*! @{ */ #define UART_UBIR_INC_MASK (0xFFFFU) #define UART_UBIR_INC_SHIFT (0U) #define UART_UBIR_INC(x) (((uint32_t)(((uint32_t)(x)) << UART_UBIR_INC_SHIFT)) & UART_UBIR_INC_MASK) /*! @} */ /*! @name UBMR - UART BRM Modulator Register */ /*! @{ */ #define UART_UBMR_MOD_MASK (0xFFFFU) #define UART_UBMR_MOD_SHIFT (0U) #define UART_UBMR_MOD(x) (((uint32_t)(((uint32_t)(x)) << UART_UBMR_MOD_SHIFT)) & UART_UBMR_MOD_MASK) /*! @} */ /*! @name UBRC - UART Baud Rate Count Register */ /*! @{ */ #define UART_UBRC_BCNT_MASK (0xFFFFU) #define UART_UBRC_BCNT_SHIFT (0U) #define UART_UBRC_BCNT(x) (((uint32_t)(((uint32_t)(x)) << UART_UBRC_BCNT_SHIFT)) & UART_UBRC_BCNT_MASK) /*! @} */ /*! @name ONEMS - UART One Millisecond Register */ /*! @{ */ #define UART_ONEMS_ONEMS_MASK (0xFFFFFFU) #define UART_ONEMS_ONEMS_SHIFT (0U) #define UART_ONEMS_ONEMS(x) (((uint32_t)(((uint32_t)(x)) << UART_ONEMS_ONEMS_SHIFT)) & UART_ONEMS_ONEMS_MASK) /*! @} */ /*! @name UTS - UART Test Register */ /*! @{ */ #define UART_UTS_SOFTRST_MASK (0x1U) #define UART_UTS_SOFTRST_SHIFT (0U) /*! SOFTRST * 0b0..Software reset inactive * 0b1..Software reset active */ #define UART_UTS_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_SOFTRST_SHIFT)) & UART_UTS_SOFTRST_MASK) #define UART_UTS_RXFULL_MASK (0x8U) #define UART_UTS_RXFULL_SHIFT (3U) /*! RXFULL * 0b0..The RxFIFO is not full * 0b1..The RxFIFO is full */ #define UART_UTS_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXFULL_SHIFT)) & UART_UTS_RXFULL_MASK) #define UART_UTS_TXFULL_MASK (0x10U) #define UART_UTS_TXFULL_SHIFT (4U) /*! TXFULL * 0b0..The TxFIFO is not full * 0b1..The TxFIFO is full */ #define UART_UTS_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXFULL_SHIFT)) & UART_UTS_TXFULL_MASK) #define UART_UTS_RXEMPTY_MASK (0x20U) #define UART_UTS_RXEMPTY_SHIFT (5U) /*! RXEMPTY * 0b0..The RxFIFO is not empty * 0b1..The RxFIFO is empty */ #define UART_UTS_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXEMPTY_SHIFT)) & UART_UTS_RXEMPTY_MASK) #define UART_UTS_TXEMPTY_MASK (0x40U) #define UART_UTS_TXEMPTY_SHIFT (6U) /*! TXEMPTY * 0b0..The TxFIFO is not empty * 0b1..The TxFIFO is empty */ #define UART_UTS_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXEMPTY_SHIFT)) & UART_UTS_TXEMPTY_MASK) #define UART_UTS_RXDBG_MASK (0x200U) #define UART_UTS_RXDBG_SHIFT (9U) /*! RXDBG * 0b0..rx fifo read pointer does not increment * 0b1..rx_fifo read pointer increments as normal */ #define UART_UTS_RXDBG(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXDBG_SHIFT)) & UART_UTS_RXDBG_MASK) #define UART_UTS_LOOPIR_MASK (0x400U) #define UART_UTS_LOOPIR_SHIFT (10U) /*! LOOPIR * 0b0..No IR loop * 0b1..Connect IR transmitter to IR receiver */ #define UART_UTS_LOOPIR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOPIR_SHIFT)) & UART_UTS_LOOPIR_MASK) #define UART_UTS_DBGEN_MASK (0x800U) #define UART_UTS_DBGEN_SHIFT (11U) /*! DBGEN * 0b0..UART will go into debug mode when debug_req is HIGH * 0b1..UART will not go into debug mode even if debug_req is HIGH */ #define UART_UTS_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_DBGEN_SHIFT)) & UART_UTS_DBGEN_MASK) #define UART_UTS_LOOP_MASK (0x1000U) #define UART_UTS_LOOP_SHIFT (12U) /*! LOOP * 0b0..Normal receiver operation * 0b1..Internally connect the transmitter output to the receiver input */ #define UART_UTS_LOOP(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOP_SHIFT)) & UART_UTS_LOOP_MASK) #define UART_UTS_FRCPERR_MASK (0x2000U) #define UART_UTS_FRCPERR_SHIFT (13U) /*! FRCPERR * 0b0..Generate normal parity * 0b1..Generate inverted parity (error) */ #define UART_UTS_FRCPERR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_FRCPERR_SHIFT)) & UART_UTS_FRCPERR_MASK) /*! @} */ /*! @name UMCR - UART RS-485 Mode Control Register */ /*! @{ */ #define UART_UMCR_MDEN_MASK (0x1U) #define UART_UMCR_MDEN_SHIFT (0U) /*! MDEN * 0b0..Normal RS-232 or IrDA mode, see for detail. * 0b1..Enable RS-485 mode, see for detail */ #define UART_UMCR_MDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_MDEN_SHIFT)) & UART_UMCR_MDEN_MASK) #define UART_UMCR_SLAM_MASK (0x2U) #define UART_UMCR_SLAM_SHIFT (1U) /*! SLAM * 0b0..Select Normal Address Detect mode * 0b1..Select Automatic Address Detect mode */ #define UART_UMCR_SLAM(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLAM_SHIFT)) & UART_UMCR_SLAM_MASK) #define UART_UMCR_TXB8_MASK (0x4U) #define UART_UMCR_TXB8_SHIFT (2U) /*! TXB8 * 0b0..0 will be transmitted as the RS485 9th data bit * 0b1..1 will be transmitted as the RS485 9th data bit */ #define UART_UMCR_TXB8(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_TXB8_SHIFT)) & UART_UMCR_TXB8_MASK) #define UART_UMCR_SADEN_MASK (0x8U) #define UART_UMCR_SADEN_SHIFT (3U) /*! SADEN * 0b0..Disable RS-485 Slave Address Detected Interrupt * 0b1..Enable RS-485 Slave Address Detected Interrupt */ #define UART_UMCR_SADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SADEN_SHIFT)) & UART_UMCR_SADEN_MASK) #define UART_UMCR_SLADDR_MASK (0xFF00U) #define UART_UMCR_SLADDR_SHIFT (8U) #define UART_UMCR_SLADDR(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLADDR_SHIFT)) & UART_UMCR_SLADDR_MASK) /*! @} */ /*! * @} */ /* end of group UART_Register_Masks */ /* UART - Peripheral instance base addresses */ /** Peripheral UART1 base address */ #define UART1_BASE (0x30860000u) /** Peripheral UART1 base pointer */ #define UART1 ((UART_Type *)UART1_BASE) /** Peripheral UART2 base address */ #define UART2_BASE (0x30890000u) /** Peripheral UART2 base pointer */ #define UART2 ((UART_Type *)UART2_BASE) /** Peripheral UART3 base address */ #define UART3_BASE (0x30880000u) /** Peripheral UART3 base pointer */ #define UART3 ((UART_Type *)UART3_BASE) /** Peripheral UART4 base address */ #define UART4_BASE (0x30A60000u) /** Peripheral UART4 base pointer */ #define UART4 ((UART_Type *)UART4_BASE) /** Array initializer of UART peripheral base addresses */ #define UART_BASE_ADDRS \ { \ 0u, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE \ } /** Array initializer of UART peripheral base pointers */ #define UART_BASE_PTRS \ { \ (UART_Type *)0u, UART1, UART2, UART3, UART4 \ } /** Interrupt vectors for the UART peripheral type */ #define UART_IRQS \ { \ NotAvail_IRQn, UART1_IRQn, UART2_IRQn, UART3_IRQn, UART4_IRQn \ } /*! * @} */ /* end of group UART_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer * @{ */ /** USB - Register Layout Typedef */ typedef struct { __I uint32_t ID; /**< Identification register, offset: 0x0 */ __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ uint8_t RESERVED_0[104]; __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ uint8_t RESERVED_1[108]; __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ uint8_t RESERVED_2[1]; __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ uint8_t RESERVED_3[20]; __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ uint8_t RESERVED_4[2]; __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ uint8_t RESERVED_5[24]; __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */ __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */ __IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */ __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ uint8_t RESERVED_6[4]; union { /* offset: 0x154 */ __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ }; union { /* offset: 0x158 */ __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ }; uint8_t RESERVED_7[4]; __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ uint8_t RESERVED_8[16]; __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */ __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ uint8_t RESERVED_9[28]; __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ __IO uint32_t ENDPTCTRL[8]; /**< Endpoint Control0..Endpoint Control 7, array offset: 0x1C0, array step: 0x4 */ } USB_Type; /* ---------------------------------------------------------------------------- -- USB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_Register_Masks USB Register Masks * @{ */ /*! @name ID - Identification register */ /*! @{ */ #define USB_ID_ID_MASK (0x3FU) #define USB_ID_ID_SHIFT (0U) #define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) #define USB_ID_NID_MASK (0x3F00U) #define USB_ID_NID_SHIFT (8U) #define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK) #define USB_ID_REVISION_MASK (0xFF0000U) #define USB_ID_REVISION_SHIFT (16U) #define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) /*! @} */ /*! @name HWGENERAL - Hardware General */ /*! @{ */ #define USB_HWGENERAL_PHYW_MASK (0x30U) #define USB_HWGENERAL_PHYW_SHIFT (4U) /*! PHYW * 0b11..Reset to 16 bit wide data bus Software programmable */ #define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) #define USB_HWGENERAL_PHYM_MASK (0x1C0U) #define USB_HWGENERAL_PHYM_SHIFT (6U) /*! PHYM * 0b000..UTMI/UMTI+ * 0b001..ULPI DDR * 0b010..ULPI * 0b011..Serial Only * 0b100..Software programmable - reset to UTMI/UTMI+ * 0b101..Software programmable - reset to ULPI DDR * 0b110..Software programmable - reset to ULPI * 0b111..Software programmable - reset to Serial */ #define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) #define USB_HWGENERAL_SM_MASK (0x600U) #define USB_HWGENERAL_SM_SHIFT (9U) /*! SM * 0b00..No Serial Engine, always use parallel signalling. * 0b01..Serial Engine present, always use serial signalling for FS/LS. * 0b10..Software programmable - Reset to use parallel signalling for FS/LS * 0b11..Software programmable - Reset to use serial signalling for FS/LS */ #define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) /*! @} */ /*! @name HWHOST - Host Hardware Parameters */ /*! @{ */ #define USB_HWHOST_HC_MASK (0x1U) #define USB_HWHOST_HC_SHIFT (0U) /*! HC * 0b1..Supported * 0b0..Not supported */ #define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) #define USB_HWHOST_NPORT_MASK (0xEU) #define USB_HWHOST_NPORT_SHIFT (1U) #define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) /*! @} */ /*! @name HWDEVICE - Device Hardware Parameters */ /*! @{ */ #define USB_HWDEVICE_DC_MASK (0x1U) #define USB_HWDEVICE_DC_SHIFT (0U) /*! DC * 0b1..Supported * 0b0..Not supported */ #define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) #define USB_HWDEVICE_DEVEP_MASK (0x3EU) #define USB_HWDEVICE_DEVEP_SHIFT (1U) #define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) /*! @} */ /*! @name HWTXBUF - TX Buffer Hardware Parameters */ /*! @{ */ #define USB_HWTXBUF_TXBURST_MASK (0xFFU) #define USB_HWTXBUF_TXBURST_SHIFT (0U) #define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) #define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) #define USB_HWTXBUF_TXCHANADD_SHIFT (16U) #define USB_HWTXBUF_TXCHANADD(x) \ (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) /*! @} */ /*! @name HWRXBUF - RX Buffer Hardware Parameters */ /*! @{ */ #define USB_HWRXBUF_RXBURST_MASK (0xFFU) #define USB_HWRXBUF_RXBURST_SHIFT (0U) #define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) #define USB_HWRXBUF_RXADD_MASK (0xFF00U) #define USB_HWRXBUF_RXADD_SHIFT (8U) #define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) /*! @} */ /*! @name GPTIMER0LD - General Purpose Timer #0 Load */ /*! @{ */ #define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) #define USB_GPTIMER0LD_GPTLD_SHIFT (0U) #define USB_GPTIMER0LD_GPTLD(x) \ (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) /*! @} */ /*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ /*! @{ */ #define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) #define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) #define USB_GPTIMER0CTRL_GPTCNT(x) \ (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) #define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) #define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) /*! GPTMODE * 0b0..One Shot Mode * 0b1..Repeat Mode */ #define USB_GPTIMER0CTRL_GPTMODE(x) \ (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) #define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) #define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) /*! GPTRST * 0b0..No action * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD */ #define USB_GPTIMER0CTRL_GPTRST(x) \ (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) #define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) #define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) /*! GPTRUN * 0b0..Stop counting * 0b1..Run */ #define USB_GPTIMER0CTRL_GPTRUN(x) \ (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) /*! @} */ /*! @name GPTIMER1LD - General Purpose Timer #1 Load */ /*! @{ */ #define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) #define USB_GPTIMER1LD_GPTLD_SHIFT (0U) #define USB_GPTIMER1LD_GPTLD(x) \ (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) /*! @} */ /*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ /*! @{ */ #define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) #define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) #define USB_GPTIMER1CTRL_GPTCNT(x) \ (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) #define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) #define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) /*! GPTMODE * 0b0..One Shot Mode * 0b1..Repeat Mode */ #define USB_GPTIMER1CTRL_GPTMODE(x) \ (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) #define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) #define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) /*! GPTRST * 0b0..No action * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD */ #define USB_GPTIMER1CTRL_GPTRST(x) \ (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) #define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) #define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) /*! GPTRUN * 0b0..Stop counting * 0b1..Run */ #define USB_GPTIMER1CTRL_GPTRUN(x) \ (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) /*! @} */ /*! @name SBUSCFG - System Bus Config */ /*! @{ */ #define USB_SBUSCFG_AHBBRST_MASK (0x7U) #define USB_SBUSCFG_AHBBRST_SHIFT (0U) /*! AHBBRST * 0b000..Incremental burst of unspecified length only * 0b001..INCR4 burst, then single transfer * 0b010..INCR8 burst, INCR4 burst, then single transfer * 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer * 0b100..Reserved, don't use * 0b101..INCR4 burst, then incremental burst of unspecified length * 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length * 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length */ #define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) /*! @} */ /*! @name CAPLENGTH - Capability Registers Length */ /*! @{ */ #define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) #define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) #define USB_CAPLENGTH_CAPLENGTH(x) \ (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) /*! @} */ /*! @name HCIVERSION - Host Controller Interface Version */ /*! @{ */ #define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) #define USB_HCIVERSION_HCIVERSION_SHIFT (0U) #define USB_HCIVERSION_HCIVERSION(x) \ (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) /*! @} */ /*! @name HCSPARAMS - Host Controller Structural Parameters */ /*! @{ */ #define USB_HCSPARAMS_N_PORTS_MASK (0xFU) #define USB_HCSPARAMS_N_PORTS_SHIFT (0U) #define USB_HCSPARAMS_N_PORTS(x) \ (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) #define USB_HCSPARAMS_PPC_MASK (0x10U) #define USB_HCSPARAMS_PPC_SHIFT (4U) #define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK) #define USB_HCSPARAMS_N_PCC_MASK (0xF00U) #define USB_HCSPARAMS_N_PCC_SHIFT (8U) #define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) #define USB_HCSPARAMS_N_CC_MASK (0xF000U) #define USB_HCSPARAMS_N_CC_SHIFT (12U) /*! N_CC * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported. * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported. */ #define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) #define USB_HCSPARAMS_PI_MASK (0x10000U) #define USB_HCSPARAMS_PI_SHIFT (16U) #define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK) #define USB_HCSPARAMS_N_PTT_MASK (0xF00000U) #define USB_HCSPARAMS_N_PTT_SHIFT (20U) #define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK) #define USB_HCSPARAMS_N_TT_MASK (0xF000000U) #define USB_HCSPARAMS_N_TT_SHIFT (24U) #define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) /*! @} */ /*! @name HCCPARAMS - Host Controller Capability Parameters */ /*! @{ */ #define USB_HCCPARAMS_ADC_MASK (0x1U) #define USB_HCCPARAMS_ADC_SHIFT (0U) #define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) #define USB_HCCPARAMS_PFL_MASK (0x2U) #define USB_HCCPARAMS_PFL_SHIFT (1U) #define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK) #define USB_HCCPARAMS_ASP_MASK (0x4U) #define USB_HCCPARAMS_ASP_SHIFT (2U) #define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK) #define USB_HCCPARAMS_IST_MASK (0xF0U) #define USB_HCCPARAMS_IST_SHIFT (4U) #define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK) #define USB_HCCPARAMS_EECP_MASK (0xFF00U) #define USB_HCCPARAMS_EECP_SHIFT (8U) #define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) /*! @} */ /*! @name DCIVERSION - Device Controller Interface Version */ /*! @{ */ #define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) #define USB_DCIVERSION_DCIVERSION_SHIFT (0U) #define USB_DCIVERSION_DCIVERSION(x) \ (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) /*! @} */ /*! @name DCCPARAMS - Device Controller Capability Parameters */ /*! @{ */ #define USB_DCCPARAMS_DEN_MASK (0x1FU) #define USB_DCCPARAMS_DEN_SHIFT (0U) #define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) #define USB_DCCPARAMS_DC_MASK (0x80U) #define USB_DCCPARAMS_DC_SHIFT (7U) #define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK) #define USB_DCCPARAMS_HC_MASK (0x100U) #define USB_DCCPARAMS_HC_SHIFT (8U) #define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) /*! @} */ /*! @name USBCMD - USB Command Register */ /*! @{ */ #define USB_USBCMD_RS_MASK (0x1U) #define USB_USBCMD_RS_SHIFT (0U) #define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) #define USB_USBCMD_RST_MASK (0x2U) #define USB_USBCMD_RST_SHIFT (1U) #define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK) #define USB_USBCMD_FS_1_MASK (0xCU) #define USB_USBCMD_FS_1_SHIFT (2U) #define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) #define USB_USBCMD_PSE_MASK (0x10U) #define USB_USBCMD_PSE_SHIFT (4U) /*! PSE * 0b0..Do not process the Periodic Schedule * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule. */ #define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) #define USB_USBCMD_ASE_MASK (0x20U) #define USB_USBCMD_ASE_SHIFT (5U) /*! ASE * 0b0..Do not process the Asynchronous Schedule. * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule. */ #define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) #define USB_USBCMD_IAA_MASK (0x40U) #define USB_USBCMD_IAA_SHIFT (6U) #define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK) #define USB_USBCMD_ASP_MASK (0x300U) #define USB_USBCMD_ASP_SHIFT (8U) #define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK) #define USB_USBCMD_ASPE_MASK (0x800U) #define USB_USBCMD_ASPE_SHIFT (11U) #define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK) #define USB_USBCMD_SUTW_MASK (0x2000U) #define USB_USBCMD_SUTW_SHIFT (13U) #define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) #define USB_USBCMD_ATDTW_MASK (0x4000U) #define USB_USBCMD_ATDTW_SHIFT (14U) #define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK) #define USB_USBCMD_FS_2_MASK (0x8000U) #define USB_USBCMD_FS_2_SHIFT (15U) /*! FS_2 * 0b0..1024 elements (4096 bytes) Default value * 0b1..512 elements (2048 bytes) */ #define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) #define USB_USBCMD_ITC_MASK (0xFF0000U) #define USB_USBCMD_ITC_SHIFT (16U) /*! ITC * 0b00000000..Immediate (no threshold) * 0b00000001..1 micro-frame * 0b00000010..2 micro-frames * 0b00000100..4 micro-frames * 0b00001000..8 micro-frames * 0b00010000..16 micro-frames * 0b00100000..32 micro-frames * 0b01000000..64 micro-frames */ #define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) /*! @} */ /*! @name USBSTS - USB Status Register */ /*! @{ */ #define USB_USBSTS_UI_MASK (0x1U) #define USB_USBSTS_UI_SHIFT (0U) #define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) #define USB_USBSTS_UEI_MASK (0x2U) #define USB_USBSTS_UEI_SHIFT (1U) #define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) #define USB_USBSTS_PCI_MASK (0x4U) #define USB_USBSTS_PCI_SHIFT (2U) #define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) #define USB_USBSTS_FRI_MASK (0x8U) #define USB_USBSTS_FRI_SHIFT (3U) #define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) #define USB_USBSTS_SEI_MASK (0x10U) #define USB_USBSTS_SEI_SHIFT (4U) #define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) #define USB_USBSTS_AAI_MASK (0x20U) #define USB_USBSTS_AAI_SHIFT (5U) #define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) #define USB_USBSTS_URI_MASK (0x40U) #define USB_USBSTS_URI_SHIFT (6U) #define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) #define USB_USBSTS_SRI_MASK (0x80U) #define USB_USBSTS_SRI_SHIFT (7U) #define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) #define USB_USBSTS_SLI_MASK (0x100U) #define USB_USBSTS_SLI_SHIFT (8U) #define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) #define USB_USBSTS_ULPII_MASK (0x400U) #define USB_USBSTS_ULPII_SHIFT (10U) #define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) #define USB_USBSTS_HCH_MASK (0x1000U) #define USB_USBSTS_HCH_SHIFT (12U) #define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK) #define USB_USBSTS_RCL_MASK (0x2000U) #define USB_USBSTS_RCL_SHIFT (13U) #define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK) #define USB_USBSTS_PS_MASK (0x4000U) #define USB_USBSTS_PS_SHIFT (14U) #define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK) #define USB_USBSTS_AS_MASK (0x8000U) #define USB_USBSTS_AS_SHIFT (15U) #define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK) #define USB_USBSTS_NAKI_MASK (0x10000U) #define USB_USBSTS_NAKI_SHIFT (16U) #define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK) #define USB_USBSTS_TI0_MASK (0x1000000U) #define USB_USBSTS_TI0_SHIFT (24U) #define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) #define USB_USBSTS_TI1_MASK (0x2000000U) #define USB_USBSTS_TI1_SHIFT (25U) #define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) /*! @} */ /*! @name USBINTR - Interrupt Enable Register */ /*! @{ */ #define USB_USBINTR_UE_MASK (0x1U) #define USB_USBINTR_UE_SHIFT (0U) #define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) #define USB_USBINTR_UEE_MASK (0x2U) #define USB_USBINTR_UEE_SHIFT (1U) #define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK) #define USB_USBINTR_PCE_MASK (0x4U) #define USB_USBINTR_PCE_SHIFT (2U) #define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK) #define USB_USBINTR_FRE_MASK (0x8U) #define USB_USBINTR_FRE_SHIFT (3U) #define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK) #define USB_USBINTR_SEE_MASK (0x10U) #define USB_USBINTR_SEE_SHIFT (4U) #define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK) #define USB_USBINTR_AAE_MASK (0x20U) #define USB_USBINTR_AAE_SHIFT (5U) #define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK) #define USB_USBINTR_URE_MASK (0x40U) #define USB_USBINTR_URE_SHIFT (6U) #define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK) #define USB_USBINTR_SRE_MASK (0x80U) #define USB_USBINTR_SRE_SHIFT (7U) #define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK) #define USB_USBINTR_SLE_MASK (0x100U) #define USB_USBINTR_SLE_SHIFT (8U) #define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK) #define USB_USBINTR_ULPIE_MASK (0x400U) #define USB_USBINTR_ULPIE_SHIFT (10U) #define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK) #define USB_USBINTR_NAKE_MASK (0x10000U) #define USB_USBINTR_NAKE_SHIFT (16U) #define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK) #define USB_USBINTR_UAIE_MASK (0x40000U) #define USB_USBINTR_UAIE_SHIFT (18U) #define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK) #define USB_USBINTR_UPIE_MASK (0x80000U) #define USB_USBINTR_UPIE_SHIFT (19U) #define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK) #define USB_USBINTR_TIE0_MASK (0x1000000U) #define USB_USBINTR_TIE0_SHIFT (24U) #define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK) #define USB_USBINTR_TIE1_MASK (0x2000000U) #define USB_USBINTR_TIE1_SHIFT (25U) #define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) /*! @} */ /*! @name FRINDEX - USB Frame Index */ /*! @{ */ #define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) #define USB_FRINDEX_FRINDEX_SHIFT (0U) /*! FRINDEX * 0b00000000000000..(1024) 12 * 0b00000000000001..(512) 11 * 0b00000000000010..(256) 10 * 0b00000000000011..(128) 9 * 0b00000000000100..(64) 8 * 0b00000000000101..(32) 7 * 0b00000000000110..(16) 6 * 0b00000000000111..(8) 5 */ #define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) /*! @} */ /*! @name DEVICEADDR - Device Address */ /*! @{ */ #define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) #define USB_DEVICEADDR_USBADRA_SHIFT (24U) #define USB_DEVICEADDR_USBADRA(x) \ (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) #define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) #define USB_DEVICEADDR_USBADR_SHIFT (25U) #define USB_DEVICEADDR_USBADR(x) \ (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) /*! @} */ /*! @name PERIODICLISTBASE - Frame List Base Address */ /*! @{ */ #define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) #define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) #define USB_PERIODICLISTBASE_BASEADR(x) \ (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) /*! @} */ /*! @name ASYNCLISTADDR - Next Asynch. Address */ /*! @{ */ #define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) #define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) #define USB_ASYNCLISTADDR_ASYBASE(x) \ (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) /*! @} */ /*! @name ENDPTLISTADDR - Endpoint List Address */ /*! @{ */ #define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) #define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) #define USB_ENDPTLISTADDR_EPBASE(x) \ (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) /*! @} */ /*! @name BURSTSIZE - Programmable Burst Size */ /*! @{ */ #define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) #define USB_BURSTSIZE_RXPBURST_SHIFT (0U) #define USB_BURSTSIZE_RXPBURST(x) \ (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) #define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U) #define USB_BURSTSIZE_TXPBURST_SHIFT (8U) #define USB_BURSTSIZE_TXPBURST(x) \ (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) /*! @} */ /*! @name TXFILLTUNING - TX FIFO Fill Tuning */ /*! @{ */ #define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU) #define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) #define USB_TXFILLTUNING_TXSCHOH(x) \ (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) #define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) #define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) #define USB_TXFILLTUNING_TXSCHHEALTH(x) \ (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) #define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) #define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) #define USB_TXFILLTUNING_TXFIFOTHRES(x) \ (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) /*! @} */ /*! @name ENDPTNAK - Endpoint NAK */ /*! @{ */ #define USB_ENDPTNAK_EPRN_MASK (0xFFU) #define USB_ENDPTNAK_EPRN_SHIFT (0U) #define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) #define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) #define USB_ENDPTNAK_EPTN_SHIFT (16U) #define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) /*! @} */ /*! @name ENDPTNAKEN - Endpoint NAK Enable */ /*! @{ */ #define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) #define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) #define USB_ENDPTNAKEN_EPRNE(x) \ (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) #define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) #define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) #define USB_ENDPTNAKEN_EPTNE(x) \ (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) /*! @} */ /*! @name CONFIGFLAG - Configure Flag Register */ /*! @{ */ #define USB_CONFIGFLAG_CF_MASK (0x1U) #define USB_CONFIGFLAG_CF_SHIFT (0U) /*! CF * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller. * 0b1..Port routing control logic default-routes all ports to this host controller. */ #define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) /*! @} */ /*! @name PORTSC1 - Port Status & Control */ /*! @{ */ #define USB_PORTSC1_CCS_MASK (0x1U) #define USB_PORTSC1_CCS_SHIFT (0U) #define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) #define USB_PORTSC1_CSC_MASK (0x2U) #define USB_PORTSC1_CSC_SHIFT (1U) #define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK) #define USB_PORTSC1_PE_MASK (0x4U) #define USB_PORTSC1_PE_SHIFT (2U) #define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK) #define USB_PORTSC1_PEC_MASK (0x8U) #define USB_PORTSC1_PEC_SHIFT (3U) #define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) #define USB_PORTSC1_OCA_MASK (0x10U) #define USB_PORTSC1_OCA_SHIFT (4U) /*! OCA * 0b1..This port currently has an over-current condition * 0b0..This port does not have an over-current condition. */ #define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) #define USB_PORTSC1_OCC_MASK (0x20U) #define USB_PORTSC1_OCC_SHIFT (5U) #define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK) #define USB_PORTSC1_FPR_MASK (0x40U) #define USB_PORTSC1_FPR_SHIFT (6U) #define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK) #define USB_PORTSC1_SUSP_MASK (0x80U) #define USB_PORTSC1_SUSP_SHIFT (7U) #define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK) #define USB_PORTSC1_PR_MASK (0x100U) #define USB_PORTSC1_PR_SHIFT (8U) #define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK) #define USB_PORTSC1_HSP_MASK (0x200U) #define USB_PORTSC1_HSP_SHIFT (9U) #define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) #define USB_PORTSC1_LS_MASK (0xC00U) #define USB_PORTSC1_LS_SHIFT (10U) /*! LS * 0b00..SE0 * 0b10..J-state * 0b01..K-state * 0b11..Undefined */ #define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) #define USB_PORTSC1_PP_MASK (0x1000U) #define USB_PORTSC1_PP_SHIFT (12U) #define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK) #define USB_PORTSC1_PO_MASK (0x2000U) #define USB_PORTSC1_PO_SHIFT (13U) #define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) #define USB_PORTSC1_PIC_MASK (0xC000U) #define USB_PORTSC1_PIC_SHIFT (14U) /*! PIC * 0b00..Port indicators are off * 0b01..Amber * 0b10..Green * 0b11..Undefined */ #define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) #define USB_PORTSC1_PTC_MASK (0xF0000U) #define USB_PORTSC1_PTC_SHIFT (16U) /*! PTC * 0b0000..TEST_MODE_DISABLE * 0b0001..J_STATE * 0b0010..K_STATE * 0b0011..SE0 (host) / NAK (device) * 0b0100..Packet * 0b0101..FORCE_ENABLE_HS * 0b0110..FORCE_ENABLE_FS * 0b0111..FORCE_ENABLE_LS */ #define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) #define USB_PORTSC1_WKCN_MASK (0x100000U) #define USB_PORTSC1_WKCN_SHIFT (20U) #define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK) #define USB_PORTSC1_WKDC_MASK (0x200000U) #define USB_PORTSC1_WKDC_SHIFT (21U) #define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK) #define USB_PORTSC1_WKOC_MASK (0x400000U) #define USB_PORTSC1_WKOC_SHIFT (22U) #define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) #define USB_PORTSC1_PHCD_MASK (0x800000U) #define USB_PORTSC1_PHCD_SHIFT (23U) /*! PHCD * 0b1..Disable PHY clock * 0b0..Enable PHY clock */ #define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) #define USB_PORTSC1_PFSC_MASK (0x1000000U) #define USB_PORTSC1_PFSC_SHIFT (24U) /*! PFSC * 0b1..Forced to full speed * 0b0..Normal operation */ #define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) #define USB_PORTSC1_PTS_2_MASK (0x2000000U) #define USB_PORTSC1_PTS_2_SHIFT (25U) #define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) #define USB_PORTSC1_PSPD_MASK (0xC000000U) #define USB_PORTSC1_PSPD_SHIFT (26U) /*! PSPD * 0b00..Full Speed * 0b01..Low Speed * 0b10..High Speed * 0b11..Undefined */ #define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) #define USB_PORTSC1_PTW_MASK (0x10000000U) #define USB_PORTSC1_PTW_SHIFT (28U) /*! PTW * 0b0..Select the 8-bit UTMI interface [60MHz] * 0b1..Select the 16-bit UTMI interface [30MHz] */ #define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) #define USB_PORTSC1_STS_MASK (0x20000000U) #define USB_PORTSC1_STS_SHIFT (29U) #define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK) #define USB_PORTSC1_PTS_1_MASK (0xC0000000U) #define USB_PORTSC1_PTS_1_SHIFT (30U) #define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) /*! @} */ /*! @name OTGSC - On-The-Go Status & control */ /*! @{ */ #define USB_OTGSC_VD_MASK (0x1U) #define USB_OTGSC_VD_SHIFT (0U) #define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) #define USB_OTGSC_VC_MASK (0x2U) #define USB_OTGSC_VC_SHIFT (1U) #define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK) #define USB_OTGSC_OT_MASK (0x8U) #define USB_OTGSC_OT_SHIFT (3U) #define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK) #define USB_OTGSC_DP_MASK (0x10U) #define USB_OTGSC_DP_SHIFT (4U) #define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK) #define USB_OTGSC_IDPU_MASK (0x20U) #define USB_OTGSC_IDPU_SHIFT (5U) #define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK) #define USB_OTGSC_ID_MASK (0x100U) #define USB_OTGSC_ID_SHIFT (8U) #define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK) #define USB_OTGSC_AVV_MASK (0x200U) #define USB_OTGSC_AVV_SHIFT (9U) #define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK) #define USB_OTGSC_ASV_MASK (0x400U) #define USB_OTGSC_ASV_SHIFT (10U) #define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK) #define USB_OTGSC_BSV_MASK (0x800U) #define USB_OTGSC_BSV_SHIFT (11U) #define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK) #define USB_OTGSC_BSE_MASK (0x1000U) #define USB_OTGSC_BSE_SHIFT (12U) #define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK) #define USB_OTGSC_TOG_1MS_MASK (0x2000U) #define USB_OTGSC_TOG_1MS_SHIFT (13U) #define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK) #define USB_OTGSC_DPS_MASK (0x4000U) #define USB_OTGSC_DPS_SHIFT (14U) #define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK) #define USB_OTGSC_IDIS_MASK (0x10000U) #define USB_OTGSC_IDIS_SHIFT (16U) #define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK) #define USB_OTGSC_AVVIS_MASK (0x20000U) #define USB_OTGSC_AVVIS_SHIFT (17U) #define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) #define USB_OTGSC_ASVIS_MASK (0x40000U) #define USB_OTGSC_ASVIS_SHIFT (18U) #define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) #define USB_OTGSC_BSVIS_MASK (0x80000U) #define USB_OTGSC_BSVIS_SHIFT (19U) #define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) #define USB_OTGSC_BSEIS_MASK (0x100000U) #define USB_OTGSC_BSEIS_SHIFT (20U) #define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) #define USB_OTGSC_STATUS_1MS_MASK (0x200000U) #define USB_OTGSC_STATUS_1MS_SHIFT (21U) #define USB_OTGSC_STATUS_1MS(x) \ (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK) #define USB_OTGSC_DPIS_MASK (0x400000U) #define USB_OTGSC_DPIS_SHIFT (22U) #define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) #define USB_OTGSC_IDIE_MASK (0x1000000U) #define USB_OTGSC_IDIE_SHIFT (24U) #define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK) #define USB_OTGSC_AVVIE_MASK (0x2000000U) #define USB_OTGSC_AVVIE_SHIFT (25U) #define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK) #define USB_OTGSC_ASVIE_MASK (0x4000000U) #define USB_OTGSC_ASVIE_SHIFT (26U) #define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK) #define USB_OTGSC_BSVIE_MASK (0x8000000U) #define USB_OTGSC_BSVIE_SHIFT (27U) #define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK) #define USB_OTGSC_BSEIE_MASK (0x10000000U) #define USB_OTGSC_BSEIE_SHIFT (28U) #define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK) #define USB_OTGSC_EN_1MS_MASK (0x20000000U) #define USB_OTGSC_EN_1MS_SHIFT (29U) #define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK) #define USB_OTGSC_DPIE_MASK (0x40000000U) #define USB_OTGSC_DPIE_SHIFT (30U) #define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) /*! @} */ /*! @name USBMODE - USB Device Mode */ /*! @{ */ #define USB_USBMODE_CM_MASK (0x3U) #define USB_USBMODE_CM_SHIFT (0U) /*! CM * 0b00..Idle [Default for combination host/device] * 0b01..Reserved * 0b10..Device Controller [Default for device only controller] * 0b11..Host Controller [Default for host only controller] */ #define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) #define USB_USBMODE_ES_MASK (0x4U) #define USB_USBMODE_ES_SHIFT (2U) /*! ES * 0b0..Little Endian [Default] * 0b1..Big Endian */ #define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) #define USB_USBMODE_SLOM_MASK (0x8U) #define USB_USBMODE_SLOM_SHIFT (3U) /*! SLOM * 0b0..Setup Lockouts On (default); * 0b1..Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register . */ #define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) #define USB_USBMODE_SDIS_MASK (0x10U) #define USB_USBMODE_SDIS_SHIFT (4U) #define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) /*! @} */ /*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ /*! @{ */ #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) \ (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) /*! @} */ /*! @name ENDPTPRIME - Endpoint Prime */ /*! @{ */ #define USB_ENDPTPRIME_PERB_MASK (0xFFU) #define USB_ENDPTPRIME_PERB_SHIFT (0U) #define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) #define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) #define USB_ENDPTPRIME_PETB_SHIFT (16U) #define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) /*! @} */ /*! @name ENDPTFLUSH - Endpoint Flush */ /*! @{ */ #define USB_ENDPTFLUSH_FERB_MASK (0xFFU) #define USB_ENDPTFLUSH_FERB_SHIFT (0U) #define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) #define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) #define USB_ENDPTFLUSH_FETB_SHIFT (16U) #define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) /*! @} */ /*! @name ENDPTSTAT - Endpoint Status */ /*! @{ */ #define USB_ENDPTSTAT_ERBR_MASK (0xFFU) #define USB_ENDPTSTAT_ERBR_SHIFT (0U) #define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) #define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) #define USB_ENDPTSTAT_ETBR_SHIFT (16U) #define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) /*! @} */ /*! @name ENDPTCOMPLETE - Endpoint Complete */ /*! @{ */ #define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) #define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) #define USB_ENDPTCOMPLETE_ERCE(x) \ (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) #define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) #define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) #define USB_ENDPTCOMPLETE_ETCE(x) \ (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) /*! @} */ /*! @name ENDPTCTRL - Endpoint Control0..Endpoint Control 7 */ /*! @{ */ #define USB_ENDPTCTRL_RXS_MASK (0x1U) #define USB_ENDPTCTRL_RXS_SHIFT (0U) #define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) #define USB_ENDPTCTRL_RXD_MASK (0x2U) #define USB_ENDPTCTRL_RXD_SHIFT (1U) #define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK) #define USB_ENDPTCTRL_RXT_MASK (0xCU) #define USB_ENDPTCTRL_RXT_SHIFT (2U) #define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK) #define USB_ENDPTCTRL_RXI_MASK (0x20U) #define USB_ENDPTCTRL_RXI_SHIFT (5U) #define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK) #define USB_ENDPTCTRL_RXR_MASK (0x40U) #define USB_ENDPTCTRL_RXR_SHIFT (6U) #define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK) #define USB_ENDPTCTRL_RXE_MASK (0x80U) #define USB_ENDPTCTRL_RXE_SHIFT (7U) #define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK) #define USB_ENDPTCTRL_TXS_MASK (0x10000U) #define USB_ENDPTCTRL_TXS_SHIFT (16U) #define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK) #define USB_ENDPTCTRL_TXD_MASK (0x20000U) #define USB_ENDPTCTRL_TXD_SHIFT (17U) #define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK) #define USB_ENDPTCTRL_TXT_MASK (0xC0000U) #define USB_ENDPTCTRL_TXT_SHIFT (18U) #define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK) #define USB_ENDPTCTRL_TXI_MASK (0x200000U) #define USB_ENDPTCTRL_TXI_SHIFT (21U) #define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK) #define USB_ENDPTCTRL_TXR_MASK (0x400000U) #define USB_ENDPTCTRL_TXR_SHIFT (22U) #define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK) #define USB_ENDPTCTRL_TXE_MASK (0x800000U) #define USB_ENDPTCTRL_TXE_SHIFT (23U) #define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) /*! @} */ /* The count of USB_ENDPTCTRL */ #define USB_ENDPTCTRL_COUNT (8U) /*! * @} */ /* end of group USB_Register_Masks */ /* USB - Peripheral instance base addresses */ /** Peripheral USB base address */ #define USB_BASE (0x32E40000u) /** Peripheral USB base pointer */ #define USB ((USB_Type *)USB_BASE) /** Array initializer of USB peripheral base addresses */ #define USB_BASE_ADDRS \ { \ USB_BASE \ } /** Array initializer of USB peripheral base pointers */ #define USB_BASE_PTRS \ { \ USB \ } /*! * @} */ /* end of group USB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USBNC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer * @{ */ /** USBNC - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[512]; __IO uint32_t OTG1_CTRL1; /**< , offset: 0x200 */ __IO uint32_t OTG1_CTRL2; /**< , offset: 0x204 */ uint8_t RESERVED_1[40]; __IO uint32_t OTG1_PHY_CFG1; /**< USB OTG PHY Configuration Register 1, offset: 0x230 */ __IO uint32_t OTG1_PHY_CFG2; /**< USB OTG PHY Configuration Register 2, offset: 0x234 */ uint8_t RESERVED_2[4]; __I uint32_t OTG1_PHY_STATUS; /**< USB OTG PHY Status Register, offset: 0x23C */ uint8_t RESERVED_3[16]; __IO uint32_t ADP_CFG1; /**< , offset: 0x250 */ __IO uint32_t ADP_CFG2; /**< , offset: 0x254 */ __I uint32_t ADP_STATUS; /**< , offset: 0x258 */ } USBNC_Type; /* ---------------------------------------------------------------------------- -- USBNC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBNC_Register_Masks USBNC Register Masks * @{ */ /*! @name OTG1_CTRL1 - */ /*! @{ */ #define USBNC_OTG1_CTRL1_OVER_CUR_DIS_MASK (0x80U) #define USBNC_OTG1_CTRL1_OVER_CUR_DIS_SHIFT (7U) /*! OVER_CUR_DIS * 0b1..Disables overcurrent detection * 0b0..Enables overcurrent detection */ #define USBNC_OTG1_CTRL1_OVER_CUR_DIS(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_OTG1_CTRL1_OVER_CUR_DIS_MASK) #define USBNC_OTG1_CTRL1_OVER_CUR_POL_MASK (0x100U) #define USBNC_OTG1_CTRL1_OVER_CUR_POL_SHIFT (8U) /*! OVER_CUR_POL * 0b1..Low active (low on this signal represents an overcurrent condition) * 0b0..High active (high on this signal represents an overcurrent condition) */ #define USBNC_OTG1_CTRL1_OVER_CUR_POL(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_OTG1_CTRL1_OVER_CUR_POL_MASK) #define USBNC_OTG1_CTRL1_PWR_POL_MASK (0x200U) #define USBNC_OTG1_CTRL1_PWR_POL_SHIFT (9U) /*! PWR_POL * 0b1..PMIC Power Pin is High active. * 0b0..PMIC Power Pin is Low active. */ #define USBNC_OTG1_CTRL1_PWR_POL(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_PWR_POL_SHIFT)) & USBNC_OTG1_CTRL1_PWR_POL_MASK) #define USBNC_OTG1_CTRL1_WIE_MASK (0x400U) #define USBNC_OTG1_CTRL1_WIE_SHIFT (10U) /*! WIE * 0b1..Interrupt Enabled * 0b0..Interrupt Disabled */ #define USBNC_OTG1_CTRL1_WIE(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_WIE_SHIFT)) & USBNC_OTG1_CTRL1_WIE_MASK) #define USBNC_OTG1_CTRL1_WKUP_SW_EN_MASK (0x4000U) #define USBNC_OTG1_CTRL1_WKUP_SW_EN_SHIFT (14U) /*! WKUP_SW_EN * 0b1..Enable * 0b0..Disable */ #define USBNC_OTG1_CTRL1_WKUP_SW_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_OTG1_CTRL1_WKUP_SW_EN_MASK) #define USBNC_OTG1_CTRL1_WKUP_SW_MASK (0x8000U) #define USBNC_OTG1_CTRL1_WKUP_SW_SHIFT (15U) /*! WKUP_SW * 0b1..Force wake-up * 0b0..Inactive */ #define USBNC_OTG1_CTRL1_WKUP_SW(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_WKUP_SW_SHIFT)) & USBNC_OTG1_CTRL1_WKUP_SW_MASK) #define USBNC_OTG1_CTRL1_WKUP_ID_EN_MASK (0x10000U) #define USBNC_OTG1_CTRL1_WKUP_ID_EN_SHIFT (16U) /*! WKUP_ID_EN * 0b1..Enable * 0b0..Disable */ #define USBNC_OTG1_CTRL1_WKUP_ID_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_OTG1_CTRL1_WKUP_ID_EN_MASK) #define USBNC_OTG1_CTRL1_WKUP_VBUS_EN_MASK (0x20000U) #define USBNC_OTG1_CTRL1_WKUP_VBUS_EN_SHIFT (17U) /*! WKUP_VBUS_EN * 0b1..Enable * 0b0..Disable */ #define USBNC_OTG1_CTRL1_WKUP_VBUS_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_OTG1_CTRL1_WKUP_VBUS_EN_MASK) #define USBNC_OTG1_CTRL1_WKUP_DPDM_EN_MASK (0x20000000U) #define USBNC_OTG1_CTRL1_WKUP_DPDM_EN_SHIFT (29U) /*! WKUP_DPDM_EN * 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only. * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0. */ #define USBNC_OTG1_CTRL1_WKUP_DPDM_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_OTG1_CTRL1_WKUP_DPDM_EN_MASK) #define USBNC_OTG1_CTRL1_WIR_MASK (0x80000000U) #define USBNC_OTG1_CTRL1_WIR_SHIFT (31U) /*! WIR * 0b1..Wake-up Interrupt Request received * 0b0..No wake-up interrupt request received */ #define USBNC_OTG1_CTRL1_WIR(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_WIR_SHIFT)) & USBNC_OTG1_CTRL1_WIR_MASK) /*! @} */ /*! @name OTG1_CTRL2 - */ /*! @{ */ #define USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_MASK (0x3U) #define USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_SHIFT (0U) #define USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_MASK) #define USBNC_OTG1_CTRL2_AUTURESUME_EN_MASK (0x4U) #define USBNC_OTG1_CTRL2_AUTURESUME_EN_SHIFT (2U) /*! AUTURESUME_EN - Auto Resume Enable * 0b0..Default */ #define USBNC_OTG1_CTRL2_AUTURESUME_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_OTG1_CTRL2_AUTURESUME_EN_MASK) #define USBNC_OTG1_CTRL2_LOWSPEED_EN_MASK (0x8U) #define USBNC_OTG1_CTRL2_LOWSPEED_EN_SHIFT (3U) /*! LOWSPEED_EN * 0b0..Default */ #define USBNC_OTG1_CTRL2_LOWSPEED_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_OTG1_CTRL2_LOWSPEED_EN_MASK) #define USBNC_OTG1_CTRL2_TERMSEL_OVERRIDE_MASK (0x10U) #define USBNC_OTG1_CTRL2_TERMSEL_OVERRIDE_SHIFT (4U) #define USBNC_OTG1_CTRL2_TERMSEL_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_TERMSEL_OVERRIDE_SHIFT)) & USBNC_OTG1_CTRL2_TERMSEL_OVERRIDE_MASK) #define USBNC_OTG1_CTRL2_TERMSEL_OVERRIDEEN_MASK (0x20U) #define USBNC_OTG1_CTRL2_TERMSEL_OVERRIDEEN_SHIFT (5U) /*! TERMSEL_OVERRIDEEN * 0b0..The state of the UTMI TermSelect signal to the USB PHY is set by the USB controller. * 0b1..The state of the UTMI TermSelect signal to the USB PHY is set by the value in the * USBNC_x_CTRL2[TERMSEL_OVERRIDE] bit field. */ #define USBNC_OTG1_CTRL2_TERMSEL_OVERRIDEEN(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_TERMSEL_OVERRIDEEN_SHIFT)) & \ USBNC_OTG1_CTRL2_TERMSEL_OVERRIDEEN_MASK) #define USBNC_OTG1_CTRL2_OPMODE_OVERRIDE_MASK (0xC0U) #define USBNC_OTG1_CTRL2_OPMODE_OVERRIDE_SHIFT (6U) #define USBNC_OTG1_CTRL2_OPMODE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_OPMODE_OVERRIDE_SHIFT)) & USBNC_OTG1_CTRL2_OPMODE_OVERRIDE_MASK) #define USBNC_OTG1_CTRL2_OPMODE_OVERRIDEEN_MASK (0x100U) #define USBNC_OTG1_CTRL2_OPMODE_OVERRIDEEN_SHIFT (8U) /*! OPMODE_OVERRIDEEN * 0b0..The state of the UTMI OpMode signals to the USB PHY is set by the USB controller. * 0b1..The state of the UTMI OpMode signals to the USB PHY is set by the values in the USBNC_x_CTRL2[OPMODE_OVERRIDE] * bit field. */ #define USBNC_OTG1_CTRL2_OPMODE_OVERRIDEEN(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_OPMODE_OVERRIDEEN_SHIFT)) & \ USBNC_OTG1_CTRL2_OPMODE_OVERRIDEEN_MASK) #define USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDE_MASK (0x600U) #define USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDE_SHIFT (9U) #define USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDE_SHIFT)) & USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDE_MASK) #define USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDEEN_MASK (0x800U) #define USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDEEN_SHIFT (11U) /*! XCVRSEL_OVERRIDEEN * 0b0..The state of the UTMI XcvrSelect signals to the USB PHY is set by the USB controller. * 0b1..The state of the UTMI XcvrSelect signals to the USB PHY is set by the values in the * USBNC_x_CTRL2[XCVRSEL_OVERRIDE] bit field. */ #define USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDEEN(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDEEN_SHIFT)) & \ USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDEEN_MASK) #define USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDE_MASK (0x1000U) #define USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDE_SHIFT (12U) /*! DPPULLDOWN_OVERRIDE * 0b0..DP pulldown resistor disabled * 0b1..DP pulldown resistor enabled */ #define USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDE_SHIFT)) & \ USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDE_MASK) #define USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDEEN_MASK (0x2000U) #define USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDEEN_SHIFT (13U) /*! DPPULLDOWN_OVERRIDEEN * 0b0..USB controller enables/disables the DP pulldown resistor in the USB PHY. * 0b1..Use the value set by the USBNC_n_CTRL2[DPPULLDOWN_OVERRIDE] bit field to enable/disable the DP pulldown * resistor in the USB PHY. */ #define USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDEEN(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDEEN_SHIFT)) & \ USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDEEN_MASK) #define USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDE_MASK (0x4000U) #define USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDE_SHIFT (14U) /*! DMPULLDOWN_OVERRIDE * 0b0..DM pulldown resistor disabled * 0b1..DM pulldown resistor enabled */ #define USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDE_SHIFT)) & \ USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDE_MASK) #define USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDEEN_MASK (0x8000U) #define USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDEEN_SHIFT (15U) /*! DMPULLDOWN_OVERRIDEEN * 0b0..USB controller enables/disables the DM pulldown resistor in the USB PHY. * 0b1..Use the value set by the USBNC_n_CTRL2[DMPULLDOWN_OVERRIDE] bit field to enable/disable the DM pulldown * resistor in the USB PHY. */ #define USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDEEN(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDEEN_SHIFT)) & \ USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDEEN_MASK) #define USBNC_OTG1_CTRL2_DIG_ID_SEL_MASK (0x100000U) #define USBNC_OTG1_CTRL2_DIG_ID_SEL_SHIFT (20U) /*! DIG_ID_SEL * 0b0..Use the USB_OTG*_ID pin for the USB OTG ID pin detection function(default) * 0b1..Use the pin configured by the IOMUXC_USB_OTG*_ID_SELECT_INPUT register for the USB OTG ID pin detection * function */ #define USBNC_OTG1_CTRL2_DIG_ID_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_DIG_ID_SEL_SHIFT)) & USBNC_OTG1_CTRL2_DIG_ID_SEL_MASK) #define USBNC_OTG1_CTRL2_UTMI_CLK_VLD_MASK (0x80000000U) #define USBNC_OTG1_CTRL2_UTMI_CLK_VLD_SHIFT (31U) /*! UTMI_CLK_VLD * 0b0..UTMI clock to USB PHY is not toggling (Default) * 0b1..UTMI clock to USB PHY has toggled several times */ #define USBNC_OTG1_CTRL2_UTMI_CLK_VLD(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_OTG1_CTRL2_UTMI_CLK_VLD_MASK) /*! @} */ /*! @name OTG1_PHY_CFG1 - USB OTG PHY Configuration Register 1 */ /*! @{ */ #define USBNC_OTG1_PHY_CFG1_COMMONONN_MASK (0x1U) #define USBNC_OTG1_PHY_CFG1_COMMONONN_SHIFT (0U) /*! COMMONONN - Common Block Power-Down Control * 0b0..In Suspend or Sleep modes, the Bias and PLL blocks remain powered * 0b1..In Suspend or Sleep modes, the Bias and PLL blocks are powered down * 0b0.. */ #define USBNC_OTG1_PHY_CFG1_COMMONONN(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_COMMONONN_SHIFT)) & USBNC_OTG1_PHY_CFG1_COMMONONN_MASK) #define USBNC_OTG1_PHY_CFG1_FSEL_MASK (0xEU) #define USBNC_OTG1_PHY_CFG1_FSEL_SHIFT (1U) /*! FSEL - Reference Clock Frequency Select * 0b000..9.6 MHz * 0b001..10 MHz * 0b010..12 MHz * 0b011..19.2 MHz * 0b100..20 MHz * 0b101..24 MHz (only valid setting for this SOC) * 0b110..Reserved * 0b111..50 MHz */ #define USBNC_OTG1_PHY_CFG1_FSEL(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_FSEL_SHIFT)) & USBNC_OTG1_PHY_CFG1_FSEL_MASK) #define USBNC_OTG1_PHY_CFG1_COMPDISTUNE0_MASK (0x70U) #define USBNC_OTG1_PHY_CFG1_COMPDISTUNE0_SHIFT (4U) /*! COMPDISTUNE0 - Disconnect Threshold Adjustment * 0b000..-6% * 0b001..-4.5% * 0b010..-3% * 0b011..-1.5% * 0b100..Design default * 0b101..+1.5% * 0b110..+3% * 0b111..+4.5% */ #define USBNC_OTG1_PHY_CFG1_COMPDISTUNE0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_COMPDISTUNE0_SHIFT)) & USBNC_OTG1_PHY_CFG1_COMPDISTUNE0_MASK) #define USBNC_OTG1_PHY_CFG1_SQRXTUNE0_MASK (0x380U) #define USBNC_OTG1_PHY_CFG1_SQRXTUNE0_SHIFT (7U) /*! SQRXTUNE0 - Squelch Threshold Adjustment * 0b000..+15% * 0b001..+10% * 0b010..+5% * 0b011..Design default * 0b100..-5% * 0b101..-10% * 0b110..-15% * 0b111..-20% */ #define USBNC_OTG1_PHY_CFG1_SQRXTUNE0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_SQRXTUNE0_SHIFT)) & USBNC_OTG1_PHY_CFG1_SQRXTUNE0_MASK) #define USBNC_OTG1_PHY_CFG1_OTGTUNE0_MASK (0x1C00U) #define USBNC_OTG1_PHY_CFG1_OTGTUNE0_SHIFT (10U) /*! OTGTUNE0 - VBUS Valid Threshold Adjustment * 0b000..-6% * 0b001..-4.5% * 0b010..-3% * 0b011..-1.5% * 0b100..Design default * 0b101..+1.5% * 0b110..+3% * 0b111..+4.5% */ #define USBNC_OTG1_PHY_CFG1_OTGTUNE0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_OTGTUNE0_SHIFT)) & USBNC_OTG1_PHY_CFG1_OTGTUNE0_MASK) #define USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0_MASK (0x6000U) #define USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0_SHIFT (13U) /*! TXHSXVTUNE0 - Transmitter High-Speed Crossover Adjustment * 0b00..Reserved * 0b01..-15mV * 0b10..+15mV * 0b11..Design default */ #define USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0_SHIFT)) & USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0_MASK) #define USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0_MASK (0xF0000U) #define USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0_SHIFT (16U) /*! TXFSLSTUNE0 - FS/LS Source Impedance Adjustment * 0b0000..+5% * 0b0001..+2.5% * 0b0011..Design default * 0b0111..-2.5% * 0b1111..-5% */ #define USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0_SHIFT)) & USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0_MASK) #define USBNC_OTG1_PHY_CFG1_TXVREFTUNE0_MASK (0xF00000U) #define USBNC_OTG1_PHY_CFG1_TXVREFTUNE0_SHIFT (20U) /*! TXVREFTUNE0 - HS DC Voltage Level Adjustment * 0b0000..-6% * 0b0001..-4% * 0b0010..-2% * 0b0011..Design default * 0b0100..+2% * 0b0101..+4% * 0b0110..+6% * 0b0111..+8% * 0b1000..+10% * 0b1001..+12% * 0b1010..+14% * 0b1011..+16% * 0b1100..+18% * 0b1101..+20% * 0b1110..+22% * 0b1111..+24% */ #define USBNC_OTG1_PHY_CFG1_TXVREFTUNE0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_TXVREFTUNE0_SHIFT)) & USBNC_OTG1_PHY_CFG1_TXVREFTUNE0_MASK) #define USBNC_OTG1_PHY_CFG1_TXRISETUNE0_MASK (0x3000000U) #define USBNC_OTG1_PHY_CFG1_TXRISETUNE0_SHIFT (24U) /*! TXRISETUNE0 - HS Transmitter Rise/Fall Time Adjustment * 0b00..-10% * 0b01..Design default * 0b10..+15% * 0b11..+20% */ #define USBNC_OTG1_PHY_CFG1_TXRISETUNE0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_TXRISETUNE0_SHIFT)) & USBNC_OTG1_PHY_CFG1_TXRISETUNE0_MASK) #define USBNC_OTG1_PHY_CFG1_TXRESTUNE0_MASK (0xC000000U) #define USBNC_OTG1_PHY_CFG1_TXRESTUNE0_SHIFT (26U) /*! TXRESTUNE0 - USB Source Impedance Adjustment * 0b00..Source impedance is increased by approximately 1.5 ohm * 0b01..Design default * 0b10..Source impedance is decreased by approximately 2 ohm * 0b11..Source impedance is decreased by approximately 4 ohm */ #define USBNC_OTG1_PHY_CFG1_TXRESTUNE0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_TXRESTUNE0_SHIFT)) & USBNC_OTG1_PHY_CFG1_TXRESTUNE0_MASK) #define USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0_MASK (0x30000000U) #define USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0_SHIFT (28U) /*! TXPREEMPAMPTUNE0 - HS Treansmitter Pre-Emphasis Current Control * 0b00..HS Transmitter pre-emphasis is disabled * 0b01..HS Transmitter pre-emphasis circuit sources 1X pre-emphasis current (design default) * 0b10..HS Transmitter pre-emphasis circuit sources 2X pre-emphasis current * 0b11..HS Transmitter pre-emphasis circuit sources 3X pre-emphasis current */ #define USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0_SHIFT)) & \ USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0_MASK) #define USBNC_OTG1_PHY_CFG1_TXPREEMPPULSETUNE0_MASK (0x40000000U) #define USBNC_OTG1_PHY_CFG1_TXPREEMPPULSETUNE0_SHIFT (30U) /*! TXPREEMPPULSETUNE0 - HS Transmitter Pre-Emphasis Duration Control * 0b0..2X, long pre-emphasis current duration (design default) * 0b1..1X, short pre-emphasis current duration */ #define USBNC_OTG1_PHY_CFG1_TXPREEMPPULSETUNE0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_TXPREEMPPULSETUNE0_SHIFT)) & \ USBNC_OTG1_PHY_CFG1_TXPREEMPPULSETUNE0_MASK) #define USBNC_OTG1_PHY_CFG1_CHRGDET_Megamix_MASK (0x80000000U) #define USBNC_OTG1_PHY_CFG1_CHRGDET_Megamix_SHIFT (31U) /*! CHRGDET_Megamix - USB_OTG1_CHD_B output control * 0b0..The external state of USB_OTG1_CHD_B is only controlled by the state of the CHRGDET signal * 0b1..The external state of USB_OTG1_CHD_B is forced low */ #define USBNC_OTG1_PHY_CFG1_CHRGDET_Megamix(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_CHRGDET_Megamix_SHIFT)) & \ USBNC_OTG1_PHY_CFG1_CHRGDET_Megamix_MASK) /*! @} */ /*! @name OTG1_PHY_CFG2 - USB OTG PHY Configuration Register 2 */ /*! @{ */ #define USBNC_OTG1_PHY_CFG2_CHRGSEL_MASK (0x1U) #define USBNC_OTG1_PHY_CFG2_CHRGSEL_SHIFT (0U) /*! CHRGSEL - Battery Charging Source Select * 0b0..VDP_SRC is connected to USB_OTG*_DP and IDM_SINK is connected to USB_OTG*_DN. Used for Primary Detection. * 0b1..VDM_SRC is connected to USB_OTG*_DN and IDP_SINK is connected to USB_OTG*_DP. Used for Secondary Detection. */ #define USBNC_OTG1_PHY_CFG2_CHRGSEL(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_CHRGSEL_SHIFT)) & USBNC_OTG1_PHY_CFG2_CHRGSEL_MASK) #define USBNC_OTG1_PHY_CFG2_VDATDETENB0_MASK (0x2U) #define USBNC_OTG1_PHY_CFG2_VDATDETENB0_SHIFT (1U) /*! VDATDETENB0 - Battery Charging Detection Comparator Enable * 0b0..Battery Charging detection comparator connected to USB_OTG*_D* pin is disabled * 0b1..Battery Charging detection comparator connected to USB_OTG*_D* pin is enabled */ #define USBNC_OTG1_PHY_CFG2_VDATDETENB0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_VDATDETENB0_SHIFT)) & USBNC_OTG1_PHY_CFG2_VDATDETENB0_MASK) #define USBNC_OTG1_PHY_CFG2_VDATSRCENB0_MASK (0x4U) #define USBNC_OTG1_PHY_CFG2_VDATSRCENB0_SHIFT (2U) /*! VDATSRCENB0 - Battery Charging Source Select * 0b0..VD*_SRC and ID*_SINK are disabled * 0b1..VD*_SRC and ID*_SINK are enabled */ #define USBNC_OTG1_PHY_CFG2_VDATSRCENB0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_VDATSRCENB0_SHIFT)) & USBNC_OTG1_PHY_CFG2_VDATSRCENB0_MASK) #define USBNC_OTG1_PHY_CFG2_DCDENB_MASK (0x8U) #define USBNC_OTG1_PHY_CFG2_DCDENB_SHIFT (3U) /*! DCDENB - Data Contact Detection Enable * 0b0..IDP_SRC current and RDM_DWN pull-down resistance are disabled * 0b1..IDP_SRC current and RDM_DWN pull-down resistance are enabled */ #define USBNC_OTG1_PHY_CFG2_DCDENB(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_DCDENB_SHIFT)) & USBNC_OTG1_PHY_CFG2_DCDENB_MASK) #define USBNC_OTG1_PHY_CFG2_ACAENB0_MASK (0x10U) #define USBNC_OTG1_PHY_CFG2_ACAENB0_SHIFT (4U) /*! ACAENB0 - ACA USB_OTG*_ID Pin Resistance Detection Enable * 0b0..Disables detection of resistance on the USB_OTG*_ID pin * 0b1..Enables detection of resistance on the USB_OTG*_ID pin */ #define USBNC_OTG1_PHY_CFG2_ACAENB0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_ACAENB0_SHIFT)) & USBNC_OTG1_PHY_CFG2_ACAENB0_MASK) #define USBNC_OTG1_PHY_CFG2_SLEEPM0_MASK (0x20U) #define USBNC_OTG1_PHY_CFG2_SLEEPM0_SHIFT (5U) /*! SLEEPM0 - Sleep Mode Assertion * 0b0..Sleep mode * 0b1..Normal operating mode */ #define USBNC_OTG1_PHY_CFG2_SLEEPM0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_SLEEPM0_SHIFT)) & USBNC_OTG1_PHY_CFG2_SLEEPM0_MASK) #define USBNC_OTG1_PHY_CFG2_LOOPBACKENB0_MASK (0x40U) #define USBNC_OTG1_PHY_CFG2_LOOPBACKENB0_SHIFT (6U) /*! LOOPBACKENB0 - Loopback Test Enable * 0b0..During data transmission, the receive logic is disabled * 0b1..During data transmission, the receive logic is enabled */ #define USBNC_OTG1_PHY_CFG2_LOOPBACKENB0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_LOOPBACKENB0_SHIFT)) & USBNC_OTG1_PHY_CFG2_LOOPBACKENB0_MASK) #define USBNC_OTG1_PHY_CFG2_TXBITSTUFFEN0_MASK (0x100U) #define USBNC_OTG1_PHY_CFG2_TXBITSTUFFEN0_SHIFT (8U) /*! TXBITSTUFFEN0 - Low-Byte Transmit Bit-Stuffing Enable * 0b0..Bit stuffing is disabled * 0b1..Bit stuffing is enabled */ #define USBNC_OTG1_PHY_CFG2_TXBITSTUFFEN0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_TXBITSTUFFEN0_SHIFT)) & USBNC_OTG1_PHY_CFG2_TXBITSTUFFEN0_MASK) #define USBNC_OTG1_PHY_CFG2_TXBITSTUFFENH0_MASK (0x200U) #define USBNC_OTG1_PHY_CFG2_TXBITSTUFFENH0_SHIFT (9U) /*! TXBITSTUFFENH0 - High-Byte Transmit Bit-Stuffing Enable * 0b0..Bit stuffing is disabled * 0b1..Bit stuffing is enabled */ #define USBNC_OTG1_PHY_CFG2_TXBITSTUFFENH0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_TXBITSTUFFENH0_SHIFT)) & \ USBNC_OTG1_PHY_CFG2_TXBITSTUFFENH0_MASK) #define USBNC_OTG1_PHY_CFG2_OTGDISABLE0_MASK (0x400U) #define USBNC_OTG1_PHY_CFG2_OTGDISABLE0_SHIFT (10U) /*! OTGDISABLE0 - OTG Block Disable * 0b0..The OTG block is powered up * 0b1..The OTG block is powered down */ #define USBNC_OTG1_PHY_CFG2_OTGDISABLE0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_OTGDISABLE0_SHIFT)) & USBNC_OTG1_PHY_CFG2_OTGDISABLE0_MASK) #define USBNC_OTG1_PHY_CFG2_ADPCHRG0_MASK (0x800U) #define USBNC_OTG1_PHY_CFG2_ADPCHRG0_SHIFT (11U) /*! ADPCHRG0 - VBUS Input ADP Charge Enable * 0b0..Disables charging USB_OTG*_VBUS during ADP * 0b1..Disables charging USB_OTG*_VBUS during ADP */ #define USBNC_OTG1_PHY_CFG2_ADPCHRG0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_ADPCHRG0_SHIFT)) & USBNC_OTG1_PHY_CFG2_ADPCHRG0_MASK) #define USBNC_OTG1_PHY_CFG2_ADPDISCHRG0_MASK (0x1000U) #define USBNC_OTG1_PHY_CFG2_ADPDISCHRG0_SHIFT (12U) /*! ADPDISCHRG0 - VBUS Input ADP Discharge Enable * 0b0..Disables discharging USB_OTG*_VBUS during ADP * 0b1..Enables discharging USB_OTG*_VBUS during ADP */ #define USBNC_OTG1_PHY_CFG2_ADPDISCHRG0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_ADPDISCHRG0_SHIFT)) & USBNC_OTG1_PHY_CFG2_ADPDISCHRG0_MASK) #define USBNC_OTG1_PHY_CFG2_ADPPRBENB0_MASK (0x2000U) #define USBNC_OTG1_PHY_CFG2_ADPPRBENB0_SHIFT (13U) /*! ADPPRBENB0 - ADP Probe Enable * 0b0..ADP Probe comparator is disabled * 0b1..ADP Probe comparator is enabled */ #define USBNC_OTG1_PHY_CFG2_ADPPRBENB0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_ADPPRBENB0_SHIFT)) & USBNC_OTG1_PHY_CFG2_ADPPRBENB0_MASK) #define USBNC_OTG1_PHY_CFG2_VBUSVLDEXTSEL0_MASK (0x4000U) #define USBNC_OTG1_PHY_CFG2_VBUSVLDEXTSEL0_SHIFT (14U) /*! VBUSVLDEXTSEL0 - External VBUS Valid Select * 0b0..The USB OTG PHY internal Session Valid comparator is used to enable the pull-up resistor on the USB_OTG*_DP pin * 0b1..The VBUSVLDEXT signal is used to enable the pull-up resistor on the USB_OTG*_DP pin */ #define USBNC_OTG1_PHY_CFG2_VBUSVLDEXTSEL0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_VBUSVLDEXTSEL0_SHIFT)) & \ USBNC_OTG1_PHY_CFG2_VBUSVLDEXTSEL0_MASK) #define USBNC_OTG1_PHY_CFG2_VBUSVLDEXT_MASK (0x8000U) #define USBNC_OTG1_PHY_CFG2_VBUSVLDEXT_SHIFT (15U) /*! VBUSVLDEXT - External VBUS Valid Indicator * 0b0..The VBUS signal sensed outside the USB OTG PHY is not valid, and the pull-up resistor on USB_OTG*_DP is * disabled 0b1..The VBUS signal sensed outside the USB OTG PHY is valid, and the pull-up resistor on USB_OTG*_DP is * enabled */ #define USBNC_OTG1_PHY_CFG2_VBUSVLDEXT(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_VBUSVLDEXT_SHIFT)) & USBNC_OTG1_PHY_CFG2_VBUSVLDEXT_MASK) #define USBNC_OTG1_PHY_CFG2_DRVVBUS0_MASK (0x10000U) #define USBNC_OTG1_PHY_CFG2_DRVVBUS0_SHIFT (16U) /*! DRVVBUS0 - VBUS Valid Comparator Enable * 0b0..The VBUS Valid comparator is disabled * 0b1..The VBUS Valid comparator is enabled */ #define USBNC_OTG1_PHY_CFG2_DRVVBUS0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_DRVVBUS0_SHIFT)) & USBNC_OTG1_PHY_CFG2_DRVVBUS0_MASK) /*! @} */ /*! @name OTG1_PHY_STATUS - USB OTG PHY Status Register */ /*! @{ */ #define USBNC_OTG1_PHY_STATUS_LINE_STATE_MASK (0x3U) #define USBNC_OTG1_PHY_STATUS_LINE_STATE_SHIFT (0U) /*! LINE_STATE - Line State Indicator outputs from USB OTG PHY * 0b00..SE0 (DP low, DN low) * 0b01..J state for high-speed and full-speed USB traffic; K state for low-speed USB traffic (DP high, DN low) * 0b10..K state for high-speed and full-speed USB traffic; J state for low-speed USB traffic (DP low, DN high) * 0b11..SE1 (DP high, DN high) */ #define USBNC_OTG1_PHY_STATUS_LINE_STATE(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_LINE_STATE_SHIFT)) & USBNC_OTG1_PHY_STATUS_LINE_STATE_MASK) #define USBNC_OTG1_PHY_STATUS_SESS_VLD_MASK (0x4U) #define USBNC_OTG1_PHY_STATUS_SESS_VLD_SHIFT (2U) /*! SESS_VLD - OTG Device Session Valid Indicator from USB OTG PHY * 0b0..The voltage on USB_OTG*_VBUS is below the OTG Device Session Valid threshold * 0b1..The voltage on USB_OTG*_VBUS is above the OTG Device Session Valid threshold */ #define USBNC_OTG1_PHY_STATUS_SESS_VLD(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_SESS_VLD_SHIFT)) & USBNC_OTG1_PHY_STATUS_SESS_VLD_MASK) #define USBNC_OTG1_PHY_STATUS_VBUS_VLD_MASK (0x8U) #define USBNC_OTG1_PHY_STATUS_VBUS_VLD_SHIFT (3U) /*! VBUS_VLD - VBUS Valid Indicator from USB OTG PHY * 0b0..The voltage on USB_OTG*_VBUS is below the VBUS Valid threshold * 0b1..The voltage on USB_OTG*_VBUS is above the VBUS Valid threshold */ #define USBNC_OTG1_PHY_STATUS_VBUS_VLD(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_VBUS_VLD_SHIFT)) & USBNC_OTG1_PHY_STATUS_VBUS_VLD_MASK) #define USBNC_OTG1_PHY_STATUS_ID_DIG_MASK (0x10U) #define USBNC_OTG1_PHY_STATUS_ID_DIG_SHIFT (4U) /*! ID_DIG - Micro- or Mini- A/B Plug Indicator * 0b0..The connnected plug is a Micro- or Mini-A plug * 0b1..The connnected plug is a Micro- or Mini-B plug */ #define USBNC_OTG1_PHY_STATUS_ID_DIG(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_ID_DIG_SHIFT)) & USBNC_OTG1_PHY_STATUS_ID_DIG_MASK) #define USBNC_OTG1_PHY_STATUS_HOST_DISCONNECT_MASK (0x20U) #define USBNC_OTG1_PHY_STATUS_HOST_DISCONNECT_SHIFT (5U) /*! HOST_DISCONNECT - Peripheral Disconnect Indicator * 0b0..Peripheral is connected * 0b1..No peripheral is connected */ #define USBNC_OTG1_PHY_STATUS_HOST_DISCONNECT(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_HOST_DISCONNECT_SHIFT)) & \ USBNC_OTG1_PHY_STATUS_HOST_DISCONNECT_MASK) #define USBNC_OTG1_PHY_STATUS_RIDC0_MASK (0x1000000U) #define USBNC_OTG1_PHY_STATUS_RIDC0_SHIFT (24U) /*! RIDC0 - ACA USB_OTG*_ID Pin Resistance Indicator * 0b0..ACA OTG_ID pin resistance is >= RID_B (min) and <= RID_GND max * 0b1..ACA OTG_ID pin resistance is >= RID_C (min) and <= RID_C max */ #define USBNC_OTG1_PHY_STATUS_RIDC0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_RIDC0_SHIFT)) & USBNC_OTG1_PHY_STATUS_RIDC0_MASK) #define USBNC_OTG1_PHY_STATUS_RIDB0_MASK (0x2000000U) #define USBNC_OTG1_PHY_STATUS_RIDB0_SHIFT (25U) /*! RIDB0 - ACA USB_OTG*_ID Pin Resistance Indicator * 0b0..ACA OTG_ID pin resistance is >= RID_A (min) and <= RID_C max * 0b1..ACA OTG_ID pin resistance is >= RID_B (min) and <= RID_B max */ #define USBNC_OTG1_PHY_STATUS_RIDB0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_RIDB0_SHIFT)) & USBNC_OTG1_PHY_STATUS_RIDB0_MASK) #define USBNC_OTG1_PHY_STATUS_RIDA0_MASK (0x4000000U) #define USBNC_OTG1_PHY_STATUS_RIDA0_SHIFT (26U) /*! RIDA0 - ACA USB_OTG*_ID Pin Resistance Indicator * 0b0..ACA OTG_ID pin resistance is >= RID_FLOAT (min) and <= RID_B max * 0b1..ACA OTG_ID pin resistance is >= RID_A (min) and <= RID_A max */ #define USBNC_OTG1_PHY_STATUS_RIDA0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_RIDA0_SHIFT)) & USBNC_OTG1_PHY_STATUS_RIDA0_MASK) #define USBNC_OTG1_PHY_STATUS_RIDGND0_MASK (0x8000000U) #define USBNC_OTG1_PHY_STATUS_RIDGND0_SHIFT (27U) /*! RIDGND0 - ACA USB_OTG*_ID Pin Resistance Indicator * 0b0..ACA OTG_ID pin resistance is >= RID_C (min) * 0b1..ACA OTG_ID pin resistance is <= RID_GND (max) */ #define USBNC_OTG1_PHY_STATUS_RIDGND0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_RIDGND0_SHIFT)) & USBNC_OTG1_PHY_STATUS_RIDGND0_MASK) #define USBNC_OTG1_PHY_STATUS_RIDFLOAT0_MASK (0x10000000U) #define USBNC_OTG1_PHY_STATUS_RIDFLOAT0_SHIFT (28U) /*! RIDFLOAT0 - ACA USB_OTG*_ID Pin Resistance Indicator * 0b0..ACA OTG_ID pin resistance is <= RID_A (max) * 0b1..ACA OTG_ID pin resistance is >= RID_FLOAT (min) */ #define USBNC_OTG1_PHY_STATUS_RIDFLOAT0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_RIDFLOAT0_SHIFT)) & USBNC_OTG1_PHY_STATUS_RIDFLOAT0_MASK) #define USBNC_OTG1_PHY_STATUS_CHRGDET_MASK (0x20000000U) #define USBNC_OTG1_PHY_STATUS_CHRGDET_SHIFT (29U) /*! CHRGDET - Battery Charger Detection Output * 0b0..VD* < VDAT_REF * 0b1..VD* > VDAT_REF */ #define USBNC_OTG1_PHY_STATUS_CHRGDET(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_CHRGDET_SHIFT)) & USBNC_OTG1_PHY_STATUS_CHRGDET_MASK) #define USBNC_OTG1_PHY_STATUS_ADPPRB0_MASK (0x40000000U) #define USBNC_OTG1_PHY_STATUS_ADPPRB0_SHIFT (30U) /*! ADPPRB0 - ADP Probe Indicator * 0b0..The voltage on USB_OTG*_VBUS is below the ADP probing voltage * 0b1..The voltage on USB_OTG*_VBUS is above the ADP probing voltage */ #define USBNC_OTG1_PHY_STATUS_ADPPRB0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_ADPPRB0_SHIFT)) & USBNC_OTG1_PHY_STATUS_ADPPRB0_MASK) #define USBNC_OTG1_PHY_STATUS_ADPSNS0_MASK (0x80000000U) #define USBNC_OTG1_PHY_STATUS_ADPSNS0_SHIFT (31U) /*! ADPSNS0 - ADP Sense Indicator * 0b0..The voltage on USB_OTG*_VBUS is below the ADP sensing voltage * 0b1..The voltage on USB_OTG*_VBUS is above the ADP sensing voltage */ #define USBNC_OTG1_PHY_STATUS_ADPSNS0(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_ADPSNS0_SHIFT)) & USBNC_OTG1_PHY_STATUS_ADPSNS0_MASK) /*! @} */ /*! @name ADP_CFG1 - */ /*! @{ */ #define USBNC_ADP_CFG1_ADP_WAIT_MASK (0x3FFFFU) #define USBNC_ADP_CFG1_ADP_WAIT_SHIFT (0U) /*! ADP_WAIT * 0b001100000000000000..Default */ #define USBNC_ADP_CFG1_ADP_WAIT(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_ADP_WAIT_SHIFT)) & USBNC_ADP_CFG1_ADP_WAIT_MASK) #define USBNC_ADP_CFG1_TIMER_EN_MASK (0x100000U) #define USBNC_ADP_CFG1_TIMER_EN_SHIFT (20U) /*! TIMER_EN - ADP Timer Test Enable * 0b0..Default */ #define USBNC_ADP_CFG1_TIMER_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_TIMER_EN_SHIFT)) & USBNC_ADP_CFG1_TIMER_EN_MASK) #define USBNC_ADP_CFG1_ADP_SNS_INT_EN_MASK (0x200000U) #define USBNC_ADP_CFG1_ADP_SNS_INT_EN_SHIFT (21U) /*! ADP_SNS_INT_EN - ADP Sense Interrupt Enable * 0b0..Default */ #define USBNC_ADP_CFG1_ADP_SNS_INT_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_ADP_SNS_INT_EN_SHIFT)) & USBNC_ADP_CFG1_ADP_SNS_INT_EN_MASK) #define USBNC_ADP_CFG1_ADP_PRB_INT_EN_MASK (0x400000U) #define USBNC_ADP_CFG1_ADP_PRB_INT_EN_SHIFT (22U) /*! ADP_PRB_INT_EN * 0b0..Default */ #define USBNC_ADP_CFG1_ADP_PRB_INT_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_ADP_PRB_INT_EN_SHIFT)) & USBNC_ADP_CFG1_ADP_PRB_INT_EN_MASK) #define USBNC_ADP_CFG1_ADP_PRB_EN_MASK (0x800000U) #define USBNC_ADP_CFG1_ADP_PRB_EN_SHIFT (23U) /*! ADP_PRB_EN * 0b0..Default */ #define USBNC_ADP_CFG1_ADP_PRB_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_ADP_PRB_EN_SHIFT)) & USBNC_ADP_CFG1_ADP_PRB_EN_MASK) /*! @} */ /*! @name ADP_CFG2 - */ /*! @{ */ #define USBNC_ADP_CFG2_ADP_CHRG_DELTA_MASK (0x7FU) #define USBNC_ADP_CFG2_ADP_CHRG_DELTA_SHIFT (0U) /*! ADP_CHRG_DELTA * 0b0010000..Default */ #define USBNC_ADP_CFG2_ADP_CHRG_DELTA(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG2_ADP_CHRG_DELTA_SHIFT)) & USBNC_ADP_CFG2_ADP_CHRG_DELTA_MASK) #define USBNC_ADP_CFG2_ADP_CHRG_SWCMP_MASK (0x80U) #define USBNC_ADP_CFG2_ADP_CHRG_SWCMP_SHIFT (7U) /*! ADP_CHRG_SWCMP * 0b0..Default */ #define USBNC_ADP_CFG2_ADP_CHRG_SWCMP(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG2_ADP_CHRG_SWCMP_SHIFT)) & USBNC_ADP_CFG2_ADP_CHRG_SWCMP_MASK) #define USBNC_ADP_CFG2_ADP_CHRG_SWTIME_MASK (0xFF00U) #define USBNC_ADP_CFG2_ADP_CHRG_SWTIME_SHIFT (8U) /*! ADP_CHRG_SWTIME * 0b01000000..Default */ #define USBNC_ADP_CFG2_ADP_CHRG_SWTIME(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG2_ADP_CHRG_SWTIME_SHIFT)) & USBNC_ADP_CFG2_ADP_CHRG_SWTIME_MASK) #define USBNC_ADP_CFG2_ADP_DISCHG_TIME_MASK (0xFF0000U) #define USBNC_ADP_CFG2_ADP_DISCHG_TIME_SHIFT (16U) /*! ADP_DISCHG_TIME - ADP Discharge time * 0b01000110..Default */ #define USBNC_ADP_CFG2_ADP_DISCHG_TIME(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG2_ADP_DISCHG_TIME_SHIFT)) & USBNC_ADP_CFG2_ADP_DISCHG_TIME_MASK) /*! @} */ /*! @name ADP_STATUS - */ /*! @{ */ #define USBNC_ADP_STATUS_ADP_PRB_TIMR_MASK (0xFFU) #define USBNC_ADP_STATUS_ADP_PRB_TIMR_SHIFT (0U) /*! ADP_PRB_TIMR - ADP Probe Time * 0b00000000..Default */ #define USBNC_ADP_STATUS_ADP_PRB_TIMR(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_STATUS_ADP_PRB_TIMR_SHIFT)) & USBNC_ADP_STATUS_ADP_PRB_TIMR_MASK) #define USBNC_ADP_STATUS_ADP_CNT_MASK (0x3FFFF00U) #define USBNC_ADP_STATUS_ADP_CNT_SHIFT (8U) #define USBNC_ADP_STATUS_ADP_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_STATUS_ADP_CNT_SHIFT)) & USBNC_ADP_STATUS_ADP_CNT_MASK) #define USBNC_ADP_STATUS_ADP_SNS_INT_MASK (0x4000000U) #define USBNC_ADP_STATUS_ADP_SNS_INT_SHIFT (26U) /*! ADP_SNS_INT - ADP Sense Interrupt Status * 0b0..Default */ #define USBNC_ADP_STATUS_ADP_SNS_INT(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_STATUS_ADP_SNS_INT_SHIFT)) & USBNC_ADP_STATUS_ADP_SNS_INT_MASK) #define USBNC_ADP_STATUS_ADP_PRB_INT_MASK (0x8000000U) #define USBNC_ADP_STATUS_ADP_PRB_INT_SHIFT (27U) /*! ADP_PRB_INT - ADP Probe Interrupt Status * 0b0..Default */ #define USBNC_ADP_STATUS_ADP_PRB_INT(x) \ (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_STATUS_ADP_PRB_INT_SHIFT)) & USBNC_ADP_STATUS_ADP_PRB_INT_MASK) /*! @} */ /*! * @} */ /* end of group USBNC_Register_Masks */ /* USBNC - Peripheral instance base addresses */ /** Peripheral USBNC base address */ #define USBNC_BASE (0x32E40000u) /** Peripheral USBNC base pointer */ #define USBNC ((USBNC_Type *)USBNC_BASE) /** Array initializer of USBNC peripheral base addresses */ #define USBNC_BASE_ADDRS \ { \ USBNC_BASE \ } /** Array initializer of USBNC peripheral base pointers */ #define USBNC_BASE_PTRS \ { \ USBNC \ } /*! * @} */ /* end of group USBNC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USDHC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer * @{ */ /** USDHC - Register Layout Typedef */ typedef struct { __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ uint8_t RESERVED_0[4]; __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */ __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ uint8_t RESERVED_1[4]; __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ uint8_t RESERVED_2[4]; __IO uint32_t STROBE_DLL_CTRL; /**< Strobe DLL Control, offset: 0x70 */ __I uint32_t STROBE_DLL_STATUS; /**< Strobe DLL Status, offset: 0x74 */ uint8_t RESERVED_3[72]; __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ __IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */ __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ __IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */ } USDHC_Type; /* ---------------------------------------------------------------------------- -- USDHC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USDHC_Register_Masks USDHC Register Masks * @{ */ /*! @name DS_ADDR - DMA System Address */ /*! @{ */ #define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFCU) #define USDHC_DS_ADDR_DS_ADDR_SHIFT (2U) #define USDHC_DS_ADDR_DS_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) /*! @} */ /*! @name BLK_ATT - Block Attributes */ /*! @{ */ #define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) #define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) /*! BLKSIZE * 0b0000000001000..4096 Bytes * 0b0001100100000..2048 Bytes * 0b0000011001000..512 Bytes * 0b0000000000100..4 Bytes * 0b0000000000011..3 Bytes * 0b0000000000010..2 Bytes * 0b0000000000001..1 Byte * 0b0000000000000..No data transfer */ #define USDHC_BLK_ATT_BLKSIZE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) #define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) #define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) /*! BLKCNT * 0b0000000000000010..2 blocks * 0b0000000000000001..1 block * 0b0000000000000000..Stop Count */ #define USDHC_BLK_ATT_BLKCNT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) /*! @} */ /*! @name CMD_ARG - Command Argument */ /*! @{ */ #define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) #define USDHC_CMD_ARG_CMDARG_SHIFT (0U) #define USDHC_CMD_ARG_CMDARG(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) /*! @} */ /*! @name CMD_XFR_TYP - Command Transfer Type */ /*! @{ */ #define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) /*! RSPTYP - Response Type Select * 0b00..No Response * 0b01..Response Length 136 * 0b10..Response Length 48 * 0b11..Response Length 48, check Busy after response */ #define USDHC_CMD_XFR_TYP_RSPTYP(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) #define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) /*! CCCEN - Command CRC Check Enable * 0b1..Enable * 0b0..Disable */ #define USDHC_CMD_XFR_TYP_CCCEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) #define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) #define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) /*! CICEN - Command Index Check Enable * 0b1..Enable * 0b0..Disable */ #define USDHC_CMD_XFR_TYP_CICEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) #define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) /*! DPSEL - Data Present Select * 0b1..Data Present * 0b0..No Data Present */ #define USDHC_CMD_XFR_TYP_DPSEL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) #define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) /*! CMDTYP - Command Type * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR * 0b10..Resume CMD52 for writing Function Select in CCCR * 0b01..Suspend CMD52 for writing Bus Suspend in CCCR * 0b00..Normal Other commands */ #define USDHC_CMD_XFR_TYP_CMDTYP(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) #define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) #define USDHC_CMD_XFR_TYP_CMDINX(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) /*! @} */ /*! @name CMD_RSP0 - Command Response0 */ /*! @{ */ #define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) #define USDHC_CMD_RSP0_CMDRSP0(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) /*! @} */ /*! @name CMD_RSP1 - Command Response1 */ /*! @{ */ #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) #define USDHC_CMD_RSP1_CMDRSP1(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) /*! @} */ /*! @name CMD_RSP2 - Command Response2 */ /*! @{ */ #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) #define USDHC_CMD_RSP2_CMDRSP2(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) /*! @} */ /*! @name CMD_RSP3 - Command Response3 */ /*! @{ */ #define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) #define USDHC_CMD_RSP3_CMDRSP3(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) /*! @} */ /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ /*! @{ */ #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) /*! @} */ /*! @name PRES_STATE - Present State */ /*! @{ */ #define USDHC_PRES_STATE_CIHB_MASK (0x1U) #define USDHC_PRES_STATE_CIHB_SHIFT (0U) /*! CIHB - Command Inhibit (CMD) * 0b1..Cannot issue command * 0b0..Can issue command using only CMD line */ #define USDHC_PRES_STATE_CIHB(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) #define USDHC_PRES_STATE_CDIHB_MASK (0x2U) #define USDHC_PRES_STATE_CDIHB_SHIFT (1U) /*! CDIHB - Command Inhibit (DATA) * 0b1..Cannot issue command which uses the DATA line * 0b0..Can issue command which uses the DATA line */ #define USDHC_PRES_STATE_CDIHB(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) #define USDHC_PRES_STATE_DLA_MASK (0x4U) #define USDHC_PRES_STATE_DLA_SHIFT (2U) /*! DLA - Data Line Active * 0b1..DATA Line Active * 0b0..DATA Line Inactive */ #define USDHC_PRES_STATE_DLA(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) #define USDHC_PRES_STATE_SDSTB_MASK (0x8U) #define USDHC_PRES_STATE_SDSTB_SHIFT (3U) /*! SDSTB - SD Clock Stable * 0b1..Clock is stable. * 0b0..Clock is changing frequency and not stable. */ #define USDHC_PRES_STATE_SDSTB(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) #define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) #define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) /*! IPGOFF - IPG_CLK Gated Off Internally * 0b1..IPG_CLK is gated off. * 0b0..IPG_CLK is active. */ #define USDHC_PRES_STATE_IPGOFF(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) #define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) #define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) /*! HCKOFF - HCLK Gated Off Internally * 0b1..HCLK is gated off. * 0b0..HCLK is active. */ #define USDHC_PRES_STATE_HCKOFF(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) #define USDHC_PRES_STATE_PEROFF_MASK (0x40U) #define USDHC_PRES_STATE_PEROFF_SHIFT (6U) /*! PEROFF - IPG_PERCLK Gated Off Internally * 0b1..IPG_PERCLK is gated off. * 0b0..IPG_PERCLK is active. */ #define USDHC_PRES_STATE_PEROFF(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) #define USDHC_PRES_STATE_SDOFF_MASK (0x80U) #define USDHC_PRES_STATE_SDOFF_SHIFT (7U) /*! SDOFF - SD Clock Gated Off Internally * 0b1..SD Clock is gated off. * 0b0..SD Clock is active. */ #define USDHC_PRES_STATE_SDOFF(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) #define USDHC_PRES_STATE_WTA_MASK (0x100U) #define USDHC_PRES_STATE_WTA_SHIFT (8U) /*! WTA - Write Transfer Active * 0b1..Transferring data * 0b0..No valid data */ #define USDHC_PRES_STATE_WTA(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) #define USDHC_PRES_STATE_RTA_MASK (0x200U) #define USDHC_PRES_STATE_RTA_SHIFT (9U) /*! RTA - Read Transfer Active * 0b1..Transferring data * 0b0..No valid data */ #define USDHC_PRES_STATE_RTA(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) #define USDHC_PRES_STATE_BWEN_MASK (0x400U) #define USDHC_PRES_STATE_BWEN_SHIFT (10U) /*! BWEN - Buffer Write Enable * 0b1..Write enable * 0b0..Write disable */ #define USDHC_PRES_STATE_BWEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) #define USDHC_PRES_STATE_BREN_MASK (0x800U) #define USDHC_PRES_STATE_BREN_SHIFT (11U) /*! BREN - Buffer Read Enable * 0b1..Read enable * 0b0..Read disable */ #define USDHC_PRES_STATE_BREN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) #define USDHC_PRES_STATE_RTR_MASK (0x1000U) #define USDHC_PRES_STATE_RTR_SHIFT (12U) /*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode) * 0b1..Sampling clock needs re-tuning * 0b0..Fixed or well tuned sampling clock */ #define USDHC_PRES_STATE_RTR(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) #define USDHC_PRES_STATE_TSCD_MASK (0x8000U) #define USDHC_PRES_STATE_TSCD_SHIFT (15U) /*! TSCD - Tape Select Change Done * 0b1..Delay cell select change is finished. * 0b0..Delay cell select change is not finished. */ #define USDHC_PRES_STATE_TSCD(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) #define USDHC_PRES_STATE_CINST_MASK (0x10000U) #define USDHC_PRES_STATE_CINST_SHIFT (16U) /*! CINST - Card Inserted * 0b1..Card Inserted * 0b0..Power on Reset or No Card */ #define USDHC_PRES_STATE_CINST(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) #define USDHC_PRES_STATE_CDPL_MASK (0x40000U) #define USDHC_PRES_STATE_CDPL_SHIFT (18U) /*! CDPL - Card Detect Pin Level * 0b1..Card present (CD_B = 0) * 0b0..No card present (CD_B = 1) */ #define USDHC_PRES_STATE_CDPL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) #define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) #define USDHC_PRES_STATE_WPSPL_SHIFT (19U) /*! WPSPL - Write Protect Switch Pin Level * 0b1..Write enabled (WP = 0) * 0b0..Write protected (WP = 1) */ #define USDHC_PRES_STATE_WPSPL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) #define USDHC_PRES_STATE_CLSL_MASK (0x800000U) #define USDHC_PRES_STATE_CLSL_SHIFT (23U) #define USDHC_PRES_STATE_CLSL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) #define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) #define USDHC_PRES_STATE_DLSL_SHIFT (24U) #define USDHC_PRES_STATE_DLSL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) /*! @} */ /*! @name PROT_CTRL - Protocol Control */ /*! @{ */ #define USDHC_PROT_CTRL_LCTL_MASK (0x1U) #define USDHC_PROT_CTRL_LCTL_SHIFT (0U) /*! LCTL - LED Control * 0b1..LED on * 0b0..LED off */ #define USDHC_PROT_CTRL_LCTL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) #define USDHC_PROT_CTRL_DTW_MASK (0x6U) #define USDHC_PROT_CTRL_DTW_SHIFT (1U) /*! DTW - Data Transfer Width * 0b10..8-bit mode * 0b01..4-bit mode * 0b00..1-bit mode * 0b11..Reserved */ #define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) #define USDHC_PROT_CTRL_D3CD_MASK (0x8U) #define USDHC_PROT_CTRL_D3CD_SHIFT (3U) /*! D3CD - DATA3 as Card Detection Pin * 0b1..DATA3 as Card Detection Pin * 0b0..DATA3 does not monitor Card Insertion */ #define USDHC_PROT_CTRL_D3CD(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) #define USDHC_PROT_CTRL_EMODE_MASK (0x30U) #define USDHC_PROT_CTRL_EMODE_SHIFT (4U) /*! EMODE - Endian Mode * 0b00..Big Endian Mode * 0b01..Half Word Big Endian Mode * 0b10..Little Endian Mode * 0b11..Reserved */ #define USDHC_PROT_CTRL_EMODE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) #define USDHC_PROT_CTRL_CDTL_MASK (0x40U) #define USDHC_PROT_CTRL_CDTL_SHIFT (6U) /*! CDTL - Card Detect Test Level * 0b1..Card Detect Test Level is 1, card inserted * 0b0..Card Detect Test Level is 0, no card inserted */ #define USDHC_PROT_CTRL_CDTL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) #define USDHC_PROT_CTRL_CDSS_MASK (0x80U) #define USDHC_PROT_CTRL_CDSS_SHIFT (7U) /*! CDSS - Card Detect Signal Selection * 0b1..Card Detection Test Level is selected (for test purpose). * 0b0..Card Detection Level is selected (for normal purpose). */ #define USDHC_PROT_CTRL_CDSS(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) #define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) #define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) /*! DMASEL - DMA Select * 0b00..No DMA or Simple DMA is selected * 0b01..ADMA1 is selected * 0b10..ADMA2 is selected * 0b11..reserved */ #define USDHC_PROT_CTRL_DMASEL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) #define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) #define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) /*! SABGREQ - Stop At Block Gap Request * 0b1..Stop * 0b0..Transfer */ #define USDHC_PROT_CTRL_SABGREQ(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) #define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) #define USDHC_PROT_CTRL_CREQ_SHIFT (17U) /*! CREQ - Continue Request * 0b1..Restart * 0b0..No effect */ #define USDHC_PROT_CTRL_CREQ(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) #define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) #define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) /*! RWCTL - Read Wait Control * 0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set * 0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set */ #define USDHC_PROT_CTRL_RWCTL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) #define USDHC_PROT_CTRL_IABG_MASK (0x80000U) #define USDHC_PROT_CTRL_IABG_SHIFT (19U) /*! IABG - Interrupt At Block Gap * 0b1..Enabled * 0b0..Disabled */ #define USDHC_PROT_CTRL_IABG(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) #define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) #define USDHC_PROT_CTRL_WECINT_SHIFT (24U) /*! WECINT - Wakeup Event Enable On Card Interrupt * 0b1..Enable * 0b0..Disable */ #define USDHC_PROT_CTRL_WECINT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) #define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) #define USDHC_PROT_CTRL_WECINS_SHIFT (25U) /*! WECINS - Wakeup Event Enable On SD Card Insertion * 0b1..Enable * 0b0..Disable */ #define USDHC_PROT_CTRL_WECINS(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) #define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) #define USDHC_PROT_CTRL_WECRM_SHIFT (26U) /*! WECRM - Wakeup Event Enable On SD Card Removal * 0b1..Enable * 0b0..Disable */ #define USDHC_PROT_CTRL_WECRM(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) #define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U) #define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U) /*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP * 0bxx1..Burst length is enabled for INCR * 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16 * 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP */ #define USDHC_PROT_CTRL_BURST_LEN_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK) #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) /*! NON_EXACT_BLK_RD * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block * read. 0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this * multi-block read. */ #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) /*! @} */ /*! @name SYS_CTRL - System Control */ /*! @{ */ #define USDHC_SYS_CTRL_DVS_MASK (0xF0U) #define USDHC_SYS_CTRL_DVS_SHIFT (4U) /*! DVS - Divisor * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) #define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) #define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) #define USDHC_SYS_CTRL_SDCLKFS(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) #define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) #define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) /*! DTOCV - Data Timeout Counter Value * 0b1111..SDCLK x 2 29 * 0b1110..SDCLK x 2 28 * 0b0001..SDCLK x 2 15 * 0b0000..SDCLK x 2 14 */ #define USDHC_SYS_CTRL_DTOCV(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) #define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) #define USDHC_SYS_CTRL_IPP_RST_N(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) #define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) #define USDHC_SYS_CTRL_RSTA_SHIFT (24U) /*! RSTA - Software Reset For ALL * 0b1..Reset * 0b0..No Reset */ #define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) #define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) #define USDHC_SYS_CTRL_RSTC_SHIFT (25U) /*! RSTC - Software Reset For CMD Line * 0b1..Reset * 0b0..No Reset */ #define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) #define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) #define USDHC_SYS_CTRL_RSTD_SHIFT (26U) /*! RSTD - Software Reset For DATA Line * 0b1..Reset * 0b0..No Reset */ #define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) #define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) #define USDHC_SYS_CTRL_INITA_SHIFT (27U) #define USDHC_SYS_CTRL_INITA(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) #define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) #define USDHC_SYS_CTRL_RSTT_SHIFT (28U) #define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) /*! @} */ /*! @name INT_STATUS - Interrupt Status */ /*! @{ */ #define USDHC_INT_STATUS_CC_MASK (0x1U) #define USDHC_INT_STATUS_CC_SHIFT (0U) /*! CC - Command Complete * 0b1..Command complete * 0b0..Command not complete */ #define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) #define USDHC_INT_STATUS_TC_MASK (0x2U) #define USDHC_INT_STATUS_TC_SHIFT (1U) /*! TC - Transfer Complete * 0b1..Transfer complete * 0b0..Transfer not complete */ #define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) #define USDHC_INT_STATUS_BGE_MASK (0x4U) #define USDHC_INT_STATUS_BGE_SHIFT (2U) /*! BGE - Block Gap Event * 0b1..Transaction stopped at block gap * 0b0..No block gap event */ #define USDHC_INT_STATUS_BGE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) #define USDHC_INT_STATUS_DINT_MASK (0x8U) #define USDHC_INT_STATUS_DINT_SHIFT (3U) /*! DINT - DMA Interrupt * 0b1..DMA Interrupt is generated * 0b0..No DMA Interrupt */ #define USDHC_INT_STATUS_DINT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) #define USDHC_INT_STATUS_BWR_MASK (0x10U) #define USDHC_INT_STATUS_BWR_SHIFT (4U) /*! BWR - Buffer Write Ready * 0b1..Ready to write buffer: * 0b0..Not ready to write buffer */ #define USDHC_INT_STATUS_BWR(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) #define USDHC_INT_STATUS_BRR_MASK (0x20U) #define USDHC_INT_STATUS_BRR_SHIFT (5U) /*! BRR - Buffer Read Ready * 0b1..Ready to read buffer * 0b0..Not ready to read buffer */ #define USDHC_INT_STATUS_BRR(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) #define USDHC_INT_STATUS_CINS_MASK (0x40U) #define USDHC_INT_STATUS_CINS_SHIFT (6U) /*! CINS - Card Insertion * 0b1..Card inserted * 0b0..Card state unstable or removed */ #define USDHC_INT_STATUS_CINS(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) #define USDHC_INT_STATUS_CRM_MASK (0x80U) #define USDHC_INT_STATUS_CRM_SHIFT (7U) /*! CRM - Card Removal * 0b1..Card removed * 0b0..Card state unstable or inserted */ #define USDHC_INT_STATUS_CRM(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) #define USDHC_INT_STATUS_CINT_MASK (0x100U) #define USDHC_INT_STATUS_CINT_SHIFT (8U) /*! CINT - Card Interrupt * 0b1..Generate Card Interrupt * 0b0..No Card Interrupt */ #define USDHC_INT_STATUS_CINT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) #define USDHC_INT_STATUS_RTE_MASK (0x1000U) #define USDHC_INT_STATUS_RTE_SHIFT (12U) /*! RTE - Re-Tuning Event: (only for SD3.0 SDR104 mode) * 0b1..Re-Tuning should be performed * 0b0..Re-Tuning is not required */ #define USDHC_INT_STATUS_RTE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) #define USDHC_INT_STATUS_TP_MASK (0x4000U) #define USDHC_INT_STATUS_TP_SHIFT (14U) #define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) #define USDHC_INT_STATUS_CTOE_MASK (0x10000U) #define USDHC_INT_STATUS_CTOE_SHIFT (16U) /*! CTOE - Command Timeout Error * 0b1..Time out * 0b0..No Error */ #define USDHC_INT_STATUS_CTOE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) #define USDHC_INT_STATUS_CCE_MASK (0x20000U) #define USDHC_INT_STATUS_CCE_SHIFT (17U) /*! CCE - Command CRC Error * 0b1..CRC Error Generated. * 0b0..No Error */ #define USDHC_INT_STATUS_CCE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) #define USDHC_INT_STATUS_CEBE_MASK (0x40000U) #define USDHC_INT_STATUS_CEBE_SHIFT (18U) /*! CEBE - Command End Bit Error * 0b1..End Bit Error Generated * 0b0..No Error */ #define USDHC_INT_STATUS_CEBE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) #define USDHC_INT_STATUS_CIE_MASK (0x80000U) #define USDHC_INT_STATUS_CIE_SHIFT (19U) /*! CIE - Command Index Error * 0b1..Error * 0b0..No Error */ #define USDHC_INT_STATUS_CIE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) #define USDHC_INT_STATUS_DTOE_MASK (0x100000U) #define USDHC_INT_STATUS_DTOE_SHIFT (20U) /*! DTOE - Data Timeout Error * 0b1..Time out * 0b0..No Error */ #define USDHC_INT_STATUS_DTOE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) #define USDHC_INT_STATUS_DCE_MASK (0x200000U) #define USDHC_INT_STATUS_DCE_SHIFT (21U) /*! DCE - Data CRC Error * 0b1..Error * 0b0..No Error */ #define USDHC_INT_STATUS_DCE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) #define USDHC_INT_STATUS_DEBE_MASK (0x400000U) #define USDHC_INT_STATUS_DEBE_SHIFT (22U) /*! DEBE - Data End Bit Error * 0b1..Error * 0b0..No Error */ #define USDHC_INT_STATUS_DEBE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) #define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) #define USDHC_INT_STATUS_AC12E_SHIFT (24U) /*! AC12E - Auto CMD12 Error * 0b1..Error * 0b0..No Error */ #define USDHC_INT_STATUS_AC12E(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) #define USDHC_INT_STATUS_TNE_MASK (0x4000000U) #define USDHC_INT_STATUS_TNE_SHIFT (26U) #define USDHC_INT_STATUS_TNE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) #define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) #define USDHC_INT_STATUS_DMAE_SHIFT (28U) /*! DMAE - DMA Error * 0b1..Error * 0b0..No Error */ #define USDHC_INT_STATUS_DMAE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) /*! @} */ /*! @name INT_STATUS_EN - Interrupt Status Enable */ /*! @{ */ #define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) #define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) /*! CCSEN - Command Complete Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CCSEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) #define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) #define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) /*! TCSEN - Transfer Complete Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_TCSEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) #define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) #define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) /*! BGESEN - Block Gap Event Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_BGESEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) #define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) /*! DINTSEN - DMA Interrupt Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DINTSEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) #define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) /*! BWRSEN - Buffer Write Ready Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_BWRSEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) #define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) /*! BRRSEN - Buffer Read Ready Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_BRRSEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) #define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) /*! CINSSEN - Card Insertion Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CINSSEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) #define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) /*! CRMSEN - Card Removal Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CRMSEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) #define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) /*! CINTSEN - Card Interrupt Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CINTSEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) #define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) #define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) /*! RTESEN - Re-Tuning Event Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_RTESEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) #define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U) #define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U) /*! TPSEN - Tuning Pass Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_TPSEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) #define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) /*! CTOESEN - Command Timeout Error Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CTOESEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) #define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) #define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) /*! CCESEN - Command CRC Error Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CCESEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) #define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) /*! CEBESEN - Command End Bit Error Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CEBESEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) #define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) #define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) /*! CIESEN - Command Index Error Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CIESEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) #define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) /*! DTOESEN - Data Timeout Error Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DTOESEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) #define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) #define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) /*! DCESEN - Data CRC Error Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DCESEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) #define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) /*! DEBESEN - Data End Bit Error Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DEBESEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) #define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) /*! AC12ESEN - Auto CMD12 Error Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_AC12ESEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) #define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) #define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) /*! TNESEN - Tuning Error Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_TNESEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) #define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) /*! DMAESEN - DMA Error Status Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DMAESEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) /*! @} */ /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ /*! @{ */ #define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) /*! CCIEN - Command Complete Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CCIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) #define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) /*! TCIEN - Transfer Complete Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_TCIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) /*! BGEIEN - Block Gap Event Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_BGEIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) /*! DINTIEN - DMA Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DINTIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) /*! BWRIEN - Buffer Write Ready Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_BWRIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) /*! BRRIEN - Buffer Read Ready Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_BRRIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) /*! CINSIEN - Card Insertion Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CINSIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) /*! CRMIEN - Card Removal Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CRMIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) /*! CINTIEN - Card Interrupt Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CINTIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) /*! RTEIEN - Re-Tuning Event Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_RTEIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) #define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U) #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U) /*! TPIEN - Tuning Pass Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_TPIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) /*! CTOEIEN - Command Timeout Error Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CTOEIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) /*! CCEIEN - Command CRC Error Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CCEIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) /*! CEBEIEN - Command End Bit Error Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CEBEIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) /*! CIEIEN - Command Index Error Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CIEIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) /*! DTOEIEN - Data Timeout Error Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DTOEIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) /*! DCEIEN - Data CRC Error Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DCEIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) /*! DEBEIEN - Data End Bit Error Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DEBEIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) /*! AC12EIEN - Auto CMD12 Error Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_AC12EIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) /*! TNEIEN - Tuning Error Interrupt Enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_TNEIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) /*! DMAEIEN - DMA Error Interrupt Enable * 0b1..Enable * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DMAEIEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) /*! @} */ /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ /*! @{ */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) /*! AC12NE - Auto CMD12 Not Executed * 0b1..Not executed * 0b0..Executed */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) /*! AC12TOE - Auto CMD12 / 23 Timeout Error * 0b1..Time out * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & \ USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) /*! AC12EBE - Auto CMD12 / 23 End Bit Error * 0b1..End Bit Error Generated * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & \ USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) /*! AC12CE - Auto CMD12 / 23 CRC Error * 0b1..CRC Error Met in Auto CMD12/23 Response * 0b0..No CRC error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) /*! AC12IE - Auto CMD12 / 23 Index Error * 0b1..Error, the CMD index in response is not CMD12/23 * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) /*! CNIBAC12E - Command Not Issued By Auto CMD12 Error * 0b1..Not Issued * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & \ USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & \ USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) /*! SMP_CLK_SEL - Sample Clock Select * 0b1..Tuned clock is used to sample data * 0b0..Fixed clock is used to sample data */ #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & \ USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) /*! @} */ /*! @name HOST_CTRL_CAP - Host Controller Capabilities */ /*! @{ */ #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & \ USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U) #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U) #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & \ USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) /*! USE_TUNING_SDR50 - Use Tuning for SDR50 * 0b1..SDR50 requires tuning * 0b0..SDR does not require tuning */ #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & \ USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U) #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U) /*! RETUNING_MODE - Retuning Mode * 0b00..Mode 1 * 0b01..Mode 2 * 0b10..Mode 3 * 0b11..Reserved */ #define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) #define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) #define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) /*! MBL - Max Block Length * 0b000..512 bytes * 0b001..1024 bytes * 0b010..2048 bytes * 0b011..4096 bytes */ #define USDHC_HOST_CTRL_CAP_MBL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) #define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) /*! ADMAS - ADMA Support * 0b1..Advanced DMA Supported * 0b0..Advanced DMA Not supported */ #define USDHC_HOST_CTRL_CAP_ADMAS(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) #define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) #define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) /*! HSS - High Speed Support * 0b1..High Speed Supported * 0b0..High Speed Not Supported */ #define USDHC_HOST_CTRL_CAP_HSS(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) #define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) /*! DMAS - DMA Support * 0b1..DMA Supported * 0b0..DMA not supported */ #define USDHC_HOST_CTRL_CAP_DMAS(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) #define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) #define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) /*! SRS - Suspend / Resume Support * 0b1..Supported * 0b0..Not supported */ #define USDHC_HOST_CTRL_CAP_SRS(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) #define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) #define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) /*! VS33 - Voltage Support 3.3V * 0b1..3.3V supported * 0b0..3.3V not supported */ #define USDHC_HOST_CTRL_CAP_VS33(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) #define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) #define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) /*! VS30 - Voltage Support 3.0 V * 0b1..3.0V supported * 0b0..3.0V not supported */ #define USDHC_HOST_CTRL_CAP_VS30(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) #define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) #define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) /*! VS18 - Voltage Support 1.8 V * 0b1..1.8V supported * 0b0..1.8V not supported */ #define USDHC_HOST_CTRL_CAP_VS18(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) /*! @} */ /*! @name WTMK_LVL - Watermark Level */ /*! @{ */ #define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) #define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) #define USDHC_WTMK_LVL_RD_WML(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) #define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U) #define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U) #define USDHC_WTMK_LVL_RD_BRST_LEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK) #define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) #define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) #define USDHC_WTMK_LVL_WR_WML(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) #define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) #define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) #define USDHC_WTMK_LVL_WR_BRST_LEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) /*! @} */ /*! @name MIX_CTRL - Mixer Control */ /*! @{ */ #define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) #define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) /*! DMAEN - DMA Enable * 0b1..Enable * 0b0..Disable */ #define USDHC_MIX_CTRL_DMAEN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) #define USDHC_MIX_CTRL_BCEN_MASK (0x2U) #define USDHC_MIX_CTRL_BCEN_SHIFT (1U) /*! BCEN - Block Count Enable * 0b1..Enable * 0b0..Disable */ #define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) #define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) #define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) /*! AC12EN - Auto CMD12 Enable * 0b1..Enable * 0b0..Disable */ #define USDHC_MIX_CTRL_AC12EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) #define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) #define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) #define USDHC_MIX_CTRL_DDR_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) #define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) #define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) /*! DTDSEL - Data Transfer Direction Select * 0b1..Read (Card to Host) * 0b0..Write (Host to Card) */ #define USDHC_MIX_CTRL_DTDSEL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) #define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) #define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) /*! MSBSEL - Multi / Single Block Select * 0b1..Multiple Blocks * 0b0..Single Block */ #define USDHC_MIX_CTRL_MSBSEL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) #define USDHC_MIX_CTRL_NIBBLE_POS(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) #define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) #define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) #define USDHC_MIX_CTRL_AC23EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) #define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) /*! EXE_TUNE - Execute Tuning: (Only used for SD3.0, SDR104 mode) * 0b1..Execute Tuning * 0b0..Not Tuned or Tuning Completed */ #define USDHC_MIX_CTRL_EXE_TUNE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) /*! SMP_CLK_SEL * 0b1..Tuned clock is used to sample data / cmd * 0b0..Fixed clock is used to sample data / cmd */ #define USDHC_MIX_CTRL_SMP_CLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) /*! AUTO_TUNE_EN - Auto Tuning Enable (Only used for SD3.0, SDR104 mode) * 0b1..Enable auto tuning * 0b0..Disable auto tuning */ #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) #define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) /*! FBCLK_SEL - Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode) * 0b1..Feedback clock comes from the ipp_card_clk_out * 0b0..Feedback clock comes from the loopback CLK */ #define USDHC_MIX_CTRL_FBCLK_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) #define USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U) #define USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U) #define USDHC_MIX_CTRL_HS400_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK) /*! @} */ /*! @name FORCE_EVENT - Force Event */ /*! @{ */ #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) #define USDHC_FORCE_EVENT_FEVTAC12NE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) #define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) #define USDHC_FORCE_EVENT_FEVTAC12TOE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) #define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) #define USDHC_FORCE_EVENT_FEVTAC12CE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) #define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) #define USDHC_FORCE_EVENT_FEVTAC12EBE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) #define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) #define USDHC_FORCE_EVENT_FEVTAC12IE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) #define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) #define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) #define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) #define USDHC_FORCE_EVENT_FEVTCTOE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) #define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) #define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) #define USDHC_FORCE_EVENT_FEVTCCE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) #define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) #define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) #define USDHC_FORCE_EVENT_FEVTCEBE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) #define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) #define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) #define USDHC_FORCE_EVENT_FEVTCIE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) #define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) #define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) #define USDHC_FORCE_EVENT_FEVTDTOE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) #define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) #define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) #define USDHC_FORCE_EVENT_FEVTDCE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) #define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) #define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) #define USDHC_FORCE_EVENT_FEVTDEBE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) #define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) #define USDHC_FORCE_EVENT_FEVTAC12E(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) #define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) #define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) #define USDHC_FORCE_EVENT_FEVTTNE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) #define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) #define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) #define USDHC_FORCE_EVENT_FEVTDMAE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) #define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) #define USDHC_FORCE_EVENT_FEVTCINT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) /*! @} */ /*! @name ADMA_ERR_STATUS - ADMA Error Status Register */ /*! @{ */ #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) #define USDHC_ADMA_ERR_STATUS_ADMAES(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) /*! ADMALME - ADMA Length Mismatch Error * 0b1..Error * 0b0..No Error */ #define USDHC_ADMA_ERR_STATUS_ADMALME(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) /*! ADMADCE - ADMA Descritor Error * 0b1..Error * 0b0..No Error */ #define USDHC_ADMA_ERR_STATUS_ADMADCE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) /*! @} */ /*! @name ADMA_SYS_ADDR - ADMA System Address */ /*! @{ */ #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) /*! @} */ /*! @name DLL_CTRL - DLL (Delay Line) Control */ /*! @{ */ #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) #define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) #define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & \ USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & \ USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & \ USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & \ USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & \ USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & \ USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & \ USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & \ USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) /*! @} */ /*! @name DLL_STATUS - DLL Status */ /*! @{ */ #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) /*! @} */ /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ /*! @{ */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & \ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & \ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & \ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & \ USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & \ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & \ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & \ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & \ USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) /*! @} */ /*! @name STROBE_DLL_CTRL - Strobe DLL Control */ /*! @{ */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & \ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & \ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & \ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x38U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & \ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK (0x40U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT (6U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT)) & \ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK (0x80U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT (7U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT)) & \ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & \ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & \ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & \ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & \ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK) /*! @} */ /*! @name STROBE_DLL_STATUS - Strobe DLL Status */ /*! @{ */ #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & \ USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & \ USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & \ USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & \ USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK) /*! @} */ /*! @name VEND_SPEC - Vendor Specific Register */ /*! @{ */ #define USDHC_VEND_SPEC_EXT_DMA_EN_MASK (0x1U) #define USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT (0U) /*! EXT_DMA_EN - External DMA Request Enable * 0b0..In any scenario, uSDHC does not send out external DMA request. * 0b1..When internal DMA is not active, the external DMA request will be sent out. */ #define USDHC_VEND_SPEC_EXT_DMA_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT)) & USDHC_VEND_SPEC_EXT_DMA_EN_MASK) #define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) #define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) /*! VSELECT - Voltage Selection * 0b1..Change the voltage to low voltage range, around 1.8 V * 0b0..Change the voltage to high voltage range, around 3.0 V */ #define USDHC_VEND_SPEC_VSELECT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) /*! CONFLICT_CHK_EN - Conflict check enable. * 0b0..Conflict check disable * 0b1..Conflict check enable */ #define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) /*! AC12_WR_CHKBUSY_EN * 0b0..Do not check busy after auto CMD12 for write data packet * 0b1..Check busy after auto CMD12 for write data packet */ #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & \ USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) #define USDHC_VEND_SPEC_DAT3_CD_POL_MASK (0x10U) #define USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT (4U) /*! DAT3_CD_POL * 0b0..Card detected when DATA3 is high. * 0b1..Card detected when DATA3 is low. */ #define USDHC_VEND_SPEC_DAT3_CD_POL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT)) & USDHC_VEND_SPEC_DAT3_CD_POL_MASK) #define USDHC_VEND_SPEC_CD_POL_MASK (0x20U) #define USDHC_VEND_SPEC_CD_POL_SHIFT (5U) /*! CD_POL * 0b0..CD_B pin is low active. * 0b1..CD_B pin is high active. */ #define USDHC_VEND_SPEC_CD_POL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CD_POL_SHIFT)) & USDHC_VEND_SPEC_CD_POL_MASK) #define USDHC_VEND_SPEC_WP_POL_MASK (0x40U) #define USDHC_VEND_SPEC_WP_POL_SHIFT (6U) /*! WP_POL * 0b0..WP pin is high active. * 0b1..WP pin is low active. */ #define USDHC_VEND_SPEC_WP_POL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_WP_POL_SHIFT)) & USDHC_VEND_SPEC_WP_POL_MASK) #define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK (0x80U) #define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT (7U) /*! CLKONJ_IN_ABORT * 0b0..The CLK output is active when sending abort command while data is transmitting even if the internal FIFO * is full (for read) or empty (for write). * 0b1..The CLK output is inactive when sending abort command while data is transmitting if the internal FIFO is * full (for read) or empty (for write). */ #define USDHC_VEND_SPEC_CLKONJ_IN_ABORT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT)) & USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK) #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) /*! FRC_SDCLK_ON * 0b0..CLK active or inactive is fully controlled by the hardware. * 0b1..Force CLK active. */ #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) #define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK (0x800U) #define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT (11U) /*! IPG_CLK_SOFT_EN - IPG_CLK Software Enable * 0b0..Gate off the IPG_CLK * 0b1..Enable the IPG_CLK */ #define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK) #define USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK (0x1000U) #define USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT (12U) /*! HCLK_SOFT_EN - AHB Clock Software Enable * 0b0..Gate off the AHB clock. * 0b1..Enable the AHB clock. */ #define USDHC_VEND_SPEC_HCLK_SOFT_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK) #define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK (0x2000U) #define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT (13U) /*! IPG_PERCLK_SOFT_EN - IPG_PERCLK Software Enable * 0b0..Gate off the IPG_PERCLK * 0b1..Enable the IPG_PERCLK */ #define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT)) & \ USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK) #define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK (0x4000U) #define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT (14U) /*! CARD_CLK_SOFT_EN - Card Clock Software Enable * 0b0..Gate off the sd_clk * 0b1..Enable the sd_clk */ #define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK) #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) /*! CRC_CHK_DIS - CRC Check Disable * 0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet * 0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet */ #define USDHC_VEND_SPEC_CRC_CHK_DIS(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) #define USDHC_VEND_SPEC_INT_ST_VAL_MASK (0xFF0000U) #define USDHC_VEND_SPEC_INT_ST_VAL_SHIFT (16U) #define USDHC_VEND_SPEC_INT_ST_VAL(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_INT_ST_VAL_SHIFT)) & USDHC_VEND_SPEC_INT_ST_VAL_MASK) #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) /*! CMD_BYTE_EN * 0b0..Disable * 0b1..Enable */ #define USDHC_VEND_SPEC_CMD_BYTE_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) /*! @} */ /*! @name MMC_BOOT - MMC Boot Register */ /*! @{ */ #define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) /*! DTOCV_ACK * 0b0000..SDCLK x 2^13 * 0b0001..SDCLK x 2^14 * 0b0010..SDCLK x 2^15 * 0b0011..SDCLK x 2^16 * 0b0100..SDCLK x 2^17 * 0b0101..SDCLK x 2^18 * 0b0110..SDCLK x 2^19 * 0b0111..SDCLK x 2^20 * 0b1110..SDCLK x 2^27 * 0b1111..SDCLK x 2^28 */ #define USDHC_MMC_BOOT_DTOCV_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) #define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) /*! BOOT_ACK * 0b0..No ack * 0b1..Ack */ #define USDHC_MMC_BOOT_BOOT_ACK(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) #define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) /*! BOOT_MODE * 0b0..Normal boot * 0b1..Alternative boot */ #define USDHC_MMC_BOOT_BOOT_MODE(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) #define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) #define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) /*! BOOT_EN * 0b0..Fast boot disable * 0b1..Fast boot enable */ #define USDHC_MMC_BOOT_BOOT_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) #define USDHC_MMC_BOOT_AUTO_SABG_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) /*! DISABLE_TIME_OUT - Disable Time Out * 0b0..Enable time out * 0b1..Disable time out */ #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) /*! @} */ /*! @name VEND_SPEC2 - Vendor Specific 2 Register */ /*! @{ */ #define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK (0x1U) #define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT (0U) /*! SDR104_TIMING_DIS * 0b0..The timeout counter for Ncr changes to 80, Ncrc changes to 21. * 0b1..The timeout counter for Ncr changes to 72, Ncrc changes to 15. */ #define USDHC_VEND_SPEC2_SDR104_TIMING_DIS(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT)) & \ USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK) #define USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK (0x2U) #define USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT (1U) /*! SDR104_OE_DIS * 0b0..Drive the CMD_OE / DATA_OE for one more clock cycle after the end bit. * 0b1..Stop to drive the CMD_OE / DATA_OE at once after driving the end bit. */ #define USDHC_VEND_SPEC2_SDR104_OE_DIS(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK) #define USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK (0x4U) #define USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT (2U) /*! SDR104_NSD_DIS * 0b0..Enable the interrupt window 9 cycles later after the end of the I/O abort command (or CMD12) is sent. * 0b1..Enable the interrupt window 5 cycles later after the end of the I/O abort command (or CMD12) is sent. */ #define USDHC_VEND_SPEC2_SDR104_NSD_DIS(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK) #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) /*! CARD_INT_D3_TEST - Card Interrupt Detection Test * 0b0..Check the card interrupt only when DATA3 is high. * 0b1..Check the card interrupt by ignoring the status of DATA3. */ #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) #define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) #define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) /*! TUNING_8bit_EN * 0b0..Tuning circuit only checks the DATA[3:0]. * 0b1..Tuning circuit only checks the DATA0. */ #define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK) #define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U) #define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U) #define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) /*! TUNING_CMD_EN * 0b0..Auto tuning circuit does not check the CMD line. * 0b1..Auto tuning circuit checks the CMD line. */ #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) #define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK (0x80U) #define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT (7U) /*! CARD_INT_AUTO_CLR_DIS * 0b0..Card interrupt status bit (CINT) can be cleared when Card Interrupt status enable bit is 0. * 0b1..Card interrupt status bit (CINT) can only be cleared by writting a 1 to CINT bit. */ #define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT)) & \ USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK) #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U) #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U) #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & \ USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK) #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U) #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U) #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & \ USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK) /*! @} */ /*! @name TUNING_CTRL - Tuning Control Register */ /*! @{ */ #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU) #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) #define USDHC_TUNING_CTRL_TUNING_START_TAP(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & \ USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) #define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) #define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) #define USDHC_TUNING_CTRL_TUNING_COUNTER(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) #define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) #define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) #define USDHC_TUNING_CTRL_TUNING_STEP(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) #define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) #define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) #define USDHC_TUNING_CTRL_TUNING_WINDOW(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) #define USDHC_TUNING_CTRL_STD_TUNING_EN(x) \ (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) /*! @} */ /*! * @} */ /* end of group USDHC_Register_Masks */ /* USDHC - Peripheral instance base addresses */ /** Peripheral uSDHC1 base address */ #define uSDHC1_BASE (0x30B40000u) /** Peripheral uSDHC1 base pointer */ #define uSDHC1 ((USDHC_Type *)uSDHC1_BASE) /** Peripheral uSDHC2 base address */ #define uSDHC2_BASE (0x30B50000u) /** Peripheral uSDHC2 base pointer */ #define uSDHC2 ((USDHC_Type *)uSDHC2_BASE) /** Peripheral uSDHC3 base address */ #define uSDHC3_BASE (0x30B60000u) /** Peripheral uSDHC3 base pointer */ #define uSDHC3 ((USDHC_Type *)uSDHC3_BASE) /** Array initializer of USDHC peripheral base addresses */ #define USDHC_BASE_ADDRS \ { \ 0u, uSDHC1_BASE, uSDHC2_BASE, uSDHC3_BASE \ } /** Array initializer of USDHC peripheral base pointers */ #define USDHC_BASE_PTRS \ { \ (USDHC_Type *)0u, uSDHC1, uSDHC2, uSDHC3 \ } /** Interrupt vectors for the USDHC peripheral type */ #define USDHC_IRQS \ { \ NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn, USDHC3_IRQn \ } /*! * @} */ /* end of group USDHC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- WDOG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer * @{ */ /** WDOG - Register Layout Typedef */ typedef struct { __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */ __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */ __I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */ __IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */ __IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */ } WDOG_Type; /* ---------------------------------------------------------------------------- -- WDOG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WDOG_Register_Masks WDOG Register Masks * @{ */ /*! @name WCR - Watchdog Control Register */ /*! @{ */ #define WDOG_WCR_WDZST_MASK (0x1U) #define WDOG_WCR_WDZST_SHIFT (0U) /*! WDZST * 0b0..Continue timer operation (Default). * 0b1..Suspend the watchdog timer. */ #define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) #define WDOG_WCR_WDBG_MASK (0x2U) #define WDOG_WCR_WDBG_SHIFT (1U) /*! WDBG * 0b0..Continue WDOG timer operation (Default). * 0b1..Suspend the watchdog timer. */ #define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) #define WDOG_WCR_WDE_MASK (0x4U) #define WDOG_WCR_WDE_SHIFT (2U) /*! WDE * 0b0..Disable the Watchdog (Default). * 0b1..Enable the Watchdog. */ #define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) #define WDOG_WCR_WDT_MASK (0x8U) #define WDOG_WCR_WDT_SHIFT (3U) /*! WDT * 0b0..No effect on WDOG_B (Default). * 0b1..Assert WDOG_B upon a Watchdog Time-out event. */ #define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) #define WDOG_WCR_SRS_MASK (0x10U) #define WDOG_WCR_SRS_SHIFT (4U) /*! SRS * 0b0..Assert system reset signal. * 0b1..No effect on the system (Default). */ #define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) #define WDOG_WCR_WDA_MASK (0x20U) #define WDOG_WCR_WDA_SHIFT (5U) /*! WDA * 0b0..Assert WDOG_B output. * 0b1..No effect on system (Default). */ #define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) #define WDOG_WCR_SRE_MASK (0x40U) #define WDOG_WCR_SRE_SHIFT (6U) /*! SRE - Software Reset Extension. Required to be set to 1 when used in conjunction with the Software Reset Signal * (SRS). 0b0..Reserved 0b1..This bit must be set to 1. */ #define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) #define WDOG_WCR_WDW_MASK (0x80U) #define WDOG_WCR_WDW_SHIFT (7U) /*! WDW * 0b0..Continue WDOG timer operation (Default). * 0b1..Suspend WDOG timer operation. */ #define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) #define WDOG_WCR_WT_MASK (0xFF00U) #define WDOG_WCR_WT_SHIFT (8U) /*! WT * 0b00000000..- 0.5 Seconds (Default). * 0b00000001..- 1.0 Seconds. * 0b00000010..- 1.5 Seconds. * 0b00000011..- 2.0 Seconds. * 0b11111111..- 128 Seconds. */ #define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) /*! @} */ /*! @name WSR - Watchdog Service Register */ /*! @{ */ #define WDOG_WSR_WSR_MASK (0xFFFFU) #define WDOG_WSR_WSR_SHIFT (0U) /*! WSR * 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR). * 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR). */ #define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) /*! @} */ /*! @name WRSR - Watchdog Reset Status Register */ /*! @{ */ #define WDOG_WRSR_SFTW_MASK (0x1U) #define WDOG_WRSR_SFTW_SHIFT (0U) /*! SFTW * 0b0..Reset is not the result of a software reset. * 0b1..Reset is the result of a software reset. */ #define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) #define WDOG_WRSR_TOUT_MASK (0x2U) #define WDOG_WRSR_TOUT_SHIFT (1U) /*! TOUT * 0b0..Reset is not the result of a WDOG timeout. * 0b1..Reset is the result of a WDOG timeout. */ #define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) #define WDOG_WRSR_POR_MASK (0x10U) #define WDOG_WRSR_POR_SHIFT (4U) /*! POR * 0b0..Reset is not the result of a power on reset. * 0b1..Reset is the result of a power on reset. */ #define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) /*! @} */ /*! @name WICR - Watchdog Interrupt Control Register */ /*! @{ */ #define WDOG_WICR_WICT_MASK (0xFFU) #define WDOG_WICR_WICT_SHIFT (0U) /*! WICT * 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. * 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. * 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). * 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. */ #define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) #define WDOG_WICR_WTIS_MASK (0x4000U) #define WDOG_WICR_WTIS_SHIFT (14U) /*! WTIS * 0b0..No interrupt has occurred (Default). * 0b1..Interrupt has occurred */ #define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) #define WDOG_WICR_WIE_MASK (0x8000U) #define WDOG_WICR_WIE_SHIFT (15U) /*! WIE * 0b0..Disable Interrupt (Default). * 0b1..Enable Interrupt. */ #define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) /*! @} */ /*! @name WMCR - Watchdog Miscellaneous Control Register */ /*! @{ */ #define WDOG_WMCR_PDE_MASK (0x1U) #define WDOG_WMCR_PDE_SHIFT (0U) /*! PDE * 0b0..Power Down Counter of WDOG is disabled. * 0b1..Power Down Counter of WDOG is enabled (Default). */ #define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) /*! @} */ /*! * @} */ /* end of group WDOG_Register_Masks */ /* WDOG - Peripheral instance base addresses */ /** Peripheral WDOG1 base address */ #define WDOG1_BASE (0x30280000u) /** Peripheral WDOG1 base pointer */ #define WDOG1 ((WDOG_Type *)WDOG1_BASE) /** Peripheral WDOG2 base address */ #define WDOG2_BASE (0x30290000u) /** Peripheral WDOG2 base pointer */ #define WDOG2 ((WDOG_Type *)WDOG2_BASE) /** Peripheral WDOG3 base address */ #define WDOG3_BASE (0x302A0000u) /** Peripheral WDOG3 base pointer */ #define WDOG3 ((WDOG_Type *)WDOG3_BASE) /** Array initializer of WDOG peripheral base addresses */ #define WDOG_BASE_ADDRS \ { \ 0u, WDOG1_BASE, WDOG2_BASE, WDOG3_BASE \ } /** Array initializer of WDOG peripheral base pointers */ #define WDOG_BASE_PTRS \ { \ (WDOG_Type *)0u, WDOG1, WDOG2, WDOG3 \ } /** Interrupt vectors for the WDOG peripheral type */ #define WDOG_IRQS \ { \ NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn, WDOG3_IRQn \ } /*! * @} */ /* end of group WDOG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- XTALOSC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup XTALOSC_Peripheral_Access_Layer XTALOSC Peripheral Access Layer * @{ */ /** XTALOSC - Register Layout Typedef */ typedef struct { __IO uint32_t SYS_OSCNML_CTL0; /**< OSC Normal Clock Generation Control Register0, offset: 0x0 */ __IO uint32_t SYS_OSCNML_CTL1; /**< OSC Normal Clock Generation Control Register1, offset: 0x4 */ } XTALOSC_Type; /* ---------------------------------------------------------------------------- -- XTALOSC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup XTALOSC_Register_Masks XTALOSC Register Masks * @{ */ /*! @name SYS_OSCNML_CTL0 - OSC Normal Clock Generation Control Register0 */ /*! @{ */ #define XTALOSC_SYS_OSCNML_CTL0_SF0_MASK (0x1U) #define XTALOSC_SYS_OSCNML_CTL0_SF0_SHIFT (0U) #define XTALOSC_SYS_OSCNML_CTL0_SF0(x) \ (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_SF0_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_SF0_MASK) #define XTALOSC_SYS_OSCNML_CTL0_SF1_MASK (0x2U) #define XTALOSC_SYS_OSCNML_CTL0_SF1_SHIFT (1U) #define XTALOSC_SYS_OSCNML_CTL0_SF1(x) \ (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_SF1_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_SF1_MASK) #define XTALOSC_SYS_OSCNML_CTL0_SP_MASK (0x4U) #define XTALOSC_SYS_OSCNML_CTL0_SP_SHIFT (2U) #define XTALOSC_SYS_OSCNML_CTL0_SP(x) \ (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_SP_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_SP_MASK) #define XTALOSC_SYS_OSCNML_CTL0_RTO_MASK (0x10U) #define XTALOSC_SYS_OSCNML_CTL0_RTO_SHIFT (4U) #define XTALOSC_SYS_OSCNML_CTL0_RTO(x) \ (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_RTO_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_RTO_MASK) #define XTALOSC_SYS_OSCNML_CTL0_EN_MASK (0x80000000U) #define XTALOSC_SYS_OSCNML_CTL0_EN_SHIFT (31U) #define XTALOSC_SYS_OSCNML_CTL0_EN(x) \ (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_EN_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_EN_MASK) /*! @} */ /*! @name SYS_OSCNML_CTL1 - OSC Normal Clock Generation Control Register1 */ /*! @{ */ #define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE_MASK (0x2U) #define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE_SHIFT (1U) #define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE(x) \ (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE_SHIFT)) & \ XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE_MASK) #define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_MASK (0x4U) #define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_SHIFT (2U) #define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE(x) \ (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_SHIFT)) & XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_MASK) #define XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT_MASK (0xFF0U) #define XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT_SHIFT (4U) #define XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT(x) \ (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT_SHIFT)) & \ XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT_MASK) /*! @} */ /*! * @} */ /* end of group XTALOSC_Register_Masks */ /* XTALOSC - Peripheral instance base addresses */ /** Peripheral XTALOSC base address */ #define XTALOSC_BASE (0x30270000u) /** Peripheral XTALOSC base pointer */ #define XTALOSC ((XTALOSC_Type *)XTALOSC_BASE) /** Array initializer of XTALOSC peripheral base addresses */ #define XTALOSC_BASE_ADDRS \ { \ XTALOSC_BASE \ } /** Array initializer of XTALOSC peripheral base pointers */ #define XTALOSC_BASE_PTRS \ { \ XTALOSC \ } /*! * @} */ /* end of group XTALOSC_Peripheral_Access_Layer */ /* ** End of section using anonymous unions */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #else #pragma pop #endif #elif defined(__GNUC__) /* leave anonymous unions enabled */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language = default #else #error Not supported compiler type #endif /*! * @} */ /* end of group Peripheral_access_layer */ /* ---------------------------------------------------------------------------- -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). ---------------------------------------------------------------------------- */ /*! * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). * @{ */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang system_header #endif #elif defined(__IAR_SYSTEMS_ICC__) #pragma system_include #endif /** * @brief Mask and left-shift a bit field value for use in a register bit range. * @param field Name of the register bit field. * @param value Value of the bit field. * @return Masked and shifted value. */ #define NXP_VAL2FLD(field, value) (((value) << (field##_SHIFT)) & (field##_MASK)) /** * @brief Mask and right-shift a register value to extract a bit field value. * @param field Name of the register bit field. * @param value Value of the register. * @return Masked and shifted bit field value. */ #define NXP_FLD2VAL(field, value) (((value) & (field##_MASK)) >> (field##_SHIFT)) /*! * @} */ /* end of group Bit_Field_Generic_Macros */ /* ---------------------------------------------------------------------------- -- SDK Compatibility ---------------------------------------------------------------------------- */ /*! * @addtogroup SDK_Compatibility_Symbols SDK Compatibility * @{ */ /* No SDK compatibility issues. */ /*! * @} */ /* end of group SDK_Compatibility_Symbols */ #endif /* _MIMX8MN4_CM7_H_ */