/* ** ################################################################### ** Version: rev. 7.0, 2018-11-05 ** Build: b200927 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2020 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2016-04-13) ** Initial version. ** - rev. 2.0 (2016-07-19) ** RevC Header ER ** - rev. 3.0 (2017-02-28) ** RevD Header ER ** - rev. 4.0 (2017-05-02) ** RevE Header ER ** - rev. 5.0 (2017-12-22) ** RevA(B0) Header GA ** - rev. 6.0 (2018-02-01) ** RevB(B0) Header GA ** - rev. 7.0 (2018-11-05) ** RevA(B1) Header ** ** ################################################################### */ #ifndef _MCIMX7U5_cm4_FEATURES_H_ #define _MCIMX7U5_cm4_FEATURES_H_ /* SOC module features */ /* @brief ACMP availability on the SoC. */ #define FSL_FEATURE_SOC_ACMP_COUNT (2) /* @brief AXBS availability on the SoC. */ #define FSL_FEATURE_SOC_AXBS_COUNT (2) /* @brief CRC availability on the SoC. */ #define FSL_FEATURE_SOC_CRC_COUNT (1) /* @brief DAC availability on the SoC. */ #define FSL_FEATURE_SOC_DAC_COUNT (2) /* @brief DMAMUX availability on the SoC. */ #define FSL_FEATURE_SOC_DMAMUX_COUNT (2) /* @brief EDMA availability on the SoC. */ #define FSL_FEATURE_SOC_EDMA_COUNT (2) /* @brief EWM availability on the SoC. */ #define FSL_FEATURE_SOC_EWM_COUNT (1) /* @brief FB availability on the SoC. */ #define FSL_FEATURE_SOC_FB_COUNT (1) /* @brief FGPIO availability on the SoC. */ #define FSL_FEATURE_SOC_FGPIO_COUNT (2) /* @brief FLEXIO availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXIO_COUNT (2) /* @brief GPIO availability on the SoC. */ #define FSL_FEATURE_SOC_GPIO_COUNT (6) /* @brief I2S availability on the SoC. */ #define FSL_FEATURE_SOC_I2S_COUNT (2) /* @brief LCDIF availability on the SoC. */ #define FSL_FEATURE_SOC_LCDIF_COUNT (1) /* @brief LLWU availability on the SoC. */ #define FSL_FEATURE_SOC_LLWU_COUNT (1) /* @brief LMEM availability on the SoC. */ #define FSL_FEATURE_SOC_LMEM_COUNT (1) /* @brief LPADC availability on the SoC. */ #define FSL_FEATURE_SOC_LPADC_COUNT (2) /* @brief LPI2C availability on the SoC. */ #define FSL_FEATURE_SOC_LPI2C_COUNT (8) /* @brief LPIT availability on the SoC. */ #define FSL_FEATURE_SOC_LPIT_COUNT (2) /* @brief LPSPI availability on the SoC. */ #define FSL_FEATURE_SOC_LPSPI_COUNT (4) /* @brief LPTMR availability on the SoC. */ #define FSL_FEATURE_SOC_LPTMR_COUNT (2) /* @brief LPUART availability on the SoC. */ #define FSL_FEATURE_SOC_LPUART_COUNT (8) /* @brief LTC availability on the SoC. */ #define FSL_FEATURE_SOC_LTC_COUNT (1) /* @brief MCM availability on the SoC. */ #define FSL_FEATURE_SOC_MCM_COUNT (1) /* @brief MIPI_DSI_HOST availability on the SoC. */ #define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (1) /* @brief MMCAU availability on the SoC. */ #define FSL_FEATURE_SOC_MMCAU_COUNT (1) /* @brief MMDC availability on the SoC. */ #define FSL_FEATURE_SOC_MMDC_COUNT (1) /* @brief MU availability on the SoC. */ #define FSL_FEATURE_SOC_MU_COUNT (1) /* @brief OCOTP availability on the SoC. */ #define FSL_FEATURE_SOC_OCOTP_COUNT (1) /* @brief OTFAD availability on the SoC. */ #define FSL_FEATURE_SOC_OTFAD_COUNT (1) /* @brief PCC availability on the SoC. */ #define FSL_FEATURE_SOC_PCC_COUNT (4) /* @brief PMC availability on the SoC. */ #define FSL_FEATURE_SOC_PMC_COUNT (2) /* @brief PORT availability on the SoC. */ #define FSL_FEATURE_SOC_PORT_COUNT (6) /* @brief QuadSPI availability on the SoC. */ #define FSL_FEATURE_SOC_QuadSPI_COUNT (1) /* @brief ROMC availability on the SoC. */ #define FSL_FEATURE_SOC_ROMC_COUNT (2) /* @brief SCG availability on the SoC. */ #define FSL_FEATURE_SOC_SCG_COUNT (2) /* @brief SEMA42 availability on the SoC. */ #define FSL_FEATURE_SOC_SEMA42_COUNT (2) /* @brief SIM availability on the SoC. */ #define FSL_FEATURE_SOC_SIM_COUNT (1) /* @brief SMC availability on the SoC. */ #define FSL_FEATURE_SOC_SMC_COUNT (2) /* @brief SNVS availability on the SoC. */ #define FSL_FEATURE_SOC_SNVS_COUNT (1) /* @brief TPM availability on the SoC. */ #define FSL_FEATURE_SOC_TPM_COUNT (8) /* @brief TRGMUX availability on the SoC. */ #define FSL_FEATURE_SOC_TRGMUX_COUNT (2) /* @brief TRNG availability on the SoC. */ #define FSL_FEATURE_SOC_TRNG_COUNT (1) /* @brief TSTMR availability on the SoC. */ #define FSL_FEATURE_SOC_TSTMR_COUNT (2) /* @brief USBHS availability on the SoC. */ #define FSL_FEATURE_SOC_USBHS_COUNT (2) /* @brief USBHSDCD availability on the SoC. */ #define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) /* @brief USBNC availability on the SoC. */ #define FSL_FEATURE_SOC_USBNC_COUNT (2) /* @brief USBPHY availability on the SoC. */ #define FSL_FEATURE_SOC_USBPHY_COUNT (1) /* @brief USDHC availability on the SoC. */ #define FSL_FEATURE_SOC_USDHC_COUNT (2) /* @brief VIU availability on the SoC. */ #define FSL_FEATURE_SOC_VIU_COUNT (1) /* @brief WDOG availability on the SoC. */ #define FSL_FEATURE_SOC_WDOG_COUNT (3) /* @brief XRDC availability on the SoC. */ #define FSL_FEATURE_SOC_XRDC_COUNT (1) /* LPADC module features */ /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (1) /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (1) /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (0) /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (0) /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (0) /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (0) /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (0) /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (0) /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) /* @brief Has calibration (bitfield CFG[CALOFS]). */ #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) /* @brief Has offset trim (register OFSTRIM). */ #define FSL_FEATURE_LPADC_HAS_OFSTRIM (0) /* ACMP module features */ /* @brief Has CMP_C3. */ #define FSL_FEATURE_ACMP_HAS_C3_REG (1) /* @brief Has C0 LINKEN Bit */ #define FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT (1) /* @brief Has C0 OFFSET Bit */ #define FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT (0) /* @brief Has C1 INPSEL Bit */ #define FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT (0) /* @brief Has C1 INNSEL Bit */ #define FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT (0) /* @brief Has C1 DACOE Bit */ #define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (1) /* @brief Has C1 DMODE Bit */ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) /* CRC module features */ /* @brief Has data register with name CRC */ #define FSL_FEATURE_CRC_HAS_CRC_REG (0) /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ #define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) /* @brief Total number of DMA channels on all modules. */ #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32) /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) /* @brief Has DMA_Error interrupt vector. */ #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) /* @brief Channel IRQ entry shared offset. */ #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (4) /* @brief If 8 bytes transfer supported. */ #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) /* @brief If 16 bytes transfer supported. */ #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (0) /* DMAMUX module features */ /* @brief Number of DMA channels (related to number of register CHCFGn). */ #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32) /* @brief Total number of DMA channels on all modules. */ #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (64) /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) /* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */ #define FSL_FEATURE_DMAMUX_HAS_A_ON (1) /* EWM module features */ /* @brief Has clock select (register CLKCTRL). */ #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) /* @brief Has clock prescaler (register CLKPRESCALER). */ #define FSL_FEATURE_EWM_HAS_PRESCALER (1) /* FLEXIO module features */ /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) /* @brief Reset value of the FLEXIO_VERID register */ #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) /* @brief Reset value of the FLEXIO_PARAM register */ #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808) /* @brief Flexio DMA request base channel */ #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) /* GPIO module features */ /* @brief Has port input disable register (PIDR). */ #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) /* @brief Has GPIO attribute checker register (GACR). */ #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) /* SAI module features */ /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNT (16) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \ (((x) == I2S0) ? (2) : \ (((x) == I2S1) ? (4) : (-1))) /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) /* @brief Interrupt source number */ #define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) /* @brief Has register of MCR. */ #define FSL_FEATURE_SAI_HAS_MCR (0) /* @brief Has bit field MICS of the MCR register. */ #define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) /* @brief Has register of MDR */ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) /* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) /* LLWU module features */ /* @brief Maximum number of pins connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) /* @brief Maximum number of internal modules connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) /* @brief Number of digital filters. */ #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4) /* @brief Has MF register. */ #define FSL_FEATURE_LLWU_HAS_MF (1) /* @brief Has PF register. */ #define FSL_FEATURE_LLWU_HAS_PF (1) /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) /* @brief Has no internal module wakeup flag register. */ #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) /* @brief Has external pin 0 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOA_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0) /* @brief Has external pin 1 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOA_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (3) /* @brief Has external pin 2 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOA_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (13) /* @brief Has external pin 3 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (14) /* @brief Has external pin 4 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (18) /* @brief Has external pin 5 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (19) /* @brief Has external pin 6 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (23) /* @brief Has external pin 7 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (31) /* @brief Has external pin 8 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (1) /* @brief Has external pin 9 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOB_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (3) /* @brief Has external pin 10 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOB_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) /* @brief Has external pin 11 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOB_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (7) /* @brief Has external pin 12 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOB_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (9) /* @brief Has external pin 13 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOB_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (14) /* @brief Has external pin 14 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOB_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (16) /* @brief Has external pin 15 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOB_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (19) /* @brief Has external pin 16 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) /* @brief Has external pin 17 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) /* @brief Has external pin 18 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) /* @brief Has external pin 19 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) /* @brief Has external pin 20 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) /* @brief Has external pin 21 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) /* @brief Has external pin 22 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) /* @brief Has external pin 23 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) /* @brief Has external pin 24 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) /* @brief Has external pin 25 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) /* @brief Has external pin 26 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) /* @brief Has external pin 27 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) /* @brief Has external pin 28 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) /* @brief Has external pin 29 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) /* @brief Has external pin 30 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) /* @brief Has external pin 31 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) /* @brief Has internal module 0 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) /* @brief Has internal module 1 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) /* @brief Has internal module 2 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) /* @brief Has internal module 3 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) /* @brief Has internal module 4 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) /* @brief Has internal module 5 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) /* @brief Has internal module 6 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (1) /* @brief Has internal module 7 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) /* @brief Has LLWU_VERID. */ #define FSL_FEATURE_LLWU_HAS_VERID (1) /* @brief Has LLWU_PARAM. */ #define FSL_FEATURE_LLWU_HAS_PARAM (1) /* @brief LLWU register bit width. */ #define FSL_FEATURE_LLWU_REG_BITWIDTH (32) /* @brief Has DMA Enable register LLWU_DE. */ #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) /* LMEM module features */ /* @brief Has process identifier support. */ #define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (0) /* @brief Support instruction cache demote. */ #define FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE (1) /* @brief Has no NONCACHEABLE section. */ #define FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION (1) /* @brief L1 ICACHE line size in byte. */ #define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32) /* @brief L1 DCACHE line size in byte. */ #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32) /* LPI2C module features */ /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) /* LPIT module features */ /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ #define FSL_FEATURE_LPIT_TIMER_COUNT (4) /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ #define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0) /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ #define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (0) /* LPSPI module features */ /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) \ (((x) == LPSPI0) ? (4) : \ (((x) == LPSPI1) ? (4) : \ (((x) == LPSPI2) ? (16) : \ (((x) == LPSPI3) ? (16) : (-1))))) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* LPTMR module features */ /* @brief Has shared interrupt handler with another LPTMR module. */ #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) /* @brief Whether LPTMR counter is 32 bits width. */ #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) /* @brief Do not has prescaler clock source 1. */ #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) /* LPUART module features */ /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPUART_HAS_FIFO (1) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (1) /* @brief Hardware flow control (RTS, CTS) is supported. */ #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) /* @brief Infrared (modulation) is supported. */ #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) /* @brief 2 bits long stop bit is available. */ #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) /* @brief If 10-bit mode is supported. */ #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) /* @brief If 7-bit mode is supported. */ #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) /* @brief Baud rate fine adjustment is available. */ #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) /* @brief Baud rate oversampling is available. */ #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) /* @brief Baud rate oversampling is available. */ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ (((x) == LPUART0) ? (4) : \ (((x) == LPUART1) ? (4) : \ (((x) == LPUART2) ? (8) : \ (((x) == LPUART3) ? (8) : \ (((x) == LPUART4) ? (8) : \ (((x) == LPUART5) ? (8) : \ (((x) == LPUART6) ? (8) : \ (((x) == LPUART7) ? (8) : (-1))))))))) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) /* @brief Has improved smart card (ISO7816 protocol) support. */ #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) /* @brief Has local operation network (CEA709.1-B protocol) support. */ #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has separate RX and TX interrupts. */ #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) /* @brief Has LPAURT_PARAM. */ #define FSL_FEATURE_LPUART_HAS_PARAM (1) /* @brief Has LPUART_VERID. */ #define FSL_FEATURE_LPUART_HAS_VERID (1) /* @brief Has LPUART_GLOBAL. */ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) /* LTC module features */ /* @brief LTC module supports DES algorithm. */ #define FSL_FEATURE_LTC_HAS_DES (0) /* @brief LTC module supports PKHA algorithm. */ #define FSL_FEATURE_LTC_HAS_PKHA (0) /* @brief LTC module supports SHA algorithm. */ #define FSL_FEATURE_LTC_HAS_SHA (0) /* @brief LTC module supports AES GCM mode. */ #define FSL_FEATURE_LTC_HAS_GCM (0) /* @brief LTC module supports DPAMS registers. */ #define FSL_FEATURE_LTC_HAS_DPAMS (0) /* @brief LTC module supports AES with 24 bytes key. */ #define FSL_FEATURE_LTC_HAS_AES192 (0) /* @brief LTC module supports AES with 32 bytes key. */ #define FSL_FEATURE_LTC_HAS_AES256 (0) /* SMC module features */ /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ #define FSL_FEATURE_SMC_HAS_PSTOPO (0) /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ #define FSL_FEATURE_SMC_HAS_LPOPO (0) /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ #define FSL_FEATURE_SMC_HAS_PORPO (0) /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ #define FSL_FEATURE_SMC_HAS_LPWUI (0) /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) /* @brief Has stop submode. */ #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (0) /* @brief Has stop submode 0(VLLS0). */ #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (0) /* @brief Has stop submode 2(VLLS2). */ #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0) /* @brief Has SMC_PARAM. */ #define FSL_FEATURE_SMC_HAS_PARAM (1) /* @brief Has SMC_VERID. */ #define FSL_FEATURE_SMC_HAS_VERID (1) /* @brief Has SMC_CSRE. */ #define FSL_FEATURE_SMC_HAS_CSRE (1) /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) /* @brief Has tamper reset (register bit SRS[TAMPER]). */ #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (1) /* @brief Has security violation reset (register bit SRS[SECVIO]). */ #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (1) /* @brief Has security violation reset (register bit SRS[VBAT]). */ #define FSL_FEATURE_SMC_HAS_SRS_VBAT (1) /* @brief Has security violation reset (register bit SRS[CORE0]). */ #define FSL_FEATURE_SMC_HAS_SRS_CORE0 (1) /* @brief Has security violation reset (register bit SRS[CORE1]). */ #define FSL_FEATURE_SMC_HAS_SRS_CORE1 (1) /* @brief Has security violation reset (register bit SRIE[VBAT]). */ #define FSL_FEATURE_SMC_HAS_SRIE_VBAT (1) /* @brief Has security violation reset (register bit SRIE[CORE0]). */ #define FSL_FEATURE_SMC_HAS_SRIE_CORE0 (0) /* @brief Has security violation reset (register bit SRIE[CORE1]). */ #define FSL_FEATURE_SMC_HAS_SRIE_CORE1 (0) /* @brief Width of SMC registers. */ #define FSL_FEATURE_SMC_REG_WIDTH (32) /* MU module features */ /* @brief MU side for current core */ #define FSL_FEATURE_MU_SIDE_A (1) /* @brief MU Has register CCR */ #define FSL_FEATURE_MU_HAS_CCR (0) /* @brief MU Has register SR[RS], BSR[ARS] */ #define FSL_FEATURE_MU_HAS_SR_RS (1) /* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */ #define FSL_FEATURE_MU_HAS_RESET_INT (1) /* @brief MU Has register SR[MURIP] */ #define FSL_FEATURE_MU_HAS_SR_MURIP (0) /* @brief MU Has register SR[HRIP] */ #define FSL_FEATURE_MU_HAS_SR_HRIP (0) /* @brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */ #define FSL_FEATURE_MU_NO_CLKE (0) /* @brief MU does not support NMI, CR[NMI]. */ #define FSL_FEATURE_MU_NO_NMI (0) /* @brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */ #define FSL_FEATURE_MU_NO_RSTH (0) /* @brief MU does not supports MU reset, CR[MUR]. */ #define FSL_FEATURE_MU_NO_MUR (0) /* @brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */ #define FSL_FEATURE_MU_NO_HR (0) /* @brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */ #define FSL_FEATURE_MU_HAS_HRM (0) /* @brief MU does not support check the other core power mode. SR[PM]. */ #define FSL_FEATURE_MU_NO_PM (0) /* @brief MU supports reset assert interrupt. CR[RAIE] or BCR[RAIE]. */ #define FSL_FEATURE_MU_HAS_RESET_ASSERT_INT (1) /* @brief MU supports reset de-assert interrupt. CR[RDIE] or BCR[RDIE]. */ #define FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT (1) /* interrupt module features */ /* @brief Lowest interrupt request number. */ #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) /* @brief Highest interrupt request number. */ #define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) /* PCC module features */ /* @brief PCC has SAI clock divider. */ #define FSL_FEATURE_PCC_HAS_SAI_DIVIDER (1) /* @brief Remove EWM Clock Gate. */ #define FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE (1) /* PORT module features */ /* @brief Has control lock (register bit PCR[LK]). */ #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) /* @brief Has open drain control (register bit PCR[ODE]). */ #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) /* @brief Has DMA request (register bit field PCR[IRQC] values). */ #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) /* @brief Has pull resistor selection available. */ #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (0) /* @brief Has pull resistor enable (register bit PCR[PE]). */ #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (0) /* @brief Has slew rate control (register bit PCR[SRE]). */ #define FSL_FEATURE_PORT_HAS_SLEW_RATE (0) /* @brief Has passive filter (register bit field PCR[PFE]). */ #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (0) /* @brief Has drive strength control (register bit PCR[DSE]). */ #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (0) /* @brief Has separate drive strength register (HDRVE). */ #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) /* @brief Has glitch filter (register IOFLT). */ #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) /* @brief Defines width of PCR[MUX] field. */ #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (0) /* @brief Has dedicated interrupt vector. */ #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (1) /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (1) /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (1) /* QSPI module features */ /* @brief QSPI lookup table depth. */ #define FSL_FEATURE_QSPI_LUT_DEPTH (64) /* @brief QSPI Tx FIFO depth. */ #define FSL_FEATURE_QSPI_TXFIFO_DEPTH (16) /* @brief QSPI Rx FIFO depth. */ #define FSL_FEATURE_QSPI_RXFIFO_DEPTH (16) /* @brief QSPI AHB buffer count. */ #define FSL_FEATURE_QSPI_AHB_BUFFER_COUNT (4) /* @brief QSPI has command usage error flag. */ #define FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR (0) /* @brief QSPI support parallel mode. */ #define FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE (0) /* @brief QSPI support dual die. */ #define FSL_FEATURE_QSPI_SUPPORT_DUAL_DIE (0) /* @brief there is no SCLKCFG bit in MCR register. */ #define FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL (0) /* @brief there is no AITEF bit in FR register. */ #define FSL_FEATURE_QSPI_HAS_NO_AITEF (1) /* @brief there is no AIBSEF bit in FR register. */ #define FSL_FEATURE_QSPI_HAS_NO_AIBSEF (0) /* @brief there is no TXDMA and TXWA bit in SR register. */ #define FSL_FEATURE_QSPI_HAS_NO_TXDMA (0) /* @brief there is no SFACR register. */ #define FSL_FEATURE_QSPI_HAS_NO_SFACR (0) /* @brief there is no TDH bit in FLSHCR register. */ #define FSL_FEATURE_QSPI_HAS_NO_TDH (0) /* @brief QSPI AHB buffer size in byte. */ #define FSL_FEATURE_QSPI_AHB_BUFFER_SIZE (128U) /* @brief QSPI AMBA base address. */ #define FSL_FEATURE_QSPI_AMBA_BASE (0xC0000000U) /* @brief QSPI AHB buffer ARDB base address. */ #define FSL_FEATURE_QSPI_ARDB_BASE (0x24000000U) /* SCG module features */ /* @brief Has platform clock divider SCG_CSR[DIVPLAT]. */ #define FSL_FEATURE_SCG_HAS_DIVPLAT (1) /* @brief Has bus clock divider SCG_CSR[DIVBUS]. */ #define FSL_FEATURE_SCG_HAS_DIVBUS (1) /* @brief Has external clock divide ratio SCG_CSR[DIVEXT]. */ #define FSL_FEATURE_SCG_HAS_DIVEXT (0) /* @brief Has OSC capacitor setting SOSCCFG[SC2P ~ SC16P]. */ #define FSL_FEATURE_SCG_HAS_OSC_SCXP (0) /* @brief Has SOSCCSR[SOSCERCLKEN]. */ #define FSL_FEATURE_SCG_HAS_OSC_ERCLK (0) /* @brief Has OSC freq range SOSCCFG[RANGE]. */ #define FSL_FEATURE_SCG_HAS_SOSC_RANGE (0) /* @brief Has CLKOUT configure register SCG_CLKOUTCNFG. */ #define FSL_FEATURE_SCG_HAS_CLKOUTCNFG (1) /* @brief Has SCG_SOSCDIV[SOSCDIV1]. */ #define FSL_FEATURE_SCG_HAS_SOSCDIV1 (1) /* @brief Has SCG_SOSCDIV[SOSCDIV3]. */ #define FSL_FEATURE_SCG_HAS_SOSCDIV3 (1) /* @brief Has SCG_SIRCDIV[SIRCDIV1]. */ #define FSL_FEATURE_SCG_HAS_SIRCDIV1 (1) /* @brief Has SCG_SIRCDIV[SIRCDIV3]. */ #define FSL_FEATURE_SCG_HAS_SIRCDIV3 (1) /* @brief Has SCG_SIRCCSR[LPOPO]. */ #define FSL_FEATURE_SCG_HAS_SIRC_LPOPO (1) /* @brief Has SCG_FIRCDIV[FIRCDIV1]. */ #define FSL_FEATURE_SCG_HAS_FIRCDIV1 (1) /* @brief Has SCG_FIRCDIV[FIRCDIV3]. */ #define FSL_FEATURE_SCG_HAS_FIRCDIV3 (1) /* @brief Has SCG_FIRCCSR[FIRCLPEN]. */ #define FSL_FEATURE_SCG_HAS_FIRCLPEN (1) /* @brief Has SCG_FIRCCSR[FIRCREGOFF]. */ #define FSL_FEATURE_SCG_HAS_FIRCREGOFF (0) /* @brief Has SCG_SPLLDIV[SPLLDIV1]. */ #define FSL_FEATURE_SCG_HAS_SPLLDIV1 (1) /* @brief Has SCG_SPLLDIV[SPLLDIV3]. */ #define FSL_FEATURE_SCG_HAS_SPLLDIV3 (1) /* @brief Has SCG_SPLLCFG[PLLPOSTDIV1]. */ #define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV1 (0) /* @brief Has SCG_SPLLCFG[PLLPOSTDIV2]. */ #define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV2 (0) /* @brief Has SCG_SPLLCFG[PLLS]. */ #define FSL_FEATURE_SCG_HAS_SPLL_PLLS (1) /* @brief Has SCG_SPLLCFG[BYPASS]. */ #define FSL_FEATURE_SCG_HAS_SPLL_BYPASS (0) /* @brief Has SCG_SPLLCFG[PFDSEL]. */ #define FSL_FEATURE_SCG_HAS_SPLL_PFDSEL (1) /* @brief Has SCG_SPLLCSR[SPLLCM]. */ #define FSL_FEATURE_SCG_HAS_SPLL_MONITOR (0) /* @brief Has SCG_LPFLLDIV[FLLDIV1]. */ #define FSL_FEATURE_SCG_HAS_FLLDIV1 (0) /* @brief Has SCG_LPFLLDIV[FLLDIV3]. */ #define FSL_FEATURE_SCG_HAS_FLLDIV3 (0) /* @brief Has low power FLL, SCG_LPFLLCSR. */ #define FSL_FEATURE_SCG_HAS_LPFLL (0) /* @brief Has system PLL, SCG_SPLLCSR. */ #define FSL_FEATURE_SCG_HAS_SPLL (1) /* @brief Has system PLL PFD, SCG_SPLLPFD. */ #define FSL_FEATURE_SCG_HAS_SPLLPFD (1) /* @brief Has auxiliary PLL, SCG_APLLCSR. */ #define FSL_FEATURE_SCG_HAS_APLL (1) /* @brief Has RTC OSC control, SCG_ROSCCSR. */ #define FSL_FEATURE_SCG_HAS_ROSC (1) /* @brief Has RTC OSC clock source. */ #define FSL_FEATURE_SCG_HAS_ROSC_SYS_CLK_SRC (1) /* @brief Has RTC OSC clock out select. */ #define FSL_FEATURE_SCG_HAS_ROSC_CLKOUT (1) /* @brief Has EXTERNAL clock out select. */ #define FSL_FEATURE_SCG_HAS_EXT_CLKOUT (0) /* @brief Has no System OSC configuration register, SCG_SOSCCFG. */ #define FSL_FEATURE_SCG_HAS_NO_SOSCCFG (1) /* @brief Has no SCG_SOSCCSR[SOSCEN]. */ #define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCEN (1) /* @brief Has no SCG_SOSCCSR[SOSCSTEN]. */ #define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCSTEN (1) /* @brief Has no SCG_SOSCCSR[SOSCLPEN]. */ #define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCLPEN (1) /* @brief Has no FIRC trim configuration register, SCG_FIRCTCFG. */ #define FSL_FEATURE_SCG_HAS_NO_FIRCTCFG (1) /* @brief Has FIRC trim source USB0 Start of Frame. */ #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB0 (1) /* @brief Has FIRC trim source USB1 Start of Frame. */ #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB1 (1) /* @brief Has FIRC trim source system OSC. */ #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_SOSC (1) /* @brief Has FIRC trim source RTC OSC. */ #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_RTCOSC (1) /* SEMA42 module features */ /* @brief Gate counts */ #define FSL_FEATURE_SEMA42_GATE_COUNT (16) /* SIM module features */ /* @brief Has USB FS divider. */ #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (0) /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (0) /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ #define FSL_FEATURE_SIM_OPT_UART_COUNT (0) /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) /* @brief Has FTM module(s) configuration. */ #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) /* @brief Number of FTM modules. */ #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) /* @brief Number of FTM triggers with selectable source. */ #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) /* @brief Has TPM module(s) configuration. */ #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) /* @brief The highest TPM module index. */ #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) /* @brief Has TPM module with index 0. */ #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ #define FSL_FEATURE_SIM_OPT_ADC_COUNT (0) /* @brief ADC module has alternate trigger (register bit SOPT7[ADC0ALTTRGEN]). */ #define FSL_FEATURE_SIM_OPT_ADC_HAS_ALTERNATE_TRIGGER (0) /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (0) /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (0) /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (0) /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (0) /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (0) /* @brief Has device die ID (register bit field SDID[DIEID]). */ #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (0) /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (0) /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) /* @brief Has flash for core0(CM4) (register bit field FCFG1[CORE0_PFSIZE]). */ #define FSL_FEATURE_SIM_FCFG_HAS_CORE0_PFSIZE (0) /* @brief Has flash for core1(CM0) (register bit field FCFG1[CORE1_PFSIZE]). */ #define FSL_FEATURE_SIM_FCFG_HAS_CORE1_PFSIZE (0) /* @brief Has sram for core0(CM4) (register bit field FCFG1[CORE0_SRAMSIZE]). */ #define FSL_FEATURE_SIM_FCFG_HAS_CORE0_SRAMSIZE (0) /* @brief Has sram for core1(CM0) (register bit field FCFG1[CORE1_SRAMSIZE]). */ #define FSL_FEATURE_SIM_FCFG_HAS_CORE1_SRAMSIZE (0) /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (0) /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) /* @brief Has miscellanious control register (register MCR). */ #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) /* @brief Has COP watchdog (registers COPC and SRVCOP). */ #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ #define FSL_FEATURE_SIM_HAS_COP_STOP (0) /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) /* @brief Has MISCCTRL reg. */ #define FSL_FEATURE_SIM_HAS_MISCCTRL (0) /* @brief Has LTCEN bit (e.g SIM_MISCCTRL). */ #define FSL_FEATURE_SIM_HAS_MISCCTRL_LTCEN (0) /* @brief Has DMAINTSEL0 bit (e.g SIM_MISCCTRL). */ #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL0 (0) /* @brief Has DMAINTSEL1 bit (e.g SIM_MISCCTRL). */ #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL1 (0) /* @brief Has DMAINTSEL2 bit (e.g SIM_MISCCTRL). */ #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL2 (0) /* @brief Has DMAINTSEL3 bit (e.g SIM_MISCCTRL). */ #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL3 (0) /* @brief Has SECKEY0 reg. */ #define FSL_FEATURE_SIM_HAS_SECKEY0 (0) /* @brief Has SECKEY bit (e.g SIM_SECKEY0). */ #define FSL_FEATURE_SIM_HAS_SECKEY0_SECKEY (0) /* @brief Has SECKEY1 reg. */ #define FSL_FEATURE_SIM_HAS_SECKEY1 (0) /* @brief Has SECKEY bit (e.g SIM_SECKEY1). */ #define FSL_FEATURE_SIM_HAS_SECKEY1_SECKEY (0) /* @brief Has SECKEY2 reg. */ #define FSL_FEATURE_SIM_HAS_SECKEY2 (0) /* @brief Has SECKEY bit (e.g SIM_SECKEY2). */ #define FSL_FEATURE_SIM_HAS_SECKEY2_SECKEY (0) /* @brief Has SECKEY3 reg. */ #define FSL_FEATURE_SIM_HAS_SECKEY3 (0) /* @brief Has SECKEY bit (e.g SIM_SECKEY3). */ #define FSL_FEATURE_SIM_HAS_SECKEY3_SECKEY (0) /* @brief Has no SDID reg. */ #define FSL_FEATURE_SIM_HAS_NO_SDID (1) /* @brief Has no UID reg. */ #define FSL_FEATURE_SIM_HAS_NO_UID (1) /* @brief Has RFADDRL and RFADDRH registers. */ #define FSL_FEATURE_SIM_HAS_RF_MAC_ADDR (0) /* @brief Has SYSTICK_CLK_EN bit in SIM_MISC2 register. */ #define FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN (0) /* @brief Has UIDM registers. */ #define FSL_FEATURE_SIM_HAS_UIDM (0) /* SNVS module features */ /* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */ #define FSL_FEATURE_SNVS_HAS_SRTC (1) /* @brief Has Set Lock. */ #define FSL_FEATURE_SNVS_HAS_SET_LOCK (1) /* @brief Has State Transition. */ #define FSL_FEATURE_SNVS_HAS_STATE_TRANSITION (1) /* SysTick module features */ /* @brief Systick has external reference clock. */ #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) /* @brief Systick external reference clock is core clock divided by this value. */ #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) /* TPM module features */ /* @brief Number of channels. */ #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ (((x) == TPM0) ? (6) : \ (((x) == TPM1) ? (2) : \ (((x) == TPM2) ? (2) : \ (((x) == TPM3) ? (6) : \ (((x) == TPM4) ? (6) : \ (((x) == TPM5) ? (2) : \ (((x) == TPM6) ? (2) : \ (((x) == TPM7) ? (6) : (-1))))))))) /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) /* @brief Has TPM_PARAM. */ #define FSL_FEATURE_TPM_HAS_PARAM (1) /* @brief Has TPM_VERID. */ #define FSL_FEATURE_TPM_HAS_VERID (1) /* @brief Has TPM_GLOBAL. */ #define FSL_FEATURE_TPM_HAS_GLOBAL (1) /* @brief Has TPM_TRIG. */ #define FSL_FEATURE_TPM_HAS_TRIG (1) /* @brief Has counter pause on trigger. */ #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) /* @brief Has external trigger selection. */ #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) /* @brief Has TPM_COMBINE register. */ #define FSL_FEATURE_TPM_HAS_COMBINE (1) /* @brief Whether COMBINE register has effect. */ #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1) /* @brief Has TPM_POL. */ #define FSL_FEATURE_TPM_HAS_POL (1) /* @brief Has TPM_FILTER register. */ #define FSL_FEATURE_TPM_HAS_FILTER (1) /* @brief Whether FILTER register has effect. */ #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1) /* @brief Has TPM_QDCTRL register. */ #define FSL_FEATURE_TPM_HAS_QDCTRL (1) /* @brief Whether QDCTRL register has effect. */ #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1) /* TRNG module features */ /* No feature definitions */ /* TSTMR module features */ /* @brief TSTMR clock frequency is 1MHZ. */ #define FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ (1) /* USBHS module features */ /* @brief EHCI module instance count */ #define FSL_FEATURE_USBHS_EHCI_COUNT (2) /* @brief Number of endpoints supported */ #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) /* USBPHY module features */ /* @brief USBPHY contain DCD analog module */ #define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) /* @brief USBPHY has register TRIM_OVERRIDE_EN */ #define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) /* @brief USBPHY is 28FDSOI */ #define FSL_FEATURE_USBPHY_28FDSOI (0) /* WDOG module features */ /* @brief Watchdog is available. */ #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) /* @brief WDOG_CNT can be 32-bit written. */ #define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1) /* XRDC module features */ /* @brief Has domain ID of faulted access (register bit FDID[FDID]). */ #define FSL_FEATURE_XRDC_HAS_FDID (0) /* @brief Has special 4-state model option (register bit PID[SP4SM]). */ #define FSL_FEATURE_XRDC_HAS_PID_SP4SM (0) /* @brief Does not have logical partition identifier (register bit MDA_W[LPID]). */ #define FSL_FEATURE_XRDC_NO_MDA_LPID (1) /* @brief Does not have logical partition enable option (register bit MDA_W[LPE]). */ #define FSL_FEATURE_XRDC_NO_MDA_LPE (1) /* @brief Does not have peripheral semaphore enable option (register bit PDAC_W0[SE]). */ #define FSL_FEATURE_XRDC_NO_PDAC_SE (0) /* @brief Does not have peripheral semaphore number (register bit PDAC_W0[SNUM]). */ #define FSL_FEATURE_XRDC_NO_PDAC_SNUM (0) /* @brief Has peripheral excessive access lock owner (register bit PDAC_W0[EALO]). */ #define FSL_FEATURE_XRDC_HAS_PDAC_EALO (0) /* @brief Has peripheral excessive access lock option (register bit PDAC_W1[EAL]). */ #define FSL_FEATURE_XRDC_HAS_PDAC_EAL (0) /* @brief Has memory region end address (register bit MRGD_W1[ENDADDR]). */ #define FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR (0) /* @brief Does not have region size configuration (register bit MRGD_W1[SZ]). */ #define FSL_FEATURE_XRDC_NO_MRGD_SZ (0) /* @brief Does not have subregion disable option (register bit MRGD_W1[SRD]). */ #define FSL_FEATURE_XRDC_NO_MRGD_SRD (0) /* @brief Does not have memory region semaphore enable option (register bit MRGD_W2[SE]). */ #define FSL_FEATURE_XRDC_NO_MRGD_SE (0) /* @brief Does not have memory region semaphore number (register bit MRGD_W2[SNUM]). */ #define FSL_FEATURE_XRDC_NO_MRGD_SNUM (0) /* @brief Does not domain x access control policy option (register bit MRGD_W2[DxACP]). */ #define FSL_FEATURE_XRDC_NO_MRGD_DXACP (0) /* @brief Has memory region excessive access lock owner (register bit MRGD_W2[EALO]). */ #define FSL_FEATURE_XRDC_HAS_MRGD_EALO (0) /* @brief Has domain x access policy select option (register bit MRGD_W2[DxSEL]). */ #define FSL_FEATURE_XRDC_HAS_MRGD_DXSEL (0) /* @brief Has memory region excessive access lock option (register bit MRGD_W3[EAL]). */ #define FSL_FEATURE_XRDC_HAS_MRGD_EAL (0) /* @brief Does not have lock option in MRGD_W3 register (register bit MRGD_W3[LK2]). */ #define FSL_FEATURE_XRDC_NO_MRGD_W3_LK2 (0) /* @brief Does not have valid option in MRGD_W3 register (register bit MRGD_W3[VLD]). */ #define FSL_FEATURE_XRDC_NO_MRGD_W3_VLD (0) /* @brief Has code region indicator select option (register bit MRGD_W3[CR]). */ #define FSL_FEATURE_XRDC_HAS_MRGD_CR (0) /* @brief XRDC domain number (reset value of HWCFG0[NDID] plus 1). */ #define FSL_FEATURE_XRDC_DOMAIN_COUNT (8) #endif /* _MCIMX7U5_cm4_FEATURES_H_ */