/* ** ################################################################### ** Processors: MCIMX7U3CVP06 ** MCIMX7U3DVK07 ** ** Compilers: GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX7ULPRM, Rev. 0, Nov. 2018 ** Version: rev. 7.0, 2018-11-05 ** Build: b200408 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCIMX7U3_cm4 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. ** Copyright 2016-2020 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2016-04-13) ** Initial version. ** - rev. 2.0 (2016-07-19) ** RevC Header ER ** - rev. 3.0 (2017-02-28) ** RevD Header ER ** - rev. 4.0 (2017-05-02) ** RevE Header ER ** - rev. 5.0 (2017-12-22) ** RevA(B0) Header GA ** - rev. 6.0 (2018-02-01) ** RevB(B0) Header GA ** - rev. 7.0 (2018-11-05) ** RevA(B1) Header ** ** ################################################################### */ /*! * @file MCIMX7U3_cm4.h * @version 7.0 * @date 2018-11-05 * @brief CMSIS Peripheral Access Layer for MCIMX7U3_cm4 * * CMSIS Peripheral Access Layer for MCIMX7U3_cm4 */ #ifndef _MCIMX7U3_CM4_H_ #define _MCIMX7U3_CM4_H_ /**< Symbol preventing repeated inclusion */ /** Memory map major version (memory maps with equal major version number are * compatible) */ #define MCU_MEM_MAP_VERSION 0x0700U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U /* ---------------------------------------------------------------------------- -- Interrupt vector numbers ---------------------------------------------------------------------------- */ /*! * @addtogroup Interrupt_vector_numbers Interrupt vector numbers * @{ */ /** Interrupt Number Definitions */ #define NUMBER_OF_INT_VECTORS 144 /**< Number of interrupts in the Vector table */ typedef enum IRQn { /* Auxiliary constants */ NotAvail_IRQn = -128, /**< Not available device specific interrupt */ /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ /* Device specific interrupts */ CTI0_IRQn = 0, /**< Cross Trigger Interface for CM4 */ DMA0_0_4_IRQn = 1, /**< DMA Channel 0, 4 Transfer Complete */ DMA0_1_5_IRQn = 2, /**< DMA Channel 1, 5 Transfer Complete */ DMA0_2_6_IRQn = 3, /**< DMA Channel 2, 6 Transfer Complete */ DMA0_3_7_IRQn = 4, /**< DMA Channel 3, 7 Transfer Complete */ DMA0_8_12_IRQn = 5, /**< DMA Channel 8, 12 Transfer Complete */ DMA0_9_13_IRQn = 6, /**< DMA Channel 9, 13 Transfer Complete */ DMA0_10_14_IRQn = 7, /**< DMA Channel 10, 14 Transfer Complete */ DMA0_11_15_IRQn = 8, /**< DMA Channel 11, 15 Transfer Complete */ DMA0_16_20_IRQn = 9, /**< DMA Channel 16, 20 Transfer Complete */ DMA0_17_21_IRQn = 10, /**< DMA Channel 17, 21 Transfer Complete */ DMA0_18_22_IRQn = 11, /**< DMA Channel 18, 22 Transfer Complete */ DMA0_19_23_IRQn = 12, /**< DMA Channel 19, 23 Transfer Complete */ DMA0_24_28_IRQn = 13, /**< DMA Channel 24, 28 Transfer Complete */ DMA0_25_29_IRQn = 14, /**< DMA Channel 25, 29 Transfer Complete */ DMA0_26_30_IRQn = 15, /**< DMA Channel 26, 30 Transfer Complete */ DMA0_27_31_IRQn = 16, /**< DMA Channel 27, 31 Transfer Complete */ DMA0_Error_IRQn = 17, /**< DMA Error Interrupt - All Channels */ MCM0_IRQn = 18, /**< MCM Interrupt */ EWM_IRQn = 19, /**< External Watchdog Monitor Interrupt */ LLWU0_IRQn = 20, /**< Low Leakage Wake Up */ SIM_IRQn = 21, /**< System Integation Module */ MU_A_IRQn = 22, /**< Messaging Unit - Side A */ Reserved39_IRQn = 23, /**< Secured JTAG Controller */ Software1_IRQn = 24, /**< Software Interrupt */ Software2_IRQn = 25, /**< Software Interrupt */ WDOG0_IRQn = 26, /**< Watchdog Interrupt */ SCG0_IRQn = 27, /**< System Clock Generator for M4 domain */ QSPI_IRQn = 28, /**< Quad Serial Peripheral Interface */ LTC_IRQn = 29, /**< Low Power Trusted Cryptography */ XRDC_IRQn = 30, /**< Extended Domain Resource Controller */ SNVS_IRQn = 31, /**< Secure Non-Volatile Storage Consolidated Interrupt */ TRNG0_IRQn = 32, /**< Random Number Generator */ LPIT0_IRQn = 33, /**< Low Power Periodic Interrupt Timer */ PMC0_IRQn = 34, /**< Power Management Control interrupts for M4 domain */ CMC0_IRQn = 35, /**< Core Mode Controller interrupts for M4 domain */ LPTMR0_IRQn = 36, /**< Low Power Timer */ LPTMR1_IRQn = 37, /**< Low Power Timer */ TPM0_IRQn = 38, /**< Timer PWM module */ TPM1_IRQn = 39, /**< Timer PWM module */ TPM2_IRQn = 40, /**< Timer PWM module */ TPM3_IRQn = 41, /**< Timer PWM module */ FLEXIO0_IRQn = 42, /**< Flexible IO */ LPI2C0_IRQn = 43, /**< Inter-integrated circuit 0 */ LPI2C1_IRQn = 44, /**< Inter-integrated circuit 1 */ LPI2C2_IRQn = 45, /**< Inter-integrated circuit 2 */ LPI2C3_IRQn = 46, /**< Inter-integrated circuit 3 */ I2S0_IRQn = 47, /**< Serial Audio Interface 0 */ I2S1_IRQn = 48, /**< Serial Audio Interface 1 */ LPSPI0_IRQn = 49, /**< Low Power Serial Peripheral Interface */ LPSPI1_IRQn = 50, /**< Low Power Serial Peripheral Interface */ LPUART0_IRQn = 51, /**< Low Power UART */ LPUART1_IRQn = 52, /**< Low Power UART */ LPUART2_IRQn = 53, /**< Low Power UART */ LPUART3_IRQn = 54, /**< Low Power UART */ DPM_IRQn = 55, /**< Dynamic Process Monitor */ PCTLA_IRQn = 56, /**< Port A pin interrupt */ PCTLB_IRQn = 57, /**< Port B pin interrupt */ ADC0_IRQn = 58, /**< Analog to Digital Convertor */ ADC1_IRQn = 59, /**< Analog to Digital Convertor */ CMP0_IRQn = 60, /**< Comparator */ CMP1_IRQn = 61, /**< Comparator */ DAC0_IRQn = 62, /**< Digital to Analog Convertor */ DAC1_IRQn = 63, /**< Digital to Analog Convertor */ WDOG1_IRQn = 64, /**< Watchdog Interrupt from A7 subsystem */ USB0_IRQn = 65, /**< USB 0 Interrupt from A7 subsystem */ USB1_IRQn = 66, /**< USB 1 Interrupt from A7 subsystem */ Reserved83_IRQn = 67, WDOG2_IRQn = 68, /**< Watchdog Interrupt from A7 subsystem */ USBPHY_IRQn = 69, /**< USB PHY (used in conjunction with USBOTG1) */ CMC1_IRQn = 70, /**< A7 resets */ Reserved87_IRQn = 71, /**< Reserved interrupt */ Reserved88_IRQn = 72, /**< Reserved interrupt */ Reserved89_IRQn = 73, /**< Reserved interrupt */ Reserved90_IRQn = 74, /**< Reserved interrupt */ Reserved91_IRQn = 75, /**< Reserved interrupt */ Reserved92_IRQn = 76, /**< Reserved interrupt */ Reserved93_IRQn = 77, /**< Reserved interrupt */ Reserved94_IRQn = 78, /**< Reserved interrupt */ Reserved95_IRQn = 79, /**< Reserved interrupt */ Reserved96_IRQn = 80, /**< Reserved interrupt */ Reserved97_IRQn = 81, /**< Reserved interrupt */ Reserved98_IRQn = 82, /**< Reserved interrupt */ Reserved99_IRQn = 83, /**< Reserved interrupt */ Reserved100_IRQn = 84, /**< Reserved interrupt */ Reserved101_IRQn = 85, /**< Reserved interrupt */ Reserved102_IRQn = 86, /**< Reserved interrupt */ Reserved103_IRQn = 87, /**< Reserved interrupt */ Reserved104_IRQn = 88, /**< Reserved interrupt */ Reserved105_IRQn = 89, /**< Reserved interrupt */ Reserved106_IRQn = 90, /**< Reserved interrupt */ Reserved107_IRQn = 91, /**< Reserved interrupt */ Reserved108_IRQn = 92, /**< Reserved interrupt */ Reserved109_IRQn = 93, /**< Reserved interrupt */ Reserved110_IRQn = 94, /**< Reserved interrupt */ Reserved111_IRQn = 95, /**< Reserved interrupt */ Reserved112_IRQn = 96, /**< Reserved interrupt */ Reserved113_IRQn = 97, /**< Reserved interrupt */ Reserved114_IRQn = 98, /**< Reserved interrupt */ Reserved115_IRQn = 99, /**< Reserved interrupt */ Reserved116_IRQn = 100, /**< Reserved interrupt */ Reserved117_IRQn = 101, /**< Reserved interrupt */ Reserved118_IRQn = 102, /**< Reserved interrupt */ Reserved119_IRQn = 103, /**< Reserved interrupt */ Reserved120_IRQn = 104, /**< Reserved interrupt */ Reserved121_IRQn = 105, /**< Reserved interrupt */ Reserved122_IRQn = 106, /**< Reserved interrupt */ Reserved123_IRQn = 107, /**< Reserved interrupt */ Reserved124_IRQn = 108, /**< Reserved interrupt */ Reserved125_IRQn = 109, /**< Reserved interrupt */ Reserved126_IRQn = 110, /**< Reserved interrupt */ Reserved127_IRQn = 111, /**< Reserved interrupt */ Reserved128_IRQn = 112, /**< Reserved interrupt */ Reserved129_IRQn = 113, /**< Reserved interrupt */ Reserved130_IRQn = 114, /**< Reserved interrupt */ Reserved131_IRQn = 115, /**< Reserved interrupt */ Reserved132_IRQn = 116, /**< Reserved interrupt */ Reserved133_IRQn = 117, /**< Reserved interrupt */ Reserved134_IRQn = 118, /**< Reserved interrupt */ Reserved135_IRQn = 119, /**< Reserved interrupt */ Reserved136_IRQn = 120, /**< Reserved interrupt */ Reserved137_IRQn = 121, /**< Reserved interrupt */ Reserved138_IRQn = 122, /**< Reserved interrupt */ Reserved139_IRQn = 123, /**< Reserved interrupt */ Reserved140_IRQn = 124, /**< Reserved interrupt */ Reserved141_IRQn = 125, /**< Reserved interrupt */ Reserved142_IRQn = 126, /**< Reserved interrupt */ Reserved143_IRQn = 127 /**< Reserved interrupt */ } IRQn_Type; /*! * @} */ /* end of group Interrupt_vector_numbers */ /* ---------------------------------------------------------------------------- -- Configuration of the Cortex-M4 Processor and Core Peripherals ---------------------------------------------------------------------------- */ /*! * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-M4 Processor and Core Peripherals * @{ */ #define __CM4_REV 0x0001 /**< Core revision r0p1 */ #define __MPU_PRESENT 1 /**< MPU present or not */ #define __NVIC_PRIO_BITS 4 /**< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1 /**< FPU present or not */ #include "core_cm4.h" /* Core Peripheral Access Layer */ #include "system_MCIMX7U3_cm4.h" /* Device specific configuration file */ /*! * @} */ /* end of group Cortex_Core_Configuration */ /* ---------------------------------------------------------------------------- -- Mapping Information ---------------------------------------------------------------------------- */ /*! * @addtogroup Mapping_Information Mapping Information * @{ */ /** Mapping Information */ /*! * @addtogroup iomuxc0_pads * @{ */ /******************************************************************************* * Definitions *******************************************************************************/ /*! * @brief Enumeration for the IOMUXC0 SW_MUX_CTL_PAD * * Defines the enumeration for the IOMUXC0 SW_MUX_CTL_PAD collections. */ typedef enum _iomuxc0_sw_mux_ctl_pad { kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA0 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA1 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA2 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA3 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA4 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA5 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA6 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA7 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA8 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA9 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA16 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA17 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA18 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA19 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA20 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA21 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA22 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA23 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA24 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA25 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA26 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA27 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA28 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA29 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA30 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTA31 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB0 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB1 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB2 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB3 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB4 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB5 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB6 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB7 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB8 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB9 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB10 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB11 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB12 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB13 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB14 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB15 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB16 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB17 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB18 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC0_IOMUXC0_SW_MUX_CTL_PAD_PTB19 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */ } iomuxc0_sw_mux_ctl_pad_t; /* @} */ /*! * @brief Enumeration for the IOMUXC0 select input * * Defines the enumeration for the IOMUXC0 select input collections. */ typedef enum _iomuxc0_select_input { kIOMUXC0_IOMUXC0_LPSPI0_IPP_IND_LPSPI_PCS0_SELECT_INPUT = 0U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPSPI0_IPP_IND_LPSPI_PCS1_SELECT_INPUT = 1U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPSPI0_IPP_IND_LPSPI_PCS2_SELECT_INPUT = 2U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPSPI0_IPP_IND_LPSPI_PCS3_SELECT_INPUT = 3U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPSPI0_IPP_IND_LPSPI_SCK_SELECT_INPUT = 4U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPSPI0_IPP_IND_LPSPI_SDI_SELECT_INPUT = 5U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPSPI0_IPP_IND_LPSPI_SDO_SELECT_INPUT = 6U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPSPI1_IPP_IND_LPSPI_PCS0_SELECT_INPUT = 7U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPSPI1_IPP_IND_LPSPI_PCS1_SELECT_INPUT = 8U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPSPI1_IPP_IND_LPSPI_PCS2_SELECT_INPUT = 9U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPSPI1_IPP_IND_LPSPI_PCS3_SELECT_INPUT = 10U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPSPI1_IPP_IND_LPSPI_SCK_SELECT_INPUT = 11U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPSPI1_IPP_IND_LPSPI_SDI_SELECT_INPUT = 12U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPSPI1_IPP_IND_LPSPI_SDO_SELECT_INPUT = 13U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM0_IPP_IND_LPTPM_CH0_SELECT_INPUT = 14U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM0_IPP_IND_LPTPM_CH1_SELECT_INPUT = 15U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM0_IPP_IND_LPTPM_CH2_SELECT_INPUT = 16U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM0_IPP_IND_LPTPM_CH3_SELECT_INPUT = 17U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM0_IPP_IND_LPTPM_CH4_SELECT_INPUT = 18U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM0_IPP_IND_LPTPM_CH5_SELECT_INPUT = 19U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM1_IPP_IND_LPTPM_CH0_SELECT_INPUT = 20U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM1_IPP_IND_LPTPM_CH1_SELECT_INPUT = 21U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM2_IPP_IND_LPTPM_CH0_SELECT_INPUT = 22U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM2_IPP_IND_LPTPM_CH1_SELECT_INPUT = 23U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM3_IPP_IND_LPTPM_CH0_SELECT_INPUT = 24U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM3_IPP_IND_LPTPM_CH1_SELECT_INPUT = 25U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM3_IPP_IND_LPTPM_CH2_SELECT_INPUT = 26U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM3_IPP_IND_LPTPM_CH3_SELECT_INPUT = 27U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM3_IPP_IND_LPTPM_CH4_SELECT_INPUT = 28U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM3_IPP_IND_LPTPM_CH5_SELECT_INPUT = 29U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPI2C0_IPP_IND_LPI2C_HREQ_SELECT_INPUT = 30U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPI2C0_IPP_IND_LPI2C_SCL_SELECT_INPUT = 31U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPI2C0_IPP_IND_LPI2C_SDA_SELECT_INPUT = 32U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPI2C1_IPP_IND_LPI2C_HREQ_SELECT_INPUT = 33U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPI2C1_IPP_IND_LPI2C_SCL_SELECT_INPUT = 34U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPI2C1_IPP_IND_LPI2C_SDA_SELECT_INPUT = 35U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPI2C2_IPP_IND_LPI2C_HREQ_SELECT_INPUT = 36U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPI2C2_IPP_IND_LPI2C_SCL_SELECT_INPUT = 37U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPI2C2_IPP_IND_LPI2C_SDA_SELECT_INPUT = 38U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPI2C3_IPP_IND_LPI2C_HREQ_SELECT_INPUT = 39U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPI2C3_IPP_IND_LPI2C_SCL_SELECT_INPUT = 40U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPI2C3_IPP_IND_LPI2C_SDA_SELECT_INPUT = 41U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM0_IPP_IND_LPTPM_CLK_SELECT_INPUT = 42U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM1_IPP_IND_LPTPM_CLK_SELECT_INPUT = 43U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM3_IPP_IND_LPTPM_CLK_SELECT_INPUT = 44U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_PCC_AIPS0_IPP_IND_EXTCLK55_SELECT_INPUT = 45U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_SAI0_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 46U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_SAI0_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 47U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_SAI0_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 48U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_SAI0_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 49U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_PCC_AIPS1_IPP_IND_EXTCLK42_SELECT_INPUT = 50U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 51U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 52U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 53U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 54U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_SAI0_IPP_IND_SAI_RXDATA0_SELECT_INPUT = 55U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_SAI0_IPP_IND_SAI_RXDATA1_SELECT_INPUT = 56U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_SAI1_IPP_IND_SAI_RXDATA0_SELECT_INPUT = 57U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_SAI1_IPP_IND_SAI_RXDATA1_SELECT_INPUT = 58U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_SAI1_IPP_IND_SAI_RXDATA2_SELECT_INPUT = 59U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_SAI1_IPP_IND_SAI_RXDATA3_SELECT_INPUT = 60U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPTPM2_IPP_IND_LPTPM_CLK_SELECT_INPUT = 61U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPUART0_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 62U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPUART0_IPP_IND_LPUART_RXD_SELECT_INPUT = 63U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPUART0_IPP_IND_LPUART_TXD_SELECT_INPUT = 64U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPUART1_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 65U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPUART1_IPP_IND_LPUART_RXD_SELECT_INPUT = 66U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPUART1_IPP_IND_LPUART_TXD_SELECT_INPUT = 67U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPUART2_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 68U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPUART2_IPP_IND_LPUART_RXD_SELECT_INPUT = 69U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPUART2_IPP_IND_LPUART_TXD_SELECT_INPUT = 70U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPUART3_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 71U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT = 72U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT = 73U, /**< IOMUXC select input index */ kIOMUXC0_IOMUXC0_D_IP_EWM_SYN_EWM_IN_SELECT_INPUT = 74U, /**< IOMUXC select input index */ } iomuxc0_select_input_t; /*! * @addtogroup iomuxc1_pads * @{ */ /******************************************************************************* * Definitions *******************************************************************************/ /*! * @brief Enumeration for the IOMUXC1 SW_MUX_CTL_PAD * * Defines the enumeration for the IOMUXC1 SW_MUX_CTL_PAD collections. */ typedef enum _iomuxc1_sw_mux_ctl_pad { kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC0 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC1 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC2 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC3 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC4 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC5 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC6 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC7 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC8 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC9 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC16 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC17 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC18 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTC19 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED0 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED1 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED2 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED3 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED4 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED5 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED6 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED7 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED8 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED9 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED10 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED11 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD0 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD1 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD2 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD3 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD4 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD5 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD6 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD7 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD8 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD9 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD10 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTD11 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED12 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED13 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED14 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED15 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED16 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED17 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED18 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED19 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED20 = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED21 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED22 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED23 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED24 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED25 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED26 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED27 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED28 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED29 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED30 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED31 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE0 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE1 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE2 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE3 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE4 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE5 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE6 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE7 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE8 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE9 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE10 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE11 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE12 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE13 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE14 = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTE15 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED32 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED33 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED34 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED35 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED36 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED37 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED38 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED39 = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED40 = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED41 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED42 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED43 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED44 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED45 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED46 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_RESERVED47 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF0 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF1 = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF2 = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF3 = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF4 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF5 = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF6 = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF7 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF8 = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF9 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF10 = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF11 = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF12 = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF13 = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF14 = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF15 = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF16 = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF17 = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF18 = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */ kIOMUXC1_IOMUXC1_SW_MUX_CTL_PAD_PTF19 = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */ } iomuxc1_sw_mux_ctl_pad_t; /*! * @brief Enumeration for the IOMUXC1 select input * * Defines the enumeration for the IOMUXC1 select input collections. */ typedef enum _iomuxc1_select_input { kIOMUXC1_IOMUXC1_USDHC1_IPP_WP_ON_SELECT_INPUT = 0U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO0_SELECT_INPUT = 1U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO1_SELECT_INPUT = 2U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO2_SELECT_INPUT = 3U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO3_SELECT_INPUT = 4U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO4_SELECT_INPUT = 5U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO5_SELECT_INPUT = 6U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO6_SELECT_INPUT = 7U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO7_SELECT_INPUT = 8U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO8_SELECT_INPUT = 9U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO9_SELECT_INPUT = 10U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO10_SELECT_INPUT = 11U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO11_SELECT_INPUT = 12U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO12_SELECT_INPUT = 13U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO13_SELECT_INPUT = 14U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO14_SELECT_INPUT = 15U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_D_IP_FLEXIO_SYN1_IPP_IND_FLEXIO15_SELECT_INPUT = 16U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPUART4_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 17U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT = 18U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT = 19U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPUART5_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 20U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPUART5_IPP_IND_LPUART_RXD_SELECT_INPUT = 21U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPUART5_IPP_IND_LPUART_TXD_SELECT_INPUT = 22U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPUART6_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 23U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPUART6_IPP_IND_LPUART_RXD_SELECT_INPUT = 24U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPUART6_IPP_IND_LPUART_TXD_SELECT_INPUT = 25U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPUART7_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 26U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPUART7_IPP_IND_LPUART_RXD_SELECT_INPUT = 27U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPUART7_IPP_IND_LPUART_TXD_SELECT_INPUT = 28U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPI2C4_IPP_IND_LPI2C_HREQ_SELECT_INPUT = 29U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPI2C4_IPP_IND_LPI2C_SCL_SELECT_INPUT = 30U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPI2C4_IPP_IND_LPI2C_SDA_SELECT_INPUT = 31U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM4_IPP_IND_LPTPM_CH0_SELECT_INPUT = 32U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM4_IPP_IND_LPTPM_CH1_SELECT_INPUT = 33U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM4_IPP_IND_LPTPM_CH2_SELECT_INPUT = 34U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM4_IPP_IND_LPTPM_CH3_SELECT_INPUT = 35U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM4_IPP_IND_LPTPM_CH4_SELECT_INPUT = 36U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM4_IPP_IND_LPTPM_CH5_SELECT_INPUT = 37U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM4_IPP_IND_LPTPM_CLK_SELECT_INPUT = 38U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPSPI2_IPP_IND_LPSPI_PCS0_SELECT_INPUT = 39U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPSPI2_IPP_IND_LPSPI_PCS1_SELECT_INPUT = 40U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPSPI2_IPP_IND_LPSPI_PCS2_SELECT_INPUT = 41U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPSPI2_IPP_IND_LPSPI_PCS3_SELECT_INPUT = 42U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPSPI2_IPP_IND_LPSPI_SCK_SELECT_INPUT = 43U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPSPI2_IPP_IND_LPSPI_SDI_SELECT_INPUT = 44U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPSPI2_IPP_IND_LPSPI_SDO_SELECT_INPUT = 45U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPI2C5_IPP_IND_LPI2C_HREQ_SELECT_INPUT = 46U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT = 47U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT = 48U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM5_IPP_IND_LPTPM_CH0_SELECT_INPUT = 49U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM5_IPP_IND_LPTPM_CH1_SELECT_INPUT = 50U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM5_IPP_IND_LPTPM_CLK_SELECT_INPUT = 51U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM6_IPP_IND_LPTPM_CH0_SELECT_INPUT = 52U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM6_IPP_IND_LPTPM_CH1_SELECT_INPUT = 53U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM6_IPP_IND_LPTPM_CLK_SELECT_INPUT = 54U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM7_IPP_IND_LPTPM_CH0_SELECT_INPUT = 55U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM7_IPP_IND_LPTPM_CH1_SELECT_INPUT = 56U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM7_IPP_IND_LPTPM_CH2_SELECT_INPUT = 57U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM7_IPP_IND_LPTPM_CH3_SELECT_INPUT = 58U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM7_IPP_IND_LPTPM_CH4_SELECT_INPUT = 59U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM7_IPP_IND_LPTPM_CH5_SELECT_INPUT = 60U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPTPM7_IPP_IND_LPTPM_CLK_SELECT_INPUT = 61U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPI2C6_IPP_IND_LPI2C_HREQ_SELECT_INPUT = 62U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT = 63U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT = 64U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPI2C7_IPP_IND_LPI2C_HREQ_SELECT_INPUT = 65U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT = 66U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT = 67U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPSPI3_IPP_IND_LPSPI_PCS0_SELECT_INPUT = 68U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPSPI3_IPP_IND_LPSPI_PCS1_SELECT_INPUT = 69U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPSPI3_IPP_IND_LPSPI_PCS2_SELECT_INPUT = 70U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPSPI3_IPP_IND_LPSPI_PCS3_SELECT_INPUT = 71U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPSPI3_IPP_IND_LPSPI_SCK_SELECT_INPUT = 72U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPSPI3_IPP_IND_LPSPI_SDI_SELECT_INPUT = 73U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_LPSPI3_IPP_IND_LPSPI_SDO_SELECT_INPUT = 74U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_USDHC1_IPP_CARD_DET_SELECT_INPUT = 75U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_USBO2_ULP1_IPP_IND_OTG_OC_SELECT_INPUT = 76U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_USBO2_ULP1_IPP_IND_OTG2_OC_SELECT_INPUT = 77U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_DA_IP_HS_USB2PHY_28FDSOI_USB_ID_SELECT_INPUT = 78U, /**< IOMUXC select input index */ kIOMUXC1_IOMUXC1_VIDEO_IN_IPP_IND_DE_SELECT_INPUT = 79U, /**< IOMUXC select input index */ } iomuxc1_select_input_t; /* @} */ /*! * @addtogroup edma0_request * @{ */ /******************************************************************************* * Definitions *******************************************************************************/ /*! * @brief Enumeration for the DMA0 hardware request * * Defines the enumeration for the DMA0 hardware request collections. */ typedef enum _dma0_request_source { kDmaRequestMux0Disable = 0|0x100U, /**< Channel disabled */ kDmaRequestMux0QSPIRx = 1|0x100U, /**< QSPI Receive */ kDmaRequestMux0QSPITx = 2|0x100U, /**< QSPI Transmit */ kDmaRequestMux0LTCRx = 3|0x100U, /**< Low Power Trusted Cryptography RX */ kDmaRequestMux0LTCTx = 4|0x100U, /**< Low Power Trusted Cryptography TX */ kDmaRequestMux0LPTMR0 = 5|0x100U, /**< Low Power Timer */ kDmaRequestMux0LPTMR1 = 6|0x100U, /**< Low Power Timer */ kDmaRequestMux0TPM0Channel0 = 7|0x100U, /**< TPM0 Channel 0 */ kDmaRequestMux0TPM0Channel1 = 8|0x100U, /**< TPM0 Channel 1 */ kDmaRequestMux0TPM0Channel2 = 9|0x100U, /**< TPM0 Channel 2 */ kDmaRequestMux0TPM0Channel3 = 10|0x100U, /**< TPM0 Channel 3 */ kDmaRequestMux0TPM0Channel4 = 11|0x100U, /**< TPM0 Channel 4 */ kDmaRequestMux0TPM0Channel5 = 12|0x100U, /**< TPM0 Channel 5 */ kDmaRequestMux0TPM0Overflow = 13|0x100U, /**< TPM0 Overflow */ kDmaRequestMux0TPM1Channel0 = 14|0x100U, /**< TPM1 Channel 0 */ kDmaRequestMux0TPM1Channel1 = 15|0x100U, /**< TPM1 Channel 1 */ kDmaRequestMux0TPM1Overflow = 16|0x100U, /**< TPM1 Overflow */ kDmaRequestMux0TPM2Channel0 = 17|0x100U, /**< TPM2 Channel 0 */ kDmaRequestMux0TPM2Channel1 = 18|0x100U, /**< TPM2 Channel 1 */ kDmaRequestMux0TPM2Overflow = 19|0x100U, /**< TPM2 Overflow */ kDmaRequestMux0TPM3Channel0 = 20|0x100U, /**< TPM3 Channel 0 */ kDmaRequestMux0TPM3Channel1 = 21|0x100U, /**< TPM3 Channel 1 */ kDmaRequestMux0TPM3Channel2 = 22|0x100U, /**< TPM3 Channel 2 */ kDmaRequestMux0TPM3Channel3 = 23|0x100U, /**< TPM3 Channel 3 */ kDmaRequestMux0TPM3Channel4 = 24|0x100U, /**< TPM3 Channel 4 */ kDmaRequestMux0TPM3Channel5 = 25|0x100U, /**< TPM3 Channel 5 */ kDmaRequestMux0TPM3Overflow = 26|0x100U, /**< TPM3 Overflow */ kDmaRequestMux0FlexIO0Shifter0 = 27|0x100U, /**< FlexIO0 Shifter 0 */ kDmaRequestMux0FlexIO0Shifter1 = 28|0x100U, /**< FlexIO0 Shifter 1 */ kDmaRequestMux0FlexIO0Shifter2 = 29|0x100U, /**< FlexIO0 Shifter 2 */ kDmaRequestMux0FlexIO0Shifter3 = 30|0x100U, /**< FlexIO0 Shifter 3 */ kDmaRequestMux0FlexIO0Shifter4 = 31|0x100U, /**< FlexIO0 Shifter 4 */ kDmaRequestMux0FlexIO0Shifter5 = 32|0x100U, /**< FlexIO0 Shifter 5 */ kDmaRequestMux0FlexIO0Shifter6 = 33|0x100U, /**< FlexIO0 Shifter 6 */ kDmaRequestMux0FlexIO0Shifter7 = 34|0x100U, /**< FlexIO0 Shifter 7 */ kDmaRequestMux0LPI2C0Rx = 35|0x100U, /**< LPI2C0 Master/Slave Receive */ kDmaRequestMux0LPI2C0Tx = 36|0x100U, /**< LPI2C0 Master/Slave Transmit */ kDmaRequestMux0LPI2C1Rx = 37|0x100U, /**< LPI2C1 Master/Slave Receive */ kDmaRequestMux0LPI2C1Tx = 38|0x100U, /**< LPI2C1 Master/Slave Transmit */ kDmaRequestMux0LPI2C2Rx = 39|0x100U, /**< LPI2C2 Master/Slave Receive */ kDmaRequestMux0LPI2C2Tx = 40|0x100U, /**< LPI2C2 Master/Slave Transmit */ kDmaRequestMux0LPI2C3Rx = 41|0x100U, /**< LPI2C3 Master/Slave Receive */ kDmaRequestMux0LPI2C3Tx = 42|0x100U, /**< LPI2C3 Master/Slave Transmit */ kDmaRequestMux0SAI0Rx = 43|0x100U, /**< SAI0 Receive */ kDmaRequestMux0SAI0Tx = 44|0x100U, /**< SAI0 Transmit */ kDmaRequestMux0SAI1Rx = 45|0x100U, /**< SAI1 Receive */ kDmaRequestMux0SAI1Tx = 46|0x100U, /**< SAI1 Transmit */ kDmaRequestMux0LPSPI0Rx = 47|0x100U, /**< LPSPI0 Receive */ kDmaRequestMux0LPSPI0Tx = 48|0x100U, /**< LPSPI0 Transmit */ kDmaRequestMux0LPSPI1Rx = 49|0x100U, /**< LPSPI1 Receive */ kDmaRequestMux0LPSPI1Tx = 50|0x100U, /**< LPSPI1 Transmit */ kDmaRequestMux0LPUART0Rx = 51|0x100U, /**< LPUART0 Receive */ kDmaRequestMux0LPUART0Tx = 52|0x100U, /**< LPUART0 Transmit */ kDmaRequestMux0LPUART1Rx = 53|0x100U, /**< LPUART1 Receive */ kDmaRequestMux0LPUART1Tx = 54|0x100U, /**< LPUART1 Transmit */ kDmaRequestMux0LPUART2Rx = 55|0x100U, /**< LPUART2 Receive */ kDmaRequestMux0LPUART2Tx = 56|0x100U, /**< LPUART2 Transmit */ kDmaRequestMux0LPUART3Rx = 57|0x100U, /**< LPUART3 Receive */ kDmaRequestMux0LPUART3Tx = 58|0x100U, /**< LPUART3 Transmit */ kDmaRequestMux0PCTLA = 60|0x100U, /**< Port A pin request */ kDmaRequestMux0PCTLB = 61|0x100U, /**< Port B pin request */ kDmaRequestMux0ADC0 = 62|0x100U, /**< ADC0 Conversion Complete */ kDmaRequestMux0ADC1 = 63|0x100U, /**< ADC1 Conversion Complete */ kDmaRequestMux0CMP0 = 64|0x100U, /**< CMP0 Comparison Event */ kDmaRequestMux0CMP1 = 65|0x100U, /**< CMP1 Comparison Event */ kDmaRequestMux0DAC0 = 66|0x100U, /**< DAC0 Request */ kDmaRequestMux0DAC1 = 67|0x100U, /**< DAC1 Request */ } dma0_request_source_t; /* @} */ /*! * @addtogroup edma1_request * @{ */ /******************************************************************************* * Definitions *******************************************************************************/ /*! * @brief Enumeration for the DMA1 hardware request * * Defines the enumeration for the DMA1 hardware request collections. */ typedef enum _dma1_request_source { kDmaRequestMux1Disable = 0|0x200U, /**< Channel disabled */ kDmaRequestMux1FlexIO1Shifter0 = 1|0x200U, /**< FlexIO1 Shifter 0 */ kDmaRequestMux1FlexIO1Shifter1 = 2|0x200U, /**< FlexIO1 Shifter 1 */ kDmaRequestMux1FlexIO1Shifter2 = 3|0x200U, /**< FlexIO1 Shifter 2 */ kDmaRequestMux1FlexIO1Shifter3 = 4|0x200U, /**< FlexIO1 Shifter 3 */ kDmaRequestMux1FlexIO1Shifter4 = 5|0x200U, /**< FlexIO1 Shifter 4 */ kDmaRequestMux1FlexIO1Shifter5 = 6|0x200U, /**< FlexIO1 Shifter 5 */ kDmaRequestMux1FlexIO1Shifter6 = 7|0x200U, /**< FlexIO1 Shifter 6 */ kDmaRequestMux1FlexIO1Shifter7 = 8|0x200U, /**< FlexIO1 Shifter 7 */ kDmaRequestMux1LPI2C4Rx = 9|0x200U, /**< LPI2C4 Master/Slave Receive */ kDmaRequestMux1LPI2C4Tx = 10|0x200U, /**< LPI2C4 Master/Slave Transmit */ kDmaRequestMux1LPI2C5Rx = 11|0x200U, /**< LPI2C5 Master/Slave Receive */ kDmaRequestMux1LPI2C5Tx = 12|0x200U, /**< LPI2C5 Master/Slave Transmit */ kDmaRequestMux1LPI2C6Rx = 13|0x200U, /**< LPI2C6 Master/Slave Receive */ kDmaRequestMux1LPI2C6Tx = 14|0x200U, /**< LPI2C6 Master/Slave Transmit */ kDmaRequestMux1LPI2C7Rx = 15|0x200U, /**< LPI2C7 Master/Slave Receive */ kDmaRequestMux1LPI2C7Tx = 16|0x200U, /**< LPI2C7 Master/Slave Transmit */ kDmaRequestMux1LPUART4Rx = 17|0x200U, /**< LPUART4 Receive */ kDmaRequestMux1LPUART4Tx = 18|0x200U, /**< LPUART4 Transmit */ kDmaRequestMux1LPUART5Rx = 19|0x200U, /**< LPUART5 Receive */ kDmaRequestMux1LPUART5Tx = 20|0x200U, /**< LPUART5 Transmit */ kDmaRequestMux1LPUART6Rx = 21|0x200U, /**< LPUART6 Receive */ kDmaRequestMux1LPUART6Tx = 22|0x200U, /**< LPUART6 Transmit */ kDmaRequestMux1LPUART7Rx = 23|0x200U, /**< LPUART7 Receive */ kDmaRequestMux1LPUART7Tx = 24|0x200U, /**< LPUART7 Transmit */ kDmaRequestMux1LPSPI2Rx = 25|0x200U, /**< LPSPI2 Receive */ kDmaRequestMux1LPSPI2Tx = 26|0x200U, /**< LPSPI2 Transmit */ kDmaRequestMux1LPSPI3Rx = 27|0x200U, /**< LPSPI3 Receive */ kDmaRequestMux1LPSPI3Tx = 28|0x200U, /**< LPSPI3 Transmit */ kDmaRequestMux1TPM4Channel0 = 29|0x200U, /**< TPM4 Channel 0 */ kDmaRequestMux1TPM4Channel1 = 30|0x200U, /**< TPM4 Channel 1 */ kDmaRequestMux1TPM4Channel2 = 31|0x200U, /**< TPM4 Channel 2 */ kDmaRequestMux1TPM4Channel3 = 32|0x200U, /**< TPM4 Channel 3 */ kDmaRequestMux1TPM4Channel4 = 33|0x200U, /**< TPM4 Channel 4 */ kDmaRequestMux1TPM4Channel5 = 34|0x200U, /**< TPM4 Channel 5 */ kDmaRequestMux1TPM4Overflow = 35|0x200U, /**< TPM4 Overflow */ kDmaRequestMux1TPM5Channel0 = 36|0x200U, /**< TPM5 Channel 0 */ kDmaRequestMux1TPM5Channel1 = 37|0x200U, /**< TPM5 Channel 1 */ kDmaRequestMux1TPM5Overflow = 38|0x200U, /**< TPM5 Overflow */ kDmaRequestMux1TPM6Channel3 = 39|0x200U, /**< TPM6 Channel 3 */ kDmaRequestMux1TPM6Channel4 = 40|0x200U, /**< TPM6 Channel 4 */ kDmaRequestMux1TPM6Overflow = 41|0x200U, /**< TPM6 Overflow */ kDmaRequestMux1TPM7Channel0 = 42|0x200U, /**< TPM7 Channel 0 */ kDmaRequestMux1TPM7Channel1 = 43|0x200U, /**< TPM7 Channel 1 */ kDmaRequestMux1TPM7Channel2 = 44|0x200U, /**< TPM7 Channel 2 */ kDmaRequestMux1TPM7Channel3 = 45|0x200U, /**< TPM7 Channel 3 */ kDmaRequestMux1TPM7Channel4 = 46|0x200U, /**< TPM7 Channel 4 */ kDmaRequestMux1TPM7Channel5 = 47|0x200U, /**< TPM7 Channel 5 */ kDmaRequestMux1TPM7Overflow = 48|0x200U, /**< TPM7 Overflow */ kDmaRequestMux1PCTLC = 51|0x200U, /**< Port Interrupt Control module C */ kDmaRequestMux1PCTLD = 52|0x200U, /**< Port Interrupt Control module D */ kDmaRequestMux1PCTLE = 53|0x200U, /**< Port Interrupt Control module E */ kDmaRequestMux1PCTLF = 54|0x200U, /**< Port Interrupt Control module F */ kDmaRequestMux1QSPIRx = 57|0x200U, /**< QSPI Receive */ kDmaRequestMux1QSPITx = 58|0x200U, /**< QSPI Transmit */ kDmaRequestMux1SAI0Rx = 59|0x200U, /**< SAI0 Receive */ kDmaRequestMux1SAI0Tx = 60|0x200U, /**< SAI0 Transmit */ kDmaRequestMux1SAI1Rx = 61|0x200U, /**< SAI1 Receive */ kDmaRequestMux1SAI1Tx = 62|0x200U, /**< SAI1 Transmit */ kDmaRequestMux1PCTLA = 63|0x200U, /**< Port Interrupt Control module A */ kDmaRequestMux1PCTLB = 64|0x200U, /**< Port Interrupt Control module B */ } dma1_request_source_t; /* @} */ /*! * @addtogroup trgmux0_source * @{ */ /******************************************************************************* * Definitions *******************************************************************************/ /*! * @brief Enumeration for the TRGMUX0 source * * Defines the enumeration for the TRGMUX0 source collections. */ typedef enum _trgmux0_source { kTRGMUX0_SourceDisabled = 0U, /**< Trigger function is disabled */ kTRGMUX0_SourceFlexIO0Timer0 = 2U, /**< FlexIO0 Timer0 input is selected */ kTRGMUX0_SourceFlexIO0Timer1 = 3U, /**< FlexIO0 Timer1 input is selected */ kTRGMUX0_SourceFlexIO0Timer2 = 4U, /**< FlexIO0 Timer2 input is selected */ kTRGMUX0_SourceFlexIO0Timer3 = 5U, /**< FlexIO0 Timer3 input is selected */ kTRGMUX0_SourceFlexIO0Timer4 = 6U, /**< FlexIO0 Timer4 input is selected */ kTRGMUX0_SourceFlexIO0Timer5 = 7U, /**< FlexIO0 Timer5 input is selected */ kTRGMUX0_SourceFlexIO0Timer6 = 8U, /**< FlexIO0 Timer6 input is selected */ kTRGMUX0_SourceFlexIO0Timer7 = 9U, /**< FlexIO0 Timer7 input is selected */ kTRGMUX0_SourceTPM0Overflow = 10U, /**< TPM0 Overflow input is selected */ kTRGMUX0_SourceTPM0Channel0 = 11U, /**< TPM0 Channel0 input is selected */ kTRGMUX0_SourceTPM0Channel1 = 12U, /**< TPM0 Channel1 input is selected */ kTRGMUX0_SourceTPM1Overflow = 13U, /**< TPM1 Overflow input is selected */ kTRGMUX0_SourceTPM1Channel0 = 14U, /**< TPM1 Channel0 input is selected */ kTRGMUX0_SourceTPM1Channel1 = 15U, /**< TPM1 Channel1 input is selected */ kTRGMUX0_SourceTPM2Overflow = 16U, /**< TPM2 Overflow input is selected */ kTRGMUX0_SourceTPM2Channel0 = 17U, /**< TPM2 Channel0 input is selected */ kTRGMUX0_SourceTPM2Channel1 = 18U, /**< TPM2 Channel1 input is selected */ kTRGMUX0_SourceTPM3Overflow = 19U, /**< TPM3 Overflow input is selected */ kTRGMUX0_SourceTPM3Channel0 = 20U, /**< TPM3 Channel0 input is selected */ kTRGMUX0_SourceTPM3Channel1 = 21U, /**< TPM3 Channel1 input is selected */ kTRGMUX0_SourceLPIT0Channel0 = 22U, /**< LPIT0 Channel0 input is selected */ kTRGMUX0_SourceLPIT0Channel1 = 23U, /**< LPIT0 Channel1 input is selected */ kTRGMUX0_SourceLPIT0Channel2 = 24U, /**< LPIT0 Channel2 input is selected */ kTRGMUX0_SourceLPIT0Channel3 = 25U, /**< LPIT0 Channel3 input is selected */ kTRGMUX0_SourceLPUART0RxData = 30U, /**< LPUART0 RX Data input is selected */ kTRGMUX0_SourceLPUART0TxData = 31U, /**< LPUART0 TX Data input is selected */ kTRGMUX0_SourceLPUART0RxIdle = 32U, /**< LPUART0 RX Idle input is selected */ kTRGMUX0_SourceLPUART1RxData = 33U, /**< LPUART1 RX Data input is selected */ kTRGMUX0_SourceLPUART1TxData = 34U, /**< LPUART1 TX Data input is selected */ kTRGMUX0_SourceLPUART1RxIdle = 35U, /**< LPUART1 RX Idle input is selected */ kTRGMUX0_SourceLPUART2RxData = 36U, /**< LPUART2 RX Data input is selected */ kTRGMUX0_SourceLPUART2TxData = 37U, /**< LPUART2 TX Data input is selected */ kTRGMUX0_SourceLPUART2RxIdle = 38U, /**< LPUART2 RX Idle input is selected */ kTRGMUX0_SourceLPUART3RxData = 39U, /**< LPUART3 RX Data input is selected */ kTRGMUX0_SourceLPUART3TxData = 40U, /**< LPUART3 TX Data input is selected */ kTRGMUX0_SourceLPUART3RxIdle = 41U, /**< LPUART3 RX Idle input is selected */ kTRGMUX0_SourceLPI2C0MasterStop = 42U, /**< LPI2C0 Master Stop input is selected */ kTRGMUX0_SourceLPI2C0SlaveStop = 43U, /**< LPI2C0 Slave Stop input is selected */ kTRGMUX0_SourceLPI2C1MasterStop = 44U, /**< LPI2C1 Master Stop input is selected */ kTRGMUX0_SourceLPI2C1SlaveStop = 45U, /**< LPI2C1 Slave Stop input is selected */ kTRGMUX0_SourceLPI2C2MasterStop = 46U, /**< LPI2C2 Master Stop input is selected */ kTRGMUX0_SourceLPI2C2SlaveStop = 47U, /**< LPI2C2 Slave Stop input is selected */ kTRGMUX0_SourceLPI2C3MasterStop = 48U, /**< LPI2C3 Master Stop input is selected */ kTRGMUX0_SourceLPI2C3SlaveStop = 49U, /**< LPI2C3 Slave Stop input is selected */ kTRGMUX0_SourceLPSPI0Frame = 50U, /**< LPSPI0 Frame input is selected */ kTRGMUX0_SourceLPSPI0RxData = 51U, /**< LPSPI0 RX Data input is selected */ kTRGMUX0_SourceLPSPI1Frame = 52U, /**< LPSPI1 Frame input is selected */ kTRGMUX0_SourceLPSPI1RxData = 53U, /**< LPSPI1 RX Data input is selected */ kTRGMUX0_SourceLPTMR0 = 56U, /**< LPTMR0 input is selected */ kTRGMUX0_SourceLPTMR1 = 57U, /**< LPTMR1 input is selected */ kTRGMUX0_SourceCMP0Output = 58U, /**< CMP0 Output input is selected */ kTRGMUX0_SourceCMP1Output = 59U, /**< CMP1 Output input is selected */ kTRGMUX0_SourcePORTAPin = 64U, /**< PORT A Pin input is selected */ kTRGMUX0_SourcePORTBPin = 65U, /**< PORT B Pin input is selected */ kTRGMUX0_SourceI2S0TxFrameSync = 66U, /**< I2S0 TX Frame Sync input is selected */ kTRGMUX0_SourceI2S0RxFrameSync = 67U, /**< I2S0 RX Frame Sync input is selected */ kTRGMUX0_SourceI2S1TxFrameSync = 68U, /**< I2S1 TX Frame Sync input is selected */ kTRGMUX0_SourceI2S1RxFrameSync = 69U, /**< I2S1 RX Frame Sync input is selected */ } trgmux0_source_t; /* @} */ /*! * @addtogroup trgmux1_source * @{ */ /******************************************************************************* * Definitions *******************************************************************************/ /*! * @brief Enumeration for the TRGMUX1 source * * Defines the enumeration for the TRGMUX1 source collections. */ typedef enum _trgmux1_source { kTRGMUX1_SourceDisabled = 0U, /**< Trigger function is disabled */ kTRGMUX1_SourceFlexIO1Timer0 = 1U, /**< FlexIO1 Timer0 input is selected */ kTRGMUX1_SourceFlexIO1Timer1 = 2U, /**< FlexIO1 Timer1 input is selected */ kTRGMUX1_SourceFlexIO1Timer2 = 3U, /**< FlexIO1 Timer2 input is selected */ kTRGMUX1_SourceFlexIO1Timer3 = 4U, /**< FlexIO1 Timer3 input is selected */ kTRGMUX1_SourceFlexIO1Timer4 = 5U, /**< FlexIO1 Timer4 input is selected */ kTRGMUX1_SourceFlexIO1Timer5 = 6U, /**< FlexIO1 Timer5 input is selected */ kTRGMUX1_SourceFlexIO1Timer6 = 7U, /**< FlexIO1 Timer6 input is selected */ kTRGMUX1_SourceFlexIO1Timer7 = 8U, /**< FlexIO1 Timer7 input is selected */ kTRGMUX1_SourceTPM4Overflow = 9U, /**< TPM4 Overflow input is selected */ kTRGMUX1_SourceTPM4Channel0 = 10U, /**< TPM4 Channel0 input is selected */ kTRGMUX1_SourceTPM4Channel1 = 11U, /**< TPM4 Channel1 input is selected */ kTRGMUX1_SourceTPM5Overflow = 12U, /**< TPM5 Overflow input is selected */ kTRGMUX1_SourceTPM5Channel0 = 13U, /**< TPM5 Channel0 input is selected */ kTRGMUX1_SourceTPM5Channel1 = 14U, /**< TPM5 Channel1 input is selected */ kTRGMUX1_SourceTPM6Overflow = 15U, /**< TPM6 Overflow input is selected */ kTRGMUX1_SourceTPM6Channel0 = 16U, /**< TPM6 Channel0 input is selected */ kTRGMUX1_SourceTPM6Channel1 = 17U, /**< TPM6 Channel1 input is selected */ kTRGMUX1_SourceTPM7Overflow = 18U, /**< TPM7 Overflow input is selected */ kTRGMUX1_SourceTPM7Channel0 = 19U, /**< TPM7 Channel0 input is selected */ kTRGMUX1_SourceTPM7Channel1 = 20U, /**< TPM7 Channel1 input is selected */ kTRGMUX1_SourceLPUART4RxData = 21U, /**< LPUART4 RX data input is selected */ kTRGMUX1_SourceLPUART4TxData = 22U, /**< LPUART4 TX data input is selected */ kTRGMUX1_SourceLPUART4RxIdle = 23U, /**< LPUART4 RX idle input is selected */ kTRGMUX1_SourceLPUART5RxData = 24U, /**< LPUART5 RX data input is selected */ kTRGMUX1_SourceLPUART5TxData = 25U, /**< LPUART5 TX data input is selected */ kTRGMUX1_SourceLPUART5RXIdle = 26U, /**< LPUART5 RX Idle input is selected */ kTRGMUX1_SourceLPUART6RxData = 27U, /**< LPUART6 RX data input is selected */ kTRGMUX1_SourceLPUART6TxData = 28U, /**< LPUART6 TX data input is selected */ kTRGMUX1_SourceLPUART6RxIdle = 29U, /**< LPUART6 RX idle input is selected */ kTRGMUX1_SourceLPUART7RxData = 30U, /**< LPUART7 RX data input is selected */ kTRGMUX1_SourceLPUART7TxData = 31U, /**< LPUART7 TX data input is selected */ kTRGMUX1_SourceLPUART7RxIdle = 32U, /**< LPUART7 RX idle input is selected */ kTRGMUX1_SourceLPI2C4MasterSTOP = 33U, /**< LPI2C4 Master STOP input is selected */ kTRGMUX1_SourceLPI2C4SlaveSTOP = 34U, /**< LPI2C4 Slave STOP input is selected */ kTRGMUX1_SourceLPI2C5MasterSTOP = 35U, /**< LPI2C5 Master STOP input is selected */ kTRGMUX1_SourceLPI2C5SlaveSTOP = 36U, /**< LPI2C5 Slave STOP input is selected */ kTRGMUX1_SourceLPI2C6MasterSTOP = 37U, /**< LPI2C6 Master STOP input is selected */ kTRGMUX1_SourceLPI2C6SlaveSTOP = 38U, /**< LPI2C6 Slave STOP input is selected */ kTRGMUX1_SourceLPI2C7MasterSTOP = 39U, /**< LPI2C7 Master STOP input is selected */ kTRGMUX1_SourceLPI2C7SlaveSTOP = 40U, /**< LPI2C7 Slave STOP input is selected */ kTRGMUX1_SourceLPSPI2Frame = 41U, /**< LPSPI2 Frame input is selected */ kTRGMUX1_SourceLPSPI2RxData = 42U, /**< LPSPI2 RX data input is selected */ kTRGMUX1_SourceLPSPI3Frame = 43U, /**< LPSPI3 Frame input is selected */ kTRGMUX1_SourceLPSPI3RxData = 44U, /**< LPSPI3 RX data input is selected */ kTRGMUX1_SourcePORTCPin = 45U, /**< PORT C Pin input is selected */ kTRGMUX1_SourcePORTDPin = 46U, /**< PORT D Pin input is selected */ kTRGMUX1_SourcePORTEPin = 47U, /**< PORT E Pin input is selected */ kTRGMUX1_SourcePORTFPin = 48U, /**< PORT F Pin input is selected */ kTRGMUX1_SourceUSB0StartOfFrame = 49U, /**< USB0 Start of Frame input is selected */ kTRGMUX1_SourceUSB1StartOfFrame = 50U, /**< USB1 Start of Frame input is selected */ kTRGMUX1_SourceLPIT1Channel0 = 51U, /**< LPIT1 Channel 0 input is selected */ kTRGMUX1_SourceLPIT1Channel1 = 52U, /**< LPIT1 Channel 1 input is selected */ kTRGMUX1_SourceLPIT1Channel2 = 53U, /**< LPIT1 Channel 2 input is selected */ kTRGMUX1_SourceLPIT1Channel3 = 54U, /**< LPIT1 Channel 3 input is selected */ } trgmux1_source_t; /* @} */ /*! * @brief Enumeration for the TRGMUX0 device * * Defines the enumeration for the TRGMUX0 device collections. */ typedef enum _trgmux0_device { kTRGMUX0_DMAMUX0_CH0_3 = 0U, /**< DMAMUX0 channel 0-3 trigger */ kTRGMUX0_DMAMUX0_CH4_7 = 1U, /**< DMAMUX0 channel 4-7 trigger */ kTRGMUX0_LPIT0 = 2U, /**< LPIT0 trigger 0-3 */ kTRGMUX0_TPM0 = 4U, /**< TPM0 channel 0-1 trigger */ kTRGMUX0_TPM1 = 5U, /**< TPM1 channel 0-1 trigger */ kTRGMUX0_TPM2 = 6U, /**< TPM2 channel 0-1 trigger */ kTRGMUX0_TPM3 = 7U, /**< TPM3 channel 0-1 trigger */ kTRGMUX0_ADC0 = 8U, /**< ADC0 Trigger A, B */ kTRGMUX0_ADC1 = 9U, /**< ADC1 Trigger A, B */ kTRGMUX0_CMP0 = 10U, /**< CMP0 Window trigger */ kTRGMUX0_CMP1 = 11U, /**< CMP1 Window trigger */ kTRGMUX0_DAC0 = 12U, /**< DAC0 Trigger */ kTRGMUX0_DAC1 = 13U, /**< DAC1 Trigger */ kTRGMUX0_LPUART0 = 14U, /**< LPUART0 input */ kTRGMUX0_LPUART1 = 15U, /**< LPUART1 input */ kTRGMUX0_LPUART2 = 16U, /**< LPUART2 input */ kTRGMUX0_LPUART3 = 17U, /**< LPUART3 input */ kTRGMUX0_LPI2C0 = 18U, /**< LPI2C0 Host request */ kTRGMUX0_LPI2C1 = 19U, /**< LPI2C1 Host request */ kTRGMUX0_LPI2C2 = 20U, /**< LPI2C2 Host request */ kTRGMUX0_LPI2C3 = 21U, /**< LPI2C3 Host request */ kTRGMUX0_LPSPI0 = 22U, /**< LPSPI0 Host request */ kTRGMUX0_LPSPI1 = 23U, /**< LPSPI1 Host request */ kTRGMUX0_FLEXIO0 = 24U, /**< FlexIO0 trigger 0-3 */ } trgmux0_device_t; /*! * @brief Enumeration for the TRGMUX1 device * * Defines the enumeration for the TRGMUX1 device collections. */ typedef enum _trgmux1_device { kTRGMUX1_DMAMUX1_CH0_3 = 0U, /**< DMAMUX1 channel 0-3 trigger */ kTRGMUX1_DMAMUX1_CH4_7 = 1U, /**< DMAMUX1 channel 4-7 trigger */ kTRGMUX1_TPM4 = 2U, /**< TPM4 channel 0-1 trigger */ kTRGMUX1_TPM5 = 3U, /**< TPM5 channel 0-1 trigger */ kTRGMUX1_TPM6 = 4U, /**< TPM6 channel 0-1 trigger */ kTRGMUX1_TPM7 = 5U, /**< TPM7 channel 0-1 trigger */ kTRGMUX1_LPUART4 = 6U, /**< LPUART4 input */ kTRGMUX1_LPUART5 = 7U, /**< LPUART5 input */ kTRGMUX1_LPUART6 = 8U, /**< LPUART6 input */ kTRGMUX1_LPUART7 = 9U, /**< LPUART7 input */ kTRGMUX1_LPI2C4 = 10U, /**< LPI2C4 Host request */ kTRGMUX1_LPI2C5 = 11U, /**< LPI2C5 Host request */ kTRGMUX1_LPI2C6 = 12U, /**< LPI2C6 Host request */ kTRGMUX1_LPI2C7 = 13U, /**< LPI2C7 Host request */ kTRGMUX1_LPSPI2 = 14U, /**< LPSPI2 Host request */ kTRGMUX1_LPSPI3 = 15U, /**< LPSPI3 Host request */ kTRGMUX1_FLEXIO1 = 16U, /**< FlexIO1 trigger 0-3 */ kTRGMUX1_LPIT1 = 17U, /**< LPIT1 trigger 0-3 */ } trgmux1_device_t; /*! * @addtogroup xrdc_mapping * @{ */ /******************************************************************************* * Definitions ******************************************************************************/ /*! * @brief Structure for the XRDC mapping * * Defines the structure for the XRDC resource collections. */ typedef enum _xrdc_master { kXRDC_MasterCM4Code = 0U, /**< Cortex-M4 Code Bus Master */ kXRDC_MasterCM4System = 1U, /**< Cortex-M4 System Bus Master */ kXRDC_MasterDma0 = 2U, /**< DMA0 Bus Master */ kXRDC_MasterCA7 = 3U, /**< Cortex-A7 Bus Master */ kXRDC_MasterLcdif = 4U, /**< LCDIF Bus Master */ kXRDC_MasterGpu3D = 5U, /**< GPU 3D Bus Master */ kXRDC_MasterDma1 = 6U, /**< DMA1 Bus Master */ kXRDC_MasterAxbs2NIC1 = 7U, /**< AXBS2NIC1 Bus Master */ kXRDC_MasterCaam = 8U, /**< CAAM Bus Master */ kXRDC_MasterUsb_0_1 = 9U, /**< USB0/1 Bus Master */ kXRDC_MasterViu = 10U, /**< VIU Bus Master */ kXRDC_MasterSdhc0 = 11U, /**< SDHC0 Bus Master */ kXRDC_MasterSdhc1 = 12U, /**< SDHC1 Bus Master */ kXRDC_MasterGpu2D = 13U, /**< GPU 2D Bus Master */ } xrdc_master_t; /* @} */ typedef enum _xrdc_mem { kXRDC_MemMrc0_0 = 0U, /**< MRC0_0 Memory: Cortex-M4 TCMs */ kXRDC_MemMrc0_1 = 1U, /**< MRC0_1 Memory: Cortex-M4 TCMs */ kXRDC_MemMrc0_2 = 2U, /**< MRC0_2 Memory: Cortex-M4 TCMs */ kXRDC_MemMrc0_3 = 3U, /**< MRC0_3 Memory: Cortex-M4 TCMs */ kXRDC_MemMrc1_0 = 16U, /**< MRC1_0 Memory: QSPI Flash */ kXRDC_MemMrc1_1 = 17U, /**< MRC1_1 Memory: QSPI Flash */ kXRDC_MemMrc1_2 = 18U, /**< MRC1_2 Memory: QSPI Flash */ kXRDC_MemMrc1_3 = 19U, /**< MRC1_3 Memory: QSPI Flash */ kXRDC_MemMrc1_4 = 20U, /**< MRC1_4 Memory: QSPI Flash */ kXRDC_MemMrc1_5 = 21U, /**< MRC1_5 Memory: QSPI Flash */ kXRDC_MemMrc1_6 = 22U, /**< MRC1_6 Memory: QSPI Flash */ kXRDC_MemMrc1_7 = 23U, /**< MRC1_7 Memory: QSPI Flash */ kXRDC_MemMrc2_0 = 32U, /**< MRC2_0 Memory: SRAM0 */ kXRDC_MemMrc2_1 = 33U, /**< MRC2_1 Memory: SRAM0 */ kXRDC_MemMrc2_2 = 34U, /**< MRC2_2 Memory: SRAM0 */ kXRDC_MemMrc2_3 = 35U, /**< MRC2_3 Memory: SRAM0 */ kXRDC_MemMrc3_0 = 48U, /**< MRC3_0 Memory: SecRAM */ kXRDC_MemMrc3_1 = 49U, /**< MRC3_1 Memory: SecRAM */ kXRDC_MemMrc3_2 = 50U, /**< MRC3_2 Memory: SecRAM */ kXRDC_MemMrc3_3 = 51U, /**< MRC3_3 Memory: SecRAM */ kXRDC_MemMrc4_0 = 64U, /**< MRC4_0 Memory: FlexBus */ kXRDC_MemMrc4_1 = 65U, /**< MRC4_1 Memory: FlexBus */ kXRDC_MemMrc4_2 = 66U, /**< MRC4_2 Memory: FlexBus */ kXRDC_MemMrc4_3 = 67U, /**< MRC4_3 Memory: FlexBus */ kXRDC_MemMrc5_0 = 80U, /**< MRC5_0 Memory: SRAM1 */ kXRDC_MemMrc5_1 = 81U, /**< MRC5_1 Memory: SRAM1 */ kXRDC_MemMrc5_2 = 82U, /**< MRC5_2 Memory: SRAM1 */ kXRDC_MemMrc5_3 = 83U, /**< MRC5_3 Memory: SRAM1 */ kXRDC_MemMrc6_0 = 96U, /**< MRC6_0 Memory: MMDC Flash */ kXRDC_MemMrc6_1 = 97U, /**< MRC6_1 Memory: MMDC Flash */ kXRDC_MemMrc6_2 = 98U, /**< MRC6_2 Memory: MMDC Flash */ kXRDC_MemMrc6_3 = 99U, /**< MRC6_3 Memory: MMDC Flash */ kXRDC_MemMrc6_4 = 100U, /**< MRC6_4 Memory: MMDC Flash */ kXRDC_MemMrc6_5 = 101U, /**< MRC6_5 Memory: MMDC Flash */ kXRDC_MemMrc6_6 = 102U, /**< MRC6_6 Memory: MMDC Flash */ kXRDC_MemMrc6_7 = 103U, /**< MRC6_7 Memory: MMDC Flash */ } xrdc_mem_t; typedef enum _xrdc_periph { kXRDC_PeriphEdma0 = 8U, /**< Direct Memory Access Controller 0 */ kXRDC_PeriphEdma0_tcd = 9U, /**< Direct Memory Access Controller 0 Transfer */ kXRDC_PeriphRgpio0 = 15U, /**< Rapid GPIO Controller 0 */ kXRDC_PeriphXrdc0 = 20U, /**< Extended Resource Domain Controller */ kXRDC_PeriphXrdc1 = 21U, /**< Extended Resource Domain Controller */ kXRDC_PeriphXrdc2 = 22U, /**< Extended Resource Domain Controller */ kXRDC_PeriphXrdc3 = 23U, /**< Extended Resource Domain Controller */ kXRDC_PeriphSema42_0 = 27U, /**< Hardware Semaphore Module 0 */ kXRDC_PeriphDmamux0 = 32U, /**< Direct Memory Access Multiplexer 0 */ kXRDC_PeriphLlwu = 33U, /**< Low-Leakage Wakeup Unit */ kXRDC_PeriphMu_A = 34U, /**< Messaging Unit - Side A */ kXRDC_PeriphTrgmux0 = 36U, /**< Trigger MUX Control 0 */ kXRDC_PeriphWdog0 = 37U, /**< Watchdog Timer 0 */ kXRDC_PeriphPcc0 = 38U, /**< Peripheral Clock Control 0 */ kXRDC_PeriphScg0 = 39U, /**< System Clock Generator 0 */ kXRDC_PeriphCrc = 41U, /**< Cyclic Redundancy Check */ kXRDC_PeriphLtc = 42U, /**< Low Power Trusted Cryptography */ kXRDC_PeriphTrng = 44U, /**< True Random Number Generator */ kXRDC_PeriphLpit0 = 45U, /**< Low Power Interrupt Timer */ kXRDC_PeriphLptmr0 = 46U, /**< Low Power Timer 0 */ kXRDC_PeriphLptmr1 = 47U, /**< Low power Timer 1 */ kXRDC_PeriphTpm0 = 48U, /**< Timer/PWM Module 0 */ kXRDC_PeriphTpm1 = 49U, /**< Timer/PWM Module 1 */ kXRDC_PeriphFlexio0 = 50U, /**< Flexible IO Controller 0 */ kXRDC_PeriphLpi2c0 = 51U, /**< Low Power Inter-Integrated Circuit 0 */ kXRDC_PeriphLpi2c1 = 52U, /**< Low Power Inter-Integrated Circuit 1 */ kXRDC_PeriphLpi2c2 = 53U, /**< Low Power Inter-Integrated Circuit 2 */ kXRDC_PeriphLpi2c3 = 54U, /**< Low Power Inter-Integrated Circuit 3 */ kXRDC_PeriphSai0 = 55U, /**< Synchronous Audio Interface 0 */ kXRDC_PeriphLpspi0 = 56U, /**< Low Power Serial Peripheral Interface 0 */ kXRDC_PeriphLpspi1 = 57U, /**< Low Power Serial Peripheral Interface 1 */ kXRDC_PeriphLpuart0 = 58U, /**< Low Power Universal Asynchronous Receiver/Transmitter 0 */ kXRDC_PeriphLpuart1 = 59U, /**< Low Power Universal Asynchronous Receiver/Transmitter 1 */ kXRDC_PeriphIomuxc0 = 61U, /**< Input/Output Multiplexing Controller 0 */ kXRDC_PeriphPctlA = 63U, /**< Port Interrupt Control A */ kXRDC_PeriphPctlB = 64U, /**< Port Interrupt Control B */ kXRDC_PeriphAdc0 = 65U, /**< Analog to Digital Converter 0 */ kXRDC_PeriphCmp0 = 66U, /**< Analog Comparator 0 */ kXRDC_PeriphCmp1 = 67U, /**< Analog Comparator 1 */ kXRDC_PeriphDac0 = 68U, /**< Digital to Analog Converter 0 */ kXRDC_PeriphDac1 = 69U, /**< Digital to Analog Converter 1 */ kXRDC_PeriphSnvs = 112U, /**< Secure Non-Volatile Storage */ kXRDC_PeriphRomc0 = 144U, /**< ROM Controller 0 */ kXRDC_PeriphDaprom = 145U, /**< Debug Access Port ROM */ kXRDC_PeriphFunnel = 146U, /**< Coresight Funnel */ kXRDC_PeriphEtf = 147U, /**< Embedded Trace FIFO */ kXRDC_PeriphTpiu = 148U, /**< Trace Port Interface Unit */ kXRDC_PeriphEtr = 149U, /**< Embedded Trace Router */ kXRDC_PeriphCti = 150U, /**< Cross Trigger Interface */ kXRDC_PeriphSwo = 151U, /**< Single Wire Output */ kXRDC_PeriphTimestampGen = 152U, /**< Timestamp Generator */ kXRDC_PeriphA7_apb_rom = 154U, /**< Cortex-A7 APB ROM */ kXRDC_PeriphA7_apb_cpu_dbg = 155U, /**< Cortex-A7 APB CPU Debug */ kXRDC_PeriphA7_apb_pmu = 156U, /**< Cortex-A7 APB Performance Monitoring Unit */ kXRDC_PeriphA7_apb_cti = 157U, /**< Cortex-A7 APB Cross Trigger Interface */ kXRDC_PeriphA7_apb_etm = 158U, /**< Cortex-A7 APB Embedded Trace Module */ kXRDC_PeriphEwm = 160U, /**< External Watchdog Monitor */ kXRDC_PeriphPmc0 = 161U, /**< Power Management Controller 0 */ kXRDC_PeriphSim = 163U, /**< System Integration Module */ kXRDC_PeriphCmc0 = 164U, /**< Core Mode Controller 0 */ kXRDC_PeriphQspi = 165U, /**< Quad Serial Peripheral Interface And Onthe-fly AES Decryptor */ kXRDC_PeriphOcotp_ctrl = 166U, /**< On-chip One Time Programmable Controller */ kXRDC_PeriphTpm2 = 168U, /**< Timer/PWM Module 2 */ kXRDC_PeriphTpm3 = 169U, /**< Timer/PWM Module 3 */ kXRDC_PeriphSai1 = 170U, /**< Synchronous Audio Interface 1 */ kXRDC_PeriphLpuart2 = 171U, /**< Low Power Universal Asynchronous Receiver/Transmitter 2 */ kXRDC_PeriphLpuart3 = 172U, /**< Low Power Universal Asynchronous Receiver/Transmitter 3 */ kXRDC_PeriphAdc1 = 173U, /**< Analog to Digital Converter 1 */ kXRDC_PeriphPcc1 = 178U, /**< Peripheral Clock Control 1 */ kXRDC_PeriphEdma1 = 264U, /**< Direct Memory Access Controller 1 */ kXRDC_PeriphEdma1_tcd = 265U, /**< Direct Memory Access Controller 1 Transfer */ kXRDC_PeriphRgpio1 = 271U, /**< Rapid GPIO Controller 1 */ kXRDC_PeriphFlexbus = 272U, /**< External Bus Interface */ kXRDC_PeriphSema42_1 = 283U, /**< Hardware Semaphore Module 1 */ kXRDC_PeriphDmamux1 = 289U, /**< Direct Memory Access Multiplexer 1 */ kXRDC_PeriphMu_B = 290U, /**< Messaging Unit - Side B */ kXRDC_PeriphCaam = 292U, /**< Cryptographic Acceleration and Assurance Module */ kXRDC_PeriphTpm4 = 293U, /**< Timer/PWM Module 4 */ kXRDC_PeriphTpm5 = 294U, /**< Timer/PWM Module 5 */ kXRDC_PeriphLpit1 = 295U, /**< Low Power Periodic Interrupt Timer 1 */ kXRDC_PeriphLpspi2 = 297U, /**< Low Power Serial Peripheral Interface 2 */ kXRDC_PeriphLpspi3 = 298U, /**< Low Power Serial Peripheral Interface 3 */ kXRDC_PeriphLpi2c4 = 299U, /**< Low Power Inter-Integrated Circuit 4 */ kXRDC_PeriphLpi2c5 = 300U, /**< Low Power Inter-Integrated Circuit 5 */ kXRDC_PeriphLpuart4 = 301U, /**< Low Power Universal Asynchronous Receiver/Transmitter 4 */ kXRDC_PeriphLpuart5 = 302U, /**< Low Power Universal Asynchronous Receiver/Transmitter 5 */ kXRDC_PeriphFlexio1 = 305U, /**< Flexible Input/Ouput 1 */ kXRDC_PeriphUsb0 = 307U, /**< High Speed On-The-Go USB 1 */ kXRDC_PeriphUsb1 = 308U, /**< High Speed On-The-Go USB 2 */ kXRDC_PeriphUsbPhy = 309U, /**< USB-PHY Control */ kXRDC_PeriphUsb_pl301 = 310U, /**< USB PL301 */ kXRDC_PeriphUsdhc0 = 311U, /**< ultra Secure Digital Host Controller 0 */ kXRDC_PeriphUsdhc1 = 312U, /**< ultra Secure Digital Host Controller 1 */ kXRDC_PeriphTrgmux1 = 314U, /**< Trigger Multiplexer 1 */ kXRDC_PeriphWdog1 = 317U, /**< Watchdog 1 */ kXRDC_PeriphScg1 = 318U, /**< System Clock Generator 1 */ kXRDC_PeriphPcc2 = 319U, /**< Peripheral Clock Control 2 */ kXRDC_PeriphPmc1 = 320U, /**< Power Management Control 1 */ kXRDC_PeriphCmc1 = 321U, /**< Core Mode Controller 1 */ kXRDC_PeriphWdog2 = 323U, /**< Watchdog2 */ kXRDC_PeriphRomc1 = 400U, /**< ROM Controller 1 */ kXRDC_PeriphTpm6 = 417U, /**< Timer/PWM Module 6 */ kXRDC_PeriphTpm7 = 418U, /**< Timer/PWM Module 7 */ kXRDC_PeriphLpi2c6 = 420U, /**< Low Power I2C 6 */ kXRDC_PeriphLpi2c7 = 421U, /**< Low Power I2C 7 */ kXRDC_PeriphLpuart6 = 422U, /**< Low Power UART 6 */ kXRDC_PeriphLpuart7 = 423U, /**< Low Power UART 7 */ kXRDC_PeriphViu = 424U, /**< Video-In Unit */ kXRDC_PeriphDsi = 425U, /**< MIPI Display Serial Interface */ kXRDC_PeriphLcdif = 426U, /**< LCD Interface */ kXRDC_PeriphMmdc = 427U, /**< Multi Mode DDR Controller */ kXRDC_PeriphIomuxc1 = 428U, /**< Input/Output Multiplexing Control 1 */ kXRDC_PeriphIomuxc_ddr = 429U, /**< Input/Output Multiplexing Control DDR */ kXRDC_PeriphPctlC = 430U, /**< Port Interupt Control C */ kXRDC_PeriphPctlD = 431U, /**< Port Interupt Control D */ kXRDC_PeriphPctlE = 432U, /**< Port Interupt Control E */ kXRDC_PeriphPctlF = 433U, /**< Port Interupt Control F */ kXRDC_PeriphPcc3 = 435U, /**< Peripheral Clock Control 3 */ } xrdc_periph_t; /*! * @} */ /* end of group Mapping_Information */ /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup Peripheral_access_layer Device Peripheral Access Layer * @{ */ /* ** Start of section using anonymous unions */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #else #pragma push #pragma anon_unions #endif #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=extended #else #error Not supported compiler type #endif /* ---------------------------------------------------------------------------- -- ADC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer * @{ */ /** ADC - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ uint8_t RESERVED_1[8]; __IO uint32_t FCTRL; /**< ADC FIFO Control Register, offset: 0x30 */ __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ uint8_t RESERVED_2[136]; __IO uint32_t TCTRL[2]; /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_3[56]; struct { /* offset: 0x100, array step: 0x8 */ __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ } CMD[15]; uint8_t RESERVED_4[136]; __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_5[240]; __I uint32_t RESFIFO; /**< ADC Data Result FIFO Register, offset: 0x300 */ } ADC_Type; /* ---------------------------------------------------------------------------- -- ADC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Masks ADC Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define ADC_VERID_RES_MASK (0x1U) #define ADC_VERID_RES_SHIFT (0U) /*! RES - Resolution * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. * 0b1..Up to 16-bit differential/15-bit single ended resolution supported. */ #define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) #define ADC_VERID_DIFFEN_MASK (0x2U) #define ADC_VERID_DIFFEN_SHIFT (1U) /*! DIFFEN - Differential Supported * 0b0..Differential operation not supported. * 0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented. */ #define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) #define ADC_VERID_MVI_MASK (0x8U) #define ADC_VERID_MVI_SHIFT (3U) /*! MVI - Multi Vref Implemented * 0b0..Single voltage reference high (VREFH) input supported. * 0b1..Multiple voltage reference high (VREFH) inputs supported. */ #define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) #define ADC_VERID_CSW_MASK (0x70U) #define ADC_VERID_CSW_SHIFT (4U) /*! CSW - Channel Scale Width * 0b000..Channel scaling not supported. * 0b001..Channel scaling supported. 1-bit CSCALE control field. * 0b110..Channel scaling supported. 6-bit CSCALE control field. */ #define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) #define ADC_VERID_VR1RNGI_MASK (0x100U) #define ADC_VERID_VR1RNGI_SHIFT (8U) /*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. * 0b1..Range control required. CFG[VREF1RNG] is implemented. */ #define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) #define ADC_VERID_IADCKI_MASK (0x200U) #define ADC_VERID_IADCKI_SHIFT (9U) /*! IADCKI - Internal ADC Clock implemented * 0b0..Internal clock source not implemented. * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. */ #define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) #define ADC_VERID_CALOFSI_MASK (0x400U) #define ADC_VERID_CALOFSI_SHIFT (10U) /*! CALOFSI - Calibration Offset Function Implemented * 0b0..Offset calibration and offset trimming not implemented. * 0b1..Offset calibration and offset trimming implemented. */ #define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) #define ADC_VERID_MINOR_MASK (0xFF0000U) #define ADC_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) #define ADC_VERID_MAJOR_MASK (0xFF000000U) #define ADC_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define ADC_PARAM_TRIG_NUM_MASK (0xFFU) #define ADC_PARAM_TRIG_NUM_SHIFT (0U) /*! TRIG_NUM - Trigger Number */ #define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) #define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) #define ADC_PARAM_FIFOSIZE_SHIFT (8U) /*! FIFOSIZE - Result FIFO Depth * 0b00000001..Result FIFO depth = 1 dataword. * 0b00000100..Result FIFO depth = 4 datawords. * 0b00001000..Result FIFO depth = 8 datawords. * 0b00010000..Result FIFO depth = 16 datawords. * 0b00100000..Result FIFO depth = 32 datawords. * 0b01000000..Result FIFO depth = 64 datawords. */ #define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) #define ADC_PARAM_CV_NUM_MASK (0xFF0000U) #define ADC_PARAM_CV_NUM_SHIFT (16U) /*! CV_NUM - Compare Value Number */ #define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) #define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) #define ADC_PARAM_CMD_NUM_SHIFT (24U) /*! CMD_NUM - Command Buffer Number */ #define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) /*! @} */ /*! @name CTRL - ADC Control Register */ /*! @{ */ #define ADC_CTRL_ADCEN_MASK (0x1U) #define ADC_CTRL_ADCEN_SHIFT (0U) /*! ADCEN - ADC Enable * 0b0..ADC is disabled. * 0b1..ADC is enabled. */ #define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) #define ADC_CTRL_RST_MASK (0x2U) #define ADC_CTRL_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..ADC logic is not reset. * 0b1..ADC logic is reset. */ #define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) #define ADC_CTRL_DOZEN_MASK (0x4U) #define ADC_CTRL_DOZEN_SHIFT (2U) /*! DOZEN - Doze Enable * 0b0..ADC is enabled in Doze mode. * 0b1..ADC is disabled in Doze mode. */ #define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) #define ADC_CTRL_RSTFIFO_MASK (0x100U) #define ADC_CTRL_RSTFIFO_SHIFT (8U) /*! RSTFIFO - Reset FIFO * 0b0..No effect. * 0b1..FIFO is reset. */ #define ADC_CTRL_RSTFIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK) /*! @} */ /*! @name STAT - ADC Status Register */ /*! @{ */ #define ADC_STAT_RDY_MASK (0x1U) #define ADC_STAT_RDY_SHIFT (0U) /*! RDY - Result FIFO Ready Flag * 0b0..Result FIFO data level not above watermark level. * 0b1..Result FIFO holding data above watermark level. */ #define ADC_STAT_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK) #define ADC_STAT_FOF_MASK (0x2U) #define ADC_STAT_FOF_SHIFT (1U) /*! FOF - Result FIFO Overflow Flag * 0b0..No result FIFO overflow has occurred since the last time the flag was cleared. * 0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared. */ #define ADC_STAT_FOF(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK) #define ADC_STAT_ADC_ACTIVE_MASK (0x100U) #define ADC_STAT_ADC_ACTIVE_SHIFT (8U) /*! ADC_ACTIVE - ADC Active * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. */ #define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) #define ADC_STAT_TRGACT_MASK (0x10000U) #define ADC_STAT_TRGACT_SHIFT (16U) /*! TRGACT - Trigger Active * 0b0..Command (sequence) associated with Trigger 0 currently being executed. * 0b1..Command (sequence) associated with Trigger 1 currently being executed. */ #define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) #define ADC_STAT_CMDACT_MASK (0xF000000U) #define ADC_STAT_CMDACT_SHIFT (24U) /*! CMDACT - Command Active * 0b0000..No command is currently in progress. * 0b0001..Command 1 currently being executed. * 0b0010..Command 2 currently being executed. * 0b0011-0b1111..Associated command number is currently being executed. */ #define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) /*! @} */ /*! @name IE - Interrupt Enable Register */ /*! @{ */ #define ADC_IE_FWMIE_MASK (0x1U) #define ADC_IE_FWMIE_SHIFT (0U) /*! FWMIE - FIFO Watermark Interrupt Enable * 0b0..FIFO watermark interrupts are not enabled. * 0b1..FIFO watermark interrupts are enabled. */ #define ADC_IE_FWMIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK) #define ADC_IE_FOFIE_MASK (0x2U) #define ADC_IE_FOFIE_SHIFT (1U) /*! FOFIE - Result FIFO Overflow Interrupt Enable * 0b0..FIFO overflow interrupts are not enabled. * 0b1..FIFO overflow interrupts are enabled. */ #define ADC_IE_FOFIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK) /*! @} */ /*! @name DE - DMA Enable Register */ /*! @{ */ #define ADC_DE_FWMDE_MASK (0x1U) #define ADC_DE_FWMDE_SHIFT (0U) /*! FWMDE - FIFO Watermark DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled. */ #define ADC_DE_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK) /*! @} */ /*! @name CFG - ADC Configuration Register */ /*! @{ */ #define ADC_CFG_TPRICTRL_MASK (0x1U) #define ADC_CFG_TPRICTRL_SHIFT (0U) /*! TPRICTRL - ADC trigger priority control * 0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and * the new command specified by the trigger is started. * 0b1..If a higher priority trigger is received during command processing, the current conversion is completed * (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority * trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true * conversion. */ #define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) #define ADC_CFG_PWRSEL_MASK (0x30U) #define ADC_CFG_PWRSEL_SHIFT (4U) /*! PWRSEL - Power Configuration Select * 0b00..Level 1 (Lowest power setting) * 0b01..Level 2 * 0b10..Level 3 * 0b11..Level 4 (Highest power setting) */ #define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) #define ADC_CFG_REFSEL_MASK (0xC0U) #define ADC_CFG_REFSEL_SHIFT (6U) /*! REFSEL - Voltage Reference Selection * 0b00..(Default) Option 1 setting. * 0b01..Option 2 setting. * 0b10..Option 3 setting. * 0b11..Reserved */ #define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) #define ADC_CFG_PUDLY_MASK (0xFF0000U) #define ADC_CFG_PUDLY_SHIFT (16U) /*! PUDLY - Power Up Delay */ #define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) #define ADC_CFG_PWREN_MASK (0x10000000U) #define ADC_CFG_PWREN_SHIFT (28U) /*! PWREN - ADC Analog Pre-Enable * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost * of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any * detected trigger does not begin ADC operation until the power up delay time has passed. */ #define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) /*! @} */ /*! @name PAUSE - ADC Pause Register */ /*! @{ */ #define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) #define ADC_PAUSE_PAUSEDLY_SHIFT (0U) /*! PAUSEDLY - Pause Delay */ #define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) #define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) #define ADC_PAUSE_PAUSEEN_SHIFT (31U) /*! PAUSEEN - PAUSE Option Enable * 0b0..Pause operation disabled * 0b1..Pause operation enabled */ #define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) /*! @} */ /*! @name FCTRL - ADC FIFO Control Register */ /*! @{ */ #define ADC_FCTRL_FCOUNT_MASK (0x1FU) #define ADC_FCTRL_FCOUNT_SHIFT (0U) /*! FCOUNT - Result FIFO counter */ #define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) #define ADC_FCTRL_FWMARK_MASK (0xF0000U) #define ADC_FCTRL_FWMARK_SHIFT (16U) /*! FWMARK - Watermark level selection */ #define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) /*! @} */ /*! @name SWTRIG - Software Trigger Register */ /*! @{ */ #define ADC_SWTRIG_SWT0_MASK (0x1U) #define ADC_SWTRIG_SWT0_SHIFT (0U) /*! SWT0 - Software trigger 0 event * 0b0..No trigger 0 event generated. * 0b1..Trigger 0 event generated. */ #define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) #define ADC_SWTRIG_SWT1_MASK (0x2U) #define ADC_SWTRIG_SWT1_SHIFT (1U) /*! SWT1 - Software trigger 1 event * 0b0..No trigger 1 event generated. * 0b1..Trigger 1 event generated. */ #define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) /*! @} */ /*! @name TCTRL - Trigger Control Register */ /*! @{ */ #define ADC_TCTRL_HTEN_MASK (0x1U) #define ADC_TCTRL_HTEN_SHIFT (0U) /*! HTEN - Trigger enable * 0b0..Hardware trigger source disabled * 0b1..Hardware trigger source enabled */ #define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) #define ADC_TCTRL_TPRI_MASK (0x100U) #define ADC_TCTRL_TPRI_SHIFT (8U) /*! TPRI - Trigger priority setting * 0b0..Set to highest priority, Level 1 * 0b1..Set to lower priority, Level 2 */ #define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) #define ADC_TCTRL_TDLY_MASK (0xF0000U) #define ADC_TCTRL_TDLY_SHIFT (16U) /*! TDLY - Trigger delay select */ #define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) #define ADC_TCTRL_TCMD_MASK (0xF000000U) #define ADC_TCTRL_TCMD_SHIFT (24U) /*! TCMD - Trigger command select * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. * 0b0001..CMD1 is executed * 0b0010-0b1110..Corresponding CMD is executed * 0b1111..CMD15 is executed */ #define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) /*! @} */ /* The count of ADC_TCTRL */ #define ADC_TCTRL_COUNT (2U) /*! @name CMDL - ADC Command Low Buffer Register */ /*! @{ */ #define ADC_CMDL_ADCH_MASK (0x1FU) #define ADC_CMDL_ADCH_SHIFT (0U) /*! ADCH - Input channel select * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. */ #define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) #define ADC_CMDL_ABSEL_MASK (0x20U) #define ADC_CMDL_ABSEL_SHIFT (5U) /*! ABSEL - A-side vs. B-side Select * 0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). * 0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). */ #define ADC_CMDL_ABSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK) #define ADC_CMDL_DIFF_MASK (0x40U) #define ADC_CMDL_DIFF_SHIFT (6U) /*! DIFF - Differential Mode Enable * 0b0..Single-ended mode. * 0b1..Differential mode. */ #define ADC_CMDL_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK) #define ADC_CMDL_CSCALE_MASK (0x2000U) #define ADC_CMDL_CSCALE_SHIFT (13U) /*! CSCALE - Channel Scale * 0b0..Scale selected analog channel (Factor of 30/64) * 0b1..(Default) Full scale (Factor of 1) */ #define ADC_CMDL_CSCALE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK) /*! @} */ /* The count of ADC_CMDL */ #define ADC_CMDL_COUNT (15U) /*! @name CMDH - ADC Command High Buffer Register */ /*! @{ */ #define ADC_CMDH_CMPEN_MASK (0x3U) #define ADC_CMDH_CMPEN_SHIFT (0U) /*! CMPEN - Compare Function Enable * 0b00..Compare disabled. * 0b01..Reserved * 0b10..Compare enabled. Store on true. * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. */ #define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) #define ADC_CMDH_LWI_MASK (0x80U) #define ADC_CMDH_LWI_SHIFT (7U) /*! LWI - Loop with Increment * 0b0..Auto channel increment disabled * 0b1..Auto channel increment enabled */ #define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) #define ADC_CMDH_STS_MASK (0x700U) #define ADC_CMDH_STS_SHIFT (8U) /*! STS - Sample Time Select * 0b000..Minimum sample time of 3 ADCK cycles. * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. */ #define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) #define ADC_CMDH_AVGS_MASK (0x7000U) #define ADC_CMDH_AVGS_SHIFT (12U) /*! AVGS - Hardware Average Select * 0b000..Single conversion. * 0b001..2 conversions averaged. * 0b010..4 conversions averaged. * 0b011..8 conversions averaged. * 0b100..16 conversions averaged. * 0b101..32 conversions averaged. * 0b110..64 conversions averaged. * 0b111..128 conversions averaged. */ #define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) #define ADC_CMDH_LOOP_MASK (0xF0000U) #define ADC_CMDH_LOOP_SHIFT (16U) /*! LOOP - Loop Count Select * 0b0000..Looping not enabled. Command executes 1 time. * 0b0001..Loop 1 time. Command executes 2 times. * 0b0010..Loop 2 times. Command executes 3 times. * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. * 0b1111..Loop 15 times. Command executes 16 times. */ #define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) #define ADC_CMDH_NEXT_MASK (0xF000000U) #define ADC_CMDH_NEXT_SHIFT (24U) /*! NEXT - Next Command Select * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority * trigger pending, begin command associated with lower priority trigger. * 0b0001..Select CMD1 command buffer register as next command. * 0b0010-0b1110..Select corresponding CMD command buffer register as next command * 0b1111..Select CMD15 command buffer register as next command. */ #define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) /*! @} */ /* The count of ADC_CMDH */ #define ADC_CMDH_COUNT (15U) /*! @name CV - Compare Value Register */ /*! @{ */ #define ADC_CV_CVL_MASK (0xFFFFU) #define ADC_CV_CVL_SHIFT (0U) /*! CVL - Compare Value Low. */ #define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) #define ADC_CV_CVH_MASK (0xFFFF0000U) #define ADC_CV_CVH_SHIFT (16U) /*! CVH - Compare Value High. */ #define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) /*! @} */ /* The count of ADC_CV */ #define ADC_CV_COUNT (4U) /*! @name RESFIFO - ADC Data Result FIFO Register */ /*! @{ */ #define ADC_RESFIFO_D_MASK (0xFFFFU) #define ADC_RESFIFO_D_SHIFT (0U) /*! D - Data result */ #define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) #define ADC_RESFIFO_TSRC_MASK (0x10000U) #define ADC_RESFIFO_TSRC_SHIFT (16U) /*! TSRC - Trigger Source * 0b0..Trigger source 0 initiated this conversion. * 0b1..Trigger source 1 initiated this conversion. */ #define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) #define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) #define ADC_RESFIFO_LOOPCNT_SHIFT (20U) /*! LOOPCNT - Loop count value * 0b0000..Result is from initial conversion in command. * 0b0001..Result is from second conversion in command. * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. * 0b1111..Result is from 16th conversion in command. */ #define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) #define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) #define ADC_RESFIFO_CMDSRC_SHIFT (24U) /*! CMDSRC - Command Buffer Source * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. * 0b0001..CMD1 buffer used as control settings for this conversion. * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. * 0b1111..CMD15 buffer used as control settings for this conversion. */ #define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) #define ADC_RESFIFO_VALID_MASK (0x80000000U) #define ADC_RESFIFO_VALID_SHIFT (31U) /*! VALID - FIFO entry is valid * 0b0..FIFO is empty. Discard any read from RESFIFO. * 0b1..FIFO record read from RESFIFO is valid. */ #define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) /*! @} */ /*! * @} */ /* end of group ADC_Register_Masks */ /* ADC - Peripheral instance base addresses */ /** Peripheral ADC0 base address */ #define ADC0_BASE (0x41041000u) /** Peripheral ADC0 base pointer */ #define ADC0 ((ADC_Type *)ADC0_BASE) /** Peripheral ADC1 base address */ #define ADC1_BASE (0x410AD000u) /** Peripheral ADC1 base pointer */ #define ADC1 ((ADC_Type *)ADC1_BASE) /** Array initializer of ADC peripheral base addresses */ #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } /** Array initializer of ADC peripheral base pointers */ #define ADC_BASE_PTRS { ADC0, ADC1 } /** Interrupt vectors for the ADC peripheral type */ #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } /*! * @} */ /* end of group ADC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CMP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer * @{ */ /** CMP - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x8 */ __IO uint32_t C1; /**< CMP Control Register 1, offset: 0xC */ __IO uint32_t C2; /**< CMP Control Register 2, offset: 0x10 */ __IO uint32_t C3; /**< CMP Control Register 3, offset: 0x14 */ } CMP_Type; /* ---------------------------------------------------------------------------- -- CMP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CMP_Register_Masks CMP Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define CMP_VERID_FEATURE_MASK (0xFFFFU) #define CMP_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number. This read only filed returns the feature set number. */ #define CMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK) #define CMP_VERID_MINOR_MASK (0xFF0000U) #define CMP_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number. This read only field returns the minor version number for the module specification. */ #define CMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK) #define CMP_VERID_MAJOR_MASK (0xFF000000U) #define CMP_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number. This read only field returns the major version number for the module specification. */ #define CMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define CMP_PARAM_PARAM_MASK (0xFFFFFFFFU) #define CMP_PARAM_PARAM_SHIFT (0U) /*! PARAM - Parameter Registers. This read only filed returns the feature parameters implemented along with the Version ID register. */ #define CMP_PARAM_PARAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK) /*! @} */ /*! @name C0 - CMP Control Register 0 */ /*! @{ */ #define CMP_C0_HYSTCTR_MASK (0x3U) #define CMP_C0_HYSTCTR_SHIFT (0U) /*! HYSTCTR - Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level * 0b00..The hard block output has level 0 hysteresis internally. * 0b01..The hard block output has level 1 hysteresis internally. * 0b10..The hard block output has level 2 hysteresis internally. * 0b11..The hard block output has level 3 hysteresis internally. */ #define CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK) #define CMP_C0_FILTER_CNT_MASK (0x70U) #define CMP_C0_FILTER_CNT_SHIFT (4U) /*! FILTER_CNT - Filter Sample Count * 0b000..Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. * 0b001..1 consecutive sample must agree (comparator output is simply sampled). * 0b010..2 consecutive samples must agree. * 0b011..3 consecutive samples must agree. * 0b100..4 consecutive samples must agree. * 0b101..5 consecutive samples must agree. * 0b110..6 consecutive samples must agree. * 0b111..7 consecutive samples must agree. */ #define CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK) #define CMP_C0_EN_MASK (0x100U) #define CMP_C0_EN_SHIFT (8U) /*! EN - Comparator Module Enable * 0b0..Analog Comparator is disabled. * 0b1..Analog Comparator is enabled. */ #define CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK) #define CMP_C0_OPE_MASK (0x200U) #define CMP_C0_OPE_SHIFT (9U) /*! OPE - Comparator Output Pin Enable * 0b0..When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin. * 0b1..When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin. */ #define CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK) #define CMP_C0_COS_MASK (0x400U) #define CMP_C0_COS_SHIFT (10U) /*! COS - Comparator Output Select * 0b0..Set CMPO to equal COUT (filtered comparator output). * 0b1..Set CMPO to equal COUTA (unfiltered comparator output). */ #define CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK) #define CMP_C0_INVT_MASK (0x800U) #define CMP_C0_INVT_SHIFT (11U) /*! INVT - Comparator invert * 0b0..Does not invert the comparator output. * 0b1..Inverts the comparator output. */ #define CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK) #define CMP_C0_PMODE_MASK (0x1000U) #define CMP_C0_PMODE_SHIFT (12U) /*! PMODE - Power Mode Select * 0b0..Low Speed (LS) comparison mode is selected. * 0b1..High Speed (HS) comparison mode is selected. */ #define CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK) #define CMP_C0_WE_MASK (0x4000U) #define CMP_C0_WE_SHIFT (14U) /*! WE - Windowing Enable * 0b0..Windowing mode is not selected. * 0b1..Windowing mode is selected. */ #define CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK) #define CMP_C0_SE_MASK (0x8000U) #define CMP_C0_SE_SHIFT (15U) /*! SE - Sample Enable * 0b0..Sampling mode is not selected. * 0b1..Sampling mode is selected. */ #define CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK) #define CMP_C0_FPR_MASK (0xFF0000U) #define CMP_C0_FPR_SHIFT (16U) /*! FPR - Filter Sample Period */ #define CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK) #define CMP_C0_COUT_MASK (0x1000000U) #define CMP_C0_COUT_SHIFT (24U) /*! COUT - Analog Comparator Output */ #define CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK) #define CMP_C0_CFF_MASK (0x2000000U) #define CMP_C0_CFF_SHIFT (25U) /*! CFF - Analog Comparator Flag Falling * 0b0..A falling edge has not been detected on COUT. * 0b1..A falling edge on COUT has occurred. */ #define CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK) #define CMP_C0_CFR_MASK (0x4000000U) #define CMP_C0_CFR_SHIFT (26U) /*! CFR - Analog Comparator Flag Rising * 0b0..A rising edge has not been detected on COUT. * 0b1..A rising edge on COUT has occurred. */ #define CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK) #define CMP_C0_IEF_MASK (0x8000000U) #define CMP_C0_IEF_SHIFT (27U) /*! IEF - Comparator Interrupt Enable Falling * 0b0..Interrupt is disabled. * 0b1..Interrupt is enabled. */ #define CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK) #define CMP_C0_IER_MASK (0x10000000U) #define CMP_C0_IER_SHIFT (28U) /*! IER - Comparator Interrupt Enable Rising * 0b0..Interrupt is disabled. * 0b1..Interrupt is enabled. */ #define CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK) #define CMP_C0_DMAEN_MASK (0x40000000U) #define CMP_C0_DMAEN_SHIFT (30U) /*! DMAEN - DMA Enable * 0b0..DMA is disabled. * 0b1..DMA is enabled. */ #define CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK) #define CMP_C0_LINKEN_MASK (0x80000000U) #define CMP_C0_LINKEN_SHIFT (31U) /*! LINKEN - CMP to DAC link enable. * 0b0..CMP to DAC link is disabled * 0b1..CMP to DAC link is enabled. */ #define CMP_C0_LINKEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_LINKEN_SHIFT)) & CMP_C0_LINKEN_MASK) /*! @} */ /*! @name C1 - CMP Control Register 1 */ /*! @{ */ #define CMP_C1_VOSEL_MASK (0xFFU) #define CMP_C1_VOSEL_SHIFT (0U) /*! VOSEL - DAC Output Voltage Select */ #define CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK) #define CMP_C1_DMODE_MASK (0x100U) #define CMP_C1_DMODE_SHIFT (8U) /*! DMODE - DAC Mode Selection * 0b0..DAC is selected to work in low speed and low power mode. * 0b1..DAC is selected to work in high speed high power mode. */ #define CMP_C1_DMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DMODE_SHIFT)) & CMP_C1_DMODE_MASK) #define CMP_C1_VRSEL_MASK (0x200U) #define CMP_C1_VRSEL_SHIFT (9U) /*! VRSEL - Supply Voltage Reference Source Select * 0b0..Vin1 is selected as resistor ladder network supply reference Vin. Vin1 is from internal PMC. * 0b1..Vin2 is selected as resistor ladder network supply reference Vin. Vin2 is from PAD. */ #define CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK) #define CMP_C1_DACEN_MASK (0x400U) #define CMP_C1_DACEN_SHIFT (10U) /*! DACEN - DAC Enable * 0b0..DAC is disabled. * 0b1..DAC is enabled. */ #define CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK) #define CMP_C1_DACOE_MASK (0x800U) #define CMP_C1_DACOE_SHIFT (11U) /*! DACOE - DAC Output Enable * 0b0..DAC output is enabled * 0b1..DAC output is disabled */ #define CMP_C1_DACOE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACOE_SHIFT)) & CMP_C1_DACOE_MASK) #define CMP_C1_CHN0_MASK (0x10000U) #define CMP_C1_CHN0_SHIFT (16U) /*! CHN0 - Channel 0 input enable */ #define CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK) #define CMP_C1_CHN1_MASK (0x20000U) #define CMP_C1_CHN1_SHIFT (17U) /*! CHN1 - Channel 1 input enable */ #define CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK) #define CMP_C1_CHN2_MASK (0x40000U) #define CMP_C1_CHN2_SHIFT (18U) /*! CHN2 - Channel 2 input enable */ #define CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK) #define CMP_C1_CHN3_MASK (0x80000U) #define CMP_C1_CHN3_SHIFT (19U) /*! CHN3 - Channel 3 input enable */ #define CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK) #define CMP_C1_CHN4_MASK (0x100000U) #define CMP_C1_CHN4_SHIFT (20U) /*! CHN4 - Channel 4 input enable */ #define CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK) #define CMP_C1_CHN5_MASK (0x200000U) #define CMP_C1_CHN5_SHIFT (21U) /*! CHN5 - Channel 5 input enable */ #define CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK) #define CMP_C1_MSEL_MASK (0x7000000U) #define CMP_C1_MSEL_SHIFT (24U) /*! MSEL - Minus Input MUX Control * 0b000..Internal Negative Input 0 for Minus Channel -- Internal Minus Input * 0b001..External Input 1 for Minus Channel -- Reference Input 0 * 0b010..External Input 2 for Minus Channel -- Reference Input 1 * 0b011..External Input 3 for Minus Channel -- Reference Input 2 * 0b100..External Input 4 for Minus Channel -- Reference Input 3 * 0b101..External Input 5 for Minus Channel -- Reference Input 4 * 0b110..External Input 6 for Minus Channel -- Reference Input 5 * 0b111..Internal 8b DAC output */ #define CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK) #define CMP_C1_PSEL_MASK (0x70000000U) #define CMP_C1_PSEL_SHIFT (28U) /*! PSEL - Plus Input MUX Control * 0b000..Internal Positive Input 0 for Plus Channel -- Internal Plus Input * 0b001..External Input 1 for Plus Channel -- Reference Input 0 * 0b010..External Input 2 for Plus Channel -- Reference Input 1 * 0b011..External Input 3 for Plus Channel -- Reference Input 2 * 0b100..External Input 4 for Plus Channel -- Reference Input 3 * 0b101..External Input 5 for Plus Channel -- Reference Input 4 * 0b110..External Input 6 for Plus Channel -- Reference Input 5 * 0b111..Internal 8b DAC output */ #define CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK) /*! @} */ /*! @name C2 - CMP Control Register 2 */ /*! @{ */ #define CMP_C2_ACOn_MASK (0x3FU) #define CMP_C2_ACOn_SHIFT (0U) /*! ACOn - ACOn */ #define CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK) #define CMP_C2_INITMOD_MASK (0x3F00U) #define CMP_C2_INITMOD_SHIFT (8U) /*! INITMOD - Comparator and DAC initialization delay modulus. */ #define CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK) #define CMP_C2_NSAM_MASK (0xC000U) #define CMP_C2_NSAM_SHIFT (14U) /*! NSAM - Number of sample clocks * 0b00..The comparison result is sampled as soon as the active channel is scanned in one round-robin clock. * 0b01..The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock. * 0b10..The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock. * 0b11..The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock. */ #define CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK) #define CMP_C2_CH0F_MASK (0x10000U) #define CMP_C2_CH0F_SHIFT (16U) /*! CH0F - CH0F */ #define CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK) #define CMP_C2_CH1F_MASK (0x20000U) #define CMP_C2_CH1F_SHIFT (17U) /*! CH1F - CH1F */ #define CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK) #define CMP_C2_CH2F_MASK (0x40000U) #define CMP_C2_CH2F_SHIFT (18U) /*! CH2F - CH2F */ #define CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK) #define CMP_C2_CH3F_MASK (0x80000U) #define CMP_C2_CH3F_SHIFT (19U) /*! CH3F - CH3F */ #define CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK) #define CMP_C2_CH4F_MASK (0x100000U) #define CMP_C2_CH4F_SHIFT (20U) /*! CH4F - CH4F */ #define CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK) #define CMP_C2_CH5F_MASK (0x200000U) #define CMP_C2_CH5F_SHIFT (21U) /*! CH5F - CH5F */ #define CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK) #define CMP_C2_FXMXCH_MASK (0xE000000U) #define CMP_C2_FXMXCH_SHIFT (25U) /*! FXMXCH - Fixed channel selection * 0b000..External Reference Input 0 is selected as the fixed reference input for the fixed mux port. * 0b001..External Reference Input 1 is selected as the fixed reference input for the fixed mux port. * 0b010..External Reference Input 2 is selected as the fixed reference input for the fixed mux port. * 0b011..External Reference Input 3 is selected as the fixed reference input for the fixed mux port. * 0b100..External Reference Input 4 is selected as the fixed reference input for the fixed mux port. * 0b101..External Reference Input 5 is selected as the fixed reference input for the fixed mux port. * 0b110..Reserved. * 0b111..The 8bit DAC is selected as the fixed reference input for the fixed mux port. */ #define CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK) #define CMP_C2_FXMP_MASK (0x20000000U) #define CMP_C2_FXMP_SHIFT (29U) /*! FXMP - Fixed MUX Port * 0b0..The Plus port is fixed. Only the inputs to the Minus port are swept in each round. * 0b1..The Minus port is fixed. Only the inputs to the Plus port are swept in each round. */ #define CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK) #define CMP_C2_RRIE_MASK (0x40000000U) #define CMP_C2_RRIE_SHIFT (30U) /*! RRIE - Round-Robin interrupt enable * 0b0..The round-robin interrupt is disabled. * 0b1..The round-robin interrupt is enabled when a comparison result changes from the last sample. */ #define CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK) /*! @} */ /*! @name C3 - CMP Control Register 3 */ /*! @{ */ #define CMP_C3_ACPH2TC_MASK (0x70U) #define CMP_C3_ACPH2TC_SHIFT (4U) /*! ACPH2TC - Analog Comparator Phase2 Timing Control. * 0b000..Phase2 active time in one sampling period equals to T * 0b001..Phase2 active time in one sampling period equals to 2*T * 0b010..Phase2 active time in one sampling period equals to 4*T * 0b011..Phase2 active time in one sampling period equals to 8*T * 0b100..Phase2 active time in one sampling period equals to 16*T * 0b101..Phase2 active time in one sampling period equals to 32*T * 0b110..Phase2 active time in one sampling period equals to 64*T * 0b111..Phase2 active time in one sampling period equals to 16*T */ #define CMP_C3_ACPH2TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH2TC_SHIFT)) & CMP_C3_ACPH2TC_MASK) #define CMP_C3_ACPH1TC_MASK (0x700U) #define CMP_C3_ACPH1TC_SHIFT (8U) /*! ACPH1TC - Analog Comparator Phase1 Timing Control. * 0b000..Phase1 active time in one sampling period equals to T * 0b001..Phase1 active time in one sampling period equals to 2*T * 0b010..Phase1 active time in one sampling period equals to 4*T * 0b011..Phase1 active time in one sampling period equals to 8*T * 0b100..Phase1 active time in one sampling period equals to T * 0b101..Phase1 active time in one sampling period equals to T * 0b110..Phase1 active time in one sampling period equals to T * 0b111..Phase1 active time in one sampling period equals to 0 */ #define CMP_C3_ACPH1TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH1TC_SHIFT)) & CMP_C3_ACPH1TC_MASK) #define CMP_C3_ACSAT_MASK (0x7000U) #define CMP_C3_ACSAT_SHIFT (12U) /*! ACSAT - Analog Comparator Sampling Time control. * 0b000..The sampling time equals to T * 0b001..The sampling time equasl to 2*T * 0b010..The sampling time equasl to 4*T * 0b011..The sampling time equasl to 8*T * 0b100..The sampling time equasl to 16*T * 0b101..The sampling time equasl to 32*T * 0b110..The sampling time equasl to 64*T * 0b111..The sampling time equasl to 256*T */ #define CMP_C3_ACSAT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACSAT_SHIFT)) & CMP_C3_ACSAT_MASK) #define CMP_C3_DMCS_MASK (0x10000U) #define CMP_C3_DMCS_SHIFT (16U) /*! DMCS - Discrete Mode Clock Selection * 0b0..Slow clock is selected for the timing generation. * 0b1..Fast clock is selected for the timing generation. */ #define CMP_C3_DMCS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_DMCS_SHIFT)) & CMP_C3_DMCS_MASK) #define CMP_C3_RDIVE_MASK (0x100000U) #define CMP_C3_RDIVE_SHIFT (20U) /*! RDIVE - Resistor Divider Enable * 0b0..The resistor is not enabled even when either NCHEN or PCHEN is set to1 but the actual input is in the range of 0 - 1.8v. * 0b1..The resistor is enabled because the inputs are above 1.8v. */ #define CMP_C3_RDIVE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_RDIVE_SHIFT)) & CMP_C3_RDIVE_MASK) #define CMP_C3_NCHCTEN_MASK (0x1000000U) #define CMP_C3_NCHCTEN_SHIFT (24U) /*! NCHCTEN - Negative Channel Continuous Mode Enable. * 0b0..Negative channel is in Discrete Mode and special timing needs to be configured. * 0b1..Negative channel is in Continuous Mode and no special timing is requried. */ #define CMP_C3_NCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_NCHCTEN_SHIFT)) & CMP_C3_NCHCTEN_MASK) #define CMP_C3_PCHCTEN_MASK (0x10000000U) #define CMP_C3_PCHCTEN_SHIFT (28U) /*! PCHCTEN - Positive Channel Continuous Mode Enable. * 0b0..Positive channel is in Discrete Mode and special timing needs to be configured. * 0b1..Positive channel is in Continuous Mode and no special timing is requried. */ #define CMP_C3_PCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_PCHCTEN_SHIFT)) & CMP_C3_PCHCTEN_MASK) /*! @} */ /*! * @} */ /* end of group CMP_Register_Masks */ /* CMP - Peripheral instance base addresses */ /** Peripheral CMP0 base address */ #define CMP0_BASE (0x41042000u) /** Peripheral CMP0 base pointer */ #define CMP0 ((CMP_Type *)CMP0_BASE) /** Peripheral CMP1 base address */ #define CMP1_BASE (0x41043000u) /** Peripheral CMP1 base pointer */ #define CMP1 ((CMP_Type *)CMP1_BASE) /** Array initializer of CMP peripheral base addresses */ #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } /** Array initializer of CMP peripheral base pointers */ #define CMP_BASE_PTRS { CMP0, CMP1 } /** Interrupt vectors for the CMP peripheral type */ #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn } /*! * @} */ /* end of group CMP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CRC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer * @{ */ /** CRC - Register Layout Typedef */ typedef struct { union { /* offset: 0x0 */ struct { /* offset: 0x0 */ __IO uint8_t DATALL; /**< CRC_DATALL register, offset: 0x0 */ __IO uint8_t DATALU; /**< CRC_DATALU register, offset: 0x1 */ __IO uint8_t DATAHL; /**< CRC_DATAHL register, offset: 0x2 */ __IO uint8_t DATAHU; /**< CRC_DATAHU register, offset: 0x3 */ } ACCESS8BIT; struct { /* offset: 0x0 */ __IO uint16_t DATAL; /**< CRC_DATAL register, offset: 0x0 */ __IO uint16_t DATAH; /**< CRC_DATAH register, offset: 0x2 */ } ACCESS16BIT; __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ }; union { /* offset: 0x4 */ struct { /* offset: 0x4 */ __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register, offset: 0x4 */ __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register, offset: 0x5 */ __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register, offset: 0x6 */ __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register, offset: 0x7 */ } GPOLY_ACCESS8BIT; struct { /* offset: 0x4 */ __IO uint16_t GPOLYL; /**< CRC_GPOLYL register, offset: 0x4 */ __IO uint16_t GPOLYH; /**< CRC_GPOLYH register, offset: 0x6 */ } GPOLY_ACCESS16BIT; __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ }; union { /* offset: 0x8 */ struct { /* offset: 0x8 */ uint8_t RESERVED_0[3]; __IO uint8_t CTRLHU; /**< CRC_CTRLHU register, offset: 0xB */ } CTRL_ACCESS8BIT; __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ }; } CRC_Type; /* ---------------------------------------------------------------------------- -- CRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CRC_Register_Masks CRC Register Masks * @{ */ /*! @name DATALL - CRC_DATALL register */ /*! @{ */ #define CRC_DATALL_DATALL_MASK (0xFFU) #define CRC_DATALL_DATALL_SHIFT (0U) #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) /*! @} */ /*! @name DATALU - CRC_DATALU register */ /*! @{ */ #define CRC_DATALU_DATALU_MASK (0xFFU) #define CRC_DATALU_DATALU_SHIFT (0U) #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) /*! @} */ /*! @name DATAHL - CRC_DATAHL register */ /*! @{ */ #define CRC_DATAHL_DATAHL_MASK (0xFFU) #define CRC_DATAHL_DATAHL_SHIFT (0U) #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) /*! @} */ /*! @name DATAHU - CRC_DATAHU register */ /*! @{ */ #define CRC_DATAHU_DATAHU_MASK (0xFFU) #define CRC_DATAHU_DATAHU_SHIFT (0U) #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) /*! @} */ /*! @name DATAL - CRC_DATAL register */ /*! @{ */ #define CRC_DATAL_DATAL_MASK (0xFFFFU) #define CRC_DATAL_DATAL_SHIFT (0U) #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) /*! @} */ /*! @name DATAH - CRC_DATAH register */ /*! @{ */ #define CRC_DATAH_DATAH_MASK (0xFFFFU) #define CRC_DATAH_DATAH_SHIFT (0U) #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) /*! @} */ /*! @name DATA - CRC Data register */ /*! @{ */ #define CRC_DATA_LL_MASK (0xFFU) #define CRC_DATA_LL_SHIFT (0U) /*! LL - CRC Low Lower Byte */ #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) #define CRC_DATA_LU_MASK (0xFF00U) #define CRC_DATA_LU_SHIFT (8U) /*! LU - CRC Low Upper Byte */ #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) #define CRC_DATA_HL_MASK (0xFF0000U) #define CRC_DATA_HL_SHIFT (16U) /*! HL - CRC High Lower Byte */ #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) #define CRC_DATA_HU_MASK (0xFF000000U) #define CRC_DATA_HU_SHIFT (24U) /*! HU - CRC High Upper Byte */ #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) /*! @} */ /*! @name GPOLYLL - CRC_GPOLYLL register */ /*! @{ */ #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) /*! @} */ /*! @name GPOLYLU - CRC_GPOLYLU register */ /*! @{ */ #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) /*! @} */ /*! @name GPOLYHL - CRC_GPOLYHL register */ /*! @{ */ #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) /*! @} */ /*! @name GPOLYHU - CRC_GPOLYHU register */ /*! @{ */ #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) /*! @} */ /*! @name GPOLYL - CRC_GPOLYL register */ /*! @{ */ #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) #define CRC_GPOLYL_GPOLYL_SHIFT (0U) #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) /*! @} */ /*! @name GPOLYH - CRC_GPOLYH register */ /*! @{ */ #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) #define CRC_GPOLYH_GPOLYH_SHIFT (0U) #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) /*! @} */ /*! @name GPOLY - CRC Polynomial register */ /*! @{ */ #define CRC_GPOLY_LOW_MASK (0xFFFFU) #define CRC_GPOLY_LOW_SHIFT (0U) /*! LOW - Low Polynominal Half-word */ #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) #define CRC_GPOLY_HIGH_SHIFT (16U) /*! HIGH - High Polynominal Half-word */ #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) /*! @} */ /*! @name CTRLHU - CRC_CTRLHU register */ /*! @{ */ #define CRC_CTRLHU_TCRC_MASK (0x1U) #define CRC_CTRLHU_TCRC_SHIFT (0U) /*! TCRC - TCRC * 0b0..16-bit CRC protocol. * 0b1..32-bit CRC protocol. */ #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) #define CRC_CTRLHU_WAS_MASK (0x2U) #define CRC_CTRLHU_WAS_SHIFT (1U) /*! WAS - Write CRC Data Register As Seed * 0b0..Writes to the CRC data register are data values. * 0b1..Writes to the CRC data register are seed values. */ #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) #define CRC_CTRLHU_FXOR_MASK (0x4U) #define CRC_CTRLHU_FXOR_SHIFT (2U) /*! FXOR - Complement Read Of CRC Data Register * 0b0..No XOR on reading. * 0b1..Invert or complement the read value of the CRC Data register. */ #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) #define CRC_CTRLHU_TOTR_MASK (0x30U) #define CRC_CTRLHU_TOTR_SHIFT (4U) /*! TOTR - Type Of Transpose For Read * 0b00..No transposition. * 0b01..Bits in bytes are transposed; bytes are not transposed. * 0b10..Both bits in bytes and bytes are transposed. * 0b11..Only bytes are transposed; no bits in a byte are transposed. */ #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) #define CRC_CTRLHU_TOT_MASK (0xC0U) #define CRC_CTRLHU_TOT_SHIFT (6U) /*! TOT - Type Of Transpose For Writes * 0b00..No transposition. * 0b01..Bits in bytes are transposed; bytes are not transposed. * 0b10..Both bits in bytes and bytes are transposed. * 0b11..Only bytes are transposed; no bits in a byte are transposed. */ #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) /*! @} */ /*! @name CTRL - CRC Control register */ /*! @{ */ #define CRC_CTRL_TCRC_MASK (0x1000000U) #define CRC_CTRL_TCRC_SHIFT (24U) /*! TCRC - TCRC * 0b0..16-bit CRC protocol. * 0b1..32-bit CRC protocol. */ #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) #define CRC_CTRL_WAS_MASK (0x2000000U) #define CRC_CTRL_WAS_SHIFT (25U) /*! WAS - Write CRC Data Register As Seed * 0b0..Writes to the CRC data register are data values. * 0b1..Writes to the CRC data register are seed values. */ #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) #define CRC_CTRL_FXOR_MASK (0x4000000U) #define CRC_CTRL_FXOR_SHIFT (26U) /*! FXOR - Complement Read Of CRC Data Register * 0b0..No XOR on reading. * 0b1..Invert or complement the read value of the CRC Data register. */ #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) #define CRC_CTRL_TOTR_MASK (0x30000000U) #define CRC_CTRL_TOTR_SHIFT (28U) /*! TOTR - Type Of Transpose For Read * 0b00..No transposition. * 0b01..Bits in bytes are transposed; bytes are not transposed. * 0b10..Both bits in bytes and bytes are transposed. * 0b11..Only bytes are transposed; no bits in a byte are transposed. */ #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) #define CRC_CTRL_TOT_MASK (0xC0000000U) #define CRC_CTRL_TOT_SHIFT (30U) /*! TOT - Type Of Transpose For Writes * 0b00..No transposition. * 0b01..Bits in bytes are transposed; bytes are not transposed. * 0b10..Both bits in bytes and bytes are transposed. * 0b11..Only bytes are transposed; no bits in a byte are transposed. */ #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) /*! @} */ /*! * @} */ /* end of group CRC_Register_Masks */ /* CRC - Peripheral instance base addresses */ /** Peripheral CRC0 base address */ #define CRC0_BASE (0x41029000u) /** Peripheral CRC0 base pointer */ #define CRC0 ((CRC_Type *)CRC0_BASE) /** Array initializer of CRC peripheral base addresses */ #define CRC_BASE_ADDRS { CRC0_BASE } /** Array initializer of CRC peripheral base pointers */ #define CRC_BASE_PTRS { CRC0 } /*! * @} */ /* end of group CRC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DAC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer * @{ */ /** DAC - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version Identifier Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __O uint32_t DATA; /**< DAC Data Register, offset: 0x8 */ __IO uint32_t CR; /**< DAC Status and Control Register, offset: 0xC */ __I uint32_t PTR; /**< DAC FIFO Pointer Register, offset: 0x10 */ __IO uint32_t CR2; /**< DAC Status and Control Register 2, offset: 0x14 */ __IO uint32_t ITRM; /**< Internal Current Reference Trim Register, offset: 0x18 */ } DAC_Type; /* ---------------------------------------------------------------------------- -- DAC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DAC_Register_Masks DAC Register Masks * @{ */ /*! @name VERID - Version Identifier Register */ /*! @{ */ #define DAC_VERID_FEATURE_MASK (0xFFFFU) #define DAC_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Identification Number * 0b0000000000000000..Standard feature set * 0b0000000000000001..C40 feature set * 0b0000000000000010..5V DAC feature set * 0b0000000000000100..ADC BIST feature set */ #define DAC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_FEATURE_SHIFT)) & DAC_VERID_FEATURE_MASK) #define DAC_VERID_MINOR_MASK (0xFF0000U) #define DAC_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor version number */ #define DAC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MINOR_SHIFT)) & DAC_VERID_MINOR_MASK) #define DAC_VERID_MAJOR_MASK (0xFF000000U) #define DAC_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major version number */ #define DAC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MAJOR_SHIFT)) & DAC_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define DAC_PARAM_FIFOSZ_MASK (0x7U) #define DAC_PARAM_FIFOSZ_SHIFT (0U) /*! FIFOSZ - FIFO size * 0b000..FIFO depth is 2 * 0b001..FIFO depth is 4 * 0b010..FIFO depth is 8 * 0b011..FIFO depth is 16 * 0b100..FIFO depth is 32 * 0b101..FIFO depth is 64 * 0b110..FIFO depth is 128 * 0b111..FIFO depth is 256 */ #define DAC_PARAM_FIFOSZ(x) (((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK) /*! @} */ /*! @name DATA - DAC Data Register */ /*! @{ */ #define DAC_DATA_DATA0_MASK (0xFFFU) #define DAC_DATA_DATA0_SHIFT (0U) /*! DATA0 - FIFO DATA0 */ #define DAC_DATA_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DAC_DATA_DATA0_SHIFT)) & DAC_DATA_DATA0_MASK) /*! @} */ /*! @name CR - DAC Status and Control Register */ /*! @{ */ #define DAC_CR_FULLF_MASK (0x1U) #define DAC_CR_FULLF_SHIFT (0U) /*! FULLF - Full Flag * 0b0..FIFO is not full. * 0b1..FIFO is full. */ #define DAC_CR_FULLF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLF_SHIFT)) & DAC_CR_FULLF_MASK) #define DAC_CR_NEMPTF_MASK (0x2U) #define DAC_CR_NEMPTF_SHIFT (1U) /*! NEMPTF - Nearly Empty Flag * 0b0..More than one data is available in the FIFO. * 0b1..One data is available in the FIFO. */ #define DAC_CR_NEMPTF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_NEMPTF_SHIFT)) & DAC_CR_NEMPTF_MASK) #define DAC_CR_WMF_MASK (0x4U) #define DAC_CR_WMF_SHIFT (2U) /*! WMF - FIFO Watermark Status Flag * 0b0..The DAC buffer read pointer has not reached the watermark level. * 0b1..The DAC buffer read pointer has reached the watermark level. */ #define DAC_CR_WMF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WMF_SHIFT)) & DAC_CR_WMF_MASK) #define DAC_CR_UDFF_MASK (0x8U) #define DAC_CR_UDFF_SHIFT (3U) /*! UDFF - Underflow Flag * 0b0..No underflow has occurred since the last time the flag was cleared. * 0b1..At least one trigger underflow has occurred since the last time the flag was cleared. */ #define DAC_CR_UDFF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UDFF_SHIFT)) & DAC_CR_UDFF_MASK) #define DAC_CR_OVFF_MASK (0x10U) #define DAC_CR_OVFF_SHIFT (4U) /*! OVFF - Overflow Flag * 0b0..No overflow has occurred since the last time the flag was cleared. * 0b1..At least one FIFO overflow has occurred since the last time the flag was cleared. */ #define DAC_CR_OVFF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_OVFF_SHIFT)) & DAC_CR_OVFF_MASK) #define DAC_CR_FULLIE_MASK (0x100U) #define DAC_CR_FULLIE_SHIFT (8U) /*! FULLIE - Full Interrupt Enable * 0b0..FIFO Full interrupt is disabled. * 0b1..FIFO Full interrupt is enabled. */ #define DAC_CR_FULLIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLIE_SHIFT)) & DAC_CR_FULLIE_MASK) #define DAC_CR_EMPTIE_MASK (0x200U) #define DAC_CR_EMPTIE_SHIFT (9U) /*! EMPTIE - Nearly Empty Interrupt Enable * 0b0..FIFO Nearly Empty interrupt is disabled. * 0b1..FIFO Nearly Empty interrupt is enabled. */ #define DAC_CR_EMPTIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_EMPTIE_SHIFT)) & DAC_CR_EMPTIE_MASK) #define DAC_CR_WTMIE_MASK (0x400U) #define DAC_CR_WTMIE_SHIFT (10U) /*! WTMIE - Watermark Interrupt Enable * 0b0..Watermark interrupt is disabled. * 0b1..Watermark interrupt is enabled. */ #define DAC_CR_WTMIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WTMIE_SHIFT)) & DAC_CR_WTMIE_MASK) #define DAC_CR_SWTRG_MASK (0x1000U) #define DAC_CR_SWTRG_SHIFT (12U) /*! SWTRG - DAC Software Trigger * 0b0..The DAC soft trigger is not valid. * 0b1..The DAC soft trigger is valid. */ #define DAC_CR_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWTRG_SHIFT)) & DAC_CR_SWTRG_MASK) #define DAC_CR_TRGSEL_MASK (0x2000U) #define DAC_CR_TRGSEL_SHIFT (13U) /*! TRGSEL - DAC Trigger Select * 0b0..The DAC hardware trigger is selected. * 0b1..The DAC software trigger is selected. */ #define DAC_CR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_TRGSEL_SHIFT)) & DAC_CR_TRGSEL_MASK) #define DAC_CR_DACRFS_MASK (0x4000U) #define DAC_CR_DACRFS_SHIFT (14U) /*! DACRFS - DAC Reference Select * 0b0..The DAC selects DACREF_1 as the reference voltage. * 0b1..The DAC selects DACREF_2 as the reference voltage. */ #define DAC_CR_DACRFS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACRFS_SHIFT)) & DAC_CR_DACRFS_MASK) #define DAC_CR_DACEN_MASK (0x8000U) #define DAC_CR_DACEN_SHIFT (15U) /*! DACEN - DAC Enable * 0b0..The DAC system is disabled. * 0b1..The DAC system is enabled. */ #define DAC_CR_DACEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACEN_SHIFT)) & DAC_CR_DACEN_MASK) #define DAC_CR_FIFOEN_MASK (0x10000U) #define DAC_CR_FIFOEN_SHIFT (16U) /*! FIFOEN - FIFO Enable * 0b0..FIFO is disabled and only one level buffer is enabled. Any data written from this buffer goes to conversion. * 0b1..FIFO is enabled. Data will first read from FIFO to buffer then go to conversion. */ #define DAC_CR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFOEN_SHIFT)) & DAC_CR_FIFOEN_MASK) #define DAC_CR_SWMD_MASK (0x20000U) #define DAC_CR_SWMD_SHIFT (17U) /*! SWMD - DAC FIFO Mode Select * 0b0..Normal mode * 0b1..Swing back mode */ #define DAC_CR_SWMD(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWMD_SHIFT)) & DAC_CR_SWMD_MASK) #define DAC_CR_UVIE_MASK (0x40000U) #define DAC_CR_UVIE_SHIFT (18U) /*! UVIE - Underflow and overflow interrupt enable * 0b0..Underflow and overflow interrupt is disabled. * 0b1..Underflow and overflow interrupt is enabled. */ #define DAC_CR_UVIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UVIE_SHIFT)) & DAC_CR_UVIE_MASK) #define DAC_CR_FIFORST_MASK (0x200000U) #define DAC_CR_FIFORST_SHIFT (21U) /*! FIFORST - FIFO Reset * 0b0..No effect * 0b1..FIFO reset */ #define DAC_CR_FIFORST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFORST_SHIFT)) & DAC_CR_FIFORST_MASK) #define DAC_CR_SWRST_MASK (0x400000U) #define DAC_CR_SWRST_SHIFT (22U) /*! SWRST - Software reset */ #define DAC_CR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWRST_SHIFT)) & DAC_CR_SWRST_MASK) #define DAC_CR_DMAEN_MASK (0x800000U) #define DAC_CR_DMAEN_SHIFT (23U) /*! DMAEN - DMA Enable Select * 0b0..DMA is disabled. * 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The * interrupts will not be presented on this module at the same time. */ #define DAC_CR_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DMAEN_SHIFT)) & DAC_CR_DMAEN_MASK) #define DAC_CR_WML_MASK (0xFF000000U) #define DAC_CR_WML_SHIFT (24U) /*! WML - Watermark Level Select */ #define DAC_CR_WML(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WML_SHIFT)) & DAC_CR_WML_MASK) /*! @} */ /*! @name PTR - DAC FIFO Pointer Register */ /*! @{ */ #define DAC_PTR_DACWFP_MASK (0xFFU) #define DAC_PTR_DACWFP_SHIFT (0U) /*! DACWFP - DACWFP */ #define DAC_PTR_DACWFP(x) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACWFP_SHIFT)) & DAC_PTR_DACWFP_MASK) #define DAC_PTR_DACRFP_MASK (0xFF0000U) #define DAC_PTR_DACRFP_SHIFT (16U) /*! DACRFP - DACRFP */ #define DAC_PTR_DACRFP(x) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACRFP_SHIFT)) & DAC_PTR_DACRFP_MASK) /*! @} */ /*! @name CR2 - DAC Status and Control Register 2 */ /*! @{ */ #define DAC_CR2_BFEN_MASK (0x1U) #define DAC_CR2_BFEN_SHIFT (0U) /*! BFEN - Buffer Enable * 0b0..Opamp is not used as buffer * 0b1..Opamp is used as buffer */ #define DAC_CR2_BFEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFEN_SHIFT)) & DAC_CR2_BFEN_MASK) #define DAC_CR2_OEN_MASK (0x2U) #define DAC_CR2_OEN_SHIFT (1U) /*! OEN - Optional Enable * 0b0..Output buffer is not bypassed * 0b1..Output buffer is bypassed */ #define DAC_CR2_OEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_OEN_SHIFT)) & DAC_CR2_OEN_MASK) #define DAC_CR2_BFMS_MASK (0x4U) #define DAC_CR2_BFMS_SHIFT (2U) /*! BFMS - Buffer Middle Speed Select * 0b0..Buffer middle speed not selected * 0b1..Buffer middle speed selected */ #define DAC_CR2_BFMS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFMS_SHIFT)) & DAC_CR2_BFMS_MASK) #define DAC_CR2_BFHS_MASK (0x8U) #define DAC_CR2_BFHS_SHIFT (3U) /*! BFHS - Buffer High Speed Select * 0b0..Buffer high speed not selected * 0b1..Buffer high speed selected */ #define DAC_CR2_BFHS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFHS_SHIFT)) & DAC_CR2_BFHS_MASK) #define DAC_CR2_IREF2_MASK (0x10U) #define DAC_CR2_IREF2_SHIFT (4U) /*! IREF2 - Internal PTAT (Proportional To Absolute Temperature) Current Reference Select * 0b0..Internal PTAT Current Reference not selected * 0b1..Internal PTAT Current Reference selected */ #define DAC_CR2_IREF2(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF2_SHIFT)) & DAC_CR2_IREF2_MASK) #define DAC_CR2_IREF1_MASK (0x20U) #define DAC_CR2_IREF1_SHIFT (5U) /*! IREF1 - Internal ZTC (Zero Temperature Coefficient) Current Reference Select * 0b0..Internal ZTC Current Reference not selected * 0b1..Internal ZTC Current Reference selected */ #define DAC_CR2_IREF1(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF1_SHIFT)) & DAC_CR2_IREF1_MASK) #define DAC_CR2_IREF_MASK (0x40U) #define DAC_CR2_IREF_SHIFT (6U) /*! IREF - Internal Current Reference Select * 0b0..Internal Current Reference not selected * 0b1..Internal Current Reference selected */ #define DAC_CR2_IREF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF_SHIFT)) & DAC_CR2_IREF_MASK) /*! @} */ /*! @name ITRM - Internal Current Reference Trim Register */ /*! @{ */ #define DAC_ITRM_TRIM_MASK (0x7U) #define DAC_ITRM_TRIM_SHIFT (0U) /*! TRIM - Internal Current Trim Register */ #define DAC_ITRM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DAC_ITRM_TRIM_SHIFT)) & DAC_ITRM_TRIM_MASK) /*! @} */ /*! * @} */ /* end of group DAC_Register_Masks */ /* DAC - Peripheral instance base addresses */ /** Peripheral DAC0 base address */ #define DAC0_BASE (0x41044000u) /** Peripheral DAC0 base pointer */ #define DAC0 ((DAC_Type *)DAC0_BASE) /** Peripheral DAC1 base address */ #define DAC1_BASE (0x41045000u) /** Peripheral DAC1 base pointer */ #define DAC1 ((DAC_Type *)DAC1_BASE) /** Array initializer of DAC peripheral base addresses */ #define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } /** Array initializer of DAC peripheral base pointers */ #define DAC_BASE_PTRS { DAC0, DAC1 } /** Interrupt vectors for the DAC peripheral type */ #define DAC_IRQS { DAC0_IRQn, DAC1_IRQn } /*! * @} */ /* end of group DAC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer * @{ */ /** DMA - Register Layout Typedef */ typedef struct { __IO uint32_t CR; /**< Control Register, offset: 0x0 */ __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ uint8_t RESERVED_0[4]; __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ uint8_t RESERVED_1[4]; __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ uint8_t RESERVED_2[4]; __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ uint8_t RESERVED_3[4]; __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ uint8_t RESERVED_4[4]; __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ uint8_t RESERVED_5[12]; __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */ uint8_t RESERVED_6[184]; __IO uint8_t DCHPRI3; /**< Channel Priority Register, offset: 0x100 */ __IO uint8_t DCHPRI2; /**< Channel Priority Register, offset: 0x101 */ __IO uint8_t DCHPRI1; /**< Channel Priority Register, offset: 0x102 */ __IO uint8_t DCHPRI0; /**< Channel Priority Register, offset: 0x103 */ __IO uint8_t DCHPRI7; /**< Channel Priority Register, offset: 0x104 */ __IO uint8_t DCHPRI6; /**< Channel Priority Register, offset: 0x105 */ __IO uint8_t DCHPRI5; /**< Channel Priority Register, offset: 0x106 */ __IO uint8_t DCHPRI4; /**< Channel Priority Register, offset: 0x107 */ __IO uint8_t DCHPRI11; /**< Channel Priority Register, offset: 0x108 */ __IO uint8_t DCHPRI10; /**< Channel Priority Register, offset: 0x109 */ __IO uint8_t DCHPRI9; /**< Channel Priority Register, offset: 0x10A */ __IO uint8_t DCHPRI8; /**< Channel Priority Register, offset: 0x10B */ __IO uint8_t DCHPRI15; /**< Channel Priority Register, offset: 0x10C */ __IO uint8_t DCHPRI14; /**< Channel Priority Register, offset: 0x10D */ __IO uint8_t DCHPRI13; /**< Channel Priority Register, offset: 0x10E */ __IO uint8_t DCHPRI12; /**< Channel Priority Register, offset: 0x10F */ __IO uint8_t DCHPRI19; /**< Channel Priority Register, offset: 0x110 */ __IO uint8_t DCHPRI18; /**< Channel Priority Register, offset: 0x111 */ __IO uint8_t DCHPRI17; /**< Channel Priority Register, offset: 0x112 */ __IO uint8_t DCHPRI16; /**< Channel Priority Register, offset: 0x113 */ __IO uint8_t DCHPRI23; /**< Channel Priority Register, offset: 0x114 */ __IO uint8_t DCHPRI22; /**< Channel Priority Register, offset: 0x115 */ __IO uint8_t DCHPRI21; /**< Channel Priority Register, offset: 0x116 */ __IO uint8_t DCHPRI20; /**< Channel Priority Register, offset: 0x117 */ __IO uint8_t DCHPRI27; /**< Channel Priority Register, offset: 0x118 */ __IO uint8_t DCHPRI26; /**< Channel Priority Register, offset: 0x119 */ __IO uint8_t DCHPRI25; /**< Channel Priority Register, offset: 0x11A */ __IO uint8_t DCHPRI24; /**< Channel Priority Register, offset: 0x11B */ __IO uint8_t DCHPRI31; /**< Channel Priority Register, offset: 0x11C */ __IO uint8_t DCHPRI30; /**< Channel Priority Register, offset: 0x11D */ __IO uint8_t DCHPRI29; /**< Channel Priority Register, offset: 0x11E */ __IO uint8_t DCHPRI28; /**< Channel Priority Register, offset: 0x11F */ uint8_t RESERVED_7[3808]; struct { /* offset: 0x1000, array step: 0x20 */ __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ union { /* offset: 0x1008, array step: 0x20 */ __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ }; __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ union { /* offset: 0x1016, array step: 0x20 */ __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ }; __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ union { /* offset: 0x101E, array step: 0x20 */ __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ }; } TCD[32]; } DMA_Type; /* ---------------------------------------------------------------------------- -- DMA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Register_Masks DMA Register Masks * @{ */ /*! @name CR - Control Register */ /*! @{ */ #define DMA_CR_EBWR_MASK (0x1U) #define DMA_CR_EBWR_SHIFT (0U) /*! EBWR - Enable Buffered Writes * 0b0..Buffered writes are disabled. * 0b1..Buffered writes are enabled. */ #define DMA_CR_EBWR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EBWR_SHIFT)) & DMA_CR_EBWR_MASK) #define DMA_CR_EDBG_MASK (0x2U) #define DMA_CR_EDBG_SHIFT (1U) /*! EDBG - Enable Debug * 0b0..When in debug mode, the DMA continues to operate. * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to * complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. */ #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) #define DMA_CR_ERCA_MASK (0x4U) #define DMA_CR_ERCA_SHIFT (2U) /*! ERCA - Enable Round Robin Channel Arbitration * 0b0..Fixed priority arbitration is used for channel selection within each group. * 0b1..Round robin arbitration is used for channel selection within each group. */ #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) #define DMA_CR_ERGA_MASK (0x8U) #define DMA_CR_ERGA_SHIFT (3U) /*! ERGA - Enable Round Robin Group Arbitration * 0b0..Fixed priority arbitration is used for selection among the groups. * 0b1..Round robin arbitration is used for selection among the groups. */ #define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK) #define DMA_CR_HOE_MASK (0x10U) #define DMA_CR_HOE_SHIFT (4U) /*! HOE - Halt On Error * 0b0..Normal operation * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. */ #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) #define DMA_CR_HALT_MASK (0x20U) #define DMA_CR_HALT_SHIFT (5U) /*! HALT - Halt DMA Operations * 0b0..Normal operation * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. */ #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) #define DMA_CR_CLM_MASK (0x40U) #define DMA_CR_CLM_SHIFT (6U) /*! CLM - Continuous Link Mode * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated * again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel * link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the * next minor loop. */ #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) #define DMA_CR_EMLM_MASK (0x80U) #define DMA_CR_EMLM_SHIFT (7U) /*! EMLM - Enable Minor Loop Mapping * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES * field. The individual enable fields allow the minor loop offset to be applied to the source address, the * destination address, or both. The NBYTES field is reduced when either offset is enabled. */ #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) #define DMA_CR_GRP0PRI_MASK (0x100U) #define DMA_CR_GRP0PRI_SHIFT (8U) /*! GRP0PRI - Channel Group 0 Priority */ #define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK) #define DMA_CR_GRP1PRI_MASK (0x400U) #define DMA_CR_GRP1PRI_SHIFT (10U) /*! GRP1PRI - Channel Group 1 Priority */ #define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK) #define DMA_CR_ECX_MASK (0x10000U) #define DMA_CR_ECX_SHIFT (16U) /*! ECX - Error Cancel Transfer * 0b0..Normal operation * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and * force the minor loop to finish. The cancel takes effect after the last write of the current read/write * sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX * treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an * optional error interrupt. */ #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) #define DMA_CR_CX_MASK (0x20000U) #define DMA_CR_CX_SHIFT (17U) /*! CX - Cancel Transfer * 0b0..Normal operation * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The * cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after * the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. */ #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) #define DMA_CR_ACTIVE_MASK (0x80000000U) #define DMA_CR_ACTIVE_SHIFT (31U) /*! ACTIVE - DMA Active Status * 0b0..eDMA is idle. * 0b1..eDMA is executing a channel. */ #define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) /*! @} */ /*! @name ES - Error Status Register */ /*! @{ */ #define DMA_ES_DBE_MASK (0x1U) #define DMA_ES_DBE_SHIFT (0U) /*! DBE - Destination Bus Error * 0b0..No destination bus error * 0b1..The last recorded error was a bus error on a destination write */ #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) #define DMA_ES_SBE_MASK (0x2U) #define DMA_ES_SBE_SHIFT (1U) /*! SBE - Source Bus Error * 0b0..No source bus error * 0b1..The last recorded error was a bus error on a source read */ #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) #define DMA_ES_SGE_MASK (0x4U) #define DMA_ES_SGE_SHIFT (2U) /*! SGE - Scatter/Gather Configuration Error * 0b0..No scatter/gather configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is * checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is * enabled. TCDn_DLASTSGA is not on a 32 byte boundary. */ #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) #define DMA_ES_NCE_MASK (0x8U) #define DMA_ES_NCE_SHIFT (3U) /*! NCE - NBYTES/CITER Configuration Error * 0b0..No NBYTES/CITER configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. * TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, * or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] */ #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) #define DMA_ES_DOE_MASK (0x10U) #define DMA_ES_DOE_SHIFT (4U) /*! DOE - Destination Offset Error * 0b0..No destination offset configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. */ #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) #define DMA_ES_DAE_MASK (0x20U) #define DMA_ES_DAE_SHIFT (5U) /*! DAE - Destination Address Error * 0b0..No destination address configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. */ #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) #define DMA_ES_SOE_MASK (0x40U) #define DMA_ES_SOE_SHIFT (6U) /*! SOE - Source Offset Error * 0b0..No source offset configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. */ #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) #define DMA_ES_SAE_MASK (0x80U) #define DMA_ES_SAE_SHIFT (7U) /*! SAE - Source Address Error * 0b0..No source address configuration error. * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. */ #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) #define DMA_ES_ERRCHN_MASK (0x1F00U) #define DMA_ES_ERRCHN_SHIFT (8U) /*! ERRCHN - Error Channel Number or Canceled Channel Number */ #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) #define DMA_ES_CPE_MASK (0x4000U) #define DMA_ES_CPE_SHIFT (14U) /*! CPE - Channel Priority Error * 0b0..No channel priority error * 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel * priorities within a group are not unique. */ #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) #define DMA_ES_GPE_MASK (0x8000U) #define DMA_ES_GPE_SHIFT (15U) /*! GPE - Group Priority Error * 0b0..No group priority error * 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique. */ #define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK) #define DMA_ES_ECX_MASK (0x10000U) #define DMA_ES_ECX_SHIFT (16U) /*! ECX - Transfer Canceled * 0b0..No canceled transfers * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input */ #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) #define DMA_ES_VLD_MASK (0x80000000U) #define DMA_ES_VLD_SHIFT (31U) /*! VLD - VLD * 0b0..No ERR bits are set. * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared. */ #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) /*! @} */ /*! @name ERQ - Enable Request Register */ /*! @{ */ #define DMA_ERQ_ERQ0_MASK (0x1U) #define DMA_ERQ_ERQ0_SHIFT (0U) /*! ERQ0 - Enable DMA Request 0 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) #define DMA_ERQ_ERQ1_MASK (0x2U) #define DMA_ERQ_ERQ1_SHIFT (1U) /*! ERQ1 - Enable DMA Request 1 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) #define DMA_ERQ_ERQ2_MASK (0x4U) #define DMA_ERQ_ERQ2_SHIFT (2U) /*! ERQ2 - Enable DMA Request 2 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) #define DMA_ERQ_ERQ3_MASK (0x8U) #define DMA_ERQ_ERQ3_SHIFT (3U) /*! ERQ3 - Enable DMA Request 3 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) #define DMA_ERQ_ERQ4_MASK (0x10U) #define DMA_ERQ_ERQ4_SHIFT (4U) /*! ERQ4 - Enable DMA Request 4 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) #define DMA_ERQ_ERQ5_MASK (0x20U) #define DMA_ERQ_ERQ5_SHIFT (5U) /*! ERQ5 - Enable DMA Request 5 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) #define DMA_ERQ_ERQ6_MASK (0x40U) #define DMA_ERQ_ERQ6_SHIFT (6U) /*! ERQ6 - Enable DMA Request 6 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) #define DMA_ERQ_ERQ7_MASK (0x80U) #define DMA_ERQ_ERQ7_SHIFT (7U) /*! ERQ7 - Enable DMA Request 7 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) #define DMA_ERQ_ERQ8_MASK (0x100U) #define DMA_ERQ_ERQ8_SHIFT (8U) /*! ERQ8 - Enable DMA Request 8 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) #define DMA_ERQ_ERQ9_MASK (0x200U) #define DMA_ERQ_ERQ9_SHIFT (9U) /*! ERQ9 - Enable DMA Request 9 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) #define DMA_ERQ_ERQ10_MASK (0x400U) #define DMA_ERQ_ERQ10_SHIFT (10U) /*! ERQ10 - Enable DMA Request 10 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) #define DMA_ERQ_ERQ11_MASK (0x800U) #define DMA_ERQ_ERQ11_SHIFT (11U) /*! ERQ11 - Enable DMA Request 11 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) #define DMA_ERQ_ERQ12_MASK (0x1000U) #define DMA_ERQ_ERQ12_SHIFT (12U) /*! ERQ12 - Enable DMA Request 12 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) #define DMA_ERQ_ERQ13_MASK (0x2000U) #define DMA_ERQ_ERQ13_SHIFT (13U) /*! ERQ13 - Enable DMA Request 13 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) #define DMA_ERQ_ERQ14_MASK (0x4000U) #define DMA_ERQ_ERQ14_SHIFT (14U) /*! ERQ14 - Enable DMA Request 14 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) #define DMA_ERQ_ERQ15_MASK (0x8000U) #define DMA_ERQ_ERQ15_SHIFT (15U) /*! ERQ15 - Enable DMA Request 15 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) #define DMA_ERQ_ERQ16_MASK (0x10000U) #define DMA_ERQ_ERQ16_SHIFT (16U) /*! ERQ16 - Enable DMA Request 16 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK) #define DMA_ERQ_ERQ17_MASK (0x20000U) #define DMA_ERQ_ERQ17_SHIFT (17U) /*! ERQ17 - Enable DMA Request 17 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK) #define DMA_ERQ_ERQ18_MASK (0x40000U) #define DMA_ERQ_ERQ18_SHIFT (18U) /*! ERQ18 - Enable DMA Request 18 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK) #define DMA_ERQ_ERQ19_MASK (0x80000U) #define DMA_ERQ_ERQ19_SHIFT (19U) /*! ERQ19 - Enable DMA Request 19 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK) #define DMA_ERQ_ERQ20_MASK (0x100000U) #define DMA_ERQ_ERQ20_SHIFT (20U) /*! ERQ20 - Enable DMA Request 20 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK) #define DMA_ERQ_ERQ21_MASK (0x200000U) #define DMA_ERQ_ERQ21_SHIFT (21U) /*! ERQ21 - Enable DMA Request 21 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK) #define DMA_ERQ_ERQ22_MASK (0x400000U) #define DMA_ERQ_ERQ22_SHIFT (22U) /*! ERQ22 - Enable DMA Request 22 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK) #define DMA_ERQ_ERQ23_MASK (0x800000U) #define DMA_ERQ_ERQ23_SHIFT (23U) /*! ERQ23 - Enable DMA Request 23 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK) #define DMA_ERQ_ERQ24_MASK (0x1000000U) #define DMA_ERQ_ERQ24_SHIFT (24U) /*! ERQ24 - Enable DMA Request 24 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK) #define DMA_ERQ_ERQ25_MASK (0x2000000U) #define DMA_ERQ_ERQ25_SHIFT (25U) /*! ERQ25 - Enable DMA Request 25 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK) #define DMA_ERQ_ERQ26_MASK (0x4000000U) #define DMA_ERQ_ERQ26_SHIFT (26U) /*! ERQ26 - Enable DMA Request 26 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK) #define DMA_ERQ_ERQ27_MASK (0x8000000U) #define DMA_ERQ_ERQ27_SHIFT (27U) /*! ERQ27 - Enable DMA Request 27 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK) #define DMA_ERQ_ERQ28_MASK (0x10000000U) #define DMA_ERQ_ERQ28_SHIFT (28U) /*! ERQ28 - Enable DMA Request 28 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK) #define DMA_ERQ_ERQ29_MASK (0x20000000U) #define DMA_ERQ_ERQ29_SHIFT (29U) /*! ERQ29 - Enable DMA Request 29 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK) #define DMA_ERQ_ERQ30_MASK (0x40000000U) #define DMA_ERQ_ERQ30_SHIFT (30U) /*! ERQ30 - Enable DMA Request 30 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK) #define DMA_ERQ_ERQ31_MASK (0x80000000U) #define DMA_ERQ_ERQ31_SHIFT (31U) /*! ERQ31 - Enable DMA Request 31 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK) /*! @} */ /*! @name EEI - Enable Error Interrupt Register */ /*! @{ */ #define DMA_EEI_EEI0_MASK (0x1U) #define DMA_EEI_EEI0_SHIFT (0U) /*! EEI0 - Enable Error Interrupt 0 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) #define DMA_EEI_EEI1_MASK (0x2U) #define DMA_EEI_EEI1_SHIFT (1U) /*! EEI1 - Enable Error Interrupt 1 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) #define DMA_EEI_EEI2_MASK (0x4U) #define DMA_EEI_EEI2_SHIFT (2U) /*! EEI2 - Enable Error Interrupt 2 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) #define DMA_EEI_EEI3_MASK (0x8U) #define DMA_EEI_EEI3_SHIFT (3U) /*! EEI3 - Enable Error Interrupt 3 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) #define DMA_EEI_EEI4_MASK (0x10U) #define DMA_EEI_EEI4_SHIFT (4U) /*! EEI4 - Enable Error Interrupt 4 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) #define DMA_EEI_EEI5_MASK (0x20U) #define DMA_EEI_EEI5_SHIFT (5U) /*! EEI5 - Enable Error Interrupt 5 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) #define DMA_EEI_EEI6_MASK (0x40U) #define DMA_EEI_EEI6_SHIFT (6U) /*! EEI6 - Enable Error Interrupt 6 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) #define DMA_EEI_EEI7_MASK (0x80U) #define DMA_EEI_EEI7_SHIFT (7U) /*! EEI7 - Enable Error Interrupt 7 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) #define DMA_EEI_EEI8_MASK (0x100U) #define DMA_EEI_EEI8_SHIFT (8U) /*! EEI8 - Enable Error Interrupt 8 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) #define DMA_EEI_EEI9_MASK (0x200U) #define DMA_EEI_EEI9_SHIFT (9U) /*! EEI9 - Enable Error Interrupt 9 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) #define DMA_EEI_EEI10_MASK (0x400U) #define DMA_EEI_EEI10_SHIFT (10U) /*! EEI10 - Enable Error Interrupt 10 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) #define DMA_EEI_EEI11_MASK (0x800U) #define DMA_EEI_EEI11_SHIFT (11U) /*! EEI11 - Enable Error Interrupt 11 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) #define DMA_EEI_EEI12_MASK (0x1000U) #define DMA_EEI_EEI12_SHIFT (12U) /*! EEI12 - Enable Error Interrupt 12 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) #define DMA_EEI_EEI13_MASK (0x2000U) #define DMA_EEI_EEI13_SHIFT (13U) /*! EEI13 - Enable Error Interrupt 13 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) #define DMA_EEI_EEI14_MASK (0x4000U) #define DMA_EEI_EEI14_SHIFT (14U) /*! EEI14 - Enable Error Interrupt 14 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) #define DMA_EEI_EEI15_MASK (0x8000U) #define DMA_EEI_EEI15_SHIFT (15U) /*! EEI15 - Enable Error Interrupt 15 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) #define DMA_EEI_EEI16_MASK (0x10000U) #define DMA_EEI_EEI16_SHIFT (16U) /*! EEI16 - Enable Error Interrupt 16 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK) #define DMA_EEI_EEI17_MASK (0x20000U) #define DMA_EEI_EEI17_SHIFT (17U) /*! EEI17 - Enable Error Interrupt 17 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK) #define DMA_EEI_EEI18_MASK (0x40000U) #define DMA_EEI_EEI18_SHIFT (18U) /*! EEI18 - Enable Error Interrupt 18 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK) #define DMA_EEI_EEI19_MASK (0x80000U) #define DMA_EEI_EEI19_SHIFT (19U) /*! EEI19 - Enable Error Interrupt 19 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK) #define DMA_EEI_EEI20_MASK (0x100000U) #define DMA_EEI_EEI20_SHIFT (20U) /*! EEI20 - Enable Error Interrupt 20 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK) #define DMA_EEI_EEI21_MASK (0x200000U) #define DMA_EEI_EEI21_SHIFT (21U) /*! EEI21 - Enable Error Interrupt 21 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK) #define DMA_EEI_EEI22_MASK (0x400000U) #define DMA_EEI_EEI22_SHIFT (22U) /*! EEI22 - Enable Error Interrupt 22 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK) #define DMA_EEI_EEI23_MASK (0x800000U) #define DMA_EEI_EEI23_SHIFT (23U) /*! EEI23 - Enable Error Interrupt 23 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK) #define DMA_EEI_EEI24_MASK (0x1000000U) #define DMA_EEI_EEI24_SHIFT (24U) /*! EEI24 - Enable Error Interrupt 24 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK) #define DMA_EEI_EEI25_MASK (0x2000000U) #define DMA_EEI_EEI25_SHIFT (25U) /*! EEI25 - Enable Error Interrupt 25 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK) #define DMA_EEI_EEI26_MASK (0x4000000U) #define DMA_EEI_EEI26_SHIFT (26U) /*! EEI26 - Enable Error Interrupt 26 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK) #define DMA_EEI_EEI27_MASK (0x8000000U) #define DMA_EEI_EEI27_SHIFT (27U) /*! EEI27 - Enable Error Interrupt 27 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK) #define DMA_EEI_EEI28_MASK (0x10000000U) #define DMA_EEI_EEI28_SHIFT (28U) /*! EEI28 - Enable Error Interrupt 28 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK) #define DMA_EEI_EEI29_MASK (0x20000000U) #define DMA_EEI_EEI29_SHIFT (29U) /*! EEI29 - Enable Error Interrupt 29 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK) #define DMA_EEI_EEI30_MASK (0x40000000U) #define DMA_EEI_EEI30_SHIFT (30U) /*! EEI30 - Enable Error Interrupt 30 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK) #define DMA_EEI_EEI31_MASK (0x80000000U) #define DMA_EEI_EEI31_SHIFT (31U) /*! EEI31 - Enable Error Interrupt 31 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK) /*! @} */ /*! @name CEEI - Clear Enable Error Interrupt Register */ /*! @{ */ #define DMA_CEEI_CEEI_MASK (0x1FU) #define DMA_CEEI_CEEI_SHIFT (0U) /*! CEEI - Clear Enable Error Interrupt */ #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) #define DMA_CEEI_CAEE_MASK (0x40U) #define DMA_CEEI_CAEE_SHIFT (6U) /*! CAEE - Clear All Enable Error Interrupts * 0b0..Clear only the EEI bit specified in the CEEI field * 0b1..Clear all bits in EEI */ #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) #define DMA_CEEI_NOP_MASK (0x80U) #define DMA_CEEI_NOP_SHIFT (7U) /*! NOP - No Op enable * 0b0..Normal operation * 0b1..No operation, ignore the other bits in this register */ #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) /*! @} */ /*! @name SEEI - Set Enable Error Interrupt Register */ /*! @{ */ #define DMA_SEEI_SEEI_MASK (0x1FU) #define DMA_SEEI_SEEI_SHIFT (0U) /*! SEEI - Set Enable Error Interrupt */ #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) #define DMA_SEEI_SAEE_MASK (0x40U) #define DMA_SEEI_SAEE_SHIFT (6U) /*! SAEE - Sets All Enable Error Interrupts * 0b0..Set only the EEI bit specified in the SEEI field. * 0b1..Sets all bits in EEI */ #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) #define DMA_SEEI_NOP_MASK (0x80U) #define DMA_SEEI_NOP_SHIFT (7U) /*! NOP - No Op enable * 0b0..Normal operation * 0b1..No operation, ignore the other bits in this register */ #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) /*! @} */ /*! @name CERQ - Clear Enable Request Register */ /*! @{ */ #define DMA_CERQ_CERQ_MASK (0x1FU) #define DMA_CERQ_CERQ_SHIFT (0U) /*! CERQ - Clear Enable Request */ #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) #define DMA_CERQ_CAER_MASK (0x40U) #define DMA_CERQ_CAER_SHIFT (6U) /*! CAER - Clear All Enable Requests * 0b0..Clear only the ERQ bit specified in the CERQ field * 0b1..Clear all bits in ERQ */ #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) #define DMA_CERQ_NOP_MASK (0x80U) #define DMA_CERQ_NOP_SHIFT (7U) /*! NOP - No Op enable * 0b0..Normal operation * 0b1..No operation, ignore the other bits in this register */ #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) /*! @} */ /*! @name SERQ - Set Enable Request Register */ /*! @{ */ #define DMA_SERQ_SERQ_MASK (0x1FU) #define DMA_SERQ_SERQ_SHIFT (0U) /*! SERQ - Set Enable Request */ #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) #define DMA_SERQ_SAER_MASK (0x40U) #define DMA_SERQ_SAER_SHIFT (6U) /*! SAER - Set All Enable Requests * 0b0..Set only the ERQ bit specified in the SERQ field * 0b1..Set all bits in ERQ */ #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) #define DMA_SERQ_NOP_MASK (0x80U) #define DMA_SERQ_NOP_SHIFT (7U) /*! NOP - No Op enable * 0b0..Normal operation * 0b1..No operation, ignore the other bits in this register */ #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) /*! @} */ /*! @name CDNE - Clear DONE Status Bit Register */ /*! @{ */ #define DMA_CDNE_CDNE_MASK (0x1FU) #define DMA_CDNE_CDNE_SHIFT (0U) /*! CDNE - Clear DONE Bit */ #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) #define DMA_CDNE_CADN_MASK (0x40U) #define DMA_CDNE_CADN_SHIFT (6U) /*! CADN - Clears All DONE Bits * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field * 0b1..Clears all bits in TCDn_CSR[DONE] */ #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) #define DMA_CDNE_NOP_MASK (0x80U) #define DMA_CDNE_NOP_SHIFT (7U) /*! NOP - No Op enable * 0b0..Normal operation * 0b1..No operation, ignore the other bits in this register */ #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) /*! @} */ /*! @name SSRT - Set START Bit Register */ /*! @{ */ #define DMA_SSRT_SSRT_MASK (0x1FU) #define DMA_SSRT_SSRT_SHIFT (0U) /*! SSRT - Set START Bit */ #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) #define DMA_SSRT_SAST_MASK (0x40U) #define DMA_SSRT_SAST_SHIFT (6U) /*! SAST - Set All START Bits (activates all channels) * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field * 0b1..Set all bits in TCDn_CSR[START] */ #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) #define DMA_SSRT_NOP_MASK (0x80U) #define DMA_SSRT_NOP_SHIFT (7U) /*! NOP - No Op enable * 0b0..Normal operation * 0b1..No operation, ignore the other bits in this register */ #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) /*! @} */ /*! @name CERR - Clear Error Register */ /*! @{ */ #define DMA_CERR_CERR_MASK (0x1FU) #define DMA_CERR_CERR_SHIFT (0U) /*! CERR - Clear Error Indicator */ #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) #define DMA_CERR_CAEI_MASK (0x40U) #define DMA_CERR_CAEI_SHIFT (6U) /*! CAEI - Clear All Error Indicators * 0b0..Clear only the ERR bit specified in the CERR field * 0b1..Clear all bits in ERR */ #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) #define DMA_CERR_NOP_MASK (0x80U) #define DMA_CERR_NOP_SHIFT (7U) /*! NOP - No Op enable * 0b0..Normal operation * 0b1..No operation, ignore the other bits in this register */ #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) /*! @} */ /*! @name CINT - Clear Interrupt Request Register */ /*! @{ */ #define DMA_CINT_CINT_MASK (0x1FU) #define DMA_CINT_CINT_SHIFT (0U) /*! CINT - Clear Interrupt Request */ #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) #define DMA_CINT_CAIR_MASK (0x40U) #define DMA_CINT_CAIR_SHIFT (6U) /*! CAIR - Clear All Interrupt Requests * 0b0..Clear only the INT bit specified in the CINT field * 0b1..Clear all bits in INT */ #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) #define DMA_CINT_NOP_MASK (0x80U) #define DMA_CINT_NOP_SHIFT (7U) /*! NOP - No Op enable * 0b0..Normal operation * 0b1..No operation, ignore the other bits in this register */ #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) /*! @} */ /*! @name INT - Interrupt Request Register */ /*! @{ */ #define DMA_INT_INT0_MASK (0x1U) #define DMA_INT_INT0_SHIFT (0U) /*! INT0 - Interrupt Request 0 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) #define DMA_INT_INT1_MASK (0x2U) #define DMA_INT_INT1_SHIFT (1U) /*! INT1 - Interrupt Request 1 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) #define DMA_INT_INT2_MASK (0x4U) #define DMA_INT_INT2_SHIFT (2U) /*! INT2 - Interrupt Request 2 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) #define DMA_INT_INT3_MASK (0x8U) #define DMA_INT_INT3_SHIFT (3U) /*! INT3 - Interrupt Request 3 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) #define DMA_INT_INT4_MASK (0x10U) #define DMA_INT_INT4_SHIFT (4U) /*! INT4 - Interrupt Request 4 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) #define DMA_INT_INT5_MASK (0x20U) #define DMA_INT_INT5_SHIFT (5U) /*! INT5 - Interrupt Request 5 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) #define DMA_INT_INT6_MASK (0x40U) #define DMA_INT_INT6_SHIFT (6U) /*! INT6 - Interrupt Request 6 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) #define DMA_INT_INT7_MASK (0x80U) #define DMA_INT_INT7_SHIFT (7U) /*! INT7 - Interrupt Request 7 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) #define DMA_INT_INT8_MASK (0x100U) #define DMA_INT_INT8_SHIFT (8U) /*! INT8 - Interrupt Request 8 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) #define DMA_INT_INT9_MASK (0x200U) #define DMA_INT_INT9_SHIFT (9U) /*! INT9 - Interrupt Request 9 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) #define DMA_INT_INT10_MASK (0x400U) #define DMA_INT_INT10_SHIFT (10U) /*! INT10 - Interrupt Request 10 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) #define DMA_INT_INT11_MASK (0x800U) #define DMA_INT_INT11_SHIFT (11U) /*! INT11 - Interrupt Request 11 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) #define DMA_INT_INT12_MASK (0x1000U) #define DMA_INT_INT12_SHIFT (12U) /*! INT12 - Interrupt Request 12 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) #define DMA_INT_INT13_MASK (0x2000U) #define DMA_INT_INT13_SHIFT (13U) /*! INT13 - Interrupt Request 13 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) #define DMA_INT_INT14_MASK (0x4000U) #define DMA_INT_INT14_SHIFT (14U) /*! INT14 - Interrupt Request 14 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) #define DMA_INT_INT15_MASK (0x8000U) #define DMA_INT_INT15_SHIFT (15U) /*! INT15 - Interrupt Request 15 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) #define DMA_INT_INT16_MASK (0x10000U) #define DMA_INT_INT16_SHIFT (16U) /*! INT16 - Interrupt Request 16 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK) #define DMA_INT_INT17_MASK (0x20000U) #define DMA_INT_INT17_SHIFT (17U) /*! INT17 - Interrupt Request 17 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK) #define DMA_INT_INT18_MASK (0x40000U) #define DMA_INT_INT18_SHIFT (18U) /*! INT18 - Interrupt Request 18 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK) #define DMA_INT_INT19_MASK (0x80000U) #define DMA_INT_INT19_SHIFT (19U) /*! INT19 - Interrupt Request 19 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK) #define DMA_INT_INT20_MASK (0x100000U) #define DMA_INT_INT20_SHIFT (20U) /*! INT20 - Interrupt Request 20 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK) #define DMA_INT_INT21_MASK (0x200000U) #define DMA_INT_INT21_SHIFT (21U) /*! INT21 - Interrupt Request 21 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK) #define DMA_INT_INT22_MASK (0x400000U) #define DMA_INT_INT22_SHIFT (22U) /*! INT22 - Interrupt Request 22 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK) #define DMA_INT_INT23_MASK (0x800000U) #define DMA_INT_INT23_SHIFT (23U) /*! INT23 - Interrupt Request 23 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK) #define DMA_INT_INT24_MASK (0x1000000U) #define DMA_INT_INT24_SHIFT (24U) /*! INT24 - Interrupt Request 24 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK) #define DMA_INT_INT25_MASK (0x2000000U) #define DMA_INT_INT25_SHIFT (25U) /*! INT25 - Interrupt Request 25 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK) #define DMA_INT_INT26_MASK (0x4000000U) #define DMA_INT_INT26_SHIFT (26U) /*! INT26 - Interrupt Request 26 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK) #define DMA_INT_INT27_MASK (0x8000000U) #define DMA_INT_INT27_SHIFT (27U) /*! INT27 - Interrupt Request 27 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK) #define DMA_INT_INT28_MASK (0x10000000U) #define DMA_INT_INT28_SHIFT (28U) /*! INT28 - Interrupt Request 28 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK) #define DMA_INT_INT29_MASK (0x20000000U) #define DMA_INT_INT29_SHIFT (29U) /*! INT29 - Interrupt Request 29 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK) #define DMA_INT_INT30_MASK (0x40000000U) #define DMA_INT_INT30_SHIFT (30U) /*! INT30 - Interrupt Request 30 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK) #define DMA_INT_INT31_MASK (0x80000000U) #define DMA_INT_INT31_SHIFT (31U) /*! INT31 - Interrupt Request 31 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK) /*! @} */ /*! @name ERR - Error Register */ /*! @{ */ #define DMA_ERR_ERR0_MASK (0x1U) #define DMA_ERR_ERR0_SHIFT (0U) /*! ERR0 - Error In Channel 0 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) #define DMA_ERR_ERR1_MASK (0x2U) #define DMA_ERR_ERR1_SHIFT (1U) /*! ERR1 - Error In Channel 1 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) #define DMA_ERR_ERR2_MASK (0x4U) #define DMA_ERR_ERR2_SHIFT (2U) /*! ERR2 - Error In Channel 2 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) #define DMA_ERR_ERR3_MASK (0x8U) #define DMA_ERR_ERR3_SHIFT (3U) /*! ERR3 - Error In Channel 3 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) #define DMA_ERR_ERR4_MASK (0x10U) #define DMA_ERR_ERR4_SHIFT (4U) /*! ERR4 - Error In Channel 4 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) #define DMA_ERR_ERR5_MASK (0x20U) #define DMA_ERR_ERR5_SHIFT (5U) /*! ERR5 - Error In Channel 5 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) #define DMA_ERR_ERR6_MASK (0x40U) #define DMA_ERR_ERR6_SHIFT (6U) /*! ERR6 - Error In Channel 6 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) #define DMA_ERR_ERR7_MASK (0x80U) #define DMA_ERR_ERR7_SHIFT (7U) /*! ERR7 - Error In Channel 7 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) #define DMA_ERR_ERR8_MASK (0x100U) #define DMA_ERR_ERR8_SHIFT (8U) /*! ERR8 - Error In Channel 8 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) #define DMA_ERR_ERR9_MASK (0x200U) #define DMA_ERR_ERR9_SHIFT (9U) /*! ERR9 - Error In Channel 9 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) #define DMA_ERR_ERR10_MASK (0x400U) #define DMA_ERR_ERR10_SHIFT (10U) /*! ERR10 - Error In Channel 10 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) #define DMA_ERR_ERR11_MASK (0x800U) #define DMA_ERR_ERR11_SHIFT (11U) /*! ERR11 - Error In Channel 11 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) #define DMA_ERR_ERR12_MASK (0x1000U) #define DMA_ERR_ERR12_SHIFT (12U) /*! ERR12 - Error In Channel 12 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) #define DMA_ERR_ERR13_MASK (0x2000U) #define DMA_ERR_ERR13_SHIFT (13U) /*! ERR13 - Error In Channel 13 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) #define DMA_ERR_ERR14_MASK (0x4000U) #define DMA_ERR_ERR14_SHIFT (14U) /*! ERR14 - Error In Channel 14 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) #define DMA_ERR_ERR15_MASK (0x8000U) #define DMA_ERR_ERR15_SHIFT (15U) /*! ERR15 - Error In Channel 15 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) #define DMA_ERR_ERR16_MASK (0x10000U) #define DMA_ERR_ERR16_SHIFT (16U) /*! ERR16 - Error In Channel 16 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK) #define DMA_ERR_ERR17_MASK (0x20000U) #define DMA_ERR_ERR17_SHIFT (17U) /*! ERR17 - Error In Channel 17 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK) #define DMA_ERR_ERR18_MASK (0x40000U) #define DMA_ERR_ERR18_SHIFT (18U) /*! ERR18 - Error In Channel 18 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK) #define DMA_ERR_ERR19_MASK (0x80000U) #define DMA_ERR_ERR19_SHIFT (19U) /*! ERR19 - Error In Channel 19 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK) #define DMA_ERR_ERR20_MASK (0x100000U) #define DMA_ERR_ERR20_SHIFT (20U) /*! ERR20 - Error In Channel 20 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK) #define DMA_ERR_ERR21_MASK (0x200000U) #define DMA_ERR_ERR21_SHIFT (21U) /*! ERR21 - Error In Channel 21 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK) #define DMA_ERR_ERR22_MASK (0x400000U) #define DMA_ERR_ERR22_SHIFT (22U) /*! ERR22 - Error In Channel 22 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK) #define DMA_ERR_ERR23_MASK (0x800000U) #define DMA_ERR_ERR23_SHIFT (23U) /*! ERR23 - Error In Channel 23 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK) #define DMA_ERR_ERR24_MASK (0x1000000U) #define DMA_ERR_ERR24_SHIFT (24U) /*! ERR24 - Error In Channel 24 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK) #define DMA_ERR_ERR25_MASK (0x2000000U) #define DMA_ERR_ERR25_SHIFT (25U) /*! ERR25 - Error In Channel 25 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK) #define DMA_ERR_ERR26_MASK (0x4000000U) #define DMA_ERR_ERR26_SHIFT (26U) /*! ERR26 - Error In Channel 26 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK) #define DMA_ERR_ERR27_MASK (0x8000000U) #define DMA_ERR_ERR27_SHIFT (27U) /*! ERR27 - Error In Channel 27 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK) #define DMA_ERR_ERR28_MASK (0x10000000U) #define DMA_ERR_ERR28_SHIFT (28U) /*! ERR28 - Error In Channel 28 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK) #define DMA_ERR_ERR29_MASK (0x20000000U) #define DMA_ERR_ERR29_SHIFT (29U) /*! ERR29 - Error In Channel 29 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK) #define DMA_ERR_ERR30_MASK (0x40000000U) #define DMA_ERR_ERR30_SHIFT (30U) /*! ERR30 - Error In Channel 30 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK) #define DMA_ERR_ERR31_MASK (0x80000000U) #define DMA_ERR_ERR31_SHIFT (31U) /*! ERR31 - Error In Channel 31 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK) /*! @} */ /*! @name HRS - Hardware Request Status Register */ /*! @{ */ #define DMA_HRS_HRS0_MASK (0x1U) #define DMA_HRS_HRS0_SHIFT (0U) /*! HRS0 - Hardware Request Status Channel 0 * 0b0..A hardware service request for channel 0 is not present * 0b1..A hardware service request for channel 0 is present */ #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) #define DMA_HRS_HRS1_MASK (0x2U) #define DMA_HRS_HRS1_SHIFT (1U) /*! HRS1 - Hardware Request Status Channel 1 * 0b0..A hardware service request for channel 1 is not present * 0b1..A hardware service request for channel 1 is present */ #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) #define DMA_HRS_HRS2_MASK (0x4U) #define DMA_HRS_HRS2_SHIFT (2U) /*! HRS2 - Hardware Request Status Channel 2 * 0b0..A hardware service request for channel 2 is not present * 0b1..A hardware service request for channel 2 is present */ #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) #define DMA_HRS_HRS3_MASK (0x8U) #define DMA_HRS_HRS3_SHIFT (3U) /*! HRS3 - Hardware Request Status Channel 3 * 0b0..A hardware service request for channel 3 is not present * 0b1..A hardware service request for channel 3 is present */ #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) #define DMA_HRS_HRS4_MASK (0x10U) #define DMA_HRS_HRS4_SHIFT (4U) /*! HRS4 - Hardware Request Status Channel 4 * 0b0..A hardware service request for channel 4 is not present * 0b1..A hardware service request for channel 4 is present */ #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) #define DMA_HRS_HRS5_MASK (0x20U) #define DMA_HRS_HRS5_SHIFT (5U) /*! HRS5 - Hardware Request Status Channel 5 * 0b0..A hardware service request for channel 5 is not present * 0b1..A hardware service request for channel 5 is present */ #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) #define DMA_HRS_HRS6_MASK (0x40U) #define DMA_HRS_HRS6_SHIFT (6U) /*! HRS6 - Hardware Request Status Channel 6 * 0b0..A hardware service request for channel 6 is not present * 0b1..A hardware service request for channel 6 is present */ #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) #define DMA_HRS_HRS7_MASK (0x80U) #define DMA_HRS_HRS7_SHIFT (7U) /*! HRS7 - Hardware Request Status Channel 7 * 0b0..A hardware service request for channel 7 is not present * 0b1..A hardware service request for channel 7 is present */ #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) #define DMA_HRS_HRS8_MASK (0x100U) #define DMA_HRS_HRS8_SHIFT (8U) /*! HRS8 - Hardware Request Status Channel 8 * 0b0..A hardware service request for channel 8 is not present * 0b1..A hardware service request for channel 8 is present */ #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) #define DMA_HRS_HRS9_MASK (0x200U) #define DMA_HRS_HRS9_SHIFT (9U) /*! HRS9 - Hardware Request Status Channel 9 * 0b0..A hardware service request for channel 9 is not present * 0b1..A hardware service request for channel 9 is present */ #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) #define DMA_HRS_HRS10_MASK (0x400U) #define DMA_HRS_HRS10_SHIFT (10U) /*! HRS10 - Hardware Request Status Channel 10 * 0b0..A hardware service request for channel 10 is not present * 0b1..A hardware service request for channel 10 is present */ #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) #define DMA_HRS_HRS11_MASK (0x800U) #define DMA_HRS_HRS11_SHIFT (11U) /*! HRS11 - Hardware Request Status Channel 11 * 0b0..A hardware service request for channel 11 is not present * 0b1..A hardware service request for channel 11 is present */ #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) #define DMA_HRS_HRS12_MASK (0x1000U) #define DMA_HRS_HRS12_SHIFT (12U) /*! HRS12 - Hardware Request Status Channel 12 * 0b0..A hardware service request for channel 12 is not present * 0b1..A hardware service request for channel 12 is present */ #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) #define DMA_HRS_HRS13_MASK (0x2000U) #define DMA_HRS_HRS13_SHIFT (13U) /*! HRS13 - Hardware Request Status Channel 13 * 0b0..A hardware service request for channel 13 is not present * 0b1..A hardware service request for channel 13 is present */ #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) #define DMA_HRS_HRS14_MASK (0x4000U) #define DMA_HRS_HRS14_SHIFT (14U) /*! HRS14 - Hardware Request Status Channel 14 * 0b0..A hardware service request for channel 14 is not present * 0b1..A hardware service request for channel 14 is present */ #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) #define DMA_HRS_HRS15_MASK (0x8000U) #define DMA_HRS_HRS15_SHIFT (15U) /*! HRS15 - Hardware Request Status Channel 15 * 0b0..A hardware service request for channel 15 is not present * 0b1..A hardware service request for channel 15 is present */ #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) #define DMA_HRS_HRS16_MASK (0x10000U) #define DMA_HRS_HRS16_SHIFT (16U) /*! HRS16 - Hardware Request Status Channel 16 * 0b0..A hardware service request for channel 16 is not present * 0b1..A hardware service request for channel 16 is present */ #define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK) #define DMA_HRS_HRS17_MASK (0x20000U) #define DMA_HRS_HRS17_SHIFT (17U) /*! HRS17 - Hardware Request Status Channel 17 * 0b0..A hardware service request for channel 17 is not present * 0b1..A hardware service request for channel 17 is present */ #define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK) #define DMA_HRS_HRS18_MASK (0x40000U) #define DMA_HRS_HRS18_SHIFT (18U) /*! HRS18 - Hardware Request Status Channel 18 * 0b0..A hardware service request for channel 18 is not present * 0b1..A hardware service request for channel 18 is present */ #define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK) #define DMA_HRS_HRS19_MASK (0x80000U) #define DMA_HRS_HRS19_SHIFT (19U) /*! HRS19 - Hardware Request Status Channel 19 * 0b0..A hardware service request for channel 19 is not present * 0b1..A hardware service request for channel 19 is present */ #define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK) #define DMA_HRS_HRS20_MASK (0x100000U) #define DMA_HRS_HRS20_SHIFT (20U) /*! HRS20 - Hardware Request Status Channel 20 * 0b0..A hardware service request for channel 20 is not present * 0b1..A hardware service request for channel 20 is present */ #define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK) #define DMA_HRS_HRS21_MASK (0x200000U) #define DMA_HRS_HRS21_SHIFT (21U) /*! HRS21 - Hardware Request Status Channel 21 * 0b0..A hardware service request for channel 21 is not present * 0b1..A hardware service request for channel 21 is present */ #define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK) #define DMA_HRS_HRS22_MASK (0x400000U) #define DMA_HRS_HRS22_SHIFT (22U) /*! HRS22 - Hardware Request Status Channel 22 * 0b0..A hardware service request for channel 22 is not present * 0b1..A hardware service request for channel 22 is present */ #define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK) #define DMA_HRS_HRS23_MASK (0x800000U) #define DMA_HRS_HRS23_SHIFT (23U) /*! HRS23 - Hardware Request Status Channel 23 * 0b0..A hardware service request for channel 23 is not present * 0b1..A hardware service request for channel 23 is present */ #define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK) #define DMA_HRS_HRS24_MASK (0x1000000U) #define DMA_HRS_HRS24_SHIFT (24U) /*! HRS24 - Hardware Request Status Channel 24 * 0b0..A hardware service request for channel 24 is not present * 0b1..A hardware service request for channel 24 is present */ #define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK) #define DMA_HRS_HRS25_MASK (0x2000000U) #define DMA_HRS_HRS25_SHIFT (25U) /*! HRS25 - Hardware Request Status Channel 25 * 0b0..A hardware service request for channel 25 is not present * 0b1..A hardware service request for channel 25 is present */ #define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK) #define DMA_HRS_HRS26_MASK (0x4000000U) #define DMA_HRS_HRS26_SHIFT (26U) /*! HRS26 - Hardware Request Status Channel 26 * 0b0..A hardware service request for channel 26 is not present * 0b1..A hardware service request for channel 26 is present */ #define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK) #define DMA_HRS_HRS27_MASK (0x8000000U) #define DMA_HRS_HRS27_SHIFT (27U) /*! HRS27 - Hardware Request Status Channel 27 * 0b0..A hardware service request for channel 27 is not present * 0b1..A hardware service request for channel 27 is present */ #define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK) #define DMA_HRS_HRS28_MASK (0x10000000U) #define DMA_HRS_HRS28_SHIFT (28U) /*! HRS28 - Hardware Request Status Channel 28 * 0b0..A hardware service request for channel 28 is not present * 0b1..A hardware service request for channel 28 is present */ #define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK) #define DMA_HRS_HRS29_MASK (0x20000000U) #define DMA_HRS_HRS29_SHIFT (29U) /*! HRS29 - Hardware Request Status Channel 29 * 0b0..A hardware service request for channel 29 is not preset * 0b1..A hardware service request for channel 29 is present */ #define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK) #define DMA_HRS_HRS30_MASK (0x40000000U) #define DMA_HRS_HRS30_SHIFT (30U) /*! HRS30 - Hardware Request Status Channel 30 * 0b0..A hardware service request for channel 30 is not present * 0b1..A hardware service request for channel 30 is present */ #define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK) #define DMA_HRS_HRS31_MASK (0x80000000U) #define DMA_HRS_HRS31_SHIFT (31U) /*! HRS31 - Hardware Request Status Channel 31 * 0b0..A hardware service request for channel 31 is not present * 0b1..A hardware service request for channel 31 is present */ #define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK) /*! @} */ /*! @name EARS - Enable Asynchronous Request in Stop Register */ /*! @{ */ #define DMA_EARS_EDREQ_0_MASK (0x1U) #define DMA_EARS_EDREQ_0_SHIFT (0U) /*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. * 0b0..Disable asynchronous DMA request for channel 0. * 0b1..Enable asynchronous DMA request for channel 0. */ #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) #define DMA_EARS_EDREQ_1_MASK (0x2U) #define DMA_EARS_EDREQ_1_SHIFT (1U) /*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. * 0b0..Disable asynchronous DMA request for channel 1 * 0b1..Enable asynchronous DMA request for channel 1. */ #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) #define DMA_EARS_EDREQ_2_MASK (0x4U) #define DMA_EARS_EDREQ_2_SHIFT (2U) /*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. * 0b0..Disable asynchronous DMA request for channel 2. * 0b1..Enable asynchronous DMA request for channel 2. */ #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) #define DMA_EARS_EDREQ_3_MASK (0x8U) #define DMA_EARS_EDREQ_3_SHIFT (3U) /*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. * 0b0..Disable asynchronous DMA request for channel 3. * 0b1..Enable asynchronous DMA request for channel 3. */ #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) #define DMA_EARS_EDREQ_4_MASK (0x10U) #define DMA_EARS_EDREQ_4_SHIFT (4U) /*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4 * 0b0..Disable asynchronous DMA request for channel 4. * 0b1..Enable asynchronous DMA request for channel 4. */ #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) #define DMA_EARS_EDREQ_5_MASK (0x20U) #define DMA_EARS_EDREQ_5_SHIFT (5U) /*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5 * 0b0..Disable asynchronous DMA request for channel 5. * 0b1..Enable asynchronous DMA request for channel 5. */ #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) #define DMA_EARS_EDREQ_6_MASK (0x40U) #define DMA_EARS_EDREQ_6_SHIFT (6U) /*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6 * 0b0..Disable asynchronous DMA request for channel 6. * 0b1..Enable asynchronous DMA request for channel 6. */ #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) #define DMA_EARS_EDREQ_7_MASK (0x80U) #define DMA_EARS_EDREQ_7_SHIFT (7U) /*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7 * 0b0..Disable asynchronous DMA request for channel 7. * 0b1..Enable asynchronous DMA request for channel 7. */ #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) #define DMA_EARS_EDREQ_8_MASK (0x100U) #define DMA_EARS_EDREQ_8_SHIFT (8U) /*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8 * 0b0..Disable asynchronous DMA request for channel 8. * 0b1..Enable asynchronous DMA request for channel 8. */ #define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) #define DMA_EARS_EDREQ_9_MASK (0x200U) #define DMA_EARS_EDREQ_9_SHIFT (9U) /*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9 * 0b0..Disable asynchronous DMA request for channel 9. * 0b1..Enable asynchronous DMA request for channel 9. */ #define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) #define DMA_EARS_EDREQ_10_MASK (0x400U) #define DMA_EARS_EDREQ_10_SHIFT (10U) /*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10 * 0b0..Disable asynchronous DMA request for channel 10. * 0b1..Enable asynchronous DMA request for channel 10. */ #define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) #define DMA_EARS_EDREQ_11_MASK (0x800U) #define DMA_EARS_EDREQ_11_SHIFT (11U) /*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11 * 0b0..Disable asynchronous DMA request for channel 11. * 0b1..Enable asynchronous DMA request for channel 11. */ #define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) #define DMA_EARS_EDREQ_12_MASK (0x1000U) #define DMA_EARS_EDREQ_12_SHIFT (12U) /*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12 * 0b0..Disable asynchronous DMA request for channel 12. * 0b1..Enable asynchronous DMA request for channel 12. */ #define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) #define DMA_EARS_EDREQ_13_MASK (0x2000U) #define DMA_EARS_EDREQ_13_SHIFT (13U) /*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13 * 0b0..Disable asynchronous DMA request for channel 13. * 0b1..Enable asynchronous DMA request for channel 13. */ #define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) #define DMA_EARS_EDREQ_14_MASK (0x4000U) #define DMA_EARS_EDREQ_14_SHIFT (14U) /*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14 * 0b0..Disable asynchronous DMA request for channel 14. * 0b1..Enable asynchronous DMA request for channel 14. */ #define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) #define DMA_EARS_EDREQ_15_MASK (0x8000U) #define DMA_EARS_EDREQ_15_SHIFT (15U) /*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15 * 0b0..Disable asynchronous DMA request for channel 15. * 0b1..Enable asynchronous DMA request for channel 15. */ #define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) #define DMA_EARS_EDREQ_16_MASK (0x10000U) #define DMA_EARS_EDREQ_16_SHIFT (16U) /*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16 * 0b0..Disable asynchronous DMA request for channel 16 * 0b1..Enable asynchronous DMA request for channel 16 */ #define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK) #define DMA_EARS_EDREQ_17_MASK (0x20000U) #define DMA_EARS_EDREQ_17_SHIFT (17U) /*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17 * 0b0..Disable asynchronous DMA request for channel 17 * 0b1..Enable asynchronous DMA request for channel 17 */ #define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK) #define DMA_EARS_EDREQ_18_MASK (0x40000U) #define DMA_EARS_EDREQ_18_SHIFT (18U) /*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18 * 0b0..Disable asynchronous DMA request for channel 18 * 0b1..Enable asynchronous DMA request for channel 18 */ #define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK) #define DMA_EARS_EDREQ_19_MASK (0x80000U) #define DMA_EARS_EDREQ_19_SHIFT (19U) /*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19 * 0b0..Disable asynchronous DMA request for channel 19 * 0b1..Enable asynchronous DMA request for channel 19 */ #define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK) #define DMA_EARS_EDREQ_20_MASK (0x100000U) #define DMA_EARS_EDREQ_20_SHIFT (20U) /*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20 * 0b0..Disable asynchronous DMA request for channel 20 * 0b1..Enable asynchronous DMA request for channel 20 */ #define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK) #define DMA_EARS_EDREQ_21_MASK (0x200000U) #define DMA_EARS_EDREQ_21_SHIFT (21U) /*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21 * 0b0..Disable asynchronous DMA request for channel 21 * 0b1..Enable asynchronous DMA request for channel 21 */ #define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK) #define DMA_EARS_EDREQ_22_MASK (0x400000U) #define DMA_EARS_EDREQ_22_SHIFT (22U) /*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22 * 0b0..Disable asynchronous DMA request for channel 22 * 0b1..Enable asynchronous DMA request for channel 22 */ #define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK) #define DMA_EARS_EDREQ_23_MASK (0x800000U) #define DMA_EARS_EDREQ_23_SHIFT (23U) /*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23 * 0b0..Disable asynchronous DMA request for channel 23 * 0b1..Enable asynchronous DMA request for channel 23 */ #define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK) #define DMA_EARS_EDREQ_24_MASK (0x1000000U) #define DMA_EARS_EDREQ_24_SHIFT (24U) /*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24 * 0b0..Disable asynchronous DMA request for channel 24 * 0b1..Enable asynchronous DMA request for channel 24 */ #define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK) #define DMA_EARS_EDREQ_25_MASK (0x2000000U) #define DMA_EARS_EDREQ_25_SHIFT (25U) /*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25 * 0b0..Disable asynchronous DMA request for channel 25 * 0b1..Enable asynchronous DMA request for channel 25 */ #define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK) #define DMA_EARS_EDREQ_26_MASK (0x4000000U) #define DMA_EARS_EDREQ_26_SHIFT (26U) /*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26 * 0b0..Disable asynchronous DMA request for channel 26 * 0b1..Enable asynchronous DMA request for channel 26 */ #define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK) #define DMA_EARS_EDREQ_27_MASK (0x8000000U) #define DMA_EARS_EDREQ_27_SHIFT (27U) /*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27 * 0b0..Disable asynchronous DMA request for channel 27 * 0b1..Enable asynchronous DMA request for channel 27 */ #define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK) #define DMA_EARS_EDREQ_28_MASK (0x10000000U) #define DMA_EARS_EDREQ_28_SHIFT (28U) /*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28 * 0b0..Disable asynchronous DMA request for channel 28 * 0b1..Enable asynchronous DMA request for channel 28 */ #define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK) #define DMA_EARS_EDREQ_29_MASK (0x20000000U) #define DMA_EARS_EDREQ_29_SHIFT (29U) /*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29 * 0b0..Disable asynchronous DMA request for channel 29 * 0b1..Enable asynchronous DMA request for channel 29 */ #define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK) #define DMA_EARS_EDREQ_30_MASK (0x40000000U) #define DMA_EARS_EDREQ_30_SHIFT (30U) /*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30 * 0b0..Disable asynchronous DMA request for channel 30 * 0b1..Enable asynchronous DMA request for channel 30 */ #define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK) #define DMA_EARS_EDREQ_31_MASK (0x80000000U) #define DMA_EARS_EDREQ_31_SHIFT (31U) /*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31 * 0b0..Disable asynchronous DMA request for channel 31 * 0b1..Enable asynchronous DMA request for channel 31 */ #define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK) /*! @} */ /*! @name DCHPRI3 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI3_CHPRI_MASK (0xFU) #define DMA_DCHPRI3_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) #define DMA_DCHPRI3_GRPPRI_MASK (0x30U) #define DMA_DCHPRI3_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK) #define DMA_DCHPRI3_DPA_MASK (0x40U) #define DMA_DCHPRI3_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) #define DMA_DCHPRI3_ECP_MASK (0x80U) #define DMA_DCHPRI3_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) /*! @} */ /*! @name DCHPRI2 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI2_CHPRI_MASK (0xFU) #define DMA_DCHPRI2_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) #define DMA_DCHPRI2_GRPPRI_MASK (0x30U) #define DMA_DCHPRI2_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK) #define DMA_DCHPRI2_DPA_MASK (0x40U) #define DMA_DCHPRI2_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) #define DMA_DCHPRI2_ECP_MASK (0x80U) #define DMA_DCHPRI2_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) /*! @} */ /*! @name DCHPRI1 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI1_CHPRI_MASK (0xFU) #define DMA_DCHPRI1_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) #define DMA_DCHPRI1_GRPPRI_MASK (0x30U) #define DMA_DCHPRI1_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK) #define DMA_DCHPRI1_DPA_MASK (0x40U) #define DMA_DCHPRI1_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) #define DMA_DCHPRI1_ECP_MASK (0x80U) #define DMA_DCHPRI1_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) /*! @} */ /*! @name DCHPRI0 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI0_CHPRI_MASK (0xFU) #define DMA_DCHPRI0_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) #define DMA_DCHPRI0_GRPPRI_MASK (0x30U) #define DMA_DCHPRI0_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK) #define DMA_DCHPRI0_DPA_MASK (0x40U) #define DMA_DCHPRI0_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) #define DMA_DCHPRI0_ECP_MASK (0x80U) #define DMA_DCHPRI0_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) /*! @} */ /*! @name DCHPRI7 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI7_CHPRI_MASK (0xFU) #define DMA_DCHPRI7_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) #define DMA_DCHPRI7_GRPPRI_MASK (0x30U) #define DMA_DCHPRI7_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK) #define DMA_DCHPRI7_DPA_MASK (0x40U) #define DMA_DCHPRI7_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) #define DMA_DCHPRI7_ECP_MASK (0x80U) #define DMA_DCHPRI7_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) /*! @} */ /*! @name DCHPRI6 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI6_CHPRI_MASK (0xFU) #define DMA_DCHPRI6_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) #define DMA_DCHPRI6_GRPPRI_MASK (0x30U) #define DMA_DCHPRI6_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK) #define DMA_DCHPRI6_DPA_MASK (0x40U) #define DMA_DCHPRI6_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) #define DMA_DCHPRI6_ECP_MASK (0x80U) #define DMA_DCHPRI6_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) /*! @} */ /*! @name DCHPRI5 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI5_CHPRI_MASK (0xFU) #define DMA_DCHPRI5_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) #define DMA_DCHPRI5_GRPPRI_MASK (0x30U) #define DMA_DCHPRI5_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK) #define DMA_DCHPRI5_DPA_MASK (0x40U) #define DMA_DCHPRI5_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) #define DMA_DCHPRI5_ECP_MASK (0x80U) #define DMA_DCHPRI5_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) /*! @} */ /*! @name DCHPRI4 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI4_CHPRI_MASK (0xFU) #define DMA_DCHPRI4_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) #define DMA_DCHPRI4_GRPPRI_MASK (0x30U) #define DMA_DCHPRI4_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK) #define DMA_DCHPRI4_DPA_MASK (0x40U) #define DMA_DCHPRI4_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) #define DMA_DCHPRI4_ECP_MASK (0x80U) #define DMA_DCHPRI4_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) /*! @} */ /*! @name DCHPRI11 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI11_CHPRI_MASK (0xFU) #define DMA_DCHPRI11_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) #define DMA_DCHPRI11_GRPPRI_MASK (0x30U) #define DMA_DCHPRI11_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK) #define DMA_DCHPRI11_DPA_MASK (0x40U) #define DMA_DCHPRI11_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) #define DMA_DCHPRI11_ECP_MASK (0x80U) #define DMA_DCHPRI11_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) /*! @} */ /*! @name DCHPRI10 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI10_CHPRI_MASK (0xFU) #define DMA_DCHPRI10_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) #define DMA_DCHPRI10_GRPPRI_MASK (0x30U) #define DMA_DCHPRI10_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK) #define DMA_DCHPRI10_DPA_MASK (0x40U) #define DMA_DCHPRI10_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) #define DMA_DCHPRI10_ECP_MASK (0x80U) #define DMA_DCHPRI10_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) /*! @} */ /*! @name DCHPRI9 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI9_CHPRI_MASK (0xFU) #define DMA_DCHPRI9_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) #define DMA_DCHPRI9_GRPPRI_MASK (0x30U) #define DMA_DCHPRI9_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK) #define DMA_DCHPRI9_DPA_MASK (0x40U) #define DMA_DCHPRI9_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) #define DMA_DCHPRI9_ECP_MASK (0x80U) #define DMA_DCHPRI9_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) /*! @} */ /*! @name DCHPRI8 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI8_CHPRI_MASK (0xFU) #define DMA_DCHPRI8_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) #define DMA_DCHPRI8_GRPPRI_MASK (0x30U) #define DMA_DCHPRI8_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK) #define DMA_DCHPRI8_DPA_MASK (0x40U) #define DMA_DCHPRI8_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) #define DMA_DCHPRI8_ECP_MASK (0x80U) #define DMA_DCHPRI8_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) /*! @} */ /*! @name DCHPRI15 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI15_CHPRI_MASK (0xFU) #define DMA_DCHPRI15_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) #define DMA_DCHPRI15_GRPPRI_MASK (0x30U) #define DMA_DCHPRI15_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK) #define DMA_DCHPRI15_DPA_MASK (0x40U) #define DMA_DCHPRI15_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) #define DMA_DCHPRI15_ECP_MASK (0x80U) #define DMA_DCHPRI15_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) /*! @} */ /*! @name DCHPRI14 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI14_CHPRI_MASK (0xFU) #define DMA_DCHPRI14_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) #define DMA_DCHPRI14_GRPPRI_MASK (0x30U) #define DMA_DCHPRI14_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK) #define DMA_DCHPRI14_DPA_MASK (0x40U) #define DMA_DCHPRI14_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) #define DMA_DCHPRI14_ECP_MASK (0x80U) #define DMA_DCHPRI14_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) /*! @} */ /*! @name DCHPRI13 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI13_CHPRI_MASK (0xFU) #define DMA_DCHPRI13_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) #define DMA_DCHPRI13_GRPPRI_MASK (0x30U) #define DMA_DCHPRI13_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK) #define DMA_DCHPRI13_DPA_MASK (0x40U) #define DMA_DCHPRI13_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) #define DMA_DCHPRI13_ECP_MASK (0x80U) #define DMA_DCHPRI13_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) /*! @} */ /*! @name DCHPRI12 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI12_CHPRI_MASK (0xFU) #define DMA_DCHPRI12_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) #define DMA_DCHPRI12_GRPPRI_MASK (0x30U) #define DMA_DCHPRI12_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK) #define DMA_DCHPRI12_DPA_MASK (0x40U) #define DMA_DCHPRI12_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) #define DMA_DCHPRI12_ECP_MASK (0x80U) #define DMA_DCHPRI12_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) /*! @} */ /*! @name DCHPRI19 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI19_CHPRI_MASK (0xFU) #define DMA_DCHPRI19_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK) #define DMA_DCHPRI19_GRPPRI_MASK (0x30U) #define DMA_DCHPRI19_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK) #define DMA_DCHPRI19_DPA_MASK (0x40U) #define DMA_DCHPRI19_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK) #define DMA_DCHPRI19_ECP_MASK (0x80U) #define DMA_DCHPRI19_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK) /*! @} */ /*! @name DCHPRI18 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI18_CHPRI_MASK (0xFU) #define DMA_DCHPRI18_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK) #define DMA_DCHPRI18_GRPPRI_MASK (0x30U) #define DMA_DCHPRI18_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK) #define DMA_DCHPRI18_DPA_MASK (0x40U) #define DMA_DCHPRI18_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK) #define DMA_DCHPRI18_ECP_MASK (0x80U) #define DMA_DCHPRI18_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK) /*! @} */ /*! @name DCHPRI17 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI17_CHPRI_MASK (0xFU) #define DMA_DCHPRI17_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK) #define DMA_DCHPRI17_GRPPRI_MASK (0x30U) #define DMA_DCHPRI17_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK) #define DMA_DCHPRI17_DPA_MASK (0x40U) #define DMA_DCHPRI17_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK) #define DMA_DCHPRI17_ECP_MASK (0x80U) #define DMA_DCHPRI17_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK) /*! @} */ /*! @name DCHPRI16 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI16_CHPRI_MASK (0xFU) #define DMA_DCHPRI16_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK) #define DMA_DCHPRI16_GRPPRI_MASK (0x30U) #define DMA_DCHPRI16_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK) #define DMA_DCHPRI16_DPA_MASK (0x40U) #define DMA_DCHPRI16_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK) #define DMA_DCHPRI16_ECP_MASK (0x80U) #define DMA_DCHPRI16_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK) /*! @} */ /*! @name DCHPRI23 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI23_CHPRI_MASK (0xFU) #define DMA_DCHPRI23_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK) #define DMA_DCHPRI23_GRPPRI_MASK (0x30U) #define DMA_DCHPRI23_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK) #define DMA_DCHPRI23_DPA_MASK (0x40U) #define DMA_DCHPRI23_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK) #define DMA_DCHPRI23_ECP_MASK (0x80U) #define DMA_DCHPRI23_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK) /*! @} */ /*! @name DCHPRI22 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI22_CHPRI_MASK (0xFU) #define DMA_DCHPRI22_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK) #define DMA_DCHPRI22_GRPPRI_MASK (0x30U) #define DMA_DCHPRI22_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK) #define DMA_DCHPRI22_DPA_MASK (0x40U) #define DMA_DCHPRI22_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK) #define DMA_DCHPRI22_ECP_MASK (0x80U) #define DMA_DCHPRI22_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK) /*! @} */ /*! @name DCHPRI21 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI21_CHPRI_MASK (0xFU) #define DMA_DCHPRI21_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK) #define DMA_DCHPRI21_GRPPRI_MASK (0x30U) #define DMA_DCHPRI21_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK) #define DMA_DCHPRI21_DPA_MASK (0x40U) #define DMA_DCHPRI21_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK) #define DMA_DCHPRI21_ECP_MASK (0x80U) #define DMA_DCHPRI21_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK) /*! @} */ /*! @name DCHPRI20 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI20_CHPRI_MASK (0xFU) #define DMA_DCHPRI20_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK) #define DMA_DCHPRI20_GRPPRI_MASK (0x30U) #define DMA_DCHPRI20_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK) #define DMA_DCHPRI20_DPA_MASK (0x40U) #define DMA_DCHPRI20_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK) #define DMA_DCHPRI20_ECP_MASK (0x80U) #define DMA_DCHPRI20_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK) /*! @} */ /*! @name DCHPRI27 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI27_CHPRI_MASK (0xFU) #define DMA_DCHPRI27_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK) #define DMA_DCHPRI27_GRPPRI_MASK (0x30U) #define DMA_DCHPRI27_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK) #define DMA_DCHPRI27_DPA_MASK (0x40U) #define DMA_DCHPRI27_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK) #define DMA_DCHPRI27_ECP_MASK (0x80U) #define DMA_DCHPRI27_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK) /*! @} */ /*! @name DCHPRI26 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI26_CHPRI_MASK (0xFU) #define DMA_DCHPRI26_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK) #define DMA_DCHPRI26_GRPPRI_MASK (0x30U) #define DMA_DCHPRI26_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK) #define DMA_DCHPRI26_DPA_MASK (0x40U) #define DMA_DCHPRI26_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK) #define DMA_DCHPRI26_ECP_MASK (0x80U) #define DMA_DCHPRI26_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK) /*! @} */ /*! @name DCHPRI25 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI25_CHPRI_MASK (0xFU) #define DMA_DCHPRI25_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK) #define DMA_DCHPRI25_GRPPRI_MASK (0x30U) #define DMA_DCHPRI25_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK) #define DMA_DCHPRI25_DPA_MASK (0x40U) #define DMA_DCHPRI25_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK) #define DMA_DCHPRI25_ECP_MASK (0x80U) #define DMA_DCHPRI25_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK) /*! @} */ /*! @name DCHPRI24 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI24_CHPRI_MASK (0xFU) #define DMA_DCHPRI24_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK) #define DMA_DCHPRI24_GRPPRI_MASK (0x30U) #define DMA_DCHPRI24_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK) #define DMA_DCHPRI24_DPA_MASK (0x40U) #define DMA_DCHPRI24_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK) #define DMA_DCHPRI24_ECP_MASK (0x80U) #define DMA_DCHPRI24_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK) /*! @} */ /*! @name DCHPRI31 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI31_CHPRI_MASK (0xFU) #define DMA_DCHPRI31_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK) #define DMA_DCHPRI31_GRPPRI_MASK (0x30U) #define DMA_DCHPRI31_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK) #define DMA_DCHPRI31_DPA_MASK (0x40U) #define DMA_DCHPRI31_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK) #define DMA_DCHPRI31_ECP_MASK (0x80U) #define DMA_DCHPRI31_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK) /*! @} */ /*! @name DCHPRI30 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI30_CHPRI_MASK (0xFU) #define DMA_DCHPRI30_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK) #define DMA_DCHPRI30_GRPPRI_MASK (0x30U) #define DMA_DCHPRI30_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK) #define DMA_DCHPRI30_DPA_MASK (0x40U) #define DMA_DCHPRI30_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK) #define DMA_DCHPRI30_ECP_MASK (0x80U) #define DMA_DCHPRI30_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK) /*! @} */ /*! @name DCHPRI29 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI29_CHPRI_MASK (0xFU) #define DMA_DCHPRI29_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK) #define DMA_DCHPRI29_GRPPRI_MASK (0x30U) #define DMA_DCHPRI29_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK) #define DMA_DCHPRI29_DPA_MASK (0x40U) #define DMA_DCHPRI29_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK) #define DMA_DCHPRI29_ECP_MASK (0x80U) #define DMA_DCHPRI29_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK) /*! @} */ /*! @name DCHPRI28 - Channel Priority Register */ /*! @{ */ #define DMA_DCHPRI28_CHPRI_MASK (0xFU) #define DMA_DCHPRI28_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK) #define DMA_DCHPRI28_GRPPRI_MASK (0x30U) #define DMA_DCHPRI28_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ #define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK) #define DMA_DCHPRI28_DPA_MASK (0x40U) #define DMA_DCHPRI28_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK) #define DMA_DCHPRI28_ECP_MASK (0x80U) #define DMA_DCHPRI28_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK) /*! @} */ /*! @name SADDR - TCD Source Address */ /*! @{ */ #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) #define DMA_SADDR_SADDR_SHIFT (0U) /*! SADDR - Source Address */ #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) /*! @} */ /* The count of DMA_SADDR */ #define DMA_SADDR_COUNT (32U) /*! @name SOFF - TCD Signed Source Address Offset */ /*! @{ */ #define DMA_SOFF_SOFF_MASK (0xFFFFU) #define DMA_SOFF_SOFF_SHIFT (0U) /*! SOFF - Source address signed offset */ #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) /*! @} */ /* The count of DMA_SOFF */ #define DMA_SOFF_COUNT (32U) /*! @name ATTR - TCD Transfer Attributes */ /*! @{ */ #define DMA_ATTR_DSIZE_MASK (0x7U) #define DMA_ATTR_DSIZE_SHIFT (0U) /*! DSIZE - Destination data transfer size */ #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) #define DMA_ATTR_DMOD_MASK (0xF8U) #define DMA_ATTR_DMOD_SHIFT (3U) /*! DMOD - Destination Address Modulo */ #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) #define DMA_ATTR_SSIZE_MASK (0x700U) #define DMA_ATTR_SSIZE_SHIFT (8U) /*! SSIZE - Source data transfer size * 0b000..8-bit * 0b001..16-bit * 0b010..32-bit * 0b011..64-bit * 0b100..Reserved * 0b101..32-byte burst (4 beats of 64 bits) * 0b110..Reserved * 0b111..Reserved */ #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) #define DMA_ATTR_SMOD_MASK (0xF800U) #define DMA_ATTR_SMOD_SHIFT (11U) /*! SMOD - Source Address Modulo * 0b00000..Source address modulo feature is disabled * 0b00001-0b11111..This value defines a specific address range specified to be the value after SADDR + SOFF * calculation is performed on the original register value. Setting this field provides the ability * to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the * queue should start at a 0-modulo-size address and the SMOD field should be set to the * appropriate value for the queue, freezing the desired number of upper address bits. The value * programmed into this field specifies the number of lower address bits allowed to change. For a * circular queue application, the SOFF is typically set to the transfer size to implement * post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. */ #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) /*! @} */ /* The count of DMA_ATTR */ #define DMA_ATTR_COUNT (32U) /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ /*! @{ */ #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) /*! NBYTES - Minor Byte Transfer Count */ #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) /*! @} */ /* The count of DMA_NBYTES_MLNO */ #define DMA_NBYTES_MLNO_COUNT (32U) /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ /*! @{ */ #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) /*! NBYTES - Minor Byte Transfer Count */ #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) /*! DMLOE - Destination Minor Loop Offset enable * 0b0..The minor loop offset is not applied to the DADDR * 0b1..The minor loop offset is applied to the DADDR */ #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) /*! SMLOE - Source Minor Loop Offset Enable * 0b0..The minor loop offset is not applied to the SADDR * 0b1..The minor loop offset is applied to the SADDR */ #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) /*! @} */ /* The count of DMA_NBYTES_MLOFFNO */ #define DMA_NBYTES_MLOFFNO_COUNT (32U) /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ /*! @{ */ #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) /*! NBYTES - Minor Byte Transfer Count */ #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) /*! MLOFF - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the * source or destination address to form the next-state value after the minor loop completes. */ #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) /*! DMLOE - Destination Minor Loop Offset enable * 0b0..The minor loop offset is not applied to the DADDR * 0b1..The minor loop offset is applied to the DADDR */ #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) /*! SMLOE - Source Minor Loop Offset Enable * 0b0..The minor loop offset is not applied to the SADDR * 0b1..The minor loop offset is applied to the SADDR */ #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) /*! @} */ /* The count of DMA_NBYTES_MLOFFYES */ #define DMA_NBYTES_MLOFFYES_COUNT (32U) /*! @name SLAST - TCD Last Source Address Adjustment */ /*! @{ */ #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) #define DMA_SLAST_SLAST_SHIFT (0U) /*! SLAST - Last Source Address Adjustment */ #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) /*! @} */ /* The count of DMA_SLAST */ #define DMA_SLAST_COUNT (32U) /*! @name DADDR - TCD Destination Address */ /*! @{ */ #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) #define DMA_DADDR_DADDR_SHIFT (0U) /*! DADDR - Destination Address */ #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) /*! @} */ /* The count of DMA_DADDR */ #define DMA_DADDR_COUNT (32U) /*! @name DOFF - TCD Signed Destination Address Offset */ /*! @{ */ #define DMA_DOFF_DOFF_MASK (0xFFFFU) #define DMA_DOFF_DOFF_SHIFT (0U) /*! DOFF - Destination Address Signed Offset */ #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) /*! @} */ /* The count of DMA_DOFF */ #define DMA_DOFF_COUNT (32U) /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ /*! @{ */ #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) #define DMA_CITER_ELINKNO_CITER_SHIFT (0U) /*! CITER - Current Major Iteration Count */ #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) /*! ELINK - Enable channel-to-channel linking on minor-loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) /*! @} */ /* The count of DMA_CITER_ELINKNO */ #define DMA_CITER_ELINKNO_COUNT (32U) /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ /*! @{ */ #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) #define DMA_CITER_ELINKYES_CITER_SHIFT (0U) /*! CITER - Current Major Iteration Count */ #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) #define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U) #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) /*! LINKCH - Minor Loop Link Channel Number */ #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) /*! ELINK - Enable channel-to-channel linking on minor-loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) /*! @} */ /* The count of DMA_CITER_ELINKYES */ #define DMA_CITER_ELINKYES_COUNT (32U) /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ /*! @{ */ #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) /*! DLASTSGA - DLASTSGA */ #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) /*! @} */ /* The count of DMA_DLAST_SGA */ #define DMA_DLAST_SGA_COUNT (32U) /*! @name CSR - TCD Control and Status */ /*! @{ */ #define DMA_CSR_START_MASK (0x1U) #define DMA_CSR_START_SHIFT (0U) /*! START - Channel Start * 0b0..The channel is not explicitly started. * 0b1..The channel is explicitly started via a software initiated service request. */ #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) #define DMA_CSR_INTMAJOR_MASK (0x2U) #define DMA_CSR_INTMAJOR_SHIFT (1U) /*! INTMAJOR - Enable an interrupt when major iteration count completes. * 0b0..The end-of-major loop interrupt is disabled. * 0b1..The end-of-major loop interrupt is enabled. */ #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) #define DMA_CSR_INTHALF_MASK (0x4U) #define DMA_CSR_INTHALF_SHIFT (2U) /*! INTHALF - Enable an interrupt when major counter is half complete. * 0b0..The half-point interrupt is disabled. * 0b1..The half-point interrupt is enabled. */ #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) #define DMA_CSR_DREQ_MASK (0x8U) #define DMA_CSR_DREQ_SHIFT (3U) /*! DREQ - Disable Request * 0b0..The channel's ERQ bit is not affected. * 0b1..The channel's ERQ bit is cleared when the major loop is complete. */ #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) #define DMA_CSR_ESG_MASK (0x10U) #define DMA_CSR_ESG_SHIFT (4U) /*! ESG - Enable Scatter/Gather Processing * 0b0..The current channel's TCD is normal format. * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer * to the next TCD to be loaded into this channel after the major loop completes its execution. */ #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) #define DMA_CSR_MAJORELINK_MASK (0x20U) #define DMA_CSR_MAJORELINK_SHIFT (5U) /*! MAJORELINK - Enable channel-to-channel linking on major loop complete * 0b0..The channel-to-channel linking is disabled. * 0b1..The channel-to-channel linking is enabled. */ #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) #define DMA_CSR_ACTIVE_MASK (0x40U) #define DMA_CSR_ACTIVE_SHIFT (6U) /*! ACTIVE - Channel Active */ #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) #define DMA_CSR_DONE_MASK (0x80U) #define DMA_CSR_DONE_SHIFT (7U) /*! DONE - Channel Done */ #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) #define DMA_CSR_MAJORLINKCH_MASK (0x1F00U) #define DMA_CSR_MAJORLINKCH_SHIFT (8U) /*! MAJORLINKCH - Major Loop Link Channel Number */ #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) #define DMA_CSR_BWC_MASK (0xC000U) #define DMA_CSR_BWC_SHIFT (14U) /*! BWC - Bandwidth Control * 0b00..No eDMA engine stalls. * 0b01..Reserved * 0b10..eDMA engine stalls for 4 cycles after each R/W. * 0b11..eDMA engine stalls for 8 cycles after each R/W. */ #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) /*! @} */ /* The count of DMA_CSR */ #define DMA_CSR_COUNT (32U) /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ /*! @{ */ #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) #define DMA_BITER_ELINKNO_BITER_SHIFT (0U) /*! BITER - Starting Major Iteration Count */ #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) /*! ELINK - Enables channel-to-channel linking on minor loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) /*! @} */ /* The count of DMA_BITER_ELINKNO */ #define DMA_BITER_ELINKNO_COUNT (32U) /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ /*! @{ */ #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) #define DMA_BITER_ELINKYES_BITER_SHIFT (0U) /*! BITER - Starting major iteration count */ #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) #define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U) #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) /*! LINKCH - Link Channel Number */ #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) /*! ELINK - Enables channel-to-channel linking on minor loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) /*! @} */ /* The count of DMA_BITER_ELINKYES */ #define DMA_BITER_ELINKYES_COUNT (32U) /*! * @} */ /* end of group DMA_Register_Masks */ /* DMA - Peripheral instance base addresses */ /** Peripheral DMA0 base address */ #define DMA0_BASE (0x41008000u) /** Peripheral DMA0 base pointer */ #define DMA0 ((DMA_Type *)DMA0_BASE) /** Peripheral DMA1 base address */ #define DMA1_BASE (0x40080000u) /** Peripheral DMA1 base pointer */ #define DMA1 ((DMA_Type *)DMA1_BASE) /** Array initializer of DMA peripheral base addresses */ #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } /** Array initializer of DMA peripheral base pointers */ #define DMA_BASE_PTRS { DMA0, DMA1 } /** Interrupt vectors for the DMA peripheral type */ #define DMA_CHN_IRQS { { DMA0_0_4_IRQn, DMA0_1_5_IRQn, DMA0_2_6_IRQn, DMA0_3_7_IRQn, DMA0_0_4_IRQn, DMA0_1_5_IRQn, DMA0_2_6_IRQn, DMA0_3_7_IRQn, DMA0_8_12_IRQn, DMA0_9_13_IRQn, DMA0_10_14_IRQn, DMA0_11_15_IRQn, DMA0_8_12_IRQn, DMA0_9_13_IRQn, DMA0_10_14_IRQn, DMA0_11_15_IRQn, DMA0_16_20_IRQn, DMA0_17_21_IRQn, DMA0_18_22_IRQn, DMA0_19_23_IRQn, DMA0_16_20_IRQn, DMA0_17_21_IRQn, DMA0_18_22_IRQn, DMA0_19_23_IRQn, DMA0_24_28_IRQn, DMA0_25_29_IRQn, DMA0_26_30_IRQn, DMA0_27_31_IRQn, DMA0_24_28_IRQn, DMA0_25_29_IRQn, DMA0_26_30_IRQn, DMA0_27_31_IRQn }, \ { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } } #define DMA_ERROR_IRQS { DMA0_Error_IRQn, NotAvail_IRQn } /*! * @} */ /* end of group DMA_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMAMUX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer * @{ */ /** DMAMUX - Register Layout Typedef */ typedef struct { __IO uint32_t CHCFG[32]; /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */ } DMAMUX_Type; /* ---------------------------------------------------------------------------- -- DMAMUX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks * @{ */ /*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */ /*! @{ */ #define DMAMUX_CHCFG_SOURCE_MASK (0x7FU) #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) /*! SOURCE - DMA Channel Source (Slot Number) */ #define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) #define DMAMUX_CHCFG_A_ON_MASK (0x20000000U) #define DMAMUX_CHCFG_A_ON_SHIFT (29U) /*! A_ON - DMA Channel Always Enable * 0b0..DMA Channel Always ON function is disabled * 0b1..DMA Channel Always ON function is enabled */ #define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK) #define DMAMUX_CHCFG_TRIG_MASK (0x40000000U) #define DMAMUX_CHCFG_TRIG_SHIFT (30U) /*! TRIG - DMA Channel Trigger Enable * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the * specified source to the DMA channel. (Normal mode) * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. */ #define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) #define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) #define DMAMUX_CHCFG_ENBL_SHIFT (31U) /*! ENBL - DMA Mux Channel Enable * 0b0..DMA Mux channel is disabled * 0b1..DMA Mux channel is enabled */ #define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) /*! @} */ /* The count of DMAMUX_CHCFG */ #define DMAMUX_CHCFG_COUNT (32U) /*! * @} */ /* end of group DMAMUX_Register_Masks */ /* DMAMUX - Peripheral instance base addresses */ /** Peripheral DMA_CH_MUX0 base address */ #define DMA_CH_MUX0_BASE (0x41020000u) /** Peripheral DMA_CH_MUX0 base pointer */ #define DMA_CH_MUX0 ((DMAMUX_Type *)DMA_CH_MUX0_BASE) /** Peripheral DMA_CH_MUX1 base address */ #define DMA_CH_MUX1_BASE (0x40210000u) /** Peripheral DMA_CH_MUX1 base pointer */ #define DMA_CH_MUX1 ((DMAMUX_Type *)DMA_CH_MUX1_BASE) /** Array initializer of DMAMUX peripheral base addresses */ #define DMAMUX_BASE_ADDRS { DMA_CH_MUX0_BASE, DMA_CH_MUX1_BASE } /** Array initializer of DMAMUX peripheral base pointers */ #define DMAMUX_BASE_PTRS { DMA_CH_MUX0, DMA_CH_MUX1 } /*! * @} */ /* end of group DMAMUX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- EWM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer * @{ */ /** EWM - Register Layout Typedef */ typedef struct { __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ __O uint8_t SERV; /**< Service Register, offset: 0x1 */ __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ __IO uint8_t CLKCTRL; /**< Clock Control Register, offset: 0x4 */ __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */ } EWM_Type; /* ---------------------------------------------------------------------------- -- EWM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup EWM_Register_Masks EWM Register Masks * @{ */ /*! @name CTRL - Control Register */ /*! @{ */ #define EWM_CTRL_EWMEN_MASK (0x1U) #define EWM_CTRL_EWMEN_SHIFT (0U) /*! EWMEN - EWM enable. */ #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) #define EWM_CTRL_ASSIN_MASK (0x2U) #define EWM_CTRL_ASSIN_SHIFT (1U) /*! ASSIN - EWM_in's Assertion State Select. */ #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) #define EWM_CTRL_INEN_MASK (0x4U) #define EWM_CTRL_INEN_SHIFT (2U) /*! INEN - Input Enable. */ #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) #define EWM_CTRL_INTEN_MASK (0x8U) #define EWM_CTRL_INTEN_SHIFT (3U) /*! INTEN - Interrupt Enable. */ #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) /*! @} */ /*! @name SERV - Service Register */ /*! @{ */ #define EWM_SERV_SERVICE_MASK (0xFFU) #define EWM_SERV_SERVICE_SHIFT (0U) /*! SERVICE - SERVICE */ #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) /*! @} */ /*! @name CMPL - Compare Low Register */ /*! @{ */ #define EWM_CMPL_COMPAREL_MASK (0xFFU) #define EWM_CMPL_COMPAREL_SHIFT (0U) /*! COMPAREL - COMPAREL */ #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) /*! @} */ /*! @name CMPH - Compare High Register */ /*! @{ */ #define EWM_CMPH_COMPAREH_MASK (0xFFU) #define EWM_CMPH_COMPAREH_SHIFT (0U) /*! COMPAREH - COMPAREH */ #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) /*! @} */ /*! @name CLKCTRL - Clock Control Register */ /*! @{ */ #define EWM_CLKCTRL_CLKSEL_MASK (0x3U) #define EWM_CLKCTRL_CLKSEL_SHIFT (0U) /*! CLKSEL - CLKSEL */ #define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK) /*! @} */ /*! @name CLKPRESCALER - Clock Prescaler Register */ /*! @{ */ #define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) #define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) /*! CLK_DIV - CLK_DIV */ #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) /*! @} */ /*! * @} */ /* end of group EWM_Register_Masks */ /* EWM - Peripheral instance base addresses */ /** Peripheral EWM base address */ #define EWM_BASE (0x410A0000u) /** Peripheral EWM base pointer */ #define EWM ((EWM_Type *)EWM_BASE) /** Array initializer of EWM peripheral base addresses */ #define EWM_BASE_ADDRS { EWM_BASE } /** Array initializer of EWM peripheral base pointers */ #define EWM_BASE_PTRS { EWM } /** Interrupt vectors for the EWM peripheral type */ #define EWM_IRQS { EWM_IRQn } /*! * @} */ /* end of group EWM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer * @{ */ /** FB - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0xC */ __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */ __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */ __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */ } CS[6]; uint8_t RESERVED_0[24]; __IO uint32_t CSPMCR; /**< Chip Select Port Multiplexing Control Register, offset: 0x60 */ } FB_Type; /* ---------------------------------------------------------------------------- -- FB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FB_Register_Masks FB Register Masks * @{ */ /*! @name CSAR - Chip Select Address Register */ /*! @{ */ #define FB_CSAR_BA_MASK (0xFFFF0000U) #define FB_CSAR_BA_SHIFT (16U) /*! BA - Base Address */ #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK) /*! @} */ /* The count of FB_CSAR */ #define FB_CSAR_COUNT (6U) /*! @name CSMR - Chip Select Mask Register */ /*! @{ */ #define FB_CSMR_V_MASK (0x1U) #define FB_CSMR_V_SHIFT (0U) /*! V - Valid * 0b0..Chip-select is invalid. * 0b1..Chip-select is valid. */ #define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK) #define FB_CSMR_WP_MASK (0x100U) #define FB_CSMR_WP_SHIFT (8U) /*! WP - Write Protect * 0b0..Write accesses are allowed. * 0b1..Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set * results in a bus error termination of the internal cycle and no external cycle. */ #define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK) #define FB_CSMR_BAM_MASK (0xFFFF0000U) #define FB_CSMR_BAM_SHIFT (16U) /*! BAM - Base Address Mask * 0b0000000000000000..The corresponding address bit in CSAR is used in the chip-select decode. * 0b0000000000000001..The corresponding address bit in CSAR is a don't care in the chip-select decode. */ #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK) /*! @} */ /* The count of FB_CSMR */ #define FB_CSMR_COUNT (6U) /*! @name CSCR - Chip Select Control Register */ /*! @{ */ #define FB_CSCR_BSTW_MASK (0x8U) #define FB_CSCR_BSTW_SHIFT (3U) /*! BSTW - Burst-Write Enable * 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. * For example, a 32-bit write to an 8-bit port takes four byte writes. * 0b1..Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- * and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. */ #define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK) #define FB_CSCR_BSTR_MASK (0x10U) #define FB_CSCR_BSTR_SHIFT (4U) /*! BSTR - Burst-Read Enable * 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. * For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. * 0b1..Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and * 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. */ #define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK) #define FB_CSCR_BEM_MASK (0x20U) #define FB_CSCR_BEM_SHIFT (5U) /*! BEM - Byte-Enable Mode * 0b0..FB_BE_B is asserted for data write only. * 0b1..FB_BE_B is asserted for data read and write accesses. */ #define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK) #define FB_CSCR_PS_MASK (0xC0U) #define FB_CSCR_PS_SHIFT (6U) /*! PS - Port Size * 0b00..32-bit port size. Valid data is sampled and driven on FB_D[31:0]. * 0b01..8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. * 0b1x..16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b. */ #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK) #define FB_CSCR_AA_MASK (0x100U) #define FB_CSCR_AA_SHIFT (8U) /*! AA - Auto-Acknowledge Enable * 0b0..Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. * 0b1..Enabled. Internal transfer acknowledge is asserted as specified by WS. */ #define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK) #define FB_CSCR_BLS_MASK (0x200U) #define FB_CSCR_BLS_SHIFT (9U) /*! BLS - Byte-Lane Shift * 0b0..Not shifted. Data is left-aligned on FB_AD. * 0b1..Shifted. Data is right-aligned on FB_AD. */ #define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK) #define FB_CSCR_WS_MASK (0xFC00U) #define FB_CSCR_WS_SHIFT (10U) /*! WS - Wait States */ #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK) #define FB_CSCR_WRAH_MASK (0x30000U) #define FB_CSCR_WRAH_SHIFT (16U) /*! WRAH - Write Address Hold or Deselect * 0b00..1 cycle (default for all but FB_CS0_B) * 0b01..2 cycles * 0b10..3 cycles * 0b11..4 cycles (default for FB_CS0_B) */ #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK) #define FB_CSCR_RDAH_MASK (0xC0000U) #define FB_CSCR_RDAH_SHIFT (18U) /*! RDAH - Read Address Hold or Deselect * 0b00..When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. * 0b01..When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. * 0b10..When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. * 0b11..When AA is 1b, 4 cycles. When AA is 0b, 3 cycles. */ #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK) #define FB_CSCR_ASET_MASK (0x300000U) #define FB_CSCR_ASET_SHIFT (20U) /*! ASET - Address Setup * 0b00..Assert FB_CSn_B on the first rising clock edge after the address is asserted (default for all but FB_CS0_B). * 0b01..Assert FB_CSn_B on the second rising clock edge after the address is asserted. * 0b10..Assert FB_CSn_B on the third rising clock edge after the address is asserted. * 0b11..Assert FB_CSn_B on the fourth rising clock edge after the address is asserted (default for FB_CS0_B ). */ #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK) #define FB_CSCR_EXTS_MASK (0x400000U) #define FB_CSCR_EXTS_SHIFT (22U) /*! EXTS - EXTS * 0b0..Disabled. FB_TS_B/FB_ALE asserts for one bus clock cycle. * 0b1..Enabled. FB_TS_B/FB_ALE remains asserted until the first positive clock edge after FB_CSn_B asserts. */ #define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK) #define FB_CSCR_SWSEN_MASK (0x800000U) #define FB_CSCR_SWSEN_SHIFT (23U) /*! SWSEN - Secondary Wait State Enable * 0b0..Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. * 0b1..Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge * is generated for burst transfer secondary terminations. */ #define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK) #define FB_CSCR_SWS_MASK (0xFC000000U) #define FB_CSCR_SWS_SHIFT (26U) /*! SWS - Secondary Wait States */ #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK) /*! @} */ /* The count of FB_CSCR */ #define FB_CSCR_COUNT (6U) /*! @name CSPMCR - Chip Select Port Multiplexing Control Register */ /*! @{ */ #define FB_CSPMCR_GROUP5_MASK (0xF000U) #define FB_CSPMCR_GROUP5_SHIFT (12U) /*! GROUP5 - FlexBus Signal Group 5 Multiplex control * 0b0000..FB_TA_B * 0b0001..FB_CS3_B. You must also write 1b to CSCR[AA]. * 0b0010..FB_BE_7_0_B. You must also write 1b to CSCR[AA]. */ #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK) #define FB_CSPMCR_GROUP4_MASK (0xF0000U) #define FB_CSPMCR_GROUP4_SHIFT (16U) /*! GROUP4 - FlexBus Signal Group 4 Multiplex control * 0b0000..FB_TBST_B * 0b0001..FB_CS2_B * 0b0010..FB_BE_15_8_B */ #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK) #define FB_CSPMCR_GROUP3_MASK (0xF00000U) #define FB_CSPMCR_GROUP3_SHIFT (20U) /*! GROUP3 - FlexBus Signal Group 3 Multiplex control * 0b0000..FB_CS5_B * 0b0001..FB_TSIZ1 * 0b0010..FB_BE_23_16_B */ #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK) #define FB_CSPMCR_GROUP2_MASK (0xF000000U) #define FB_CSPMCR_GROUP2_SHIFT (24U) /*! GROUP2 - FlexBus Signal Group 2 Multiplex control * 0b0000..FB_CS4_B * 0b0001..FB_TSIZ0 * 0b0010..FB_BE_31_24_B */ #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK) #define FB_CSPMCR_GROUP1_MASK (0xF0000000U) #define FB_CSPMCR_GROUP1_SHIFT (28U) /*! GROUP1 - FlexBus Signal Group 1 Multiplex control * 0b0000..FB_ALE * 0b0001..FB_CS1_B * 0b0010..FB_TS_B */ #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK) /*! @} */ /*! * @} */ /* end of group FB_Register_Masks */ /* FB - Peripheral instance base addresses */ /** Peripheral FB base address */ #define FB_BASE (0x40100000u) /** Peripheral FB base pointer */ #define FB ((FB_Type *)FB_BASE) /** Array initializer of FB peripheral base addresses */ #define FB_BASE_ADDRS { FB_BASE } /** Array initializer of FB peripheral base pointers */ #define FB_BASE_PTRS { FB } /*! * @} */ /* end of group FB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FGPIO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer * @{ */ /** FGPIO - Register Layout Typedef */ typedef struct { __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t BDACP0[4]; /**< Port Byte Domain Access Control Register 0, array offset: 0x20, array step: 0x4 */ } FGPIO_Type; /* ---------------------------------------------------------------------------- -- FGPIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FGPIO_Register_Masks FGPIO Register Masks * @{ */ /*! @name PDOR - Port Data Output Register */ /*! @{ */ #define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU) #define FGPIO_PDOR_PDO_SHIFT (0U) /*! PDO - Port Data Output */ #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK) /*! @} */ /*! @name PSOR - Port Set Output Register */ /*! @{ */ #define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) #define FGPIO_PSOR_PTSO_SHIFT (0U) /*! PTSO - Port Set Output */ #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK) /*! @} */ /*! @name PCOR - Port Clear Output Register */ /*! @{ */ #define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) #define FGPIO_PCOR_PTCO_SHIFT (0U) /*! PTCO - Port Clear Output */ #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK) /*! @} */ /*! @name PTOR - Port Toggle Output Register */ /*! @{ */ #define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) #define FGPIO_PTOR_PTTO_SHIFT (0U) /*! PTTO - Port Toggle Output */ #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK) /*! @} */ /*! @name PDIR - Port Data Input Register */ /*! @{ */ #define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU) #define FGPIO_PDIR_PDI_SHIFT (0U) /*! PDI - Port Data Input */ #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK) /*! @} */ /*! @name PDDR - Port Data Direction Register */ /*! @{ */ #define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU) #define FGPIO_PDDR_PDD_SHIFT (0U) /*! PDD - Port Data Direction */ #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK) /*! @} */ /*! @name BDACP0 - Port Byte Domain Access Control Register 0 */ /*! @{ */ #define FGPIO_BDACP0_D0ACP_MASK (0x7U) #define FGPIO_BDACP0_D0ACP_SHIFT (0U) /*! D0ACP - Domain Access Control Policy */ #define FGPIO_BDACP0_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_D0ACP_SHIFT)) & FGPIO_BDACP0_D0ACP_MASK) #define FGPIO_BDACP0_D1ACP_MASK (0x38U) #define FGPIO_BDACP0_D1ACP_SHIFT (3U) /*! D1ACP - Domain Access Control Policy */ #define FGPIO_BDACP0_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_D1ACP_SHIFT)) & FGPIO_BDACP0_D1ACP_MASK) #define FGPIO_BDACP0_D2ACP_MASK (0x1C0U) #define FGPIO_BDACP0_D2ACP_SHIFT (6U) /*! D2ACP - Domain Access Control Policy */ #define FGPIO_BDACP0_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_D2ACP_SHIFT)) & FGPIO_BDACP0_D2ACP_MASK) #define FGPIO_BDACP0_D3ACP_MASK (0xE00U) #define FGPIO_BDACP0_D3ACP_SHIFT (9U) /*! D3ACP - Domain Access Control Policy */ #define FGPIO_BDACP0_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_D3ACP_SHIFT)) & FGPIO_BDACP0_D3ACP_MASK) #define FGPIO_BDACP0_D4ACP_MASK (0x7000U) #define FGPIO_BDACP0_D4ACP_SHIFT (12U) /*! D4ACP - Domain Access Control Policy */ #define FGPIO_BDACP0_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_D4ACP_SHIFT)) & FGPIO_BDACP0_D4ACP_MASK) #define FGPIO_BDACP0_D5ACP_MASK (0x38000U) #define FGPIO_BDACP0_D5ACP_SHIFT (15U) /*! D5ACP - Domain Access Control Policy */ #define FGPIO_BDACP0_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_D5ACP_SHIFT)) & FGPIO_BDACP0_D5ACP_MASK) #define FGPIO_BDACP0_D6ACP_MASK (0x1C0000U) #define FGPIO_BDACP0_D6ACP_SHIFT (18U) /*! D6ACP - Domain Access Control Policy */ #define FGPIO_BDACP0_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_D6ACP_SHIFT)) & FGPIO_BDACP0_D6ACP_MASK) #define FGPIO_BDACP0_D7ACP_MASK (0xE00000U) #define FGPIO_BDACP0_D7ACP_SHIFT (21U) /*! D7ACP - Domain Access Control Policy */ #define FGPIO_BDACP0_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_D7ACP_SHIFT)) & FGPIO_BDACP0_D7ACP_MASK) #define FGPIO_BDACP0_LK2_MASK (0x60000000U) #define FGPIO_BDACP0_LK2_SHIFT (29U) /*! LK2 - LK2 * 0b00..Entire DxACP can be written. * 0b01..Entire DxACP can be written. * 0b10..Domain x can only update the DxACP field; no other D*ACP fields can be written. * 0b11..DxACP is locked (read-only) until the next reset. */ #define FGPIO_BDACP0_LK2(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_LK2_SHIFT)) & FGPIO_BDACP0_LK2_MASK) #define FGPIO_BDACP0_VLD_MASK (0x80000000U) #define FGPIO_BDACP0_VLD_SHIFT (31U) /*! VLD - Valid * 0b0..The DxACP assignment is invalid. * 0b1..The DxACP assignment is valid. */ #define FGPIO_BDACP0_VLD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_BDACP0_VLD_SHIFT)) & FGPIO_BDACP0_VLD_MASK) /*! @} */ /* The count of FGPIO_BDACP0 */ #define FGPIO_BDACP0_COUNT (4U) /*! * @} */ /* end of group FGPIO_Register_Masks */ /* FGPIO - Peripheral instance base addresses */ /** Peripheral FGPIOA base address */ #define FGPIOA_BASE (0xF9000000u) /** Peripheral FGPIOA base pointer */ #define FGPIOA ((FGPIO_Type *)FGPIOA_BASE) /** Peripheral FGPIOB base address */ #define FGPIOB_BASE (0xF9000040u) /** Peripheral FGPIOB base pointer */ #define FGPIOB ((FGPIO_Type *)FGPIOB_BASE) /** Array initializer of FGPIO peripheral base addresses */ #define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOB_BASE } /** Array initializer of FGPIO peripheral base pointers */ #define FGPIO_BASE_PTRS { FGPIOA, FGPIOB } /*! * @} */ /* end of group FGPIO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FLEXIO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer * @{ */ /** FLEXIO - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ __I uint32_t PIN; /**< Pin State Register, offset: 0xC */ __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ uint8_t RESERVED_0[4]; __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ uint8_t RESERVED_1[4]; __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ uint8_t RESERVED_2[12]; __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */ uint8_t RESERVED_3[60]; __IO uint32_t SHIFTCTL[8]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_4[96]; __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_5[224]; __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_6[96]; __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ uint8_t RESERVED_7[96]; __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ uint8_t RESERVED_8[96]; __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ uint8_t RESERVED_9[96]; __IO uint32_t TIMCTL[8]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ uint8_t RESERVED_10[96]; __IO uint32_t TIMCFG[8]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ uint8_t RESERVED_11[96]; __IO uint32_t TIMCMP[8]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ uint8_t RESERVED_12[352]; __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */ uint8_t RESERVED_13[96]; __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */ uint8_t RESERVED_14[96]; __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */ } FLEXIO_Type; /* ---------------------------------------------------------------------------- -- FLEXIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) #define FLEXIO_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Standard features implemented. * 0b0000000000000001..Supports state, logic and parallel modes. */ #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) #define FLEXIO_VERID_MINOR_MASK (0xFF0000U) #define FLEXIO_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) #define FLEXIO_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) #define FLEXIO_PARAM_SHIFTER_SHIFT (0U) /*! SHIFTER - Shifter Number */ #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) #define FLEXIO_PARAM_TIMER_MASK (0xFF00U) #define FLEXIO_PARAM_TIMER_SHIFT (8U) /*! TIMER - Timer Number */ #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) #define FLEXIO_PARAM_PIN_MASK (0xFF0000U) #define FLEXIO_PARAM_PIN_SHIFT (16U) /*! PIN - Pin Number */ #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) #define FLEXIO_PARAM_TRIGGER_SHIFT (24U) /*! TRIGGER - Trigger Number */ #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) /*! @} */ /*! @name CTRL - FlexIO Control Register */ /*! @{ */ #define FLEXIO_CTRL_FLEXEN_MASK (0x1U) #define FLEXIO_CTRL_FLEXEN_SHIFT (0U) /*! FLEXEN - FlexIO Enable * 0b0..FlexIO module is disabled. * 0b1..FlexIO module is enabled. */ #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) #define FLEXIO_CTRL_SWRST_MASK (0x2U) #define FLEXIO_CTRL_SWRST_SHIFT (1U) /*! SWRST - Software Reset * 0b0..Software reset is disabled * 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset. */ #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) #define FLEXIO_CTRL_FASTACC_MASK (0x4U) #define FLEXIO_CTRL_FASTACC_SHIFT (2U) /*! FASTACC - Fast Access * 0b0..Configures for normal register accesses to FlexIO * 0b1..Configures for fast register accesses to FlexIO */ #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) #define FLEXIO_CTRL_DBGE_MASK (0x40000000U) #define FLEXIO_CTRL_DBGE_SHIFT (30U) /*! DBGE - Debug Enable * 0b0..FlexIO is disabled in debug modes. * 0b1..FlexIO is enabled in debug modes */ #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) #define FLEXIO_CTRL_DOZEN_SHIFT (31U) /*! DOZEN - Doze Enable * 0b0..FlexIO enabled in Doze modes. * 0b1..FlexIO disabled in Doze modes. */ #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) /*! @} */ /*! @name PIN - Pin State Register */ /*! @{ */ #define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) #define FLEXIO_PIN_PDI_SHIFT (0U) /*! PDI - Pin Data Input */ #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) /*! @} */ /*! @name SHIFTSTAT - Shifter Status Register */ /*! @{ */ #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) /*! SSF - Shifter Status Flag */ #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) /*! @} */ /*! @name SHIFTERR - Shifter Error Register */ /*! @{ */ #define FLEXIO_SHIFTERR_SEF_MASK (0xFFU) #define FLEXIO_SHIFTERR_SEF_SHIFT (0U) /*! SEF - Shifter Error Flags */ #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) /*! @} */ /*! @name TIMSTAT - Timer Status Register */ /*! @{ */ #define FLEXIO_TIMSTAT_TSF_MASK (0xFFU) #define FLEXIO_TIMSTAT_TSF_SHIFT (0U) /*! TSF - Timer Status Flags */ #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) /*! @} */ /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ /*! @{ */ #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU) #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) /*! SSIE - Shifter Status Interrupt Enable */ #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) /*! @} */ /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ /*! @{ */ #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU) #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) /*! SEIE - Shifter Error Interrupt Enable */ #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) /*! @} */ /*! @name TIMIEN - Timer Interrupt Enable Register */ /*! @{ */ #define FLEXIO_TIMIEN_TEIE_MASK (0xFFU) #define FLEXIO_TIMIEN_TEIE_SHIFT (0U) /*! TEIE - Timer Status Interrupt Enable */ #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) /*! @} */ /*! @name SHIFTSDEN - Shifter Status DMA Enable */ /*! @{ */ #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU) #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) /*! SSDE - Shifter Status DMA Enable */ #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) /*! @} */ /*! @name SHIFTSTATE - Shifter State Register */ /*! @{ */ #define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) #define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) /*! STATE - Current State Pointer */ #define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) /*! @} */ /*! @name SHIFTCTL - Shifter Control N Register */ /*! @{ */ #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) /*! SMOD - Shifter Mode * 0b000..Disabled. * 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. * 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. * 0b011..Reserved. * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. * 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. * 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. */ #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) /*! PINPOL - Shifter Pin Polarity * 0b0..Pin is active high * 0b1..Pin is active low */ #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) /*! PINSEL - Shifter Pin Select */ #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) /*! PINCFG - Shifter Pin Configuration * 0b00..Shifter pin output disabled * 0b01..Shifter pin open drain or bidirectional output enable * 0b10..Shifter pin bidirectional output data * 0b11..Shifter pin output */ #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) /*! TIMPOL - Timer Polarity * 0b0..Shift on posedge of Shift clock * 0b1..Shift on negedge of Shift clock */ #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U) #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) /*! TIMSEL - Timer Select */ #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) /*! @} */ /* The count of FLEXIO_SHIFTCTL */ #define FLEXIO_SHIFTCTL_COUNT (8U) /*! @name SHIFTCFG - Shifter Configuration N Register */ /*! @{ */ #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) /*! SSTART - Shifter Start bit * 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable * 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift * 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 * 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 */ #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) /*! SSTOP - Shifter Stop bit * 0b00..Stop bit disabled for transmitter/receiver/match store * 0b01..Reserved for transmitter/receiver/match store * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 */ #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) /*! INSRC - Input Source * 0b0..Pin * 0b1..Shifter N+1 Output */ #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) #define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) /*! PWIDTH - Parallel Width */ #define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) /*! @} */ /* The count of FLEXIO_SHIFTCFG */ #define FLEXIO_SHIFTCFG_COUNT (8U) /*! @name SHIFTBUF - Shifter Buffer N Register */ /*! @{ */ #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) /*! SHIFTBUF - Shift Buffer */ #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUF */ #define FLEXIO_SHIFTBUF_COUNT (8U) /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ /*! @{ */ #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) /*! SHIFTBUFBIS - Shift Buffer */ #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFBIS */ #define FLEXIO_SHIFTBUFBIS_COUNT (8U) /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ /*! @{ */ #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) /*! SHIFTBUFBYS - Shift Buffer */ #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFBYS */ #define FLEXIO_SHIFTBUFBYS_COUNT (8U) /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ /*! @{ */ #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) /*! SHIFTBUFBBS - Shift Buffer */ #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFBBS */ #define FLEXIO_SHIFTBUFBBS_COUNT (8U) /*! @name TIMCTL - Timer Control N Register */ /*! @{ */ #define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) /*! TIMOD - Timer Mode * 0b00..Timer Disabled. * 0b01..Dual 8-bit counters baud mode. * 0b10..Dual 8-bit counters PWM high mode. * 0b11..Single 16-bit counter mode. */ #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) /*! PINPOL - Timer Pin Polarity * 0b0..Pin is active high * 0b1..Pin is active low */ #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) #define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) /*! PINSEL - Timer Pin Select */ #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) /*! PINCFG - Timer Pin Configuration * 0b00..Timer pin output disabled * 0b01..Timer pin open drain or bidirectional output enable * 0b10..Timer pin bidirectional output data * 0b11..Timer pin output */ #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) /*! TRGSRC - Trigger Source * 0b0..External trigger selected * 0b1..Internal trigger selected */ #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) /*! TRGPOL - Trigger Polarity * 0b0..Trigger active high * 0b1..Trigger active low */ #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) #define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) /*! TRGSEL - Trigger Select */ #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) /*! @} */ /* The count of FLEXIO_TIMCTL */ #define FLEXIO_TIMCTL_COUNT (8U) /*! @name TIMCFG - Timer Configuration N Register */ /*! @{ */ #define FLEXIO_TIMCFG_TSTART_MASK (0x2U) #define FLEXIO_TIMCFG_TSTART_SHIFT (1U) /*! TSTART - Timer Start Bit * 0b0..Start bit disabled * 0b1..Start bit enabled */ #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) /*! TSTOP - Timer Stop Bit * 0b00..Stop bit disabled * 0b01..Stop bit is enabled on timer compare * 0b10..Stop bit is enabled on timer disable * 0b11..Stop bit is enabled on timer compare and timer disable */ #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) /*! TIMENA - Timer Enable * 0b000..Timer always enabled * 0b001..Timer enabled on Timer N-1 enable * 0b010..Timer enabled on Trigger high * 0b011..Timer enabled on Trigger high and Pin high * 0b100..Timer enabled on Pin rising edge * 0b101..Timer enabled on Pin rising edge and Trigger high * 0b110..Timer enabled on Trigger rising edge * 0b111..Timer enabled on Trigger rising or falling edge */ #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) /*! TIMDIS - Timer Disable * 0b000..Timer never disabled * 0b001..Timer disabled on Timer N-1 disable * 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement) * 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low * 0b100..Timer disabled on Pin rising or falling edge * 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high * 0b110..Timer disabled on Trigger falling edge * 0b111..Reserved */ #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) /*! TIMRST - Timer Reset * 0b000..Timer never reset * 0b001..Reserved * 0b010..Timer reset on Timer Pin equal to Timer Output * 0b011..Timer reset on Timer Trigger equal to Timer Output * 0b100..Timer reset on Timer Pin rising edge * 0b101..Reserved * 0b110..Timer reset on Trigger rising edge * 0b111..Timer reset on Trigger rising or falling edge */ #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) #define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) /*! TIMDEC - Timer Decrement * 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output. * 0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output. * 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input. * 0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. */ #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) /*! TIMOUT - Timer Output * 0b00..Timer output is logic one when enabled and is not affected by timer reset * 0b01..Timer output is logic zero when enabled and is not affected by timer reset * 0b10..Timer output is logic one when enabled and on timer reset * 0b11..Timer output is logic zero when enabled and on timer reset */ #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) /*! @} */ /* The count of FLEXIO_TIMCFG */ #define FLEXIO_TIMCFG_COUNT (8U) /*! @name TIMCMP - Timer Compare N Register */ /*! @{ */ #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) #define FLEXIO_TIMCMP_CMP_SHIFT (0U) /*! CMP - Timer Compare Value */ #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) /*! @} */ /* The count of FLEXIO_TIMCMP */ #define FLEXIO_TIMCMP_COUNT (8U) /*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ /*! @{ */ #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) /*! SHIFTBUFNBS - Shift Buffer */ #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFNBS */ #define FLEXIO_SHIFTBUFNBS_COUNT (8U) /*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */ /*! @{ */ #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) /*! SHIFTBUFHWS - Shift Buffer */ #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFHWS */ #define FLEXIO_SHIFTBUFHWS_COUNT (8U) /*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ /*! @{ */ #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) /*! SHIFTBUFNIS - Shift Buffer */ #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFNIS */ #define FLEXIO_SHIFTBUFNIS_COUNT (8U) /*! * @} */ /* end of group FLEXIO_Register_Masks */ /* FLEXIO - Peripheral instance base addresses */ /** Peripheral FLEXIO0 base address */ #define FLEXIO0_BASE (0x41032000u) /** Peripheral FLEXIO0 base pointer */ #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) /** Peripheral FLEXIO1 base address */ #define FLEXIO1_BASE (0x40310000u) /** Peripheral FLEXIO1 base pointer */ #define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE) /** Array initializer of FLEXIO peripheral base addresses */ #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE, FLEXIO1_BASE } /** Array initializer of FLEXIO peripheral base pointers */ #define FLEXIO_BASE_PTRS { FLEXIO0, FLEXIO1 } /** Interrupt vectors for the FLEXIO peripheral type */ #define FLEXIO_IRQS { FLEXIO0_IRQn, NotAvail_IRQn } /*! * @} */ /* end of group FLEXIO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPIO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer * @{ */ /** GPIO - Register Layout Typedef */ typedef struct { __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t BDACP0[4]; /**< Port Byte Domain Access Control Register 0, array offset: 0x20, array step: 0x4 */ } GPIO_Type; /* ---------------------------------------------------------------------------- -- GPIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Register_Masks GPIO Register Masks * @{ */ /*! @name PDOR - Port Data Output Register */ /*! @{ */ #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) #define GPIO_PDOR_PDO_SHIFT (0U) /*! PDO - Port Data Output */ #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) /*! @} */ /*! @name PSOR - Port Set Output Register */ /*! @{ */ #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) #define GPIO_PSOR_PTSO_SHIFT (0U) /*! PTSO - Port Set Output */ #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) /*! @} */ /*! @name PCOR - Port Clear Output Register */ /*! @{ */ #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) #define GPIO_PCOR_PTCO_SHIFT (0U) /*! PTCO - Port Clear Output */ #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) /*! @} */ /*! @name PTOR - Port Toggle Output Register */ /*! @{ */ #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) #define GPIO_PTOR_PTTO_SHIFT (0U) /*! PTTO - Port Toggle Output */ #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) /*! @} */ /*! @name PDIR - Port Data Input Register */ /*! @{ */ #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) #define GPIO_PDIR_PDI_SHIFT (0U) /*! PDI - Port Data Input */ #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) /*! @} */ /*! @name PDDR - Port Data Direction Register */ /*! @{ */ #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) #define GPIO_PDDR_PDD_SHIFT (0U) /*! PDD - Port Data Direction */ #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) /*! @} */ /*! @name BDACP0 - Port Byte Domain Access Control Register 0 */ /*! @{ */ #define GPIO_BDACP0_D0ACP_MASK (0x7U) #define GPIO_BDACP0_D0ACP_SHIFT (0U) /*! D0ACP - Domain Access Control Policy */ #define GPIO_BDACP0_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_D0ACP_SHIFT)) & GPIO_BDACP0_D0ACP_MASK) #define GPIO_BDACP0_D1ACP_MASK (0x38U) #define GPIO_BDACP0_D1ACP_SHIFT (3U) /*! D1ACP - Domain Access Control Policy */ #define GPIO_BDACP0_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_D1ACP_SHIFT)) & GPIO_BDACP0_D1ACP_MASK) #define GPIO_BDACP0_D2ACP_MASK (0x1C0U) #define GPIO_BDACP0_D2ACP_SHIFT (6U) /*! D2ACP - Domain Access Control Policy */ #define GPIO_BDACP0_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_D2ACP_SHIFT)) & GPIO_BDACP0_D2ACP_MASK) #define GPIO_BDACP0_D3ACP_MASK (0xE00U) #define GPIO_BDACP0_D3ACP_SHIFT (9U) /*! D3ACP - Domain Access Control Policy */ #define GPIO_BDACP0_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_D3ACP_SHIFT)) & GPIO_BDACP0_D3ACP_MASK) #define GPIO_BDACP0_D4ACP_MASK (0x7000U) #define GPIO_BDACP0_D4ACP_SHIFT (12U) /*! D4ACP - Domain Access Control Policy */ #define GPIO_BDACP0_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_D4ACP_SHIFT)) & GPIO_BDACP0_D4ACP_MASK) #define GPIO_BDACP0_D5ACP_MASK (0x38000U) #define GPIO_BDACP0_D5ACP_SHIFT (15U) /*! D5ACP - Domain Access Control Policy */ #define GPIO_BDACP0_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_D5ACP_SHIFT)) & GPIO_BDACP0_D5ACP_MASK) #define GPIO_BDACP0_D6ACP_MASK (0x1C0000U) #define GPIO_BDACP0_D6ACP_SHIFT (18U) /*! D6ACP - Domain Access Control Policy */ #define GPIO_BDACP0_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_D6ACP_SHIFT)) & GPIO_BDACP0_D6ACP_MASK) #define GPIO_BDACP0_D7ACP_MASK (0xE00000U) #define GPIO_BDACP0_D7ACP_SHIFT (21U) /*! D7ACP - Domain Access Control Policy */ #define GPIO_BDACP0_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_D7ACP_SHIFT)) & GPIO_BDACP0_D7ACP_MASK) #define GPIO_BDACP0_LK2_MASK (0x60000000U) #define GPIO_BDACP0_LK2_SHIFT (29U) /*! LK2 - LK2 * 0b00..Entire DxACP can be written. * 0b01..Entire DxACP can be written. * 0b10..Domain x can only update the DxACP field; no other D*ACP fields can be written. * 0b11..DxACP is locked (read-only) until the next reset. */ #define GPIO_BDACP0_LK2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_LK2_SHIFT)) & GPIO_BDACP0_LK2_MASK) #define GPIO_BDACP0_VLD_MASK (0x80000000U) #define GPIO_BDACP0_VLD_SHIFT (31U) /*! VLD - Valid * 0b0..The DxACP assignment is invalid. * 0b1..The DxACP assignment is valid. */ #define GPIO_BDACP0_VLD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BDACP0_VLD_SHIFT)) & GPIO_BDACP0_VLD_MASK) /*! @} */ /* The count of GPIO_BDACP0 */ #define GPIO_BDACP0_COUNT (4U) /*! * @} */ /* end of group GPIO_Register_Masks */ /* GPIO - Peripheral instance base addresses */ /** Peripheral GPIOA base address */ #define GPIOA_BASE (0x4100F000u) /** Peripheral GPIOA base pointer */ #define GPIOA ((GPIO_Type *)GPIOA_BASE) /** Peripheral GPIOB base address */ #define GPIOB_BASE (0x4100F040u) /** Peripheral GPIOB base pointer */ #define GPIOB ((GPIO_Type *)GPIOB_BASE) /** Peripheral GPIOC base address */ #define GPIOC_BASE (0x400F0000u) /** Peripheral GPIOC base pointer */ #define GPIOC ((GPIO_Type *)GPIOC_BASE) /** Peripheral GPIOD base address */ #define GPIOD_BASE (0x400F0040u) /** Peripheral GPIOD base pointer */ #define GPIOD ((GPIO_Type *)GPIOD_BASE) /** Peripheral GPIOE base address */ #define GPIOE_BASE (0x400F0080u) /** Peripheral GPIOE base pointer */ #define GPIOE ((GPIO_Type *)GPIOE_BASE) /** Peripheral GPIOF base address */ #define GPIOF_BASE (0x400F00C0u) /** Peripheral GPIOF base pointer */ #define GPIOF ((GPIO_Type *)GPIOF_BASE) /** Array initializer of GPIO peripheral base addresses */ #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE, GPIOF_BASE } /** Array initializer of GPIO peripheral base pointers */ #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF } /*! * @} */ /* end of group GPIO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- I2S Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer * @{ */ /** I2S - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */ __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */ __O uint32_t TDR[4]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[16]; __I uint32_t TFR[4]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ uint8_t RESERVED_1[16]; __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ uint8_t RESERVED_2[36]; __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */ __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */ __I uint32_t RDR[4]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ uint8_t RESERVED_3[16]; __I uint32_t RFR[4]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_4[16]; __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ } I2S_Type; /* ---------------------------------------------------------------------------- -- I2S Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Register_Masks I2S Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define I2S_VERID_FEATURE_MASK (0xFFFFU) #define I2S_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Standard feature set. */ #define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) #define I2S_VERID_MINOR_MASK (0xFF0000U) #define I2S_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) #define I2S_VERID_MAJOR_MASK (0xFF000000U) #define I2S_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define I2S_PARAM_DATALINE_MASK (0xFU) #define I2S_PARAM_DATALINE_SHIFT (0U) /*! DATALINE - Number of Datalines */ #define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) #define I2S_PARAM_FIFO_MASK (0xF00U) #define I2S_PARAM_FIFO_SHIFT (8U) /*! FIFO - FIFO Size */ #define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) #define I2S_PARAM_FRAME_MASK (0xF0000U) #define I2S_PARAM_FRAME_SHIFT (16U) /*! FRAME - Frame Size */ #define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) /*! @} */ /*! @name TCSR - SAI Transmit Control Register */ /*! @{ */ #define I2S_TCSR_FRDE_MASK (0x1U) #define I2S_TCSR_FRDE_SHIFT (0U) /*! FRDE - FIFO Request DMA Enable * 0b0..Disables the DMA request. * 0b1..Enables the DMA request. */ #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) #define I2S_TCSR_FWDE_MASK (0x2U) #define I2S_TCSR_FWDE_SHIFT (1U) /*! FWDE - FIFO Warning DMA Enable * 0b0..Disables the DMA request. * 0b1..Enables the DMA request. */ #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) #define I2S_TCSR_FRIE_MASK (0x100U) #define I2S_TCSR_FRIE_SHIFT (8U) /*! FRIE - FIFO Request Interrupt Enable * 0b0..Disables the interrupt. * 0b1..Enables the interrupt. */ #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) #define I2S_TCSR_FWIE_MASK (0x200U) #define I2S_TCSR_FWIE_SHIFT (9U) /*! FWIE - FIFO Warning Interrupt Enable * 0b0..Disables the interrupt. * 0b1..Enables the interrupt. */ #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) #define I2S_TCSR_FEIE_MASK (0x400U) #define I2S_TCSR_FEIE_SHIFT (10U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Disables the interrupt. * 0b1..Enables the interrupt. */ #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) #define I2S_TCSR_SEIE_MASK (0x800U) #define I2S_TCSR_SEIE_SHIFT (11U) /*! SEIE - Sync Error Interrupt Enable * 0b0..Disables interrupt. * 0b1..Enables interrupt. */ #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) #define I2S_TCSR_WSIE_MASK (0x1000U) #define I2S_TCSR_WSIE_SHIFT (12U) /*! WSIE - Word Start Interrupt Enable * 0b0..Disables interrupt. * 0b1..Enables interrupt. */ #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) #define I2S_TCSR_FRF_MASK (0x10000U) #define I2S_TCSR_FRF_SHIFT (16U) /*! FRF - FIFO Request Flag * 0b0..Transmit FIFO watermark has not been reached. * 0b1..Transmit FIFO watermark has been reached. */ #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) #define I2S_TCSR_FWF_MASK (0x20000U) #define I2S_TCSR_FWF_SHIFT (17U) /*! FWF - FIFO Warning Flag * 0b0..No enabled transmit FIFO is empty. * 0b1..Enabled transmit FIFO is empty. */ #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) #define I2S_TCSR_FEF_MASK (0x40000U) #define I2S_TCSR_FEF_SHIFT (18U) /*! FEF - FIFO Error Flag * 0b0..Transmit underrun not detected. * 0b1..Transmit underrun detected. */ #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) #define I2S_TCSR_SEF_MASK (0x80000U) #define I2S_TCSR_SEF_SHIFT (19U) /*! SEF - Sync Error Flag * 0b0..Sync error not detected. * 0b1..Frame sync error detected. */ #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) #define I2S_TCSR_WSF_MASK (0x100000U) #define I2S_TCSR_WSF_SHIFT (20U) /*! WSF - Word Start Flag * 0b0..Start of word not detected. * 0b1..Start of word detected. */ #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) #define I2S_TCSR_SR_MASK (0x1000000U) #define I2S_TCSR_SR_SHIFT (24U) /*! SR - Software Reset * 0b0..No effect. * 0b1..Software reset. */ #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) #define I2S_TCSR_FR_MASK (0x2000000U) #define I2S_TCSR_FR_SHIFT (25U) /*! FR - FIFO Reset * 0b0..No effect. * 0b1..FIFO reset. */ #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) #define I2S_TCSR_BCE_MASK (0x10000000U) #define I2S_TCSR_BCE_SHIFT (28U) /*! BCE - Bit Clock Enable * 0b0..Transmit bit clock is disabled. * 0b1..Transmit bit clock is enabled. */ #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) #define I2S_TCSR_DBGE_MASK (0x20000000U) #define I2S_TCSR_DBGE_SHIFT (29U) /*! DBGE - Debug Enable * 0b0..Transmitter is disabled in Debug mode, after completing the current frame. * 0b1..Transmitter is enabled in Debug mode. */ #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) #define I2S_TCSR_STOPE_MASK (0x40000000U) #define I2S_TCSR_STOPE_SHIFT (30U) /*! STOPE - Stop Enable * 0b0..Transmitter disabled in Stop mode. * 0b1..Transmitter enabled in Stop mode. */ #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) #define I2S_TCSR_TE_MASK (0x80000000U) #define I2S_TCSR_TE_SHIFT (31U) /*! TE - Transmitter Enable * 0b0..Transmitter is disabled. * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. */ #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) /*! @} */ /*! @name TCR1 - SAI Transmit Configuration 1 Register */ /*! @{ */ #define I2S_TCR1_TFW_MASK (0xFU) #define I2S_TCR1_TFW_SHIFT (0U) /*! TFW - Transmit FIFO Watermark */ #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) /*! @} */ /*! @name TCR2 - SAI Transmit Configuration 2 Register */ /*! @{ */ #define I2S_TCR2_DIV_MASK (0xFFU) #define I2S_TCR2_DIV_SHIFT (0U) /*! DIV - Bit Clock Divide */ #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) #define I2S_TCR2_BCD_MASK (0x1000000U) #define I2S_TCR2_BCD_SHIFT (24U) /*! BCD - Bit Clock Direction * 0b0..Bit clock is generated externally in Slave mode. * 0b1..Bit clock is generated internally in Master mode. */ #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) #define I2S_TCR2_BCP_MASK (0x2000000U) #define I2S_TCR2_BCP_SHIFT (25U) /*! BCP - Bit Clock Polarity * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. */ #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) #define I2S_TCR2_MSEL_MASK (0xC000000U) #define I2S_TCR2_MSEL_SHIFT (26U) /*! MSEL - MCLK Select * 0b00..Bus Clock selected. * 0b01..Master Clock (MCLK) 1 option selected. * 0b10..Master Clock (MCLK) 2 option selected. * 0b11..Master Clock (MCLK) 3 option selected. */ #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) #define I2S_TCR2_BCI_MASK (0x10000000U) #define I2S_TCR2_BCI_SHIFT (28U) /*! BCI - Bit Clock Input * 0b0..No effect. * 0b1..Internal logic is clocked as if bit clock was externally generated. */ #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) #define I2S_TCR2_BCS_MASK (0x20000000U) #define I2S_TCR2_BCS_SHIFT (29U) /*! BCS - Bit Clock Swap * 0b0..Use the normal bit clock source. * 0b1..Swap the bit clock source. */ #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) #define I2S_TCR2_SYNC_MASK (0xC0000000U) #define I2S_TCR2_SYNC_SHIFT (30U) /*! SYNC - Synchronous Mode * 0b00..Asynchronous mode. * 0b01..Synchronous with receiver. * 0b10..Synchronous with another SAI transmitter. * 0b11..Synchronous with another SAI receiver. */ #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) /*! @} */ /*! @name TCR3 - SAI Transmit Configuration 3 Register */ /*! @{ */ #define I2S_TCR3_WDFL_MASK (0x1FU) #define I2S_TCR3_WDFL_SHIFT (0U) /*! WDFL - Word Flag Configuration */ #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) #define I2S_TCR3_TCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ #define I2S_TCR3_TCE_SHIFT (16U) /*! TCE - Transmit Channel Enable */ #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ #define I2S_TCR3_CFR_MASK (0xF000000U) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ #define I2S_TCR3_CFR_SHIFT (24U) /*! CFR - Channel FIFO Reset */ #define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ /*! @} */ /*! @name TCR4 - SAI Transmit Configuration 4 Register */ /*! @{ */ #define I2S_TCR4_FSD_MASK (0x1U) #define I2S_TCR4_FSD_SHIFT (0U) /*! FSD - Frame Sync Direction * 0b0..Frame sync is generated externally in Slave mode. * 0b1..Frame sync is generated internally in Master mode. */ #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) #define I2S_TCR4_FSP_MASK (0x2U) #define I2S_TCR4_FSP_SHIFT (1U) /*! FSP - Frame Sync Polarity * 0b0..Frame sync is active high. * 0b1..Frame sync is active low. */ #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) #define I2S_TCR4_ONDEM_MASK (0x4U) #define I2S_TCR4_ONDEM_SHIFT (2U) /*! ONDEM - On Demand Mode * 0b0..Internal frame sync is generated continuously. * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. */ #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) #define I2S_TCR4_FSE_MASK (0x8U) #define I2S_TCR4_FSE_SHIFT (3U) /*! FSE - Frame Sync Early * 0b0..Frame sync asserts with the first bit of the frame. * 0b1..Frame sync asserts one bit before the first bit of the frame. */ #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) #define I2S_TCR4_MF_MASK (0x10U) #define I2S_TCR4_MF_SHIFT (4U) /*! MF - MSB First * 0b0..LSB is transmitted first. * 0b1..MSB is transmitted first. */ #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) #define I2S_TCR4_CHMOD_MASK (0x20U) #define I2S_TCR4_CHMOD_SHIFT (5U) /*! CHMOD - Channel Mode * 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. * 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. */ #define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) #define I2S_TCR4_SYWD_MASK (0x1F00U) #define I2S_TCR4_SYWD_SHIFT (8U) /*! SYWD - Sync Width */ #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) #define I2S_TCR4_FRSZ_MASK (0x1F0000U) #define I2S_TCR4_FRSZ_SHIFT (16U) /*! FRSZ - Frame size */ #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) #define I2S_TCR4_FPACK_MASK (0x3000000U) #define I2S_TCR4_FPACK_SHIFT (24U) /*! FPACK - FIFO Packing Mode * 0b00..FIFO packing is disabled * 0b01..Reserved * 0b10..8-bit FIFO packing is enabled * 0b11..16-bit FIFO packing is enabled */ #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) #define I2S_TCR4_FCOMB_MASK (0xC000000U) #define I2S_TCR4_FCOMB_SHIFT (26U) /*! FCOMB - FIFO Combine Mode * 0b00..FIFO combine mode disabled. * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers). * 0b10..FIFO combine mode enabled on FIFO writes (by software). * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). */ #define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) #define I2S_TCR4_FCONT_MASK (0x10000000U) #define I2S_TCR4_FCONT_SHIFT (28U) /*! FCONT - FIFO Continue on Error * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. */ #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) /*! @} */ /*! @name TCR5 - SAI Transmit Configuration 5 Register */ /*! @{ */ #define I2S_TCR5_FBT_MASK (0x1F00U) #define I2S_TCR5_FBT_SHIFT (8U) /*! FBT - First Bit Shifted */ #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) #define I2S_TCR5_W0W_MASK (0x1F0000U) #define I2S_TCR5_W0W_SHIFT (16U) /*! W0W - Word 0 Width */ #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) #define I2S_TCR5_WNW_MASK (0x1F000000U) #define I2S_TCR5_WNW_SHIFT (24U) /*! WNW - Word N Width */ #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) /*! @} */ /*! @name TDR - SAI Transmit Data Register */ /*! @{ */ #define I2S_TDR_TDR_MASK (0xFFFFFFFFU) #define I2S_TDR_TDR_SHIFT (0U) /*! TDR - Transmit Data Register */ #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) /*! @} */ /* The count of I2S_TDR */ #define I2S_TDR_COUNT (4U) /*! @name TFR - SAI Transmit FIFO Register */ /*! @{ */ #define I2S_TFR_RFP_MASK (0x1FU) #define I2S_TFR_RFP_SHIFT (0U) /*! RFP - Read FIFO Pointer */ #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) #define I2S_TFR_WFP_MASK (0x1F0000U) #define I2S_TFR_WFP_SHIFT (16U) /*! WFP - Write FIFO Pointer */ #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) #define I2S_TFR_WCP_MASK (0x80000000U) #define I2S_TFR_WCP_SHIFT (31U) /*! WCP - Write Channel Pointer * 0b0..No effect. * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. */ #define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) /*! @} */ /* The count of I2S_TFR */ #define I2S_TFR_COUNT (4U) /*! @name TMR - SAI Transmit Mask Register */ /*! @{ */ #define I2S_TMR_TWM_MASK (0xFFFFFFFFU) #define I2S_TMR_TWM_SHIFT (0U) /*! TWM - Transmit Word Mask * 0b00000000000000000000000000000000..Word N is enabled. * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked. */ #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) /*! @} */ /*! @name RCSR - SAI Receive Control Register */ /*! @{ */ #define I2S_RCSR_FRDE_MASK (0x1U) #define I2S_RCSR_FRDE_SHIFT (0U) /*! FRDE - FIFO Request DMA Enable * 0b0..Disables the DMA request. * 0b1..Enables the DMA request. */ #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) #define I2S_RCSR_FWDE_MASK (0x2U) #define I2S_RCSR_FWDE_SHIFT (1U) /*! FWDE - FIFO Warning DMA Enable * 0b0..Disables the DMA request. * 0b1..Enables the DMA request. */ #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) #define I2S_RCSR_FRIE_MASK (0x100U) #define I2S_RCSR_FRIE_SHIFT (8U) /*! FRIE - FIFO Request Interrupt Enable * 0b0..Disables the interrupt. * 0b1..Enables the interrupt. */ #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) #define I2S_RCSR_FWIE_MASK (0x200U) #define I2S_RCSR_FWIE_SHIFT (9U) /*! FWIE - FIFO Warning Interrupt Enable * 0b0..Disables the interrupt. * 0b1..Enables the interrupt. */ #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) #define I2S_RCSR_FEIE_MASK (0x400U) #define I2S_RCSR_FEIE_SHIFT (10U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Disables the interrupt. * 0b1..Enables the interrupt. */ #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) #define I2S_RCSR_SEIE_MASK (0x800U) #define I2S_RCSR_SEIE_SHIFT (11U) /*! SEIE - Sync Error Interrupt Enable * 0b0..Disables interrupt. * 0b1..Enables interrupt. */ #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) #define I2S_RCSR_WSIE_MASK (0x1000U) #define I2S_RCSR_WSIE_SHIFT (12U) /*! WSIE - Word Start Interrupt Enable * 0b0..Disables interrupt. * 0b1..Enables interrupt. */ #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) #define I2S_RCSR_FRF_MASK (0x10000U) #define I2S_RCSR_FRF_SHIFT (16U) /*! FRF - FIFO Request Flag * 0b0..Receive FIFO watermark not reached. * 0b1..Receive FIFO watermark has been reached. */ #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) #define I2S_RCSR_FWF_MASK (0x20000U) #define I2S_RCSR_FWF_SHIFT (17U) /*! FWF - FIFO Warning Flag * 0b0..No enabled receive FIFO is full. * 0b1..Enabled receive FIFO is full. */ #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) #define I2S_RCSR_FEF_MASK (0x40000U) #define I2S_RCSR_FEF_SHIFT (18U) /*! FEF - FIFO Error Flag * 0b0..Receive overflow not detected. * 0b1..Receive overflow detected. */ #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) #define I2S_RCSR_SEF_MASK (0x80000U) #define I2S_RCSR_SEF_SHIFT (19U) /*! SEF - Sync Error Flag * 0b0..Sync error not detected. * 0b1..Frame sync error detected. */ #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) #define I2S_RCSR_WSF_MASK (0x100000U) #define I2S_RCSR_WSF_SHIFT (20U) /*! WSF - Word Start Flag * 0b0..Start of word not detected. * 0b1..Start of word detected. */ #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) #define I2S_RCSR_SR_MASK (0x1000000U) #define I2S_RCSR_SR_SHIFT (24U) /*! SR - Software Reset * 0b0..No effect. * 0b1..Software reset. */ #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) #define I2S_RCSR_FR_MASK (0x2000000U) #define I2S_RCSR_FR_SHIFT (25U) /*! FR - FIFO Reset * 0b0..No effect. * 0b1..FIFO reset. */ #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) #define I2S_RCSR_BCE_MASK (0x10000000U) #define I2S_RCSR_BCE_SHIFT (28U) /*! BCE - Bit Clock Enable * 0b0..Receive bit clock is disabled. * 0b1..Receive bit clock is enabled. */ #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) #define I2S_RCSR_DBGE_MASK (0x20000000U) #define I2S_RCSR_DBGE_SHIFT (29U) /*! DBGE - Debug Enable * 0b0..Receiver is disabled in Debug mode, after completing the current frame. * 0b1..Receiver is enabled in Debug mode. */ #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) #define I2S_RCSR_STOPE_MASK (0x40000000U) #define I2S_RCSR_STOPE_SHIFT (30U) /*! STOPE - Stop Enable * 0b0..Receiver disabled in Stop mode. * 0b1..Receiver enabled in Stop mode. */ #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) #define I2S_RCSR_RE_MASK (0x80000000U) #define I2S_RCSR_RE_SHIFT (31U) /*! RE - Receiver Enable * 0b0..Receiver is disabled. * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. */ #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) /*! @} */ /*! @name RCR1 - SAI Receive Configuration 1 Register */ /*! @{ */ #define I2S_RCR1_RFW_MASK (0xFU) #define I2S_RCR1_RFW_SHIFT (0U) /*! RFW - Receive FIFO Watermark */ #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) /*! @} */ /*! @name RCR2 - SAI Receive Configuration 2 Register */ /*! @{ */ #define I2S_RCR2_DIV_MASK (0xFFU) #define I2S_RCR2_DIV_SHIFT (0U) /*! DIV - Bit Clock Divide */ #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) #define I2S_RCR2_BCD_MASK (0x1000000U) #define I2S_RCR2_BCD_SHIFT (24U) /*! BCD - Bit Clock Direction * 0b0..Bit clock is generated externally in Slave mode. * 0b1..Bit clock is generated internally in Master mode. */ #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) #define I2S_RCR2_BCP_MASK (0x2000000U) #define I2S_RCR2_BCP_SHIFT (25U) /*! BCP - Bit Clock Polarity * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. */ #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) #define I2S_RCR2_MSEL_MASK (0xC000000U) #define I2S_RCR2_MSEL_SHIFT (26U) /*! MSEL - MCLK Select * 0b00..Bus Clock selected. * 0b01..Master Clock (MCLK) 1 option selected. * 0b10..Master Clock (MCLK) 2 option selected. * 0b11..Master Clock (MCLK) 3 option selected. */ #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) #define I2S_RCR2_BCI_MASK (0x10000000U) #define I2S_RCR2_BCI_SHIFT (28U) /*! BCI - Bit Clock Input * 0b0..No effect. * 0b1..Internal logic is clocked as if bit clock was externally generated. */ #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) #define I2S_RCR2_BCS_MASK (0x20000000U) #define I2S_RCR2_BCS_SHIFT (29U) /*! BCS - Bit Clock Swap * 0b0..Use the normal bit clock source. * 0b1..Swap the bit clock source. */ #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) #define I2S_RCR2_SYNC_MASK (0xC0000000U) #define I2S_RCR2_SYNC_SHIFT (30U) /*! SYNC - Synchronous Mode * 0b00..Asynchronous mode. * 0b01..Synchronous with transmitter. * 0b10..Synchronous with another SAI receiver. * 0b11..Synchronous with another SAI transmitter. */ #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) /*! @} */ /*! @name RCR3 - SAI Receive Configuration 3 Register */ /*! @{ */ #define I2S_RCR3_WDFL_MASK (0x1FU) #define I2S_RCR3_WDFL_SHIFT (0U) /*! WDFL - Word Flag Configuration */ #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) #define I2S_RCR3_RCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ #define I2S_RCR3_RCE_SHIFT (16U) /*! RCE - Receive Channel Enable */ #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ #define I2S_RCR3_CFR_MASK (0xF000000U) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ #define I2S_RCR3_CFR_SHIFT (24U) /*! CFR - Channel FIFO Reset */ #define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ /*! @} */ /*! @name RCR4 - SAI Receive Configuration 4 Register */ /*! @{ */ #define I2S_RCR4_FSD_MASK (0x1U) #define I2S_RCR4_FSD_SHIFT (0U) /*! FSD - Frame Sync Direction * 0b0..Frame Sync is generated externally in Slave mode. * 0b1..Frame Sync is generated internally in Master mode. */ #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) #define I2S_RCR4_FSP_MASK (0x2U) #define I2S_RCR4_FSP_SHIFT (1U) /*! FSP - Frame Sync Polarity * 0b0..Frame sync is active high. * 0b1..Frame sync is active low. */ #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) #define I2S_RCR4_ONDEM_MASK (0x4U) #define I2S_RCR4_ONDEM_SHIFT (2U) /*! ONDEM - On Demand Mode * 0b0..Internal frame sync is generated continuously. * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. */ #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) #define I2S_RCR4_FSE_MASK (0x8U) #define I2S_RCR4_FSE_SHIFT (3U) /*! FSE - Frame Sync Early * 0b0..Frame sync asserts with the first bit of the frame. * 0b1..Frame sync asserts one bit before the first bit of the frame. */ #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) #define I2S_RCR4_MF_MASK (0x10U) #define I2S_RCR4_MF_SHIFT (4U) /*! MF - MSB First * 0b0..LSB is received first. * 0b1..MSB is received first. */ #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) #define I2S_RCR4_SYWD_MASK (0x1F00U) #define I2S_RCR4_SYWD_SHIFT (8U) /*! SYWD - Sync Width */ #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) #define I2S_RCR4_FRSZ_MASK (0x1F0000U) #define I2S_RCR4_FRSZ_SHIFT (16U) /*! FRSZ - Frame Size */ #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) #define I2S_RCR4_FPACK_MASK (0x3000000U) #define I2S_RCR4_FPACK_SHIFT (24U) /*! FPACK - FIFO Packing Mode * 0b00..FIFO packing is disabled * 0b01..Reserved. * 0b10..8-bit FIFO packing is enabled * 0b11..16-bit FIFO packing is enabled */ #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) #define I2S_RCR4_FCOMB_MASK (0xC000000U) #define I2S_RCR4_FCOMB_SHIFT (26U) /*! FCOMB - FIFO Combine Mode * 0b00..FIFO combine mode disabled. * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers). * 0b10..FIFO combine mode enabled on FIFO reads (by software). * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). */ #define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) #define I2S_RCR4_FCONT_MASK (0x10000000U) #define I2S_RCR4_FCONT_SHIFT (28U) /*! FCONT - FIFO Continue on Error * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. */ #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) /*! @} */ /*! @name RCR5 - SAI Receive Configuration 5 Register */ /*! @{ */ #define I2S_RCR5_FBT_MASK (0x1F00U) #define I2S_RCR5_FBT_SHIFT (8U) /*! FBT - First Bit Shifted */ #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) #define I2S_RCR5_W0W_MASK (0x1F0000U) #define I2S_RCR5_W0W_SHIFT (16U) /*! W0W - Word 0 Width */ #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) #define I2S_RCR5_WNW_MASK (0x1F000000U) #define I2S_RCR5_WNW_SHIFT (24U) /*! WNW - Word N Width */ #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) /*! @} */ /*! @name RDR - SAI Receive Data Register */ /*! @{ */ #define I2S_RDR_RDR_MASK (0xFFFFFFFFU) #define I2S_RDR_RDR_SHIFT (0U) /*! RDR - Receive Data Register */ #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) /*! @} */ /* The count of I2S_RDR */ #define I2S_RDR_COUNT (4U) /*! @name RFR - SAI Receive FIFO Register */ /*! @{ */ #define I2S_RFR_RFP_MASK (0x1FU) #define I2S_RFR_RFP_SHIFT (0U) /*! RFP - Read FIFO Pointer */ #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) #define I2S_RFR_RCP_MASK (0x8000U) #define I2S_RFR_RCP_SHIFT (15U) /*! RCP - Receive Channel Pointer * 0b0..No effect. * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. */ #define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) #define I2S_RFR_WFP_MASK (0x1F0000U) #define I2S_RFR_WFP_SHIFT (16U) /*! WFP - Write FIFO Pointer */ #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) /*! @} */ /* The count of I2S_RFR */ #define I2S_RFR_COUNT (4U) /*! @name RMR - SAI Receive Mask Register */ /*! @{ */ #define I2S_RMR_RWM_MASK (0xFFFFFFFFU) #define I2S_RMR_RWM_SHIFT (0U) /*! RWM - Receive Word Mask * 0b00000000000000000000000000000000..Word N is enabled. * 0b00000000000000000000000000000001..Word N is masked. */ #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) /*! @} */ /*! * @} */ /* end of group I2S_Register_Masks */ /* I2S - Peripheral instance base addresses */ /** Peripheral I2S0 base address */ #define I2S0_BASE (0x41037000u) /** Peripheral I2S0 base pointer */ #define I2S0 ((I2S_Type *)I2S0_BASE) /** Peripheral I2S1 base address */ #define I2S1_BASE (0x410AA000u) /** Peripheral I2S1 base pointer */ #define I2S1 ((I2S_Type *)I2S1_BASE) /** Array initializer of I2S peripheral base addresses */ #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE } /** Array initializer of I2S peripheral base pointers */ #define I2S_BASE_PTRS { I2S0, I2S1 } /** Interrupt vectors for the I2S peripheral type */ #define I2S_RX_IRQS { I2S0_IRQn, I2S1_IRQn } #define I2S_TX_IRQS { I2S0_IRQn, I2S1_IRQn } /*! * @} */ /* end of group I2S_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IOMUXC0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC0_Peripheral_Access_Layer IOMUXC0 Peripheral Access Layer * @{ */ /** IOMUXC0 - Register Layout Typedef */ typedef struct { __IO uint32_t SW_MUX_CTL_PAD[52]; /**< SW_MUX_CTL_PAD SW MUX Control Register, array offset: 0x0, array step: 0x4 */ uint8_t RESERVED_0[48]; __IO uint32_t SELECT_INPUT[75]; /**< N_SELECT_INPUT_DAISY_Register, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_1[104]; __IO uint32_t SW_MUX_CTL_PAD_RESET0_b; /**< SW_MUX_CTL_PAD_RESET0_b SW MUX Control Register, offset: 0x294 */ } IOMUXC0_Type; /* ---------------------------------------------------------------------------- -- IOMUXC0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC0_Register_Masks IOMUXC0 Register Masks * @{ */ /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD SW MUX Control Register */ /*! @{ */ #define IOMUXC0_SW_MUX_CTL_PAD_PS_MASK (0x1U) #define IOMUXC0_SW_MUX_CTL_PAD_PS_SHIFT (0U) /*! PS - Pull Select Field * 0b0..pull-down * 0b1..pull-up */ #define IOMUXC0_SW_MUX_CTL_PAD_PS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_PS_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_PS_MASK) #define IOMUXC0_SW_MUX_CTL_PAD_PE_MASK (0x2U) #define IOMUXC0_SW_MUX_CTL_PAD_PE_SHIFT (1U) /*! PE - Pull Enable field * 0b0..pull disabled * 0b1..pull enabled */ #define IOMUXC0_SW_MUX_CTL_PAD_PE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_PE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_PE_MASK) #define IOMUXC0_SW_MUX_CTL_PAD_SRE_MASK (0x4U) #define IOMUXC0_SW_MUX_CTL_PAD_SRE_SHIFT (2U) /*! SRE - Slew Rate Enable Field * 0b0..Standard * 0b1..Slow */ #define IOMUXC0_SW_MUX_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_SRE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_SRE_MASK) #define IOMUXC0_SW_MUX_CTL_PAD_ODE_MASK (0x20U) #define IOMUXC0_SW_MUX_CTL_PAD_ODE_SHIFT (5U) /*! ODE - Open-drain Enable Field * 0b0..Push-pull * 0b1..Open-drain */ #define IOMUXC0_SW_MUX_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_ODE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_ODE_MASK) #define IOMUXC0_SW_MUX_CTL_PAD_DSE_MASK (0x40U) #define IOMUXC0_SW_MUX_CTL_PAD_DSE_SHIFT (6U) /*! DSE - Drive Strength Enable Field * 0b0..Standard * 0b1..Hi Drive */ #define IOMUXC0_SW_MUX_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_DSE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_DSE_MASK) #define IOMUXC0_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xF00U) #define IOMUXC0_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (8U) /*! MUX_MODE - MUX Mode Select Field. */ #define IOMUXC0_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_MUX_MODE_MASK) #define IOMUXC0_SW_MUX_CTL_PAD_LK_MASK (0x8000U) #define IOMUXC0_SW_MUX_CTL_PAD_LK_SHIFT (15U) /*! LK - Lock Field * 0b0..Disabled * 0b1..Enabled */ #define IOMUXC0_SW_MUX_CTL_PAD_LK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_LK_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_LK_MASK) #define IOMUXC0_SW_MUX_CTL_PAD_IBE_MASK (0x10000U) #define IOMUXC0_SW_MUX_CTL_PAD_IBE_SHIFT (16U) /*! IBE - Input Buffer Enable Field * 0b0..Disabled * 0b1..Enabled */ #define IOMUXC0_SW_MUX_CTL_PAD_IBE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_IBE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_IBE_MASK) #define IOMUXC0_SW_MUX_CTL_PAD_OBE_MASK (0x20000U) #define IOMUXC0_SW_MUX_CTL_PAD_OBE_SHIFT (17U) /*! OBE - Output Buffer Enable Field * 0b0..Disabled * 0b1..Enabled */ #define IOMUXC0_SW_MUX_CTL_PAD_OBE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_OBE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_OBE_MASK) #define IOMUXC0_SW_MUX_CTL_PAD_DFE_MASK (0x100000U) #define IOMUXC0_SW_MUX_CTL_PAD_DFE_SHIFT (20U) /*! DFE - Digital Filter Enable Field * 0b0..Disabled * 0b1..Enabled */ #define IOMUXC0_SW_MUX_CTL_PAD_DFE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_DFE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_DFE_MASK) #define IOMUXC0_SW_MUX_CTL_PAD_DFCS_MASK (0x200000U) #define IOMUXC0_SW_MUX_CTL_PAD_DFCS_SHIFT (21U) /*! DFCS - Digital Filter Clock Select Field * 0b0..IPG Clk * 0b1..1Khz CLK */ #define IOMUXC0_SW_MUX_CTL_PAD_DFCS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_DFCS_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_DFCS_MASK) #define IOMUXC0_SW_MUX_CTL_PAD_DFD_MASK (0x7C00000U) #define IOMUXC0_SW_MUX_CTL_PAD_DFD_SHIFT (22U) /*! DFD - Digital Filter Duration Field * 0b00000..Disabled * 0b00001..Count1 * 0b00010..Count2 * 0b00011..Count3 * 0b00100..Count4 * 0b00101..Count5 * 0b00110..Count6 * 0b00111..Count7 * 0b01000..Count8 * 0b01001..Count9 * 0b01010..Count10 * 0b01011..Count11 * 0b01100..Count12 * 0b01101..Count13 * 0b01110..Count14 * 0b01111..Count15 * 0b10000..Count16 * 0b10001..Count17 * 0b10010..Count18 * 0b10011..Count19 * 0b10100..Count20 * 0b10101..Count21 * 0b10110..Count22 * 0b10111..Count23 * 0b11000..Count24 * 0b11001..Count25 * 0b11010..Count26 * 0b11011..Count27 * 0b11100..Count28 * 0b11101..Count29 * 0b11110..Count30 * 0b11111..Count31 */ #define IOMUXC0_SW_MUX_CTL_PAD_DFD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_DFD_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_DFD_MASK) /*! @} */ /* The count of IOMUXC0_SW_MUX_CTL_PAD */ #define IOMUXC0_SW_MUX_CTL_PAD_COUNT (52U) /*! @name SELECT_INPUT - N_SELECT_INPUT_DAISY_Register */ /*! @{ */ #define IOMUXC0_SELECT_INPUT_DAISY_MASK (0x7U) #define IOMUXC0_SELECT_INPUT_DAISY_SHIFT (0U) /*! DAISY - Selects source pad for Module Input Function. Refer to "Input SSS" column from "Input Mux" tab on IOMUX Sheet. */ #define IOMUXC0_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC0_SELECT_INPUT_DAISY_MASK) #define IOMUXC0_SELECT_INPUT_INVERSION_MASK (0x8000U) #define IOMUXC0_SELECT_INPUT_INVERSION_SHIFT (15U) /*! INVERSION - Controls the inversion of the pad->module input to instance * 0b0..Disable inversion. * 0b1..Enable inversion. */ #define IOMUXC0_SELECT_INPUT_INVERSION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SELECT_INPUT_INVERSION_SHIFT)) & IOMUXC0_SELECT_INPUT_INVERSION_MASK) /*! @} */ /* The count of IOMUXC0_SELECT_INPUT */ #define IOMUXC0_SELECT_INPUT_COUNT (75U) /*! @name SW_MUX_CTL_PAD_RESET0_b - SW_MUX_CTL_PAD_RESET0_b SW MUX Control Register */ /*! @{ */ #define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PS_MASK (0x1U) #define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PS_SHIFT (0U) /*! PS - Pull Select Field * 0b0..pull-down * 0b1..pull-up */ #define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PS_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PS_MASK) #define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PE_MASK (0x2U) #define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PE_SHIFT (1U) /*! PE - Pull Enable field * 0b0..pull disabled * 0b1..pull enabled */ #define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_PE_MASK) #define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_SRE_MASK (0x4U) #define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_SRE_SHIFT (2U) /*! SRE - Slew Rate Enable Field * 0b0..Standard * 0b1..Slow */ #define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_SRE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_SRE_MASK) #define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_ODE_MASK (0x20U) #define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_ODE_SHIFT (5U) /*! ODE - Open-drain Enable Field * 0b0..Push-pull * 0b1..Open-drain */ #define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_ODE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_ODE_MASK) #define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_DSE_MASK (0x40U) #define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_DSE_SHIFT (6U) /*! DSE - Drive Strength Enable Field * 0b0..Standard * 0b1..Hi Drive */ #define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_DSE_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_DSE_MASK) #define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_LK_MASK (0x8000U) #define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_LK_SHIFT (15U) /*! LK - Lock Field * 0b0..Disabled * 0b1..Enabled */ #define IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_LK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_LK_SHIFT)) & IOMUXC0_SW_MUX_CTL_PAD_RESET0_b_LK_MASK) /*! @} */ /*! * @} */ /* end of group IOMUXC0_Register_Masks */ /* IOMUXC0 - Peripheral instance base addresses */ /** Peripheral IOMUXC0 base address */ #define IOMUXC0_BASE (0x4103D000u) /** Peripheral IOMUXC0 base pointer */ #define IOMUXC0 ((IOMUXC0_Type *)IOMUXC0_BASE) /** Array initializer of IOMUXC0 peripheral base addresses */ #define IOMUXC0_BASE_ADDRS { IOMUXC0_BASE } /** Array initializer of IOMUXC0 peripheral base pointers */ #define IOMUXC0_BASE_PTRS { IOMUXC0 } /*! * @} */ /* end of group IOMUXC0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IOMUXC1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC1_Peripheral_Access_Layer IOMUXC1 Peripheral Access Layer * @{ */ /** IOMUXC1 - Register Layout Typedef */ typedef struct { __IO uint32_t SW_MUX_CTL_PAD[116]; /**< SW_MUX_CTL_PAD SW MUX Control Register, array offset: 0x0, array step: 0x4 */ uint8_t RESERVED_0[48]; __IO uint32_t SELECT_INPUT[80]; /**< N_SELECT_INPUT DAISY Register, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_1[92]; __IO uint32_t SW_MUX_CTL_PAD_RESET1_b; /**< SW_MUX_CTL_PAD_RESET1_b SW MUX Control Register, offset: 0x39C */ } IOMUXC1_Type; /* ---------------------------------------------------------------------------- -- IOMUXC1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC1_Register_Masks IOMUXC1 Register Masks * @{ */ /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD SW MUX Control Register */ /*! @{ */ #define IOMUXC1_SW_MUX_CTL_PAD_PS_MASK (0x1U) #define IOMUXC1_SW_MUX_CTL_PAD_PS_SHIFT (0U) /*! PS - Pull Select Field * 0b0..pull-down * 0b1..pull-up */ #define IOMUXC1_SW_MUX_CTL_PAD_PS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_PS_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_PS_MASK) #define IOMUXC1_SW_MUX_CTL_PAD_PE_MASK (0x2U) #define IOMUXC1_SW_MUX_CTL_PAD_PE_SHIFT (1U) /*! PE - Pull-up Enable Field * 0b0..pull disabled * 0b1..pull enabled */ #define IOMUXC1_SW_MUX_CTL_PAD_PE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_PE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_PE_MASK) #define IOMUXC1_SW_MUX_CTL_PAD_SRE_MASK (0x4U) #define IOMUXC1_SW_MUX_CTL_PAD_SRE_SHIFT (2U) /*! SRE - Slew Rate Enable Field * 0b0..Standard * 0b1..Slow */ #define IOMUXC1_SW_MUX_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_SRE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_SRE_MASK) #define IOMUXC1_SW_MUX_CTL_PAD_ODE_MASK (0x20U) #define IOMUXC1_SW_MUX_CTL_PAD_ODE_SHIFT (5U) /*! ODE - Open-drain Enable Field * 0b0..Push-pull * 0b1..Open-drain */ #define IOMUXC1_SW_MUX_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_ODE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_ODE_MASK) #define IOMUXC1_SW_MUX_CTL_PAD_DSE_MASK (0x40U) #define IOMUXC1_SW_MUX_CTL_PAD_DSE_SHIFT (6U) /*! DSE - Drive Strength Enable Field * 0b0..Standard * 0b1..Hi Drive */ #define IOMUXC1_SW_MUX_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_DSE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_DSE_MASK) #define IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xF00U) #define IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (8U) /*! MUX_MODE - MUX Mode Select Field. */ #define IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE_MASK) #define IOMUXC1_SW_MUX_CTL_PAD_LK_MASK (0x8000U) #define IOMUXC1_SW_MUX_CTL_PAD_LK_SHIFT (15U) /*! LK - Lock Field * 0b0..Disabled * 0b1..Enabled */ #define IOMUXC1_SW_MUX_CTL_PAD_LK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_LK_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_LK_MASK) #define IOMUXC1_SW_MUX_CTL_PAD_IBE_MASK (0x10000U) #define IOMUXC1_SW_MUX_CTL_PAD_IBE_SHIFT (16U) /*! IBE - Input Buffer Enable Field * 0b0..Disabled * 0b1..Enabled */ #define IOMUXC1_SW_MUX_CTL_PAD_IBE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_IBE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_IBE_MASK) #define IOMUXC1_SW_MUX_CTL_PAD_OBE_MASK (0x20000U) #define IOMUXC1_SW_MUX_CTL_PAD_OBE_SHIFT (17U) /*! OBE - Output Buffer Enable Field * 0b0..Disabled * 0b1..Enabled */ #define IOMUXC1_SW_MUX_CTL_PAD_OBE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_OBE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_OBE_MASK) /*! @} */ /* The count of IOMUXC1_SW_MUX_CTL_PAD */ #define IOMUXC1_SW_MUX_CTL_PAD_COUNT (116U) /*! @name SELECT_INPUT - N_SELECT_INPUT DAISY Register */ /*! @{ */ #define IOMUXC1_SELECT_INPUT_DAISY_MASK (0x7U) #define IOMUXC1_SELECT_INPUT_DAISY_SHIFT (0U) /*! DAISY - Selects source pad for Module Input Function. Refer to "Input SSS" column from "Input Mux" tab on IOMUX Sheet. */ #define IOMUXC1_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC1_SELECT_INPUT_DAISY_MASK) #define IOMUXC1_SELECT_INPUT_INVERSION_MASK (0x8000U) #define IOMUXC1_SELECT_INPUT_INVERSION_SHIFT (15U) /*! INVERSION - Control the inversion of the pad->module input * 0b0..Disable inversion. * 0b1..Enable inversion. */ #define IOMUXC1_SELECT_INPUT_INVERSION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SELECT_INPUT_INVERSION_SHIFT)) & IOMUXC1_SELECT_INPUT_INVERSION_MASK) /*! @} */ /* The count of IOMUXC1_SELECT_INPUT */ #define IOMUXC1_SELECT_INPUT_COUNT (80U) /*! @name SW_MUX_CTL_PAD_RESET1_b - SW_MUX_CTL_PAD_RESET1_b SW MUX Control Register */ /*! @{ */ #define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PS_MASK (0x1U) #define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PS_SHIFT (0U) /*! PS - Pull Select Field * 0b0..pull-down * 0b1..pull-up */ #define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PS_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PS_MASK) #define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PE_MASK (0x2U) #define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PE_SHIFT (1U) /*! PE - Pull-up Enable Field * 0b0..pull disabled * 0b1..pull enabled */ #define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_PE_MASK) #define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_SRE_MASK (0x4U) #define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_SRE_SHIFT (2U) /*! SRE - Slew Rate Enable Field * 0b0..Standard * 0b1..Slow */ #define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_SRE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_SRE_MASK) #define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_ODE_MASK (0x20U) #define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_ODE_SHIFT (5U) /*! ODE - Open-drain Enable Field * 0b0..Push-pull * 0b1..Open-drain */ #define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_ODE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_ODE_MASK) #define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_DSE_MASK (0x40U) #define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_DSE_SHIFT (6U) /*! DSE - Drive Strength Enable Field * 0b0..Standard * 0b1..Hi Drive */ #define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_DSE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_DSE_MASK) #define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_LK_MASK (0x8000U) #define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_LK_SHIFT (15U) /*! LK - Lock Field * 0b0..Disabled * 0b1..Enabled */ #define IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_LK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_LK_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_RESET1_b_LK_MASK) /*! @} */ /*! * @} */ /* end of group IOMUXC1_Register_Masks */ /* IOMUXC1 - Peripheral instance base addresses */ /** Peripheral IOMUXC1 base address */ #define IOMUXC1_BASE (0x40AC0000u) /** Peripheral IOMUXC1 base pointer */ #define IOMUXC1 ((IOMUXC1_Type *)IOMUXC1_BASE) /** Array initializer of IOMUXC1 peripheral base addresses */ #define IOMUXC1_BASE_ADDRS { IOMUXC1_BASE } /** Array initializer of IOMUXC1 peripheral base pointers */ #define IOMUXC1_BASE_PTRS { IOMUXC1 } /*! * @} */ /* end of group IOMUXC1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IOMUXC1_DDR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC1_DDR_Peripheral_Access_Layer IOMUXC1_DDR Peripheral Access Layer * @{ */ /** IOMUXC1_DDR - Register Layout Typedef */ typedef struct { __IO uint32_t SW_PAD_CTL_PAD_DDR_DQ[32]; /**< SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register, array offset: 0x0, array step: 0x4 */ __IO uint32_t SW_PAD_CTL_PAD_DDR_DQS[4]; /**< SW_PAD_CTL_PAD_DDR_DQSn SW PAD Control Register, array offset: 0x80, array step: 0x4 */ __IO uint32_t SW_PAD_CTL_PAD_DDR_DQM[4]; /**< SW_PAD_CTL_PAD_DDR_DQMn SW PAD Control Register, array offset: 0x90, array step: 0x4 */ __IO uint32_t SW_PAD_CTL_PAD_DDR[12]; /**< SW_PAD_CTL_PAD_DDR_n SW PAD Control Register, array offset: 0xA0, array step: 0x4 */ __IO uint32_t SW_PAD_CTL_PAD_DDR_CKE[2]; /**< SW_PAD_CTL_PAD_DDR_CKEn SW PAD Control Register, array offset: 0xD0, array step: 0x4 */ __IO uint32_t SW_PAD_CTL_PAD_DDR_CLK0; /**< SW_PAD_CTL_PAD_DDR_CLK0 SW PAD Control Register, offset: 0xD8 */ __IO uint32_t SW_PAD_CTL_PAD_DDR_ODT; /**< SW_PAD_CTL_PAD_DDR_ODT SW PAD Control Register, offset: 0xDC */ __IO uint32_t SW_PAD_CTL_PAD_DDR_ZQ[2]; /**< SW_PAD_CTL_PAD_DDR_ZQn SW PAD Control Register, array offset: 0xE0, array step: 0x4 */ __IO uint32_t SW_PAD_CTL_PAD_HSIC_DATA; /**< SW_PAD_CTL_PAD_HSIC_DATA SW PAD Control Register, offset: 0xE8 */ __IO uint32_t SW_PAD_CTL_PAD_HSIC_STROBE; /**< SW_PAD_CTL_PAD_HSIC_STROBE SW PAD Control Register, offset: 0xEC */ __IO uint32_t SW_PAD_CTL_GRP_PUE; /**< SW_PAD_CTL_GRP_PUE SW GRP Register, offset: 0xF0 */ __IO uint32_t SW_PAD_CTL_GRP_PUE_DAT; /**< SW_PAD_CTL_GRP_PUE_DAT SW GRP Register, offset: 0xF4 */ __IO uint32_t SW_PAD_CTL_GRP_PKE; /**< SW_PAD_CTL_GRP_PKE SW GRP Register, offset: 0xF8 */ __IO uint32_t SW_PAD_CTL_GRP_PKE_DAT; /**< SW_PAD_CTL_GRP_PKE_DAT SW GRP Register, offset: 0xFC */ __IO uint32_t SW_PAD_CTL_GRP_PUS; /**< SW_PAD_CTL_GRP_PUS SW GRP Register, offset: 0x100 */ __IO uint32_t SW_PAD_CTL_GRP_DS_ADDR; /**< SW_PAD_CTL_GRP_DS_ADDR SW GRP Register, offset: 0x104 */ __IO uint32_t SW_PAD_CTL_GRP_DS_CTRL; /**< SW_PAD_CTL_GRP_DS_CTRL SW GRP Register, offset: 0x108 */ __IO uint32_t SW_PAD_CTL_GRP_DS_DAT0; /**< SW_PAD_CTL_GRP_DS_DAT0 SW GRP Register, offset: 0x10C */ __IO uint32_t SW_PAD_CTL_GRP_DS_DAT1; /**< SW_PAD_CTL_GRP_DS_DAT1 SW GRP Register, offset: 0x110 */ __IO uint32_t SW_PAD_CTL_GRP_DS_DAT2; /**< SW_PAD_CTL_GRP_DS_DAT2 SW GRP Register, offset: 0x114 */ __IO uint32_t SW_PAD_CTL_GRP_DS_DAT3; /**< SW_PAD_CTL_GRP_DS_DAT3 SW GRP Register, offset: 0x118 */ __IO uint32_t SW_PAD_CTL_GRP_HYS; /**< SW_PAD_CTL_GRP_HYS SW GRP Register, offset: 0x11C */ __IO uint32_t SW_PAD_CTL_GRP_INSEL_DAT; /**< SW_PAD_CTL_GRP_INSEL_DAT SW GRP Register, offset: 0x120 */ __IO uint32_t SW_PAD_CTL_GRP_INSEL_DQS; /**< SW_PAD_CTL_GRP_INSEL_DQS SW GRP Register, offset: 0x124 */ __IO uint32_t SW_PAD_CTL_GRP_DDRTYPE; /**< SW_PAD_CTL_GRP_DDRTYPE SW GRP Register, offset: 0x128 */ } IOMUXC1_DDR_Type; /* ---------------------------------------------------------------------------- -- IOMUXC1_DDR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC1_DDR_Register_Masks IOMUXC1_DDR Register Masks * @{ */ /*! @name SW_PAD_CTL_PAD_DDR_DQ - SW_PAD_CTL_PAD_DDR_DQn SW PAD Control Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DCYCLE_TRIM_MASK (0x3000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DCYCLE_TRIM_SHIFT (12U) /*! DCYCLE_TRIM - Duty Cycle Control Field * 0b00..no duty cycle change * 0b01..duty cycle increased ~3.7% * 0b10..duty cycle decreased ~3.7% * 0b11..no duty cycle change */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DCYCLE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DCYCLE_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DCYCLE_TRIM_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DDR_TRIM_MASK (0xC000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DDR_TRIM_SHIFT (14U) /*! DDR_TRIM - Output Driver Delay Trim Field * 0b00..0pS * 0b01..50pS * 0b10..100pS * 0b11..150pS */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DDR_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DDR_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_DDR_TRIM_MASK) /*! @} */ /* The count of IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQ_COUNT (32U) /*! @name SW_PAD_CTL_PAD_DDR_DQS - SW_PAD_CTL_PAD_DDR_DQSn SW PAD Control Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUE_MASK (0x4U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUE_SHIFT (2U) /*! PUE - Pull Up/Down or Keeper Selection Field * 0b0..Keeper Selected * 0b1..Pull Up/Down Selected */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUE_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PKE_MASK (0x8U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PKE_SHIFT (3U) /*! PKE - Pull Up/Pull Down/Keeper Enable Field * 0b0..Pull Up/Down and Keeper Disabled * 0b1..Pull Up/Down or Keeper Enabled */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PKE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PKE_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUS_MASK (0x30U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUS_SHIFT (4U) /*! PUS - Pull Up/Down Resistance Select Field * 0b00..100 kOhm Pull Down * 0b01..47 Kohm Pull Up * 0b10..100 kOhm Pull Up * 0b11..22 kOhm Pull Up */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUS_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_PUS_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DSE_MASK (0x1C0U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DSE_SHIFT (6U) /*! DSE - Output Drive Strength Select Field * 0b000..Driver Disabled * 0b001..240 Ohm * 0b010..240/2=120 Ohm * 0b011..240/3=80 Ohm * 0b100..240/4=60 Ohm * 0b101..240/5=48 Ohm * 0b110..240/6=40 Ohm * 0b111..240/7=34 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DSE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DSE_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_CRPOINT_TRIM_MASK (0xC00U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_CRPOINT_TRIM_SHIFT (10U) /*! CRPOINT_TRIM - Crosspoint Adjustment Field * 0b00..no output crosspoint (Vix) change * 0b01..100mV Vix shift down * 0b10..100mV Vix shift up * 0b11..200mV Vix shift up */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_CRPOINT_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_CRPOINT_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_CRPOINT_TRIM_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DCYCLE_TRIM_MASK (0x3000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DCYCLE_TRIM_SHIFT (12U) /*! DCYCLE_TRIM - Duty Cycle Control Field * 0b00..no duty cycle change * 0b01..duty cycle increased ~3.7% * 0b10..duty cycle decreased ~3.7% * 0b11..no duty cycle change */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DCYCLE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DCYCLE_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_DCYCLE_TRIM_MASK) /*! @} */ /* The count of IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQS_COUNT (4U) /*! @name SW_PAD_CTL_PAD_DDR_DQM - SW_PAD_CTL_PAD_DDR_DQMn SW PAD Control Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DSE_MASK (0x1C0U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DSE_SHIFT (6U) /*! DSE - Output Drive Strength Select Field * 0b000..Driver Disabled * 0b001..240 Ohm * 0b010..240/2=120 Ohm * 0b011..240/3=80 Ohm * 0b100..240/4=60 Ohm * 0b101..240/5=48 Ohm * 0b110..240/6=40 Ohm * 0b111..240/7=34 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DSE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DSE_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_HYS_MASK (0x200U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_HYS_SHIFT (9U) /*! HYS - Input Hysteresis Field * 0b0..CMOS input * 0b1..Schmitt trigger input */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_HYS_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_HYS_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DCYCLE_TRIM_MASK (0x3000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DCYCLE_TRIM_SHIFT (12U) /*! DCYCLE_TRIM - Duty Cycle Control Field * 0b00..no duty cycle change * 0b01..duty cycle increased ~3.7% * 0b10..duty cycle decreased ~3.7% * 0b11..no duty cycle change */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DCYCLE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DCYCLE_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DCYCLE_TRIM_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_TRIM_MASK (0xC000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_TRIM_SHIFT (14U) /*! DDR_TRIM - Output Driver Delay Trim Field * 0b00..0pS * 0b01..50pS * 0b10..100pS * 0b11..150pS */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_TRIM_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_INPUT_MASK (0x10000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_INPUT_SHIFT (16U) /*! DDR_INPUT - DDR/CMOS Input Select Field * 0b0..CMOS input type * 0b1..Differential input mode */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_INPUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_INPUT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_INPUT_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_ODT_MASK (0x380000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_ODT_SHIFT (19U) /*! DDR_ODT - On Die Termination Select Field * 0b000..No Termination * 0b001..120 Ohm * 0b010..60 Ohm * 0b011..40 Ohm * 0b100..30 Ohm * 0b101..24 Ohm * 0b110..20 Ohm * 0b111..17 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_ODT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_ODT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_DDR_ODT_MASK) /*! @} */ /* The count of IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DQM_COUNT (4U) /*! @name SW_PAD_CTL_PAD_DDR - SW_PAD_CTL_PAD_DDR_n SW PAD Control Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_HYS_MASK (0x200U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_HYS_SHIFT (9U) /*! HYS - Input Hysteresis Field * 0b0..CMOS input * 0b1..Schmitt trigger input */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_HYS_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_HYS_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DCYCLE_TRIM_MASK (0x3000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DCYCLE_TRIM_SHIFT (12U) /*! DCYCLE_TRIM - Duty Cycle Control Field * 0b00..no duty cycle change * 0b01..duty cycle increased ~3.7% * 0b10..duty cycle decreased ~3.7% * 0b11..no duty cycle change */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DCYCLE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DCYCLE_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DCYCLE_TRIM_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_TRIM_MASK (0xC000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_TRIM_SHIFT (14U) /*! DDR_TRIM - Output Driver Delay Trim Field * 0b00..0pS * 0b01..50pS * 0b10..100pS * 0b11..150pS */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_TRIM_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_INPUT_MASK (0x10000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_INPUT_SHIFT (16U) /*! DDR_INPUT - DDR/CMOS Input Select Field * 0b0..CMOS input type * 0b1..Differential input mode */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_INPUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_INPUT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_INPUT_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_ODT_MASK (0x380000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_ODT_SHIFT (19U) /*! DDR_ODT - On Die Termination Select Field * 0b000..No Termination * 0b001..120 Ohm * 0b010..60 Ohm * 0b011..40 Ohm * 0b100..30 Ohm * 0b101..24 Ohm * 0b110..20 Ohm * 0b111..17 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_ODT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_ODT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_DDR_ODT_MASK) /*! @} */ /* The count of IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_COUNT (12U) /*! @name SW_PAD_CTL_PAD_DDR_CKE - SW_PAD_CTL_PAD_DDR_CKEn SW PAD Control Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_PUE_MASK (0x4U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_PUE_SHIFT (2U) /*! PUE - Pull Up/Down or Keeper Selection Field * 0b0..Keeper Selected * 0b1..Pull Up/Down Selected */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_PUE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_PUE_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_PKE_MASK (0x8U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_PKE_SHIFT (3U) /*! PKE - Pull Up/Pull Down/Keeper Enable Field * 0b0..Pull Up/Down and Keeper Disabled * 0b1..Pull Up/Down or Keeper Enabled */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_PKE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_PKE_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_PUS_MASK (0x30U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_PUS_SHIFT (4U) /*! PUS - Pull Up/Down Resistance Select Field * 0b00..100 kOhm Pull Down * 0b01..47 Kohm Pull Up * 0b10..100 kOhm Pull Up * 0b11..22 kOhm Pull Up */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_PUS_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_PUS_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_HYS_MASK (0x200U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_HYS_SHIFT (9U) /*! HYS - Input Hysteresis Field * 0b0..CMOS input * 0b1..Schmitt trigger input */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_HYS_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_HYS_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DCYCLE_TRIM_MASK (0x3000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DCYCLE_TRIM_SHIFT (12U) /*! DCYCLE_TRIM - Duty Cycle Control Field * 0b00..no duty cycle change * 0b01..duty cycle increased ~3.7% * 0b10..duty cycle decreased ~3.7% * 0b11..no duty cycle change */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DCYCLE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DCYCLE_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DCYCLE_TRIM_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DDR_TRIM_MASK (0xC000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DDR_TRIM_SHIFT (14U) /*! DDR_TRIM - Output Driver Delay Trim Field * 0b00..0pS * 0b01..50pS * 0b10..100pS * 0b11..150pS */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DDR_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DDR_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DDR_TRIM_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DDR_INPUT_MASK (0x10000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DDR_INPUT_SHIFT (16U) /*! DDR_INPUT - DDR/CMOS Input Select Field * 0b0..CMOS input type * 0b1..Differential input mode */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DDR_INPUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DDR_INPUT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DDR_INPUT_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DDR_ODT_MASK (0x380000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DDR_ODT_SHIFT (19U) /*! DDR_ODT - On Die Termination Select Field * 0b000..No Termination * 0b001..120 Ohm * 0b010..60 Ohm * 0b011..40 Ohm * 0b100..30 Ohm * 0b101..24 Ohm * 0b110..20 Ohm * 0b111..17 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DDR_ODT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DDR_ODT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_DDR_ODT_MASK) /*! @} */ /* The count of IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CKE_COUNT (2U) /*! @name SW_PAD_CTL_PAD_DDR_CLK0 - SW_PAD_CTL_PAD_DDR_CLK0 SW PAD Control Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_PUE_MASK (0x4U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_PUE_SHIFT (2U) /*! PUE - Pull Up/Down or Keeper Selection Field * 0b0..Keeper Selected * 0b1..Pull Up/Down Selected */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_PUE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_PUE_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_PKE_MASK (0x8U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_PKE_SHIFT (3U) /*! PKE - Pull Up/Pull Down/Keeper Enable Field * 0b0..Pull Up/Down and Keeper Disabled * 0b1..Pull Up/Down or Keeper Enabled */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_PKE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_PKE_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_PUS_MASK (0x30U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_PUS_SHIFT (4U) /*! PUS - Pull Up/Down Resistance Select Field * 0b00..100 kOhm Pull Down * 0b01..47 Kohm Pull Up * 0b10..100 kOhm Pull Up * 0b11..22 kOhm Pull Up */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_PUS_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_PUS_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DSE_MASK (0x1C0U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DSE_SHIFT (6U) /*! DSE - Output Drive Strength Select Field * 0b000..Driver Disabled * 0b001..240 Ohm * 0b010..240/2=120 Ohm * 0b011..240/3=80 Ohm * 0b100..240/4=60 Ohm * 0b101..240/5=48 Ohm * 0b110..240/6=40 Ohm * 0b111..240/7=34 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DSE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DSE_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_HYS_MASK (0x200U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_HYS_SHIFT (9U) /*! HYS - Input Hysteresis Field * 0b0..CMOS input * 0b1..Schmitt trigger input */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_HYS_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_HYS_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_CRPOINT_TRIM_MASK (0xC00U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_CRPOINT_TRIM_SHIFT (10U) /*! CRPOINT_TRIM - Crosspoint Adjustment Field * 0b00..no output crosspoint (Vix) change * 0b01..100mV Vix shift down * 0b10..100mV Vix shift up * 0b11..200mV Vix shift up */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_CRPOINT_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_CRPOINT_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_CRPOINT_TRIM_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DCYCLE_TRIM_MASK (0x3000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DCYCLE_TRIM_SHIFT (12U) /*! DCYCLE_TRIM - Duty Cycle Control Field * 0b00..no duty cycle change * 0b01..duty cycle increased ~3.7% * 0b10..duty cycle decreased ~3.7% * 0b11..no duty cycle change */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DCYCLE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DCYCLE_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DCYCLE_TRIM_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DDR_INPUT_MASK (0x10000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DDR_INPUT_SHIFT (16U) /*! DDR_INPUT - DDR/CMOS Input Select Field * 0b0..CMOS input type * 0b1..Differential input mode */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DDR_INPUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DDR_INPUT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DDR_INPUT_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DDR_ODT_MASK (0x380000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DDR_ODT_SHIFT (19U) /*! DDR_ODT - On Die Termination Select Field * 0b000..No Termination * 0b001..120 Ohm * 0b010..60 Ohm * 0b011..40 Ohm * 0b100..30 Ohm * 0b101..24 Ohm * 0b110..20 Ohm * 0b111..17 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DDR_ODT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DDR_ODT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_CLK0_DDR_ODT_MASK) /*! @} */ /*! @name SW_PAD_CTL_PAD_DDR_ODT - SW_PAD_CTL_PAD_DDR_ODT SW PAD Control Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_PUE_MASK (0x4U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_PUE_SHIFT (2U) /*! PUE - Pull Up/Down or Keeper Selection Field * 0b0..Keeper Selected * 0b1..Pull Up/Down Selected */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_PUE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_PUE_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_PKE_MASK (0x8U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_PKE_SHIFT (3U) /*! PKE - Pull Up/Pull Down/Keeper Enable Field * 0b0..Pull Up/Down and Keeper Disabled * 0b1..Pull Up/Down or Keeper Enabled */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_PKE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_PKE_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_PUS_MASK (0x30U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_PUS_SHIFT (4U) /*! PUS - Pull Up/Down Resistance Select Field * 0b00..100 kOhm Pull Down * 0b01..47 Kohm Pull Up * 0b10..100 kOhm Pull Up * 0b11..22 kOhm Pull Up */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_PUS_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_PUS_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DSE_MASK (0x1C0U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DSE_SHIFT (6U) /*! DSE - Output Drive Strength Select Field * 0b000..Driver Disabled * 0b001..240 Ohm * 0b010..240/2=120 Ohm * 0b011..240/3=80 Ohm * 0b100..240/4=60 Ohm * 0b101..240/5=48 Ohm * 0b110..240/6=40 Ohm * 0b111..240/7=34 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DSE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DSE_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_HYS_MASK (0x200U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_HYS_SHIFT (9U) /*! HYS - Input Hysteresis Field * 0b0..CMOS input * 0b1..Schmitt trigger input */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_HYS_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_HYS_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DCYCLE_TRIM_MASK (0x3000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DCYCLE_TRIM_SHIFT (12U) /*! DCYCLE_TRIM - Duty Cycle Control Field * 0b00..no duty cycle change * 0b01..duty cycle increased ~3.7% * 0b10..duty cycle decreased ~3.7% * 0b11..no duty cycle change */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DCYCLE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DCYCLE_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DCYCLE_TRIM_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DDR_TRIM_MASK (0xC000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DDR_TRIM_SHIFT (14U) /*! DDR_TRIM - Output Driver Delay Trim Field * 0b00..0pS * 0b01..50pS * 0b10..100pS * 0b11..150pS */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DDR_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DDR_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DDR_TRIM_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DDR_INPUT_MASK (0x10000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DDR_INPUT_SHIFT (16U) /*! DDR_INPUT - DDR/CMOS Input Select Field * 0b0..CMOS input type * 0b1..Differential input mode */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DDR_INPUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DDR_INPUT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DDR_INPUT_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DDR_ODT_MASK (0x380000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DDR_ODT_SHIFT (19U) /*! DDR_ODT - On Die Termination Select Field * 0b000..No Termination * 0b001..120 Ohm * 0b010..60 Ohm * 0b011..40 Ohm * 0b100..30 Ohm * 0b101..24 Ohm * 0b110..20 Ohm * 0b111..17 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DDR_ODT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DDR_ODT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ODT_DDR_ODT_MASK) /*! @} */ /*! @name SW_PAD_CTL_PAD_DDR_ZQ - SW_PAD_CTL_PAD_DDR_ZQn SW PAD Control Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ZQ_DDR_SELECT_MASK (0x60000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ZQ_DDR_SELECT_SHIFT (17U) /*! DDR_SELECT - DDR Select Field * 0b00..DDR3 mode * 0b01..reserved * 0b10..LPDDR2/LPDDR3 modes * 0b11..DDR_SELECT_3_HSIC_USB mode */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ZQ_DDR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ZQ_DDR_SELECT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ZQ_DDR_SELECT_MASK) /*! @} */ /* The count of IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ZQ */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_DDR_ZQ_COUNT (2U) /*! @name SW_PAD_CTL_PAD_HSIC_DATA - SW_PAD_CTL_PAD_HSIC_DATA SW PAD Control Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_PUE_MASK (0x4U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_PUE_SHIFT (2U) /*! PUE - Pull Up/Down or Keeper Selection Field * 0b0..Keeper Selected * 0b1..Pull Up/Down Selected */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_PUE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_PUE_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_PUS_MASK (0x30U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_PUS_SHIFT (4U) /*! PUS - Pull Up/Down Resistance Select Field * 0b00..100 kOhm Pull Down * 0b01..47 Kohm Pull Up * 0b10..100 kOhm Pull Up * 0b11..22 kOhm Pull Up */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_PUS_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_PUS_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DSE_MASK (0x1C0U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DSE_SHIFT (6U) /*! DSE - Output Drive Strength Select Field * 0b000..Driver Disabled * 0b001..240 Ohm * 0b010..240/2=120 Ohm * 0b011..240/3=80 Ohm * 0b100..240/4=60 Ohm * 0b101..240/5=48 Ohm * 0b110..240/6=40 Ohm * 0b111..240/7=34 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DSE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DSE_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_HYS_MASK (0x200U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_HYS_SHIFT (9U) /*! HYS - Input Hysteresis Field * 0b0..CMOS input * 0b1..Schmitt trigger input */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_HYS_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_HYS_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DCYCLE_TRIM_MASK (0x3000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DCYCLE_TRIM_SHIFT (12U) /*! DCYCLE_TRIM - Duty Cycle Control Field * 0b00..no duty cycle change * 0b01..duty cycle increased ~3.7% * 0b10..duty cycle decreased ~3.7% * 0b11..no duty cycle change */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DCYCLE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DCYCLE_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DCYCLE_TRIM_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DDR_TRIM_MASK (0xC000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DDR_TRIM_SHIFT (14U) /*! DDR_TRIM - Output Driver Delay Trim Field * 0b00..0pS * 0b01..50pS * 0b10..100pS * 0b11..150pS */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DDR_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DDR_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DDR_TRIM_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DDR_SELECT_MASK (0x60000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DDR_SELECT_SHIFT (17U) /*! DDR_SELECT - DDR Select Field * 0b00..DDR3 mode * 0b01..reserved * 0b10..LPDDR2/LPDDR3 modes * 0b11..DDR_SELECT_3_HSIC_USB mode */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DDR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DDR_SELECT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DDR_SELECT_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DDR_ODT_MASK (0x380000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DDR_ODT_SHIFT (19U) /*! DDR_ODT - On Die Termination Select Field * 0b000..No Termination * 0b001..120 Ohm * 0b010..60 Ohm * 0b011..40 Ohm * 0b100..30 Ohm * 0b101..24 Ohm * 0b110..20 Ohm * 0b111..17 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DDR_ODT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DDR_ODT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_DATA_DDR_ODT_MASK) /*! @} */ /*! @name SW_PAD_CTL_PAD_HSIC_STROBE - SW_PAD_CTL_PAD_HSIC_STROBE SW PAD Control Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_PUE_MASK (0x4U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_PUE_SHIFT (2U) /*! PUE - Pull Up/Down or Keeper Selection Field * 0b0..Keeper Selected * 0b1..Pull Up/Down Selected */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_PUE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_PUE_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_PUS_MASK (0x30U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_PUS_SHIFT (4U) /*! PUS - Pull Up/Down Resistance Select Field * 0b00..100 kOhm Pull Down * 0b01..47 Kohm Pull Up * 0b10..100 kOhm Pull Up * 0b11..22 kOhm Pull Up */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_PUS_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_PUS_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DSE_MASK (0x1C0U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DSE_SHIFT (6U) /*! DSE - Output Drive Strength Select Field * 0b000..Driver Disabled * 0b001..240 Ohm * 0b010..240/2=120 Ohm * 0b011..240/3=80 Ohm * 0b100..240/4=60 Ohm * 0b101..240/5=48 Ohm * 0b110..240/6=40 Ohm * 0b111..240/7=34 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DSE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DSE_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_HYS_MASK (0x200U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_HYS_SHIFT (9U) /*! HYS - Input Hysteresis Field * 0b0..CMOS input * 0b1..Schmitt trigger input */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_HYS_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_HYS_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DCYCLE_TRIM_MASK (0x3000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DCYCLE_TRIM_SHIFT (12U) /*! DCYCLE_TRIM - Duty Cycle Control Field * 0b00..no duty cycle change * 0b01..duty cycle increased ~3.7% * 0b10..duty cycle decreased ~3.7% * 0b11..no duty cycle change */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DCYCLE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DCYCLE_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DCYCLE_TRIM_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DDR_TRIM_MASK (0xC000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DDR_TRIM_SHIFT (14U) /*! DDR_TRIM - Output Driver Delay Trim Field * 0b00..0pS * 0b01..50pS * 0b10..100pS * 0b11..150pS */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DDR_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DDR_TRIM_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DDR_TRIM_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DDR_SELECT_MASK (0x60000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DDR_SELECT_SHIFT (17U) /*! DDR_SELECT - DDR Select Field * 0b00..DDR3 mode * 0b01..reserved * 0b10..LPDDR2/LPDDR3 modes * 0b11..DDR_SELECT_3_HSIC_USB mode */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DDR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DDR_SELECT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DDR_SELECT_MASK) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DDR_ODT_MASK (0x380000U) #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DDR_ODT_SHIFT (19U) /*! DDR_ODT - On Die Termination Select Field * 0b000..No Termination * 0b001..120 Ohm * 0b010..60 Ohm * 0b011..40 Ohm * 0b100..30 Ohm * 0b101..24 Ohm * 0b110..20 Ohm * 0b111..17 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DDR_ODT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DDR_ODT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_PAD_HSIC_STROBE_DDR_ODT_MASK) /*! @} */ /*! @name SW_PAD_CTL_GRP_PUE - SW_PAD_CTL_GRP_PUE SW GRP Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_PUE_PUE_MASK (0x4U) #define IOMUXC1_DDR_SW_PAD_CTL_GRP_PUE_PUE_SHIFT (2U) /*! PUE - Pull Up/Down or Keeper Selection Field * 0b0..Keeper Selected * 0b1..Pull Up/Down Selected */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_PUE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_GRP_PUE_PUE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_GRP_PUE_PUE_MASK) /*! @} */ /*! @name SW_PAD_CTL_GRP_PUE_DAT - SW_PAD_CTL_GRP_PUE_DAT SW GRP Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_PUE_DAT_PUE_MASK (0x4U) #define IOMUXC1_DDR_SW_PAD_CTL_GRP_PUE_DAT_PUE_SHIFT (2U) /*! PUE - Pull Up/Down or Keeper Selection Field * 0b0..Keeper Selected * 0b1..Pull Up/Down Selected */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_PUE_DAT_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_GRP_PUE_DAT_PUE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_GRP_PUE_DAT_PUE_MASK) /*! @} */ /*! @name SW_PAD_CTL_GRP_PKE - SW_PAD_CTL_GRP_PKE SW GRP Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_PKE_PKE_MASK (0x8U) #define IOMUXC1_DDR_SW_PAD_CTL_GRP_PKE_PKE_SHIFT (3U) /*! PKE - Pull Up/Pull Down/Keeper Enable Field * 0b0..Pull Up/Down and Keeper Disabled * 0b1..Pull Up/Down or Keeper Enabled */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_PKE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_GRP_PKE_PKE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_GRP_PKE_PKE_MASK) /*! @} */ /*! @name SW_PAD_CTL_GRP_PKE_DAT - SW_PAD_CTL_GRP_PKE_DAT SW GRP Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_PKE_DAT_PKE_MASK (0x8U) #define IOMUXC1_DDR_SW_PAD_CTL_GRP_PKE_DAT_PKE_SHIFT (3U) /*! PKE - Pull Up/Pull Down/Keeper Enable Field * 0b0..Pull Up/Down and Keeper Disabled * 0b1..Pull Up/Down or Keeper Enabled */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_PKE_DAT_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_GRP_PKE_DAT_PKE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_GRP_PKE_DAT_PKE_MASK) /*! @} */ /*! @name SW_PAD_CTL_GRP_PUS - SW_PAD_CTL_GRP_PUS SW GRP Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_PUS_PUS_MASK (0x30U) #define IOMUXC1_DDR_SW_PAD_CTL_GRP_PUS_PUS_SHIFT (4U) /*! PUS - Pull Up/Down Resistance Select Field * 0b00..100 kOhm Pull Down * 0b01..47 Kohm Pull Up * 0b10..100 kOhm Pull Up * 0b11..22 kOhm Pull Up */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_PUS_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_GRP_PUS_PUS_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_GRP_PUS_PUS_MASK) /*! @} */ /*! @name SW_PAD_CTL_GRP_DS_ADDR - SW_PAD_CTL_GRP_DS_ADDR SW GRP Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_ADDR_DSE_MASK (0x1C0U) #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_ADDR_DSE_SHIFT (6U) /*! DSE - Output Drive Strength Select Field * 0b000..Driver Disabled * 0b001..240 Ohm * 0b010..240/2=120 Ohm * 0b011..240/3=80 Ohm * 0b100..240/4=60 Ohm * 0b101..240/5=48 Ohm * 0b110..240/6=40 Ohm * 0b111..240/7=34 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_ADDR_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_ADDR_DSE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_ADDR_DSE_MASK) /*! @} */ /*! @name SW_PAD_CTL_GRP_DS_CTRL - SW_PAD_CTL_GRP_DS_CTRL SW GRP Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_CTRL_DSE_MASK (0x1C0U) #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_CTRL_DSE_SHIFT (6U) /*! DSE - Output Drive Strength Select Field * 0b000..Driver Disabled * 0b001..240 Ohm * 0b010..240/2=120 Ohm * 0b011..240/3=80 Ohm * 0b100..240/4=60 Ohm * 0b101..240/5=48 Ohm * 0b110..240/6=40 Ohm * 0b111..240/7=34 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_CTRL_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_CTRL_DSE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_CTRL_DSE_MASK) /*! @} */ /*! @name SW_PAD_CTL_GRP_DS_DAT0 - SW_PAD_CTL_GRP_DS_DAT0 SW GRP Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT0_DSE_MASK (0x1C0U) #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT0_DSE_SHIFT (6U) /*! DSE - Output Drive Strength Select Field * 0b000..Driver Disabled * 0b001..240 Ohm * 0b010..240/2=120 Ohm * 0b011..240/3=80 Ohm * 0b100..240/4=60 Ohm * 0b101..240/5=48 Ohm * 0b110..240/6=40 Ohm * 0b111..240/7=34 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT0_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT0_DSE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT0_DSE_MASK) /*! @} */ /*! @name SW_PAD_CTL_GRP_DS_DAT1 - SW_PAD_CTL_GRP_DS_DAT1 SW GRP Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT1_DSE_MASK (0x1C0U) #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT1_DSE_SHIFT (6U) /*! DSE - Output Drive Strength Select Field * 0b000..Driver Disabled * 0b001..240 Ohm * 0b010..240/2=120 Ohm * 0b011..240/3=80 Ohm * 0b100..240/4=60 Ohm * 0b101..240/5=48 Ohm * 0b110..240/6=40 Ohm * 0b111..240/7=34 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT1_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT1_DSE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT1_DSE_MASK) /*! @} */ /*! @name SW_PAD_CTL_GRP_DS_DAT2 - SW_PAD_CTL_GRP_DS_DAT2 SW GRP Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT2_DSE_MASK (0x1C0U) #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT2_DSE_SHIFT (6U) /*! DSE - Output Drive Strength Select Field * 0b000..Driver Disabled * 0b001..240 Ohm * 0b010..240/2=120 Ohm * 0b011..240/3=80 Ohm * 0b100..240/4=60 Ohm * 0b101..240/5=48 Ohm * 0b110..240/6=40 Ohm * 0b111..240/7=34 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT2_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT2_DSE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT2_DSE_MASK) /*! @} */ /*! @name SW_PAD_CTL_GRP_DS_DAT3 - SW_PAD_CTL_GRP_DS_DAT3 SW GRP Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT3_DSE_MASK (0x1C0U) #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT3_DSE_SHIFT (6U) /*! DSE - Output Drive Strength Select Field * 0b000..Driver Disabled * 0b001..240 Ohm * 0b010..240/2=120 Ohm * 0b011..240/3=80 Ohm * 0b100..240/4=60 Ohm * 0b101..240/5=48 Ohm * 0b110..240/6=40 Ohm * 0b111..240/7=34 Ohm */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT3_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT3_DSE_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_GRP_DS_DAT3_DSE_MASK) /*! @} */ /*! @name SW_PAD_CTL_GRP_HYS - SW_PAD_CTL_GRP_HYS SW GRP Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_HYS_HYS_MASK (0x200U) #define IOMUXC1_DDR_SW_PAD_CTL_GRP_HYS_HYS_SHIFT (9U) /*! HYS - Input Hysteresis Field * 0b0..CMOS input * 0b1..Schmitt trigger input */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_HYS_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_GRP_HYS_HYS_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_GRP_HYS_HYS_MASK) /*! @} */ /*! @name SW_PAD_CTL_GRP_INSEL_DAT - SW_PAD_CTL_GRP_INSEL_DAT SW GRP Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_INSEL_DAT_DDR_INPUT_MASK (0x10000U) #define IOMUXC1_DDR_SW_PAD_CTL_GRP_INSEL_DAT_DDR_INPUT_SHIFT (16U) /*! DDR_INPUT - DDR/CMOS Input Select Field * 0b0..CMOS input type * 0b1..Differential input mode */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_INSEL_DAT_DDR_INPUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_GRP_INSEL_DAT_DDR_INPUT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_GRP_INSEL_DAT_DDR_INPUT_MASK) /*! @} */ /*! @name SW_PAD_CTL_GRP_INSEL_DQS - SW_PAD_CTL_GRP_INSEL_DQS SW GRP Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_INSEL_DQS_DDR_INPUT_MASK (0x10000U) #define IOMUXC1_DDR_SW_PAD_CTL_GRP_INSEL_DQS_DDR_INPUT_SHIFT (16U) /*! DDR_INPUT - DDR/CMOS Input Select Field * 0b0..CMOS input type * 0b1..Differential input mode */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_INSEL_DQS_DDR_INPUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_GRP_INSEL_DQS_DDR_INPUT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_GRP_INSEL_DQS_DDR_INPUT_MASK) /*! @} */ /*! @name SW_PAD_CTL_GRP_DDRTYPE - SW_PAD_CTL_GRP_DDRTYPE SW GRP Register */ /*! @{ */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DDRTYPE_DDR_SELECT_MASK (0x60000U) #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DDRTYPE_DDR_SELECT_SHIFT (17U) /*! DDR_SELECT - DDR Select Field * 0b00..DDR3 mode * 0b01..reserved * 0b10..LPDDR2/LPDDR3 modes * 0b11..DDR_SELECT_3_HSIC_USB mode */ #define IOMUXC1_DDR_SW_PAD_CTL_GRP_DDRTYPE_DDR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_DDR_SW_PAD_CTL_GRP_DDRTYPE_DDR_SELECT_SHIFT)) & IOMUXC1_DDR_SW_PAD_CTL_GRP_DDRTYPE_DDR_SELECT_MASK) /*! @} */ /*! * @} */ /* end of group IOMUXC1_DDR_Register_Masks */ /* IOMUXC1_DDR - Peripheral instance base addresses */ /** Peripheral IOMUXC1_DDR base address */ #define IOMUXC1_DDR_BASE (0x40AD0000u) /** Peripheral IOMUXC1_DDR base pointer */ #define IOMUXC1_DDR ((IOMUXC1_DDR_Type *)IOMUXC1_DDR_BASE) /** Array initializer of IOMUXC1_DDR peripheral base addresses */ #define IOMUXC1_DDR_BASE_ADDRS { IOMUXC1_DDR_BASE } /** Array initializer of IOMUXC1_DDR peripheral base pointers */ #define IOMUXC1_DDR_BASE_PTRS { IOMUXC1_DDR } /*! * @} */ /* end of group IOMUXC1_DDR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LCDIF Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer * @{ */ /** LCDIF - Register Layout Typedef */ typedef struct { __IO uint32_t CTRL; /**< LCDIF General Control Register, offset: 0x0 */ __IO uint32_t CTRL_SET; /**< LCDIF General Control Register, offset: 0x4 */ __IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 */ __IO uint32_t CTRL_TOG; /**< LCDIF General Control Register, offset: 0xC */ __IO uint32_t CTRL1; /**< LCDIF General Control1 Register, offset: 0x10 */ __IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x14 */ __IO uint32_t CTRL1_CLR; /**< LCDIF General Control1 Register, offset: 0x18 */ __IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1C */ __IO uint32_t CTRL2; /**< LCDIF General Control2 Register, offset: 0x20 */ __IO uint32_t CTRL2_SET; /**< LCDIF General Control2 Register, offset: 0x24 */ __IO uint32_t CTRL2_CLR; /**< LCDIF General Control2 Register, offset: 0x28 */ __IO uint32_t CTRL2_TOG; /**< LCDIF General Control2 Register, offset: 0x2C */ __IO uint32_t TRANSFER_COUNT; /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ uint8_t RESERVED_0[12]; __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */ uint8_t RESERVED_1[12]; __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */ uint8_t RESERVED_2[28]; __IO uint32_t VDCTRL0; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ __IO uint32_t VDCTRL0_SET; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ __IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ __IO uint32_t VDCTRL0_TOG; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ __IO uint32_t VDCTRL1; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ uint8_t RESERVED_3[12]; __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */ uint8_t RESERVED_4[12]; __IO uint32_t VDCTRL3; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ uint8_t RESERVED_5[12]; __IO uint32_t VDCTRL4; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ uint8_t RESERVED_6[220]; __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */ uint8_t RESERVED_7[12]; __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */ uint8_t RESERVED_8[12]; __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ uint8_t RESERVED_9[92]; __IO uint32_t AS_CTRL; /**< LCDIF AS Buffer Control Register, offset: 0x210 */ uint8_t RESERVED_10[12]; __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x220 */ uint8_t RESERVED_11[12]; __IO uint32_t AS_NEXT_BUF; /**< , offset: 0x230 */ uint8_t RESERVED_12[12]; __IO uint32_t AS_CLRKEYLOW; /**< LCDIF Overlay Color Key Low, offset: 0x240 */ uint8_t RESERVED_13[12]; __IO uint32_t AS_CLRKEYHIGH; /**< LCDIF Overlay Color Key High, offset: 0x250 */ } LCDIF_Type; /* ---------------------------------------------------------------------------- -- LCDIF Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LCDIF_Register_Masks LCDIF Register Masks * @{ */ /*! @name CTRL - LCDIF General Control Register */ /*! @{ */ #define LCDIF_CTRL_RUN_MASK (0x1U) #define LCDIF_CTRL_RUN_SHIFT (0U) #define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) #define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) /*! DATA_FORMAT_24_BIT * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in * each byte do not contain any useful data, and should be dropped. */ #define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) #define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) /*! DATA_FORMAT_18_BIT * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. */ #define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) #define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U) #define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK) #define LCDIF_CTRL_RSRVD0_MASK (0x10U) #define LCDIF_CTRL_RSRVD0_SHIFT (4U) #define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK) #define LCDIF_CTRL_MASTER_MASK (0x20U) #define LCDIF_CTRL_MASTER_SHIFT (5U) #define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK) #define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U) /*! WORD_LENGTH * 0b00..Input data is 16 bits per pixel. * 0b01..Input data is 8 bits wide. * 0b10..Input data is 18 bits per pixel. * 0b11..Input data is 24 bits per pixel. */ #define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK) #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U) /*! LCD_DATABUS_WIDTH * 0b00..16-bit data bus mode. * 0b01..8-bit data bus mode. * 0b10..18-bit data bus mode. * 0b11..24-bit data bus mode. */ #define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK) #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U) /*! CSC_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U) /*! INPUT_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U) #define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK) #define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U) #define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U) #define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK) #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U) #define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U) #define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK) #define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U) /*! DATA_SHIFT_DIR * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. */ #define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK) #define LCDIF_CTRL_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_CLKGATE_SHIFT (30U) #define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK) #define LCDIF_CTRL_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_SFTRST_SHIFT (31U) #define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) /*! @} */ /*! @name CTRL_SET - LCDIF General Control Register */ /*! @{ */ #define LCDIF_CTRL_SET_RUN_MASK (0x1U) #define LCDIF_CTRL_SET_RUN_SHIFT (0U) #define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) /*! DATA_FORMAT_24_BIT * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in * each byte do not contain any useful data, and should be dropped. */ #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) /*! DATA_FORMAT_18_BIT * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. */ #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U) #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK) #define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U) #define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U) #define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK) #define LCDIF_CTRL_SET_MASTER_MASK (0x20U) #define LCDIF_CTRL_SET_MASTER_SHIFT (5U) #define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK) #define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U) /*! WORD_LENGTH * 0b00..Input data is 16 bits per pixel. * 0b01..Input data is 8 bits wide. * 0b10..Input data is 18 bits per pixel. * 0b11..Input data is 24 bits per pixel. */ #define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK) #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U) /*! LCD_DATABUS_WIDTH * 0b00..16-bit data bus mode. * 0b01..8-bit data bus mode. * 0b10..18-bit data bus mode. * 0b11..24-bit data bus mode. */ #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK) #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U) /*! CSC_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U) /*! INPUT_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U) #define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK) #define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U) #define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U) #define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK) #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U) #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U) #define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK) #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U) /*! DATA_SHIFT_DIR * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. */ #define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK) #define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U) #define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK) #define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_SET_SFTRST_SHIFT (31U) #define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) /*! @} */ /*! @name CTRL_CLR - LCDIF General Control Register */ /*! @{ */ #define LCDIF_CTRL_CLR_RUN_MASK (0x1U) #define LCDIF_CTRL_CLR_RUN_SHIFT (0U) #define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) /*! DATA_FORMAT_24_BIT * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in * each byte do not contain any useful data, and should be dropped. */ #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) /*! DATA_FORMAT_18_BIT * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. */ #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U) #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK) #define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U) #define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U) #define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK) #define LCDIF_CTRL_CLR_MASTER_MASK (0x20U) #define LCDIF_CTRL_CLR_MASTER_SHIFT (5U) #define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK) #define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U) /*! WORD_LENGTH * 0b00..Input data is 16 bits per pixel. * 0b01..Input data is 8 bits wide. * 0b10..Input data is 18 bits per pixel. * 0b11..Input data is 24 bits per pixel. */ #define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK) #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U) /*! LCD_DATABUS_WIDTH * 0b00..16-bit data bus mode. * 0b01..8-bit data bus mode. * 0b10..18-bit data bus mode. * 0b11..24-bit data bus mode. */ #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK) #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U) /*! CSC_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U) /*! INPUT_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U) #define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK) #define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U) #define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U) #define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK) #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U) #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U) #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK) #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U) /*! DATA_SHIFT_DIR * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. */ #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK) #define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U) #define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK) #define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) #define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) /*! @} */ /*! @name CTRL_TOG - LCDIF General Control Register */ /*! @{ */ #define LCDIF_CTRL_TOG_RUN_MASK (0x1U) #define LCDIF_CTRL_TOG_RUN_SHIFT (0U) #define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) /*! DATA_FORMAT_24_BIT * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in * each byte do not contain any useful data, and should be dropped. */ #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) /*! DATA_FORMAT_18_BIT * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. */ #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U) #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK) #define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U) #define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U) #define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK) #define LCDIF_CTRL_TOG_MASTER_MASK (0x20U) #define LCDIF_CTRL_TOG_MASTER_SHIFT (5U) #define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK) #define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U) /*! WORD_LENGTH * 0b00..Input data is 16 bits per pixel. * 0b01..Input data is 8 bits wide. * 0b10..Input data is 18 bits per pixel. * 0b11..Input data is 24 bits per pixel. */ #define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK) #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U) /*! LCD_DATABUS_WIDTH * 0b00..16-bit data bus mode. * 0b01..8-bit data bus mode. * 0b10..18-bit data bus mode. * 0b11..24-bit data bus mode. */ #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK) #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U) /*! CSC_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U) /*! INPUT_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U) #define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK) #define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U) #define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U) #define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK) #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U) #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U) #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK) #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U) /*! DATA_SHIFT_DIR * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. */ #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK) #define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U) #define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK) #define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) #define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) /*! @} */ /*! @name CTRL1 - LCDIF General Control1 Register */ /*! @{ */ #define LCDIF_CTRL1_RESET_MASK (0x1U) #define LCDIF_CTRL1_RESET_SHIFT (0U) /*! RESET * 0b0..LCD_RESET output signal is low. * 0b1..LCD_RESET output signal is high. */ #define LCDIF_CTRL1_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RESET_SHIFT)) & LCDIF_CTRL1_RESET_MASK) #define LCDIF_CTRL1_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U) /*! VSYNC_EDGE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U) /*! CUR_FRAME_DONE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK) #define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U) /*! UNDERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK) #define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U) /*! OVERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK) #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U) #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U) #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U) #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U) #define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U) #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U) #define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK) #define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U) #define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U) #define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK) #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK) #define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U) #define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U) #define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK) #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U) #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK) #define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U) /*! BM_ERROR_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK) #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U) #define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK) /*! @} */ /*! @name CTRL1_SET - LCDIF General Control1 Register */ /*! @{ */ #define LCDIF_CTRL1_SET_RESET_MASK (0x1U) #define LCDIF_CTRL1_SET_RESET_SHIFT (0U) /*! RESET * 0b0..LCD_RESET output signal is low. * 0b1..LCD_RESET output signal is high. */ #define LCDIF_CTRL1_SET_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RESET_SHIFT)) & LCDIF_CTRL1_SET_RESET_MASK) #define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U) /*! VSYNC_EDGE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U) /*! CUR_FRAME_DONE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U) /*! UNDERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U) /*! OVERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U) #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U) #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK) #define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U) #define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U) #define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK) #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK) #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U) #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U) #define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK) #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U) #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U) /*! BM_ERROR_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK) /*! @} */ /*! @name CTRL1_CLR - LCDIF General Control1 Register */ /*! @{ */ #define LCDIF_CTRL1_CLR_RESET_MASK (0x1U) #define LCDIF_CTRL1_CLR_RESET_SHIFT (0U) /*! RESET * 0b0..LCD_RESET output signal is low. * 0b1..LCD_RESET output signal is high. */ #define LCDIF_CTRL1_CLR_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RESET_SHIFT)) & LCDIF_CTRL1_CLR_RESET_MASK) #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U) /*! VSYNC_EDGE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U) /*! CUR_FRAME_DONE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U) /*! UNDERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U) /*! OVERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U) #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U) #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK) #define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U) #define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U) #define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK) #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK) #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U) #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U) #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK) #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U) #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U) /*! BM_ERROR_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK) /*! @} */ /*! @name CTRL1_TOG - LCDIF General Control1 Register */ /*! @{ */ #define LCDIF_CTRL1_TOG_RESET_MASK (0x1U) #define LCDIF_CTRL1_TOG_RESET_SHIFT (0U) /*! RESET * 0b0..LCD_RESET output signal is low. * 0b1..LCD_RESET output signal is high. */ #define LCDIF_CTRL1_TOG_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RESET_SHIFT)) & LCDIF_CTRL1_TOG_RESET_MASK) #define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U) /*! VSYNC_EDGE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U) /*! CUR_FRAME_DONE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U) /*! UNDERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U) /*! OVERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U) #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U) #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK) #define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U) #define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U) #define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK) #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK) #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U) #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U) #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK) #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U) #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U) /*! BM_ERROR_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK) /*! @} */ /*! @name CTRL2 - LCDIF General Control2 Register */ /*! @{ */ #define LCDIF_CTRL2_RSRVD0_MASK (0xFFFU) #define LCDIF_CTRL2_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U) /*! EVEN_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) #define LCDIF_CTRL2_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK) #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U) /*! ODD_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) #define LCDIF_CTRL2_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_RSRVD4_SHIFT (19U) #define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK) #define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U) #define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U) #define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK) #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U) /*! OUTSTANDING_REQS * 0b000..REQ_1 * 0b001..REQ_2 * 0b010..REQ_4 * 0b011..REQ_8 * 0b100..REQ_16 */ #define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK) #define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) /*! @} */ /*! @name CTRL2_SET - LCDIF General Control2 Register */ /*! @{ */ #define LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU) #define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U) /*! EVEN_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) #define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK) #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U) /*! ODD_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) #define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U) #define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK) #define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U) #define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U) #define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK) #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U) /*! OUTSTANDING_REQS * 0b000..REQ_1 * 0b001..REQ_2 * 0b010..REQ_4 * 0b011..REQ_8 * 0b100..REQ_16 */ #define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) #define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) /*! @} */ /*! @name CTRL2_CLR - LCDIF General Control2 Register */ /*! @{ */ #define LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU) #define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U) /*! EVEN_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) #define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK) #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U) /*! ODD_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) #define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U) #define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK) #define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U) #define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U) #define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK) #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U) /*! OUTSTANDING_REQS * 0b000..REQ_1 * 0b001..REQ_2 * 0b010..REQ_4 * 0b011..REQ_8 * 0b100..REQ_16 */ #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) #define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) /*! @} */ /*! @name CTRL2_TOG - LCDIF General Control2 Register */ /*! @{ */ #define LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU) #define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U) /*! EVEN_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) #define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK) #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U) /*! ODD_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) #define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U) #define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK) #define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U) #define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U) #define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK) #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U) /*! OUTSTANDING_REQS * 0b000..REQ_1 * 0b001..REQ_2 * 0b010..REQ_4 * 0b011..REQ_8 * 0b100..REQ_16 */ #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) /*! @} */ /*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */ /*! @{ */ #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU) #define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) #define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U) #define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) #define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) /*! @} */ /*! @name CUR_BUF - LCD Interface Current Buffer Address Register */ /*! @{ */ #define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_CUR_BUF_ADDR_SHIFT (0U) #define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) /*! @} */ /*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */ /*! @{ */ #define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_NEXT_BUF_ADDR_SHIFT (0U) #define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) /*! @} */ /*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ /*! @{ */ #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) #define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U) #define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U) #define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK) #define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U) #define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U) #define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK) #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U) #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U) #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK) #define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U) #define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U) #define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK) #define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U) #define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U) #define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK) #define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U) #define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U) #define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK) #define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U) #define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U) #define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK) #define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U) #define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U) #define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK) #define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U) #define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U) #define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK) #define LCDIF_VDCTRL0_VSYNC_OEB_MASK (0x20000000U) #define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT (29U) /*! VSYNC_OEB * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. */ #define LCDIF_VDCTRL0_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK) #define LCDIF_VDCTRL0_RSRVD2_MASK (0xC0000000U) #define LCDIF_VDCTRL0_RSRVD2_SHIFT (30U) #define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) /*! @} */ /*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ /*! @{ */ #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U) #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U) #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK) #define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U) #define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U) #define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK) #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U) #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U) #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK) #define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U) #define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U) #define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK) #define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U) #define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U) #define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK) #define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U) #define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U) #define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK) #define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U) #define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U) #define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK) #define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U) #define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U) #define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK) #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U) #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U) #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK) #define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK (0x20000000U) #define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT (29U) /*! VSYNC_OEB * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. */ #define LCDIF_VDCTRL0_SET_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK) #define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xC0000000U) #define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (30U) #define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) /*! @} */ /*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ /*! @{ */ #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U) #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U) #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK) #define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U) #define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U) #define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK) #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U) #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U) #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK) #define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U) #define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U) #define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK) #define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U) #define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U) #define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK) #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U) #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U) #define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK) #define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U) #define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U) #define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK) #define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U) #define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U) #define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK) #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U) #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U) #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK) #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK (0x20000000U) #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT (29U) /*! VSYNC_OEB * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. */ #define LCDIF_VDCTRL0_CLR_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK) #define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xC0000000U) #define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (30U) #define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) /*! @} */ /*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ /*! @{ */ #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U) #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U) #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK) #define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U) #define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U) #define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK) #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U) #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U) #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK) #define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U) #define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U) #define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK) #define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U) #define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U) #define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK) #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U) #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U) #define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK) #define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U) #define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U) #define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK) #define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U) #define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U) #define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK) #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U) #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U) #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK) #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK (0x20000000U) #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT (29U) /*! VSYNC_OEB * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. */ #define LCDIF_VDCTRL0_TOG_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK) #define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xC0000000U) #define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (30U) #define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) /*! @} */ /*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */ /*! @{ */ #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU) #define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) #define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) /*! @} */ /*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */ /*! @{ */ #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU) #define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) #define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) /*! @} */ /*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */ /*! @{ */ #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU) #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U) #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U) #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) #define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U) #define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U) #define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK) #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U) #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U) #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK) #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) #define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) #define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) /*! @} */ /*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */ /*! @{ */ #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU) #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U) #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U) #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK) #define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U) #define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U) #define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK) #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U) #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) /*! @} */ /*! @name BM_ERROR_STAT - Bus Master Error Status Register */ /*! @{ */ #define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) #define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) /*! @} */ /*! @name CRC_STAT - CRC Status Register */ /*! @{ */ #define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU) #define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) #define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) /*! @} */ /*! @name STAT - LCD Interface Status Register */ /*! @{ */ #define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU) #define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) #define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) #define LCDIF_STAT_RSRVD0_MASK (0x1FFFE00U) #define LCDIF_STAT_RSRVD0_SHIFT (9U) #define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK) #define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U) #define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U) #define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK) #define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U) #define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U) #define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK) #define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U) #define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U) #define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK) #define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U) #define LCDIF_STAT_LFIFO_FULL_SHIFT (29U) #define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK) #define LCDIF_STAT_PRESENT_MASK (0x80000000U) #define LCDIF_STAT_PRESENT_SHIFT (31U) #define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) /*! @} */ /*! @name AS_CTRL - LCDIF AS Buffer Control Register */ /*! @{ */ #define LCDIF_AS_CTRL_AS_ENABLE_MASK (0x1U) #define LCDIF_AS_CTRL_AS_ENABLE_SHIFT (0U) #define LCDIF_AS_CTRL_AS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_AS_ENABLE_SHIFT)) & LCDIF_AS_CTRL_AS_ENABLE_MASK) #define LCDIF_AS_CTRL_ALPHA_CTRL_MASK (0x6U) #define LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT (1U) #define LCDIF_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT)) & LCDIF_AS_CTRL_ALPHA_CTRL_MASK) #define LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) #define LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) #define LCDIF_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK) #define LCDIF_AS_CTRL_FORMAT_MASK (0xF0U) #define LCDIF_AS_CTRL_FORMAT_SHIFT (4U) #define LCDIF_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_FORMAT_SHIFT)) & LCDIF_AS_CTRL_FORMAT_MASK) #define LCDIF_AS_CTRL_ALPHA_MASK (0xFF00U) #define LCDIF_AS_CTRL_ALPHA_SHIFT (8U) #define LCDIF_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_SHIFT)) & LCDIF_AS_CTRL_ALPHA_MASK) #define LCDIF_AS_CTRL_ROP_MASK (0xF0000U) #define LCDIF_AS_CTRL_ROP_SHIFT (16U) #define LCDIF_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ROP_SHIFT)) & LCDIF_AS_CTRL_ROP_MASK) #define LCDIF_AS_CTRL_ALPHA_INVERT_MASK (0x100000U) #define LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT (20U) #define LCDIF_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT)) & LCDIF_AS_CTRL_ALPHA_INVERT_MASK) #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK (0x600000U) #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT (21U) #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_AS_CTRL_PS_DISABLE_MASK (0x800000U) #define LCDIF_AS_CTRL_PS_DISABLE_SHIFT (23U) #define LCDIF_AS_CTRL_PS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_PS_DISABLE_SHIFT)) & LCDIF_AS_CTRL_PS_DISABLE_MASK) #define LCDIF_AS_CTRL_RVDS1_MASK (0xFF000000U) #define LCDIF_AS_CTRL_RVDS1_SHIFT (24U) #define LCDIF_AS_CTRL_RVDS1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_RVDS1_SHIFT)) & LCDIF_AS_CTRL_RVDS1_MASK) /*! @} */ /*! @name AS_BUF - Alpha Surface Buffer Pointer */ /*! @{ */ #define LCDIF_AS_BUF_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_AS_BUF_ADDR_SHIFT (0U) #define LCDIF_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_BUF_ADDR_SHIFT)) & LCDIF_AS_BUF_ADDR_MASK) /*! @} */ /*! @name AS_NEXT_BUF - */ /*! @{ */ #define LCDIF_AS_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_AS_NEXT_BUF_ADDR_SHIFT (0U) #define LCDIF_AS_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_NEXT_BUF_ADDR_SHIFT)) & LCDIF_AS_NEXT_BUF_ADDR_MASK) /*! @} */ /*! @name AS_CLRKEYLOW - LCDIF Overlay Color Key Low */ /*! @{ */ #define LCDIF_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) #define LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT (0U) #define LCDIF_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYLOW_PIXEL_MASK) #define LCDIF_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) #define LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT (24U) #define LCDIF_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYLOW_RSVD1_MASK) /*! @} */ /*! @name AS_CLRKEYHIGH - LCDIF Overlay Color Key High */ /*! @{ */ #define LCDIF_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) #define LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT (0U) #define LCDIF_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYHIGH_PIXEL_MASK) #define LCDIF_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) #define LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT (24U) #define LCDIF_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYHIGH_RSVD1_MASK) /*! @} */ /*! * @} */ /* end of group LCDIF_Register_Masks */ /* LCDIF - Peripheral instance base addresses */ /** Peripheral LCDIF0 base address */ #define LCDIF0_BASE (0x40AA0000u) /** Peripheral LCDIF0 base pointer */ #define LCDIF0 ((LCDIF_Type *)LCDIF0_BASE) /** Array initializer of LCDIF peripheral base addresses */ #define LCDIF_BASE_ADDRS { LCDIF0_BASE } /** Array initializer of LCDIF peripheral base pointers */ #define LCDIF_BASE_PTRS { LCDIF0 } /*! * @} */ /* end of group LCDIF_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LLWU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer * @{ */ /** LLWU - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __IO uint32_t PE1; /**< Pin Enable 1 register, offset: 0x8 */ __I uint32_t PE2; /**< Pin Enable 2 register, offset: 0xC */ uint8_t RESERVED_0[8]; __IO uint32_t ME; /**< Module Interrupt Enable register, offset: 0x18 */ __I uint32_t DE; /**< Module DMA/Trigger Enable register, offset: 0x1C */ __IO uint32_t PF; /**< Pin Flag register, offset: 0x20 */ uint8_t RESERVED_1[4]; __I uint32_t MF; /**< Module Interrupt Flag register, offset: 0x28 */ uint8_t RESERVED_2[4]; __IO uint32_t FILT; /**< Pin Filter register, offset: 0x30 */ } LLWU_Type; /* ---------------------------------------------------------------------------- -- LLWU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LLWU_Register_Masks LLWU Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define LLWU_VERID_FEATURE_MASK (0xFFFFU) #define LLWU_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Standard features implemented */ #define LLWU_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_FEATURE_SHIFT)) & LLWU_VERID_FEATURE_MASK) #define LLWU_VERID_MINOR_MASK (0xFF0000U) #define LLWU_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LLWU_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_MINOR_SHIFT)) & LLWU_VERID_MINOR_MASK) #define LLWU_VERID_MAJOR_MASK (0xFF000000U) #define LLWU_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LLWU_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_MAJOR_SHIFT)) & LLWU_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define LLWU_PARAM_FILTERS_MASK (0xFFU) #define LLWU_PARAM_FILTERS_SHIFT (0U) /*! FILTERS - Filter Number */ #define LLWU_PARAM_FILTERS(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_FILTERS_SHIFT)) & LLWU_PARAM_FILTERS_MASK) #define LLWU_PARAM_DMAS_MASK (0xFF00U) #define LLWU_PARAM_DMAS_SHIFT (8U) /*! DMAS - DMA Number */ #define LLWU_PARAM_DMAS(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_DMAS_SHIFT)) & LLWU_PARAM_DMAS_MASK) #define LLWU_PARAM_MODULES_MASK (0xFF0000U) #define LLWU_PARAM_MODULES_SHIFT (16U) /*! MODULES - Module Number */ #define LLWU_PARAM_MODULES(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_MODULES_SHIFT)) & LLWU_PARAM_MODULES_MASK) #define LLWU_PARAM_PINS_MASK (0xFF000000U) #define LLWU_PARAM_PINS_SHIFT (24U) /*! PINS - Pin Number */ #define LLWU_PARAM_PINS(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_PINS_SHIFT)) & LLWU_PARAM_PINS_MASK) /*! @} */ /*! @name PE1 - Pin Enable 1 register */ /*! @{ */ #define LLWU_PE1_WUPE0_MASK (0x3U) #define LLWU_PE1_WUPE0_SHIFT (0U) /*! WUPE0 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE1_WUPE0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) #define LLWU_PE1_WUPE1_MASK (0xCU) #define LLWU_PE1_WUPE1_SHIFT (2U) /*! WUPE1 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE1_WUPE1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) #define LLWU_PE1_WUPE2_MASK (0x30U) #define LLWU_PE1_WUPE2_SHIFT (4U) /*! WUPE2 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE1_WUPE2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) #define LLWU_PE1_WUPE3_MASK (0xC0U) #define LLWU_PE1_WUPE3_SHIFT (6U) /*! WUPE3 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE1_WUPE3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) #define LLWU_PE1_WUPE4_MASK (0x300U) #define LLWU_PE1_WUPE4_SHIFT (8U) /*! WUPE4 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE1_WUPE4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE4_SHIFT)) & LLWU_PE1_WUPE4_MASK) #define LLWU_PE1_WUPE5_MASK (0xC00U) #define LLWU_PE1_WUPE5_SHIFT (10U) /*! WUPE5 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE1_WUPE5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE5_SHIFT)) & LLWU_PE1_WUPE5_MASK) #define LLWU_PE1_WUPE6_MASK (0x3000U) #define LLWU_PE1_WUPE6_SHIFT (12U) /*! WUPE6 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE1_WUPE6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE6_SHIFT)) & LLWU_PE1_WUPE6_MASK) #define LLWU_PE1_WUPE7_MASK (0xC000U) #define LLWU_PE1_WUPE7_SHIFT (14U) /*! WUPE7 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE1_WUPE7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE7_SHIFT)) & LLWU_PE1_WUPE7_MASK) #define LLWU_PE1_WUPE8_MASK (0x30000U) #define LLWU_PE1_WUPE8_SHIFT (16U) /*! WUPE8 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE1_WUPE8(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE8_SHIFT)) & LLWU_PE1_WUPE8_MASK) #define LLWU_PE1_WUPE9_MASK (0xC0000U) #define LLWU_PE1_WUPE9_SHIFT (18U) /*! WUPE9 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE1_WUPE9(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE9_SHIFT)) & LLWU_PE1_WUPE9_MASK) #define LLWU_PE1_WUPE10_MASK (0x300000U) #define LLWU_PE1_WUPE10_SHIFT (20U) /*! WUPE10 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE1_WUPE10(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE10_SHIFT)) & LLWU_PE1_WUPE10_MASK) #define LLWU_PE1_WUPE11_MASK (0xC00000U) #define LLWU_PE1_WUPE11_SHIFT (22U) /*! WUPE11 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE1_WUPE11(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE11_SHIFT)) & LLWU_PE1_WUPE11_MASK) #define LLWU_PE1_WUPE12_MASK (0x3000000U) #define LLWU_PE1_WUPE12_SHIFT (24U) /*! WUPE12 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE1_WUPE12(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE12_SHIFT)) & LLWU_PE1_WUPE12_MASK) #define LLWU_PE1_WUPE13_MASK (0xC000000U) #define LLWU_PE1_WUPE13_SHIFT (26U) /*! WUPE13 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE1_WUPE13(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE13_SHIFT)) & LLWU_PE1_WUPE13_MASK) #define LLWU_PE1_WUPE14_MASK (0x30000000U) #define LLWU_PE1_WUPE14_SHIFT (28U) /*! WUPE14 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE1_WUPE14(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE14_SHIFT)) & LLWU_PE1_WUPE14_MASK) #define LLWU_PE1_WUPE15_MASK (0xC0000000U) #define LLWU_PE1_WUPE15_SHIFT (30U) /*! WUPE15 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE1_WUPE15(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE15_SHIFT)) & LLWU_PE1_WUPE15_MASK) /*! @} */ /*! @name PE2 - Pin Enable 2 register */ /*! @{ */ #define LLWU_PE2_Reserved16_MASK (0x3U) #define LLWU_PE2_Reserved16_SHIFT (0U) /*! Reserved16 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE2_Reserved16(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved16_SHIFT)) & LLWU_PE2_Reserved16_MASK) #define LLWU_PE2_Reserved17_MASK (0xCU) #define LLWU_PE2_Reserved17_SHIFT (2U) /*! Reserved17 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE2_Reserved17(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved17_SHIFT)) & LLWU_PE2_Reserved17_MASK) #define LLWU_PE2_Reserved18_MASK (0x30U) #define LLWU_PE2_Reserved18_SHIFT (4U) /*! Reserved18 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE2_Reserved18(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved18_SHIFT)) & LLWU_PE2_Reserved18_MASK) #define LLWU_PE2_Reserved19_MASK (0xC0U) #define LLWU_PE2_Reserved19_SHIFT (6U) /*! Reserved19 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE2_Reserved19(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved19_SHIFT)) & LLWU_PE2_Reserved19_MASK) #define LLWU_PE2_Reserved20_MASK (0x300U) #define LLWU_PE2_Reserved20_SHIFT (8U) /*! Reserved20 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE2_Reserved20(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved20_SHIFT)) & LLWU_PE2_Reserved20_MASK) #define LLWU_PE2_Reserved21_MASK (0xC00U) #define LLWU_PE2_Reserved21_SHIFT (10U) /*! Reserved21 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE2_Reserved21(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved21_SHIFT)) & LLWU_PE2_Reserved21_MASK) #define LLWU_PE2_Reserved22_MASK (0x3000U) #define LLWU_PE2_Reserved22_SHIFT (12U) /*! Reserved22 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE2_Reserved22(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved22_SHIFT)) & LLWU_PE2_Reserved22_MASK) #define LLWU_PE2_Reserved23_MASK (0xC000U) #define LLWU_PE2_Reserved23_SHIFT (14U) /*! Reserved23 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE2_Reserved23(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved23_SHIFT)) & LLWU_PE2_Reserved23_MASK) #define LLWU_PE2_Reserved24_MASK (0x30000U) #define LLWU_PE2_Reserved24_SHIFT (16U) /*! Reserved24 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE2_Reserved24(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved24_SHIFT)) & LLWU_PE2_Reserved24_MASK) #define LLWU_PE2_Reserved25_MASK (0xC0000U) #define LLWU_PE2_Reserved25_SHIFT (18U) /*! Reserved25 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE2_Reserved25(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved25_SHIFT)) & LLWU_PE2_Reserved25_MASK) #define LLWU_PE2_Reserved26_MASK (0x300000U) #define LLWU_PE2_Reserved26_SHIFT (20U) /*! Reserved26 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE2_Reserved26(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved26_SHIFT)) & LLWU_PE2_Reserved26_MASK) #define LLWU_PE2_Reserved27_MASK (0xC00000U) #define LLWU_PE2_Reserved27_SHIFT (22U) /*! Reserved27 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE2_Reserved27(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved27_SHIFT)) & LLWU_PE2_Reserved27_MASK) #define LLWU_PE2_Reserved28_MASK (0x3000000U) #define LLWU_PE2_Reserved28_SHIFT (24U) /*! Reserved28 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE2_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved28_SHIFT)) & LLWU_PE2_Reserved28_MASK) #define LLWU_PE2_Reserved29_MASK (0xC000000U) #define LLWU_PE2_Reserved29_SHIFT (26U) /*! Reserved29 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE2_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved29_SHIFT)) & LLWU_PE2_Reserved29_MASK) #define LLWU_PE2_Reserved30_MASK (0x30000000U) #define LLWU_PE2_Reserved30_SHIFT (28U) /*! Reserved30 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE2_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved30_SHIFT)) & LLWU_PE2_Reserved30_MASK) #define LLWU_PE2_Reserved31_MASK (0xC0000000U) #define LLWU_PE2_Reserved31_SHIFT (30U) /*! Reserved31 - Wakeup pin enable for LLWU_Pn * 0b00..External input pin disabled as wakeup input * 0b01..External input pin enabled with rising edge detection * 0b10..External input pin enabled with falling edge detection * 0b11..External input pin enabled with any change detection */ #define LLWU_PE2_Reserved31(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved31_SHIFT)) & LLWU_PE2_Reserved31_MASK) /*! @} */ /*! @name ME - Module Interrupt Enable register */ /*! @{ */ #define LLWU_ME_WUME0_MASK (0x1U) #define LLWU_ME_WUME0_SHIFT (0U) /*! WUME0 - Wakeup module enable for module n * 0b0..Internal module flag not used as wakeup source * 0b1..Internal module flag used as wakeup source */ #define LLWU_ME_WUME0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) #define LLWU_ME_WUME1_MASK (0x2U) #define LLWU_ME_WUME1_SHIFT (1U) /*! WUME1 - Wakeup module enable for module n * 0b0..Internal module flag not used as wakeup source * 0b1..Internal module flag used as wakeup source */ #define LLWU_ME_WUME1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) #define LLWU_ME_WUME2_MASK (0x4U) #define LLWU_ME_WUME2_SHIFT (2U) /*! WUME2 - Wakeup module enable for module n * 0b0..Internal module flag not used as wakeup source * 0b1..Internal module flag used as wakeup source */ #define LLWU_ME_WUME2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) #define LLWU_ME_WUME3_MASK (0x8U) #define LLWU_ME_WUME3_SHIFT (3U) /*! WUME3 - Wakeup module enable for module n * 0b0..Internal module flag not used as wakeup source * 0b1..Internal module flag used as wakeup source */ #define LLWU_ME_WUME3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) #define LLWU_ME_WUME4_MASK (0x10U) #define LLWU_ME_WUME4_SHIFT (4U) /*! WUME4 - Wakeup module enable for module n * 0b0..Internal module flag not used as wakeup source * 0b1..Internal module flag used as wakeup source */ #define LLWU_ME_WUME4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK) #define LLWU_ME_Reserved5_MASK (0x20U) #define LLWU_ME_Reserved5_SHIFT (5U) /*! Reserved5 - Wakeup module enable for module n * 0b0..Internal module flag not used as wakeup source * 0b1..Internal module flag used as wakeup source */ #define LLWU_ME_Reserved5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_Reserved5_SHIFT)) & LLWU_ME_Reserved5_MASK) #define LLWU_ME_WUME6_MASK (0x40U) #define LLWU_ME_WUME6_SHIFT (6U) /*! WUME6 - Wakeup module enable for module n * 0b0..Internal module flag not used as wakeup source * 0b1..Internal module flag used as wakeup source */ #define LLWU_ME_WUME6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) #define LLWU_ME_Reserved7_MASK (0x80U) #define LLWU_ME_Reserved7_SHIFT (7U) /*! Reserved7 - Wakeup module enable for module n * 0b0..Internal module flag not used as wakeup source * 0b1..Internal module flag used as wakeup source */ #define LLWU_ME_Reserved7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_Reserved7_SHIFT)) & LLWU_ME_Reserved7_MASK) /*! @} */ /*! @name DE - Module DMA/Trigger Enable register */ /*! @{ */ #define LLWU_DE_Reserved0_MASK (0x1U) #define LLWU_DE_Reserved0_SHIFT (0U) /*! Reserved0 - DMA/Trigger wakeup enable for module n * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source * 0b1..Internal module request enabled as a DMA/Trigger wakeup source */ #define LLWU_DE_Reserved0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_Reserved0_SHIFT)) & LLWU_DE_Reserved0_MASK) #define LLWU_DE_Reserved1_MASK (0x2U) #define LLWU_DE_Reserved1_SHIFT (1U) /*! Reserved1 - DMA/Trigger wakeup enable for module n * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source * 0b1..Internal module request enabled as a DMA/Trigger wakeup source */ #define LLWU_DE_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_Reserved1_SHIFT)) & LLWU_DE_Reserved1_MASK) #define LLWU_DE_Reserved2_MASK (0x4U) #define LLWU_DE_Reserved2_SHIFT (2U) /*! Reserved2 - DMA/Trigger wakeup enable for module n * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source * 0b1..Internal module request enabled as a DMA/Trigger wakeup source */ #define LLWU_DE_Reserved2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_Reserved2_SHIFT)) & LLWU_DE_Reserved2_MASK) #define LLWU_DE_Reserved3_MASK (0x8U) #define LLWU_DE_Reserved3_SHIFT (3U) /*! Reserved3 - DMA/Trigger wakeup enable for module n * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source * 0b1..Internal module request enabled as a DMA/Trigger wakeup source */ #define LLWU_DE_Reserved3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_Reserved3_SHIFT)) & LLWU_DE_Reserved3_MASK) #define LLWU_DE_Reserved4_MASK (0x10U) #define LLWU_DE_Reserved4_SHIFT (4U) /*! Reserved4 - DMA/Trigger wakeup enable for module n * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source * 0b1..Internal module request enabled as a DMA/Trigger wakeup source */ #define LLWU_DE_Reserved4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_Reserved4_SHIFT)) & LLWU_DE_Reserved4_MASK) #define LLWU_DE_Reserved5_MASK (0x20U) #define LLWU_DE_Reserved5_SHIFT (5U) /*! Reserved5 - DMA/Trigger wakeup enable for module n * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source * 0b1..Internal module request enabled as a DMA/Trigger wakeup source */ #define LLWU_DE_Reserved5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_Reserved5_SHIFT)) & LLWU_DE_Reserved5_MASK) #define LLWU_DE_Reserved6_MASK (0x40U) #define LLWU_DE_Reserved6_SHIFT (6U) /*! Reserved6 - DMA/Trigger wakeup enable for module n * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source * 0b1..Internal module request enabled as a DMA/Trigger wakeup source */ #define LLWU_DE_Reserved6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_Reserved6_SHIFT)) & LLWU_DE_Reserved6_MASK) #define LLWU_DE_Reserved7_MASK (0x80U) #define LLWU_DE_Reserved7_SHIFT (7U) /*! Reserved7 - DMA/Trigger wakeup enable for module n * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source * 0b1..Internal module request enabled as a DMA/Trigger wakeup source */ #define LLWU_DE_Reserved7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_Reserved7_SHIFT)) & LLWU_DE_Reserved7_MASK) /*! @} */ /*! @name PF - Pin Flag register */ /*! @{ */ #define LLWU_PF_WUF0_MASK (0x1U) #define LLWU_PF_WUF0_SHIFT (0U) /*! WUF0 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_WUF0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF0_SHIFT)) & LLWU_PF_WUF0_MASK) #define LLWU_PF_WUF1_MASK (0x2U) #define LLWU_PF_WUF1_SHIFT (1U) /*! WUF1 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_WUF1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF1_SHIFT)) & LLWU_PF_WUF1_MASK) #define LLWU_PF_WUF2_MASK (0x4U) #define LLWU_PF_WUF2_SHIFT (2U) /*! WUF2 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_WUF2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF2_SHIFT)) & LLWU_PF_WUF2_MASK) #define LLWU_PF_WUF3_MASK (0x8U) #define LLWU_PF_WUF3_SHIFT (3U) /*! WUF3 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_WUF3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF3_SHIFT)) & LLWU_PF_WUF3_MASK) #define LLWU_PF_WUF4_MASK (0x10U) #define LLWU_PF_WUF4_SHIFT (4U) /*! WUF4 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_WUF4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF4_SHIFT)) & LLWU_PF_WUF4_MASK) #define LLWU_PF_WUF5_MASK (0x20U) #define LLWU_PF_WUF5_SHIFT (5U) /*! WUF5 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_WUF5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF5_SHIFT)) & LLWU_PF_WUF5_MASK) #define LLWU_PF_WUF6_MASK (0x40U) #define LLWU_PF_WUF6_SHIFT (6U) /*! WUF6 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_WUF6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF6_SHIFT)) & LLWU_PF_WUF6_MASK) #define LLWU_PF_WUF7_MASK (0x80U) #define LLWU_PF_WUF7_SHIFT (7U) /*! WUF7 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_WUF7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF7_SHIFT)) & LLWU_PF_WUF7_MASK) #define LLWU_PF_WUF8_MASK (0x100U) #define LLWU_PF_WUF8_SHIFT (8U) /*! WUF8 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_WUF8(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF8_SHIFT)) & LLWU_PF_WUF8_MASK) #define LLWU_PF_WUF9_MASK (0x200U) #define LLWU_PF_WUF9_SHIFT (9U) /*! WUF9 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_WUF9(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF9_SHIFT)) & LLWU_PF_WUF9_MASK) #define LLWU_PF_WUF10_MASK (0x400U) #define LLWU_PF_WUF10_SHIFT (10U) /*! WUF10 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_WUF10(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF10_SHIFT)) & LLWU_PF_WUF10_MASK) #define LLWU_PF_WUF11_MASK (0x800U) #define LLWU_PF_WUF11_SHIFT (11U) /*! WUF11 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_WUF11(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF11_SHIFT)) & LLWU_PF_WUF11_MASK) #define LLWU_PF_WUF12_MASK (0x1000U) #define LLWU_PF_WUF12_SHIFT (12U) /*! WUF12 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_WUF12(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF12_SHIFT)) & LLWU_PF_WUF12_MASK) #define LLWU_PF_WUF13_MASK (0x2000U) #define LLWU_PF_WUF13_SHIFT (13U) /*! WUF13 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_WUF13(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF13_SHIFT)) & LLWU_PF_WUF13_MASK) #define LLWU_PF_WUF14_MASK (0x4000U) #define LLWU_PF_WUF14_SHIFT (14U) /*! WUF14 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_WUF14(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF14_SHIFT)) & LLWU_PF_WUF14_MASK) #define LLWU_PF_WUF15_MASK (0x8000U) #define LLWU_PF_WUF15_SHIFT (15U) /*! WUF15 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_WUF15(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF15_SHIFT)) & LLWU_PF_WUF15_MASK) #define LLWU_PF_Reserved16_MASK (0x10000U) #define LLWU_PF_Reserved16_SHIFT (16U) /*! Reserved16 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_Reserved16(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved16_SHIFT)) & LLWU_PF_Reserved16_MASK) #define LLWU_PF_Reserved17_MASK (0x20000U) #define LLWU_PF_Reserved17_SHIFT (17U) /*! Reserved17 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_Reserved17(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved17_SHIFT)) & LLWU_PF_Reserved17_MASK) #define LLWU_PF_Reserved18_MASK (0x40000U) #define LLWU_PF_Reserved18_SHIFT (18U) /*! Reserved18 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_Reserved18(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved18_SHIFT)) & LLWU_PF_Reserved18_MASK) #define LLWU_PF_Reserved19_MASK (0x80000U) #define LLWU_PF_Reserved19_SHIFT (19U) /*! Reserved19 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_Reserved19(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved19_SHIFT)) & LLWU_PF_Reserved19_MASK) #define LLWU_PF_Reserved20_MASK (0x100000U) #define LLWU_PF_Reserved20_SHIFT (20U) /*! Reserved20 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_Reserved20(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved20_SHIFT)) & LLWU_PF_Reserved20_MASK) #define LLWU_PF_Reserved21_MASK (0x200000U) #define LLWU_PF_Reserved21_SHIFT (21U) /*! Reserved21 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_Reserved21(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved21_SHIFT)) & LLWU_PF_Reserved21_MASK) #define LLWU_PF_Reserved22_MASK (0x400000U) #define LLWU_PF_Reserved22_SHIFT (22U) /*! Reserved22 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_Reserved22(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved22_SHIFT)) & LLWU_PF_Reserved22_MASK) #define LLWU_PF_Reserved23_MASK (0x800000U) #define LLWU_PF_Reserved23_SHIFT (23U) /*! Reserved23 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_Reserved23(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved23_SHIFT)) & LLWU_PF_Reserved23_MASK) #define LLWU_PF_Reserved24_MASK (0x1000000U) #define LLWU_PF_Reserved24_SHIFT (24U) /*! Reserved24 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_Reserved24(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved24_SHIFT)) & LLWU_PF_Reserved24_MASK) #define LLWU_PF_Reserved25_MASK (0x2000000U) #define LLWU_PF_Reserved25_SHIFT (25U) /*! Reserved25 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_Reserved25(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved25_SHIFT)) & LLWU_PF_Reserved25_MASK) #define LLWU_PF_Reserved26_MASK (0x4000000U) #define LLWU_PF_Reserved26_SHIFT (26U) /*! Reserved26 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_Reserved26(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved26_SHIFT)) & LLWU_PF_Reserved26_MASK) #define LLWU_PF_Reserved27_MASK (0x8000000U) #define LLWU_PF_Reserved27_SHIFT (27U) /*! Reserved27 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_Reserved27(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved27_SHIFT)) & LLWU_PF_Reserved27_MASK) #define LLWU_PF_Reserved28_MASK (0x10000000U) #define LLWU_PF_Reserved28_SHIFT (28U) /*! Reserved28 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved28_SHIFT)) & LLWU_PF_Reserved28_MASK) #define LLWU_PF_Reserved29_MASK (0x20000000U) #define LLWU_PF_Reserved29_SHIFT (29U) /*! Reserved29 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved29_SHIFT)) & LLWU_PF_Reserved29_MASK) #define LLWU_PF_Reserved30_MASK (0x40000000U) #define LLWU_PF_Reserved30_SHIFT (30U) /*! Reserved30 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved30_SHIFT)) & LLWU_PF_Reserved30_MASK) #define LLWU_PF_Reserved31_MASK (0x80000000U) #define LLWU_PF_Reserved31_SHIFT (31U) /*! Reserved31 - Wakeup flag for LLWU_Pn * 0b0..LLWU_Pn input was not a wakeup source * 0b1..LLWU_Pn input was a wakeup source */ #define LLWU_PF_Reserved31(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved31_SHIFT)) & LLWU_PF_Reserved31_MASK) /*! @} */ /*! @name MF - Module Interrupt Flag register */ /*! @{ */ #define LLWU_MF_MWUF0_MASK (0x1U) #define LLWU_MF_MWUF0_SHIFT (0U) /*! MWUF0 - Wakeup flag for module n * 0b0..Module input was not a wakeup source * 0b1..Module input was a wakeup source */ #define LLWU_MF_MWUF0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF0_SHIFT)) & LLWU_MF_MWUF0_MASK) #define LLWU_MF_MWUF1_MASK (0x2U) #define LLWU_MF_MWUF1_SHIFT (1U) /*! MWUF1 - Wakeup flag for module n * 0b0..Module input was not a wakeup source * 0b1..Module input was a wakeup source */ #define LLWU_MF_MWUF1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF1_SHIFT)) & LLWU_MF_MWUF1_MASK) #define LLWU_MF_MWUF2_MASK (0x4U) #define LLWU_MF_MWUF2_SHIFT (2U) /*! MWUF2 - Wakeup flag for module n * 0b0..Module input was not a wakeup source * 0b1..Module input was a wakeup source */ #define LLWU_MF_MWUF2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF2_SHIFT)) & LLWU_MF_MWUF2_MASK) #define LLWU_MF_MWUF3_MASK (0x8U) #define LLWU_MF_MWUF3_SHIFT (3U) /*! MWUF3 - Wakeup flag for module n * 0b0..Module input was not a wakeup source * 0b1..Module input was a wakeup source */ #define LLWU_MF_MWUF3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF3_SHIFT)) & LLWU_MF_MWUF3_MASK) #define LLWU_MF_MWUF4_MASK (0x10U) #define LLWU_MF_MWUF4_SHIFT (4U) /*! MWUF4 - Wakeup flag for module n * 0b0..Module input was not a wakeup source * 0b1..Module input was a wakeup source */ #define LLWU_MF_MWUF4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF4_SHIFT)) & LLWU_MF_MWUF4_MASK) #define LLWU_MF_Reserved5_MASK (0x20U) #define LLWU_MF_Reserved5_SHIFT (5U) /*! Reserved5 - Wakeup flag for module n * 0b0..Module input was not a wakeup source * 0b1..Module input was a wakeup source */ #define LLWU_MF_Reserved5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_Reserved5_SHIFT)) & LLWU_MF_Reserved5_MASK) #define LLWU_MF_MWUF6_MASK (0x40U) #define LLWU_MF_MWUF6_SHIFT (6U) /*! MWUF6 - Wakeup flag for module n * 0b0..Module input was not a wakeup source * 0b1..Module input was a wakeup source */ #define LLWU_MF_MWUF6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF6_SHIFT)) & LLWU_MF_MWUF6_MASK) #define LLWU_MF_Reserved7_MASK (0x80U) #define LLWU_MF_Reserved7_SHIFT (7U) /*! Reserved7 - Wakeup flag for module n * 0b0..Module input was not a wakeup source * 0b1..Module input was a wakeup source */ #define LLWU_MF_Reserved7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_Reserved7_SHIFT)) & LLWU_MF_Reserved7_MASK) /*! @} */ /*! @name FILT - Pin Filter register */ /*! @{ */ #define LLWU_FILT_FILTSEL1_MASK (0x1FU) #define LLWU_FILT_FILTSEL1_SHIFT (0U) /*! FILTSEL1 - Filter 1 Pin Select * 0b00000..Select LLWU_P0 for filter * 0b11111..Select LLWU_P31 for filter */ #define LLWU_FILT_FILTSEL1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL1_SHIFT)) & LLWU_FILT_FILTSEL1_MASK) #define LLWU_FILT_FILTE1_MASK (0x60U) #define LLWU_FILT_FILTE1_SHIFT (5U) /*! FILTE1 - Filter 1 Enable * 0b00..Filter disabled * 0b01..Filter posedge detect enabled * 0b10..Filter negedge detect enabled * 0b11..Filter any edge detect enabled */ #define LLWU_FILT_FILTE1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE1_SHIFT)) & LLWU_FILT_FILTE1_MASK) #define LLWU_FILT_FILTF1_MASK (0x80U) #define LLWU_FILT_FILTF1_SHIFT (7U) /*! FILTF1 - Filter 1 Flag * 0b0..Pin Filter 1 was not a wakeup source * 0b1..Pin Filter 1 was a wakeup source */ #define LLWU_FILT_FILTF1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF1_SHIFT)) & LLWU_FILT_FILTF1_MASK) #define LLWU_FILT_FILTSEL2_MASK (0x1F00U) #define LLWU_FILT_FILTSEL2_SHIFT (8U) /*! FILTSEL2 - Filter 2 Pin Select * 0b00000..Select LLWU_P0 for filter * 0b11111..Select LLWU_P31 for filter */ #define LLWU_FILT_FILTSEL2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL2_SHIFT)) & LLWU_FILT_FILTSEL2_MASK) #define LLWU_FILT_FILTE2_MASK (0x6000U) #define LLWU_FILT_FILTE2_SHIFT (13U) /*! FILTE2 - Filter 2 Enable * 0b00..Filter disabled * 0b01..Filter posedge detect enabled * 0b10..Filter negedge detect enabled * 0b11..Filter any edge detect enabled */ #define LLWU_FILT_FILTE2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE2_SHIFT)) & LLWU_FILT_FILTE2_MASK) #define LLWU_FILT_FILTF2_MASK (0x8000U) #define LLWU_FILT_FILTF2_SHIFT (15U) /*! FILTF2 - Filter 2 Flag * 0b0..Pin Filter 2 was not a wakeup source * 0b1..Pin Filter 2 was a wakeup source */ #define LLWU_FILT_FILTF2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF2_SHIFT)) & LLWU_FILT_FILTF2_MASK) #define LLWU_FILT_FILTSEL3_MASK (0x1F0000U) #define LLWU_FILT_FILTSEL3_SHIFT (16U) /*! FILTSEL3 - Filter 3 Pin Select * 0b00000..Select LLWU_P0 for filter * 0b11111..Select LLWU_P31 for filter */ #define LLWU_FILT_FILTSEL3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL3_SHIFT)) & LLWU_FILT_FILTSEL3_MASK) #define LLWU_FILT_FILTE3_MASK (0x600000U) #define LLWU_FILT_FILTE3_SHIFT (21U) /*! FILTE3 - Filter 3 Enable * 0b00..Filter disabled * 0b01..Filter posedge detect enabled * 0b10..Filter negedge detect enabled * 0b11..Filter any edge detect enabled */ #define LLWU_FILT_FILTE3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE3_SHIFT)) & LLWU_FILT_FILTE3_MASK) #define LLWU_FILT_FILTF3_MASK (0x800000U) #define LLWU_FILT_FILTF3_SHIFT (23U) /*! FILTF3 - Filter 3 Flag * 0b0..Pin Filter 1 was not a wakeup source * 0b1..Pin Filter 1 was a wakeup source */ #define LLWU_FILT_FILTF3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF3_SHIFT)) & LLWU_FILT_FILTF3_MASK) #define LLWU_FILT_FILTSEL4_MASK (0x1F000000U) #define LLWU_FILT_FILTSEL4_SHIFT (24U) /*! FILTSEL4 - Filter 4 Pin Select * 0b00000..Select LLWU_P0 for filter * 0b11111..Select LLWU_P31 for filter */ #define LLWU_FILT_FILTSEL4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL4_SHIFT)) & LLWU_FILT_FILTSEL4_MASK) #define LLWU_FILT_FILTE4_MASK (0x60000000U) #define LLWU_FILT_FILTE4_SHIFT (29U) /*! FILTE4 - Filter 4 Enable * 0b00..Filter disabled * 0b01..Filter posedge detect enabled * 0b10..Filter negedge detect enabled * 0b11..Filter any edge detect enabled */ #define LLWU_FILT_FILTE4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE4_SHIFT)) & LLWU_FILT_FILTE4_MASK) #define LLWU_FILT_FILTF4_MASK (0x80000000U) #define LLWU_FILT_FILTF4_SHIFT (31U) /*! FILTF4 - Filter 4 Flag * 0b0..Pin Filter 1 was not a wakeup source * 0b1..Pin Filter 1 was a wakeup source */ #define LLWU_FILT_FILTF4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF4_SHIFT)) & LLWU_FILT_FILTF4_MASK) /*! @} */ /*! * @} */ /* end of group LLWU_Register_Masks */ /* LLWU - Peripheral instance base addresses */ /** Peripheral LLWU base address */ #define LLWU_BASE (0x41021000u) /** Peripheral LLWU base pointer */ #define LLWU ((LLWU_Type *)LLWU_BASE) /** Array initializer of LLWU peripheral base addresses */ #define LLWU_BASE_ADDRS { LLWU_BASE } /** Array initializer of LLWU peripheral base pointers */ #define LLWU_BASE_PTRS { LLWU } /** Interrupt vectors for the LLWU peripheral type */ #define LLWU_IRQS { LLWU0_IRQn } /*! * @} */ /* end of group LLWU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LMEM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer * @{ */ /** LMEM - Register Layout Typedef */ typedef struct { __IO uint32_t PCCCR; /**< Cache control register, offset: 0x0 */ __IO uint32_t PCCLCR; /**< Cache line control register, offset: 0x4 */ __IO uint32_t PCCSAR; /**< Cache search address register, offset: 0x8 */ __IO uint32_t PCCCVR; /**< Cache read/write value register, offset: 0xC */ } LMEM_Type; /* ---------------------------------------------------------------------------- -- LMEM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LMEM_Register_Masks LMEM Register Masks * @{ */ /*! @name PCCCR - Cache control register */ /*! @{ */ #define LMEM_PCCCR_ENCACHE_MASK (0x1U) #define LMEM_PCCCR_ENCACHE_SHIFT (0U) /*! ENCACHE - Cache enable * 0b0..Cache disabled * 0b1..Cache enabled */ #define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK) #define LMEM_PCCCR_ENWRBUF_MASK (0x2U) #define LMEM_PCCCR_ENWRBUF_SHIFT (1U) /*! ENWRBUF - Enable Write Buffer * 0b0..Write buffer disabled * 0b1..Write buffer enabled */ #define LMEM_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK) #define LMEM_PCCCR_PCCR2_MASK (0x4U) #define LMEM_PCCCR_PCCR2_SHIFT (2U) /*! PCCR2 - Forces all cacheable spaces to write through */ #define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK) #define LMEM_PCCCR_PCCR3_MASK (0x8U) #define LMEM_PCCCR_PCCR3_SHIFT (3U) /*! PCCR3 - Forces no allocation on cache misses (must also have PCCR2 asserted) */ #define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK) #define LMEM_PCCCR_INVW0_MASK (0x1000000U) #define LMEM_PCCCR_INVW0_SHIFT (24U) /*! INVW0 - Invalidate Way 0 * 0b0..No operation * 0b1..When setting the GO bit, invalidate all lines in way 0. */ #define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK) #define LMEM_PCCCR_PUSHW0_MASK (0x2000000U) #define LMEM_PCCCR_PUSHW0_SHIFT (25U) /*! PUSHW0 - Push Way 0 * 0b0..No operation * 0b1..When setting the GO bit, push all modified lines in way 0 */ #define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK) #define LMEM_PCCCR_INVW1_MASK (0x4000000U) #define LMEM_PCCCR_INVW1_SHIFT (26U) /*! INVW1 - Invalidate Way 1 * 0b0..No operation * 0b1..When setting the GO bit, invalidate all lines in way 1 */ #define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK) #define LMEM_PCCCR_PUSHW1_MASK (0x8000000U) #define LMEM_PCCCR_PUSHW1_SHIFT (27U) /*! PUSHW1 - Push Way 1 * 0b0..No operation * 0b1..When setting the GO bit, push all modified lines in way 1 */ #define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK) #define LMEM_PCCCR_GO_MASK (0x80000000U) #define LMEM_PCCCR_GO_SHIFT (31U) /*! GO - Initiate Cache Command * 0b0..Write: no effect. Read: no cache command active. * 0b1..Write: initiate command indicated by bits 27-24. Read: cache command active. */ #define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK) /*! @} */ /*! @name PCCLCR - Cache line control register */ /*! @{ */ #define LMEM_PCCLCR_LGO_MASK (0x1U) #define LMEM_PCCLCR_LGO_SHIFT (0U) /*! LGO - Initiate Cache Line Command * 0b0..Write: no effect. Read: no line command active. * 0b1..Write: initiate line command indicated by bits 27-24. Read: line command active. */ #define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK) #define LMEM_PCCLCR_CACHEADDR_MASK (0x3FF8U) #define LMEM_PCCLCR_CACHEADDR_SHIFT (3U) /*! CACHEADDR - Cache address */ #define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK) #define LMEM_PCCLCR_WSEL_MASK (0x4000U) #define LMEM_PCCLCR_WSEL_SHIFT (14U) /*! WSEL - Way select * 0b0..Way 0 * 0b1..Way 1 */ #define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK) #define LMEM_PCCLCR_TDSEL_MASK (0x10000U) #define LMEM_PCCLCR_TDSEL_SHIFT (16U) /*! TDSEL - Tag/Data Select * 0b0..Data * 0b1..Tag */ #define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK) #define LMEM_PCCLCR_LCIVB_MASK (0x100000U) #define LMEM_PCCLCR_LCIVB_SHIFT (20U) /*! LCIVB - Line Command Initial Valid Bit */ #define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK) #define LMEM_PCCLCR_LCIMB_MASK (0x200000U) #define LMEM_PCCLCR_LCIMB_SHIFT (21U) /*! LCIMB - Line Command Initial Modified Bit */ #define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK) #define LMEM_PCCLCR_LCWAY_MASK (0x400000U) #define LMEM_PCCLCR_LCWAY_SHIFT (22U) /*! LCWAY - Line Command Way */ #define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK) #define LMEM_PCCLCR_LCMD_MASK (0x3000000U) #define LMEM_PCCLCR_LCMD_SHIFT (24U) /*! LCMD - Line Command * 0b00..Search and read or write * 0b01..Invalidate * 0b10..Push * 0b11..Clear */ #define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK) #define LMEM_PCCLCR_LADSEL_MASK (0x4000000U) #define LMEM_PCCLCR_LADSEL_SHIFT (26U) /*! LADSEL - Line Address Select * 0b0..Cache address * 0b1..Physical address */ #define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK) #define LMEM_PCCLCR_LACC_MASK (0x8000000U) #define LMEM_PCCLCR_LACC_SHIFT (27U) /*! LACC - Line access type * 0b0..Read * 0b1..Write */ #define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK) /*! @} */ /*! @name PCCSAR - Cache search address register */ /*! @{ */ #define LMEM_PCCSAR_LGO_MASK (0x1U) #define LMEM_PCCSAR_LGO_SHIFT (0U) /*! LGO - Initiate Cache Line Command * 0b0..Write: no effect. Read: no line command active. * 0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active. */ #define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK) #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFF8U) #define LMEM_PCCSAR_PHYADDR_SHIFT (3U) /*! PHYADDR - Physical Address */ #define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK) /*! @} */ /*! @name PCCCVR - Cache read/write value register */ /*! @{ */ #define LMEM_PCCCVR_DATA_MASK (0xFFFFFFFFU) #define LMEM_PCCCVR_DATA_SHIFT (0U) /*! DATA - Cache read/write Data */ #define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK) /*! @} */ /*! * @} */ /* end of group LMEM_Register_Masks */ /* LMEM - Peripheral instance base addresses */ /** Peripheral LMEM base address */ #define LMEM_BASE (0xE0082000u) /** Peripheral LMEM base pointer */ #define LMEM ((LMEM_Type *)LMEM_BASE) /** Array initializer of LMEM peripheral base addresses */ #define LMEM_BASE_ADDRS { LMEM_BASE } /** Array initializer of LMEM peripheral base pointers */ #define LMEM_BASE_PTRS { LMEM } /*! * @} */ /* end of group LMEM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPI2C Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer * @{ */ /** LPI2C - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */ __IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */ __IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */ __IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */ __IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */ __IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */ __IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */ __IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */ uint8_t RESERVED_1[16]; __IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */ uint8_t RESERVED_2[4]; __IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */ uint8_t RESERVED_3[4]; __IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */ uint8_t RESERVED_4[4]; __IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */ __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ __O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */ uint8_t RESERVED_5[12]; __I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */ uint8_t RESERVED_6[156]; __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ __IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */ __IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */ __IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */ uint8_t RESERVED_7[4]; __IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */ __IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */ uint8_t RESERVED_8[20]; __IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */ uint8_t RESERVED_9[12]; __I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */ __IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */ uint8_t RESERVED_10[8]; __O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */ uint8_t RESERVED_11[12]; __I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */ } LPI2C_Type; /* ---------------------------------------------------------------------------- -- LPI2C Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPI2C_Register_Masks LPI2C Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define LPI2C_VERID_FEATURE_MASK (0xFFFFU) #define LPI2C_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000010..Master only, with standard feature set * 0b0000000000000011..Master and slave, with standard feature set */ #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) #define LPI2C_VERID_MINOR_MASK (0xFF0000U) #define LPI2C_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) #define LPI2C_VERID_MAJOR_MASK (0xFF000000U) #define LPI2C_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define LPI2C_PARAM_MTXFIFO_MASK (0xFU) #define LPI2C_PARAM_MTXFIFO_SHIFT (0U) /*! MTXFIFO - Master Transmit FIFO Size */ #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) #define LPI2C_PARAM_MRXFIFO_SHIFT (8U) /*! MRXFIFO - Master Receive FIFO Size */ #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) /*! @} */ /*! @name MCR - Master Control Register */ /*! @{ */ #define LPI2C_MCR_MEN_MASK (0x1U) #define LPI2C_MCR_MEN_SHIFT (0U) /*! MEN - Master Enable * 0b0..Master logic is disabled * 0b1..Master logic is enabled */ #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) #define LPI2C_MCR_RST_MASK (0x2U) #define LPI2C_MCR_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Master logic is not reset * 0b1..Master logic is reset */ #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) #define LPI2C_MCR_DOZEN_MASK (0x4U) #define LPI2C_MCR_DOZEN_SHIFT (2U) /*! DOZEN - Doze mode enable * 0b0..Master is enabled in Doze mode * 0b1..Master is disabled in Doze mode */ #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) #define LPI2C_MCR_DBGEN_MASK (0x8U) #define LPI2C_MCR_DBGEN_SHIFT (3U) /*! DBGEN - Debug Enable * 0b0..Master is disabled in debug mode * 0b1..Master is enabled in debug mode */ #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) #define LPI2C_MCR_RTF_MASK (0x100U) #define LPI2C_MCR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO * 0b0..No effect * 0b1..Transmit FIFO is reset */ #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) #define LPI2C_MCR_RRF_MASK (0x200U) #define LPI2C_MCR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect * 0b1..Receive FIFO is reset */ #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) /*! @} */ /*! @name MSR - Master Status Register */ /*! @{ */ #define LPI2C_MSR_TDF_MASK (0x1U) #define LPI2C_MSR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag * 0b0..Transmit data is not requested * 0b1..Transmit data is requested */ #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) #define LPI2C_MSR_RDF_MASK (0x2U) #define LPI2C_MSR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag * 0b0..Receive Data is not ready * 0b1..Receive data is ready */ #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) #define LPI2C_MSR_EPF_MASK (0x100U) #define LPI2C_MSR_EPF_SHIFT (8U) /*! EPF - End Packet Flag * 0b0..Master has not generated a STOP or Repeated START condition * 0b1..Master has generated a STOP or Repeated START condition */ #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) #define LPI2C_MSR_SDF_MASK (0x200U) #define LPI2C_MSR_SDF_SHIFT (9U) /*! SDF - STOP Detect Flag * 0b0..Master has not generated a STOP condition * 0b1..Master has generated a STOP condition */ #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) #define LPI2C_MSR_NDF_MASK (0x400U) #define LPI2C_MSR_NDF_SHIFT (10U) /*! NDF - NACK Detect Flag * 0b0..Unexpected NACK was not detected * 0b1..Unexpected NACK was detected */ #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) #define LPI2C_MSR_ALF_MASK (0x800U) #define LPI2C_MSR_ALF_SHIFT (11U) /*! ALF - Arbitration Lost Flag * 0b0..Master has not lost arbitration * 0b1..Master has lost arbitration */ #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) #define LPI2C_MSR_FEF_MASK (0x1000U) #define LPI2C_MSR_FEF_SHIFT (12U) /*! FEF - FIFO Error Flag * 0b0..No error * 0b1..Master sending or receiving data without a START condition */ #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) #define LPI2C_MSR_PLTF_MASK (0x2000U) #define LPI2C_MSR_PLTF_SHIFT (13U) /*! PLTF - Pin Low Timeout Flag * 0b0..Pin low timeout has not occurred or is disabled * 0b1..Pin low timeout has occurred */ #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) #define LPI2C_MSR_DMF_MASK (0x4000U) #define LPI2C_MSR_DMF_SHIFT (14U) /*! DMF - Data Match Flag * 0b0..Have not received matching data * 0b1..Have received matching data */ #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) #define LPI2C_MSR_MBF_MASK (0x1000000U) #define LPI2C_MSR_MBF_SHIFT (24U) /*! MBF - Master Busy Flag * 0b0..I2C Master is idle * 0b1..I2C Master is busy */ #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) #define LPI2C_MSR_BBF_MASK (0x2000000U) #define LPI2C_MSR_BBF_SHIFT (25U) /*! BBF - Bus Busy Flag * 0b0..I2C Bus is idle * 0b1..I2C Bus is busy */ #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) /*! @} */ /*! @name MIER - Master Interrupt Enable Register */ /*! @{ */ #define LPI2C_MIER_TDIE_MASK (0x1U) #define LPI2C_MIER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) #define LPI2C_MIER_RDIE_MASK (0x2U) #define LPI2C_MIER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) #define LPI2C_MIER_EPIE_MASK (0x100U) #define LPI2C_MIER_EPIE_SHIFT (8U) /*! EPIE - End Packet Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) #define LPI2C_MIER_SDIE_MASK (0x200U) #define LPI2C_MIER_SDIE_SHIFT (9U) /*! SDIE - STOP Detect Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) #define LPI2C_MIER_NDIE_MASK (0x400U) #define LPI2C_MIER_NDIE_SHIFT (10U) /*! NDIE - NACK Detect Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) #define LPI2C_MIER_ALIE_MASK (0x800U) #define LPI2C_MIER_ALIE_SHIFT (11U) /*! ALIE - Arbitration Lost Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) #define LPI2C_MIER_FEIE_MASK (0x1000U) #define LPI2C_MIER_FEIE_SHIFT (12U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Enabled * 0b1..Disabled */ #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) #define LPI2C_MIER_PLTIE_MASK (0x2000U) #define LPI2C_MIER_PLTIE_SHIFT (13U) /*! PLTIE - Pin Low Timeout Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) #define LPI2C_MIER_DMIE_MASK (0x4000U) #define LPI2C_MIER_DMIE_SHIFT (14U) /*! DMIE - Data Match Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) /*! @} */ /*! @name MDER - Master DMA Enable Register */ /*! @{ */ #define LPI2C_MDER_TDDE_MASK (0x1U) #define LPI2C_MDER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) #define LPI2C_MDER_RDDE_MASK (0x2U) #define LPI2C_MDER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) /*! @} */ /*! @name MCFGR0 - Master Configuration Register 0 */ /*! @{ */ #define LPI2C_MCFGR0_HREN_MASK (0x1U) #define LPI2C_MCFGR0_HREN_SHIFT (0U) /*! HREN - Host Request Enable * 0b0..Host request input is disabled * 0b1..Host request input is enabled */ #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) #define LPI2C_MCFGR0_HRPOL_MASK (0x2U) #define LPI2C_MCFGR0_HRPOL_SHIFT (1U) /*! HRPOL - Host Request Polarity * 0b0..Active low * 0b1..Active high */ #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) #define LPI2C_MCFGR0_HRSEL_MASK (0x4U) #define LPI2C_MCFGR0_HRSEL_SHIFT (2U) /*! HRSEL - Host Request Select * 0b0..Host request input is pin HREQ * 0b1..Host request input is input trigger */ #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) /*! CIRFIFO - Circular FIFO Enable * 0b0..Circular FIFO is disabled * 0b1..Circular FIFO is enabled */ #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) #define LPI2C_MCFGR0_RDMO_MASK (0x200U) #define LPI2C_MCFGR0_RDMO_SHIFT (9U) /*! RDMO - Receive Data Match Only * 0b0..Received data is stored in the receive FIFO * 0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set */ #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) /*! @} */ /*! @name MCFGR1 - Master Configuration Register 1 */ /*! @{ */ #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) /*! PRESCALE - Prescaler * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 4 * 0b011..Divide by 8 * 0b100..Divide by 16 * 0b101..Divide by 32 * 0b110..Divide by 64 * 0b111..Divide by 128 */ #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) /*! AUTOSTOP - Automatic STOP Generation * 0b0..No effect * 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy */ #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) #define LPI2C_MCFGR1_IGNACK_MASK (0x200U) #define LPI2C_MCFGR1_IGNACK_SHIFT (9U) /*! IGNACK - IGNACK * 0b0..LPI2C Master will receive ACK and NACK normally * 0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK */ #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) /*! TIMECFG - Timeout Configuration * 0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout * 0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout */ #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) #define LPI2C_MCFGR1_MATCFG_SHIFT (16U) /*! MATCFG - Match Configuration * 0b000..Match is disabled * 0b001..Reserved * 0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1) * 0b011..Match is enabled (any data word equals MATCH0 OR MATCH1) * 0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) * 0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) * 0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) * 0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) */ #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) #define LPI2C_MCFGR1_PINCFG_SHIFT (24U) /*! PINCFG - Pin Configuration * 0b000..2-pin open drain mode * 0b001..2-pin output only mode (ultra-fast mode) * 0b010..2-pin push-pull mode * 0b011..4-pin push-pull mode * 0b100..2-pin open drain mode with separate LPI2C slave * 0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave * 0b110..2-pin push-pull mode with separate LPI2C slave * 0b111..4-pin push-pull mode (inverted outputs) */ #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) /*! @} */ /*! @name MCFGR2 - Master Configuration Register 2 */ /*! @{ */ #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) /*! BUSIDLE - Bus Idle Timeout */ #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) #define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) #define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) /*! FILTSCL - Glitch Filter SCL */ #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) /*! FILTSDA - Glitch Filter SDA */ #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) /*! @} */ /*! @name MCFGR3 - Master Configuration Register 3 */ /*! @{ */ #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) #define LPI2C_MCFGR3_PINLOW_SHIFT (8U) /*! PINLOW - Pin Low Timeout */ #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) /*! @} */ /*! @name MDMR - Master Data Match Register */ /*! @{ */ #define LPI2C_MDMR_MATCH0_MASK (0xFFU) #define LPI2C_MDMR_MATCH0_SHIFT (0U) /*! MATCH0 - Match 0 Value */ #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) #define LPI2C_MDMR_MATCH1_SHIFT (16U) /*! MATCH1 - Match 1 Value */ #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) /*! @} */ /*! @name MCCR0 - Master Clock Configuration Register 0 */ /*! @{ */ #define LPI2C_MCCR0_CLKLO_MASK (0x3FU) #define LPI2C_MCCR0_CLKLO_SHIFT (0U) /*! CLKLO - Clock Low Period */ #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) #define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) #define LPI2C_MCCR0_CLKHI_SHIFT (8U) /*! CLKHI - Clock High Period */ #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) #define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) #define LPI2C_MCCR0_SETHOLD_SHIFT (16U) /*! SETHOLD - Setup Hold Delay */ #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) #define LPI2C_MCCR0_DATAVD_SHIFT (24U) /*! DATAVD - Data Valid Delay */ #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) /*! @} */ /*! @name MCCR1 - Master Clock Configuration Register 1 */ /*! @{ */ #define LPI2C_MCCR1_CLKLO_MASK (0x3FU) #define LPI2C_MCCR1_CLKLO_SHIFT (0U) /*! CLKLO - Clock Low Period */ #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) #define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) #define LPI2C_MCCR1_CLKHI_SHIFT (8U) /*! CLKHI - Clock High Period */ #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) #define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) #define LPI2C_MCCR1_SETHOLD_SHIFT (16U) /*! SETHOLD - Setup Hold Delay */ #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) #define LPI2C_MCCR1_DATAVD_SHIFT (24U) /*! DATAVD - Data Valid Delay */ #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) /*! @} */ /*! @name MFCR - Master FIFO Control Register */ /*! @{ */ #define LPI2C_MFCR_TXWATER_MASK (0x3U) #define LPI2C_MFCR_TXWATER_SHIFT (0U) /*! TXWATER - Transmit FIFO Watermark */ #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) #define LPI2C_MFCR_RXWATER_MASK (0x30000U) #define LPI2C_MFCR_RXWATER_SHIFT (16U) /*! RXWATER - Receive FIFO Watermark */ #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) /*! @} */ /*! @name MFSR - Master FIFO Status Register */ /*! @{ */ #define LPI2C_MFSR_TXCOUNT_MASK (0x7U) #define LPI2C_MFSR_TXCOUNT_SHIFT (0U) /*! TXCOUNT - Transmit FIFO Count */ #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) #define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) #define LPI2C_MFSR_RXCOUNT_SHIFT (16U) /*! RXCOUNT - Receive FIFO Count */ #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) /*! @} */ /*! @name MTDR - Master Transmit Data Register */ /*! @{ */ #define LPI2C_MTDR_DATA_MASK (0xFFU) #define LPI2C_MTDR_DATA_SHIFT (0U) /*! DATA - Transmit Data */ #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) #define LPI2C_MTDR_CMD_MASK (0x700U) #define LPI2C_MTDR_CMD_SHIFT (8U) /*! CMD - Command Data * 0b000..Transmit DATA[7:0] * 0b001..Receive (DATA[7:0] + 1) bytes * 0b010..Generate STOP condition * 0b011..Receive and discard (DATA[7:0] + 1) bytes * 0b100..Generate (repeated) START and transmit address in DATA[7:0] * 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. * 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode * 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. */ #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) /*! @} */ /*! @name MRDR - Master Receive Data Register */ /*! @{ */ #define LPI2C_MRDR_DATA_MASK (0xFFU) #define LPI2C_MRDR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_MRDR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - RX Empty * 0b0..Receive FIFO is not empty * 0b1..Receive FIFO is empty */ #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) /*! @} */ /*! @name SCR - Slave Control Register */ /*! @{ */ #define LPI2C_SCR_SEN_MASK (0x1U) #define LPI2C_SCR_SEN_SHIFT (0U) /*! SEN - Slave Enable * 0b0..I2C Slave mode is disabled * 0b1..I2C Slave mode is enabled */ #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) #define LPI2C_SCR_RST_MASK (0x2U) #define LPI2C_SCR_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Slave mode logic is not reset * 0b1..Slave mode logic is reset */ #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) #define LPI2C_SCR_FILTEN_MASK (0x10U) #define LPI2C_SCR_FILTEN_SHIFT (4U) /*! FILTEN - Filter Enable * 0b0..Disable digital filter and output delay counter for slave mode * 0b1..Enable digital filter and output delay counter for slave mode */ #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) #define LPI2C_SCR_FILTDZ_MASK (0x20U) #define LPI2C_SCR_FILTDZ_SHIFT (5U) /*! FILTDZ - Filter Doze Enable * 0b0..Filter remains enabled in Doze mode * 0b1..Filter is disabled in Doze mode */ #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) #define LPI2C_SCR_RTF_MASK (0x100U) #define LPI2C_SCR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO * 0b0..No effect * 0b1..Transmit Data Register is now empty */ #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) #define LPI2C_SCR_RRF_MASK (0x200U) #define LPI2C_SCR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect * 0b1..Receive Data Register is now empty */ #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) /*! @} */ /*! @name SSR - Slave Status Register */ /*! @{ */ #define LPI2C_SSR_TDF_MASK (0x1U) #define LPI2C_SSR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag * 0b0..Transmit data not requested * 0b1..Transmit data is requested */ #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) #define LPI2C_SSR_RDF_MASK (0x2U) #define LPI2C_SSR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag * 0b0..Receive data is not ready * 0b1..Receive data is ready */ #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) #define LPI2C_SSR_AVF_MASK (0x4U) #define LPI2C_SSR_AVF_SHIFT (2U) /*! AVF - Address Valid Flag * 0b0..Address Status Register is not valid * 0b1..Address Status Register is valid */ #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) #define LPI2C_SSR_TAF_MASK (0x8U) #define LPI2C_SSR_TAF_SHIFT (3U) /*! TAF - Transmit ACK Flag * 0b0..Transmit ACK/NACK is not required * 0b1..Transmit ACK/NACK is required */ #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) #define LPI2C_SSR_RSF_MASK (0x100U) #define LPI2C_SSR_RSF_SHIFT (8U) /*! RSF - Repeated Start Flag * 0b0..Slave has not detected a Repeated START condition * 0b1..Slave has detected a Repeated START condition */ #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) #define LPI2C_SSR_SDF_MASK (0x200U) #define LPI2C_SSR_SDF_SHIFT (9U) /*! SDF - STOP Detect Flag * 0b0..Slave has not detected a STOP condition * 0b1..Slave has detected a STOP condition */ #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) #define LPI2C_SSR_BEF_MASK (0x400U) #define LPI2C_SSR_BEF_SHIFT (10U) /*! BEF - Bit Error Flag * 0b0..Slave has not detected a bit error * 0b1..Slave has detected a bit error */ #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) #define LPI2C_SSR_FEF_MASK (0x800U) #define LPI2C_SSR_FEF_SHIFT (11U) /*! FEF - FIFO Error Flag * 0b0..FIFO underflow or overflow was not detected * 0b1..FIFO underflow or overflow was detected */ #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) #define LPI2C_SSR_AM0F_MASK (0x1000U) #define LPI2C_SSR_AM0F_SHIFT (12U) /*! AM0F - Address Match 0 Flag * 0b0..Have not received an ADDR0 matching address * 0b1..Have received an ADDR0 matching address */ #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) #define LPI2C_SSR_AM1F_MASK (0x2000U) #define LPI2C_SSR_AM1F_SHIFT (13U) /*! AM1F - Address Match 1 Flag * 0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address * 0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address */ #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) #define LPI2C_SSR_GCF_MASK (0x4000U) #define LPI2C_SSR_GCF_SHIFT (14U) /*! GCF - General Call Flag * 0b0..Slave has not detected the General Call Address or the General Call Address is disabled * 0b1..Slave has detected the General Call Address */ #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) #define LPI2C_SSR_SARF_MASK (0x8000U) #define LPI2C_SSR_SARF_SHIFT (15U) /*! SARF - SMBus Alert Response Flag * 0b0..SMBus Alert Response is disabled or not detected * 0b1..SMBus Alert Response is enabled and detected */ #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) #define LPI2C_SSR_SBF_MASK (0x1000000U) #define LPI2C_SSR_SBF_SHIFT (24U) /*! SBF - Slave Busy Flag * 0b0..I2C Slave is idle * 0b1..I2C Slave is busy */ #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) #define LPI2C_SSR_BBF_MASK (0x2000000U) #define LPI2C_SSR_BBF_SHIFT (25U) /*! BBF - Bus Busy Flag * 0b0..I2C Bus is idle * 0b1..I2C Bus is busy */ #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) /*! @} */ /*! @name SIER - Slave Interrupt Enable Register */ /*! @{ */ #define LPI2C_SIER_TDIE_MASK (0x1U) #define LPI2C_SIER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) #define LPI2C_SIER_RDIE_MASK (0x2U) #define LPI2C_SIER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) #define LPI2C_SIER_AVIE_MASK (0x4U) #define LPI2C_SIER_AVIE_SHIFT (2U) /*! AVIE - Address Valid Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) #define LPI2C_SIER_TAIE_MASK (0x8U) #define LPI2C_SIER_TAIE_SHIFT (3U) /*! TAIE - Transmit ACK Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) #define LPI2C_SIER_RSIE_MASK (0x100U) #define LPI2C_SIER_RSIE_SHIFT (8U) /*! RSIE - Repeated Start Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) #define LPI2C_SIER_SDIE_MASK (0x200U) #define LPI2C_SIER_SDIE_SHIFT (9U) /*! SDIE - STOP Detect Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) #define LPI2C_SIER_BEIE_MASK (0x400U) #define LPI2C_SIER_BEIE_SHIFT (10U) /*! BEIE - Bit Error Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) #define LPI2C_SIER_FEIE_MASK (0x800U) #define LPI2C_SIER_FEIE_SHIFT (11U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) #define LPI2C_SIER_AM0IE_MASK (0x1000U) #define LPI2C_SIER_AM0IE_SHIFT (12U) /*! AM0IE - Address Match 0 Interrupt Enable * 0b0..Enabled * 0b1..Disabled */ #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) #define LPI2C_SIER_AM1F_MASK (0x2000U) #define LPI2C_SIER_AM1F_SHIFT (13U) /*! AM1F - Address Match 1 Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) #define LPI2C_SIER_GCIE_MASK (0x4000U) #define LPI2C_SIER_GCIE_SHIFT (14U) /*! GCIE - General Call Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) #define LPI2C_SIER_SARIE_MASK (0x8000U) #define LPI2C_SIER_SARIE_SHIFT (15U) /*! SARIE - SMBus Alert Response Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) /*! @} */ /*! @name SDER - Slave DMA Enable Register */ /*! @{ */ #define LPI2C_SDER_TDDE_MASK (0x1U) #define LPI2C_SDER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) #define LPI2C_SDER_RDDE_MASK (0x2U) #define LPI2C_SDER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) #define LPI2C_SDER_AVDE_MASK (0x4U) #define LPI2C_SDER_AVDE_SHIFT (2U) /*! AVDE - Address Valid DMA Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) /*! @} */ /*! @name SCFGR1 - Slave Configuration Register 1 */ /*! @{ */ #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) /*! ADRSTALL - Address SCL Stall * 0b0..Clock stretching is disabled * 0b1..Clock stretching is enabled */ #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) /*! RXSTALL - RX SCL Stall * 0b0..Clock stretching is disabled * 0b1..Clock stretching is enabled */ #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) /*! TXDSTALL - TX Data SCL Stall * 0b0..Clock stretching is disabled * 0b1..Clock stretching is enabled */ #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) /*! ACKSTALL - ACK SCL Stall * 0b0..Clock stretching is disabled * 0b1..Clock stretching is enabled */ #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) #define LPI2C_SCFGR1_GCEN_MASK (0x100U) #define LPI2C_SCFGR1_GCEN_SHIFT (8U) /*! GCEN - General Call Enable * 0b0..General Call address is disabled * 0b1..General Call address is enabled */ #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) #define LPI2C_SCFGR1_SAEN_MASK (0x200U) #define LPI2C_SCFGR1_SAEN_SHIFT (9U) /*! SAEN - SMBus Alert Enable * 0b0..Disables match on SMBus Alert * 0b1..Enables match on SMBus Alert */ #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) #define LPI2C_SCFGR1_TXCFG_MASK (0x400U) #define LPI2C_SCFGR1_TXCFG_SHIFT (10U) /*! TXCFG - Transmit Flag Configuration * 0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty * 0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty */ #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) #define LPI2C_SCFGR1_RXCFG_MASK (0x800U) #define LPI2C_SCFGR1_RXCFG_SHIFT (11U) /*! RXCFG - Receive Data Configuration * 0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). * 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address * Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid * flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). */ #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) #define LPI2C_SCFGR1_IGNACK_SHIFT (12U) /*! IGNACK - Ignore NACK * 0b0..Slave will end transfer when NACK is detected * 0b1..Slave will not end transfer when NACK detected */ #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) #define LPI2C_SCFGR1_HSMEN_SHIFT (13U) /*! HSMEN - High Speed Mode Enable * 0b0..Disables detection of HS-mode master code * 0b1..Enables detection of HS-mode master code */ #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) /*! ADDRCFG - Address Configuration * 0b000..Address match 0 (7-bit) * 0b001..Address match 0 (10-bit) * 0b010..Address match 0 (7-bit) or Address match 1 (7-bit) * 0b011..Address match 0 (10-bit) or Address match 1 (10-bit) * 0b100..Address match 0 (7-bit) or Address match 1 (10-bit) * 0b101..Address match 0 (10-bit) or Address match 1 (7-bit) * 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit) * 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit) */ #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) /*! @} */ /*! @name SCFGR2 - Slave Configuration Register 2 */ /*! @{ */ #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) /*! CLKHOLD - Clock Hold Time */ #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) #define LPI2C_SCFGR2_DATAVD_SHIFT (8U) /*! DATAVD - Data Valid Delay */ #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) /*! FILTSCL - Glitch Filter SCL */ #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) /*! FILTSDA - Glitch Filter SDA */ #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) /*! @} */ /*! @name SAMR - Slave Address Match Register */ /*! @{ */ #define LPI2C_SAMR_ADDR0_MASK (0x7FEU) #define LPI2C_SAMR_ADDR0_SHIFT (1U) /*! ADDR0 - Address 0 Value */ #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) #define LPI2C_SAMR_ADDR1_SHIFT (17U) /*! ADDR1 - Address 1 Value */ #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) /*! @} */ /*! @name SASR - Slave Address Status Register */ /*! @{ */ #define LPI2C_SASR_RADDR_MASK (0x7FFU) #define LPI2C_SASR_RADDR_SHIFT (0U) /*! RADDR - Received Address */ #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) #define LPI2C_SASR_ANV_MASK (0x4000U) #define LPI2C_SASR_ANV_SHIFT (14U) /*! ANV - Address Not Valid * 0b0..Received Address (RADDR) is valid * 0b1..Received Address (RADDR) is not valid */ #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) /*! @} */ /*! @name STAR - Slave Transmit ACK Register */ /*! @{ */ #define LPI2C_STAR_TXNACK_MASK (0x1U) #define LPI2C_STAR_TXNACK_SHIFT (0U) /*! TXNACK - Transmit NACK * 0b0..Write a Transmit ACK for each received word * 0b1..Write a Transmit NACK for each received word */ #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) /*! @} */ /*! @name STDR - Slave Transmit Data Register */ /*! @{ */ #define LPI2C_STDR_DATA_MASK (0xFFU) #define LPI2C_STDR_DATA_SHIFT (0U) /*! DATA - Transmit Data */ #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) /*! @} */ /*! @name SRDR - Slave Receive Data Register */ /*! @{ */ #define LPI2C_SRDR_DATA_MASK (0xFFU) #define LPI2C_SRDR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_SRDR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - RX Empty * 0b0..The Receive Data Register is not empty * 0b1..The Receive Data Register is empty */ #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) #define LPI2C_SRDR_SOF_MASK (0x8000U) #define LPI2C_SRDR_SOF_SHIFT (15U) /*! SOF - Start Of Frame * 0b0..Indicates this is not the first data word since a (repeated) START or STOP condition * 0b1..Indicates this is the first data word since a (repeated) START or STOP condition */ #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) /*! @} */ /*! * @} */ /* end of group LPI2C_Register_Masks */ /* LPI2C - Peripheral instance base addresses */ /** Peripheral LPI2C0 base address */ #define LPI2C0_BASE (0x41033000u) /** Peripheral LPI2C0 base pointer */ #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) /** Peripheral LPI2C1 base address */ #define LPI2C1_BASE (0x41034000u) /** Peripheral LPI2C1 base pointer */ #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) /** Peripheral LPI2C2 base address */ #define LPI2C2_BASE (0x41035000u) /** Peripheral LPI2C2 base pointer */ #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) /** Peripheral LPI2C3 base address */ #define LPI2C3_BASE (0x41036000u) /** Peripheral LPI2C3 base pointer */ #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) /** Peripheral LPI2C4 base address */ #define LPI2C4_BASE (0x402B0000u) /** Peripheral LPI2C4 base pointer */ #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) /** Peripheral LPI2C5 base address */ #define LPI2C5_BASE (0x402C0000u) /** Peripheral LPI2C5 base pointer */ #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) /** Peripheral LPI2C6 base address */ #define LPI2C6_BASE (0x40A40000u) /** Peripheral LPI2C6 base pointer */ #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) /** Peripheral LPI2C7 base address */ #define LPI2C7_BASE (0x40A50000u) /** Peripheral LPI2C7 base pointer */ #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) /** Array initializer of LPI2C peripheral base addresses */ #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE } /** Array initializer of LPI2C peripheral base pointers */ #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7 } /** Interrupt vectors for the LPI2C peripheral type */ #define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } /*! * @} */ /* end of group LPI2C_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPIT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer * @{ */ /** LPIT - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __IO uint32_t MCR; /**< Module Control Register, offset: 0x8 */ __IO uint32_t MSR; /**< Module Status Register, offset: 0xC */ __IO uint32_t MIER; /**< Module Interrupt Enable Register, offset: 0x10 */ __IO uint32_t SETTEN; /**< Set Timer Enable Register, offset: 0x14 */ __O uint32_t CLRTEN; /**< Clear Timer Enable Register, offset: 0x18 */ uint8_t RESERVED_0[4]; struct { /* offset: 0x20, array step: 0x10 */ __IO uint32_t TVAL; /**< Timer Value Register, array offset: 0x20, array step: 0x10 */ __I uint32_t CVAL; /**< Current Timer Value, array offset: 0x24, array step: 0x10 */ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x28, array step: 0x10 */ uint8_t RESERVED_0[4]; } CHANNEL[4]; } LPIT_Type; /* ---------------------------------------------------------------------------- -- LPIT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPIT_Register_Masks LPIT Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define LPIT_VERID_FEATURE_MASK (0xFFFFU) #define LPIT_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Number */ #define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK) #define LPIT_VERID_MINOR_MASK (0xFF0000U) #define LPIT_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK) #define LPIT_VERID_MAJOR_MASK (0xFF000000U) #define LPIT_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define LPIT_PARAM_CHANNEL_MASK (0xFFU) #define LPIT_PARAM_CHANNEL_SHIFT (0U) /*! CHANNEL - Number of Timer Channels */ #define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK) #define LPIT_PARAM_EXT_TRIG_MASK (0xFF00U) #define LPIT_PARAM_EXT_TRIG_SHIFT (8U) /*! EXT_TRIG - Number of External Trigger Inputs */ #define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK) /*! @} */ /*! @name MCR - Module Control Register */ /*! @{ */ #define LPIT_MCR_M_CEN_MASK (0x1U) #define LPIT_MCR_M_CEN_SHIFT (0U) /*! M_CEN - Module Clock Enable * 0b0..Disable peripheral clock to timers * 0b1..Enable peripheral clock to timers */ #define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK) #define LPIT_MCR_SW_RST_MASK (0x2U) #define LPIT_MCR_SW_RST_SHIFT (1U) /*! SW_RST - Software Reset Bit * 0b0..Timer channels and registers are not reset * 0b1..Reset timer channels and registers */ #define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK) #define LPIT_MCR_DOZE_EN_MASK (0x4U) #define LPIT_MCR_DOZE_EN_SHIFT (2U) /*! DOZE_EN - DOZE Mode Enable Bit * 0b0..Stop timer channels in DOZE mode * 0b1..Allow timer channels to continue to run in DOZE mode */ #define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK) #define LPIT_MCR_DBG_EN_MASK (0x8U) #define LPIT_MCR_DBG_EN_SHIFT (3U) /*! DBG_EN - Debug Enable Bit * 0b0..Stop timer channels in Debug mode * 0b1..Allow timer channels to continue to run in Debug mode */ #define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK) /*! @} */ /*! @name MSR - Module Status Register */ /*! @{ */ #define LPIT_MSR_TIF0_MASK (0x1U) #define LPIT_MSR_TIF0_SHIFT (0U) /*! TIF0 - Channel 0 Timer Interrupt Flag * 0b0..Timer has not timed out * 0b1..Timeout has occurred (timer has timed out) */ #define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK) #define LPIT_MSR_TIF1_MASK (0x2U) #define LPIT_MSR_TIF1_SHIFT (1U) /*! TIF1 - Channel 1 Timer Interrupt Flag * 0b0..Timer has not timed out * 0b1..Timeout has occurred (timer has timed out) */ #define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK) #define LPIT_MSR_TIF2_MASK (0x4U) #define LPIT_MSR_TIF2_SHIFT (2U) /*! TIF2 - Channel 2 Timer Interrupt Flag * 0b0..Timer has not timed out * 0b1..Timeout has occurred (timer has timed out) */ #define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK) #define LPIT_MSR_TIF3_MASK (0x8U) #define LPIT_MSR_TIF3_SHIFT (3U) /*! TIF3 - Channel 3 Timer Interrupt Flag * 0b0..Timer has not timed out * 0b1..Timeout has occurred (timer has timed out) */ #define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK) /*! @} */ /*! @name MIER - Module Interrupt Enable Register */ /*! @{ */ #define LPIT_MIER_TIE0_MASK (0x1U) #define LPIT_MIER_TIE0_SHIFT (0U) /*! TIE0 - Channel 0 Timer Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK) #define LPIT_MIER_TIE1_MASK (0x2U) #define LPIT_MIER_TIE1_SHIFT (1U) /*! TIE1 - Channel 1 Timer Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK) #define LPIT_MIER_TIE2_MASK (0x4U) #define LPIT_MIER_TIE2_SHIFT (2U) /*! TIE2 - Channel 2 Timer Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK) #define LPIT_MIER_TIE3_MASK (0x8U) #define LPIT_MIER_TIE3_SHIFT (3U) /*! TIE3 - Channel 3 Timer Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK) /*! @} */ /*! @name SETTEN - Set Timer Enable Register */ /*! @{ */ #define LPIT_SETTEN_SET_T_EN_0_MASK (0x1U) #define LPIT_SETTEN_SET_T_EN_0_SHIFT (0U) /*! SET_T_EN_0 - Set Timer 0 Enable * 0b0..No effect * 0b1..Enables Timer Channel 0 */ #define LPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK) #define LPIT_SETTEN_SET_T_EN_1_MASK (0x2U) #define LPIT_SETTEN_SET_T_EN_1_SHIFT (1U) /*! SET_T_EN_1 - Set Timer 1 Enable * 0b0..No Effect * 0b1..Enables Timer Channel 1 */ #define LPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK) #define LPIT_SETTEN_SET_T_EN_2_MASK (0x4U) #define LPIT_SETTEN_SET_T_EN_2_SHIFT (2U) /*! SET_T_EN_2 - Set Timer 2 Enable * 0b0..No Effect * 0b1..Enables Timer Channel 2 */ #define LPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK) #define LPIT_SETTEN_SET_T_EN_3_MASK (0x8U) #define LPIT_SETTEN_SET_T_EN_3_SHIFT (3U) /*! SET_T_EN_3 - Set Timer 3 Enable * 0b0..No effect * 0b1..Enables Timer Channel 3 */ #define LPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK) /*! @} */ /*! @name CLRTEN - Clear Timer Enable Register */ /*! @{ */ #define LPIT_CLRTEN_CLR_T_EN_0_MASK (0x1U) #define LPIT_CLRTEN_CLR_T_EN_0_SHIFT (0U) /*! CLR_T_EN_0 - Clear Timer 0 Enable * 0b0..No action * 0b1..Clear the Timer Enable bit (TCTRL0[T_EN]) for Timer Channel 0 */ #define LPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK) #define LPIT_CLRTEN_CLR_T_EN_1_MASK (0x2U) #define LPIT_CLRTEN_CLR_T_EN_1_SHIFT (1U) /*! CLR_T_EN_1 - Clear Timer 1 Enable * 0b0..No Action * 0b1..Clear the Timer Enable bit (TCTRL1[T_EN]) for Timer Channel 1 */ #define LPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK) #define LPIT_CLRTEN_CLR_T_EN_2_MASK (0x4U) #define LPIT_CLRTEN_CLR_T_EN_2_SHIFT (2U) /*! CLR_T_EN_2 - Clear Timer 2 Enable * 0b0..No Action * 0b1..Clear the Timer Enable bit (TCTRL2[T_EN]) for Timer Channel 2 */ #define LPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK) #define LPIT_CLRTEN_CLR_T_EN_3_MASK (0x8U) #define LPIT_CLRTEN_CLR_T_EN_3_SHIFT (3U) /*! CLR_T_EN_3 - Clear Timer 3 Enable * 0b0..No Action * 0b1..Clear the Timer Enable bit (TCTRL3[T_EN]) for Timer Channel 3 */ #define LPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK) /*! @} */ /*! @name TVAL - Timer Value Register */ /*! @{ */ #define LPIT_TVAL_TMR_VAL_MASK (0xFFFFFFFFU) #define LPIT_TVAL_TMR_VAL_SHIFT (0U) /*! TMR_VAL - Timer Value * 0b00000000000000000000000000000000..Invalid load value in compare mode * 0b00000000000000000000000000000001..Invalid load value in compare mode * 0b00000000000000000000000000000010-0b11111111111111111111111111111111..In compare mode: the value to be loaded; in capture mode, the value of the timer */ #define LPIT_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK) /*! @} */ /* The count of LPIT_TVAL */ #define LPIT_TVAL_COUNT (4U) /*! @name CVAL - Current Timer Value */ /*! @{ */ #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) #define LPIT_CVAL_TMR_CUR_VAL_SHIFT (0U) /*! TMR_CUR_VAL - Current Timer Value */ #define LPIT_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK) /*! @} */ /* The count of LPIT_CVAL */ #define LPIT_CVAL_COUNT (4U) /*! @name TCTRL - Timer Control Register */ /*! @{ */ #define LPIT_TCTRL_T_EN_MASK (0x1U) #define LPIT_TCTRL_T_EN_SHIFT (0U) /*! T_EN - Timer Enable * 0b0..Timer Channel is disabled * 0b1..Timer Channel is enabled */ #define LPIT_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK) #define LPIT_TCTRL_CHAIN_MASK (0x2U) #define LPIT_TCTRL_CHAIN_SHIFT (1U) /*! CHAIN - Chain Channel * 0b0..Channel Chaining is disabled. The channel timer runs independently. * 0b1..Channel Chaining is enabled. The timer decrements on the previous channel's timeout. */ #define LPIT_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK) #define LPIT_TCTRL_MODE_MASK (0xCU) #define LPIT_TCTRL_MODE_SHIFT (2U) /*! MODE - Timer Operation Mode * 0b00..32-bit Periodic Counter * 0b01..Dual 16-bit Periodic Counter * 0b10..32-bit Trigger Accumulator * 0b11..32-bit Trigger Input Capture */ #define LPIT_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK) #define LPIT_TCTRL_TSOT_MASK (0x10000U) #define LPIT_TCTRL_TSOT_SHIFT (16U) /*! TSOT - Timer Start On Trigger * 0b0..Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI)) * 0b1..Timer starts to decrement when a rising edge on a selected trigger is detected */ #define LPIT_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK) #define LPIT_TCTRL_TSOI_MASK (0x20000U) #define LPIT_TCTRL_TSOI_SHIFT (17U) /*! TSOI - Timer Stop On Interrupt * 0b0..The channel timer does not stop after timeout * 0b1..The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On * Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable * bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, * the channel timer will restart after a rising edge on the selected trigger is detected. */ #define LPIT_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK) #define LPIT_TCTRL_TROT_MASK (0x40000U) #define LPIT_TCTRL_TROT_SHIFT (18U) /*! TROT - Timer Reload On Trigger * 0b0..Timer will not reload on the selected trigger * 0b1..Timer will reload on the selected trigger */ #define LPIT_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK) #define LPIT_TCTRL_TRG_SRC_MASK (0x800000U) #define LPIT_TCTRL_TRG_SRC_SHIFT (23U) /*! TRG_SRC - Trigger Source * 0b0..Selects external triggers * 0b1..Selects internal triggers */ #define LPIT_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK) #define LPIT_TCTRL_TRG_SEL_MASK (0xF000000U) #define LPIT_TCTRL_TRG_SEL_SHIFT (24U) /*! TRG_SEL - Trigger Select * 0b0000-0b0011..Timer channel 0 - 3 trigger source is selected * 0b0100-0b1111..Reserved */ #define LPIT_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK) /*! @} */ /* The count of LPIT_TCTRL */ #define LPIT_TCTRL_COUNT (4U) /*! * @} */ /* end of group LPIT_Register_Masks */ /* LPIT - Peripheral instance base addresses */ /** Peripheral LPIT0 base address */ #define LPIT0_BASE (0x4102D000u) /** Peripheral LPIT0 base pointer */ #define LPIT0 ((LPIT_Type *)LPIT0_BASE) /** Peripheral LPIT1 base address */ #define LPIT1_BASE (0x40270000u) /** Peripheral LPIT1 base pointer */ #define LPIT1 ((LPIT_Type *)LPIT1_BASE) /** Array initializer of LPIT peripheral base addresses */ #define LPIT_BASE_ADDRS { LPIT0_BASE, LPIT1_BASE } /** Array initializer of LPIT peripheral base pointers */ #define LPIT_BASE_PTRS { LPIT0, LPIT1 } /** Interrupt vectors for the LPIT peripheral type */ #define LPIT_IRQS { { LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn }, { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } } /*! * @} */ /* end of group LPIT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPSPI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer * @{ */ /** LPSPI - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t CR; /**< Control Register, offset: 0x10 */ __IO uint32_t SR; /**< Status Register, offset: 0x14 */ __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */ __IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */ __IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */ __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ uint8_t RESERVED_1[8]; __IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */ __IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */ uint8_t RESERVED_2[8]; __IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ uint8_t RESERVED_3[20]; __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ __I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */ __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */ __O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */ uint8_t RESERVED_4[8]; __I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */ __I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */ } LPSPI_Type; /* ---------------------------------------------------------------------------- -- LPSPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPSPI_Register_Masks LPSPI Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define LPSPI_VERID_FEATURE_MASK (0xFFFFU) #define LPSPI_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Module Identification Number * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. */ #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) #define LPSPI_VERID_MINOR_MASK (0xFF0000U) #define LPSPI_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) #define LPSPI_VERID_MAJOR_MASK (0xFF000000U) #define LPSPI_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define LPSPI_PARAM_TXFIFO_MASK (0xFFU) #define LPSPI_PARAM_TXFIFO_SHIFT (0U) /*! TXFIFO - Transmit FIFO Size */ #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) #define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) #define LPSPI_PARAM_RXFIFO_SHIFT (8U) /*! RXFIFO - Receive FIFO Size */ #define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) /*! @} */ /*! @name CR - Control Register */ /*! @{ */ #define LPSPI_CR_MEN_MASK (0x1U) #define LPSPI_CR_MEN_SHIFT (0U) /*! MEN - Module Enable * 0b0..Module is disabled * 0b1..Module is enabled */ #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) #define LPSPI_CR_RST_MASK (0x2U) #define LPSPI_CR_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Module is not reset * 0b1..Module is reset */ #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) #define LPSPI_CR_DOZEN_MASK (0x4U) #define LPSPI_CR_DOZEN_SHIFT (2U) /*! DOZEN - Doze Mode Enable * 0b0..LPSPI module is enabled in Doze mode * 0b1..LPSPI module is disabled in Doze mode */ #define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) #define LPSPI_CR_DBGEN_MASK (0x8U) #define LPSPI_CR_DBGEN_SHIFT (3U) /*! DBGEN - Debug Enable * 0b0..LPSPI module is disabled in debug mode * 0b1..LPSPI module is enabled in debug mode */ #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) #define LPSPI_CR_RTF_MASK (0x100U) #define LPSPI_CR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO * 0b0..No effect * 0b1..Transmit FIFO is reset */ #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) #define LPSPI_CR_RRF_MASK (0x200U) #define LPSPI_CR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect * 0b1..Receive FIFO is reset */ #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) /*! @} */ /*! @name SR - Status Register */ /*! @{ */ #define LPSPI_SR_TDF_MASK (0x1U) #define LPSPI_SR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag * 0b0..Transmit data not requested * 0b1..Transmit data is requested */ #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) #define LPSPI_SR_RDF_MASK (0x2U) #define LPSPI_SR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag * 0b0..Receive Data is not ready * 0b1..Receive data is ready */ #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) #define LPSPI_SR_WCF_MASK (0x100U) #define LPSPI_SR_WCF_SHIFT (8U) /*! WCF - Word Complete Flag * 0b0..Transfer of a received word has not yet completed * 0b1..Transfer of a received word has completed */ #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) #define LPSPI_SR_FCF_MASK (0x200U) #define LPSPI_SR_FCF_SHIFT (9U) /*! FCF - Frame Complete Flag * 0b0..Frame transfer has not completed * 0b1..Frame transfer has completed */ #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) #define LPSPI_SR_TCF_MASK (0x400U) #define LPSPI_SR_TCF_SHIFT (10U) /*! TCF - Transfer Complete Flag * 0b0..All transfers have not completed * 0b1..All transfers have completed */ #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) #define LPSPI_SR_TEF_MASK (0x800U) #define LPSPI_SR_TEF_SHIFT (11U) /*! TEF - Transmit Error Flag * 0b0..Transmit FIFO underrun has not occurred * 0b1..Transmit FIFO underrun has occurred */ #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) #define LPSPI_SR_REF_MASK (0x1000U) #define LPSPI_SR_REF_SHIFT (12U) /*! REF - Receive Error Flag * 0b0..Receive FIFO has not overflowed * 0b1..Receive FIFO has overflowed */ #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) #define LPSPI_SR_DMF_MASK (0x2000U) #define LPSPI_SR_DMF_SHIFT (13U) /*! DMF - Data Match Flag * 0b0..Have not received matching data * 0b1..Have received matching data */ #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) #define LPSPI_SR_MBF_MASK (0x1000000U) #define LPSPI_SR_MBF_SHIFT (24U) /*! MBF - Module Busy Flag * 0b0..LPSPI is idle * 0b1..LPSPI is busy */ #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) /*! @} */ /*! @name IER - Interrupt Enable Register */ /*! @{ */ #define LPSPI_IER_TDIE_MASK (0x1U) #define LPSPI_IER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) #define LPSPI_IER_RDIE_MASK (0x2U) #define LPSPI_IER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) #define LPSPI_IER_WCIE_MASK (0x100U) #define LPSPI_IER_WCIE_SHIFT (8U) /*! WCIE - Word Complete Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) #define LPSPI_IER_FCIE_MASK (0x200U) #define LPSPI_IER_FCIE_SHIFT (9U) /*! FCIE - Frame Complete Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) #define LPSPI_IER_TCIE_MASK (0x400U) #define LPSPI_IER_TCIE_SHIFT (10U) /*! TCIE - Transfer Complete Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) #define LPSPI_IER_TEIE_MASK (0x800U) #define LPSPI_IER_TEIE_SHIFT (11U) /*! TEIE - Transmit Error Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) #define LPSPI_IER_REIE_MASK (0x1000U) #define LPSPI_IER_REIE_SHIFT (12U) /*! REIE - Receive Error Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) #define LPSPI_IER_DMIE_MASK (0x2000U) #define LPSPI_IER_DMIE_SHIFT (13U) /*! DMIE - Data Match Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) /*! @} */ /*! @name DER - DMA Enable Register */ /*! @{ */ #define LPSPI_DER_TDDE_MASK (0x1U) #define LPSPI_DER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) #define LPSPI_DER_RDDE_MASK (0x2U) #define LPSPI_DER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) #define LPSPI_DER_FCDE_MASK (0x200U) #define LPSPI_DER_FCDE_SHIFT (9U) /*! FCDE - Frame Complete DMA Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define LPSPI_DER_FCDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK) /*! @} */ /*! @name CFGR0 - Configuration Register 0 */ /*! @{ */ #define LPSPI_CFGR0_HREN_MASK (0x1U) #define LPSPI_CFGR0_HREN_SHIFT (0U) /*! HREN - Host Request Enable * 0b0..Host request is disabled * 0b1..Host request is enabled */ #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) #define LPSPI_CFGR0_HRPOL_MASK (0x2U) #define LPSPI_CFGR0_HRPOL_SHIFT (1U) /*! HRPOL - Host Request Polarity * 0b0..Active low * 0b1..Active high */ #define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) #define LPSPI_CFGR0_HRSEL_MASK (0x4U) #define LPSPI_CFGR0_HRSEL_SHIFT (2U) /*! HRSEL - Host Request Select * 0b0..Host request input is the LPSPI_HREQ pin * 0b1..Host request input is the input trigger */ #define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) #define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) #define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) /*! CIRFIFO - Circular FIFO Enable * 0b0..Circular FIFO is disabled * 0b1..Circular FIFO is enabled */ #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) #define LPSPI_CFGR0_RDMO_MASK (0x200U) #define LPSPI_CFGR0_RDMO_SHIFT (9U) /*! RDMO - Receive Data Match Only * 0b0..Received data is stored in the receive FIFO as in normal operations * 0b1..Received data is discarded unless the Data Match Flag (DMF) is set */ #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) /*! @} */ /*! @name CFGR1 - Configuration Register 1 */ /*! @{ */ #define LPSPI_CFGR1_MASTER_MASK (0x1U) #define LPSPI_CFGR1_MASTER_SHIFT (0U) /*! MASTER - Master Mode * 0b0..Slave mode * 0b1..Master mode */ #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) #define LPSPI_CFGR1_SAMPLE_MASK (0x2U) #define LPSPI_CFGR1_SAMPLE_SHIFT (1U) /*! SAMPLE - Sample Point * 0b0..Input data is sampled on SCK edge * 0b1..Input data is sampled on delayed SCK edge */ #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) #define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) #define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) /*! AUTOPCS - Automatic PCS * 0b0..Automatic PCS generation is disabled * 0b1..Automatic PCS generation is enabled */ #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) #define LPSPI_CFGR1_NOSTALL_MASK (0x8U) #define LPSPI_CFGR1_NOSTALL_SHIFT (3U) /*! NOSTALL - No Stall * 0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full * 0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur */ #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) #define LPSPI_CFGR1_PCSPOL_SHIFT (8U) /*! PCSPOL - Peripheral Chip Select Polarity */ #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) #define LPSPI_CFGR1_MATCFG_SHIFT (16U) /*! MATCFG - Match Configuration * 0b000..Match is disabled * 0b001..Reserved * 0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) * 0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) * 0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st * data word = MATCH0) * (2nd data word = MATCH1)] * 0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., * [(any data word = MATCH0) * (next data word = MATCH1)] * 0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] * 0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] */ #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) #define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) #define LPSPI_CFGR1_PINCFG_SHIFT (24U) /*! PINCFG - Pin Configuration * 0b00..SIN is used for input data and SOUT is used for output data * 0b01..SIN is used for both input and output data * 0b10..SOUT is used for both input and output data * 0b11..SOUT is used for input data and SIN is used for output data */ #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) #define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) #define LPSPI_CFGR1_OUTCFG_SHIFT (26U) /*! OUTCFG - Output Configuration * 0b0..Output data retains last value when chip select is negated * 0b1..Output data is tristated when chip select is negated */ #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) #define LPSPI_CFGR1_PCSCFG_SHIFT (27U) /*! PCSCFG - Peripheral Chip Select Configuration * 0b0..PCS[3:2] are enabled * 0b1..PCS[3:2] are disabled */ #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) /*! @} */ /*! @name DMR0 - Data Match Register 0 */ /*! @{ */ #define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) #define LPSPI_DMR0_MATCH0_SHIFT (0U) /*! MATCH0 - Match 0 Value */ #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) /*! @} */ /*! @name DMR1 - Data Match Register 1 */ /*! @{ */ #define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) #define LPSPI_DMR1_MATCH1_SHIFT (0U) /*! MATCH1 - Match 1 Value */ #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) /*! @} */ /*! @name CCR - Clock Configuration Register */ /*! @{ */ #define LPSPI_CCR_SCKDIV_MASK (0xFFU) #define LPSPI_CCR_SCKDIV_SHIFT (0U) /*! SCKDIV - SCK Divider */ #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) #define LPSPI_CCR_DBT_MASK (0xFF00U) #define LPSPI_CCR_DBT_SHIFT (8U) /*! DBT - Delay Between Transfers */ #define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) #define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) #define LPSPI_CCR_PCSSCK_SHIFT (16U) /*! PCSSCK - PCS-to-SCK Delay */ #define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) #define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) #define LPSPI_CCR_SCKPCS_SHIFT (24U) /*! SCKPCS - SCK-to-PCS Delay */ #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) /*! @} */ /*! @name FCR - FIFO Control Register */ /*! @{ */ #define LPSPI_FCR_TXWATER_MASK (0xFU) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ #define LPSPI_FCR_TXWATER_SHIFT (0U) /*! TXWATER - Transmit FIFO Watermark */ #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ #define LPSPI_FCR_RXWATER_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ #define LPSPI_FCR_RXWATER_SHIFT (16U) /*! RXWATER - Receive FIFO Watermark */ #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ /*! @} */ /*! @name FSR - FIFO Status Register */ /*! @{ */ #define LPSPI_FSR_TXCOUNT_MASK (0x1FU) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define LPSPI_FSR_TXCOUNT_SHIFT (0U) /*! TXCOUNT - Transmit FIFO Count */ #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define LPSPI_FSR_RXCOUNT_SHIFT (16U) /*! RXCOUNT - Receive FIFO Count */ #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ /*! @} */ /*! @name TCR - Transmit Command Register */ /*! @{ */ #define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) #define LPSPI_TCR_FRAMESZ_SHIFT (0U) /*! FRAMESZ - Frame Size */ #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) #define LPSPI_TCR_WIDTH_MASK (0x30000U) #define LPSPI_TCR_WIDTH_SHIFT (16U) /*! WIDTH - Transfer Width * 0b00..1 bit transfer * 0b01..2 bit transfer * 0b10..4 bit transfer * 0b11..Reserved */ #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) #define LPSPI_TCR_TXMSK_MASK (0x40000U) #define LPSPI_TCR_TXMSK_SHIFT (18U) /*! TXMSK - Transmit Data Mask * 0b0..Normal transfer * 0b1..Mask transmit data */ #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) #define LPSPI_TCR_RXMSK_MASK (0x80000U) #define LPSPI_TCR_RXMSK_SHIFT (19U) /*! RXMSK - Receive Data Mask * 0b0..Normal transfer * 0b1..Receive data is masked */ #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) #define LPSPI_TCR_CONTC_MASK (0x100000U) #define LPSPI_TCR_CONTC_SHIFT (20U) /*! CONTC - Continuing Command * 0b0..Command word for start of new transfer * 0b1..Command word for continuing transfer */ #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) #define LPSPI_TCR_CONT_MASK (0x200000U) #define LPSPI_TCR_CONT_SHIFT (21U) /*! CONT - Continuous Transfer * 0b0..Continuous transfer is disabled * 0b1..Continuous transfer is enabled */ #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) #define LPSPI_TCR_BYSW_MASK (0x400000U) #define LPSPI_TCR_BYSW_SHIFT (22U) /*! BYSW - Byte Swap * 0b0..Byte swap is disabled * 0b1..Byte swap is enabled */ #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) #define LPSPI_TCR_LSBF_MASK (0x800000U) #define LPSPI_TCR_LSBF_SHIFT (23U) /*! LSBF - LSB First * 0b0..Data is transferred MSB first * 0b1..Data is transferred LSB first */ #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) #define LPSPI_TCR_PCS_MASK (0x3000000U) #define LPSPI_TCR_PCS_SHIFT (24U) /*! PCS - Peripheral Chip Select * 0b00..Transfer using LPSPI_PCS[0] * 0b01..Transfer using LPSPI_PCS[1] * 0b10..Transfer using LPSPI_PCS[2] * 0b11..Transfer using LPSPI_PCS[3] */ #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) #define LPSPI_TCR_PRESCALE_MASK (0x38000000U) #define LPSPI_TCR_PRESCALE_SHIFT (27U) /*! PRESCALE - Prescaler Value * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 4 * 0b011..Divide by 8 * 0b100..Divide by 16 * 0b101..Divide by 32 * 0b110..Divide by 64 * 0b111..Divide by 128 */ #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) #define LPSPI_TCR_CPHA_MASK (0x40000000U) #define LPSPI_TCR_CPHA_SHIFT (30U) /*! CPHA - Clock Phase * 0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK * 0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK */ #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) #define LPSPI_TCR_CPOL_MASK (0x80000000U) #define LPSPI_TCR_CPOL_SHIFT (31U) /*! CPOL - Clock Polarity * 0b0..The inactive state value of SCK is low * 0b1..The inactive state value of SCK is high */ #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) /*! @} */ /*! @name TDR - Transmit Data Register */ /*! @{ */ #define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_TDR_DATA_SHIFT (0U) /*! DATA - Transmit Data */ #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) /*! @} */ /*! @name RSR - Receive Status Register */ /*! @{ */ #define LPSPI_RSR_SOF_MASK (0x1U) #define LPSPI_RSR_SOF_SHIFT (0U) /*! SOF - Start Of Frame * 0b0..Subsequent data word received after LPSPI_PCS assertion * 0b1..First data word received after LPSPI_PCS assertion */ #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) #define LPSPI_RSR_RXEMPTY_MASK (0x2U) #define LPSPI_RSR_RXEMPTY_SHIFT (1U) /*! RXEMPTY - RX FIFO Empty * 0b0..RX FIFO is not empty * 0b1..RX FIFO is empty */ #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) /*! @} */ /*! @name RDR - Receive Data Register */ /*! @{ */ #define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_RDR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) /*! @} */ /*! * @} */ /* end of group LPSPI_Register_Masks */ /* LPSPI - Peripheral instance base addresses */ /** Peripheral LPSPI0 base address */ #define LPSPI0_BASE (0x41038000u) /** Peripheral LPSPI0 base pointer */ #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) /** Peripheral LPSPI1 base address */ #define LPSPI1_BASE (0x41039000u) /** Peripheral LPSPI1 base pointer */ #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) /** Peripheral LPSPI2 base address */ #define LPSPI2_BASE (0x40290000u) /** Peripheral LPSPI2 base pointer */ #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) /** Peripheral LPSPI3 base address */ #define LPSPI3_BASE (0x402A0000u) /** Peripheral LPSPI3 base pointer */ #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) /** Array initializer of LPSPI peripheral base addresses */ #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE } /** Array initializer of LPSPI peripheral base pointers */ #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3 } /** Interrupt vectors for the LPSPI peripheral type */ #define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn, NotAvail_IRQn, NotAvail_IRQn } /*! * @} */ /* end of group LPSPI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPTMR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer * @{ */ /** LPTMR - Register Layout Typedef */ typedef struct { __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ } LPTMR_Type; /* ---------------------------------------------------------------------------- -- LPTMR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPTMR_Register_Masks LPTMR Register Masks * @{ */ /*! @name CSR - Low Power Timer Control Status Register */ /*! @{ */ #define LPTMR_CSR_TEN_MASK (0x1U) #define LPTMR_CSR_TEN_SHIFT (0U) /*! TEN - Timer Enable * 0b0..LPTMR is disabled and internal logic is reset. * 0b1..LPTMR is enabled. */ #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) #define LPTMR_CSR_TMS_MASK (0x2U) #define LPTMR_CSR_TMS_SHIFT (1U) /*! TMS - Timer Mode Select * 0b0..Time Counter mode. * 0b1..Pulse Counter mode. */ #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) #define LPTMR_CSR_TFC_MASK (0x4U) #define LPTMR_CSR_TFC_SHIFT (2U) /*! TFC - Timer Free-Running Counter * 0b0..CNR is reset whenever TCF is set. * 0b1..CNR is reset on overflow. */ #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) #define LPTMR_CSR_TPP_MASK (0x8U) #define LPTMR_CSR_TPP_SHIFT (3U) /*! TPP - Timer Pin Polarity * 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. * 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. */ #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) #define LPTMR_CSR_TPS_MASK (0x30U) #define LPTMR_CSR_TPS_SHIFT (4U) /*! TPS - Timer Pin Select * 0b00..Pulse counter input 0 is selected. * 0b01..Pulse counter input 1 is selected. * 0b10..Pulse counter input 2 is selected. * 0b11..Pulse counter input 3 is selected. */ #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) #define LPTMR_CSR_TIE_MASK (0x40U) #define LPTMR_CSR_TIE_SHIFT (6U) /*! TIE - Timer Interrupt Enable * 0b0..Timer interrupt disabled. * 0b1..Timer interrupt enabled. */ #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) #define LPTMR_CSR_TCF_MASK (0x80U) #define LPTMR_CSR_TCF_SHIFT (7U) /*! TCF - Timer Compare Flag * 0b0..The value of CNR is not equal to CMR and increments. * 0b1..The value of CNR is equal to CMR and increments. */ #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) #define LPTMR_CSR_TDRE_MASK (0x100U) #define LPTMR_CSR_TDRE_SHIFT (8U) /*! TDRE - Timer DMA Request Enable * 0b0..Timer DMA Request disabled. * 0b1..Timer DMA Request enabled. */ #define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK) /*! @} */ /*! @name PSR - Low Power Timer Prescale Register */ /*! @{ */ #define LPTMR_PSR_PCS_MASK (0x3U) #define LPTMR_PSR_PCS_SHIFT (0U) /*! PCS - Prescaler Clock Select * 0b00..Prescaler/glitch filter clock 0 selected. * 0b01..Prescaler/glitch filter clock 1 selected. * 0b10..Prescaler/glitch filter clock 2 selected. * 0b11..Prescaler/glitch filter clock 3 selected. */ #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) #define LPTMR_PSR_PBYP_MASK (0x4U) #define LPTMR_PSR_PBYP_SHIFT (2U) /*! PBYP - Prescaler Bypass * 0b0..Prescaler/glitch filter is enabled. * 0b1..Prescaler/glitch filter is bypassed. */ #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) #define LPTMR_PSR_PRESCALE_MASK (0x78U) #define LPTMR_PSR_PRESCALE_SHIFT (3U) /*! PRESCALE - Prescale Value * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. */ #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) /*! @} */ /*! @name CMR - Low Power Timer Compare Register */ /*! @{ */ #define LPTMR_CMR_COMPARE_MASK (0xFFFFU) #define LPTMR_CMR_COMPARE_SHIFT (0U) /*! COMPARE - Compare Value */ #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) /*! @} */ /*! @name CNR - Low Power Timer Counter Register */ /*! @{ */ #define LPTMR_CNR_COUNTER_MASK (0xFFFFU) #define LPTMR_CNR_COUNTER_SHIFT (0U) /*! COUNTER - Counter Value */ #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) /*! @} */ /*! * @} */ /* end of group LPTMR_Register_Masks */ /* LPTMR - Peripheral instance base addresses */ /** Peripheral LPTMR0 base address */ #define LPTMR0_BASE (0x4102E000u) /** Peripheral LPTMR0 base pointer */ #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) /** Peripheral LPTMR1 base address */ #define LPTMR1_BASE (0x4102F000u) /** Peripheral LPTMR1 base pointer */ #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) /** Array initializer of LPTMR peripheral base addresses */ #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } /** Array initializer of LPTMR peripheral base pointers */ #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } /** Interrupt vectors for the LPTMR peripheral type */ #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn } /*! * @} */ /* end of group LPTMR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPUART Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer * @{ */ /** LPUART - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */ __IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */ __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */ __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */ __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */ __IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */ __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */ __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */ __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */ __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */ } LPUART_Type; /* ---------------------------------------------------------------------------- -- LPUART Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPUART_Register_Masks LPUART Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define LPUART_VERID_FEATURE_MASK (0xFFFFU) #define LPUART_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Identification Number * 0b0000000000000001..Standard feature set. * 0b0000000000000011..Standard feature set with MODEM/IrDA support. */ #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) #define LPUART_VERID_MINOR_MASK (0xFF0000U) #define LPUART_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) #define LPUART_VERID_MAJOR_MASK (0xFF000000U) #define LPUART_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define LPUART_PARAM_TXFIFO_MASK (0xFFU) #define LPUART_PARAM_TXFIFO_SHIFT (0U) /*! TXFIFO - Transmit FIFO Size */ #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) #define LPUART_PARAM_RXFIFO_MASK (0xFF00U) #define LPUART_PARAM_RXFIFO_SHIFT (8U) /*! RXFIFO - Receive FIFO Size */ #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) /*! @} */ /*! @name GLOBAL - LPUART Global Register */ /*! @{ */ #define LPUART_GLOBAL_RST_MASK (0x2U) #define LPUART_GLOBAL_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Module is not reset. * 0b1..Module is reset. */ #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) /*! @} */ /*! @name PINCFG - LPUART Pin Configuration Register */ /*! @{ */ #define LPUART_PINCFG_TRGSEL_MASK (0x3U) #define LPUART_PINCFG_TRGSEL_SHIFT (0U) /*! TRGSEL - Trigger Select * 0b00..Input trigger is disabled. * 0b01..Input trigger is used instead of RXD pin input. * 0b10..Input trigger is used instead of CTS_B pin input. * 0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. */ #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) /*! @} */ /*! @name BAUD - LPUART Baud Rate Register */ /*! @{ */ #define LPUART_BAUD_SBR_MASK (0x1FFFU) #define LPUART_BAUD_SBR_SHIFT (0U) /*! SBR - Baud Rate Modulo Divisor. */ #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) #define LPUART_BAUD_SBNS_MASK (0x2000U) #define LPUART_BAUD_SBNS_SHIFT (13U) /*! SBNS - Stop Bit Number Select * 0b0..One stop bit. * 0b1..Two stop bits. */ #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) #define LPUART_BAUD_RXEDGIE_MASK (0x4000U) #define LPUART_BAUD_RXEDGIE_SHIFT (14U) /*! RXEDGIE - RX Input Active Edge Interrupt Enable * 0b0..Hardware interrupts from STAT[RXEDGIF] are disabled. * 0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. */ #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) #define LPUART_BAUD_LBKDIE_MASK (0x8000U) #define LPUART_BAUD_LBKDIE_SHIFT (15U) /*! LBKDIE - LIN Break Detect Interrupt Enable * 0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). * 0b1..Hardware interrupt requested when STAT[LBKDIF] flag is 1. */ #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) #define LPUART_BAUD_RESYNCDIS_SHIFT (16U) /*! RESYNCDIS - Resynchronization Disable * 0b0..Resynchronization during received data word is supported * 0b1..Resynchronization during received data word is disabled */ #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) #define LPUART_BAUD_BOTHEDGE_SHIFT (17U) /*! BOTHEDGE - Both Edge Sampling * 0b0..Receiver samples input data using the rising edge of the baud rate clock. * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock. */ #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) #define LPUART_BAUD_MATCFG_MASK (0xC0000U) #define LPUART_BAUD_MATCFG_SHIFT (18U) /*! MATCFG - Match Configuration * 0b00..Address Match Wakeup * 0b01..Idle Match Wakeup * 0b10..Match On and Match Off * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input */ #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) #define LPUART_BAUD_RIDMAE_MASK (0x100000U) #define LPUART_BAUD_RIDMAE_SHIFT (20U) /*! RIDMAE - Receiver Idle DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled. */ #define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) #define LPUART_BAUD_RDMAE_MASK (0x200000U) #define LPUART_BAUD_RDMAE_SHIFT (21U) /*! RDMAE - Receiver Full DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled. */ #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) #define LPUART_BAUD_TDMAE_MASK (0x800000U) #define LPUART_BAUD_TDMAE_SHIFT (23U) /*! TDMAE - Transmitter DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled. */ #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) #define LPUART_BAUD_OSR_MASK (0x1F000000U) #define LPUART_BAUD_OSR_SHIFT (24U) /*! OSR - Oversampling Ratio * 0b00000..Writing 0 to this field will result in an oversampling ratio of 16 * 0b00001..Reserved * 0b00010..Reserved * 0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set. * 0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set. * 0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set. * 0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set. * 0b00111..Oversampling ratio of 8. * 0b01000..Oversampling ratio of 9. * 0b01001..Oversampling ratio of 10. * 0b01010..Oversampling ratio of 11. * 0b01011..Oversampling ratio of 12. * 0b01100..Oversampling ratio of 13. * 0b01101..Oversampling ratio of 14. * 0b01110..Oversampling ratio of 15. * 0b01111..Oversampling ratio of 16. * 0b10000..Oversampling ratio of 17. * 0b10001..Oversampling ratio of 18. * 0b10010..Oversampling ratio of 19. * 0b10011..Oversampling ratio of 20. * 0b10100..Oversampling ratio of 21. * 0b10101..Oversampling ratio of 22. * 0b10110..Oversampling ratio of 23. * 0b10111..Oversampling ratio of 24. * 0b11000..Oversampling ratio of 25. * 0b11001..Oversampling ratio of 26. * 0b11010..Oversampling ratio of 27. * 0b11011..Oversampling ratio of 28. * 0b11100..Oversampling ratio of 29. * 0b11101..Oversampling ratio of 30. * 0b11110..Oversampling ratio of 31. * 0b11111..Oversampling ratio of 32. */ #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) #define LPUART_BAUD_M10_MASK (0x20000000U) #define LPUART_BAUD_M10_SHIFT (29U) /*! M10 - 10-bit Mode select * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters. * 0b1..Receiver and transmitter use 10-bit data characters. */ #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) #define LPUART_BAUD_MAEN2_MASK (0x40000000U) #define LPUART_BAUD_MAEN2_SHIFT (30U) /*! MAEN2 - Match Address Mode Enable 2 * 0b0..Normal operation. * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2]. */ #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) #define LPUART_BAUD_MAEN1_MASK (0x80000000U) #define LPUART_BAUD_MAEN1_SHIFT (31U) /*! MAEN1 - Match Address Mode Enable 1 * 0b0..Normal operation. * 0b1..Enables automatic address matching or data matching mode for MATCH[MA1]. */ #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) /*! @} */ /*! @name STAT - LPUART Status Register */ /*! @{ */ #define LPUART_STAT_MA2F_MASK (0x4000U) #define LPUART_STAT_MA2F_SHIFT (14U) /*! MA2F - Match 2 Flag * 0b0..Received data is not equal to MA2 * 0b1..Received data is equal to MA2 */ #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) #define LPUART_STAT_MA1F_MASK (0x8000U) #define LPUART_STAT_MA1F_SHIFT (15U) /*! MA1F - Match 1 Flag * 0b0..Received data is not equal to MA1 * 0b1..Received data is equal to MA1 */ #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) #define LPUART_STAT_PF_MASK (0x10000U) #define LPUART_STAT_PF_SHIFT (16U) /*! PF - Parity Error Flag * 0b0..No parity error. * 0b1..Parity error. */ #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) #define LPUART_STAT_FE_MASK (0x20000U) #define LPUART_STAT_FE_SHIFT (17U) /*! FE - Framing Error Flag * 0b0..No framing error detected. This does not guarantee the framing is correct. * 0b1..Framing error. */ #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) #define LPUART_STAT_NF_MASK (0x40000U) #define LPUART_STAT_NF_SHIFT (18U) /*! NF - Noise Flag * 0b0..No noise detected. * 0b1..Noise detected in the received character in the DATA register. */ #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) #define LPUART_STAT_OR_MASK (0x80000U) #define LPUART_STAT_OR_SHIFT (19U) /*! OR - Receiver Overrun Flag * 0b0..No overrun. * 0b1..Receive overrun (new LPUART data lost). */ #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) #define LPUART_STAT_IDLE_MASK (0x100000U) #define LPUART_STAT_IDLE_SHIFT (20U) /*! IDLE - Idle Line Flag * 0b0..No idle line detected. * 0b1..Idle line was detected. */ #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) #define LPUART_STAT_RDRF_MASK (0x200000U) #define LPUART_STAT_RDRF_SHIFT (21U) /*! RDRF - Receive Data Register Full Flag * 0b0..Receive data buffer empty. * 0b1..Receive data buffer full. */ #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) #define LPUART_STAT_TC_MASK (0x400000U) #define LPUART_STAT_TC_SHIFT (22U) /*! TC - Transmission Complete Flag * 0b0..Transmitter active (sending data, a preamble, or a break). * 0b1..Transmitter idle (transmission activity complete). */ #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) #define LPUART_STAT_TDRE_MASK (0x800000U) #define LPUART_STAT_TDRE_SHIFT (23U) /*! TDRE - Transmit Data Register Empty Flag * 0b0..Transmit data buffer full. * 0b1..Transmit data buffer empty. */ #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) #define LPUART_STAT_RAF_MASK (0x1000000U) #define LPUART_STAT_RAF_SHIFT (24U) /*! RAF - Receiver Active Flag * 0b0..LPUART receiver idle waiting for a start bit. * 0b1..LPUART receiver active (RXD input not idle). */ #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) #define LPUART_STAT_LBKDE_MASK (0x2000000U) #define LPUART_STAT_LBKDE_SHIFT (25U) /*! LBKDE - LIN Break Detection Enable * 0b0..LIN break detect is disabled, normal break character can be detected. * 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). */ #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) #define LPUART_STAT_BRK13_MASK (0x4000000U) #define LPUART_STAT_BRK13_SHIFT (26U) /*! BRK13 - Break Character Generation Length * 0b0..Break character is transmitted with length of 9 to 13 bit times. * 0b1..Break character is transmitted with length of 12 to 15 bit times. */ #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) #define LPUART_STAT_RWUID_MASK (0x8000000U) #define LPUART_STAT_RWUID_SHIFT (27U) /*! RWUID - Receive Wake Up Idle Detect * 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle * character. During address match wakeup, the IDLE bit does not set when an address does not match. * 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During * address match wakeup, the IDLE bit does set when an address does not match. */ #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) #define LPUART_STAT_RXINV_MASK (0x10000000U) #define LPUART_STAT_RXINV_SHIFT (28U) /*! RXINV - Receive Data Inversion * 0b0..Receive data not inverted. * 0b1..Receive data inverted. */ #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) #define LPUART_STAT_MSBF_MASK (0x20000000U) #define LPUART_STAT_MSBF_SHIFT (29U) /*! MSBF - MSB First * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received * after the start bit is identified as bit0. * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on * the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is * identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. */ #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) #define LPUART_STAT_RXEDGIF_MASK (0x40000000U) #define LPUART_STAT_RXEDGIF_SHIFT (30U) /*! RXEDGIF - RXD Pin Active Edge Interrupt Flag * 0b0..No active edge on the receive pin has occurred. * 0b1..An active edge on the receive pin has occurred. */ #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) #define LPUART_STAT_LBKDIF_MASK (0x80000000U) #define LPUART_STAT_LBKDIF_SHIFT (31U) /*! LBKDIF - LIN Break Detect Interrupt Flag * 0b0..No LIN break character has been detected. * 0b1..LIN break character has been detected. */ #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) /*! @} */ /*! @name CTRL - LPUART Control Register */ /*! @{ */ #define LPUART_CTRL_PT_MASK (0x1U) #define LPUART_CTRL_PT_SHIFT (0U) /*! PT - Parity Type * 0b0..Even parity. * 0b1..Odd parity. */ #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) #define LPUART_CTRL_PE_MASK (0x2U) #define LPUART_CTRL_PE_SHIFT (1U) /*! PE - Parity Enable * 0b0..No hardware parity generation or checking. * 0b1..Parity enabled. */ #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) #define LPUART_CTRL_ILT_MASK (0x4U) #define LPUART_CTRL_ILT_SHIFT (2U) /*! ILT - Idle Line Type Select * 0b0..Idle character bit count starts after start bit. * 0b1..Idle character bit count starts after stop bit. */ #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) #define LPUART_CTRL_WAKE_MASK (0x8U) #define LPUART_CTRL_WAKE_SHIFT (3U) /*! WAKE - Receiver Wakeup Method Select * 0b0..Configures RWU for idle-line wakeup. * 0b1..Configures RWU with address-mark wakeup. */ #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) #define LPUART_CTRL_M_MASK (0x10U) #define LPUART_CTRL_M_SHIFT (4U) /*! M - 9-Bit or 8-Bit Mode Select * 0b0..Receiver and transmitter use 8-bit data characters. * 0b1..Receiver and transmitter use 9-bit data characters. */ #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) #define LPUART_CTRL_RSRC_MASK (0x20U) #define LPUART_CTRL_RSRC_SHIFT (5U) /*! RSRC - Receiver Source Select * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. * 0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. */ #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) #define LPUART_CTRL_DOZEEN_MASK (0x40U) #define LPUART_CTRL_DOZEEN_SHIFT (6U) /*! DOZEEN - Doze Enable * 0b0..LPUART is enabled in Doze mode. * 0b1..LPUART is disabled in Doze mode. */ #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) #define LPUART_CTRL_LOOPS_MASK (0x80U) #define LPUART_CTRL_LOOPS_SHIFT (7U) /*! LOOPS - Loop Mode Select * 0b0..Normal operation - RXD and TXD use separate pins. * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). */ #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) #define LPUART_CTRL_IDLECFG_MASK (0x700U) #define LPUART_CTRL_IDLECFG_SHIFT (8U) /*! IDLECFG - Idle Configuration * 0b000..1 idle character * 0b001..2 idle characters * 0b010..4 idle characters * 0b011..8 idle characters * 0b100..16 idle characters * 0b101..32 idle characters * 0b110..64 idle characters * 0b111..128 idle characters */ #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) #define LPUART_CTRL_M7_MASK (0x800U) #define LPUART_CTRL_M7_SHIFT (11U) /*! M7 - 7-Bit Mode Select * 0b0..Receiver and transmitter use 8-bit to 10-bit data characters. * 0b1..Receiver and transmitter use 7-bit data characters. */ #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) #define LPUART_CTRL_MA2IE_MASK (0x4000U) #define LPUART_CTRL_MA2IE_SHIFT (14U) /*! MA2IE - Match 2 Interrupt Enable * 0b0..MA2F interrupt disabled * 0b1..MA2F interrupt enabled */ #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) #define LPUART_CTRL_MA1IE_MASK (0x8000U) #define LPUART_CTRL_MA1IE_SHIFT (15U) /*! MA1IE - Match 1 Interrupt Enable * 0b0..MA1F interrupt disabled * 0b1..MA1F interrupt enabled */ #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) #define LPUART_CTRL_SBK_MASK (0x10000U) #define LPUART_CTRL_SBK_SHIFT (16U) /*! SBK - Send Break * 0b0..Normal transmitter operation. * 0b1..Queue break character(s) to be sent. */ #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) #define LPUART_CTRL_RWU_MASK (0x20000U) #define LPUART_CTRL_RWU_SHIFT (17U) /*! RWU - Receiver Wakeup Control * 0b0..Normal receiver operation. * 0b1..LPUART receiver in standby waiting for wakeup condition. */ #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) #define LPUART_CTRL_RE_MASK (0x40000U) #define LPUART_CTRL_RE_SHIFT (18U) /*! RE - Receiver Enable * 0b0..Receiver disabled. * 0b1..Receiver enabled. */ #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) #define LPUART_CTRL_TE_MASK (0x80000U) #define LPUART_CTRL_TE_SHIFT (19U) /*! TE - Transmitter Enable * 0b0..Transmitter disabled. * 0b1..Transmitter enabled. */ #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) #define LPUART_CTRL_ILIE_MASK (0x100000U) #define LPUART_CTRL_ILIE_SHIFT (20U) /*! ILIE - Idle Line Interrupt Enable * 0b0..Hardware interrupts from IDLE disabled; use polling. * 0b1..Hardware interrupt requested when IDLE flag is 1. */ #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) #define LPUART_CTRL_RIE_MASK (0x200000U) #define LPUART_CTRL_RIE_SHIFT (21U) /*! RIE - Receiver Interrupt Enable * 0b0..Hardware interrupts from RDRF disabled; use polling. * 0b1..Hardware interrupt requested when RDRF flag is 1. */ #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) #define LPUART_CTRL_TCIE_MASK (0x400000U) #define LPUART_CTRL_TCIE_SHIFT (22U) /*! TCIE - Transmission Complete Interrupt Enable for * 0b0..Hardware interrupts from TC disabled; use polling. * 0b1..Hardware interrupt requested when TC flag is 1. */ #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) #define LPUART_CTRL_TIE_MASK (0x800000U) #define LPUART_CTRL_TIE_SHIFT (23U) /*! TIE - Transmit Interrupt Enable * 0b0..Hardware interrupts from TDRE disabled; use polling. * 0b1..Hardware interrupt requested when TDRE flag is 1. */ #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) #define LPUART_CTRL_PEIE_MASK (0x1000000U) #define LPUART_CTRL_PEIE_SHIFT (24U) /*! PEIE - Parity Error Interrupt Enable * 0b0..PF interrupts disabled; use polling). * 0b1..Hardware interrupt requested when PF is set. */ #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) #define LPUART_CTRL_FEIE_MASK (0x2000000U) #define LPUART_CTRL_FEIE_SHIFT (25U) /*! FEIE - Framing Error Interrupt Enable * 0b0..FE interrupts disabled; use polling. * 0b1..Hardware interrupt requested when FE is set. */ #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) #define LPUART_CTRL_NEIE_MASK (0x4000000U) #define LPUART_CTRL_NEIE_SHIFT (26U) /*! NEIE - Noise Error Interrupt Enable * 0b0..NF interrupts disabled; use polling. * 0b1..Hardware interrupt requested when NF is set. */ #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) #define LPUART_CTRL_ORIE_MASK (0x8000000U) #define LPUART_CTRL_ORIE_SHIFT (27U) /*! ORIE - Overrun Interrupt Enable * 0b0..OR interrupts disabled; use polling. * 0b1..Hardware interrupt requested when OR is set. */ #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) #define LPUART_CTRL_TXINV_MASK (0x10000000U) #define LPUART_CTRL_TXINV_SHIFT (28U) /*! TXINV - Transmit Data Inversion * 0b0..Transmit data not inverted. * 0b1..Transmit data inverted. */ #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) #define LPUART_CTRL_TXDIR_MASK (0x20000000U) #define LPUART_CTRL_TXDIR_SHIFT (29U) /*! TXDIR - TXD Pin Direction in Single-Wire Mode * 0b0..TXD pin is an input in single-wire mode. * 0b1..TXD pin is an output in single-wire mode. */ #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) #define LPUART_CTRL_R9T8_MASK (0x40000000U) #define LPUART_CTRL_R9T8_SHIFT (30U) /*! R9T8 - Receive Bit 9 / Transmit Bit 8 */ #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) #define LPUART_CTRL_R8T9_MASK (0x80000000U) #define LPUART_CTRL_R8T9_SHIFT (31U) /*! R8T9 - Receive Bit 8 / Transmit Bit 9 */ #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) /*! @} */ /*! @name DATA - LPUART Data Register */ /*! @{ */ #define LPUART_DATA_R0T0_MASK (0x1U) #define LPUART_DATA_R0T0_SHIFT (0U) /*! R0T0 - R0T0 */ #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) #define LPUART_DATA_R1T1_MASK (0x2U) #define LPUART_DATA_R1T1_SHIFT (1U) /*! R1T1 - R1T1 */ #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) #define LPUART_DATA_R2T2_MASK (0x4U) #define LPUART_DATA_R2T2_SHIFT (2U) /*! R2T2 - R2T2 */ #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) #define LPUART_DATA_R3T3_MASK (0x8U) #define LPUART_DATA_R3T3_SHIFT (3U) /*! R3T3 - R3T3 */ #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) #define LPUART_DATA_R4T4_MASK (0x10U) #define LPUART_DATA_R4T4_SHIFT (4U) /*! R4T4 - R4T4 */ #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) #define LPUART_DATA_R5T5_MASK (0x20U) #define LPUART_DATA_R5T5_SHIFT (5U) /*! R5T5 - R5T5 */ #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) #define LPUART_DATA_R6T6_MASK (0x40U) #define LPUART_DATA_R6T6_SHIFT (6U) /*! R6T6 - R6T6 */ #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) #define LPUART_DATA_R7T7_MASK (0x80U) #define LPUART_DATA_R7T7_SHIFT (7U) /*! R7T7 - R7T7 */ #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) #define LPUART_DATA_R8T8_MASK (0x100U) #define LPUART_DATA_R8T8_SHIFT (8U) /*! R8T8 - R8T8 */ #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) #define LPUART_DATA_R9T9_MASK (0x200U) #define LPUART_DATA_R9T9_SHIFT (9U) /*! R9T9 - R9T9 */ #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) #define LPUART_DATA_IDLINE_MASK (0x800U) #define LPUART_DATA_IDLINE_SHIFT (11U) /*! IDLINE - Idle Line * 0b0..Receiver was not idle before receiving this character. * 0b1..Receiver was idle before receiving this character. */ #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) #define LPUART_DATA_RXEMPT_MASK (0x1000U) #define LPUART_DATA_RXEMPT_SHIFT (12U) /*! RXEMPT - Receive Buffer Empty * 0b0..Receive buffer contains valid data. * 0b1..Receive buffer is empty, data returned on read is not valid. */ #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) #define LPUART_DATA_FRETSC_MASK (0x2000U) #define LPUART_DATA_FRETSC_SHIFT (13U) /*! FRETSC - Frame Error / Transmit Special Character * 0b0..The dataword was received without a frame error on read, or transmit a normal character on write. * 0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit. */ #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) #define LPUART_DATA_PARITYE_MASK (0x4000U) #define LPUART_DATA_PARITYE_SHIFT (14U) /*! PARITYE - PARITYE * 0b0..The dataword was received without a parity error. * 0b1..The dataword was received with a parity error. */ #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) #define LPUART_DATA_NOISY_MASK (0x8000U) #define LPUART_DATA_NOISY_SHIFT (15U) /*! NOISY - NOISY * 0b0..The dataword was received without noise. * 0b1..The data was received with noise. */ #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) /*! @} */ /*! @name MATCH - LPUART Match Address Register */ /*! @{ */ #define LPUART_MATCH_MA1_MASK (0x3FFU) #define LPUART_MATCH_MA1_SHIFT (0U) /*! MA1 - Match Address 1 */ #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) #define LPUART_MATCH_MA2_MASK (0x3FF0000U) #define LPUART_MATCH_MA2_SHIFT (16U) /*! MA2 - Match Address 2 */ #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) /*! @} */ /*! @name MODIR - LPUART Modem IrDA Register */ /*! @{ */ #define LPUART_MODIR_TXCTSE_MASK (0x1U) #define LPUART_MODIR_TXCTSE_SHIFT (0U) /*! TXCTSE - Transmitter clear-to-send enable * 0b0..CTS has no effect on the transmitter. * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a * character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the * mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent * do not affect its transmission. */ #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) #define LPUART_MODIR_TXRTSE_MASK (0x2U) #define LPUART_MODIR_TXRTSE_SHIFT (1U) /*! TXRTSE - Transmitter request-to-send enable * 0b0..The transmitter has no effect on RTS. * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the * start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and * shift register are completely sent, including the last stop bit. */ #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) #define LPUART_MODIR_TXRTSPOL_MASK (0x4U) #define LPUART_MODIR_TXRTSPOL_SHIFT (2U) /*! TXRTSPOL - Transmitter request-to-send polarity * 0b0..Transmitter RTS is active low. * 0b1..Transmitter RTS is active high. */ #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) #define LPUART_MODIR_RXRTSE_MASK (0x8U) #define LPUART_MODIR_RXRTSE_SHIFT (3U) /*! RXRTSE - Receiver request-to-send enable * 0b0..The receiver has no effect on RTS. * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause * the receiver data register to become full. RTS is asserted if the receiver data register is not full and * has not detected a start bit that would cause the receiver data register to become full. */ #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) #define LPUART_MODIR_TXCTSC_MASK (0x10U) #define LPUART_MODIR_TXCTSC_SHIFT (4U) /*! TXCTSC - Transmit CTS Configuration * 0b0..CTS input is sampled at the start of each character. * 0b1..CTS input is sampled when the transmitter is idle. */ #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) #define LPUART_MODIR_TXCTSSRC_MASK (0x20U) #define LPUART_MODIR_TXCTSSRC_SHIFT (5U) /*! TXCTSSRC - Transmit CTS Source * 0b0..CTS input is the CTS_B pin. * 0b1..CTS input is the inverted Receiver Match result. */ #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) #define LPUART_MODIR_RTSWATER_MASK (0x700U) /* Merged from fields with different position or width, of widths (2, 3), largest definition used */ #define LPUART_MODIR_RTSWATER_SHIFT (8U) /*! RTSWATER - Receive RTS Configuration */ #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) /* Merged from fields with different position or width, of widths (2, 3), largest definition used */ #define LPUART_MODIR_TNP_MASK (0x30000U) #define LPUART_MODIR_TNP_SHIFT (16U) /*! TNP - Transmitter narrow pulse * 0b00..1/OSR. * 0b01..2/OSR. * 0b10..3/OSR. * 0b11..4/OSR. */ #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) #define LPUART_MODIR_IREN_MASK (0x40000U) #define LPUART_MODIR_IREN_SHIFT (18U) /*! IREN - Infrared enable * 0b0..IR disabled. * 0b1..IR enabled. */ #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) /*! @} */ /*! @name FIFO - LPUART FIFO Register */ /*! @{ */ #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) /*! RXFIFOSIZE - Receive FIFO Buffer Depth * 0b000..Receive FIFO/Buffer depth = 1 dataword. * 0b001..Receive FIFO/Buffer depth = 4 datawords. * 0b010..Receive FIFO/Buffer depth = 8 datawords. * 0b011..Receive FIFO/Buffer depth = 16 datawords. * 0b100..Receive FIFO/Buffer depth = 32 datawords. * 0b101..Receive FIFO/Buffer depth = 64 datawords. * 0b110..Receive FIFO/Buffer depth = 128 datawords. * 0b111..Receive FIFO/Buffer depth = 256 datawords. */ #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) #define LPUART_FIFO_RXFE_MASK (0x8U) #define LPUART_FIFO_RXFE_SHIFT (3U) /*! RXFE - Receive FIFO Enable * 0b0..Receive FIFO is not enabled. Buffer is depth 1. * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. */ #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) /*! TXFIFOSIZE - Transmit FIFO Buffer Depth * 0b000..Transmit FIFO/Buffer depth = 1 dataword. * 0b001..Transmit FIFO/Buffer depth = 4 datawords. * 0b010..Transmit FIFO/Buffer depth = 8 datawords. * 0b011..Transmit FIFO/Buffer depth = 16 datawords. * 0b100..Transmit FIFO/Buffer depth = 32 datawords. * 0b101..Transmit FIFO/Buffer depth = 64 datawords. * 0b110..Transmit FIFO/Buffer depth = 128 datawords. * 0b111..Transmit FIFO/Buffer depth = 256 datawords */ #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) #define LPUART_FIFO_TXFE_MASK (0x80U) #define LPUART_FIFO_TXFE_SHIFT (7U) /*! TXFE - Transmit FIFO Enable * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. */ #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) #define LPUART_FIFO_RXUFE_MASK (0x100U) #define LPUART_FIFO_RXUFE_SHIFT (8U) /*! RXUFE - Receive FIFO Underflow Interrupt Enable * 0b0..RXUF flag does not generate an interrupt to the host. * 0b1..RXUF flag generates an interrupt to the host. */ #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) #define LPUART_FIFO_TXOFE_MASK (0x200U) #define LPUART_FIFO_TXOFE_SHIFT (9U) /*! TXOFE - Transmit FIFO Overflow Interrupt Enable * 0b0..TXOF flag does not generate an interrupt to the host. * 0b1..TXOF flag generates an interrupt to the host. */ #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) #define LPUART_FIFO_RXIDEN_MASK (0x1C00U) #define LPUART_FIFO_RXIDEN_SHIFT (10U) /*! RXIDEN - Receiver Idle Empty Enable * 0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle. * 0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. * 0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. * 0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. * 0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. * 0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. * 0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. * 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. */ #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) #define LPUART_FIFO_RXFLUSH_MASK (0x4000U) #define LPUART_FIFO_RXFLUSH_SHIFT (14U) /*! RXFLUSH - Receive FIFO/Buffer Flush * 0b0..No flush operation occurs. * 0b1..All data in the receive FIFO/buffer is cleared out. */ #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) #define LPUART_FIFO_TXFLUSH_MASK (0x8000U) #define LPUART_FIFO_TXFLUSH_SHIFT (15U) /*! TXFLUSH - Transmit FIFO/Buffer Flush * 0b0..No flush operation occurs. * 0b1..All data in the transmit FIFO/Buffer is cleared out. */ #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) #define LPUART_FIFO_RXUF_MASK (0x10000U) #define LPUART_FIFO_RXUF_SHIFT (16U) /*! RXUF - Receiver Buffer Underflow Flag * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared. * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared. */ #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) #define LPUART_FIFO_TXOF_MASK (0x20000U) #define LPUART_FIFO_TXOF_SHIFT (17U) /*! TXOF - Transmitter Buffer Overflow Flag * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared. * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared. */ #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) #define LPUART_FIFO_RXEMPT_MASK (0x400000U) #define LPUART_FIFO_RXEMPT_SHIFT (22U) /*! RXEMPT - Receive Buffer/FIFO Empty * 0b0..Receive buffer is not empty. * 0b1..Receive buffer is empty. */ #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) #define LPUART_FIFO_TXEMPT_MASK (0x800000U) #define LPUART_FIFO_TXEMPT_SHIFT (23U) /*! TXEMPT - Transmit Buffer/FIFO Empty * 0b0..Transmit buffer is not empty. * 0b1..Transmit buffer is empty. */ #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) /*! @} */ /*! @name WATER - LPUART Watermark Register */ /*! @{ */ #define LPUART_WATER_TXWATER_MASK (0x7U) /* Merged from fields with different position or width, of widths (2, 3), largest definition used */ #define LPUART_WATER_TXWATER_SHIFT (0U) /*! TXWATER - Transmit Watermark */ #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) /* Merged from fields with different position or width, of widths (2, 3), largest definition used */ #define LPUART_WATER_TXCOUNT_MASK (0xF00U) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ #define LPUART_WATER_TXCOUNT_SHIFT (8U) /*! TXCOUNT - Transmit Counter */ #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ #define LPUART_WATER_RXWATER_MASK (0x70000U) /* Merged from fields with different position or width, of widths (2, 3), largest definition used */ #define LPUART_WATER_RXWATER_SHIFT (16U) /*! RXWATER - Receive Watermark */ #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) /* Merged from fields with different position or width, of widths (2, 3), largest definition used */ #define LPUART_WATER_RXCOUNT_MASK (0xF000000U) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ #define LPUART_WATER_RXCOUNT_SHIFT (24U) /*! RXCOUNT - Receive Counter */ #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ /*! @} */ /*! * @} */ /* end of group LPUART_Register_Masks */ /* LPUART - Peripheral instance base addresses */ /** Peripheral LPUART0 base address */ #define LPUART0_BASE (0x4103A000u) /** Peripheral LPUART0 base pointer */ #define LPUART0 ((LPUART_Type *)LPUART0_BASE) /** Peripheral LPUART1 base address */ #define LPUART1_BASE (0x4103B000u) /** Peripheral LPUART1 base pointer */ #define LPUART1 ((LPUART_Type *)LPUART1_BASE) /** Peripheral LPUART2 base address */ #define LPUART2_BASE (0x410AB000u) /** Peripheral LPUART2 base pointer */ #define LPUART2 ((LPUART_Type *)LPUART2_BASE) /** Peripheral LPUART3 base address */ #define LPUART3_BASE (0x410AC000u) /** Peripheral LPUART3 base pointer */ #define LPUART3 ((LPUART_Type *)LPUART3_BASE) /** Peripheral LPUART4 base address */ #define LPUART4_BASE (0x402D0000u) /** Peripheral LPUART4 base pointer */ #define LPUART4 ((LPUART_Type *)LPUART4_BASE) /** Peripheral LPUART5 base address */ #define LPUART5_BASE (0x402E0000u) /** Peripheral LPUART5 base pointer */ #define LPUART5 ((LPUART_Type *)LPUART5_BASE) /** Peripheral LPUART6 base address */ #define LPUART6_BASE (0x40A60000u) /** Peripheral LPUART6 base pointer */ #define LPUART6 ((LPUART_Type *)LPUART6_BASE) /** Peripheral LPUART7 base address */ #define LPUART7_BASE (0x40A70000u) /** Peripheral LPUART7 base pointer */ #define LPUART7 ((LPUART_Type *)LPUART7_BASE) /** Array initializer of LPUART peripheral base addresses */ #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE } /** Array initializer of LPUART peripheral base pointers */ #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7 } /** Interrupt vectors for the LPUART peripheral type */ #define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } /*! * @} */ /* end of group LPUART_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LTC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LTC_Peripheral_Access_Layer LTC Peripheral Access Layer * @{ */ /** LTC - Register Layout Typedef */ typedef struct { __IO uint32_t MD; /**< Mode Register, offset: 0x0 */ uint8_t RESERVED_0[4]; __O uint32_t KS; /**< Key Size Register, offset: 0x8 */ uint8_t RESERVED_1[4]; __IO uint32_t DS; /**< Data Size Register, offset: 0x10 */ uint8_t RESERVED_2[4]; __IO uint32_t ICVS; /**< ICV Size Register, offset: 0x18 */ uint8_t RESERVED_3[20]; __O uint32_t COM; /**< Command Register, offset: 0x30 */ __IO uint32_t CTL; /**< Control Register, offset: 0x34 */ uint8_t RESERVED_4[8]; __O uint32_t CW; /**< Clear Written Register, offset: 0x40 */ uint8_t RESERVED_5[4]; __IO uint32_t STA; /**< Status Register, offset: 0x48 */ __I uint32_t ESTA; /**< Error Status Register, offset: 0x4C */ uint8_t RESERVED_6[8]; __IO uint32_t AADSZ; /**< AAD Size Register, offset: 0x58 */ uint8_t RESERVED_7[164]; __IO uint32_t CTX[14]; /**< Context Register, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_8[200]; __IO uint32_t KEY[4]; /**< Key Registers, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_9[736]; __I uint32_t VID1; /**< Version ID Register, offset: 0x4F0 */ __I uint32_t VID2; /**< Version ID 2 Register, offset: 0x4F4 */ __I uint32_t CHAVID; /**< CHA Version ID Register, offset: 0x4F8 */ uint8_t RESERVED_10[708]; __I uint32_t FIFOSTA; /**< FIFO Status Register, offset: 0x7C0 */ uint8_t RESERVED_11[28]; __O uint32_t IFIFO; /**< Input Data FIFO, offset: 0x7E0 */ uint8_t RESERVED_12[12]; __I uint32_t OFIFO; /**< Output Data FIFO, offset: 0x7F0 */ } LTC_Type; /* ---------------------------------------------------------------------------- -- LTC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LTC_Register_Masks LTC Register Masks * @{ */ /*! @name MD - Mode Register */ /*! @{ */ #define LTC_MD_ENC_MASK (0x1U) #define LTC_MD_ENC_SHIFT (0U) /*! ENC - Encrypt/Decrypt. * 0b0..Decrypt. * 0b1..Encrypt. */ #define LTC_MD_ENC(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ENC_SHIFT)) & LTC_MD_ENC_MASK) #define LTC_MD_ICV_TEST_MASK (0x2U) #define LTC_MD_ICV_TEST_SHIFT (1U) /*! ICV_TEST - ICV Checking / Test AES fault detection. */ #define LTC_MD_ICV_TEST(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK) #define LTC_MD_AS_MASK (0xCU) #define LTC_MD_AS_SHIFT (2U) /*! AS - Algorithm State * 0b00..Update * 0b01..Initialize * 0b10..Finalize * 0b11..Initialize/Finalize */ #define LTC_MD_AS(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_AS_SHIFT)) & LTC_MD_AS_MASK) #define LTC_MD_AAI_MASK (0x1FF0U) #define LTC_MD_AAI_SHIFT (4U) /*! AAI - Additional Algorithm information */ #define LTC_MD_AAI(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_AAI_SHIFT)) & LTC_MD_AAI_MASK) #define LTC_MD_ALG_MASK (0xFF0000U) #define LTC_MD_ALG_SHIFT (16U) /*! ALG - Algorithm * 0b00010000..AES */ #define LTC_MD_ALG(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ALG_SHIFT)) & LTC_MD_ALG_MASK) /*! @} */ /*! @name KS - Key Size Register */ /*! @{ */ #define LTC_KS_KS_MASK (0x1FU) #define LTC_KS_KS_SHIFT (0U) /*! KS - Key Size */ #define LTC_KS_KS(x) (((uint32_t)(((uint32_t)(x)) << LTC_KS_KS_SHIFT)) & LTC_KS_KS_MASK) /*! @} */ /*! @name DS - Data Size Register */ /*! @{ */ #define LTC_DS_DS_MASK (0xFFFU) #define LTC_DS_DS_SHIFT (0U) /*! DS - Data Size */ #define LTC_DS_DS(x) (((uint32_t)(((uint32_t)(x)) << LTC_DS_DS_SHIFT)) & LTC_DS_DS_MASK) /*! @} */ /*! @name ICVS - ICV Size Register */ /*! @{ */ #define LTC_ICVS_ICVS_MASK (0x1FU) #define LTC_ICVS_ICVS_SHIFT (0U) /*! ICVS - ICV Size, in Bytes */ #define LTC_ICVS_ICVS(x) (((uint32_t)(((uint32_t)(x)) << LTC_ICVS_ICVS_SHIFT)) & LTC_ICVS_ICVS_MASK) /*! @} */ /*! @name COM - Command Register */ /*! @{ */ #define LTC_COM_ALL_MASK (0x1U) #define LTC_COM_ALL_SHIFT (0U) /*! ALL - Reset All Internal Logic * 0b0..Do Not Reset * 0b1..Reset all CHAs in use by this CCB. */ #define LTC_COM_ALL(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_ALL_SHIFT)) & LTC_COM_ALL_MASK) #define LTC_COM_AES_MASK (0x2U) #define LTC_COM_AES_SHIFT (1U) /*! AES - Reset AESA * 0b0..Do Not Reset * 0b1..Reset AES Accelerator */ #define LTC_COM_AES(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_AES_SHIFT)) & LTC_COM_AES_MASK) /*! @} */ /*! @name CTL - Control Register */ /*! @{ */ #define LTC_CTL_IM_MASK (0x1U) #define LTC_CTL_IM_SHIFT (0U) /*! IM - Interrupt Mask * 0b0..Interrupt not masked. * 0b1..Interrupt masked */ #define LTC_CTL_IM(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IM_SHIFT)) & LTC_CTL_IM_MASK) #define LTC_CTL_IFE_MASK (0x100U) #define LTC_CTL_IFE_SHIFT (8U) /*! IFE - Input FIFO DMA Enable * 0b0..DMA Request and Done signals disabled for the Input FIFO. * 0b1..DMA Request and Done signals enabled for the Input FIFO. */ #define LTC_CTL_IFE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFE_SHIFT)) & LTC_CTL_IFE_MASK) #define LTC_CTL_IFR_MASK (0x200U) #define LTC_CTL_IFR_SHIFT (9U) /*! IFR - Input FIFO DMA Request Size * 0b0..DMA request size is 1 entry. * 0b1..DMA request size is 4 entries. */ #define LTC_CTL_IFR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK) #define LTC_CTL_OFE_MASK (0x1000U) #define LTC_CTL_OFE_SHIFT (12U) /*! OFE - Output FIFO DMA Enable * 0b0..DMA Request and Done signals disabled for the Output FIFO. * 0b1..DMA Request and Done signals enabled for the Output FIFO. */ #define LTC_CTL_OFE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFE_SHIFT)) & LTC_CTL_OFE_MASK) #define LTC_CTL_OFR_MASK (0x2000U) #define LTC_CTL_OFR_SHIFT (13U) /*! OFR - Output FIFO DMA Request Size * 0b0..DMA request size is 1 entry. * 0b1..DMA request size is 4 entries. */ #define LTC_CTL_OFR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFR_SHIFT)) & LTC_CTL_OFR_MASK) #define LTC_CTL_IFS_MASK (0x10000U) #define LTC_CTL_IFS_SHIFT (16U) /*! IFS - Input FIFO Byte Swap * 0b0..Do Not Byte Swap Data. * 0b1..Byte Swap Data. */ #define LTC_CTL_IFS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFS_SHIFT)) & LTC_CTL_IFS_MASK) #define LTC_CTL_OFS_MASK (0x20000U) #define LTC_CTL_OFS_SHIFT (17U) /*! OFS - Output FIFO Byte Swap * 0b0..Do Not Byte Swap Data. * 0b1..Byte Swap Data. */ #define LTC_CTL_OFS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFS_SHIFT)) & LTC_CTL_OFS_MASK) #define LTC_CTL_KIS_MASK (0x100000U) #define LTC_CTL_KIS_SHIFT (20U) /*! KIS - Key Register Input Byte Swap * 0b0..Do Not Byte Swap Data. * 0b1..Byte Swap Data. */ #define LTC_CTL_KIS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KIS_SHIFT)) & LTC_CTL_KIS_MASK) #define LTC_CTL_KOS_MASK (0x200000U) #define LTC_CTL_KOS_SHIFT (21U) /*! KOS - Key Register Output Byte Swap * 0b0..Do Not Byte Swap Data. * 0b1..Byte Swap Data. */ #define LTC_CTL_KOS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KOS_SHIFT)) & LTC_CTL_KOS_MASK) #define LTC_CTL_CIS_MASK (0x400000U) #define LTC_CTL_CIS_SHIFT (22U) /*! CIS - Context Register Input Byte Swap * 0b0..Do Not Byte Swap Data. * 0b1..Byte Swap Data. */ #define LTC_CTL_CIS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_CIS_SHIFT)) & LTC_CTL_CIS_MASK) #define LTC_CTL_COS_MASK (0x800000U) #define LTC_CTL_COS_SHIFT (23U) /*! COS - Context Register Output Byte Swap * 0b0..Do Not Byte Swap Data. * 0b1..Byte Swap Data. */ #define LTC_CTL_COS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_COS_SHIFT)) & LTC_CTL_COS_MASK) #define LTC_CTL_KDF_MASK (0x40000000U) #define LTC_CTL_KDF_SHIFT (30U) /*! KDF - Key Derivation Function * 0b0..Key Derivation Function Disabled. * 0b1..Key Derivation Function Enabled. */ #define LTC_CTL_KDF(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KDF_SHIFT)) & LTC_CTL_KDF_MASK) #define LTC_CTL_KAL_MASK (0x80000000U) #define LTC_CTL_KAL_SHIFT (31U) /*! KAL - Key Register Access Lock * 0b0..Key Register is readable. * 0b1..Key Register is not readable. */ #define LTC_CTL_KAL(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KAL_SHIFT)) & LTC_CTL_KAL_MASK) /*! @} */ /*! @name CW - Clear Written Register */ /*! @{ */ #define LTC_CW_CM_MASK (0x1U) #define LTC_CW_CM_SHIFT (0U) /*! CM - Clear the Mode Register */ #define LTC_CW_CM(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CM_SHIFT)) & LTC_CW_CM_MASK) #define LTC_CW_CDS_MASK (0x4U) #define LTC_CW_CDS_SHIFT (2U) /*! CDS - Clear the Data Size Register */ #define LTC_CW_CDS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CDS_SHIFT)) & LTC_CW_CDS_MASK) #define LTC_CW_CICV_MASK (0x8U) #define LTC_CW_CICV_SHIFT (3U) /*! CICV - Clear the ICV Size Register */ #define LTC_CW_CICV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CICV_SHIFT)) & LTC_CW_CICV_MASK) #define LTC_CW_CCR_MASK (0x20U) #define LTC_CW_CCR_SHIFT (5U) /*! CCR - Clear the Context Register */ #define LTC_CW_CCR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CCR_SHIFT)) & LTC_CW_CCR_MASK) #define LTC_CW_CKR_MASK (0x40U) #define LTC_CW_CKR_SHIFT (6U) /*! CKR - Clear the Key Register */ #define LTC_CW_CKR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CKR_SHIFT)) & LTC_CW_CKR_MASK) #define LTC_CW_COF_MASK (0x40000000U) #define LTC_CW_COF_SHIFT (30U) /*! COF - Clear Output FIFO */ #define LTC_CW_COF(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_COF_SHIFT)) & LTC_CW_COF_MASK) #define LTC_CW_CIF_MASK (0x80000000U) #define LTC_CW_CIF_SHIFT (31U) /*! CIF - Clear Input FIFO */ #define LTC_CW_CIF(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CIF_SHIFT)) & LTC_CW_CIF_MASK) /*! @} */ /*! @name STA - Status Register */ /*! @{ */ #define LTC_STA_AB_MASK (0x2U) #define LTC_STA_AB_SHIFT (1U) /*! AB - AESA Busy * 0b0..AESA Idle * 0b1..AESA Busy. */ #define LTC_STA_AB(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_AB_SHIFT)) & LTC_STA_AB_MASK) #define LTC_STA_DI_MASK (0x10000U) #define LTC_STA_DI_SHIFT (16U) /*! DI - Done Interrupt */ #define LTC_STA_DI(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_DI_SHIFT)) & LTC_STA_DI_MASK) #define LTC_STA_EI_MASK (0x100000U) #define LTC_STA_EI_SHIFT (20U) /*! EI - Error Interrupt * 0b0..Not Error. * 0b1..Error Interrupt. */ #define LTC_STA_EI(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_EI_SHIFT)) & LTC_STA_EI_MASK) /*! @} */ /*! @name ESTA - Error Status Register */ /*! @{ */ #define LTC_ESTA_ERRID1_MASK (0xFU) #define LTC_ESTA_ERRID1_SHIFT (0U) /*! ERRID1 - Error ID 1 * 0b0001..Mode Error * 0b0010..Data Size Error * 0b0011..Key Size Error * 0b0110..Data Arrived out of Sequence Error * 0b1010..ICV Check Failed * 0b1011..Internal Hardware Failure * 0b1100..CCM AAD Size Error (either 1. AAD flag in B0 =1 and no AAD type provided, 2. AAD flag in B0 = 0 and * AAD povided, or 3. AAD flag in B0 =1 and not enough AAD provided - expecting more based on AAD size.) * 0b1111..Invalid Crypto Engine Selected */ #define LTC_ESTA_ERRID1(x) (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_ERRID1_SHIFT)) & LTC_ESTA_ERRID1_MASK) #define LTC_ESTA_CL1_MASK (0xF00U) #define LTC_ESTA_CL1_SHIFT (8U) /*! CL1 - algorithms * 0b0000..General Error * 0b0001..AES */ #define LTC_ESTA_CL1(x) (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_CL1_SHIFT)) & LTC_ESTA_CL1_MASK) /*! @} */ /*! @name AADSZ - AAD Size Register */ /*! @{ */ #define LTC_AADSZ_AADSZ_MASK (0xFU) #define LTC_AADSZ_AADSZ_SHIFT (0U) /*! AADSZ - AAD size in Bytes, mod 16 */ #define LTC_AADSZ_AADSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AADSZ_SHIFT)) & LTC_AADSZ_AADSZ_MASK) #define LTC_AADSZ_AL_MASK (0x80000000U) #define LTC_AADSZ_AL_SHIFT (31U) /*! AL - AAD Last */ #define LTC_AADSZ_AL(x) (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AL_SHIFT)) & LTC_AADSZ_AL_MASK) /*! @} */ /*! @name CTX - Context Register */ /*! @{ */ #define LTC_CTX_CTX_MASK (0xFFFFFFFFU) #define LTC_CTX_CTX_SHIFT (0U) /*! CTX - CTX */ #define LTC_CTX_CTX(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTX_CTX_SHIFT)) & LTC_CTX_CTX_MASK) /*! @} */ /* The count of LTC_CTX */ #define LTC_CTX_COUNT (14U) /*! @name KEY - Key Registers */ /*! @{ */ #define LTC_KEY_KEY_MASK (0xFFFFFFFFU) #define LTC_KEY_KEY_SHIFT (0U) /*! KEY - KEY */ #define LTC_KEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << LTC_KEY_KEY_SHIFT)) & LTC_KEY_KEY_MASK) /*! @} */ /* The count of LTC_KEY */ #define LTC_KEY_COUNT (4U) /*! @name VID1 - Version ID Register */ /*! @{ */ #define LTC_VID1_MIN_REV_MASK (0xFFU) #define LTC_VID1_MIN_REV_SHIFT (0U) /*! MIN_REV - Minor revision number. */ #define LTC_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MIN_REV_SHIFT)) & LTC_VID1_MIN_REV_MASK) #define LTC_VID1_MAJ_REV_MASK (0xFF00U) #define LTC_VID1_MAJ_REV_SHIFT (8U) /*! MAJ_REV - Major revision number. */ #define LTC_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MAJ_REV_SHIFT)) & LTC_VID1_MAJ_REV_MASK) #define LTC_VID1_IP_ID_MASK (0xFFFF0000U) #define LTC_VID1_IP_ID_SHIFT (16U) #define LTC_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK) /*! @} */ /*! @name VID2 - Version ID 2 Register */ /*! @{ */ #define LTC_VID2_ECO_REV_MASK (0xFFU) #define LTC_VID2_ECO_REV_SHIFT (0U) /*! ECO_REV - ECO revision number. */ #define LTC_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID2_ECO_REV_SHIFT)) & LTC_VID2_ECO_REV_MASK) #define LTC_VID2_ARCH_ERA_MASK (0xFF00U) #define LTC_VID2_ARCH_ERA_SHIFT (8U) /*! ARCH_ERA - Architectural ERA. */ #define LTC_VID2_ARCH_ERA(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID2_ARCH_ERA_SHIFT)) & LTC_VID2_ARCH_ERA_MASK) /*! @} */ /*! @name CHAVID - CHA Version ID Register */ /*! @{ */ #define LTC_CHAVID_AESREV_MASK (0xFU) #define LTC_CHAVID_AESREV_SHIFT (0U) /*! AESREV - AES Revision Number */ #define LTC_CHAVID_AESREV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESREV_SHIFT)) & LTC_CHAVID_AESREV_MASK) #define LTC_CHAVID_AESVID_MASK (0xF0U) #define LTC_CHAVID_AESVID_SHIFT (4U) /*! AESVID - AES Version ID */ #define LTC_CHAVID_AESVID(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK) /*! @} */ /*! @name FIFOSTA - FIFO Status Register */ /*! @{ */ #define LTC_FIFOSTA_IFL_MASK (0x7FU) #define LTC_FIFOSTA_IFL_SHIFT (0U) /*! IFL - Input FIFO Level */ #define LTC_FIFOSTA_IFL(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFL_SHIFT)) & LTC_FIFOSTA_IFL_MASK) #define LTC_FIFOSTA_IFF_MASK (0x8000U) #define LTC_FIFOSTA_IFF_SHIFT (15U) /*! IFF - Input FIFO Full */ #define LTC_FIFOSTA_IFF(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFF_SHIFT)) & LTC_FIFOSTA_IFF_MASK) #define LTC_FIFOSTA_OFL_MASK (0x7F0000U) #define LTC_FIFOSTA_OFL_SHIFT (16U) /*! OFL - Output FIFO Level */ #define LTC_FIFOSTA_OFL(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFL_SHIFT)) & LTC_FIFOSTA_OFL_MASK) #define LTC_FIFOSTA_OFF_MASK (0x80000000U) #define LTC_FIFOSTA_OFF_SHIFT (31U) /*! OFF - Output FIFO Full */ #define LTC_FIFOSTA_OFF(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFF_SHIFT)) & LTC_FIFOSTA_OFF_MASK) /*! @} */ /*! @name IFIFO - Input Data FIFO */ /*! @{ */ #define LTC_IFIFO_IFIFO_MASK (0xFFFFFFFFU) #define LTC_IFIFO_IFIFO_SHIFT (0U) /*! IFIFO - IFIFO */ #define LTC_IFIFO_IFIFO(x) (((uint32_t)(((uint32_t)(x)) << LTC_IFIFO_IFIFO_SHIFT)) & LTC_IFIFO_IFIFO_MASK) /*! @} */ /*! @name OFIFO - Output Data FIFO */ /*! @{ */ #define LTC_OFIFO_OFIFO_MASK (0xFFFFFFFFU) #define LTC_OFIFO_OFIFO_SHIFT (0U) /*! OFIFO - Output FIFO */ #define LTC_OFIFO_OFIFO(x) (((uint32_t)(((uint32_t)(x)) << LTC_OFIFO_OFIFO_SHIFT)) & LTC_OFIFO_OFIFO_MASK) /*! @} */ /*! * @} */ /* end of group LTC_Register_Masks */ /* LTC - Peripheral instance base addresses */ /** Peripheral LTC0 base address */ #define LTC0_BASE (0x4102A000u) /** Peripheral LTC0 base pointer */ #define LTC0 ((LTC_Type *)LTC0_BASE) /** Array initializer of LTC peripheral base addresses */ #define LTC_BASE_ADDRS { LTC0_BASE } /** Array initializer of LTC peripheral base pointers */ #define LTC_BASE_PTRS { LTC0 } /** Interrupt vectors for the LTC peripheral type */ #define LTC_IRQS { LTC_IRQn } /*! * @} */ /* end of group LTC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MCM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer * @{ */ /** MCM - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[8]; __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ __IO uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */ uint8_t RESERVED_1[16]; __I uint32_t FADR; /**< Fault address register, offset: 0x20 */ __I uint32_t FATR; /**< Fault attributes register, offset: 0x24 */ __I uint32_t FDR; /**< Fault data register, offset: 0x28 */ } MCM_Type; /* ---------------------------------------------------------------------------- -- MCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MCM_Register_Masks MCM Register Masks * @{ */ /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ /*! @{ */ #define MCM_PLASC_ASC_MASK (0xFFU) #define MCM_PLASC_ASC_SHIFT (0U) /*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the * crossbar switch's slave input port. * 0b00000000..A bus slave connection to AXBS input port n is absent * 0b00000001..A bus slave connection to AXBS input port n is present */ #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) /*! @} */ /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ /*! @{ */ #define MCM_PLAMC_AMC_MASK (0xFFU) #define MCM_PLAMC_AMC_SHIFT (0U) /*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. * 0b00000000..A bus master connection to AXBS input port n is absent * 0b00000001..A bus master connection to AXBS input port n is present */ #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) /*! @} */ /*! @name PLACR - Crossbar Switch (AXBS) Control Register */ /*! @{ */ #define MCM_PLACR_ARB_MASK (0x200U) #define MCM_PLACR_ARB_SHIFT (9U) /*! ARB - Arbitration select * 0b0..Fixed-priority arbitration for the crossbar masters * 0b1..Round-robin arbitration for the crossbar masters */ #define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK) #define MCM_PLACR_TCRAMU_Priority_MASK (0x3000000U) #define MCM_PLACR_TCRAMU_Priority_SHIFT (24U) /*! TCRAMU_Priority - TCRAMU_Priority */ #define MCM_PLACR_TCRAMU_Priority(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_TCRAMU_Priority_SHIFT)) & MCM_PLACR_TCRAMU_Priority_MASK) #define MCM_PLACR_TCRAMU_Write_Protect_MASK (0x4000000U) #define MCM_PLACR_TCRAMU_Write_Protect_SHIFT (26U) /*! TCRAMU_Write_Protect - TCRAMU_Write_Protect */ #define MCM_PLACR_TCRAMU_Write_Protect(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_TCRAMU_Write_Protect_SHIFT)) & MCM_PLACR_TCRAMU_Write_Protect_MASK) #define MCM_PLACR_TCRAML_Priority_MASK (0x30000000U) #define MCM_PLACR_TCRAML_Priority_SHIFT (28U) /*! TCRAML_Priority - TCRAML_Priority */ #define MCM_PLACR_TCRAML_Priority(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_TCRAML_Priority_SHIFT)) & MCM_PLACR_TCRAML_Priority_MASK) #define MCM_PLACR_TCRAML_Write_Protect_MASK (0x40000000U) #define MCM_PLACR_TCRAML_Write_Protect_SHIFT (30U) /*! TCRAML_Write_Protect - TCRAML_Write_Protect */ #define MCM_PLACR_TCRAML_Write_Protect(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_TCRAML_Write_Protect_SHIFT)) & MCM_PLACR_TCRAML_Write_Protect_MASK) /*! @} */ /*! @name FADR - Fault address register */ /*! @{ */ #define MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU) #define MCM_FADR_ADDRESS_SHIFT (0U) /*! ADDRESS - Fault address */ #define MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK) /*! @} */ /*! @name FATR - Fault attributes register */ /*! @{ */ #define MCM_FATR_BEDA_MASK (0x1U) #define MCM_FATR_BEDA_SHIFT (0U) /*! BEDA - Bus error access type * 0b0..Instruction * 0b1..Data */ #define MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK) #define MCM_FATR_BEMD_MASK (0x2U) #define MCM_FATR_BEMD_SHIFT (1U) /*! BEMD - Bus error privilege level * 0b0..User mode * 0b1..Supervisor/privileged mode */ #define MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK) #define MCM_FATR_BESZ_MASK (0x30U) #define MCM_FATR_BESZ_SHIFT (4U) /*! BESZ - Bus error size * 0b00..8-bit access * 0b01..16-bit access * 0b10..32-bit access * 0b11..Reserved */ #define MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK) #define MCM_FATR_BEWT_MASK (0x80U) #define MCM_FATR_BEWT_SHIFT (7U) /*! BEWT - Bus error write * 0b0..Read access * 0b1..Write access */ #define MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK) #define MCM_FATR_BEMN_MASK (0xF00U) #define MCM_FATR_BEMN_SHIFT (8U) /*! BEMN - Bus error master number */ #define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK) #define MCM_FATR_BEOVR_MASK (0x80000000U) #define MCM_FATR_BEOVR_SHIFT (31U) /*! BEOVR - Bus error overrun * 0b0..No bus error overrun * 0b1..Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error. */ #define MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK) /*! @} */ /*! @name FDR - Fault data register */ /*! @{ */ #define MCM_FDR_DATA_MASK (0xFFFFFFFFU) #define MCM_FDR_DATA_SHIFT (0U) /*! DATA - Fault data */ #define MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK) /*! @} */ /*! * @} */ /* end of group MCM_Register_Masks */ /* MCM - Peripheral instance base addresses */ /** Peripheral MCM base address */ #define MCM_BASE (0xE0080000u) /** Peripheral MCM base pointer */ #define MCM ((MCM_Type *)MCM_BASE) /** Array initializer of MCM peripheral base addresses */ #define MCM_BASE_ADDRS { MCM_BASE } /** Array initializer of MCM peripheral base pointers */ #define MCM_BASE_PTRS { MCM } /** Interrupt vectors for the MCM peripheral type */ #define MCM_IRQS { MCM0_IRQn } /*! * @} */ /* end of group MCM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MIPI_DSI_HOST Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_DSI_HOST_Peripheral_Access_Layer MIPI_DSI_HOST Peripheral Access Layer * @{ */ /** MIPI_DSI_HOST - Register Layout Typedef */ typedef struct { __IO uint32_t DSI_HOST_CFG_NUM_LANES; /**< , offset: 0x0 */ __IO uint32_t DSI_HOST_CFG_NONCONTINUOUS_CLK; /**< , offset: 0x4 */ __IO uint32_t DSI_HOST_CFG_T_PRE; /**< , offset: 0x8 */ __IO uint32_t DSI_HOST_CFG_T_POST; /**< , offset: 0xC */ __IO uint32_t DSI_HOST_CFG_TX_GAP; /**< , offset: 0x10 */ __IO uint32_t DSI_HOST_CFG_AUTOINSERT_EOTP; /**< , offset: 0x14 */ __IO uint32_t DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP; /**< , offset: 0x18 */ __IO uint32_t DSI_HOST_CFG_HTX_TO_COUNT; /**< , offset: 0x1C */ __IO uint32_t DSI_HOST_CFG_LRX_H_TO_COUNT; /**< , offset: 0x20 */ __IO uint32_t DSI_HOST_CFG_BTA_H_TO_COUNT; /**< , offset: 0x24 */ uint8_t RESERVED_0[4]; __I uint32_t DSI_HOST_CFG_STATUS_OUT; /**< , offset: 0x2C */ __I uint32_t DSI_HOST_RX_ERROR_STATUS; /**< , offset: 0x30 */ } MIPI_DSI_HOST_Type; /* ---------------------------------------------------------------------------- -- MIPI_DSI_HOST Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_DSI_HOST_Register_Masks MIPI_DSI_HOST Register Masks * @{ */ /*! @name DSI_HOST_CFG_NUM_LANES - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK (0x3U) #define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT (0U) /*! dsi_host_cfg_num_lanes - Sets the number of active lanes that are to be used for transmitting * data. 2'b00 - 1 Lane 2'b01 - 2 Lanes 2'b10 - Reserved 2'b11 - Reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK) /*! @} */ /*! @name DSI_HOST_CFG_NONCONTINUOUS_CLK - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK (0x1U) #define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT (0U) /*! dsi_host_cfg_noncontinuous_clk - Sets the Host Controller into non-continuous MIPI clock mode. * When in non-continuous clock mode, the high speed clock will transistion into low power mode * between transmissions. 1'b0 - Continuous high speed clock 1'b1 - Non-Continuous high speed clock */ #define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK) /*! @} */ /*! @name DSI_HOST_CFG_T_PRE - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK (0x7FU) #define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT (0U) /*! dsi_host_cfg_t_pre - Sets the number of byte clock periods ('clk_byte' input) that the * controller will wait after enabling the clock lane for HS operation before enabling the data lanes for * HS operation. This setting represents the TCLK-PRE parameter. The minimum value for this port * is 1. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK) /*! @} */ /*! @name DSI_HOST_CFG_T_POST - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK (0x7FU) #define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT (0U) /*! dsi_host_cfg_t_post - Sets the number of byte clock periods ('clk_byte' input) to wait before * putting the clock lane into LP mode after the data lanes have been detected to be in Stop State. * This setting represents the DPHY timing parameters TLPX (TxClkEsc) + TCLK-PREPARE + TCLK-ZERO * + TCLK-PRE requirement for the clock lane before the data lane is allowed to change from LP11 * to start a high speed transmission. The minimum value for this port is 1. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK) /*! @} */ /*! @name DSI_HOST_CFG_TX_GAP - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_MASK (0x7FU) #define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_SHIFT (0U) /*! dsi_host_cfg_tx_gap - Sets the number of byte clock periods ('clk_byte' input) that the * controller will wait after the clock lane has been put into LP mode before enabling the clock lane for * HS mode again. This setting represents the THS-EXIT parameter. The minimum value for this * port is 1. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_MASK) /*! @} */ /*! @name DSI_HOST_CFG_AUTOINSERT_EOTP - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK (0x1U) #define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT (0U) /*! dsi_host_cfg_autoinsert_eotp - Enables the Host Controller to automatically insert an EoTp short * packet when switching from HS to LP mode. 1'b0 - EoTp is not automatically inserted 1'b1 - * EoTp is automatically inserted */ #define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK) /*! @} */ /*! @name DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK (0xFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT (0U) /*! dsi_host_cfg_extra_cmds_after_eotp - Configures the DSI Host Controller to send extra End Of * Transmission Packets after the end of a packet. The value is the number of extra EOTP packets * sent. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK) /*! @} */ /*! @name DSI_HOST_CFG_HTX_TO_COUNT - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK (0xFFFFFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT (0U) /*! dsi_host_cfg_htx_to_count - Sets the value of the DSI Host High Speed TX timeout count in * clk_byte clock periods that once reached will initiate a timeout error and follow the recovery * procedure documented in the DSI specification. This timeout parameter should be configured to * represent the time taken to transmit the biggest HS data payload. If this timeout is reached the * DSI byte count is cleared and the HS transmission is aborted. This timer can be also disabled, * when set to 0. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK) /*! @} */ /*! @name DSI_HOST_CFG_LRX_H_TO_COUNT - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK (0xFFFFFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT (0U) /*! dsi_host_cfg_lrx_h_to_count - Sets the value of the DSI Host low power RX timeout count in * clk_byte clock periods that once reached will initiate a timeout error and follow the recovery * procedure documented in the DSI specification. This timeout parameter should be configured to * represent the time taken to receive the biggest LP (Escape mode) data payload. If this timeout is * reached, the DSI byte count is cleared and the LP reception is aborted. This timer can be also * disabled, when set to 0 */ #define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK) /*! @} */ /*! @name DSI_HOST_CFG_BTA_H_TO_COUNT - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK (0xFFFFFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT (0U) /*! dsi_host_cfg_bta_h_to_count - Sets the value of the DSI Host Bus Turn Around (BTA) timeout in * clk_byte clock periods that once reached will initiate a timeout error. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK) /*! @} */ /*! @name DSI_HOST_CFG_STATUS_OUT - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR_MASK (0x1U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR_SHIFT (0U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR_MASK (0x2U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR_SHIFT (1U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR_MASK (0x4U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR_SHIFT (2U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR_MASK (0x8U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR_SHIFT (3U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR_MASK (0x10U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR_SHIFT (4U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR_MASK (0x20U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR_SHIFT (5U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR_MASK (0x40U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR_SHIFT (6U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT_MASK (0x80U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT_SHIFT (7U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT_MASK (0x100U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT_SHIFT (8U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT_MASK (0x200U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT_SHIFT (9U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR_MASK (0x400U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR_SHIFT (10U) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR_MASK) /*! @} */ /*! @name DSI_HOST_RX_ERROR_STATUS - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK (0x7FFU) #define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT (0U) /*! dsi_host_rx_error_status - Status Register for Host receive error detection, ECC errors, CRC * errors and for timeout indicators [0] ECC single bit error detected [1] ECC multi bit error * detected [6:2] Errored bit position for single bit ECC error [7] CRC error detected [8] High Speed * forward TX timeout detected [9] Reverse Low power data receive timeout detected [10] BTA * timeout detected */ #define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK) /*! @} */ /*! * @} */ /* end of group MIPI_DSI_HOST_Register_Masks */ /* MIPI_DSI_HOST - Peripheral instance base addresses */ /** Peripheral MIPI_DSI_HOST0 base address */ #define MIPI_DSI_HOST0_BASE (0x40A90000u) /** Peripheral MIPI_DSI_HOST0 base pointer */ #define MIPI_DSI_HOST0 ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST0_BASE) /** Array initializer of MIPI_DSI_HOST peripheral base addresses */ #define MIPI_DSI_HOST_BASE_ADDRS { MIPI_DSI_HOST0_BASE } /** Array initializer of MIPI_DSI_HOST peripheral base pointers */ #define MIPI_DSI_HOST_BASE_PTRS { MIPI_DSI_HOST0 } /*! * @} */ /* end of group MIPI_DSI_HOST_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MIPI_DSI_HOST_APB_PKT_IF Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer MIPI_DSI_HOST_APB_PKT_IF Peripheral Access Layer * @{ */ /** MIPI_DSI_HOST_APB_PKT_IF - Register Layout Typedef */ typedef struct { __IO uint32_t DSI_HOST_TX_PAYLOAD; /**< , offset: 0x0 */ __IO uint32_t DSI_HOST_PKT_CONTROL; /**< , offset: 0x4 */ __IO uint32_t DSI_HOST_SEND_PACKET; /**< , offset: 0x8 */ __I uint32_t DSI_HOST_PKT_STATUS; /**< , offset: 0xC */ __I uint32_t DSI_HOST_PKT_FIFO_WR_LEVEL; /**< , offset: 0x10 */ __I uint32_t DSI_HOST_PKT_FIFO_RD_LEVEL; /**< , offset: 0x14 */ __I uint32_t DSI_HOST_PKT_RX_PAYLOAD; /**< , offset: 0x18 */ __I uint32_t DSI_HOST_PKT_RX_PKT_HEADER; /**< , offset: 0x1C */ __I uint32_t DSI_HOST_IRQ_STATUS; /**< , offset: 0x20 */ __I uint32_t DSI_HOST_IRQ_STATUS2; /**< , offset: 0x24 */ __IO uint32_t DSI_HOST_IRQ_MASK; /**< , offset: 0x28 */ __IO uint32_t DSI_HOST_IRQ_MASK2; /**< , offset: 0x2C */ } MIPI_DSI_HOST_APB_PKT_IF_Type; /* ---------------------------------------------------------------------------- -- MIPI_DSI_HOST_APB_PKT_IF Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_DSI_HOST_APB_PKT_IF_Register_Masks MIPI_DSI_HOST_APB_PKT_IF Register Masks * @{ */ /*! @name DSI_HOST_TX_PAYLOAD - */ /*! @{ */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK (0xFFFFFFFFU) #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT (0U) /*! dsi_host_tx_payload - Tx Payload data write register. Writes to this registers load the payload fifo with 32 bit values. */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK) /*! @} */ /*! @name DSI_HOST_PKT_CONTROL - */ /*! @{ */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK (0x7FFFFFFU) #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT (0U) /*! dsi_host_pkt_control - Tx packet control register. [15:0] - Packet word count [17:16] - Packet * Virtual Channel [23:18] - Packet Header DSI Data Type [24] - Lp or HS select. 0 - LP mode, 1 - * HS mode [25] - perform BTA after packet is sent [26] - perform BTA only, no packet tx */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK) /*! @} */ /*! @name DSI_HOST_SEND_PACKET - */ /*! @{ */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK (0x1U) #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT (0U) /*! dsi_host_send_packet - Tx send packet. Writing to this register causes the packet described in dsi_host_pkt_control to be sent. */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK) /*! @} */ /*! @name DSI_HOST_PKT_STATUS - */ /*! @{ */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK (0x1FFU) #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT (0U) /*! dsi_host_pkt_status - Status of APB to packet interface [0] - state machine not idle [1] - Tx * packet done [2] - dphy direction 0 - tx had control, 1 - rx has control [3] - tx fifo overflow * [4] - tx fifo underflow [5] - rx fifo overflow [6] - rx fifo underflow [7] - rx packet header * has been received [8] - all rx packet payload data has been receive d */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK) /*! @} */ /*! @name DSI_HOST_PKT_FIFO_WR_LEVEL - */ /*! @{ */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK (0xFFFFU) #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT (0U) /*! dsi_host_pkt_fifo_wr_level - Write level of APB to pkt interface fifo */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK) /*! @} */ /*! @name DSI_HOST_PKT_FIFO_RD_LEVEL - */ /*! @{ */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK (0xFFFFU) #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT (0U) /*! dsi_host_pkt_fifo_rd_level - Read level of APB to pkt interface fifo */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK) /*! @} */ /*! @name DSI_HOST_PKT_RX_PAYLOAD - */ /*! @{ */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK (0xFFFFFFFFU) #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT (0U) /*! dsi_host_pkt_rx_payload - APB to pkt interface rx payload read */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK) /*! @} */ /*! @name DSI_HOST_PKT_RX_PKT_HEADER - */ /*! @{ */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK (0xFFFFFFU) #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT (0U) /*! dsi_host_pkt_rx_pkt_header - APB to pkt interface rx packet header [15:0] word count [21:16] data type [23:22] Virtual Channel */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK) /*! @} */ /*! @name DSI_HOST_IRQ_STATUS - */ /*! @{ */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK (0xFFFFFFFFU) #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT (0U) /*! dsi_host_irq_status - Status of APB to packet interface [0] - state machine not idle [1] - Tx * packet done [2] - dphy direction 0 - tx had control, 1 - rx has control [3] - tx fifo overflow * [4] - tx fifo underflow [5] - rx fifo overflow [6] - rx fifo underflow [7] - rx packet header * has been received [8] - all rx packet payload data has been received [28:9] - map directory to * dsi host controller status_out port bit descriptions [29] - host bta timeout, host controller * host_bta_timeout port [30] - low power rx timeout, host controller lp_rx_timeout port [31] - * high speed tx timeout, host controller hs_tx_timeout port */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK) /*! @} */ /*! @name DSI_HOST_IRQ_STATUS2 - */ /*! @{ */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK (0x7U) #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT (0U) /*! dsi_host_irq_status2 - Status of APB to packet interface part 2. Read part 2 first then * dsi_host_irq_status. Reading dsi_host_irq_status will clear both status and status 2. [0] - single bit * ecc error [1] - multi bit ecc error [2] - crc error */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK) /*! @} */ /*! @name DSI_HOST_IRQ_MASK - */ /*! @{ */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK (0xFFFFFFFFU) #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT (0U) /*! dsi_host_irq_mask - irq mask [0] - state machine not idle [1] - Tx packet done [2] - dphy * direction 0 - tx had control, 1 - rx has control [3] - tx fifo overflow [4] - tx fifo underflow [5] * - rx fifo overflow [6] - rx fifo underflow [7] - rx packet header has been received [8] - all * rx packet payload data has been received [28:9] - map directory to dsi host controller * status_out port bit descriptions [29] - host bta timeout, host controller host_bta_timeout port [30] * - low power rx timeout, host controller lp_rx_timeout port [31] - high speed tx timeout, host * controller hs_tx_timeout port */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK) /*! @} */ /*! @name DSI_HOST_IRQ_MASK2 - */ /*! @{ */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK (0x7U) #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT (0U) /*! dsi_host_irq_mask2 - irq mask 2 [0] - single bit ecc error [1] - multi bit ecc error [2] - crc error */ #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK) /*! @} */ /*! * @} */ /* end of group MIPI_DSI_HOST_APB_PKT_IF_Register_Masks */ /* MIPI_DSI_HOST_APB_PKT_IF - Peripheral instance base addresses */ /** Peripheral MIPI_DSI_HOST_APB_PKT_IF0 base address */ #define MIPI_DSI_HOST_APB_PKT_IF0_BASE (0x40A90280u) /** Peripheral MIPI_DSI_HOST_APB_PKT_IF0 base pointer */ #define MIPI_DSI_HOST_APB_PKT_IF0 ((MIPI_DSI_HOST_APB_PKT_IF_Type *)MIPI_DSI_HOST_APB_PKT_IF0_BASE) /** Array initializer of MIPI_DSI_HOST_APB_PKT_IF peripheral base addresses */ #define MIPI_DSI_HOST_APB_PKT_IF_BASE_ADDRS { MIPI_DSI_HOST_APB_PKT_IF0_BASE } /** Array initializer of MIPI_DSI_HOST_APB_PKT_IF peripheral base pointers */ #define MIPI_DSI_HOST_APB_PKT_IF_BASE_PTRS { MIPI_DSI_HOST_APB_PKT_IF0 } /*! * @} */ /* end of group MIPI_DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MIPI_DSI_HOST_DPI_INTFC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_DSI_HOST_DPI_INTFC_Peripheral_Access_Layer MIPI_DSI_HOST_DPI_INTFC Peripheral Access Layer * @{ */ /** MIPI_DSI_HOST_DPI_INTFC - Register Layout Typedef */ typedef struct { __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE; /**< , offset: 0x0 */ __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL; /**< , offset: 0x4 */ __IO uint32_t DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING; /**< , offset: 0x8 */ __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FORMAT; /**< , offset: 0xC */ __IO uint32_t DSI_HOST_CFG_DPI_VSYNC_POLARITY; /**< , offset: 0x10 */ __IO uint32_t DSI_HOST_CFG_DPI_HSYNC_POLARITY; /**< , offset: 0x14 */ __IO uint32_t DSI_HOST_CFG_DPI_VIDEO_MODE; /**< , offset: 0x18 */ __IO uint32_t DSI_HOST_CFG_DPI_HFP; /**< , offset: 0x1C */ __IO uint32_t DSI_HOST_CFG_DPI_HBP; /**< , offset: 0x20 */ __IO uint32_t DSI_HOST_CFG_DPI_HSA; /**< , offset: 0x24 */ __IO uint32_t DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS; /**< , offset: 0x28 */ __IO uint32_t DSI_HOST_CFG_DPI_VBP; /**< , offset: 0x2C */ __IO uint32_t DSI_HOST_CFG_DPI_VFP; /**< , offset: 0x30 */ __IO uint32_t DSI_HOST_CFG_DPI_BLLP_MODE; /**< , offset: 0x34 */ __IO uint32_t DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP; /**< , offset: 0x38 */ __IO uint32_t DSI_HOST_CFG_DPI_VACTIVE; /**< , offset: 0x3C */ __IO uint32_t DSI_HOST_CFG_DPI_VC; /**< , offset: 0x40 */ } MIPI_DSI_HOST_DPI_INTFC_Type; /* ---------------------------------------------------------------------------- -- MIPI_DSI_HOST_DPI_INTFC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_DSI_HOST_DPI_INTFC_Register_Masks MIPI_DSI_HOST_DPI_INTFC Register Masks * @{ */ /*! @name DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE - */ /*! @{ */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK (0xFFFFU) #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT (0U) /*! dsi_host_cfg_dpi_pixel_payload_size - Maximum number of pixels that should be sent as one DSI * packet. Recommended that the line size (in pixels) is evenly divisible by this parameter (packet * payload size in pixels). */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL - */ /*! @{ */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK (0xFFFFU) #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT (0U) /*! dsi_host_cfg_dpi_pixel_fifo_send_level - In order to optimize DSI utility, the DPI bridge * buffers a cerntain number of DPI pixels before initiating a DSI packet. This configuration port * controls the level at which the DPI Host bridge begins sending pixels. */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING - */ /*! @{ */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK (0x7U) #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT (0U) /*! dsi_host_cfg_dpi_interface_color_coding - Sets the distribution of RGB bits within the 24-bit d * bus, as specified by the DPI specification. 0= 16-bit Configuration 1 1= 16-bit Configuration * 2 2= 16-bit Configuration 3 3= 18-bit Configuration 1 4= 18-bit Configuration 2 5= 24-bit */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_PIXEL_FORMAT - */ /*! @{ */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK (0x3U) #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT (0U) /*! dsi_host_cfg_dpi_pixel_format - Sets the DSI packet type of the pixels. 0 - 16 bit 1 - 18 bit 2 - 18 bit loosely packed 3 - 24 bit */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_VSYNC_POLARITY - */ /*! @{ */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK (0x1U) #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT (0U) /*! dsi_host_cfg_dpi_vsync_polarity - Sets polarity of dpi_vsync_input 0 - active low 1 - active high */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_HSYNC_POLARITY - */ /*! @{ */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK (0x1U) #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT (0U) /*! dsi_host_cfg_dpi_hsync_polarity - Sets polarity of dpi_hsync_input 0 - active low 1 - active high */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_VIDEO_MODE - */ /*! @{ */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK (0x3U) #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT (0U) /*! dsi_host_cfg_dpi_video_mode - Select DSI video mode that the host DPI module should generate * packets for. 2'b00 - Non-Burst mode with Sync Pulses 2'b01 - Non-Burst mode with Sync Events * 2'b10 - Burst mode 2'b11 - Reserved, not valid */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_HFP - */ /*! @{ */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK (0xFFFFU) #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT (0U) /*! dsi_host_cfg_dpi_hfp - Sets the DSI packet payload size, in bytes, of the horizontal front porch blanking packet. */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_HBP - */ /*! @{ */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK (0xFFFFU) #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT (0U) /*! dsi_host_cfg_dpi_hbp - Sets the DSI packet payload size, in bytes, of the horizontal back porch blanking packet. */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_HSA - */ /*! @{ */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK (0xFFFFU) #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT (0U) /*! dsi_host_cfg_dpi_hsa - Sets the DSI packet payload size, in bytes, of the horizontal sync width filler blanking packet. */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS - */ /*! @{ */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK (0x1U) #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT (0U) /*! dsi_host_cfg_dpi_enable_mult_pkts - Enable Multiple packets per video line. When enabled, * cfg_dpi_pixel_payload_size must be set to exactly half the size of the video line. 0 - Video Line is * sent in a single packet 1 - Video Line is sent in two packets */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_VBP - */ /*! @{ */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK (0xFFU) #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT (0U) /*! dsi_host_cfg_dpi_vbp - Sets the number of lines in the vertical back porch. */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_VFP - */ /*! @{ */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK (0xFFU) #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT (0U) /*! dsi_host_cfg_dpi_vfp - Sets the number of lines in the vertical front porch. */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_BLLP_MODE - */ /*! @{ */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK (0x1U) #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT (0U) /*! dsi_host_cfg_dpi_bllp_mode - Optimize bllp periods to Low Power mode when possible 0 - blanking * packets are sent during BLLP periods 1 - LP mode is used for BLLP periods */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP - */ /*! @{ */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK (0x1U) #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT (0U) /*! dsi_host_cfg_dpi_use_null_pkt_bllp - Selects type of blanking packet to be sent during bllp * region 0 - Blanking packet used in bllp region 1 - Null packet used in bllp region */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_VACTIVE - */ /*! @{ */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK (0x3FFFU) #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT (0U) /*! dsi_host_cfg_dpi_vactive - Sets the number of lines in the vertical active area. This field is * equivalent to (real vertical size) - 1. For example, for an image of size 640x480, the bit * field should be set as 479. */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_VC - */ /*! @{ */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK (0x3U) #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT (0U) /*! dsi_host_cfg_dpi_vc - Sets the Virtual Channel (VC) of packets that will be sent to the receive * packet interface. Packets with VC not equal to this value are discarded and the "DSI VC ID * Invalid" bit (bit 12) in the DSI error report is set. */ #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK) /*! @} */ /*! * @} */ /* end of group MIPI_DSI_HOST_DPI_INTFC_Register_Masks */ /* MIPI_DSI_HOST_DPI_INTFC - Peripheral instance base addresses */ /** Peripheral MIPI_DSI_HOST_DPI_INTFC0 base address */ #define MIPI_DSI_HOST_DPI_INTFC0_BASE (0x40A90200u) /** Peripheral MIPI_DSI_HOST_DPI_INTFC0 base pointer */ #define MIPI_DSI_HOST_DPI_INTFC0 ((MIPI_DSI_HOST_DPI_INTFC_Type *)MIPI_DSI_HOST_DPI_INTFC0_BASE) /** Array initializer of MIPI_DSI_HOST_DPI_INTFC peripheral base addresses */ #define MIPI_DSI_HOST_DPI_INTFC_BASE_ADDRS { MIPI_DSI_HOST_DPI_INTFC0_BASE } /** Array initializer of MIPI_DSI_HOST_DPI_INTFC peripheral base pointers */ #define MIPI_DSI_HOST_DPI_INTFC_BASE_PTRS { MIPI_DSI_HOST_DPI_INTFC0 } /*! * @} */ /* end of group MIPI_DSI_HOST_DPI_INTFC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Peripheral_Access_Layer MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC Peripheral Access Layer * @{ */ /** MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC - Register Layout Typedef */ typedef struct { __IO uint32_t DPHY_PD_DPHY; /**< , offset: 0x0 */ __IO uint32_t DPHY_M_PRG_HS_PREPARE; /**< , offset: 0x4 */ __IO uint32_t DPHY_MC_PRG_HS_PREPARE; /**< , offset: 0x8 */ __IO uint32_t DPHY_M_PRG_HS_ZERO; /**< , offset: 0xC */ __IO uint32_t DPHY_MC_PRG_HS_ZERO; /**< , offset: 0x10 */ __IO uint32_t DPHY_M_PRG_HS_TRAIL; /**< , offset: 0x14 */ __IO uint32_t DPHY_MC_PRG_HS_TRAIL; /**< , offset: 0x18 */ __IO uint32_t DPHY_PD_PLL; /**< , offset: 0x1C */ __IO uint32_t DPHY_TST; /**< , offset: 0x20 */ __IO uint32_t DPHY_CN; /**< , offset: 0x24 */ __IO uint32_t DPHY_CM; /**< , offset: 0x28 */ __IO uint32_t DPHY_CO; /**< , offset: 0x2C */ __I uint32_t DPHY_LOCK; /**< , offset: 0x30 */ __IO uint32_t DPHY_LOCK_BYP; /**< , offset: 0x34 */ __IO uint32_t DPHY_RTERM_SEL; /**< , offset: 0x38 */ __IO uint32_t DPHY_AUTO_PD_EN; /**< , offset: 0x3C */ __IO uint32_t DPHY_RXLPRP; /**< , offset: 0x40 */ __IO uint32_t DPHY_RXCDRP; /**< , offset: 0x44 */ } MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Type; /* ---------------------------------------------------------------------------- -- MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Register_Masks MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC Register Masks * @{ */ /*! @name DPHY_PD_DPHY - */ /*! @{ */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy_MASK (0x1U) #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy_SHIFT (0U) /*! dphy_pd_dphy - DPHY PD_DPHY input control. Detailed information about this parameter programming * is available in the MIPI-DSI DPHY section. */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy_MASK) /*! @} */ /*! @name DPHY_M_PRG_HS_PREPARE - */ /*! @{ */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK (0x3U) #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT (0U) /*! dphy_m_prg_hs_prepare - DPHY m_PRG_HS_PREPARE input. Detailed information about this parameter * programming is available in the MIPI-DSI DPHY section. * 0b00..1 * 0b01..1.5 * 0b10..2 * 0b11..2.5 */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK) /*! @} */ /*! @name DPHY_MC_PRG_HS_PREPARE - */ /*! @{ */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK (0x1U) #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT (0U) /*! dphy_mc_prg_hs_prepare - DPHY mc_PRG_HS_PREPARE input. Detailed information about this parameter * programming is available in the MIPI-DSI DPHY section. * 0b0..1 * 0b1..1.5 */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK) /*! @} */ /*! @name DPHY_M_PRG_HS_ZERO - */ /*! @{ */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK (0x1FU) #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT (0U) /*! dphy_m_prg_hs_zero - DPHY m_PRG_HS_ZERO input. Detailed information about this parameter * programming is available in the MIPI-DSI DPHY section. * 0b00000..0 * 0b00001..1 * 0b00010..2 * 0b00011..3 * 0b00100..4 * 0b00101..5 * 0b00110..6 * 0b00111..7 * 0b01000..8 * 0b01001..9 * 0b01010..10 * 0b01011..11 * 0b01100..12 * 0b01101..13 * 0b01110..14 * 0b01111..15 * 0b10000..16 * 0b10001..17 * 0b10010..18 * 0b10011..19 * 0b10100..20 * 0b10101..21 * 0b10110..22 * 0b10111..23 * 0b11000..24 * 0b11001..25 * 0b11010..26 * 0b11011..27 * 0b11100..28 * 0b11101..29 * 0b11110..30 * 0b11111..31 */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK) /*! @} */ /*! @name DPHY_MC_PRG_HS_ZERO - */ /*! @{ */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK (0x3FU) #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT (0U) /*! dphy_mc_prg_hs_zero - DPHY mc_PRG_HS_ZERO input. Detailed information about this parameter * programming is available in the MIPI-DSI DPHY section. * 0b100000..32 * 0b100001..33 * 0b100010..34 * 0b100011..35 * 0b100100..36 * 0b100101..37 * 0b100110..38 * 0b100111..39 * 0b101000..40 * 0b101001..41 * 0b101010..42 * 0b101011..43 * 0b101100..44 * 0b101101..45 * 0b101110..46 * 0b101111..47 * 0b110000..48 * 0b110001..49 * 0b110010..50 * 0b110011..51 * 0b110100..52 * 0b110101..53 * 0b110110..54 * 0b110111..55 * 0b111000..56 * 0b111001..57 * 0b111010..58 * 0b111011..59 * 0b111100..60 * 0b111101..61 * 0b111110..62 * 0b111111..63 */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK) /*! @} */ /*! @name DPHY_M_PRG_HS_TRAIL - */ /*! @{ */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK (0xFU) #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT (0U) /*! dphy_m_prg_hs_trail - DPHY m_PRG_HS_TRAIL input. Detailed information about this parameter * programming is available in the MIPI-DSI DPHY section. * 0b0000..0 * 0b0001..1 * 0b0010..2 * 0b0011..3 * 0b0100..4 * 0b0101..5 * 0b0110..6 * 0b0111..7 * 0b1000..8 * 0b1001..9 * 0b1010..10 * 0b1011..11 * 0b1100..12 * 0b1101..13 * 0b1110..14 * 0b1111..15 */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK) /*! @} */ /*! @name DPHY_MC_PRG_HS_TRAIL - */ /*! @{ */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK (0xFU) #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT (0U) /*! dphy_mc_prg_hs_trail - DPHY mc_PRG_HS_TRAIL input. Detailed information about this parameter * programming is available in the MIPI-DSI DPHY section. * 0b0000..0 * 0b0001..1 * 0b0010..2 * 0b0011..3 * 0b0100..4 * 0b0101..5 * 0b0110..6 * 0b0111..7 * 0b1000..8 * 0b1001..9 * 0b1010..10 * 0b1011..11 * 0b1100..12 * 0b1101..13 * 0b1110..14 * 0b1111..15 */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK) /*! @} */ /*! @name DPHY_PD_PLL - */ /*! @{ */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD_MASK (0x1U) #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD_SHIFT (0U) /*! PD - DPHY PD_PLL input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD_MASK) /*! @} */ /*! @name DPHY_TST - */ /*! @{ */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST_MASK (0x3FU) #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST_SHIFT (0U) /*! TST - DPHY TST input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST_MASK) /*! @} */ /*! @name DPHY_CN - */ /*! @{ */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN_MASK (0x1FU) #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN_SHIFT (0U) /*! CN * 0b11111..Divide by 1 * 0b00000..Divide by 2 * 0b10000..Divide by 3 * 0b11000..Divide by 4 * 0b11100..Divide by 5 * 0b01110..Divide by 6 * 0b00111..Divide by 7 * 0b10011..Divide by 8 * 0b01001..Divide by 9 * 0b00100..Divide by 10 * 0b00010..Divide by 11 * 0b10001..Divide by 12 * 0b01000..Divide by 13 * 0b10100..Divide by 14 * 0b01010..Divide by 15 * 0b10101..Divide by 16 * 0b11010..Divide by 17 * 0b11101..Divide by 18 * 0b11110..Divide by 19 * 0b01111..Divide by 20 * 0b10111..Divide by 21 * 0b11011..Divide by 22 * 0b01101..Divide by 23 * 0b10110..Divide by 24 * 0b01011..Divide by 25 * 0b00101..Divide by 26 * 0b10010..Divide by 27 * 0b11001..Divide by 28 * 0b01100..Divide by 29 * 0b00110..Divide by 30 * 0b00011..Divide by 31 * 0b00001..Divide by 32 */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN_MASK) /*! @} */ /*! @name DPHY_CM - */ /*! @{ */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM_MASK (0xFFU) #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM_SHIFT (0U) /*! CM * 0b111x0000..Divide by 16 * 0b111x1111..Divide by 31 * 0b11000000..Divide by 32 * 0b11011111..Divide by 63 * 0b10000000..Divide by 64 * 0b10111111..Divide by 127 * 0b00000000..Divide by 128 * 0b01111111..Divide by 255 */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM_MASK) /*! @} */ /*! @name DPHY_CO - */ /*! @{ */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO_MASK (0x3U) #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO_SHIFT (0U) /*! CO * 0b00..Divide by 1 * 0b01..Divide by 2 * 0b10..Divide by 4 * 0b11..Divide by 8 */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO_MASK) /*! @} */ /*! @name DPHY_LOCK - */ /*! @{ */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK_MASK (0x1U) #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK_SHIFT (0U) /*! LOCK - DPHY PLL LOCK output. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK_MASK) /*! @} */ /*! @name DPHY_LOCK_BYP - */ /*! @{ */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp_MASK (0x1U) #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp_SHIFT (0U) /*! dphy_lock_byp - DPHY LOCK_BYP input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp_MASK) /*! @} */ /*! @name DPHY_RTERM_SEL - */ /*! @{ */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel_MASK (0x1U) #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel_SHIFT (0U) /*! dphy_rterm_sel - DPHY RTERM_SEL input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel_MASK) /*! @} */ /*! @name DPHY_AUTO_PD_EN - */ /*! @{ */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK (0x1U) #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT (0U) /*! dphy_auto_pd_en - DPHY AUTO_PD_EN input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK) /*! @} */ /*! @name DPHY_RXLPRP - */ /*! @{ */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp_MASK (0x3U) #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp_SHIFT (0U) /*! dphy_rxlprp - DPHY RXLPRP input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp_MASK) /*! @} */ /*! @name DPHY_RXCDRP - */ /*! @{ */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp_MASK (0x3U) #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp_SHIFT (0U) /*! dphy_rxcdrp - DPHY RXCDRP input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp_MASK) /*! @} */ /*! * @} */ /* end of group MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Register_Masks */ /* MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC - Peripheral instance base addresses */ /** Peripheral MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC0 base address */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC0_BASE (0x40A90300u) /** Peripheral MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC0 base pointer */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC0 ((MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Type *)MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC0_BASE) /** Array initializer of MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC peripheral base * addresses */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_BASE_ADDRS { MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC0_BASE } /** Array initializer of MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC peripheral base * pointers */ #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_BASE_PTRS { MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC0 } /*! * @} */ /* end of group MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MMCAU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MMCAU_Peripheral_Access_Layer MMCAU Peripheral Access Layer * @{ */ /** MMCAU - Register Layout Typedef */ typedef struct { __IO uint32_t CASR; /**< Status Register, offset: 0x0 */ __IO uint32_t CAA; /**< Accumulator, offset: 0x4 */ __IO uint32_t CA[9]; /**< General Purpose Register, array offset: 0x8, array step: 0x4 */ } MMCAU_Type; /* ---------------------------------------------------------------------------- -- MMCAU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MMCAU_Register_Masks MMCAU Register Masks * @{ */ /*! @name CASR - Status Register */ /*! @{ */ #define MMCAU_CASR_IC_MASK (0x1U) #define MMCAU_CASR_IC_SHIFT (0U) /*! IC - Illegal Command * 0b0..No illegal commands issued. * 0b1..Illegal command issued. */ #define MMCAU_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_IC_SHIFT)) & MMCAU_CASR_IC_MASK) #define MMCAU_CASR_DPE_MASK (0x2U) #define MMCAU_CASR_DPE_SHIFT (1U) /*! DPE - DES Parity Error * 0b0..No error detected. * 0b1..DES key parity error detected. */ #define MMCAU_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_DPE_SHIFT)) & MMCAU_CASR_DPE_MASK) #define MMCAU_CASR_VER_MASK (0xF0000000U) #define MMCAU_CASR_VER_SHIFT (28U) /*! VER - CAU Version * 0b0001..Initial CAU version. * 0b0010..Second version, added support for SHA-256 algorithm (This is the value on this device). */ #define MMCAU_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_VER_SHIFT)) & MMCAU_CASR_VER_MASK) /*! @} */ /*! @name CAA - Accumulator */ /*! @{ */ #define MMCAU_CAA_ACC_MASK (0xFFFFFFFFU) #define MMCAU_CAA_ACC_SHIFT (0U) /*! ACC - Accumulator */ #define MMCAU_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << MMCAU_CAA_ACC_SHIFT)) & MMCAU_CAA_ACC_MASK) /*! @} */ /*! @name CA - General Purpose Register */ /*! @{ */ #define MMCAU_CA_CAn_MASK (0xFFFFFFFFU) #define MMCAU_CA_CAn_SHIFT (0U) /*! CAn - General Purpose Registers */ #define MMCAU_CA_CAn(x) (((uint32_t)(((uint32_t)(x)) << MMCAU_CA_CAn_SHIFT)) & MMCAU_CA_CAn_MASK) /*! @} */ /* The count of MMCAU_CA */ #define MMCAU_CA_COUNT (9U) /*! * @} */ /* end of group MMCAU_Register_Masks */ /* MMCAU - Peripheral instance base addresses */ /** Peripheral MMCAU base address */ #define MMCAU_BASE (0xE0081000u) /** Peripheral MMCAU base pointer */ #define MMCAU ((MMCAU_Type *)MMCAU_BASE) /** Array initializer of MMCAU peripheral base addresses */ #define MMCAU_BASE_ADDRS { MMCAU_BASE } /** Array initializer of MMCAU peripheral base pointers */ #define MMCAU_BASE_PTRS { MMCAU } /*! * @} */ /* end of group MMCAU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MMDC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MMDC_Peripheral_Access_Layer MMDC Peripheral Access Layer * @{ */ /** MMDC - Register Layout Typedef */ typedef struct { __IO uint32_t MDCTL; /**< MMDC Core Control Register, offset: 0x0 */ __IO uint32_t MDPDC; /**< MMDC Core Power Down Control Register, offset: 0x4 */ uint8_t RESERVED_0[4]; __IO uint32_t MDCFG0; /**< MMDC Core Timing Configuration Register 0, offset: 0xC */ __IO uint32_t MDCFG1; /**< MMDC Core Timing Configuration Register 1, offset: 0x10 */ __IO uint32_t MDCFG2; /**< MMDC Core Timing Configuration Register 2, offset: 0x14 */ __IO uint32_t MDMISC; /**< MMDC Core Miscellaneous Register, offset: 0x18 */ __IO uint32_t MDSCR; /**< MMDC Core Special Command Register, offset: 0x1C */ __IO uint32_t MDREF; /**< MMDC Core Refresh Control Register, offset: 0x20 */ uint8_t RESERVED_1[8]; __IO uint32_t MDRWD; /**< MMDC Core Read/Write Command Delay Register, offset: 0x2C */ __IO uint32_t MDOR; /**< MMDC Core Out of Reset Delays Register, offset: 0x30 */ __I uint32_t MDMRR; /**< MMDC Core MRR Data Register, offset: 0x34 */ __IO uint32_t MDCFG3LP; /**< MMDC Core Timing Configuration Register 3, offset: 0x38 */ __IO uint32_t MDMR4; /**< MMDC Core MR4 Derating Register, offset: 0x3C */ __IO uint32_t MDASP; /**< MMDC Core Address Space Partition Register, offset: 0x40 */ uint8_t RESERVED_2[956]; __IO uint32_t MAARCR; /**< MMDC Core AXI Reordering Control Register, offset: 0x400 */ __IO uint32_t MAPSR; /**< MMDC Core Power Saving Control and Status Register, offset: 0x404 */ __IO uint32_t MAEXIDR0; /**< MMDC Core Exclusive ID Monitor Register0, offset: 0x408 */ __IO uint32_t MAEXIDR1; /**< MMDC Core Exclusive ID Monitor Register1, offset: 0x40C */ __IO uint32_t MADPCR0; /**< MMDC Core Debug and Profiling Control Register 0, offset: 0x410 */ __IO uint32_t MADPCR1; /**< MMDC Core Debug and Profiling Control Register 1, offset: 0x414 */ __I uint32_t MADPSR0; /**< MMDC Core Debug and Profiling Status Register 0, offset: 0x418 */ __I uint32_t MADPSR1; /**< MMDC Core Debug and Profiling Status Register 1, offset: 0x41C */ __I uint32_t MADPSR2; /**< MMDC Core Debug and Profiling Status Register 2, offset: 0x420 */ __I uint32_t MADPSR3; /**< MMDC Core Debug and Profiling Status Register 3, offset: 0x424 */ __I uint32_t MADPSR4; /**< MMDC Core Debug and Profiling Status Register 4, offset: 0x428 */ __I uint32_t MADPSR5; /**< MMDC Core Debug and Profiling Status Register 5, offset: 0x42C */ __I uint32_t MASBS0; /**< MMDC Core Step By Step Address Register, offset: 0x430 */ __I uint32_t MASBS1; /**< MMDC Core Step By Step Address Attributes Register, offset: 0x434 */ uint8_t RESERVED_3[8]; __IO uint32_t MAGENP; /**< MMDC Core General Purpose Register, offset: 0x440 */ uint8_t RESERVED_4[956]; __IO uint32_t MPZQHWCTRL; /**< MMDC PHY ZQ HW control register, offset: 0x800 */ __IO uint32_t MPZQSWCTRL; /**< MMDC PHY ZQ SW control register, offset: 0x804 */ uint8_t RESERVED_5[20]; __IO uint32_t MPRDDQBY0DL; /**< MMDC PHY Read DQ Byte0 Delay Register, offset: 0x81C */ __IO uint32_t MPRDDQBY1DL; /**< MMDC PHY Read DQ Byte1 Delay Register, offset: 0x820 */ __IO uint32_t MPRDDQBY2DL; /**< MMDC PHY Read DQ Byte2 Delay Register, offset: 0x824 */ __IO uint32_t MPRDDQBY3DL; /**< MMDC PHY Read DQ Byte3 Delay Register, offset: 0x828 */ uint8_t RESERVED_6[16]; __IO uint32_t MPDGCTRL0; /**< MMDC PHY Read DQS Gating Control Register 0, offset: 0x83C */ uint8_t RESERVED_7[8]; __IO uint32_t MPRDDLCTL; /**< MMDC PHY Read delay-lines Configuration Register, offset: 0x848 */ __I uint32_t MPRDDLST; /**< MMDC PHY Read delay-lines Status Register, offset: 0x84C */ __IO uint32_t MPWRDLCTL; /**< MMDC PHY Write delay-lines Configuration Register, offset: 0x850 */ __I uint32_t MPWRDLST; /**< MMDC PHY Write delay-lines Status Register, offset: 0x854 */ uint8_t RESERVED_8[4]; __IO uint32_t MPZQLP2CTL; /**< MMDC ZQ LPDDR2 HW Control Register, offset: 0x85C */ __IO uint32_t MPRDDLHWCTL; /**< MMDC PHY Read Delay HW Calibration Control Register, offset: 0x860 */ __IO uint32_t MPWRDLHWCTL; /**< MMDC PHY Write Delay HW Calibration Control Register, offset: 0x864 */ __I uint32_t MPRDDLHWST0; /**< MMDC PHY Read Delay HW Calibration Status Register 0, offset: 0x868 */ __I uint32_t MPRDDLHWST1; /**< MMDC PHY Read Delay HW Calibration Status Register 1, offset: 0x86C */ __I uint32_t MPWRDLHWST0; /**< MMDC PHY Write Delay HW Calibration Status Register 0, offset: 0x870 */ __I uint32_t MPWRDLHWST1; /**< MMDC PHY Write Delay HW Calibration Status Register 1, offset: 0x874 */ uint8_t RESERVED_9[20]; __IO uint32_t MPPDCMPR1; /**< MMDC PHY Pre-defined Compare Register 1, offset: 0x88C */ __IO uint32_t MPPDCMPR2; /**< MMDC PHY Pre-defined Compare and CA delay-line Configuration Register, offset: 0x890 */ __IO uint32_t MPSWDAR0; /**< MMDC PHY SW Dummy Access Register, offset: 0x894 */ __I uint32_t MPSWDRDR0; /**< MMDC PHY SW Dummy Read Data Register 0, offset: 0x898 */ __I uint32_t MPSWDRDR1; /**< MMDC PHY SW Dummy Read Data Register 1, offset: 0x89C */ __I uint32_t MPSWDRDR2; /**< MMDC PHY SW Dummy Read Data Register 2, offset: 0x8A0 */ __I uint32_t MPSWDRDR3; /**< MMDC PHY SW Dummy Read Data Register 3, offset: 0x8A4 */ __I uint32_t MPSWDRDR4; /**< MMDC PHY SW Dummy Read Data Register 4, offset: 0x8A8 */ __I uint32_t MPSWDRDR5; /**< MMDC PHY SW Dummy Read Data Register 5, offset: 0x8AC */ __I uint32_t MPSWDRDR6; /**< MMDC PHY SW Dummy Read Data Register 6, offset: 0x8B0 */ __I uint32_t MPSWDRDR7; /**< MMDC PHY SW Dummy Read Data Register 7, offset: 0x8B4 */ __IO uint32_t MPMUR0; /**< MMDC PHY Measure Unit Register, offset: 0x8B8 */ uint8_t RESERVED_10[4]; __IO uint32_t MPDCCR; /**< MMDC Duty Cycle Control Register, offset: 0x8C0 */ } MMDC_Type; /* ---------------------------------------------------------------------------- -- MMDC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MMDC_Register_Masks MMDC Register Masks * @{ */ /*! @name MDCTL - MMDC Core Control Register */ /*! @{ */ #define MMDC_MDCTL_DSIZ_MASK (0x30000U) #define MMDC_MDCTL_DSIZ_SHIFT (16U) /*! DSIZ * 0b00..16-bit data bus * 0b01..32-bit data bus */ #define MMDC_MDCTL_DSIZ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_DSIZ_SHIFT)) & MMDC_MDCTL_DSIZ_MASK) #define MMDC_MDCTL_BL_MASK (0x80000U) #define MMDC_MDCTL_BL_SHIFT (19U) /*! BL * 0b0..Burst Length 4 is used * 0b1..Burst Length 8 is used */ #define MMDC_MDCTL_BL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_BL_SHIFT)) & MMDC_MDCTL_BL_MASK) #define MMDC_MDCTL_COL_MASK (0x700000U) #define MMDC_MDCTL_COL_SHIFT (20U) /*! COL * 0b000..9 bits column * 0b001..10 bits column * 0b010..11 bits column * 0b011..8 bits column * 0b100..12 bits column */ #define MMDC_MDCTL_COL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_COL_SHIFT)) & MMDC_MDCTL_COL_MASK) #define MMDC_MDCTL_ROW_MASK (0x7000000U) #define MMDC_MDCTL_ROW_SHIFT (24U) /*! ROW * 0b000..11 bits Row * 0b001..12 bits Row * 0b010..13 bits Row * 0b011..14 bits Row * 0b100..15 bits Row * 0b101..16 bits Row */ #define MMDC_MDCTL_ROW(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_ROW_SHIFT)) & MMDC_MDCTL_ROW_MASK) #define MMDC_MDCTL_SDE_1_MASK (0x40000000U) #define MMDC_MDCTL_SDE_1_SHIFT (30U) /*! SDE_1 * 0b0..Disabled * 0b1..Enabled */ #define MMDC_MDCTL_SDE_1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_SDE_1_SHIFT)) & MMDC_MDCTL_SDE_1_MASK) #define MMDC_MDCTL_SDE_0_MASK (0x80000000U) #define MMDC_MDCTL_SDE_0_SHIFT (31U) /*! SDE_0 * 0b0..Disabled * 0b1..Enabled */ #define MMDC_MDCTL_SDE_0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_SDE_0_SHIFT)) & MMDC_MDCTL_SDE_0_MASK) /*! @} */ /*! @name MDPDC - MMDC Core Power Down Control Register */ /*! @{ */ #define MMDC_MDPDC_tCKSRE_MASK (0x7U) #define MMDC_MDPDC_tCKSRE_SHIFT (0U) /*! tCKSRE * 0b000..0 cycle * 0b001..1 cycles * 0b110..6 cycles * 0b111..7 cycles */ #define MMDC_MDPDC_tCKSRE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_tCKSRE_SHIFT)) & MMDC_MDPDC_tCKSRE_MASK) #define MMDC_MDPDC_tCKSRX_MASK (0x38U) #define MMDC_MDPDC_tCKSRX_SHIFT (3U) /*! tCKSRX * 0b000..0 cycle * 0b001..1 cycles * 0b110..6 cycles * 0b111..7 cycles */ #define MMDC_MDPDC_tCKSRX(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_tCKSRX_SHIFT)) & MMDC_MDPDC_tCKSRX_MASK) #define MMDC_MDPDC_BOTH_CS_PD_MASK (0x40U) #define MMDC_MDPDC_BOTH_CS_PD_SHIFT (6U) /*! BOTH_CS_PD * 0b0..Each chip select can enter power down independently according to its configuration. * 0b1..Chip selects can enter power down only if the amount of idle cycles of both chip selects was obtained. */ #define MMDC_MDPDC_BOTH_CS_PD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_BOTH_CS_PD_SHIFT)) & MMDC_MDPDC_BOTH_CS_PD_MASK) #define MMDC_MDPDC_SLOW_PD_MASK (0x80U) #define MMDC_MDPDC_SLOW_PD_SHIFT (7U) /*! SLOW_PD * 0b0..Fast mode. * 0b1..Slow mode. */ #define MMDC_MDPDC_SLOW_PD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_SLOW_PD_SHIFT)) & MMDC_MDPDC_SLOW_PD_MASK) #define MMDC_MDPDC_PWDT_0_MASK (0xF00U) #define MMDC_MDPDC_PWDT_0_SHIFT (8U) #define MMDC_MDPDC_PWDT_0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PWDT_0_SHIFT)) & MMDC_MDPDC_PWDT_0_MASK) #define MMDC_MDPDC_PWDT_1_MASK (0xF000U) #define MMDC_MDPDC_PWDT_1_SHIFT (12U) #define MMDC_MDPDC_PWDT_1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PWDT_1_SHIFT)) & MMDC_MDPDC_PWDT_1_MASK) #define MMDC_MDPDC_tCKE_MASK (0x70000U) #define MMDC_MDPDC_tCKE_SHIFT (16U) /*! tCKE * 0b000..1 cycle * 0b001..2 cycles * 0b110..7 cycles * 0b111..8 cycles */ #define MMDC_MDPDC_tCKE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_tCKE_SHIFT)) & MMDC_MDPDC_tCKE_MASK) #define MMDC_MDPDC_PRCT_0_MASK (0x7000000U) #define MMDC_MDPDC_PRCT_0_SHIFT (24U) #define MMDC_MDPDC_PRCT_0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PRCT_0_SHIFT)) & MMDC_MDPDC_PRCT_0_MASK) #define MMDC_MDPDC_PRCT_1_MASK (0x70000000U) #define MMDC_MDPDC_PRCT_1_SHIFT (28U) #define MMDC_MDPDC_PRCT_1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PRCT_1_SHIFT)) & MMDC_MDPDC_PRCT_1_MASK) /*! @} */ /*! @name MDCFG0 - MMDC Core Timing Configuration Register 0 */ /*! @{ */ #define MMDC_MDCFG0_tCL_MASK (0xFU) #define MMDC_MDCFG0_tCL_SHIFT (0U) /*! tCL * 0b0000..3 cycles * 0b0001..4 cycles * 0b0010..5 cycles * 0b0011..6 cycles * 0b0100..7 cycles * 0b0101..8 cycles * 0b0110..9 cycles * 0b0111..10 cycles * 0b1000..11 cycles * 0b1001..- 0xF Reserved */ #define MMDC_MDCFG0_tCL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_tCL_SHIFT)) & MMDC_MDCFG0_tCL_MASK) #define MMDC_MDCFG0_tFAW_MASK (0x1F0U) #define MMDC_MDCFG0_tFAW_SHIFT (4U) /*! tFAW * 0b00000..1 clock * 0b00001..2 clocks * 0b00010..3 clocks * 0b11110..31 clocks * 0b11111..32 clocks */ #define MMDC_MDCFG0_tFAW(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_tFAW_SHIFT)) & MMDC_MDCFG0_tFAW_MASK) #define MMDC_MDCFG0_tXPDLL_MASK (0x1E00U) #define MMDC_MDCFG0_tXPDLL_SHIFT (9U) /*! tXPDLL * 0b0000..1 clock * 0b0001..2 clocks * 0b0010..3 clocks * 0b1110..15 clocks * 0b1111..16 clocks */ #define MMDC_MDCFG0_tXPDLL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_tXPDLL_SHIFT)) & MMDC_MDCFG0_tXPDLL_MASK) #define MMDC_MDCFG0_tXP_MASK (0xE000U) #define MMDC_MDCFG0_tXP_SHIFT (13U) /*! tXP * 0b000..1 cycle * 0b001..2 cycles * 0b110..7 cycles * 0b111..8 cycles */ #define MMDC_MDCFG0_tXP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_tXP_SHIFT)) & MMDC_MDCFG0_tXP_MASK) #define MMDC_MDCFG0_tXS_MASK (0xFF0000U) #define MMDC_MDCFG0_tXS_SHIFT (16U) /*! tXS * 0b00000000..- 0x15 reserved * 0b00010110..23 clocks * 0b00010111..24 clocks * 0b11111110..255 clocks * 0b11111111..256 clocks */ #define MMDC_MDCFG0_tXS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_tXS_SHIFT)) & MMDC_MDCFG0_tXS_MASK) #define MMDC_MDCFG0_tRFC_MASK (0xFF000000U) #define MMDC_MDCFG0_tRFC_SHIFT (24U) /*! tRFC * 0b00000000..1 clock * 0b00000001..2 clocks * 0b00000010..3 clocks * 0b11111110..255 clocks * 0b11111111..256 clocks */ #define MMDC_MDCFG0_tRFC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_tRFC_SHIFT)) & MMDC_MDCFG0_tRFC_MASK) /*! @} */ /*! @name MDCFG1 - MMDC Core Timing Configuration Register 1 */ /*! @{ */ #define MMDC_MDCFG1_tCWL_MASK (0x7U) #define MMDC_MDCFG1_tCWL_SHIFT (0U) /*! tCWL * 0b000..1 cycles (LPDDR2/LPDDR3) * 0b001..2 cycles (LPDDR2/LPDDR3) * 0b010..3 cycles (LPDDR2/LPDDR3) * 0b011..4 cycles (LPDDR2/LPDDR3) * 0b100..5 cycles (LPDDR2/LPDDR3) * 0b101..6 cycles (LPDDR2/LPDDR3) * 0b110..7 cycles (LPDDR2/LPDDR3) * 0b111..Reserved */ #define MMDC_MDCFG1_tCWL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_tCWL_SHIFT)) & MMDC_MDCFG1_tCWL_MASK) #define MMDC_MDCFG1_tMRD_MASK (0x1E0U) #define MMDC_MDCFG1_tMRD_SHIFT (5U) /*! tMRD * 0b0000..1 clock * 0b0001..2 clocks * 0b0010..3 clocks * 0b1110..15 clocks * 0b1111..16 clocks */ #define MMDC_MDCFG1_tMRD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_tMRD_SHIFT)) & MMDC_MDCFG1_tMRD_MASK) #define MMDC_MDCFG1_tWR_MASK (0xE00U) #define MMDC_MDCFG1_tWR_SHIFT (9U) /*! tWR * 0b000..1cycle * 0b001..2cycles * 0b010..3cycles * 0b011..4cycles * 0b100..5cycles * 0b101..6cycles * 0b110..7cycles * 0b111..8 cycles */ #define MMDC_MDCFG1_tWR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_tWR_SHIFT)) & MMDC_MDCFG1_tWR_MASK) #define MMDC_MDCFG1_tRPA_MASK (0x8000U) #define MMDC_MDCFG1_tRPA_SHIFT (15U) /*! tRPA * 0b0..Will be equal to: tRP. * 0b1..Will be equal to: tRP+1. */ #define MMDC_MDCFG1_tRPA(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_tRPA_SHIFT)) & MMDC_MDCFG1_tRPA_MASK) #define MMDC_MDCFG1_tRAS_MASK (0x1F0000U) #define MMDC_MDCFG1_tRAS_SHIFT (16U) /*! tRAS * 0b00000..1 clock * 0b00001..2 clocks * 0b00010..3 clocks * 0b11110..31 clocks * 0b11111..Reserved */ #define MMDC_MDCFG1_tRAS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_tRAS_SHIFT)) & MMDC_MDCFG1_tRAS_MASK) #define MMDC_MDCFG1_tRC_MASK (0x3E00000U) #define MMDC_MDCFG1_tRC_SHIFT (21U) /*! tRC * 0b00000..1 clock * 0b00001..2 clocks * 0b00010..3 clocks * 0b11110..31 clocks * 0b11111..32 clocks */ #define MMDC_MDCFG1_tRC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_tRC_SHIFT)) & MMDC_MDCFG1_tRC_MASK) #define MMDC_MDCFG1_tRP_MASK (0x1C000000U) #define MMDC_MDCFG1_tRP_SHIFT (26U) /*! tRP * 0b000..1 clock * 0b001..2 clocks * 0b010..3 clocks * 0b011..4 clocks * 0b100..5 clocks * 0b101..6 clocks * 0b110..7 clocks * 0b111..8 clocks */ #define MMDC_MDCFG1_tRP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_tRP_SHIFT)) & MMDC_MDCFG1_tRP_MASK) #define MMDC_MDCFG1_tRCD_MASK (0xE0000000U) #define MMDC_MDCFG1_tRCD_SHIFT (29U) /*! tRCD * 0b000..1 clock * 0b001..2 clocks * 0b010..3 clocks * 0b011..4 clocks * 0b100..5 clocks * 0b101..6 clocks * 0b110..7 clocks * 0b111..8 clocks */ #define MMDC_MDCFG1_tRCD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_tRCD_SHIFT)) & MMDC_MDCFG1_tRCD_MASK) /*! @} */ /*! @name MDCFG2 - MMDC Core Timing Configuration Register 2 */ /*! @{ */ #define MMDC_MDCFG2_tRRD_MASK (0x7U) #define MMDC_MDCFG2_tRRD_SHIFT (0U) /*! tRRD * 0b000..1cycle * 0b001..2cycles * 0b010..3cycles * 0b011..4cycles * 0b100..5cycles * 0b101..6cycles * 0b110..7cycles * 0b111..Reserved */ #define MMDC_MDCFG2_tRRD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_tRRD_SHIFT)) & MMDC_MDCFG2_tRRD_MASK) #define MMDC_MDCFG2_tWTR_MASK (0x38U) #define MMDC_MDCFG2_tWTR_SHIFT (3U) /*! tWTR * 0b000..1cycle * 0b001..2cycles * 0b010..3cycles * 0b011..4cycles * 0b100..5cycles * 0b101..6cycles * 0b110..7cycles * 0b111..8 cycles */ #define MMDC_MDCFG2_tWTR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_tWTR_SHIFT)) & MMDC_MDCFG2_tWTR_MASK) #define MMDC_MDCFG2_tRTP_MASK (0x1C0U) #define MMDC_MDCFG2_tRTP_SHIFT (6U) /*! tRTP * 0b000..1cycle * 0b001..2cycles * 0b010..3cycles * 0b011..4cycles * 0b100..5cycles * 0b101..6cycles * 0b110..7cycles * 0b111..8 cycles */ #define MMDC_MDCFG2_tRTP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_tRTP_SHIFT)) & MMDC_MDCFG2_tRTP_MASK) #define MMDC_MDCFG2_tDLLK_MASK (0x1FF0000U) #define MMDC_MDCFG2_tDLLK_SHIFT (16U) /*! tDLLK * 0b000000000..1 cycle. * 0b000000001..2 cycles. * 0b000000010..3 cycles. * 0b011000111..200 cycles * 0b111111110..511 cycles. * 0b111111111..512 cycles */ #define MMDC_MDCFG2_tDLLK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_tDLLK_SHIFT)) & MMDC_MDCFG2_tDLLK_MASK) /*! @} */ /*! @name MDMISC - MMDC Core Miscellaneous Register */ /*! @{ */ #define MMDC_MDMISC_RST_MASK (0x2U) #define MMDC_MDMISC_RST_SHIFT (1U) /*! RST * 0b0..Do nothing. * 0b1..Assert reset to the MMDC. */ #define MMDC_MDMISC_RST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_RST_SHIFT)) & MMDC_MDMISC_RST_MASK) #define MMDC_MDMISC_DDR_TYPE_MASK (0x18U) #define MMDC_MDMISC_DDR_TYPE_SHIFT (3U) /*! DDR_TYPE * 0b00..Reserved * 0b01..LPDDR2 device is used. * 0b10..Reserved * 0b11..LPDDR3 device is used. */ #define MMDC_MDMISC_DDR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_DDR_TYPE_SHIFT)) & MMDC_MDMISC_DDR_TYPE_MASK) #define MMDC_MDMISC_DDR_4_BANK_MASK (0x20U) #define MMDC_MDMISC_DDR_4_BANK_SHIFT (5U) /*! DDR_4_BANK * 0b0..8 banks device is being used. (Default) * 0b1..4 banks device is being used */ #define MMDC_MDMISC_DDR_4_BANK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_DDR_4_BANK_SHIFT)) & MMDC_MDMISC_DDR_4_BANK_MASK) #define MMDC_MDMISC_RALAT_MASK (0x1C0U) #define MMDC_MDMISC_RALAT_SHIFT (6U) /*! RALAT * 0b000..no additional latency. * 0b001..1 cycle additional latency. * 0b010..2 cycles additional latency. * 0b011..3 cycles additional latency. * 0b100..4 cycles additional latency. * 0b101..5 cycles additional latency. * 0b110..6 cycles additional latency. * 0b111..7 cycles additional latency. */ #define MMDC_MDMISC_RALAT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_RALAT_SHIFT)) & MMDC_MDMISC_RALAT_MASK) #define MMDC_MDMISC_MIF3_MODE_MASK (0x600U) #define MMDC_MDMISC_MIF3_MODE_SHIFT (9U) /*! MIF3_MODE * 0b00..Disable prediction. * 0b01..Enable prediction based on : Valid access on first pipe line stage. * 0b10..Enable prediction based on: Valid access on first pipe line stage, Valid access on axi bus. * 0b11..Enable prediction based on: Valid access on first pipe line stage, Valid access on axi bus, Next miss access from access queue. */ #define MMDC_MDMISC_MIF3_MODE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_MIF3_MODE_SHIFT)) & MMDC_MDMISC_MIF3_MODE_MASK) #define MMDC_MDMISC_LPDDR2_S2_MASK (0x800U) #define MMDC_MDMISC_LPDDR2_S2_SHIFT (11U) /*! LPDDR2_S2 * 0b0..LPDDR2-S4 device is used. * 0b1..LPDDR2-S2 device is used. */ #define MMDC_MDMISC_LPDDR2_S2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_LPDDR2_S2_SHIFT)) & MMDC_MDMISC_LPDDR2_S2_MASK) #define MMDC_MDMISC_BI_ON_MASK (0x1000U) #define MMDC_MDMISC_BI_ON_SHIFT (12U) /*! BI_ON * 0b0..Banks are not interleaved, and address will be decoded as bank-row-column * 0b1..Banks are interleaved, and address will be decoded as row-bank-column */ #define MMDC_MDMISC_BI_ON(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_BI_ON_SHIFT)) & MMDC_MDMISC_BI_ON_MASK) #define MMDC_MDMISC_WALAT_MASK (0x30000U) #define MMDC_MDMISC_WALAT_SHIFT (16U) /*! WALAT * 0b00..No additional latency required. * 0b01..1 cycle additional delay * 0b10..2 cycles additional delay * 0b11..3 cycles additional delay */ #define MMDC_MDMISC_WALAT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_WALAT_SHIFT)) & MMDC_MDMISC_WALAT_MASK) #define MMDC_MDMISC_LHD_MASK (0x40000U) #define MMDC_MDMISC_LHD_SHIFT (18U) /*! LHD * 0b0..Latency hiding on. * 0b1..Latency hiding disable. */ #define MMDC_MDMISC_LHD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_LHD_SHIFT)) & MMDC_MDMISC_LHD_MASK) #define MMDC_MDMISC_CALIB_PER_CS_MASK (0x100000U) #define MMDC_MDMISC_CALIB_PER_CS_SHIFT (20U) /*! CALIB_PER_CS * 0b0..Calibration is targeted to CS0 * 0b1..Calibration is targeted to CS1 */ #define MMDC_MDMISC_CALIB_PER_CS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CALIB_PER_CS_SHIFT)) & MMDC_MDMISC_CALIB_PER_CS_MASK) #define MMDC_MDMISC_CK1_GATING_MASK (0x200000U) #define MMDC_MDMISC_CK1_GATING_SHIFT (21U) /*! CK1_GATING * 0b0..MMDC drives two clocks toward the DDR memory * 0b1..MMDC drives only one clock toward the DDR memory (CK0) */ #define MMDC_MDMISC_CK1_GATING(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CK1_GATING_SHIFT)) & MMDC_MDMISC_CK1_GATING_MASK) #define MMDC_MDMISC_CS1_RDY_MASK (0x40000000U) #define MMDC_MDMISC_CS1_RDY_SHIFT (30U) /*! CS1_RDY * 0b0..Device in wake-up period. * 0b1..Device is ready for initialization. */ #define MMDC_MDMISC_CS1_RDY(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CS1_RDY_SHIFT)) & MMDC_MDMISC_CS1_RDY_MASK) #define MMDC_MDMISC_CS0_RDY_MASK (0x80000000U) #define MMDC_MDMISC_CS0_RDY_SHIFT (31U) /*! CS0_RDY * 0b0..Device in wake-up period. * 0b1..Device is ready for initialization. */ #define MMDC_MDMISC_CS0_RDY(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CS0_RDY_SHIFT)) & MMDC_MDMISC_CS0_RDY_MASK) /*! @} */ /*! @name MDSCR - MMDC Core Special Command Register */ /*! @{ */ #define MMDC_MDSCR_CMD_BA_MASK (0x7U) #define MMDC_MDSCR_CMD_BA_SHIFT (0U) /*! CMD_BA * 0b000..bank address 0 * 0b001..bank address 1 * 0b010..bank address 2 * 0b111..bank address 7 */ #define MMDC_MDSCR_CMD_BA(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_BA_SHIFT)) & MMDC_MDSCR_CMD_BA_MASK) #define MMDC_MDSCR_CMD_CS_MASK (0x8U) #define MMDC_MDSCR_CMD_CS_SHIFT (3U) /*! CMD_CS * 0b0..to Chip-select 0 * 0b1..to Chip-select 1 */ #define MMDC_MDSCR_CMD_CS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_CS_SHIFT)) & MMDC_MDSCR_CMD_CS_MASK) #define MMDC_MDSCR_CMD_MASK (0x70U) #define MMDC_MDSCR_CMD_SHIFT (4U) /*! CMD * 0b000..Normal operation * 0b001..Precharge all, command is sent independently of bank status (set correct CMD_CS). Will be issued even * if banks are closed. Primarily used for initialization sequence purposes. Not to be used during run-time * operation. * 0b010..Auto-Refresh Command (set correct CMD_CS). * 0b011..Load Mode Register Command (LPDDR2/LPDDR3, set correct CMD_CS, MR_OP, MR_ADDR) * 0b100..ZQ calibration * 0b101..Precharge all, only if banks open (set correct CMD_CS). * 0b110..MRR command (LPDDR2/LPDDR3, set correct CMD_CS, MR_ADDR) * 0b111..Reserved */ #define MMDC_MDSCR_CMD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_SHIFT)) & MMDC_MDSCR_CMD_MASK) #define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK (0x400U) #define MMDC_MDSCR_MRR_READ_DATA_VALID_SHIFT (10U) /*! MRR_READ_DATA_VALID * 0b0..Cleared upon the assertion of MRR command * 0b1..Set after MRR data is valid and stored at MDMRR register. */ #define MMDC_MDSCR_MRR_READ_DATA_VALID(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_MRR_READ_DATA_VALID_SHIFT)) & MMDC_MDSCR_MRR_READ_DATA_VALID_MASK) #define MMDC_MDSCR_CON_ACK_MASK (0x4000U) #define MMDC_MDSCR_CON_ACK_SHIFT (14U) /*! CON_ACK * 0b0..Configuration of MMDC registers is forbidden. * 0b1..Configuration of MMDC registers is permitted. */ #define MMDC_MDSCR_CON_ACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CON_ACK_SHIFT)) & MMDC_MDSCR_CON_ACK_MASK) #define MMDC_MDSCR_CON_REQ_MASK (0x8000U) #define MMDC_MDSCR_CON_REQ_SHIFT (15U) /*! CON_REQ * 0b0..No request to configure MMDC. * 0b1..A request to configure MMDC is valid */ #define MMDC_MDSCR_CON_REQ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CON_REQ_SHIFT)) & MMDC_MDSCR_CON_REQ_MASK) #define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_MASK (0xFF0000U) #define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_SHIFT (16U) #define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_SHIFT)) & MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_MASK) #define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_MASK (0xFF000000U) #define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_SHIFT (24U) #define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_SHIFT)) & MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_MASK) /*! @} */ /*! @name MDREF - MMDC Core Refresh Control Register */ /*! @{ */ #define MMDC_MDREF_START_REF_MASK (0x1U) #define MMDC_MDREF_START_REF_SHIFT (0U) /*! START_REF * 0b0..Do nothing. * 0b1..Start a refresh cycle. */ #define MMDC_MDREF_START_REF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_START_REF_SHIFT)) & MMDC_MDREF_START_REF_MASK) #define MMDC_MDREF_REFR_MASK (0x3800U) #define MMDC_MDREF_REFR_SHIFT (11U) /*! REFR * 0b000..1 refresh * 0b001..2 refreshes * 0b010..3 refreshes * 0b011..4 refreshes * 0b100..5 refreshes * 0b101..6 refreshes * 0b110..7 refreshes * 0b111..8 refreshes */ #define MMDC_MDREF_REFR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_REFR_SHIFT)) & MMDC_MDREF_REFR_MASK) #define MMDC_MDREF_REF_SEL_MASK (0xC000U) #define MMDC_MDREF_REF_SEL_SHIFT (14U) /*! REF_SEL * 0b00..Periodic refresh cycles will be triggered in frequency of 64KHz. * 0b01..Periodic refresh cycles will be triggered in frequency of 32KHz. * 0b10..Periodic refresh cycles will be triggered every amount of cycles that are configured in REF_CNT field. * 0b11..No refresh cycles will be triggered. */ #define MMDC_MDREF_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_REF_SEL_SHIFT)) & MMDC_MDREF_REF_SEL_MASK) #define MMDC_MDREF_REF_CNT_MASK (0xFFFF0000U) #define MMDC_MDREF_REF_CNT_SHIFT (16U) /*! REF_CNT * 0b0000000000000000..Reserved. * 0b0000000000000001..1 cycle. * 0b1111111111111110..65534 cycles. * 0b1111111111111111..65535 cycles. */ #define MMDC_MDREF_REF_CNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_REF_CNT_SHIFT)) & MMDC_MDREF_REF_CNT_MASK) /*! @} */ /*! @name MDRWD - MMDC Core Read/Write Command Delay Register */ /*! @{ */ #define MMDC_MDRWD_RTR_DIFF_MASK (0x7U) #define MMDC_MDRWD_RTR_DIFF_SHIFT (0U) /*! RTR_DIFF * 0b000..0 cycle * 0b001..1 cycle * 0b010..2 cycles (Default) * 0b011..3 cycles * 0b100..4 cycles * 0b101..5 cycles * 0b110..6 cycles * 0b111..7 cycles */ #define MMDC_MDRWD_RTR_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_RTR_DIFF_SHIFT)) & MMDC_MDRWD_RTR_DIFF_MASK) #define MMDC_MDRWD_RTW_DIFF_MASK (0x38U) #define MMDC_MDRWD_RTW_DIFF_SHIFT (3U) /*! RTW_DIFF * 0b000..0 cycle * 0b001..1 cycle * 0b010..2 cycles (Default) * 0b011..3 cycles * 0b100..4 cycles * 0b101..5 cycles * 0b110..6 cycles * 0b111..7 cycles */ #define MMDC_MDRWD_RTW_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_RTW_DIFF_SHIFT)) & MMDC_MDRWD_RTW_DIFF_MASK) #define MMDC_MDRWD_WTW_DIFF_MASK (0x1C0U) #define MMDC_MDRWD_WTW_DIFF_SHIFT (6U) /*! WTW_DIFF * 0b000..0 cycle * 0b001..1 cycle * 0b010..2 cycles * 0b011..3 cycles (Default) * 0b100..4 cycles * 0b101..5 cycles * 0b110..6 cycles * 0b111..7 cycles */ #define MMDC_MDRWD_WTW_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_WTW_DIFF_SHIFT)) & MMDC_MDRWD_WTW_DIFF_MASK) #define MMDC_MDRWD_WTR_DIFF_MASK (0xE00U) #define MMDC_MDRWD_WTR_DIFF_SHIFT (9U) /*! WTR_DIFF * 0b000..0 cycle * 0b001..1 cycle * 0b010..2 cycles * 0b011..3 cycles (Default) * 0b100..4 cycles * 0b101..5 cycles * 0b110..6 cycles * 0b111..7 cycles */ #define MMDC_MDRWD_WTR_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_WTR_DIFF_SHIFT)) & MMDC_MDRWD_WTR_DIFF_MASK) #define MMDC_MDRWD_RTW_SAME_MASK (0x7000U) #define MMDC_MDRWD_RTW_SAME_SHIFT (12U) /*! RTW_SAME * 0b000..0 cycle * 0b001..1 cycle * 0b010..2 cycles (Default) * 0b011..3 cycles * 0b100..4 cycles * 0b101..5 cycles * 0b110..6 cycles * 0b111..7 cycles */ #define MMDC_MDRWD_RTW_SAME(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_RTW_SAME_SHIFT)) & MMDC_MDRWD_RTW_SAME_MASK) #define MMDC_MDRWD_tDAI_MASK (0x1FFF0000U) #define MMDC_MDRWD_tDAI_SHIFT (16U) /*! tDAI * 0b0000000000000..1 cycle * 0b0111110011111..4000 cycles (Default, JEDEC value for LPDDR2, gives 10us at 400MHz clock). * 0b1111111111111..8192 cycles */ #define MMDC_MDRWD_tDAI(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_tDAI_SHIFT)) & MMDC_MDRWD_tDAI_MASK) /*! @} */ /*! @name MDOR - MMDC Core Out of Reset Delays Register */ /*! @{ */ #define MMDC_MDOR_RST_to_CKE_MASK (0x3FU) #define MMDC_MDOR_RST_to_CKE_SHIFT (0U) /*! RST_to_CKE * 0b000000..Reserved * 0b000001..Reserved * 0b000010..Reserved * 0b000011..1 cycles * 0b010000..14 cycles (JEDEC value for LPDDR2) - total of 200 us * 0b100011..33 cycles - total of 500 us * 0b111110..60 cycles * 0b111111..61 cycles */ #define MMDC_MDOR_RST_to_CKE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOR_RST_to_CKE_SHIFT)) & MMDC_MDOR_RST_to_CKE_MASK) #define MMDC_MDOR_SDE_to_RST_MASK (0x3F00U) #define MMDC_MDOR_SDE_to_RST_SHIFT (8U) /*! SDE_to_RST * 0b000000..Reserved * 0b000001..Reserved * 0b000010..Reserved * 0b000011..1 cycles * 0b000100..2 cycles * 0b010000..14 cycles - total of 200 us * 0b111110..60 cycles * 0b111111..61 cycles */ #define MMDC_MDOR_SDE_to_RST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOR_SDE_to_RST_SHIFT)) & MMDC_MDOR_SDE_to_RST_MASK) #define MMDC_MDOR_tXPR_MASK (0xFF0000U) #define MMDC_MDOR_tXPR_SHIFT (16U) /*! tXPR * 0b00000000..Reserved * 0b00000001..2 cycles * 0b00000010..3 cycles * 0b11111110..255 cycles * 0b11111111..256 cycles */ #define MMDC_MDOR_tXPR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOR_tXPR_SHIFT)) & MMDC_MDOR_tXPR_MASK) /*! @} */ /*! @name MDMRR - MMDC Core MRR Data Register */ /*! @{ */ #define MMDC_MDMRR_MRR_READ_DATA0_MASK (0xFFU) #define MMDC_MDMRR_MRR_READ_DATA0_SHIFT (0U) #define MMDC_MDMRR_MRR_READ_DATA0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMRR_MRR_READ_DATA0_SHIFT)) & MMDC_MDMRR_MRR_READ_DATA0_MASK) #define MMDC_MDMRR_MRR_READ_DATA1_MASK (0xFF00U) #define MMDC_MDMRR_MRR_READ_DATA1_SHIFT (8U) #define MMDC_MDMRR_MRR_READ_DATA1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMRR_MRR_READ_DATA1_SHIFT)) & MMDC_MDMRR_MRR_READ_DATA1_MASK) #define MMDC_MDMRR_MRR_READ_DATA2_MASK (0xFF0000U) #define MMDC_MDMRR_MRR_READ_DATA2_SHIFT (16U) #define MMDC_MDMRR_MRR_READ_DATA2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMRR_MRR_READ_DATA2_SHIFT)) & MMDC_MDMRR_MRR_READ_DATA2_MASK) #define MMDC_MDMRR_MRR_READ_DATA3_MASK (0xFF000000U) #define MMDC_MDMRR_MRR_READ_DATA3_SHIFT (24U) #define MMDC_MDMRR_MRR_READ_DATA3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMRR_MRR_READ_DATA3_SHIFT)) & MMDC_MDMRR_MRR_READ_DATA3_MASK) /*! @} */ /*! @name MDCFG3LP - MMDC Core Timing Configuration Register 3 */ /*! @{ */ #define MMDC_MDCFG3LP_tRPab_LP_MASK (0xFU) #define MMDC_MDCFG3LP_tRPab_LP_SHIFT (0U) /*! tRPab_LP * 0b0000..1 clock * 0b0001..2 clocks * 0b0010..3 clocks * 0b1110..15 clocks * 0b1111..Reserved */ #define MMDC_MDCFG3LP_tRPab_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_tRPab_LP_SHIFT)) & MMDC_MDCFG3LP_tRPab_LP_MASK) #define MMDC_MDCFG3LP_tRPpb_LP_MASK (0xF0U) #define MMDC_MDCFG3LP_tRPpb_LP_SHIFT (4U) /*! tRPpb_LP * 0b0000..1 clock * 0b0001..2 clocks * 0b0010..3 clocks * 0b1110..15 clocks * 0b1111..Reserved */ #define MMDC_MDCFG3LP_tRPpb_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_tRPpb_LP_SHIFT)) & MMDC_MDCFG3LP_tRPpb_LP_MASK) #define MMDC_MDCFG3LP_tRCD_LP_MASK (0xF00U) #define MMDC_MDCFG3LP_tRCD_LP_SHIFT (8U) /*! tRCD_LP * 0b0000..1 clock * 0b0001..2 clocks * 0b0010..3 clocks * 0b1110..15 clocks * 0b1111..Reserved */ #define MMDC_MDCFG3LP_tRCD_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_tRCD_LP_SHIFT)) & MMDC_MDCFG3LP_tRCD_LP_MASK) #define MMDC_MDCFG3LP_RC_LP_MASK (0x3F0000U) #define MMDC_MDCFG3LP_RC_LP_SHIFT (16U) /*! RC_LP * 0b000000..1 clock * 0b000001..2 clocks * 0b000010..3 clocks * 0b111110..63 clocks * 0b111111..Reserved */ #define MMDC_MDCFG3LP_RC_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_RC_LP_SHIFT)) & MMDC_MDCFG3LP_RC_LP_MASK) /*! @} */ /*! @name MDMR4 - MMDC Core MR4 Derating Register */ /*! @{ */ #define MMDC_MDMR4_UPDATE_DE_REQ_MASK (0x1U) #define MMDC_MDMR4_UPDATE_DE_REQ_SHIFT (0U) /*! UPDATE_DE_REQ * 0b0..Do nothing. * 0b1..Request to update the following values: tRRD, tRCD, tRP, tRC, tRAS and refresh related fields(MDREF register): REF_CNT, REF_SEL, REFR */ #define MMDC_MDMR4_UPDATE_DE_REQ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_UPDATE_DE_REQ_SHIFT)) & MMDC_MDMR4_UPDATE_DE_REQ_MASK) #define MMDC_MDMR4_UPDATE_DE_ACK_MASK (0x2U) #define MMDC_MDMR4_UPDATE_DE_ACK_SHIFT (1U) #define MMDC_MDMR4_UPDATE_DE_ACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_UPDATE_DE_ACK_SHIFT)) & MMDC_MDMR4_UPDATE_DE_ACK_MASK) #define MMDC_MDMR4_tRCD_DE_MASK (0x10U) #define MMDC_MDMR4_tRCD_DE_SHIFT (4U) /*! tRCD_DE * 0b0..Original tRCD is used. * 0b1..tRCD is derated in 1 cycle. */ #define MMDC_MDMR4_tRCD_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_tRCD_DE_SHIFT)) & MMDC_MDMR4_tRCD_DE_MASK) #define MMDC_MDMR4_tRC_DE_MASK (0x20U) #define MMDC_MDMR4_tRC_DE_SHIFT (5U) /*! tRC_DE * 0b0..Original tRC is used. * 0b1..tRC is derated in 1 cycle. */ #define MMDC_MDMR4_tRC_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_tRC_DE_SHIFT)) & MMDC_MDMR4_tRC_DE_MASK) #define MMDC_MDMR4_tRAS_DE_MASK (0x40U) #define MMDC_MDMR4_tRAS_DE_SHIFT (6U) /*! tRAS_DE * 0b0..Original tRAS is used. * 0b1..tRAS is derated in 1 cycle. */ #define MMDC_MDMR4_tRAS_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_tRAS_DE_SHIFT)) & MMDC_MDMR4_tRAS_DE_MASK) #define MMDC_MDMR4_tRP_DE_MASK (0x80U) #define MMDC_MDMR4_tRP_DE_SHIFT (7U) /*! tRP_DE * 0b0..Original tRP is used. * 0b1..tRP is derated in 1 cycle. */ #define MMDC_MDMR4_tRP_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_tRP_DE_SHIFT)) & MMDC_MDMR4_tRP_DE_MASK) #define MMDC_MDMR4_tRRD_DE_MASK (0x100U) #define MMDC_MDMR4_tRRD_DE_SHIFT (8U) /*! tRRD_DE * 0b0..Original tRRD is used. * 0b1..tRRD is derated in 1 cycle. */ #define MMDC_MDMR4_tRRD_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_tRRD_DE_SHIFT)) & MMDC_MDMR4_tRRD_DE_MASK) /*! @} */ /*! @name MDASP - MMDC Core Address Space Partition Register */ /*! @{ */ #define MMDC_MDASP_CS0_END_MASK (0x7FU) #define MMDC_MDASP_CS0_END_SHIFT (0U) #define MMDC_MDASP_CS0_END(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDASP_CS0_END_SHIFT)) & MMDC_MDASP_CS0_END_MASK) /*! @} */ /*! @name MAARCR - MMDC Core AXI Reordering Control Register */ /*! @{ */ #define MMDC_MAARCR_ARCR_GUARD_MASK (0xFU) #define MMDC_MAARCR_ARCR_GUARD_SHIFT (0U) /*! ARCR_GUARD * 0b0000..15 (default) * 0b0001..16 * 0b1111..30 */ #define MMDC_MAARCR_ARCR_GUARD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_GUARD_SHIFT)) & MMDC_MAARCR_ARCR_GUARD_MASK) #define MMDC_MAARCR_ARCR_DYN_MAX_MASK (0xF0U) #define MMDC_MAARCR_ARCR_DYN_MAX_SHIFT (4U) /*! ARCR_DYN_MAX * 0b0000..0 * 0b0001..1 * 0b1111..15 (default) */ #define MMDC_MAARCR_ARCR_DYN_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_DYN_MAX_SHIFT)) & MMDC_MAARCR_ARCR_DYN_MAX_MASK) #define MMDC_MAARCR_ARCR_DYN_JMP_MASK (0xF00U) #define MMDC_MAARCR_ARCR_DYN_JMP_SHIFT (8U) #define MMDC_MAARCR_ARCR_DYN_JMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_DYN_JMP_SHIFT)) & MMDC_MAARCR_ARCR_DYN_JMP_MASK) #define MMDC_MAARCR_ARCR_ACC_HIT_MASK (0x70000U) #define MMDC_MAARCR_ARCR_ACC_HIT_SHIFT (16U) #define MMDC_MAARCR_ARCR_ACC_HIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_ACC_HIT_SHIFT)) & MMDC_MAARCR_ARCR_ACC_HIT_MASK) #define MMDC_MAARCR_ARCR_PAG_HIT_MASK (0x700000U) #define MMDC_MAARCR_ARCR_PAG_HIT_SHIFT (20U) #define MMDC_MAARCR_ARCR_PAG_HIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_PAG_HIT_SHIFT)) & MMDC_MAARCR_ARCR_PAG_HIT_MASK) #define MMDC_MAARCR_ARCR_RCH_EN_MASK (0x1000000U) #define MMDC_MAARCR_ARCR_RCH_EN_SHIFT (24U) /*! ARCR_RCH_EN * 0b0..normal prioritization, no bypassing * 0b1..accesses with QoS=='F' bypass the arbitration */ #define MMDC_MAARCR_ARCR_RCH_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_RCH_EN_SHIFT)) & MMDC_MAARCR_ARCR_RCH_EN_MASK) #define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK (0x10000000U) #define MMDC_MAARCR_ARCR_EXC_ERR_EN_SHIFT (28U) /*! ARCR_EXC_ERR_EN * 0b0..violation of AXI exclusive rules (6.2.4) result in OKAY response (rresp/bresp=2'b00) * 0b1..violation of AXI exclusive rules (6.2.4) result in SLAVE Error response (rresp/bresp=2'b10) */ #define MMDC_MAARCR_ARCR_EXC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_EXC_ERR_EN_SHIFT)) & MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK) #define MMDC_MAARCR_ARCR_SEC_ERR_EN_MASK (0x40000000U) #define MMDC_MAARCR_ARCR_SEC_ERR_EN_SHIFT (30U) /*! ARCR_SEC_ERR_EN * 0b0..security violation results in OKAY response (rresp/bresp=2'b00) * 0b1..security violation results in SLAVE Error response (rresp/bresp=2'b10) */ #define MMDC_MAARCR_ARCR_SEC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_SEC_ERR_EN_SHIFT)) & MMDC_MAARCR_ARCR_SEC_ERR_EN_MASK) #define MMDC_MAARCR_ARCR_SEC_ERR_LOCK_MASK (0x80000000U) #define MMDC_MAARCR_ARCR_SEC_ERR_LOCK_SHIFT (31U) /*! ARCR_SEC_ERR_LOCK * 0b0..ARCR_SEC_ERR_EN is unlocked, so can be updated any moment * 0b1..ARCR_SEC_ERR_EN is locked, so it can't be updated */ #define MMDC_MAARCR_ARCR_SEC_ERR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_SEC_ERR_LOCK_SHIFT)) & MMDC_MAARCR_ARCR_SEC_ERR_LOCK_MASK) /*! @} */ /*! @name MAPSR - MMDC Core Power Saving Control and Status Register */ /*! @{ */ #define MMDC_MAPSR_PSD_MASK (0x1U) #define MMDC_MAPSR_PSD_SHIFT (0U) /*! PSD * 0b0..power saving enabled * 0b1..power saving disabled (default) */ #define MMDC_MAPSR_PSD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_PSD_SHIFT)) & MMDC_MAPSR_PSD_MASK) #define MMDC_MAPSR_PSS_MASK (0x10U) #define MMDC_MAPSR_PSS_SHIFT (4U) /*! PSS * 0b0..not in power saving mode * 0b1..power saving mode */ #define MMDC_MAPSR_PSS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_PSS_SHIFT)) & MMDC_MAPSR_PSS_MASK) #define MMDC_MAPSR_RIS_MASK (0x20U) #define MMDC_MAPSR_RIS_SHIFT (5U) /*! RIS * 0b0..not idle * 0b1..idle */ #define MMDC_MAPSR_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_RIS_SHIFT)) & MMDC_MAPSR_RIS_MASK) #define MMDC_MAPSR_WIS_MASK (0x40U) #define MMDC_MAPSR_WIS_SHIFT (6U) /*! WIS * 0b0..not idle * 0b1..idle */ #define MMDC_MAPSR_WIS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_WIS_SHIFT)) & MMDC_MAPSR_WIS_MASK) #define MMDC_MAPSR_PST_MASK (0xFF00U) #define MMDC_MAPSR_PST_SHIFT (8U) /*! PST * 0b00000000..Reserved - this value is forbidden. * 0b00000001..timer is configured to 64 clock cycles. * 0b00000010..timer is configured to 128 clock cycles. * 0b00010000..(Default)- 1024 clock cycles. * 0b11111111..timer clock is configured to 16320 clock cycles. */ #define MMDC_MAPSR_PST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_PST_SHIFT)) & MMDC_MAPSR_PST_MASK) #define MMDC_MAPSR_LPMD_MASK (0x100000U) #define MMDC_MAPSR_LPMD_SHIFT (20U) /*! LPMD * 0b0..no lpmd request * 0b1..lpmd request */ #define MMDC_MAPSR_LPMD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_LPMD_SHIFT)) & MMDC_MAPSR_LPMD_MASK) #define MMDC_MAPSR_DVFS_MASK (0x200000U) #define MMDC_MAPSR_DVFS_SHIFT (21U) /*! DVFS * 0b0..no DVFS/Self-Refresh entry request * 0b1..DVFS/Self-Refresh entry request */ #define MMDC_MAPSR_DVFS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_DVFS_SHIFT)) & MMDC_MAPSR_DVFS_MASK) #define MMDC_MAPSR_LPACK_MASK (0x1000000U) #define MMDC_MAPSR_LPACK_SHIFT (24U) #define MMDC_MAPSR_LPACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_LPACK_SHIFT)) & MMDC_MAPSR_LPACK_MASK) #define MMDC_MAPSR_DVACK_MASK (0x2000000U) #define MMDC_MAPSR_DVACK_SHIFT (25U) #define MMDC_MAPSR_DVACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_DVACK_SHIFT)) & MMDC_MAPSR_DVACK_MASK) /*! @} */ /*! @name MAEXIDR0 - MMDC Core Exclusive ID Monitor Register0 */ /*! @{ */ #define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK (0xFFFFU) #define MMDC_MAEXIDR0_EXC_ID_MONITOR0_SHIFT (0U) #define MMDC_MAEXIDR0_EXC_ID_MONITOR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR0_EXC_ID_MONITOR0_SHIFT)) & MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK) #define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK (0xFFFF0000U) #define MMDC_MAEXIDR0_EXC_ID_MONITOR1_SHIFT (16U) #define MMDC_MAEXIDR0_EXC_ID_MONITOR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR0_EXC_ID_MONITOR1_SHIFT)) & MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK) /*! @} */ /*! @name MAEXIDR1 - MMDC Core Exclusive ID Monitor Register1 */ /*! @{ */ #define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK (0xFFFFU) #define MMDC_MAEXIDR1_EXC_ID_MONITOR2_SHIFT (0U) #define MMDC_MAEXIDR1_EXC_ID_MONITOR2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR1_EXC_ID_MONITOR2_SHIFT)) & MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK) #define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK (0xFFFF0000U) #define MMDC_MAEXIDR1_EXC_ID_MONITOR3_SHIFT (16U) #define MMDC_MAEXIDR1_EXC_ID_MONITOR3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR1_EXC_ID_MONITOR3_SHIFT)) & MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK) /*! @} */ /*! @name MADPCR0 - MMDC Core Debug and Profiling Control Register 0 */ /*! @{ */ #define MMDC_MADPCR0_DBG_EN_MASK (0x1U) #define MMDC_MADPCR0_DBG_EN_SHIFT (0U) /*! DBG_EN * 0b0..disable (default) * 0b1..enable */ #define MMDC_MADPCR0_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_DBG_EN_SHIFT)) & MMDC_MADPCR0_DBG_EN_MASK) #define MMDC_MADPCR0_DBG_RST_MASK (0x2U) #define MMDC_MADPCR0_DBG_RST_SHIFT (1U) /*! DBG_RST * 0b0..no reset * 0b1..reset */ #define MMDC_MADPCR0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_DBG_RST_SHIFT)) & MMDC_MADPCR0_DBG_RST_MASK) #define MMDC_MADPCR0_PRF_FRZ_MASK (0x4U) #define MMDC_MADPCR0_PRF_FRZ_SHIFT (2U) /*! PRF_FRZ * 0b0..profiling counters are not frozen * 0b1..profiling counters are frozen */ #define MMDC_MADPCR0_PRF_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_PRF_FRZ_SHIFT)) & MMDC_MADPCR0_PRF_FRZ_MASK) #define MMDC_MADPCR0_CYC_OVF_MASK (0x8U) #define MMDC_MADPCR0_CYC_OVF_SHIFT (3U) /*! CYC_OVF * 0b0..no overflow * 0b1..overflow */ #define MMDC_MADPCR0_CYC_OVF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_CYC_OVF_SHIFT)) & MMDC_MADPCR0_CYC_OVF_MASK) #define MMDC_MADPCR0_SBS_EN_MASK (0x100U) #define MMDC_MADPCR0_SBS_EN_SHIFT (8U) /*! SBS_EN * 0b0..disable * 0b1..enable */ #define MMDC_MADPCR0_SBS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_SBS_EN_SHIFT)) & MMDC_MADPCR0_SBS_EN_MASK) #define MMDC_MADPCR0_SBS_MASK (0x200U) #define MMDC_MADPCR0_SBS_SHIFT (9U) /*! SBS * 0b1..Launch AXI pending access toward the DDR * 0b0..No access will be launched toward the DDR */ #define MMDC_MADPCR0_SBS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_SBS_SHIFT)) & MMDC_MADPCR0_SBS_MASK) /*! @} */ /*! @name MADPCR1 - MMDC Core Debug and Profiling Control Register 1 */ /*! @{ */ #define MMDC_MADPCR1_PRF_AXI_ID_MASK (0xFFFFU) #define MMDC_MADPCR1_PRF_AXI_ID_SHIFT (0U) #define MMDC_MADPCR1_PRF_AXI_ID(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR1_PRF_AXI_ID_SHIFT)) & MMDC_MADPCR1_PRF_AXI_ID_MASK) #define MMDC_MADPCR1_PRF_AXI_IDMASK_MASK (0xFFFF0000U) #define MMDC_MADPCR1_PRF_AXI_IDMASK_SHIFT (16U) /*! PRF_AXI_IDMASK * 0b0000000000000001..AXI ID specific bit is chosen for profiling * 0b0000000000000000..AXI ID specific bit is ignored (don't care) */ #define MMDC_MADPCR1_PRF_AXI_IDMASK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR1_PRF_AXI_IDMASK_SHIFT)) & MMDC_MADPCR1_PRF_AXI_IDMASK_MASK) /*! @} */ /*! @name MADPSR0 - MMDC Core Debug and Profiling Status Register 0 */ /*! @{ */ #define MMDC_MADPSR0_CYC_COUNT_MASK (0xFFFFFFFFU) #define MMDC_MADPSR0_CYC_COUNT_SHIFT (0U) #define MMDC_MADPSR0_CYC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR0_CYC_COUNT_SHIFT)) & MMDC_MADPSR0_CYC_COUNT_MASK) /*! @} */ /*! @name MADPSR1 - MMDC Core Debug and Profiling Status Register 1 */ /*! @{ */ #define MMDC_MADPSR1_BUSY_COUNT_MASK (0xFFFFFFFFU) #define MMDC_MADPSR1_BUSY_COUNT_SHIFT (0U) #define MMDC_MADPSR1_BUSY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR1_BUSY_COUNT_SHIFT)) & MMDC_MADPSR1_BUSY_COUNT_MASK) /*! @} */ /*! @name MADPSR2 - MMDC Core Debug and Profiling Status Register 2 */ /*! @{ */ #define MMDC_MADPSR2_RD_ACC_COUNT_MASK (0xFFFFFFFFU) #define MMDC_MADPSR2_RD_ACC_COUNT_SHIFT (0U) #define MMDC_MADPSR2_RD_ACC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR2_RD_ACC_COUNT_SHIFT)) & MMDC_MADPSR2_RD_ACC_COUNT_MASK) /*! @} */ /*! @name MADPSR3 - MMDC Core Debug and Profiling Status Register 3 */ /*! @{ */ #define MMDC_MADPSR3_WR_ACC_COUNT_MASK (0xFFFFFFFFU) #define MMDC_MADPSR3_WR_ACC_COUNT_SHIFT (0U) #define MMDC_MADPSR3_WR_ACC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR3_WR_ACC_COUNT_SHIFT)) & MMDC_MADPSR3_WR_ACC_COUNT_MASK) /*! @} */ /*! @name MADPSR4 - MMDC Core Debug and Profiling Status Register 4 */ /*! @{ */ #define MMDC_MADPSR4_RD_BYTES_COUNT_MASK (0xFFFFFFFFU) #define MMDC_MADPSR4_RD_BYTES_COUNT_SHIFT (0U) #define MMDC_MADPSR4_RD_BYTES_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR4_RD_BYTES_COUNT_SHIFT)) & MMDC_MADPSR4_RD_BYTES_COUNT_MASK) /*! @} */ /*! @name MADPSR5 - MMDC Core Debug and Profiling Status Register 5 */ /*! @{ */ #define MMDC_MADPSR5_WR_BYTES_COUNT_MASK (0xFFFFFFFFU) #define MMDC_MADPSR5_WR_BYTES_COUNT_SHIFT (0U) #define MMDC_MADPSR5_WR_BYTES_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR5_WR_BYTES_COUNT_SHIFT)) & MMDC_MADPSR5_WR_BYTES_COUNT_MASK) /*! @} */ /*! @name MASBS0 - MMDC Core Step By Step Address Register */ /*! @{ */ #define MMDC_MASBS0_SBS_ADDR_MASK (0xFFFFFFFFU) #define MMDC_MASBS0_SBS_ADDR_SHIFT (0U) #define MMDC_MASBS0_SBS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS0_SBS_ADDR_SHIFT)) & MMDC_MASBS0_SBS_ADDR_MASK) /*! @} */ /*! @name MASBS1 - MMDC Core Step By Step Address Attributes Register */ /*! @{ */ #define MMDC_MASBS1_SBS_VLD_MASK (0x1U) #define MMDC_MASBS1_SBS_VLD_SHIFT (0U) /*! SBS_VLD * 0b0..not valid * 0b1..valid */ #define MMDC_MASBS1_SBS_VLD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_VLD_SHIFT)) & MMDC_MASBS1_SBS_VLD_MASK) #define MMDC_MASBS1_SBS_TYPE_MASK (0x2U) #define MMDC_MASBS1_SBS_TYPE_SHIFT (1U) /*! SBS_TYPE * 0b0..write * 0b1..read */ #define MMDC_MASBS1_SBS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_TYPE_SHIFT)) & MMDC_MASBS1_SBS_TYPE_MASK) #define MMDC_MASBS1_SBS_LOCK_MASK (0xCU) #define MMDC_MASBS1_SBS_LOCK_SHIFT (2U) #define MMDC_MASBS1_SBS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_LOCK_SHIFT)) & MMDC_MASBS1_SBS_LOCK_MASK) #define MMDC_MASBS1_SBS_PROT_MASK (0x70U) #define MMDC_MASBS1_SBS_PROT_SHIFT (4U) #define MMDC_MASBS1_SBS_PROT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_PROT_SHIFT)) & MMDC_MASBS1_SBS_PROT_MASK) #define MMDC_MASBS1_SBS_SIZE_MASK (0x380U) #define MMDC_MASBS1_SBS_SIZE_SHIFT (7U) /*! SBS_SIZE * 0b000..8 bits * 0b001..16 bits * 0b010..32 bits * 0b011..64 bits * 0b100..128bits */ #define MMDC_MASBS1_SBS_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_SIZE_SHIFT)) & MMDC_MASBS1_SBS_SIZE_MASK) #define MMDC_MASBS1_SBS_BURST_MASK (0xC00U) #define MMDC_MASBS1_SBS_BURST_SHIFT (10U) /*! SBS_BURST * 0b00..FIXED * 0b01..INCR burst * 0b10..WRAP burst * 0b11..reserved */ #define MMDC_MASBS1_SBS_BURST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_BURST_SHIFT)) & MMDC_MASBS1_SBS_BURST_MASK) #define MMDC_MASBS1_SBS_BUFF_MASK (0x1000U) #define MMDC_MASBS1_SBS_BUFF_SHIFT (12U) #define MMDC_MASBS1_SBS_BUFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_BUFF_SHIFT)) & MMDC_MASBS1_SBS_BUFF_MASK) #define MMDC_MASBS1_SBS_LEN_MASK (0xE000U) #define MMDC_MASBS1_SBS_LEN_SHIFT (13U) /*! SBS_LEN * 0b000..burst of length 1 * 0b001..burst of length 2 * 0b111..burst of length 8 */ #define MMDC_MASBS1_SBS_LEN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_LEN_SHIFT)) & MMDC_MASBS1_SBS_LEN_MASK) #define MMDC_MASBS1_SBS_AXI_ID_MASK (0xFFFF0000U) #define MMDC_MASBS1_SBS_AXI_ID_SHIFT (16U) #define MMDC_MASBS1_SBS_AXI_ID(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_AXI_ID_SHIFT)) & MMDC_MASBS1_SBS_AXI_ID_MASK) /*! @} */ /*! @name MAGENP - MMDC Core General Purpose Register */ /*! @{ */ #define MMDC_MAGENP_GP31_GP0_MASK (0xFFFFFFFFU) #define MMDC_MAGENP_GP31_GP0_SHIFT (0U) #define MMDC_MAGENP_GP31_GP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAGENP_GP31_GP0_SHIFT)) & MMDC_MAGENP_GP31_GP0_MASK) /*! @} */ /*! @name MPZQHWCTRL - MMDC PHY ZQ HW control register */ /*! @{ */ #define MMDC_MPZQHWCTRL_ZQ_MODE_MASK (0x3U) #define MMDC_MPZQHWCTRL_ZQ_MODE_SHIFT (0U) /*! ZQ_MODE * 0b00..No ZQ calibration is issued. (Default) * 0b01..ZQ calibration is issued to i.MX ZQ calibration pad together with ZQ long command to the external DDR device only when exiting self refresh. * 0b10..ZQ calibration command long/short is issued only to the external DDR device periodically and when exiting self refresh * 0b11..ZQ calibration is issued to i.MX ZQ calibration pad together with ZQ calibration command long/short to * the external DDR device periodically and when exiting self refresh */ #define MMDC_MPZQHWCTRL_ZQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_MODE_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_MODE_MASK) #define MMDC_MPZQHWCTRL_ZQ_HW_PER_MASK (0x3CU) #define MMDC_MPZQHWCTRL_ZQ_HW_PER_SHIFT (2U) /*! ZQ_HW_PER * 0b0000..ZQ calibration is performed every 1 ms. * 0b0001..ZQ calibration is performed every 2 ms. * 0b0010..ZQ calibration is performed every 4 ms. * 0b1010..ZQ calibration is performed every 1 sec. * 0b1110..ZQ calibration is performed every 16 sec. * 0b1111..ZQ calibration is performed every 32 sec. */ #define MMDC_MPZQHWCTRL_ZQ_HW_PER(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_PER_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_PER_MASK) #define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_MASK (0x7C0U) #define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_SHIFT (6U) /*! ZQ_HW_PU_RES * 0b00000..Min. resistance. * 0b11111..Max. resistance. */ #define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_MASK) #define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_MASK (0xF800U) #define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_SHIFT (11U) /*! ZQ_HW_PD_RES * 0b00000..Max. resistance. * 0b11111..Min. resistance. */ #define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_MASK) #define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK (0x10000U) #define MMDC_MPZQHWCTRL_ZQ_HW_FOR_SHIFT (16U) #define MMDC_MPZQHWCTRL_ZQ_HW_FOR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_FOR_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK) #define MMDC_MPZQHWCTRL_TZQ_INIT_MASK (0xE0000U) #define MMDC_MPZQHWCTRL_TZQ_INIT_SHIFT (17U) /*! TZQ_INIT * 0b000..Reserved * 0b001..Reserved * 0b010..128 cycles * 0b011..256 cycles * 0b100..512 cycles - Default * 0b101..1024 cycles */ #define MMDC_MPZQHWCTRL_TZQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_TZQ_INIT_SHIFT)) & MMDC_MPZQHWCTRL_TZQ_INIT_MASK) #define MMDC_MPZQHWCTRL_TZQ_OPER_MASK (0x700000U) #define MMDC_MPZQHWCTRL_TZQ_OPER_SHIFT (20U) /*! TZQ_OPER * 0b000..Reserved * 0b001..Reserved * 0b010..128 cycles * 0b011..256 cycles - Default * 0b100..512 cycles * 0b101..1024 cycles */ #define MMDC_MPZQHWCTRL_TZQ_OPER(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_TZQ_OPER_SHIFT)) & MMDC_MPZQHWCTRL_TZQ_OPER_MASK) #define MMDC_MPZQHWCTRL_TZQ_CS_MASK (0x3800000U) #define MMDC_MPZQHWCTRL_TZQ_CS_SHIFT (23U) /*! TZQ_CS * 0b000..Reserved * 0b001..Reserved * 0b010..128 cycles (Default) * 0b011..256 cycles * 0b100..512 cycles * 0b101..1024 cycles */ #define MMDC_MPZQHWCTRL_TZQ_CS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_TZQ_CS_SHIFT)) & MMDC_MPZQHWCTRL_TZQ_CS_MASK) #define MMDC_MPZQHWCTRL_ZQ_PARA_EN_MASK (0x4000000U) #define MMDC_MPZQHWCTRL_ZQ_PARA_EN_SHIFT (26U) /*! ZQ_PARA_EN * 0b0..Device ZQ calibration is done in serial (CS0 first and then CS1). * 0b1..ZQ calibration of both CS is done in parallel */ #define MMDC_MPZQHWCTRL_ZQ_PARA_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_PARA_EN_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_PARA_EN_MASK) #define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_MASK (0xF8000000U) #define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_SHIFT (27U) /*! ZQ_EARLY_COMPARATOR_EN_TIMER * 0b00000..- 0x6 Reserved * 0b00111..8 cycles * 0b10100..21 cycles (Default) * 0b11110..31 cycles * 0b11111..32 cycles */ #define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_MASK) /*! @} */ /*! @name MPZQSWCTRL - MMDC PHY ZQ SW control register */ /*! @{ */ #define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK (0x1U) #define MMDC_MPZQSWCTRL_ZQ_SW_FOR_SHIFT (0U) #define MMDC_MPZQSWCTRL_ZQ_SW_FOR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_FOR_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK) #define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK (0x2U) #define MMDC_MPZQSWCTRL_ZQ_SW_RES_SHIFT (1U) /*! ZQ_SW_RES * 0b0..Current ZQ calibration voltage is less than VDD/2. * 0b1..Current ZQ calibration voltage is more than VDD/2 */ #define MMDC_MPZQSWCTRL_ZQ_SW_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_RES_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK) #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK (0x7CU) #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_SHIFT (2U) /*! ZQ_SW_PU_VAL * 0b00000..Min. resistance. * 0b11111..Max. resistance. */ #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK) #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK (0xF80U) #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_SHIFT (7U) /*! ZQ_SW_PD_VAL * 0b00000..Max. resistance. * 0b11111..Min. resistance. */ #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK) #define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK (0x1000U) #define MMDC_MPZQSWCTRL_ZQ_SW_PD_SHIFT (12U) /*! ZQ_SW_PD * 0b0..PU resistor calibration * 0b1..PD resistor calibration */ #define MMDC_MPZQSWCTRL_ZQ_SW_PD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_PD_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK) #define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK (0x2000U) #define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_SHIFT (13U) /*! USE_ZQ_SW_VAL * 0b0..Fields ZQ_HW_PD_VAL & ZQ_HW_PU_VAL will be driven to I/O pads resistor controls. * 0b1..Fields ZQ_SW_PD_VAL & ZQ_SW_PU_VAL will be driven to I/O pads resistor controls. */ #define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_SHIFT)) & MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK) #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK (0x30000U) #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_SHIFT (16U) /*! ZQ_CMP_OUT_SMP * 0b00..7 cycles * 0b01..15 cycles * 0b10..23 cycles * 0b11..31 cycles */ #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK) /*! @} */ /*! @name MPRDDQBY0DL - MMDC PHY Read DQ Byte0 Delay Register */ /*! @{ */ #define MMDC_MPRDDQBY0DL_rd_dq0_del_MASK (0x7U) #define MMDC_MPRDDQBY0DL_rd_dq0_del_SHIFT (0U) /*! rd_dq0_del * 0b000..No change in dq0 delay * 0b001..Add dq0 delay of 1 delay unit * 0b010..Add dq0 delay of 2 delay units. * 0b011..Add dq0 delay of 3 delay units. * 0b100..Add dq0 delay of 4 delay units. * 0b101..Add dq0 delay of 5 delay units. * 0b110..Add dq0 delay of 6 delay units. * 0b111..Add dq0 delay of 7 delay units. */ #define MMDC_MPRDDQBY0DL_rd_dq0_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_rd_dq0_del_SHIFT)) & MMDC_MPRDDQBY0DL_rd_dq0_del_MASK) #define MMDC_MPRDDQBY0DL_rd_dq1_del_MASK (0x70U) #define MMDC_MPRDDQBY0DL_rd_dq1_del_SHIFT (4U) /*! rd_dq1_del * 0b000..No change in dq1 delay * 0b001..Add dq1 delay of 1 delay unit * 0b010..Add dq1 delay of 2 delay units. * 0b011..Add dq1 delay of 3 delay units. * 0b100..Add dq1 delay of 4 delay units. * 0b101..Add dq1 delay of 5 delay units. * 0b110..Add dq1 delay of 6 delay units. * 0b111..Add dq1 delay of 7 delay units. */ #define MMDC_MPRDDQBY0DL_rd_dq1_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_rd_dq1_del_SHIFT)) & MMDC_MPRDDQBY0DL_rd_dq1_del_MASK) #define MMDC_MPRDDQBY0DL_rd_dq2_del_MASK (0x700U) #define MMDC_MPRDDQBY0DL_rd_dq2_del_SHIFT (8U) /*! rd_dq2_del * 0b000..No change in dq2 delay * 0b001..Add dq2 delay of 1 delay unit * 0b010..Add dq2 delay of 2 delay units. * 0b011..Add dq2 delay of 3 delay units. * 0b100..Add dq2 delay of 4 delay units. * 0b101..Add dq2 delay of 5 delay units. * 0b110..Add dq2 delay of 6 delay units. * 0b111..Add dq2 delay of 7 delay units. */ #define MMDC_MPRDDQBY0DL_rd_dq2_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_rd_dq2_del_SHIFT)) & MMDC_MPRDDQBY0DL_rd_dq2_del_MASK) #define MMDC_MPRDDQBY0DL_rd_dq3_del_MASK (0x7000U) #define MMDC_MPRDDQBY0DL_rd_dq3_del_SHIFT (12U) /*! rd_dq3_del * 0b000..No change in dq3 delay * 0b001..Add dq3 delay of 1 delay unit * 0b010..Add dq3 delay of 2 delay units. * 0b011..Add dq3 delay of 3 delay units. * 0b100..Add dq3 delay of 4 delay units. * 0b101..Add dq3 delay of 5 delay units. * 0b110..Add dq3 delay of 6 delay units. * 0b111..Add dq3 delay of 7 delay units. */ #define MMDC_MPRDDQBY0DL_rd_dq3_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_rd_dq3_del_SHIFT)) & MMDC_MPRDDQBY0DL_rd_dq3_del_MASK) #define MMDC_MPRDDQBY0DL_rd_dq4_del_MASK (0x70000U) #define MMDC_MPRDDQBY0DL_rd_dq4_del_SHIFT (16U) /*! rd_dq4_del * 0b000..No change in dq4 delay * 0b001..Add dq4 delay of 1 delay unit * 0b010..Add dq4 delay of 2 delay units. * 0b011..Add dq4 delay of 3 delay units. * 0b100..Add dq4 delay of 4 delay units. * 0b101..Add dq4 delay of 5 delay units. * 0b110..Add dq4 delay of 6 delay units. * 0b111..Add dq4 delay of 7 delay units. */ #define MMDC_MPRDDQBY0DL_rd_dq4_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_rd_dq4_del_SHIFT)) & MMDC_MPRDDQBY0DL_rd_dq4_del_MASK) #define MMDC_MPRDDQBY0DL_rd_dq5_del_MASK (0x700000U) #define MMDC_MPRDDQBY0DL_rd_dq5_del_SHIFT (20U) /*! rd_dq5_del * 0b000..No change in dq5 delay * 0b001..Add dq5 delay of 1 delay unit * 0b010..Add dq5 delay of 2 delay units. * 0b011..Add dq5 delay of 3 delay units. * 0b100..Add dq5 delay of 4 delay units. * 0b101..Add dq5 delay of 5 delay units. * 0b110..Add dq5 delay of 6 delay units. * 0b111..Add dq5 delay of 7 delay units. */ #define MMDC_MPRDDQBY0DL_rd_dq5_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_rd_dq5_del_SHIFT)) & MMDC_MPRDDQBY0DL_rd_dq5_del_MASK) #define MMDC_MPRDDQBY0DL_rd_dq6_del_MASK (0x7000000U) #define MMDC_MPRDDQBY0DL_rd_dq6_del_SHIFT (24U) /*! rd_dq6_del * 0b000..No change in dq6 delay * 0b001..Add dq6 delay of 1 delay unit * 0b010..Add dq6 delay of 2 delay units. * 0b011..Add dq6 delay of 3 delay units. * 0b100..Add dq6 delay of 4 delay units. * 0b101..Add dq6 delay of 5 delay units. * 0b110..Add dq6 delay of 6 delay units. * 0b111..Add dq6 delay of 7 delay units. */ #define MMDC_MPRDDQBY0DL_rd_dq6_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_rd_dq6_del_SHIFT)) & MMDC_MPRDDQBY0DL_rd_dq6_del_MASK) #define MMDC_MPRDDQBY0DL_rd_dq7_del_MASK (0x70000000U) #define MMDC_MPRDDQBY0DL_rd_dq7_del_SHIFT (28U) /*! rd_dq7_del * 0b000..No change in dq7 delay * 0b001..Add dq7 delay of 1 delay unit * 0b010..Add dq7 delay of 2 delay units. * 0b011..Add dq7 delay of 3 delay units. * 0b100..Add dq7 delay of 4 delay units. * 0b101..Add dq7 delay of 5 delay units. * 0b110..Add dq7 delay of 6 delay units. * 0b111..Add dq7 delay of 7 delay units. */ #define MMDC_MPRDDQBY0DL_rd_dq7_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_rd_dq7_del_SHIFT)) & MMDC_MPRDDQBY0DL_rd_dq7_del_MASK) /*! @} */ /*! @name MPRDDQBY1DL - MMDC PHY Read DQ Byte1 Delay Register */ /*! @{ */ #define MMDC_MPRDDQBY1DL_rd_dq8_del_MASK (0x7U) #define MMDC_MPRDDQBY1DL_rd_dq8_del_SHIFT (0U) /*! rd_dq8_del * 0b000..No change in dq8 delay * 0b001..Add dq8 delay of 1 delay unit * 0b010..Add dq8 delay of 2 delay units. * 0b011..Add dq8 delay of 3 delay units. * 0b100..Add dq8 delay of 4 delay units. * 0b101..Add dq8 delay of 5 delay units. * 0b110..Add dq8 delay of 6 delay units. * 0b111..Add dq8 delay of 7 delay units. */ #define MMDC_MPRDDQBY1DL_rd_dq8_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_rd_dq8_del_SHIFT)) & MMDC_MPRDDQBY1DL_rd_dq8_del_MASK) #define MMDC_MPRDDQBY1DL_rd_dq9_del_MASK (0x70U) #define MMDC_MPRDDQBY1DL_rd_dq9_del_SHIFT (4U) /*! rd_dq9_del * 0b000..No change in dq9 delay * 0b001..Add dq9 delay of 1 delay unit * 0b010..Add dq9 delay of 2 delay units. * 0b011..Add dq9 delay of 3 delay units. * 0b100..Add dq9 delay of 4 delay units. * 0b101..Add dq9 delay of 5 delay units. * 0b110..Add dq9 delay of 6 delay units. * 0b111..Add dq9 delay of 7 delay units. */ #define MMDC_MPRDDQBY1DL_rd_dq9_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_rd_dq9_del_SHIFT)) & MMDC_MPRDDQBY1DL_rd_dq9_del_MASK) #define MMDC_MPRDDQBY1DL_rd_dq10_del_MASK (0x700U) #define MMDC_MPRDDQBY1DL_rd_dq10_del_SHIFT (8U) /*! rd_dq10_del * 0b000..No change in dq10 delay * 0b001..Add dq10 delay of 1 delay unit * 0b010..Add dq10 delay of 2 delay units. * 0b011..Add dq10 delay of 3 delay units. * 0b100..Add dq10 delay of 4 delay units. * 0b101..Add dq10 delay of 5 delay unit * 0b110..Add dq10 delay of 6 delay units. * 0b111..Add dq10 delay of 7 delay units. */ #define MMDC_MPRDDQBY1DL_rd_dq10_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_rd_dq10_del_SHIFT)) & MMDC_MPRDDQBY1DL_rd_dq10_del_MASK) #define MMDC_MPRDDQBY1DL_rd_dq11_del_MASK (0x7000U) #define MMDC_MPRDDQBY1DL_rd_dq11_del_SHIFT (12U) /*! rd_dq11_del * 0b000..No change in dq11 delay * 0b001..Add dq11 delay of 1 delay unit * 0b010..Add dq11 delay of 2 delay units. * 0b011..Add dq11 delay of 3 delay units. * 0b100..Add dq11 delay of 4 delay units. * 0b101..Add dq11 delay of 5 delay units. * 0b110..Add dq11 delay of 6 delay units. * 0b111..Add dq11 delay of 7 delay units. */ #define MMDC_MPRDDQBY1DL_rd_dq11_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_rd_dq11_del_SHIFT)) & MMDC_MPRDDQBY1DL_rd_dq11_del_MASK) #define MMDC_MPRDDQBY1DL_rd_dq12_del_MASK (0x70000U) #define MMDC_MPRDDQBY1DL_rd_dq12_del_SHIFT (16U) /*! rd_dq12_del * 0b000..No change in dq12 delay * 0b001..Add dq12 delay of 1 delay unit * 0b010..Add dq12 delay of 2 delay units. * 0b011..Add dq12 delay of 3 delay units. * 0b100..Add dq12 delay of 4 delay units. * 0b101..Add dq12 delay of 5 delay units. * 0b110..Add dq12 delay of 6 delay units. * 0b111..Add dq12 delay of 7 delay units. */ #define MMDC_MPRDDQBY1DL_rd_dq12_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_rd_dq12_del_SHIFT)) & MMDC_MPRDDQBY1DL_rd_dq12_del_MASK) #define MMDC_MPRDDQBY1DL_rd_dq13_del_MASK (0x700000U) #define MMDC_MPRDDQBY1DL_rd_dq13_del_SHIFT (20U) /*! rd_dq13_del * 0b000..No change in dq13 delay * 0b001..Add dq13 delay of 1 delay unit * 0b010..Add dq13 delay of 2 delay units. * 0b011..Add dq13 delay of 3 delay units. * 0b100..Add dq13 delay of 4 delay units. * 0b101..Add dq13 delay of 5 delay units. * 0b110..Add dq13 delay of 6 delay units. * 0b111..Add dq13 delay of 7 delay units. */ #define MMDC_MPRDDQBY1DL_rd_dq13_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_rd_dq13_del_SHIFT)) & MMDC_MPRDDQBY1DL_rd_dq13_del_MASK) #define MMDC_MPRDDQBY1DL_rd_dq14_del_MASK (0x7000000U) #define MMDC_MPRDDQBY1DL_rd_dq14_del_SHIFT (24U) /*! rd_dq14_del * 0b000..No change in dq14 delay * 0b001..Add dq14 delay of 1 delay unit * 0b010..Add dq14 delay of 2 delay units. * 0b011..Add dq14 delay of 3 delay units. * 0b100..Add dq14 delay of 4 delay units. * 0b101..Add dq14 delay of 5 delay units. * 0b110..Add dq14 delay of 6 delay units. * 0b111..Add dq14 delay of 7 delay units. */ #define MMDC_MPRDDQBY1DL_rd_dq14_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_rd_dq14_del_SHIFT)) & MMDC_MPRDDQBY1DL_rd_dq14_del_MASK) #define MMDC_MPRDDQBY1DL_rd_dq15_del_MASK (0x70000000U) #define MMDC_MPRDDQBY1DL_rd_dq15_del_SHIFT (28U) /*! rd_dq15_del * 0b000..No change in dq15 delay * 0b001..Add dq15 delay of 1 delay unit * 0b010..Add dq15 delay of 2 delay units. * 0b011..Add dq15 delay of 3 delay units. * 0b100..Add dq15 delay of 4 delay units. * 0b101..Add dq15 delay of 5 delay units. * 0b110..Add dq15 delay of 6 delay units. * 0b111..Add dq15 delay of 7 delay units. */ #define MMDC_MPRDDQBY1DL_rd_dq15_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_rd_dq15_del_SHIFT)) & MMDC_MPRDDQBY1DL_rd_dq15_del_MASK) /*! @} */ /*! @name MPRDDQBY2DL - MMDC PHY Read DQ Byte2 Delay Register */ /*! @{ */ #define MMDC_MPRDDQBY2DL_rd_dq16_del_MASK (0x7U) #define MMDC_MPRDDQBY2DL_rd_dq16_del_SHIFT (0U) /*! rd_dq16_del * 0b000..No change in dq16 delay * 0b001..Add dq16 delay of 1 delay unit * 0b010..Add dq16 delay of 2 delay units. * 0b011..Add dq16 delay of 3 delay units. * 0b100..Add dq16 delay of 4 delay units. * 0b101..Add dq16 delay of 5 delay units. * 0b110..Add dq16 delay of 6 delay units. * 0b111..Add dq16 delay of 7 delay units. */ #define MMDC_MPRDDQBY2DL_rd_dq16_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY2DL_rd_dq16_del_SHIFT)) & MMDC_MPRDDQBY2DL_rd_dq16_del_MASK) #define MMDC_MPRDDQBY2DL_rd_dq17_del_MASK (0x70U) #define MMDC_MPRDDQBY2DL_rd_dq17_del_SHIFT (4U) /*! rd_dq17_del * 0b000..No change in dq17 delay * 0b001..Add dq17 delay of 1 delay unit * 0b010..Add dq17 delay of 2 delay units. * 0b011..Add dq17 delay of 3 delay units. * 0b100..Add dq17 delay of 4 delay units. * 0b101..Add dq17 delay of 5 delay units. * 0b110..Add dq17 delay of 6 delay units. * 0b111..Add dq17 delay of 7 delay units. */ #define MMDC_MPRDDQBY2DL_rd_dq17_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY2DL_rd_dq17_del_SHIFT)) & MMDC_MPRDDQBY2DL_rd_dq17_del_MASK) #define MMDC_MPRDDQBY2DL_rd_dq18_del_MASK (0x700U) #define MMDC_MPRDDQBY2DL_rd_dq18_del_SHIFT (8U) /*! rd_dq18_del * 0b000..No change in dq18 delay * 0b001..Add dq18 delay of 1 delay unit * 0b010..Add dq18 delay of 2 delay units. * 0b011..Add dq18 delay of 3 delay units. * 0b100..Add dq18 delay of 4 delay units. * 0b101..Add dq18 delay of 5 delay units. * 0b110..Add dq18 delay of 6 delay units. * 0b111..Add dq18 delay of 7 delay units. */ #define MMDC_MPRDDQBY2DL_rd_dq18_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY2DL_rd_dq18_del_SHIFT)) & MMDC_MPRDDQBY2DL_rd_dq18_del_MASK) #define MMDC_MPRDDQBY2DL_rd_dq19_del_MASK (0x7000U) #define MMDC_MPRDDQBY2DL_rd_dq19_del_SHIFT (12U) /*! rd_dq19_del * 0b000..No change in dq19 delay * 0b001..Add dq19 delay of 1 delay unit * 0b010..Add dq19 delay of 2 delay units. * 0b011..Add dq19 delay of 3 delay units. * 0b100..Add dq19 delay of 4 delay units. * 0b101..Add dq19 delay of 5 delay units. * 0b110..Add dq19 delay of 6 delay units. * 0b111..Add dq19 delay of 7 delay units. */ #define MMDC_MPRDDQBY2DL_rd_dq19_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY2DL_rd_dq19_del_SHIFT)) & MMDC_MPRDDQBY2DL_rd_dq19_del_MASK) #define MMDC_MPRDDQBY2DL_rd_dq20_del_MASK (0x70000U) #define MMDC_MPRDDQBY2DL_rd_dq20_del_SHIFT (16U) /*! rd_dq20_del * 0b000..No change in dq20 delay * 0b001..Add dq20 delay of 1 delay unit * 0b010..Add dq20 delay of 2 delay units. * 0b011..Add dq20 delay of 3 delay units. * 0b100..Add dq20 delay of 4 delay units. * 0b101..Add dq20 delay of 5 delay units. * 0b110..Add dq20 delay of 6 delay units. * 0b111..Add dq20 delay of 7 delay units. */ #define MMDC_MPRDDQBY2DL_rd_dq20_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY2DL_rd_dq20_del_SHIFT)) & MMDC_MPRDDQBY2DL_rd_dq20_del_MASK) #define MMDC_MPRDDQBY2DL_rd_dq21_del_MASK (0x700000U) #define MMDC_MPRDDQBY2DL_rd_dq21_del_SHIFT (20U) /*! rd_dq21_del * 0b000..No change in dq21 delay * 0b001..Add dq21 delay of 1 delay unit * 0b010..Add dq21 delay of 2 delay units. * 0b011..Add dq21 delay of 3 delay units. * 0b100..Add dq21 delay of 4 delay units. * 0b101..Add dq21 delay of 5 delay units. * 0b110..Add dq21 delay of 6 delay units. * 0b111..Add dq21 delay of 7 delay units. */ #define MMDC_MPRDDQBY2DL_rd_dq21_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY2DL_rd_dq21_del_SHIFT)) & MMDC_MPRDDQBY2DL_rd_dq21_del_MASK) #define MMDC_MPRDDQBY2DL_rd_dq22_del_MASK (0x7000000U) #define MMDC_MPRDDQBY2DL_rd_dq22_del_SHIFT (24U) /*! rd_dq22_del * 0b000..No change in dq22 delay * 0b001..Add dq22 delay of 1 delay unit * 0b010..Add dq22 delay of 2 delay units. * 0b011..Add dq22 delay of 3 delay units. * 0b100..Add dq22 delay of 4 delay units. * 0b101..Add dq22 delay of 5 delay units. * 0b110..Add dq22 delay of 6 delay units. * 0b111..Add dq22 delay of 7 delay units. */ #define MMDC_MPRDDQBY2DL_rd_dq22_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY2DL_rd_dq22_del_SHIFT)) & MMDC_MPRDDQBY2DL_rd_dq22_del_MASK) #define MMDC_MPRDDQBY2DL_rd_dq23_del_MASK (0x70000000U) #define MMDC_MPRDDQBY2DL_rd_dq23_del_SHIFT (28U) /*! rd_dq23_del * 0b000..No change in dq23 delay * 0b001..Add dq23 delay of 1 delay unit * 0b010..Add dq23 delay of 2 delay units. * 0b011..Add dq23 delay of 3 delay units. * 0b100..Add dq23 delay of 4 delay units. * 0b101..Add dq23 delay of 5 delay units. * 0b110..Add dq23 delay of 6 delay units. * 0b111..Add dq23 delay of 7 delay units. */ #define MMDC_MPRDDQBY2DL_rd_dq23_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY2DL_rd_dq23_del_SHIFT)) & MMDC_MPRDDQBY2DL_rd_dq23_del_MASK) /*! @} */ /*! @name MPRDDQBY3DL - MMDC PHY Read DQ Byte3 Delay Register */ /*! @{ */ #define MMDC_MPRDDQBY3DL_rd_dq24_del_MASK (0x7U) #define MMDC_MPRDDQBY3DL_rd_dq24_del_SHIFT (0U) /*! rd_dq24_del * 0b000..No change in dq24 delay * 0b001..Add dq24 delay of 1 delay unit * 0b010..Add dq24 delay of 2 delay units. * 0b011..Add dq24 delay of 3 delay units. * 0b100..Add dq24 delay of 4 delay units. * 0b101..Add dq24 delay of 5 delay units. * 0b110..Add dq24 delay of 6 delay units. * 0b111..Add dq24 delay of 7 delay units. */ #define MMDC_MPRDDQBY3DL_rd_dq24_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY3DL_rd_dq24_del_SHIFT)) & MMDC_MPRDDQBY3DL_rd_dq24_del_MASK) #define MMDC_MPRDDQBY3DL_rd_dq25_del_MASK (0x70U) #define MMDC_MPRDDQBY3DL_rd_dq25_del_SHIFT (4U) /*! rd_dq25_del * 0b000..No change in dq25 delay * 0b001..Add dq25 delay of 1 delay unit * 0b010..Add dq25 delay of 2 delay units. * 0b011..Add dq25 delay of 3 delay units. * 0b100..Add dq25 delay of 4 delay units. * 0b101..Add dq25 delay of 5 delay units. * 0b110..Add dq25 delay of 6 delay units. * 0b111..Add dq25 delay of 7 delay units. */ #define MMDC_MPRDDQBY3DL_rd_dq25_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY3DL_rd_dq25_del_SHIFT)) & MMDC_MPRDDQBY3DL_rd_dq25_del_MASK) #define MMDC_MPRDDQBY3DL_rd_dq26_del_MASK (0x700U) #define MMDC_MPRDDQBY3DL_rd_dq26_del_SHIFT (8U) /*! rd_dq26_del * 0b000..No change in dq26 delay * 0b001..Add dq26 delay of 1 delay unit * 0b010..Add dq26 delay of 2 delay units. * 0b011..Add dq26 delay of 3 delay units. * 0b100..Add dq26 delay of 4 delay units. * 0b101..Add dq26 delay of 5 delay units. * 0b110..Add dq26 delay of 6 delay units. * 0b111..Add dq26 delay of 7 delay units. */ #define MMDC_MPRDDQBY3DL_rd_dq26_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY3DL_rd_dq26_del_SHIFT)) & MMDC_MPRDDQBY3DL_rd_dq26_del_MASK) #define MMDC_MPRDDQBY3DL_rd_dq27_del_MASK (0x7000U) #define MMDC_MPRDDQBY3DL_rd_dq27_del_SHIFT (12U) /*! rd_dq27_del * 0b000..No change in dq27 delay * 0b001..Add dq27 delay of 1 delay unit * 0b010..Add dq27 delay of 2 delay units. * 0b011..Add dq27 delay of 3 delay units. * 0b100..Add dq27 delay of 4 delay units. * 0b101..Add dq27 delay of 5 delay units. * 0b110..Add dq27 delay of 6 delay units. * 0b111..Add dq27 delay of 7 delay units. */ #define MMDC_MPRDDQBY3DL_rd_dq27_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY3DL_rd_dq27_del_SHIFT)) & MMDC_MPRDDQBY3DL_rd_dq27_del_MASK) #define MMDC_MPRDDQBY3DL_rd_dq28_del_MASK (0x70000U) #define MMDC_MPRDDQBY3DL_rd_dq28_del_SHIFT (16U) /*! rd_dq28_del * 0b000..No change in dq28 delay * 0b001..Add dq28 delay of 1 delay unit * 0b010..Add dq28 delay of 2 delay units. * 0b011..Add dq28 delay of 3 delay units. * 0b100..Add dq28 delay of 4 delay units. * 0b101..Add dq28 delay of 5 delay units. * 0b110..Add dq28 delay of 6 delay units. * 0b111..Add dq28 delay of 7 delay units. */ #define MMDC_MPRDDQBY3DL_rd_dq28_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY3DL_rd_dq28_del_SHIFT)) & MMDC_MPRDDQBY3DL_rd_dq28_del_MASK) #define MMDC_MPRDDQBY3DL_rd_dq29_del_MASK (0x700000U) #define MMDC_MPRDDQBY3DL_rd_dq29_del_SHIFT (20U) /*! rd_dq29_del * 0b000..No change in dq29 delay * 0b001..Add dq29 delay of 1 delay unit * 0b010..Add dq29 delay of 2 delay units. * 0b011..Add dq29 delay of 3 delay units. * 0b100..Add dq29 delay of 4 delay units. * 0b101..Add dq29 delay of 5 delay units. * 0b110..Add dq29 delay of 6 delay units. * 0b111..Add dq29 delay of 7 delay units. */ #define MMDC_MPRDDQBY3DL_rd_dq29_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY3DL_rd_dq29_del_SHIFT)) & MMDC_MPRDDQBY3DL_rd_dq29_del_MASK) #define MMDC_MPRDDQBY3DL_rd_dq30_del_MASK (0x7000000U) #define MMDC_MPRDDQBY3DL_rd_dq30_del_SHIFT (24U) /*! rd_dq30_del * 0b000..No change in dq30 delay * 0b001..Add dq30 delay of 1 delay unit * 0b010..Add dq30 delay of 2 delay units. * 0b011..Add dq30 delay of 3 delay units. * 0b100..Add dq30 delay of 4 delay units. * 0b101..Add dq30 delay of 5 delay units. * 0b110..Add dq30 delay of 6 delay units. * 0b111..Add dq30 delay of 7 delay units. */ #define MMDC_MPRDDQBY3DL_rd_dq30_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY3DL_rd_dq30_del_SHIFT)) & MMDC_MPRDDQBY3DL_rd_dq30_del_MASK) #define MMDC_MPRDDQBY3DL_rd_dq31_del_MASK (0x70000000U) #define MMDC_MPRDDQBY3DL_rd_dq31_del_SHIFT (28U) /*! rd_dq31_del * 0b000..No change in dq31 delay * 0b001..Add dq31 delay of 1 delay unit * 0b010..Add dq31 delay of 2 delay units. * 0b011..Add dq31 delay of 3 delay units. * 0b100..Add dq31 delay of 4 delay units. * 0b101..Add dq31 delay of 5 delay units. * 0b110..Add dq31 delay of 6 delay units. * 0b111..Add dq31 delay of 7 delay units. */ #define MMDC_MPRDDQBY3DL_rd_dq31_del(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY3DL_rd_dq31_del_SHIFT)) & MMDC_MPRDDQBY3DL_rd_dq31_del_MASK) /*! @} */ /*! @name MPDGCTRL0 - MMDC PHY Read DQS Gating Control Register 0 */ /*! @{ */ #define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK (0x80000000U) #define MMDC_MPDGCTRL0_RST_RD_FIFO_SHIFT (31U) #define MMDC_MPDGCTRL0_RST_RD_FIFO(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_RST_RD_FIFO_SHIFT)) & MMDC_MPDGCTRL0_RST_RD_FIFO_MASK) /*! @} */ /*! @name MPRDDLCTL - MMDC PHY Read delay-lines Configuration Register */ /*! @{ */ #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK (0x7FU) #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_SHIFT (0U) #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_SHIFT)) & MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK) #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK (0x7F00U) #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_SHIFT (8U) #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_SHIFT)) & MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK) #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK (0x7F0000U) #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_SHIFT (16U) #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_SHIFT)) & MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK) #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK (0x7F000000U) #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_SHIFT (24U) #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_SHIFT)) & MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK) /*! @} */ /*! @name MPRDDLST - MMDC PHY Read delay-lines Status Register */ /*! @{ */ #define MMDC_MPRDDLST_RD_DL_UNIT_NUM0_MASK (0x7FU) #define MMDC_MPRDDLST_RD_DL_UNIT_NUM0_SHIFT (0U) #define MMDC_MPRDDLST_RD_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLST_RD_DL_UNIT_NUM0_SHIFT)) & MMDC_MPRDDLST_RD_DL_UNIT_NUM0_MASK) #define MMDC_MPRDDLST_RD_DL_UNIT_NUM1_MASK (0x7F00U) #define MMDC_MPRDDLST_RD_DL_UNIT_NUM1_SHIFT (8U) #define MMDC_MPRDDLST_RD_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLST_RD_DL_UNIT_NUM1_SHIFT)) & MMDC_MPRDDLST_RD_DL_UNIT_NUM1_MASK) #define MMDC_MPRDDLST_RD_DL_UNIT_NUM2_MASK (0x7F0000U) #define MMDC_MPRDDLST_RD_DL_UNIT_NUM2_SHIFT (16U) #define MMDC_MPRDDLST_RD_DL_UNIT_NUM2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLST_RD_DL_UNIT_NUM2_SHIFT)) & MMDC_MPRDDLST_RD_DL_UNIT_NUM2_MASK) #define MMDC_MPRDDLST_RD_DL_UNIT_NUM3_MASK (0x7F000000U) #define MMDC_MPRDDLST_RD_DL_UNIT_NUM3_SHIFT (24U) #define MMDC_MPRDDLST_RD_DL_UNIT_NUM3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLST_RD_DL_UNIT_NUM3_SHIFT)) & MMDC_MPRDDLST_RD_DL_UNIT_NUM3_MASK) /*! @} */ /*! @name MPWRDLCTL - MMDC PHY Write delay-lines Configuration Register */ /*! @{ */ #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK (0x7FU) #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_SHIFT (0U) #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_SHIFT)) & MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK) #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK (0x7F00U) #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_SHIFT (8U) #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_SHIFT)) & MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK) #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK (0x7F0000U) #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_SHIFT (16U) #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_SHIFT)) & MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK) #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK (0x7F000000U) #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_SHIFT (24U) #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_SHIFT)) & MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK) /*! @} */ /*! @name MPWRDLST - MMDC PHY Write delay-lines Status Register */ /*! @{ */ #define MMDC_MPWRDLST_WR_DL_UNIT_NUM0_MASK (0x7FU) #define MMDC_MPWRDLST_WR_DL_UNIT_NUM0_SHIFT (0U) #define MMDC_MPWRDLST_WR_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLST_WR_DL_UNIT_NUM0_SHIFT)) & MMDC_MPWRDLST_WR_DL_UNIT_NUM0_MASK) #define MMDC_MPWRDLST_WR_DL_UNIT_NUM1_MASK (0x7F00U) #define MMDC_MPWRDLST_WR_DL_UNIT_NUM1_SHIFT (8U) #define MMDC_MPWRDLST_WR_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLST_WR_DL_UNIT_NUM1_SHIFT)) & MMDC_MPWRDLST_WR_DL_UNIT_NUM1_MASK) #define MMDC_MPWRDLST_WR_DL_UNIT_NUM2_MASK (0x7F0000U) #define MMDC_MPWRDLST_WR_DL_UNIT_NUM2_SHIFT (16U) #define MMDC_MPWRDLST_WR_DL_UNIT_NUM2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLST_WR_DL_UNIT_NUM2_SHIFT)) & MMDC_MPWRDLST_WR_DL_UNIT_NUM2_MASK) #define MMDC_MPWRDLST_WR_DL_UNIT_NUM3_MASK (0x7F000000U) #define MMDC_MPWRDLST_WR_DL_UNIT_NUM3_SHIFT (24U) #define MMDC_MPWRDLST_WR_DL_UNIT_NUM3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLST_WR_DL_UNIT_NUM3_SHIFT)) & MMDC_MPWRDLST_WR_DL_UNIT_NUM3_MASK) /*! @} */ /*! @name MPZQLP2CTL - MMDC ZQ LPDDR2 HW Control Register */ /*! @{ */ #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK (0x1FFU) #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_SHIFT (0U) /*! ZQ_LP2_HW_ZQINIT * 0b000110111..112 cycles * 0b000111000..114 cycles * 0b100001001..532 cycles (Default. This may need to be adjusted to achieve the correct timing depending on the DDR clock frequency.) * 0b111111110..1022 cycles * 0b111111111..1024 cycles */ #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_SHIFT)) & MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK) #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK (0xFF0000U) #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_SHIFT (16U) /*! ZQ_LP2_HW_ZQCL * 0b00110111..112 cycles * 0b00111000..114 cycles * 0b01011111..192 cycles (Default. This may need to be adjusted to achieve the correct timing depending on the DDR clock frequency.) * 0b11111110..510 cycles * 0b11111111..512 cycles */ #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_SHIFT)) & MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK) #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK (0x7F000000U) #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_SHIFT (24U) /*! ZQ_LP2_HW_ZQCS * 0b0011011..112 cycles (default) * 0b0011100..116 cycles * 0b1111110..508 cycles * 0b1111111..512 cycles */ #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_SHIFT)) & MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK) /*! @} */ /*! @name MPRDDLHWCTL - MMDC PHY Read Delay HW Calibration Control Register */ /*! @{ */ #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_MASK (0x1U) #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_SHIFT (0U) /*! HW_RD_DL_ERR0 * 0b0..No error was found in read delay-line 0 during the automatic (HW) read calibration process of read delay-line 0. * 0b1..An error was found in read delay-line 0 during the automatic (HW) read calibration process of read delay-line 0. */ #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_MASK) #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_MASK (0x2U) #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_SHIFT (1U) /*! HW_RD_DL_ERR1 * 0b0..No error was found in read delay-line 1 during the automatic (HW) read calibration process of read delay-line 1. * 0b1..An error was found in read delay-line 1 during the automatic (HW) read calibration process of read delay-line 1. */ #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_MASK) #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR2_MASK (0x4U) #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR2_SHIFT (2U) /*! HW_RD_DL_ERR2 * 0b0..No error was found in read delay-line 2 during the automatic (HW) read calibration process of read delay-line 2. * 0b1..An error was found in read delay-line 2 during the automatic (HW) read calibration process of read delay-line 2. */ #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR2_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_ERR2_MASK) #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR3_MASK (0x8U) #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR3_SHIFT (3U) /*! HW_RD_DL_ERR3 * 0b0..No error was found in read delay-line 3 during the automatic (HW) read calibration process of read delay-line 3. * 0b1..An error was found in read delay-line 3 during the automatic (HW) read calibration process of read delay-line 3. */ #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR3_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_ERR3_MASK) #define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK (0x10U) #define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_SHIFT (4U) #define MMDC_MPRDDLHWCTL_HW_RD_DL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_EN_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK) #define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK (0x20U) #define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_SHIFT (5U) #define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK) /*! @} */ /*! @name MPWRDLHWCTL - MMDC PHY Write Delay HW Calibration Control Register */ /*! @{ */ #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_MASK (0x1U) #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_SHIFT (0U) /*! HW_WR_DL_ERR0 * 0b0..No error was found during the automatic (HW) write calibration process of write delay-line 0. * 0b1..An error was found during the automatic (HW) write calibration process of write delay-line 0. */ #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_MASK) #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_MASK (0x2U) #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_SHIFT (1U) /*! HW_WR_DL_ERR1 * 0b0..No error was found during the automatic (HW) write calibration process of write delay-line 1. * 0b1..An error was found during the automatic (HW) write calibration process of write delay-line 1. */ #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_MASK) #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR2_MASK (0x4U) #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR2_SHIFT (2U) /*! HW_WR_DL_ERR2 * 0b0..No error was found during the automatic (HW) write calibration process of write delay-line 2. * 0b1..An error was found during the automatic (HW) write calibration process of write delay-line 2. */ #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR2_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_ERR2_MASK) #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR3_MASK (0x8U) #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR3_SHIFT (3U) /*! HW_WR_DL_ERR3 * 0b0..No error was found during the automatic (HW) write calibration process of write delay-line 3. * 0b1..An error was found during the automatic (HW) write calibration process of write delay-line 3. */ #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR3_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_ERR3_MASK) #define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK (0x10U) #define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_SHIFT (4U) #define MMDC_MPWRDLHWCTL_HW_WR_DL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_EN_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK) #define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK (0x20U) #define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_SHIFT (5U) #define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK) /*! @} */ /*! @name MPRDDLHWST0 - MMDC PHY Read Delay HW Calibration Status Register 0 */ /*! @{ */ #define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_MASK (0x7FU) #define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_SHIFT (0U) #define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_MASK) #define MMDC_MPRDDLHWST0_HW_RD_DL_UP0_MASK (0x7F00U) #define MMDC_MPRDDLHWST0_HW_RD_DL_UP0_SHIFT (8U) #define MMDC_MPRDDLHWST0_HW_RD_DL_UP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_UP0_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_UP0_MASK) #define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_MASK (0x7F0000U) #define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_SHIFT (16U) #define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_MASK) #define MMDC_MPRDDLHWST0_HW_RD_DL_UP1_MASK (0x7F000000U) #define MMDC_MPRDDLHWST0_HW_RD_DL_UP1_SHIFT (24U) #define MMDC_MPRDDLHWST0_HW_RD_DL_UP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_UP1_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_UP1_MASK) /*! @} */ /*! @name MPRDDLHWST1 - MMDC PHY Read Delay HW Calibration Status Register 1 */ /*! @{ */ #define MMDC_MPRDDLHWST1_HW_RD_DL_LOW2_MASK (0x7FU) #define MMDC_MPRDDLHWST1_HW_RD_DL_LOW2_SHIFT (0U) #define MMDC_MPRDDLHWST1_HW_RD_DL_LOW2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST1_HW_RD_DL_LOW2_SHIFT)) & MMDC_MPRDDLHWST1_HW_RD_DL_LOW2_MASK) #define MMDC_MPRDDLHWST1_HW_RD_DL_UP2_MASK (0x7F00U) #define MMDC_MPRDDLHWST1_HW_RD_DL_UP2_SHIFT (8U) #define MMDC_MPRDDLHWST1_HW_RD_DL_UP2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST1_HW_RD_DL_UP2_SHIFT)) & MMDC_MPRDDLHWST1_HW_RD_DL_UP2_MASK) #define MMDC_MPRDDLHWST1_HW_RD_DL_LOW3_MASK (0x7F0000U) #define MMDC_MPRDDLHWST1_HW_RD_DL_LOW3_SHIFT (16U) #define MMDC_MPRDDLHWST1_HW_RD_DL_LOW3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST1_HW_RD_DL_LOW3_SHIFT)) & MMDC_MPRDDLHWST1_HW_RD_DL_LOW3_MASK) #define MMDC_MPRDDLHWST1_HW_RD_DL_UP3_MASK (0x7F000000U) #define MMDC_MPRDDLHWST1_HW_RD_DL_UP3_SHIFT (24U) #define MMDC_MPRDDLHWST1_HW_RD_DL_UP3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST1_HW_RD_DL_UP3_SHIFT)) & MMDC_MPRDDLHWST1_HW_RD_DL_UP3_MASK) /*! @} */ /*! @name MPWRDLHWST0 - MMDC PHY Write Delay HW Calibration Status Register 0 */ /*! @{ */ #define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_MASK (0x7FU) #define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_SHIFT (0U) #define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_MASK) #define MMDC_MPWRDLHWST0_HW_WR_DL_UP0_MASK (0x7F00U) #define MMDC_MPWRDLHWST0_HW_WR_DL_UP0_SHIFT (8U) #define MMDC_MPWRDLHWST0_HW_WR_DL_UP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_UP0_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_UP0_MASK) #define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_MASK (0x7F0000U) #define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_SHIFT (16U) #define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_MASK) #define MMDC_MPWRDLHWST0_HW_WR_DL_UP1_MASK (0x7F000000U) #define MMDC_MPWRDLHWST0_HW_WR_DL_UP1_SHIFT (24U) #define MMDC_MPWRDLHWST0_HW_WR_DL_UP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_UP1_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_UP1_MASK) /*! @} */ /*! @name MPWRDLHWST1 - MMDC PHY Write Delay HW Calibration Status Register 1 */ /*! @{ */ #define MMDC_MPWRDLHWST1_HW_WR_DL_LOW2_MASK (0x7FU) #define MMDC_MPWRDLHWST1_HW_WR_DL_LOW2_SHIFT (0U) #define MMDC_MPWRDLHWST1_HW_WR_DL_LOW2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST1_HW_WR_DL_LOW2_SHIFT)) & MMDC_MPWRDLHWST1_HW_WR_DL_LOW2_MASK) #define MMDC_MPWRDLHWST1_HW_WR_DL_UP2_MASK (0x7F00U) #define MMDC_MPWRDLHWST1_HW_WR_DL_UP2_SHIFT (8U) #define MMDC_MPWRDLHWST1_HW_WR_DL_UP2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST1_HW_WR_DL_UP2_SHIFT)) & MMDC_MPWRDLHWST1_HW_WR_DL_UP2_MASK) #define MMDC_MPWRDLHWST1_HW_WR_DL_LOW3_MASK (0x7F0000U) #define MMDC_MPWRDLHWST1_HW_WR_DL_LOW3_SHIFT (16U) #define MMDC_MPWRDLHWST1_HW_WR_DL_LOW3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST1_HW_WR_DL_LOW3_SHIFT)) & MMDC_MPWRDLHWST1_HW_WR_DL_LOW3_MASK) #define MMDC_MPWRDLHWST1_HW_WR_DL_UP3_MASK (0x7F000000U) #define MMDC_MPWRDLHWST1_HW_WR_DL_UP3_SHIFT (24U) #define MMDC_MPWRDLHWST1_HW_WR_DL_UP3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST1_HW_WR_DL_UP3_SHIFT)) & MMDC_MPWRDLHWST1_HW_WR_DL_UP3_MASK) /*! @} */ /*! @name MPPDCMPR1 - MMDC PHY Pre-defined Compare Register 1 */ /*! @{ */ #define MMDC_MPPDCMPR1_PDV1_MASK (0xFFFFU) #define MMDC_MPPDCMPR1_PDV1_SHIFT (0U) #define MMDC_MPPDCMPR1_PDV1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR1_PDV1_SHIFT)) & MMDC_MPPDCMPR1_PDV1_MASK) #define MMDC_MPPDCMPR1_PDV2_MASK (0xFFFF0000U) #define MMDC_MPPDCMPR1_PDV2_SHIFT (16U) #define MMDC_MPPDCMPR1_PDV2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR1_PDV2_SHIFT)) & MMDC_MPPDCMPR1_PDV2_MASK) /*! @} */ /*! @name MPPDCMPR2 - MMDC PHY Pre-defined Compare and CA delay-line Configuration Register */ /*! @{ */ #define MMDC_MPPDCMPR2_MPR_CMP_MASK (0x1U) #define MMDC_MPPDCMPR2_MPR_CMP_SHIFT (0U) #define MMDC_MPPDCMPR2_MPR_CMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_MPR_CMP_SHIFT)) & MMDC_MPPDCMPR2_MPR_CMP_MASK) #define MMDC_MPPDCMPR2_MPR_FULL_CMP_MASK (0x2U) #define MMDC_MPPDCMPR2_MPR_FULL_CMP_SHIFT (1U) #define MMDC_MPPDCMPR2_MPR_FULL_CMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_MPR_FULL_CMP_SHIFT)) & MMDC_MPPDCMPR2_MPR_FULL_CMP_MASK) #define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_MASK (0x4U) #define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_SHIFT (2U) /*! READ_LEVEL_PATTERN * 0b0..Compare with read pattern 1010 * 0b1..Compare with read pattern 0011 (Used only in LPDDR2/LPDDR3 mode) */ #define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_SHIFT)) & MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_MASK) #define MMDC_MPPDCMPR2_ZQ_OFFSET_EN_MASK (0x8U) #define MMDC_MPPDCMPR2_ZQ_OFFSET_EN_SHIFT (3U) /*! ZQ_OFFSET_EN - ZQ Offset Enable * 0b0..Hardware ZQ offset disabled * 0b1..Hardware ZQ offset enabled */ #define MMDC_MPPDCMPR2_ZQ_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_ZQ_OFFSET_EN_SHIFT)) & MMDC_MPPDCMPR2_ZQ_OFFSET_EN_MASK) #define MMDC_MPPDCMPR2_ZQ_PD_OFFSET_MASK (0xF0U) #define MMDC_MPPDCMPR2_ZQ_PD_OFFSET_SHIFT (4U) /*! ZQ_PD_OFFSET * 0b0000..-0 * 0b0001..-1 * 0b0010..-2 * 0b0011..-3 * 0b0100..-4 * 0b0101..-5 * 0b0110..-6 * 0b0111..-7 * 0b1000..Offset is subtracted from ZQ_HW_PD_RES field * 0b1001..Offset is subtracted from ZQ_HW_PD_RES field * 0b1010..Offset is subtracted from ZQ_HW_PD_RES field * 0b1011..Offset is subtracted from ZQ_HW_PD_RES field * 0b1100..Offset is subtracted from ZQ_HW_PD_RES field * 0b1101..Offset is subtracted from ZQ_HW_PD_RES field * 0b1110..Offset is subtracted from ZQ_HW_PD_RES field * 0b1111..Offset is subtracted from ZQ_HW_PD_RES field */ #define MMDC_MPPDCMPR2_ZQ_PD_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_ZQ_PD_OFFSET_SHIFT)) & MMDC_MPPDCMPR2_ZQ_PD_OFFSET_MASK) #define MMDC_MPPDCMPR2_ZQ_PU_OFFSET_MASK (0xF00U) #define MMDC_MPPDCMPR2_ZQ_PU_OFFSET_SHIFT (8U) /*! ZQ_PU_OFFSET * 0b0000..-0 * 0b0001..-1 * 0b0010..-2 * 0b0011..-3 * 0b0100..-4 * 0b0101..-5 * 0b0110..-6 * 0b0111..-7 * 0b1000..Offset is subtracted from ZQ_HW_PU_RES field * 0b1001..Offset is subtracted from ZQ_HW_PU_RES field * 0b1010..Offset is subtracted from ZQ_HW_PU_RES field * 0b1011..Offset is subtracted from ZQ_HW_PU_RES field * 0b1100..Offset is subtracted from ZQ_HW_PU_RES field * 0b1101..Offset is subtracted from ZQ_HW_PU_RES field * 0b1110..Offset is subtracted from ZQ_HW_PU_RES field * 0b1111..Offset is subtracted from ZQ_HW_PU_RES field */ #define MMDC_MPPDCMPR2_ZQ_PU_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_ZQ_PU_OFFSET_SHIFT)) & MMDC_MPPDCMPR2_ZQ_PU_OFFSET_MASK) #define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_MASK (0x7F0000U) #define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_SHIFT (16U) #define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_SHIFT)) & MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_MASK) #define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_MASK (0x7F000000U) #define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_SHIFT (24U) #define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_SHIFT)) & MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_MASK) /*! @} */ /*! @name MPSWDAR0 - MMDC PHY SW Dummy Access Register */ /*! @{ */ #define MMDC_MPSWDAR0_SW_DUMMY_WR_MASK (0x1U) #define MMDC_MPSWDAR0_SW_DUMMY_WR_SHIFT (0U) #define MMDC_MPSWDAR0_SW_DUMMY_WR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUMMY_WR_SHIFT)) & MMDC_MPSWDAR0_SW_DUMMY_WR_MASK) #define MMDC_MPSWDAR0_SW_DUMMY_RD_MASK (0x2U) #define MMDC_MPSWDAR0_SW_DUMMY_RD_SHIFT (1U) #define MMDC_MPSWDAR0_SW_DUMMY_RD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUMMY_RD_SHIFT)) & MMDC_MPSWDAR0_SW_DUMMY_RD_MASK) #define MMDC_MPSWDAR0_SW_DUM_CMP0_MASK (0x4U) #define MMDC_MPSWDAR0_SW_DUM_CMP0_SHIFT (2U) /*! SW_DUM_CMP0 * 0b0..Dummy read fail * 0b1..Dummy read pass */ #define MMDC_MPSWDAR0_SW_DUM_CMP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUM_CMP0_SHIFT)) & MMDC_MPSWDAR0_SW_DUM_CMP0_MASK) #define MMDC_MPSWDAR0_SW_DUM_CMP1_MASK (0x8U) #define MMDC_MPSWDAR0_SW_DUM_CMP1_SHIFT (3U) /*! SW_DUM_CMP1 * 0b0..Dummy read fail * 0b1..Dummy read pass */ #define MMDC_MPSWDAR0_SW_DUM_CMP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUM_CMP1_SHIFT)) & MMDC_MPSWDAR0_SW_DUM_CMP1_MASK) #define MMDC_MPSWDAR0_SW_DUM_CMP2_MASK (0x10U) #define MMDC_MPSWDAR0_SW_DUM_CMP2_SHIFT (4U) /*! SW_DUM_CMP2 * 0b0..Dummy read fail * 0b1..Dummy read pass */ #define MMDC_MPSWDAR0_SW_DUM_CMP2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUM_CMP2_SHIFT)) & MMDC_MPSWDAR0_SW_DUM_CMP2_MASK) #define MMDC_MPSWDAR0_SW_DUM_CMP3_MASK (0x20U) #define MMDC_MPSWDAR0_SW_DUM_CMP3_SHIFT (5U) /*! SW_DUM_CMP3 * 0b0..Dummy read fail * 0b1..Dummy read pass */ #define MMDC_MPSWDAR0_SW_DUM_CMP3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUM_CMP3_SHIFT)) & MMDC_MPSWDAR0_SW_DUM_CMP3_MASK) /*! @} */ /*! @name MPSWDRDR0 - MMDC PHY SW Dummy Read Data Register 0 */ /*! @{ */ #define MMDC_MPSWDRDR0_DUM_RD0_MASK (0xFFFFFFFFU) #define MMDC_MPSWDRDR0_DUM_RD0_SHIFT (0U) #define MMDC_MPSWDRDR0_DUM_RD0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR0_DUM_RD0_SHIFT)) & MMDC_MPSWDRDR0_DUM_RD0_MASK) /*! @} */ /*! @name MPSWDRDR1 - MMDC PHY SW Dummy Read Data Register 1 */ /*! @{ */ #define MMDC_MPSWDRDR1_DUM_RD1_MASK (0xFFFFFFFFU) #define MMDC_MPSWDRDR1_DUM_RD1_SHIFT (0U) #define MMDC_MPSWDRDR1_DUM_RD1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR1_DUM_RD1_SHIFT)) & MMDC_MPSWDRDR1_DUM_RD1_MASK) /*! @} */ /*! @name MPSWDRDR2 - MMDC PHY SW Dummy Read Data Register 2 */ /*! @{ */ #define MMDC_MPSWDRDR2_DUM_RD2_MASK (0xFFFFFFFFU) #define MMDC_MPSWDRDR2_DUM_RD2_SHIFT (0U) #define MMDC_MPSWDRDR2_DUM_RD2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR2_DUM_RD2_SHIFT)) & MMDC_MPSWDRDR2_DUM_RD2_MASK) /*! @} */ /*! @name MPSWDRDR3 - MMDC PHY SW Dummy Read Data Register 3 */ /*! @{ */ #define MMDC_MPSWDRDR3_DUM_RD3_MASK (0xFFFFFFFFU) #define MMDC_MPSWDRDR3_DUM_RD3_SHIFT (0U) #define MMDC_MPSWDRDR3_DUM_RD3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR3_DUM_RD3_SHIFT)) & MMDC_MPSWDRDR3_DUM_RD3_MASK) /*! @} */ /*! @name MPSWDRDR4 - MMDC PHY SW Dummy Read Data Register 4 */ /*! @{ */ #define MMDC_MPSWDRDR4_DUM_RD4_MASK (0xFFFFFFFFU) #define MMDC_MPSWDRDR4_DUM_RD4_SHIFT (0U) #define MMDC_MPSWDRDR4_DUM_RD4(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR4_DUM_RD4_SHIFT)) & MMDC_MPSWDRDR4_DUM_RD4_MASK) /*! @} */ /*! @name MPSWDRDR5 - MMDC PHY SW Dummy Read Data Register 5 */ /*! @{ */ #define MMDC_MPSWDRDR5_DUM_RD5_MASK (0xFFFFFFFFU) #define MMDC_MPSWDRDR5_DUM_RD5_SHIFT (0U) #define MMDC_MPSWDRDR5_DUM_RD5(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR5_DUM_RD5_SHIFT)) & MMDC_MPSWDRDR5_DUM_RD5_MASK) /*! @} */ /*! @name MPSWDRDR6 - MMDC PHY SW Dummy Read Data Register 6 */ /*! @{ */ #define MMDC_MPSWDRDR6_DUM_RD6_MASK (0xFFFFFFFFU) #define MMDC_MPSWDRDR6_DUM_RD6_SHIFT (0U) #define MMDC_MPSWDRDR6_DUM_RD6(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR6_DUM_RD6_SHIFT)) & MMDC_MPSWDRDR6_DUM_RD6_MASK) /*! @} */ /*! @name MPSWDRDR7 - MMDC PHY SW Dummy Read Data Register 7 */ /*! @{ */ #define MMDC_MPSWDRDR7_DUM_RD7_MASK (0xFFFFFFFFU) #define MMDC_MPSWDRDR7_DUM_RD7_SHIFT (0U) #define MMDC_MPSWDRDR7_DUM_RD7(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR7_DUM_RD7_SHIFT)) & MMDC_MPSWDRDR7_DUM_RD7_MASK) /*! @} */ /*! @name MPMUR0 - MMDC PHY Measure Unit Register */ /*! @{ */ #define MMDC_MPMUR0_MU_BYP_VAL_MASK (0x3FFU) #define MMDC_MPMUR0_MU_BYP_VAL_SHIFT (0U) #define MMDC_MPMUR0_MU_BYP_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_MU_BYP_VAL_SHIFT)) & MMDC_MPMUR0_MU_BYP_VAL_MASK) #define MMDC_MPMUR0_MU_BYP_EN_MASK (0x400U) #define MMDC_MPMUR0_MU_BYP_EN_SHIFT (10U) /*! MU_BYP_EN * 0b0..The delay-lines use delay units as indicated at MU_UNIT_DEL_NUM. * 0b1..The delay-lines use delay units as indicated at MU_BYPASS_VAL. */ #define MMDC_MPMUR0_MU_BYP_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_MU_BYP_EN_SHIFT)) & MMDC_MPMUR0_MU_BYP_EN_MASK) #define MMDC_MPMUR0_FRC_MSR_MASK (0x800U) #define MMDC_MPMUR0_FRC_MSR_SHIFT (11U) /*! FRC_MSR * 0b0..No measurement is performed * 0b1..Perform measurement process */ #define MMDC_MPMUR0_FRC_MSR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_FRC_MSR_SHIFT)) & MMDC_MPMUR0_FRC_MSR_MASK) #define MMDC_MPMUR0_MU_UNIT_DEL_NUM_MASK (0x3FF0000U) #define MMDC_MPMUR0_MU_UNIT_DEL_NUM_SHIFT (16U) #define MMDC_MPMUR0_MU_UNIT_DEL_NUM(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_MU_UNIT_DEL_NUM_SHIFT)) & MMDC_MPMUR0_MU_UNIT_DEL_NUM_MASK) /*! @} */ /*! @name MPDCCR - MMDC Duty Cycle Control Register */ /*! @{ */ #define MMDC_MPDCCR_WR_DQS0_FT_DCC_MASK (0x7U) #define MMDC_MPDCCR_WR_DQS0_FT_DCC_SHIFT (0U) /*! WR_DQS0_FT_DCC * 0b001..51.5% low 48.5% high * 0b010..50% duty cycle (default) * 0b100..48.5% low 51.5% high */ #define MMDC_MPDCCR_WR_DQS0_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_WR_DQS0_FT_DCC_SHIFT)) & MMDC_MPDCCR_WR_DQS0_FT_DCC_MASK) #define MMDC_MPDCCR_WR_DQS1_FT_DCC_MASK (0x38U) #define MMDC_MPDCCR_WR_DQS1_FT_DCC_SHIFT (3U) /*! WR_DQS1_FT_DCC * 0b001..51.5% low 48.5% high * 0b010..50% duty cycle (default) * 0b100..48.5% low 51.5% high */ #define MMDC_MPDCCR_WR_DQS1_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_WR_DQS1_FT_DCC_SHIFT)) & MMDC_MPDCCR_WR_DQS1_FT_DCC_MASK) #define MMDC_MPDCCR_WR_DQS2_FT_DCC_MASK (0x1C0U) #define MMDC_MPDCCR_WR_DQS2_FT_DCC_SHIFT (6U) /*! WR_DQS2_FT_DCC * 0b001..51.5% low 48.5% high * 0b010..50% duty cycle (default) * 0b100..48.5% low 51.5% high */ #define MMDC_MPDCCR_WR_DQS2_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_WR_DQS2_FT_DCC_SHIFT)) & MMDC_MPDCCR_WR_DQS2_FT_DCC_MASK) #define MMDC_MPDCCR_WR_DQS3_FT_DCC_MASK (0xE00U) #define MMDC_MPDCCR_WR_DQS3_FT_DCC_SHIFT (9U) /*! WR_DQS3_FT_DCC * 0b001..51.5% low 48.5% high * 0b010..50% duty cycle (default) * 0b100..48.5% low 51.5% high */ #define MMDC_MPDCCR_WR_DQS3_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_WR_DQS3_FT_DCC_SHIFT)) & MMDC_MPDCCR_WR_DQS3_FT_DCC_MASK) #define MMDC_MPDCCR_CK_FT0_DCC_MASK (0x7000U) #define MMDC_MPDCCR_CK_FT0_DCC_SHIFT (12U) /*! CK_FT0_DCC * 0b001..48.5% low 51.5% high * 0b010..50% duty cycle (default) * 0b100..51.5% low 48.5% high */ #define MMDC_MPDCCR_CK_FT0_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_CK_FT0_DCC_SHIFT)) & MMDC_MPDCCR_CK_FT0_DCC_MASK) #define MMDC_MPDCCR_CK_FT1_DCC_MASK (0x70000U) #define MMDC_MPDCCR_CK_FT1_DCC_SHIFT (16U) /*! CK_FT1_DCC * 0b001..48.5% low 51.5% high * 0b010..50% duty cycle (default) * 0b100..51.5% low 48.5% high */ #define MMDC_MPDCCR_CK_FT1_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_CK_FT1_DCC_SHIFT)) & MMDC_MPDCCR_CK_FT1_DCC_MASK) #define MMDC_MPDCCR_RD_DQS0_FT_DCC_MASK (0x380000U) #define MMDC_MPDCCR_RD_DQS0_FT_DCC_SHIFT (19U) /*! RD_DQS0_FT_DCC * 0b001..51.5% low 48.5% high * 0b010..50% duty cycle (default) * 0b100..48.5% low 51.5% high */ #define MMDC_MPDCCR_RD_DQS0_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_RD_DQS0_FT_DCC_SHIFT)) & MMDC_MPDCCR_RD_DQS0_FT_DCC_MASK) #define MMDC_MPDCCR_RD_DQS1_FT_DCC_MASK (0x1C00000U) #define MMDC_MPDCCR_RD_DQS1_FT_DCC_SHIFT (22U) /*! RD_DQS1_FT_DCC * 0b001..51.5% low 48.5% high * 0b010..50% duty cycle (default) * 0b100..48.5% low 51.5% high */ #define MMDC_MPDCCR_RD_DQS1_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_RD_DQS1_FT_DCC_SHIFT)) & MMDC_MPDCCR_RD_DQS1_FT_DCC_MASK) #define MMDC_MPDCCR_RD_DQS2_FT_DCC_MASK (0xE000000U) #define MMDC_MPDCCR_RD_DQS2_FT_DCC_SHIFT (25U) /*! RD_DQS2_FT_DCC * 0b001..51.5% low 48.5% high * 0b010..50% duty cycle (default) * 0b100..48.5% low 51.5% high */ #define MMDC_MPDCCR_RD_DQS2_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_RD_DQS2_FT_DCC_SHIFT)) & MMDC_MPDCCR_RD_DQS2_FT_DCC_MASK) #define MMDC_MPDCCR_RD_DQS3_FT_DCC_MASK (0x70000000U) #define MMDC_MPDCCR_RD_DQS3_FT_DCC_SHIFT (28U) /*! RD_DQS3_FT_DCC * 0b001..51.5% low 48.5% high * 0b010..50% duty cycle (default) * 0b100..48.5% low 51.5% high */ #define MMDC_MPDCCR_RD_DQS3_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_RD_DQS3_FT_DCC_SHIFT)) & MMDC_MPDCCR_RD_DQS3_FT_DCC_MASK) /*! @} */ /*! * @} */ /* end of group MMDC_Register_Masks */ /* MMDC - Peripheral instance base addresses */ /** Peripheral MMDC0 base address */ #define MMDC0_BASE (0x40AB0000u) /** Peripheral MMDC0 base pointer */ #define MMDC0 ((MMDC_Type *)MMDC0_BASE) /** Array initializer of MMDC peripheral base addresses */ #define MMDC_BASE_ADDRS { MMDC0_BASE } /** Array initializer of MMDC peripheral base pointers */ #define MMDC_BASE_PTRS { MMDC0 } /*! * @} */ /* end of group MMDC_Peripheral_Access_Layer */ /*! * @brief Core boot mode. */ typedef enum _mu_core_boot_mode { kMU_CoreBootFromAddr0 = 0x00U, /*!< Boot from 0x00. */ kMU_CoreBootFromFlash = 0x01U, /*!< Boot from Flash base. */ kMU_CoreBootFromItcm = 0x02U, /*!< Boot from ITCM base. */ } mu_core_boot_mode_t; /*! * @brief Power mode on the other side definition. */ typedef enum _mu_power_mode { kMU_PowerModeRun = 0x00U, /*!< Run mode. */ kMU_PowerModeWait = 0x01U, /*!< WAIT mode. */ kMU_PowerModeStop = 0x02U, /*!< STOP/VLPS mode. */ kMU_PowerModeDsm = 0x03U, /*!< DSM: LLS/VLLS mode. */ } mu_power_mode_t; /* ---------------------------------------------------------------------------- -- MU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer * @{ */ /** MU - Register Layout Typedef */ typedef struct { __I uint32_t VER; /**< Version ID Register, offset: 0x0 */ __I uint32_t PAR; /**< Parameter Register, offset: 0x4 */ uint8_t RESERVED_0[24]; __IO uint32_t TR[4]; /**< Transmit Register, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_1[16]; __I uint32_t RR[4]; /**< Receive Register, array offset: 0x40, array step: 0x4 */ uint8_t RESERVED_2[16]; __IO uint32_t SR; /**< Status Register, offset: 0x60 */ __IO uint32_t CR; /**< Control Register, offset: 0x64 */ } MU_Type; /* ---------------------------------------------------------------------------- -- MU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MU_Register_Masks MU Register Masks * @{ */ /*! @name VER - Version ID Register */ /*! @{ */ #define MU_VER_FEATURE_MASK (0xFFFFU) #define MU_VER_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b000000000000x1xx..Core Control and Status Registers are implemented in both MUA and MUB. * 0b000000000000xx1x..RAIP/RAIE register bits are implemented. * 0b000000000000xxx0..Standard features implemented */ #define MU_VER_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_FEATURE_SHIFT)) & MU_VER_FEATURE_MASK) #define MU_VER_MINOR_MASK (0xFF0000U) #define MU_VER_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define MU_VER_MINOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MINOR_SHIFT)) & MU_VER_MINOR_MASK) #define MU_VER_MAJOR_MASK (0xFF000000U) #define MU_VER_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define MU_VER_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MAJOR_SHIFT)) & MU_VER_MAJOR_MASK) /*! @} */ /*! @name PAR - Parameter Register */ /*! @{ */ #define MU_PAR_PARAMETER_MASK (0xFFFFFFFFU) #define MU_PAR_PARAMETER_SHIFT (0U) /*! PARAMETER - This bitfield contains the parameter settings of MUA. */ #define MU_PAR_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_PARAMETER_SHIFT)) & MU_PAR_PARAMETER_MASK) /*! @} */ /*! @name TR - Transmit Register */ /*! @{ */ #define MU_TR_DATA_MASK (0xFFFFFFFFU) #define MU_TR_DATA_SHIFT (0U) /*! DATA - DATA */ #define MU_TR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_DATA_SHIFT)) & MU_TR_DATA_MASK) /*! @} */ /* The count of MU_TR */ #define MU_TR_COUNT (4U) /*! @name RR - Receive Register */ /*! @{ */ #define MU_RR_DATA_MASK (0xFFFFFFFFU) #define MU_RR_DATA_SHIFT (0U) /*! DATA - DATA */ #define MU_RR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK) /*! @} */ /* The count of MU_RR */ #define MU_RR_COUNT (4U) /*! @name SR - Status Register */ /*! @{ */ #define MU_SR_Fn_MASK (0x7U) #define MU_SR_Fn_SHIFT (0U) /*! Fn - Fn * 0b000..Fn bit in the MUB CR register is written 0 (default). * 0b001..Fn bit in the MUB CR register is written 1. */ #define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK) #define MU_SR_NMIC_MASK (0x8U) #define MU_SR_NMIC_SHIFT (3U) /*! NMIC - NMIC * 0b0..Default * 0b1..Writing "1" clears the NMI bit in the MUB CR register. */ #define MU_SR_NMIC(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_NMIC_SHIFT)) & MU_SR_NMIC_MASK) #define MU_SR_EP_MASK (0x10U) #define MU_SR_EP_SHIFT (4U) /*! EP - EP * 0b0..The MUA side event is not pending (default). * 0b1..The MUA side event is pending. */ #define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK) #define MU_SR_PM_MASK (0x60U) #define MU_SR_PM_SHIFT (5U) /*! PM - PM * 0b00..The MUB processor is in Run Mode. * 0b01..The MUB processor is in WAIT Mode. * 0b10..The MUB processor is in STOP/VLPS Mode. * 0b11..The MUB processor is in LLS/VLLS Mode. */ #define MU_SR_PM(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_PM_SHIFT)) & MU_SR_PM_MASK) #define MU_SR_RS_MASK (0x80U) #define MU_SR_RS_SHIFT (7U) /*! RS - RS * 0b0..The MUB side of the MU is not in reset. * 0b1..The MUB side of the MU is in reset. */ #define MU_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RS_SHIFT)) & MU_SR_RS_MASK) #define MU_SR_FUP_MASK (0x100U) #define MU_SR_FUP_SHIFT (8U) /*! FUP - FUP * 0b0..No flags updated, initiated by the MUA, in progress (default) * 0b1..MUA initiated flags update, processing */ #define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK) #define MU_SR_RDIP_MASK (0x200U) #define MU_SR_RDIP_SHIFT (9U) /*! RDIP - RDIP * 0b0..Processor B-side did not exit reset * 0b1..Processor B-side exited from reset */ #define MU_SR_RDIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RDIP_SHIFT)) & MU_SR_RDIP_MASK) #define MU_SR_RAIP_MASK (0x400U) #define MU_SR_RAIP_SHIFT (10U) /*! RAIP - RAIP * 0b0..Processor B-side did not enter reset * 0b1..Processor B-side entered reset */ #define MU_SR_RAIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RAIP_SHIFT)) & MU_SR_RAIP_MASK) #define MU_SR_TEn_MASK (0xF00000U) #define MU_SR_TEn_SHIFT (20U) /*! TEn - TEn * 0b0000..MUA TRn register is not empty. * 0b0001..MUA TRn register is empty (default). */ #define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK) #define MU_SR_RFn_MASK (0xF000000U) #define MU_SR_RFn_SHIFT (24U) /*! RFn - RFn * 0b0000..MUA RRn register is not full (default). * 0b0001..MUA RRn register has received data from MUB TRn register and is ready to be read by the MUA. */ #define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK) #define MU_SR_GIPn_MASK (0xF0000000U) #define MU_SR_GIPn_SHIFT (28U) /*! GIPn - GIPn * 0b0000..MUA general purpose interrupt n is not pending. (default) * 0b0001..MUA general purpose interrupt n is pending. */ #define MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK) /*! @} */ /*! @name CR - Control Register */ /*! @{ */ #define MU_CR_Fn_MASK (0x7U) #define MU_CR_Fn_SHIFT (0U) /*! Fn - Fn * 0b000..Clears the Fn bit in the SR register. * 0b001..Sets the Fn bit in the SR register. */ #define MU_CR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK) #define MU_CR_NMI_MASK (0x8U) #define MU_CR_NMI_SHIFT (3U) /*! NMI - NMI * 0b0..Non-maskable interrupt is not issued to the Processor B by the Processor A (default). * 0b1..Non-maskable interrupt is issued to the Processor B by the Processor A. */ #define MU_CR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_NMI_SHIFT)) & MU_CR_NMI_MASK) #define MU_CR_BHR_MASK (0x10U) #define MU_CR_BHR_SHIFT (4U) /*! BHR - BHR * 0b0..De-assert Hardware reset to the Processor B. (default) * 0b1..Assert Hardware reset to the Processor B. */ #define MU_CR_BHR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_BHR_SHIFT)) & MU_CR_BHR_MASK) #define MU_CR_MUR_MASK (0x20U) #define MU_CR_MUR_SHIFT (5U) /*! MUR - MUR * 0b0..N/A. Self clearing bit (default). * 0b1..Asserts the MU reset. */ #define MU_CR_MUR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK) #define MU_CR_RDIE_MASK (0x40U) #define MU_CR_RDIE_SHIFT (6U) /*! RDIE - RDIE * 0b0..Disables Processor A General Purpose Interrupt 3 request due to Processor B reset de-assertion. * 0b1..Enables Processor A General Purpose Interrupt 3 request due to Processor B reset de-assertion. */ #define MU_CR_RDIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RDIE_SHIFT)) & MU_CR_RDIE_MASK) #define MU_CR_RSTH_MASK (0x80U) #define MU_CR_RSTH_SHIFT (7U) /*! RSTH - Processor B Reset Hold * 0b0..Release Processor B from reset * 0b1..Hold Processor B in reset */ #define MU_CR_RSTH(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RSTH_SHIFT)) & MU_CR_RSTH_MASK) #define MU_CR_CLKE_MASK (0x100U) #define MU_CR_CLKE_SHIFT (8U) /*! CLKE - MUB clock enable * 0b0..MUB platform clock gated when MUB enters a stop mode. * 0b1..MUB platform clock kept running after MUB enters a stop mode, until MUA also enters a stop mode. */ #define MU_CR_CLKE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_CLKE_SHIFT)) & MU_CR_CLKE_MASK) #define MU_CR_BBOOT_MASK (0x600U) #define MU_CR_BBOOT_SHIFT (9U) /*! BBOOT - Processor B Boot Config. * 0b00..Boot from 0x0 * 0b01..Boot from DMEM Base * 0b10..Boot from IMEM Base * 0b11..Reserved */ #define MU_CR_BBOOT(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_BBOOT_SHIFT)) & MU_CR_BBOOT_MASK) #define MU_CR_RAIE_MASK (0x1000U) #define MU_CR_RAIE_SHIFT (12U) /*! RAIE - RAIE * 0b0..Disables Processor A General Purpose Interrupt 3 request due to Processor B reset assertion. * 0b1..Enables Processor A General Purpose Interrupt 3 request due to Processor B reset assertion. */ #define MU_CR_RAIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RAIE_SHIFT)) & MU_CR_RAIE_MASK) #define MU_CR_GIRn_MASK (0xF0000U) #define MU_CR_GIRn_SHIFT (16U) /*! GIRn - GIRn * 0b0000..MUA General Interrupt n is not requested to the MUB (default). * 0b0001..MUA General Interrupt n is requested to the MUB. */ #define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK) #define MU_CR_TIEn_MASK (0xF00000U) #define MU_CR_TIEn_SHIFT (20U) /*! TIEn - TIEn * 0b0000..Disables MUA Transmit Interrupt n. (default) * 0b0001..Enables MUA Transmit Interrupt n. */ #define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK) #define MU_CR_RIEn_MASK (0xF000000U) #define MU_CR_RIEn_SHIFT (24U) /*! RIEn - RIEn * 0b0000..Disables MUA Receive Interrupt n. (default) * 0b0001..Enables MUA Receive Interrupt n. */ #define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK) #define MU_CR_GIEn_MASK (0xF0000000U) #define MU_CR_GIEn_SHIFT (28U) /*! GIEn - GIEn * 0b0000..Disables MUA General Interrupt n. (default) * 0b0001..Enables MUA General Interrupt n. */ #define MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK) /*! @} */ /*! * @} */ /* end of group MU_Register_Masks */ /* MU - Peripheral instance base addresses */ /** Peripheral MUA base address */ #define MUA_BASE (0x41022000u) /** Peripheral MUA base pointer */ #define MUA ((MU_Type *)MUA_BASE) /** Array initializer of MU peripheral base addresses */ #define MU_BASE_ADDRS { MUA_BASE } /** Array initializer of MU peripheral base pointers */ #define MU_BASE_PTRS { MUA } /** Interrupt vectors for the MU peripheral type */ #define MU_IRQS { MU_A_IRQn } /* Backward compatibility */ #define MU_CR_HR_MASK MU_CR_BHR_MASK #define MU_CR_HR(x) MU_CR_BHR(x) #define MU_CR_HR_SHIFT MU_CR_BHR_SHIFT #define MU_CR_BOOT_MASK MU_CR_BBOOT_MASK #define MU_CR_BOOT(x) MU_CR_BBOOT(x) #define MU_CR_BOOT_SHIFT MU_CR_BBOOT_SHIFT /*! * @} */ /* end of group MU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- OCOTP_CTRL Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup OCOTP_CTRL_Peripheral_Access_Layer OCOTP_CTRL Peripheral Access Layer * @{ */ /** OCOTP_CTRL - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0 */ __IO uint32_t RW; /**< OTP Controller Control Register, offset: 0x0 */ __IO uint32_t SET; /**< OTP Controller Control Register, offset: 0x4 */ __IO uint32_t CLR; /**< OTP Controller Control Register, offset: 0x8 */ __IO uint32_t TOG; /**< OTP Controller Control Register, offset: 0xC */ } HW_OCOTP_CTRL; __IO uint32_t HW_OCOTP_PDN; /**< OTP Controller PDN Register, offset: 0x10 */ uint8_t RESERVED_0[12]; __IO uint32_t HW_OCOTP_DATA; /**< OTP Controller Write Data Register, offset: 0x20 */ uint8_t RESERVED_1[12]; __IO uint32_t HW_OCOTP_READ_CTRL; /**< OTP Controller Read Control Register, offset: 0x30 */ uint8_t RESERVED_2[12]; __I uint32_t HW_OCOTP_READ_FUSE_DATA; /**< OTP Controller Read Fuse Data Register, offset: 0x40 */ uint8_t RESERVED_3[12]; __IO uint32_t HW_OCOTP_SW_STICKY; /**< OTP Controller Sticky Bit Register, offset: 0x50 */ uint8_t RESERVED_4[12]; struct { /* offset: 0x60 */ __IO uint32_t RW; /**< OTP Controller Software Controllable Signals Register, offset: 0x60 */ __IO uint32_t SET; /**< OTP Controller Software Controllable Signals Register, offset: 0x64 */ __IO uint32_t CLR; /**< OTP Controller Software Controllable Signals Register, offset: 0x68 */ __IO uint32_t TOG; /**< OTP Controller Software Controllable Signals Register, offset: 0x6C */ } HW_OCOTP_SCS; uint8_t RESERVED_5[32]; struct { /* offset: 0x90 */ __IO uint32_t RW; /**< OTP Controller Output Status Register, offset: 0x90 */ __IO uint32_t SET; /**< OTP Controller Output Status Register, offset: 0x94 */ __IO uint32_t CLR; /**< OTP Controller Output Status Register, offset: 0x98 */ __IO uint32_t TOG; /**< OTP Controller Output Status Register, offset: 0x9C */ } HW_OCOTP_OUT_STATUS; __I uint32_t HW_OCOTP_STARTWORD; /**< OTP Controller Output Startword Register, offset: 0xA0 */ uint8_t RESERVED_6[12]; __I uint32_t HW_OCOTP_VERSION; /**< OTP Controller Version Register, offset: 0xB0 */ uint8_t RESERVED_7[972]; __I uint32_t HW_OCOTP_LOCK0; /**< OTP Controller Lock Control Register 0, offset: 0x480 */ uint8_t RESERVED_8[12]; __I uint32_t HW_OCOTP_LOCK1; /**< OTP Controller Lock Control Register 1, offset: 0x490 */ uint8_t RESERVED_9[12]; __I uint32_t HW_OCOTP_LOCK2; /**< OTP Controller Lock Control Register 2, offset: 0x4A0 */ uint8_t RESERVED_10[12]; __IO uint32_t HW_OCOTP_CFG0; /**< Value of OTP Bank1 Word3 (ID Info.), offset: 0x4B0 */ uint8_t RESERVED_11[12]; __IO uint32_t HW_OCOTP_CFG1; /**< Value of OTP Bank1 Word4 (ID Info.), offset: 0x4C0 */ uint8_t RESERVED_12[12]; __IO uint32_t HW_OCOTP_CFG2; /**< Value of OTP Bank1 Word5 (ID Info.), offset: 0x4D0 */ uint8_t RESERVED_13[12]; __IO uint32_t HW_OCOTP_CFG3; /**< Value of OTP Bank1 Word6 (ID Info.), offset: 0x4E0 */ uint8_t RESERVED_14[12]; __IO uint32_t HW_OCOTP_CFG4; /**< Value of OTP Bank1 Word7 (ID Info.), offset: 0x4F0 */ uint8_t RESERVED_15[12]; __IO uint32_t HW_OCOTP_BOOT0; /**< Value of OTP Bank2 Word0 (Boot Configuration Info.), offset: 0x500 */ uint8_t RESERVED_16[44]; __IO uint32_t HW_OCOTP_BOOT3; /**< OTP Controller Boot Configuration Register 3, offset: 0x530 */ uint8_t RESERVED_17[12]; __IO uint32_t HW_OCOTP_BOOT4; /**< OTP Controller Boot Configuration Register 4, offset: 0x540 */ uint8_t RESERVED_18[12]; __IO uint32_t HW_OCOTP_BOOT5; /**< OTP Controller Boot Configuration Register 5, offset: 0x550 */ uint8_t RESERVED_19[12]; __IO uint32_t HW_OCOTP_BOOT6; /**< OTP Controller Boot Configuration Register 6, offset: 0x560 */ uint8_t RESERVED_20[12]; __IO uint32_t HW_OCOTP_BOOT7; /**< OTP Controller Boot Configuration Register 7, offset: 0x570 */ uint8_t RESERVED_21[92]; __IO uint32_t HW_OCOTP_ANA1; /**< Value of OTP Bank3 Word5 (Memory Related Info.), offset: 0x5D0 */ uint8_t RESERVED_22[12]; __IO uint32_t HW_OCOTP_ANA2; /**< OTP Controller Analog Register 2, offset: 0x5E0 */ uint8_t RESERVED_23[12]; __IO uint32_t HW_OCOTP_ANA3; /**< OTP Controller Analog Register 3, offset: 0x5F0 */ uint8_t RESERVED_24[668]; __IO uint32_t HW_OCOTP_PAD_MISC1; /**< Value of OTP Bank9 Word1, offset: 0x890 */ uint8_t RESERVED_25[28]; __IO uint32_t HW_OCOTP_PAD_MISC3; /**< Value of OTP Bank9 Word3, offset: 0x8B0 */ uint8_t RESERVED_26[1868]; __IO uint32_t HW_OCOTP_GP60; /**< Value of OTP Bank24 Word0 (GP6), offset: 0x1000 */ uint8_t RESERVED_27[12]; __IO uint32_t HW_OCOTP_GP61; /**< Value of OTP Bank24 Word1 (GP6), offset: 0x1010 */ uint8_t RESERVED_28[12]; __IO uint32_t HW_OCOTP_GP62; /**< Value of OTP Bank24 Word2 (GP6), offset: 0x1020 */ uint8_t RESERVED_29[12]; __IO uint32_t HW_OCOTP_GP63; /**< Value of OTP Bank24 Word3 (GP6), offset: 0x1030 */ uint8_t RESERVED_30[12]; __IO uint32_t HW_OCOTP_GP64; /**< Value of OTP Bank24 Word4 (GP6), offset: 0x1040 */ uint8_t RESERVED_31[12]; __IO uint32_t HW_OCOTP_GP65; /**< Value of OTP Bank24 Word5 (GP6), offset: 0x1050 */ uint8_t RESERVED_32[12]; __IO uint32_t HW_OCOTP_GP66; /**< Value of OTP Bank24 Word6 (GP6), offset: 0x1060 */ uint8_t RESERVED_33[12]; __IO uint32_t HW_OCOTP_GP67; /**< Value of OTP Bank24 Word7 (GP6), offset: 0x1070 */ uint8_t RESERVED_34[12]; __IO uint32_t HW_OCOTP_GP70; /**< Value of OTP Bank25 Word0 (GP7), offset: 0x1080 */ uint8_t RESERVED_35[12]; __IO uint32_t HW_OCOTP_GP71; /**< Value of OTP Bank25 Word1 (GP7), offset: 0x1090 */ uint8_t RESERVED_36[12]; __IO uint32_t HW_OCOTP_GP72; /**< Value of OTP Bank25 Word2 (GP7), offset: 0x10A0 */ uint8_t RESERVED_37[12]; __IO uint32_t HW_OCOTP_GP73; /**< Value of OTP Bank25 Word3 (GP7), offset: 0x10B0 */ uint8_t RESERVED_38[12]; __IO uint32_t HW_OCOTP_GP74; /**< Value of OTP Bank25 Word4 (GP7), offset: 0x10C0 */ uint8_t RESERVED_39[12]; __IO uint32_t HW_OCOTP_GP75; /**< Value of OTP Bank25 Word5 (GP7), offset: 0x10D0 */ uint8_t RESERVED_40[12]; __IO uint32_t HW_OCOTP_GP76; /**< Value of OTP Bank25 Word6 (GP7), offset: 0x10E0 */ uint8_t RESERVED_41[12]; __IO uint32_t HW_OCOTP_GP77; /**< Value of OTP Bank25 Word7 (GP7), offset: 0x10F0 */ uint8_t RESERVED_42[12]; __IO uint32_t HW_OCOTP_GP80; /**< Value of OTP Bank26 Word0 (GP8), offset: 0x1100 */ uint8_t RESERVED_43[12]; __IO uint32_t HW_OCOTP_GP81; /**< Value of OTP Bank26 Word1 (GP8), offset: 0x1110 */ uint8_t RESERVED_44[12]; __IO uint32_t HW_OCOTP_GP82; /**< Value of OTP Bank26 Word2 (GP8), offset: 0x1120 */ uint8_t RESERVED_45[12]; __IO uint32_t HW_OCOTP_GP83; /**< Value of OTP Bank26 Word3 (GP8), offset: 0x1130 */ uint8_t RESERVED_46[12]; __IO uint32_t HW_OCOTP_GP84; /**< Value of OTP Bank26 Word4 (GP8), offset: 0x1140 */ uint8_t RESERVED_47[12]; __IO uint32_t HW_OCOTP_GP85; /**< Value of OTP Bank26 Word5 (GP8), offset: 0x1150 */ uint8_t RESERVED_48[12]; __IO uint32_t HW_OCOTP_GP86; /**< Value of OTP Bank26 Word6 (GP8), offset: 0x1160 */ uint8_t RESERVED_49[12]; __IO uint32_t HW_OCOTP_GP87; /**< Value of OTP Bank26 Word7 (GP8), offset: 0x1170 */ uint8_t RESERVED_50[12]; __IO uint32_t HW_OCOTP_GP90; /**< Value of OTP Bank27 Word0 (GP9), offset: 0x1180 */ uint8_t RESERVED_51[12]; __IO uint32_t HW_OCOTP_GP91; /**< Value of OTP Bank27 Word1 (GP9), offset: 0x1190 */ uint8_t RESERVED_52[12]; __IO uint32_t HW_OCOTP_GP92; /**< Value of OTP Bank27 Word2 (GP9), offset: 0x11A0 */ uint8_t RESERVED_53[12]; __IO uint32_t HW_OCOTP_GP93; /**< Value of OTP Bank27 Word3 (GP9), offset: 0x11B0 */ uint8_t RESERVED_54[12]; __IO uint32_t HW_OCOTP_GP94; /**< Value of OTP Bank27 Word4 (GP9), offset: 0x11C0 */ uint8_t RESERVED_55[12]; __IO uint32_t HW_OCOTP_GP95; /**< Value of OTP Bank27 Word5 (GP9), offset: 0x11D0 */ uint8_t RESERVED_56[12]; __IO uint32_t HW_OCOTP_GP96; /**< Value of OTP Bank27 Word6 (GP9), offset: 0x11E0 */ uint8_t RESERVED_57[12]; __IO uint32_t HW_OCOTP_GP97; /**< Value of OTP Bank27 Word7 (GP9), offset: 0x11F0 */ uint8_t RESERVED_58[124]; __IO uint32_t HW_OCOTP_GP107; /**< Value of OTP Bank28 Word7, offset: 0x1270 */ uint8_t RESERVED_59[12]; __IO uint32_t HW_OCOTP_OTFAD_KEY0; /**< OTP Controller OTFAD Key Register 0, offset: 0x1280 */ uint8_t RESERVED_60[12]; __IO uint32_t HW_OCOTP_OTFAD_KEY1; /**< OTP Controller OTFAD Key Register 1, offset: 0x1290 */ uint8_t RESERVED_61[12]; __IO uint32_t HW_OCOTP_OTFAD_KEY2; /**< OTP Controller OTFAD Key Register 2, offset: 0x12A0 */ uint8_t RESERVED_62[12]; __IO uint32_t HW_OCOTP_OTFAD_KEY3; /**< OTP Controller OTFAD Key Register 3, offset: 0x12B0 */ uint8_t RESERVED_63[12]; __IO uint32_t HW_OCOTP_OTFAD_CFG0; /**< OTP Controller OTFAD Configuration Register 0, offset: 0x12C0 */ uint8_t RESERVED_64[12]; __IO uint32_t HW_OCOTP_OTFAD_CFG1; /**< OTP Controller OTFAD Configuration Register 1, offset: 0x12D0 */ uint8_t RESERVED_65[12]; __IO uint32_t HW_OCOTP_OTFAD_CFG2; /**< OTP Controller OTFAD Configuration Register 2, offset: 0x12E0 */ uint8_t RESERVED_66[12]; __IO uint32_t HW_OCOTP_OTFAD_CFG3; /**< OTP Controller OTFAD Configuration Register 3, offset: 0x12F0 */ } OCOTP_CTRL_Type; /* ---------------------------------------------------------------------------- -- OCOTP_CTRL Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup OCOTP_CTRL_Register_Masks OCOTP_CTRL Register Masks * @{ */ /*! @name HW_OCOTP_CTRL - OTP Controller Control Register */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_CTRL_ADDR_MASK (0xFFU) #define OCOTP_CTRL_HW_OCOTP_CTRL_ADDR_SHIFT (0U) /*! ADDR - ADDRESS */ #define OCOTP_CTRL_HW_OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_HW_OCOTP_CTRL_ADDR_MASK) #define OCOTP_CTRL_HW_OCOTP_CTRL_BUSY_MASK (0x100U) #define OCOTP_CTRL_HW_OCOTP_CTRL_BUSY_SHIFT (8U) /*! BUSY - BUSY */ #define OCOTP_CTRL_HW_OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_HW_OCOTP_CTRL_BUSY_MASK) #define OCOTP_CTRL_HW_OCOTP_CTRL_ERROR_MASK (0x200U) #define OCOTP_CTRL_HW_OCOTP_CTRL_ERROR_SHIFT (9U) /*! ERROR - ERROR */ #define OCOTP_CTRL_HW_OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_HW_OCOTP_CTRL_ERROR_MASK) #define OCOTP_CTRL_HW_OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U) #define OCOTP_CTRL_HW_OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U) /*! RELOAD_SHADOWS - RELOAD_SHADOWS */ #define OCOTP_CTRL_HW_OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_CTRL_RELOAD_SHADOWS_MASK) #define OCOTP_CTRL_HW_OCOTP_CTRL_SUPPADD_MASK (0x2000U) #define OCOTP_CTRL_HW_OCOTP_CTRL_SUPPADD_SHIFT (13U) /*! SUPPADD - Supplementary Address */ #define OCOTP_CTRL_HW_OCOTP_CTRL_SUPPADD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_CTRL_SUPPADD_SHIFT)) & OCOTP_CTRL_HW_OCOTP_CTRL_SUPPADD_MASK) #define OCOTP_CTRL_HW_OCOTP_CTRL_WORDLOCK_MASK (0x4000U) #define OCOTP_CTRL_HW_OCOTP_CTRL_WORDLOCK_SHIFT (14U) /*! WORDLOCK - WORDLOCK */ #define OCOTP_CTRL_HW_OCOTP_CTRL_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_CTRL_WORDLOCK_SHIFT)) & OCOTP_CTRL_HW_OCOTP_CTRL_WORDLOCK_MASK) #define OCOTP_CTRL_HW_OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) #define OCOTP_CTRL_HW_OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) /*! WR_UNLOCK - Write Unlock * 0b0000000000000000..OTP write accesses are locked. * 0b0011111001110111..OPT write access is unlocked. */ #define OCOTP_CTRL_HW_OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_HW_OCOTP_CTRL_WR_UNLOCK_MASK) /*! @} */ /*! @name HW_OCOTP_PDN - OTP Controller PDN Register */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_PDN_PDN_MASK (0x1U) #define OCOTP_CTRL_HW_OCOTP_PDN_PDN_SHIFT (0U) /*! PDN - PDN */ #define OCOTP_CTRL_HW_OCOTP_PDN_PDN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_PDN_PDN_SHIFT)) & OCOTP_CTRL_HW_OCOTP_PDN_PDN_MASK) /*! @} */ /*! @name HW_OCOTP_DATA - OTP Controller Write Data Register */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_DATA_DATA_SHIFT (0U) /*! DATA - DATA */ #define OCOTP_CTRL_HW_OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_DATA_DATA_SHIFT)) & OCOTP_CTRL_HW_OCOTP_DATA_DATA_MASK) /*! @} */ /*! @name HW_OCOTP_READ_CTRL - OTP Controller Read Control Register */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) #define OCOTP_CTRL_HW_OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) /*! READ_FUSE - READ_FUSE */ #define OCOTP_CTRL_HW_OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_CTRL_HW_OCOTP_READ_CTRL_READ_FUSE_MASK) /*! @} */ /*! @name HW_OCOTP_READ_FUSE_DATA - OTP Controller Read Fuse Data Register */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) /*! DATA - DATA */ #define OCOTP_CTRL_HW_OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_CTRL_HW_OCOTP_READ_FUSE_DATA_DATA_MASK) /*! @} */ /*! @name HW_OCOTP_SW_STICKY - OTP Controller Sticky Bit Register */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U) #define OCOTP_CTRL_HW_OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U) /*! FIELD_RETURN_LOCK - FIELD_RETURN_LOCK */ #define OCOTP_CTRL_HW_OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_CTRL_HW_OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK) /*! @} */ /*! @name HW_OCOTP_SCS - OTP Controller Software Controllable Signals Register */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_SCS_HAB_JDE_MASK (0x1U) #define OCOTP_CTRL_HW_OCOTP_SCS_HAB_JDE_SHIFT (0U) /*! HAB_JDE - HAB_JDE * 0b0..JTAG debugging is not enabled by the HAB (it may still be enabled by other mechanisms). * 0b1..JTAG debugging is enabled by the HAB (though this signal may be gated off). */ #define OCOTP_CTRL_HW_OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_CTRL_HW_OCOTP_SCS_HAB_JDE_MASK) #define OCOTP_CTRL_HW_OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU) #define OCOTP_CTRL_HW_OCOTP_SCS_SPARE_SHIFT (1U) /*! SPARE - SPARE */ #define OCOTP_CTRL_HW_OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_SCS_SPARE_SHIFT)) & OCOTP_CTRL_HW_OCOTP_SCS_SPARE_MASK) #define OCOTP_CTRL_HW_OCOTP_SCS_LOCK_MASK (0x80000000U) #define OCOTP_CTRL_HW_OCOTP_SCS_LOCK_SHIFT (31U) /*! LOCK - LOCK */ #define OCOTP_CTRL_HW_OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_SCS_LOCK_SHIFT)) & OCOTP_CTRL_HW_OCOTP_SCS_LOCK_MASK) /*! @} */ /*! @name HW_OCOTP_OUT_STATUS - OTP Controller Output Status Register */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_DOUT_40_32_MASK (0x1FFU) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_DOUT_40_32_SHIFT (0U) /*! DOUT_40_32 - DOUT_40_32 */ #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_DOUT_40_32(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OUT_STATUS_DOUT_40_32_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OUT_STATUS_DOUT_40_32_MASK) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_SEC_MASK (0x200U) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_SEC_SHIFT (9U) /*! SEC - SEC */ #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OUT_STATUS_SEC_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OUT_STATUS_SEC_MASK) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_DED_MASK (0x400U) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_DED_SHIFT (10U) /*! DED - DED */ #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OUT_STATUS_DED_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OUT_STATUS_DED_MASK) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_LOCKED_MASK (0x800U) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_LOCKED_SHIFT (11U) /*! LOCKED - LOCKED */ #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OUT_STATUS_LOCKED_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OUT_STATUS_LOCKED_MASK) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_PROGFAIL_MASK (0x1000U) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_PROGFAIL_SHIFT (12U) /*! PROGFAIL - PROGFAIL */ #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OUT_STATUS_PROGFAIL_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OUT_STATUS_PROGFAIL_MASK) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_ACK_MASK (0x2000U) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_ACK_SHIFT (13U) /*! ACK - ACK */ #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OUT_STATUS_ACK_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OUT_STATUS_ACK_MASK) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_PWOK_MASK (0x4000U) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_PWOK_SHIFT (14U) /*! PWOK - PWOK */ #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OUT_STATUS_PWOK_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OUT_STATUS_PWOK_MASK) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_FLAGSTATE_MASK (0x78000U) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_FLAGSTATE_SHIFT (15U) /*! FLAGSTATE - FLAGSTATE */ #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OUT_STATUS_FLAGSTATE_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OUT_STATUS_FLAGSTATE_MASK) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_SEC_RELOAD_MASK (0x80000U) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_SEC_RELOAD_SHIFT (19U) /*! SEC_RELOAD - SEC_RELOAD */ #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OUT_STATUS_SEC_RELOAD_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OUT_STATUS_SEC_RELOAD_MASK) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_DED_RELOAD_MASK (0x100000U) #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_DED_RELOAD_SHIFT (20U) /*! DED_RELOAD - DED_RELOAD */ #define OCOTP_CTRL_HW_OCOTP_OUT_STATUS_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OUT_STATUS_DED_RELOAD_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OUT_STATUS_DED_RELOAD_MASK) /*! @} */ /*! @name HW_OCOTP_STARTWORD - OTP Controller Output Startword Register */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_STARTWORD_STARTWORD_MASK (0xFFFFU) #define OCOTP_CTRL_HW_OCOTP_STARTWORD_STARTWORD_SHIFT (0U) /*! STARTWORD - STARTWORD */ #define OCOTP_CTRL_HW_OCOTP_STARTWORD_STARTWORD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_STARTWORD_STARTWORD_SHIFT)) & OCOTP_CTRL_HW_OCOTP_STARTWORD_STARTWORD_MASK) /*! @} */ /*! @name HW_OCOTP_VERSION - OTP Controller Version Register */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_VERSION_STEP_MASK (0xFFFFU) #define OCOTP_CTRL_HW_OCOTP_VERSION_STEP_SHIFT (0U) /*! STEP - STEP */ #define OCOTP_CTRL_HW_OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_VERSION_STEP_SHIFT)) & OCOTP_CTRL_HW_OCOTP_VERSION_STEP_MASK) #define OCOTP_CTRL_HW_OCOTP_VERSION_MINOR_MASK (0xFF0000U) #define OCOTP_CTRL_HW_OCOTP_VERSION_MINOR_SHIFT (16U) /*! MINOR - MINOR */ #define OCOTP_CTRL_HW_OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_CTRL_HW_OCOTP_VERSION_MINOR_MASK) #define OCOTP_CTRL_HW_OCOTP_VERSION_MAJOR_MASK (0xFF000000U) #define OCOTP_CTRL_HW_OCOTP_VERSION_MAJOR_SHIFT (24U) /*! MAJOR - MAJOR */ #define OCOTP_CTRL_HW_OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_CTRL_HW_OCOTP_VERSION_MAJOR_MASK) /*! @} */ /*! @name HW_OCOTP_LOCK0 - OTP Controller Lock Control Register 0 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_LOCK0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_LOCK0_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_LOCK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_LOCK0_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_LOCK0_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_LOCK1 - OTP Controller Lock Control Register 1 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_LOCK1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_LOCK1_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_LOCK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_LOCK1_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_LOCK1_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_LOCK2 - OTP Controller Lock Control Register 2 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_LOCK2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_LOCK2_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_LOCK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_LOCK2_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_LOCK2_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_CFG0 - Value of OTP Bank1 Word3 (ID Info.) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_CFG0_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_CFG0_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_CFG1 - Value of OTP Bank1 Word4 (ID Info.) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_CFG1_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_CFG1_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_CFG2 - Value of OTP Bank1 Word5 (ID Info.) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_CFG2_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_CFG2_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_CFG3 - Value of OTP Bank1 Word6 (ID Info.) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_CFG3_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_CFG3_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_CFG4 - Value of OTP Bank1 Word7 (ID Info.) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_CFG4_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_CFG4_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_BOOT0 - Value of OTP Bank2 Word0 (Boot Configuration Info.) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_BOOT0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_BOOT0_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_BOOT0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_BOOT0_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_BOOT0_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_BOOT3 - OTP Controller Boot Configuration Register 3 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_BOOT3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_BOOT3_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_BOOT3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_BOOT3_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_BOOT3_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_BOOT4 - OTP Controller Boot Configuration Register 4 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_BOOT4_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_BOOT4_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_BOOT4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_BOOT4_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_BOOT4_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_BOOT5 - OTP Controller Boot Configuration Register 5 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_BOOT5_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_BOOT5_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_BOOT5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_BOOT5_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_BOOT5_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_BOOT6 - OTP Controller Boot Configuration Register 6 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_BOOT6_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_BOOT6_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_BOOT6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_BOOT6_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_BOOT6_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_BOOT7 - OTP Controller Boot Configuration Register 7 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_BOOT7_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_BOOT7_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_BOOT7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_BOOT7_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_BOOT7_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_ANA1 - Value of OTP Bank3 Word5 (Memory Related Info.) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_ANA1_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_ANA1_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_ANA1_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_ANA2 - OTP Controller Analog Register 2 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_ANA2_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_ANA2_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_ANA2_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_ANA3 - OTP Controller Analog Register 3 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_ANA3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_ANA3_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_ANA3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_ANA3_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_ANA3_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_PAD_MISC1 - Value of OTP Bank9 Word1 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_PAD_MISC1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_PAD_MISC1_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_PAD_MISC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_PAD_MISC1_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_PAD_MISC1_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_PAD_MISC3 - Value of OTP Bank9 Word3 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_PAD_MISC3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_PAD_MISC3_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_PAD_MISC3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_PAD_MISC3_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_PAD_MISC3_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP60 - Value of OTP Bank24 Word0 (GP6) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP60_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP60_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP60_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP60_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP60_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP61 - Value of OTP Bank24 Word1 (GP6) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP61_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP61_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP61_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP61_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP61_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP62 - Value of OTP Bank24 Word2 (GP6) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP62_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP62_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP62_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP62_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP62_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP63 - Value of OTP Bank24 Word3 (GP6) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP63_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP63_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP63_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP63_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP63_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP64 - Value of OTP Bank24 Word4 (GP6) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP64_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP64_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP64_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP64_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP64_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP65 - Value of OTP Bank24 Word5 (GP6) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP65_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP65_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP65_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP65_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP65_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP66 - Value of OTP Bank24 Word6 (GP6) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP66_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP66_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP66_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP66_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP66_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP67 - Value of OTP Bank24 Word7 (GP6) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP67_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP67_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP67_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP67_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP67_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP70 - Value of OTP Bank25 Word0 (GP7) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP70_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP70_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP70_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP70_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP70_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP71 - Value of OTP Bank25 Word1 (GP7) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP71_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP71_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP71_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP71_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP71_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP72 - Value of OTP Bank25 Word2 (GP7) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP72_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP72_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP72_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP72_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP72_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP73 - Value of OTP Bank25 Word3 (GP7) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP73_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP73_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP73_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP73_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP73_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP74 - Value of OTP Bank25 Word4 (GP7) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP74_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP74_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP74_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP74_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP74_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP75 - Value of OTP Bank25 Word5 (GP7) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP75_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP75_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP75_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP75_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP75_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP76 - Value of OTP Bank25 Word6 (GP7) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP76_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP76_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP76_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP76_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP76_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP77 - Value of OTP Bank25 Word7 (GP7) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP77_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP77_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP77_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP77_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP77_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP80 - Value of OTP Bank26 Word0 (GP8) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP80_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP80_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP80_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP80_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP80_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP81 - Value of OTP Bank26 Word1 (GP8) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP81_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP81_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP81_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP81_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP81_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP82 - Value of OTP Bank26 Word2 (GP8) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP82_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP82_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP82_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP82_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP82_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP83 - Value of OTP Bank26 Word3 (GP8) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP83_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP83_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP83_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP83_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP83_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP84 - Value of OTP Bank26 Word4 (GP8) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP84_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP84_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP84_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP84_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP84_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP85 - Value of OTP Bank26 Word5 (GP8) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP85_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP85_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP85_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP85_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP85_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP86 - Value of OTP Bank26 Word6 (GP8) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP86_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP86_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP86_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP86_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP86_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP87 - Value of OTP Bank26 Word7 (GP8) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP87_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP87_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP87_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP87_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP87_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP90 - Value of OTP Bank27 Word0 (GP9) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP90_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP90_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP90_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP90_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP90_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP91 - Value of OTP Bank27 Word1 (GP9) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP91_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP91_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP91_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP91_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP91_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP92 - Value of OTP Bank27 Word2 (GP9) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP92_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP92_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP92_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP92_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP92_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP93 - Value of OTP Bank27 Word3 (GP9) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP93_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP93_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP93_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP93_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP93_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP94 - Value of OTP Bank27 Word4 (GP9) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP94_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP94_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP94_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP94_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP94_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP95 - Value of OTP Bank27 Word5 (GP9) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP95_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP95_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP95_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP95_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP95_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP96 - Value of OTP Bank27 Word6 (GP9) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP96_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP96_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP96_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP96_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP96_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP97 - Value of OTP Bank27 Word7 (GP9) */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP97_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP97_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP97_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP97_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP97_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_GP107 - Value of OTP Bank28 Word7 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_GP107_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_GP107_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_GP107_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_GP107_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_GP107_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_OTFAD_KEY0 - OTP Controller OTFAD Key Register 0 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY0_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OTFAD_KEY0_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OTFAD_KEY0_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_OTFAD_KEY1 - OTP Controller OTFAD Key Register 1 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY1_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OTFAD_KEY1_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OTFAD_KEY1_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_OTFAD_KEY2 - OTP Controller OTFAD Key Register 2 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY2_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OTFAD_KEY2_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OTFAD_KEY2_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_OTFAD_KEY3 - OTP Controller OTFAD Key Register 3 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY3_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OTFAD_KEY3_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OTFAD_KEY3_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_OTFAD_CFG0 - OTP Controller OTFAD Configuration Register 0 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_CFG0_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_OTFAD_CFG0_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OTFAD_CFG0_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OTFAD_CFG0_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_OTFAD_CFG1 - OTP Controller OTFAD Configuration Register 1 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_CFG1_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_OTFAD_CFG1_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OTFAD_CFG1_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OTFAD_CFG1_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_OTFAD_CFG2 - OTP Controller OTFAD Configuration Register 2 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_CFG2_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_OTFAD_CFG2_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OTFAD_CFG2_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OTFAD_CFG2_BITS_MASK) /*! @} */ /*! @name HW_OCOTP_OTFAD_CFG3 - OTP Controller OTFAD Configuration Register 3 */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_CFG3_BITS_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_OTFAD_CFG3_BITS_SHIFT (0U) /*! BITS - BITS */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OTFAD_CFG3_BITS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OTFAD_CFG3_BITS_MASK) /*! @} */ /*! * @} */ /* end of group OCOTP_CTRL_Register_Masks */ /* OCOTP_CTRL - Peripheral instance base addresses */ /** Peripheral OCOTP_CTRL base address */ #define OCOTP_CTRL_BASE (0x410A6000u) /** Peripheral OCOTP_CTRL base pointer */ #define OCOTP_CTRL ((OCOTP_CTRL_Type *)OCOTP_CTRL_BASE) /** Array initializer of OCOTP_CTRL peripheral base addresses */ #define OCOTP_CTRL_BASE_ADDRS { OCOTP_CTRL_BASE } /** Array initializer of OCOTP_CTRL peripheral base pointers */ #define OCOTP_CTRL_BASE_PTRS { OCOTP_CTRL } /* Backward compatibility */ /*! @name HW_OCOTP_OTFAD_KEY_BLOB_EN - OTP Controller OTFAD Key Blob Enable */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY_BLOB_EN_MASK (0x20U) #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY_BLOB_EN_SHIFT (5U) #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY_BLOB_EN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OTFAD_KEY_BLOB_EN_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OTFAD_KEY_BLOB_EN_MASK) /*! @} */ /*! @name HW_OCOTP_OTFAD_KEY_SCRAMBLE_EN - OTP Controller OTFAD Key Scramble Enable */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY_SCRAMBLE_EN_MASK (0x80U) #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY_SCRAMBLE_EN_SHIFT (7U) #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY_SCRAMBLE_EN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OTFAD_KEY_SCRAMBLE_EN_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OTFAD_KEY_SCRAMBLE_EN_MASK) /*! @} */ /*! @name HW_OCOTP_OTFAD_KEY0_SCRAMBLE - OTP Controller OTFAD Key Scramble 0 Align */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY0_SCRAMBLE_MASK (0x300U) #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY0_SCRAMBLE_SHIFT (8U) #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY0_SCRAMBLE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OTFAD_KEY0_SCRAMBLE_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OTFAD_KEY0_SCRAMBLE_MASK) /*! @} */ /*! @name HW_OCOTP_OTFAD_KEY1_SCRAMBLE - OTP Controller OTFAD Key Scramble 1 Align */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY1_SCRAMBLE_MASK (0xC00U) #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY1_SCRAMBLE_SHIFT (10U) #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY1_SCRAMBLE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OTFAD_KEY1_SCRAMBLE_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OTFAD_KEY1_SCRAMBLE_MASK) /*! @} */ /*! @name HW_OCOTP_OTFAD_KEY2_SCRAMBLE - OTP Controller OTFAD Key Scramble 2 Align */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY2_SCRAMBLE_MASK (0x3000U) #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY2_SCRAMBLE_SHIFT (12U) #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY2_SCRAMBLE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OTFAD_KEY2_SCRAMBLE_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OTFAD_KEY2_SCRAMBLE_MASK) /*! @} */ /*! @name HW_OCOTP_OTFAD_KEY3_SCRAMBLE - OTP Controller OTFAD Key Scramble 3 Align */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY3_SCRAMBLE_MASK (0xC000U) #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY3_SCRAMBLE_SHIFT (14U) #define OCOTP_CTRL_HW_OCOTP_OTFAD_KEY3_SCRAMBLE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OTFAD_KEY3_SCRAMBLE_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OTFAD_KEY3_SCRAMBLE_MASK) /*! @} */ /*! @name HW_OCOTP_OTFAD_RESTRICT_OTFAD_IPS - OTP Controller OTFAD Restrict OTFAD IPS */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_RESTRICT_OTFAD_IPS_MASK (0x10000U) #define OCOTP_CTRL_HW_OCOTP_OTFAD_RESTRICT_OTFAD_IPS_SHIFT (16U) #define OCOTP_CTRL_HW_OCOTP_OTFAD_RESTRICT_OTFAD_IPS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OTFAD_RESTRICT_OTFAD_IPS_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OTFAD_RESTRICT_OTFAD_IPS_MASK) /*! @} */ /*! @name HW_OCOTP_FORCE_INTERNAL_BT - OTP Controller Force Internal Boot */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_FORCE_INTERNAL_BT_MASK (0x1U) #define OCOTP_CTRL_HW_OCOTP_FORCE_INTERNAL_BT_SHIFT (0U) #define OCOTP_CTRL_HW_OCOTP_FORCE_INTERNAL_BT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_FORCE_INTERNAL_BT_SHIFT)) & OCOTP_CTRL_HW_OCOTP_FORCE_INTERNAL_BT_MASK) /*! @} */ /*! @name HW_OCOTP_SDP_DISABLE - OTP Controller SDP Disable */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_SDP_DISABLE_MASK (0x2U) #define OCOTP_CTRL_HW_OCOTP_SDP_DISABLE_SHIFT (1U) #define OCOTP_CTRL_HW_OCOTP_SDP_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_SDP_DISABLE_SHIFT)) & OCOTP_CTRL_HW_OCOTP_SDP_DISABLE_MASK) /*! @} */ /*! @name HW_OCOTP_SDP_READ_DISABLE - OTP Controller SDP Read Disable */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_SDP_READ_DISABLE_MASK (0x4U) #define OCOTP_CTRL_HW_OCOTP_SDP_READ_DISABLE_SHIFT (2U) #define OCOTP_CTRL_HW_OCOTP_SDP_READ_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_SDP_READ_DISABLE_SHIFT)) & OCOTP_CTRL_HW_OCOTP_SDP_READ_DISABLE_MASK) /*! @} */ /*! @name HW_OCOTP_SEC_CONFIG1 - OTP Controller SEC CONFIG[1] */ /*! @{ */ #define SEC_CONFIG_OPEN 0U #define SEC_CONFIG_CLOSED 1U #define OCOTP_CTRL_HW_OCOTP_SEC_CONFIG1_MASK (0x80000000U) #define OCOTP_CTRL_HW_OCOTP_SEC_CONFIG1_SHIFT (31U) #define OCOTP_CTRL_HW_OCOTP_SEC_CONFIG1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_SEC_CONFIG1_SHIFT)) & OCOTP_CTRL_HW_OCOTP_SEC_CONFIG1_MASK) /*! @} */ /*! @name HW_OCOTP_OTFAD_OTFAD_KEY_SCRAMBLE - OTP Controller OTFAD OTFAD Key Scramble */ /*! @{ */ #define OCOTP_CTRL_HW_OCOTP_OTFAD_OTFAD_KEY_SCRAMBLE_MASK (0xFFFFFFFFU) #define OCOTP_CTRL_HW_OCOTP_OTFAD_OTFAD_KEY_SCRAMBLE_SHIFT (0U) #define OCOTP_CTRL_HW_OCOTP_OTFAD_OTFAD_KEY_SCRAMBLE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_HW_OCOTP_OTFAD_OTFAD_KEY_SCRAMBLE_SHIFT)) & OCOTP_CTRL_HW_OCOTP_OTFAD_OTFAD_KEY_SCRAMBLE_MASK) /*! @} */ /*! * @} */ /* end of group OCOTP_CTRL_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- OTFAD Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup OTFAD_Peripheral_Access_Layer OTFAD Peripheral Access Layer * @{ */ /** OTFAD - Register Layout Typedef */ typedef struct { __IO uint32_t CR; /**< Control Register, offset: 0x0 */ __I uint32_t SR; /**< Status Register, offset: 0x4 */ uint8_t RESERVED_0[248]; struct { /* offset: 0x100, array step: 0x40 */ __IO uint32_t KEY[4]; /**< AES Key Word, array offset: 0x100, array step: index*0x40, index2*0x4 */ __IO uint32_t CTR[2]; /**< AES Counter Word, array offset: 0x110, array step: index*0x40, index2*0x4 */ __IO uint32_t RGD_W0; /**< AES Region Descriptor Word0, array offset: 0x118, array step: 0x40 */ __IO uint32_t RGD_W1; /**< AES Region Descriptor Word1, array offset: 0x11C, array step: 0x40 */ uint8_t RESERVED_0[32]; } CTX[4]; } OTFAD_Type; /* ---------------------------------------------------------------------------- -- OTFAD Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup OTFAD_Register_Masks OTFAD Register Masks * @{ */ /*! @name CR - Control Register */ /*! @{ */ #define OTFAD_CR_FLDM_MASK (0x8U) #define OTFAD_CR_FLDM_SHIFT (3U) /*! FLDM - Force Logically Disabled Mode * 0b0..No effect on the operating mode. * 0b1..Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode. */ #define OTFAD_CR_FLDM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK) #define OTFAD_CR_RRAE_MASK (0x80U) #define OTFAD_CR_RRAE_SHIFT (7U) /*! RRAE - Restricted Register Access Enable * 0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally". * 0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI. */ #define OTFAD_CR_RRAE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK) #define OTFAD_CR_GE_MASK (0x80000000U) #define OTFAD_CR_GE_SHIFT (31U) /*! GE - Global OTFAD Enable * 0b0..OTFAD has decryption disabled. All data fetched by the QuadSPI bypasses OTFAD processing. * 0b1..OTFAD has decryption enabled, and processes data fetched by the QuadSPI as defined by the hardware configuration. */ #define OTFAD_CR_GE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK) /*! @} */ /*! @name SR - Status Register */ /*! @{ */ #define OTFAD_SR_MDPCP_MASK (0x2U) #define OTFAD_SR_MDPCP_SHIFT (1U) /*! MDPCP - MDPC Present */ #define OTFAD_SR_MDPCP(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MDPCP_SHIFT)) & OTFAD_SR_MDPCP_MASK) #define OTFAD_SR_MODE_MASK (0xCU) #define OTFAD_SR_MODE_SHIFT (2U) /*! MODE - Operating Mode * 0b00..Operating in Normal mode (NRM) * 0b01..Unused (reserved) * 0b10..Unused (reserved) * 0b11..Operating in Logically Disabled Mode (LDM) */ #define OTFAD_SR_MODE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MODE_SHIFT)) & OTFAD_SR_MODE_MASK) #define OTFAD_SR_NCTX_MASK (0xF0U) #define OTFAD_SR_NCTX_SHIFT (4U) /*! NCTX - Number of Contexts */ #define OTFAD_SR_NCTX(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_NCTX_SHIFT)) & OTFAD_SR_NCTX_MASK) #define OTFAD_SR_HRL_MASK (0xF000000U) #define OTFAD_SR_HRL_SHIFT (24U) /*! HRL - Hardware Revision Level */ #define OTFAD_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_HRL_SHIFT)) & OTFAD_SR_HRL_MASK) #define OTFAD_SR_RRAM_MASK (0x10000000U) #define OTFAD_SR_RRAM_SHIFT (28U) /*! RRAM - Restricted Register Access Mode * 0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally". * 0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI. */ #define OTFAD_SR_RRAM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK) #define OTFAD_SR_GEM_MASK (0x20000000U) #define OTFAD_SR_GEM_SHIFT (29U) /*! GEM - Global Enable Mode * 0b0..OTFAD is disabled. All data fetched by the QuadSPI bypasses OTFAD processing. * 0b1..OTFAD is enabled, and processes data fetched by the QuadSPI as defined by the hardware configuration. */ #define OTFAD_SR_GEM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_GEM_SHIFT)) & OTFAD_SR_GEM_MASK) /*! @} */ /*! @name KEY - AES Key Word */ /*! @{ */ #define OTFAD_KEY_KEY_MASK (0xFFFFFFFFU) #define OTFAD_KEY_KEY_SHIFT (0U) /*! KEY - AES Key */ #define OTFAD_KEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_KEY_KEY_SHIFT)) & OTFAD_KEY_KEY_MASK) /*! @} */ /* The count of OTFAD_KEY */ #define OTFAD_KEY_COUNT (4U) /* The count of OTFAD_KEY */ #define OTFAD_KEY_COUNT2 (4U) /*! @name CTR - AES Counter Word */ /*! @{ */ #define OTFAD_CTR_CTR_MASK (0xFFFFFFFFU) #define OTFAD_CTR_CTR_SHIFT (0U) /*! CTR - AES Counter */ #define OTFAD_CTR_CTR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTR_CTR_SHIFT)) & OTFAD_CTR_CTR_MASK) /*! @} */ /* The count of OTFAD_CTR */ #define OTFAD_CTR_COUNT (4U) /* The count of OTFAD_CTR */ #define OTFAD_CTR_COUNT2 (2U) /*! @name RGD_W0 - AES Region Descriptor Word0 */ /*! @{ */ #define OTFAD_RGD_W0_SRTADDR_MASK (0xFFFFFC00U) #define OTFAD_RGD_W0_SRTADDR_SHIFT (10U) /*! SRTADDR - Start Address */ #define OTFAD_RGD_W0_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W0_SRTADDR_SHIFT)) & OTFAD_RGD_W0_SRTADDR_MASK) /*! @} */ /* The count of OTFAD_RGD_W0 */ #define OTFAD_RGD_W0_COUNT (4U) /*! @name RGD_W1 - AES Region Descriptor Word1 */ /*! @{ */ #define OTFAD_RGD_W1_VLD_MASK (0x1U) #define OTFAD_RGD_W1_VLD_SHIFT (0U) /*! VLD - Valid * 0b0..Context is invalid. * 0b1..Context is valid. */ #define OTFAD_RGD_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_VLD_SHIFT)) & OTFAD_RGD_W1_VLD_MASK) #define OTFAD_RGD_W1_ADE_MASK (0x2U) #define OTFAD_RGD_W1_ADE_SHIFT (1U) /*! ADE - AES Decryption Enable. * 0b0..Bypass the fetched data. * 0b1..Perform the CTR-AES128 mode decryption on the fetched data. */ #define OTFAD_RGD_W1_ADE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ADE_SHIFT)) & OTFAD_RGD_W1_ADE_MASK) #define OTFAD_RGD_W1_RO_MASK (0x4U) #define OTFAD_RGD_W1_RO_SHIFT (2U) /*! RO - Read-Only * 0b0..The context registers can be accessed normally (as defined by SR[RRAM]). * 0b1..The context registers are read-only and accesses may be further restricted based on SR[RRAM]. */ #define OTFAD_RGD_W1_RO(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_RO_SHIFT)) & OTFAD_RGD_W1_RO_MASK) #define OTFAD_RGD_W1_ENDADDR_MASK (0xFFFFFC00U) #define OTFAD_RGD_W1_ENDADDR_SHIFT (10U) /*! ENDADDR - End Address */ #define OTFAD_RGD_W1_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ENDADDR_SHIFT)) & OTFAD_RGD_W1_ENDADDR_MASK) /*! @} */ /* The count of OTFAD_RGD_W1 */ #define OTFAD_RGD_W1_COUNT (4U) /*! * @} */ /* end of group OTFAD_Register_Masks */ /* OTFAD - Peripheral instance base addresses */ /** Peripheral OTFAD base address */ #define OTFAD_BASE (0x410A5C00u) /** Peripheral OTFAD base pointer */ #define OTFAD ((OTFAD_Type *)OTFAD_BASE) /** Array initializer of OTFAD peripheral base addresses */ #define OTFAD_BASE_ADDRS { OTFAD_BASE } /** Array initializer of OTFAD peripheral base pointers */ #define OTFAD_BASE_PTRS { OTFAD } /*! * @} */ /* end of group OTFAD_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PCC0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PCC0_Peripheral_Access_Layer PCC0 Peripheral Access Layer * @{ */ /** PCC0 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[32]; __IO uint32_t PCC_DMA0; /**< PCC DMA0 Register, offset: 0x20 */ uint8_t RESERVED_1[24]; __IO uint32_t PCC_RGPIO2P0; /**< PCC RGPIO2P0 Register, offset: 0x3C */ uint8_t RESERVED_2[16]; __IO uint32_t PCC_XRDC; /**< PCC XRDC Register, offset: 0x50 */ uint8_t RESERVED_3[24]; __IO uint32_t PCC_SEMA42_0; /**< PCC SEMA42_0 Register, offset: 0x6C */ uint8_t RESERVED_4[16]; __IO uint32_t PCC_DMA_MUX0; /**< PCC DMA_MUX0 Register, offset: 0x80 */ uint8_t RESERVED_5[4]; __IO uint32_t PCC_MU_A; /**< PCC MU_A Register, offset: 0x88 */ uint8_t RESERVED_6[8]; __IO uint32_t PCC_WDOG0; /**< PCC WDOG0 Register, offset: 0x94 */ uint8_t RESERVED_7[12]; __IO uint32_t PCC_CRC; /**< PCC CRC Register, offset: 0xA4 */ __IO uint32_t PCC_LTC; /**< PCC LTC Register, offset: 0xA8 */ uint8_t RESERVED_8[4]; __IO uint32_t PCC_TRNG; /**< PCC TRNG Register, offset: 0xB0 */ __IO uint32_t PCC_LPIT0; /**< PCC LPIT0 Register, offset: 0xB4 */ __IO uint32_t PCC_LPTIMER0; /**< PCC LPTIMER0 Register, offset: 0xB8 */ __IO uint32_t PCC_LPTIMER1; /**< PCC LPTIMER1 Register, offset: 0xBC */ __IO uint32_t PCC_TPM0; /**< PCC TPM0 Register, offset: 0xC0 */ __IO uint32_t PCC_TPM1; /**< PCC TPM1 Register, offset: 0xC4 */ __IO uint32_t PCC_FLEXIO0; /**< PCC FLEXIO0 Register, offset: 0xC8 */ __IO uint32_t PCC_LPI2C0; /**< PCC LPI2C0 Register, offset: 0xCC */ __IO uint32_t PCC_LPI2C1; /**< PCC LPI2C1 Register, offset: 0xD0 */ __IO uint32_t PCC_LPI2C2; /**< PCC LPI2C2 Register, offset: 0xD4 */ __IO uint32_t PCC_LPI2C3; /**< PCC LPI2C3 Register, offset: 0xD8 */ __IO uint32_t PCC_SAI0; /**< PCC SAI0 Register, offset: 0xDC */ __IO uint32_t PCC_LPSPI0; /**< PCC LPSPI0 Register, offset: 0xE0 */ __IO uint32_t PCC_LPSPI1; /**< PCC LPSPI1 Register, offset: 0xE4 */ __IO uint32_t PCC_LPUART0; /**< PCC LPUART0 Register, offset: 0xE8 */ __IO uint32_t PCC_LPUART1; /**< PCC LPUART1 Register, offset: 0xEC */ uint8_t RESERVED_9[12]; __IO uint32_t PCC_PCTLA; /**< PCC PCTLA Register, offset: 0xFC */ __IO uint32_t PCC_PCTLB; /**< PCC PCTLB Register, offset: 0x100 */ __IO uint32_t PCC_ADC0; /**< PCC ADC0 Register, offset: 0x104 */ __IO uint32_t PCC_CMP0; /**< PCC CMP0 Register, offset: 0x108 */ __IO uint32_t PCC_CMP1; /**< PCC CMP1 Register, offset: 0x10C */ __IO uint32_t PCC_DAC0; /**< PCC DAC0 Register, offset: 0x110 */ __IO uint32_t PCC_DAC1; /**< PCC DAC1 Register, offset: 0x114 */ uint8_t RESERVED_10[168]; __IO uint32_t PCC_SNVS; /**< PCC SNVS Register, offset: 0x1C0 */ } PCC0_Type; /* ---------------------------------------------------------------------------- -- PCC0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PCC0_Register_Masks PCC0 Register Masks * @{ */ /*! @name PCC_DMA0 - PCC DMA0 Register */ /*! @{ */ #define PCC0_PCC_DMA0_INUSE_MASK (0x20000000U) #define PCC0_PCC_DMA0_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_DMA0_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_INUSE_SHIFT)) & PCC0_PCC_DMA0_INUSE_MASK) #define PCC0_PCC_DMA0_CGC_MASK (0x40000000U) #define PCC0_PCC_DMA0_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_DMA0_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_CGC_SHIFT)) & PCC0_PCC_DMA0_CGC_MASK) #define PCC0_PCC_DMA0_PR_MASK (0x80000000U) #define PCC0_PCC_DMA0_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_DMA0_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA0_PR_SHIFT)) & PCC0_PCC_DMA0_PR_MASK) /*! @} */ /*! @name PCC_RGPIO2P0 - PCC RGPIO2P0 Register */ /*! @{ */ #define PCC0_PCC_RGPIO2P0_INUSE_MASK (0x20000000U) #define PCC0_PCC_RGPIO2P0_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_RGPIO2P0_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_RGPIO2P0_INUSE_SHIFT)) & PCC0_PCC_RGPIO2P0_INUSE_MASK) #define PCC0_PCC_RGPIO2P0_CGC_MASK (0x40000000U) #define PCC0_PCC_RGPIO2P0_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_RGPIO2P0_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_RGPIO2P0_CGC_SHIFT)) & PCC0_PCC_RGPIO2P0_CGC_MASK) #define PCC0_PCC_RGPIO2P0_PR_MASK (0x80000000U) #define PCC0_PCC_RGPIO2P0_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_RGPIO2P0_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_RGPIO2P0_PR_SHIFT)) & PCC0_PCC_RGPIO2P0_PR_MASK) /*! @} */ /*! @name PCC_XRDC - PCC XRDC Register */ /*! @{ */ #define PCC0_PCC_XRDC_INUSE_MASK (0x20000000U) #define PCC0_PCC_XRDC_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_XRDC_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_XRDC_INUSE_SHIFT)) & PCC0_PCC_XRDC_INUSE_MASK) #define PCC0_PCC_XRDC_CGC_MASK (0x40000000U) #define PCC0_PCC_XRDC_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_XRDC_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_XRDC_CGC_SHIFT)) & PCC0_PCC_XRDC_CGC_MASK) #define PCC0_PCC_XRDC_PR_MASK (0x80000000U) #define PCC0_PCC_XRDC_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_XRDC_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_XRDC_PR_SHIFT)) & PCC0_PCC_XRDC_PR_MASK) /*! @} */ /*! @name PCC_SEMA42_0 - PCC SEMA42_0 Register */ /*! @{ */ #define PCC0_PCC_SEMA42_0_INUSE_MASK (0x20000000U) #define PCC0_PCC_SEMA42_0_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_SEMA42_0_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_SEMA42_0_INUSE_SHIFT)) & PCC0_PCC_SEMA42_0_INUSE_MASK) #define PCC0_PCC_SEMA42_0_CGC_MASK (0x40000000U) #define PCC0_PCC_SEMA42_0_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_SEMA42_0_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_SEMA42_0_CGC_SHIFT)) & PCC0_PCC_SEMA42_0_CGC_MASK) #define PCC0_PCC_SEMA42_0_PR_MASK (0x80000000U) #define PCC0_PCC_SEMA42_0_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_SEMA42_0_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_SEMA42_0_PR_SHIFT)) & PCC0_PCC_SEMA42_0_PR_MASK) /*! @} */ /*! @name PCC_DMA_MUX0 - PCC DMA_MUX0 Register */ /*! @{ */ #define PCC0_PCC_DMA_MUX0_INUSE_MASK (0x20000000U) #define PCC0_PCC_DMA_MUX0_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_DMA_MUX0_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA_MUX0_INUSE_SHIFT)) & PCC0_PCC_DMA_MUX0_INUSE_MASK) #define PCC0_PCC_DMA_MUX0_CGC_MASK (0x40000000U) #define PCC0_PCC_DMA_MUX0_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_DMA_MUX0_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA_MUX0_CGC_SHIFT)) & PCC0_PCC_DMA_MUX0_CGC_MASK) #define PCC0_PCC_DMA_MUX0_PR_MASK (0x80000000U) #define PCC0_PCC_DMA_MUX0_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_DMA_MUX0_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DMA_MUX0_PR_SHIFT)) & PCC0_PCC_DMA_MUX0_PR_MASK) /*! @} */ /*! @name PCC_MU_A - PCC MU_A Register */ /*! @{ */ #define PCC0_PCC_MU_A_INUSE_MASK (0x20000000U) #define PCC0_PCC_MU_A_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_MU_A_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_MU_A_INUSE_SHIFT)) & PCC0_PCC_MU_A_INUSE_MASK) #define PCC0_PCC_MU_A_CGC_MASK (0x40000000U) #define PCC0_PCC_MU_A_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_MU_A_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_MU_A_CGC_SHIFT)) & PCC0_PCC_MU_A_CGC_MASK) #define PCC0_PCC_MU_A_PR_MASK (0x80000000U) #define PCC0_PCC_MU_A_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_MU_A_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_MU_A_PR_SHIFT)) & PCC0_PCC_MU_A_PR_MASK) /*! @} */ /*! @name PCC_WDOG0 - PCC WDOG0 Register */ /*! @{ */ #define PCC0_PCC_WDOG0_PCD_MASK (0x7U) #define PCC0_PCC_WDOG0_PCD_SHIFT (0U) /*! PCD - Peripheral Clock Divider Select * 0b000..Divide by 1. * 0b001..Divide by 2. * 0b010..Divide by 3. * 0b011..Divide by 4. * 0b100..Divide by 5. * 0b101..Divide by 6. * 0b110..Divide by 7. * 0b111..Divide by 8. */ #define PCC0_PCC_WDOG0_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG0_PCD_SHIFT)) & PCC0_PCC_WDOG0_PCD_MASK) #define PCC0_PCC_WDOG0_FRAC_MASK (0x8U) #define PCC0_PCC_WDOG0_FRAC_SHIFT (3U) /*! FRAC - Peripheral Clock Divider Fraction * 0b0..Fractional value is 0. * 0b1..Fractional value is 1. */ #define PCC0_PCC_WDOG0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG0_FRAC_SHIFT)) & PCC0_PCC_WDOG0_FRAC_MASK) #define PCC0_PCC_WDOG0_PCS_MASK (0x7000000U) #define PCC0_PCC_WDOG0_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC0_PCC_WDOG0_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG0_PCS_SHIFT)) & PCC0_PCC_WDOG0_PCS_MASK) #define PCC0_PCC_WDOG0_INUSE_MASK (0x20000000U) #define PCC0_PCC_WDOG0_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_WDOG0_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG0_INUSE_SHIFT)) & PCC0_PCC_WDOG0_INUSE_MASK) #define PCC0_PCC_WDOG0_CGC_MASK (0x40000000U) #define PCC0_PCC_WDOG0_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_WDOG0_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG0_CGC_SHIFT)) & PCC0_PCC_WDOG0_CGC_MASK) #define PCC0_PCC_WDOG0_PR_MASK (0x80000000U) #define PCC0_PCC_WDOG0_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_WDOG0_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_WDOG0_PR_SHIFT)) & PCC0_PCC_WDOG0_PR_MASK) /*! @} */ /*! @name PCC_CRC - PCC CRC Register */ /*! @{ */ #define PCC0_PCC_CRC_INUSE_MASK (0x20000000U) #define PCC0_PCC_CRC_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_CRC_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_CRC_INUSE_SHIFT)) & PCC0_PCC_CRC_INUSE_MASK) #define PCC0_PCC_CRC_CGC_MASK (0x40000000U) #define PCC0_PCC_CRC_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_CRC_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_CRC_CGC_SHIFT)) & PCC0_PCC_CRC_CGC_MASK) #define PCC0_PCC_CRC_PR_MASK (0x80000000U) #define PCC0_PCC_CRC_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_CRC_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_CRC_PR_SHIFT)) & PCC0_PCC_CRC_PR_MASK) /*! @} */ /*! @name PCC_LTC - PCC LTC Register */ /*! @{ */ #define PCC0_PCC_LTC_INUSE_MASK (0x20000000U) #define PCC0_PCC_LTC_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_LTC_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LTC_INUSE_SHIFT)) & PCC0_PCC_LTC_INUSE_MASK) #define PCC0_PCC_LTC_CGC_MASK (0x40000000U) #define PCC0_PCC_LTC_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_LTC_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LTC_CGC_SHIFT)) & PCC0_PCC_LTC_CGC_MASK) #define PCC0_PCC_LTC_PR_MASK (0x80000000U) #define PCC0_PCC_LTC_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_LTC_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LTC_PR_SHIFT)) & PCC0_PCC_LTC_PR_MASK) /*! @} */ /*! @name PCC_TRNG - PCC TRNG Register */ /*! @{ */ #define PCC0_PCC_TRNG_INUSE_MASK (0x20000000U) #define PCC0_PCC_TRNG_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_TRNG_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRNG_INUSE_SHIFT)) & PCC0_PCC_TRNG_INUSE_MASK) #define PCC0_PCC_TRNG_CGC_MASK (0x40000000U) #define PCC0_PCC_TRNG_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_TRNG_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRNG_CGC_SHIFT)) & PCC0_PCC_TRNG_CGC_MASK) #define PCC0_PCC_TRNG_PR_MASK (0x80000000U) #define PCC0_PCC_TRNG_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_TRNG_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TRNG_PR_SHIFT)) & PCC0_PCC_TRNG_PR_MASK) /*! @} */ /*! @name PCC_LPIT0 - PCC LPIT0 Register */ /*! @{ */ #define PCC0_PCC_LPIT0_PCS_MASK (0x7000000U) #define PCC0_PCC_LPIT0_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC0_PCC_LPIT0_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPIT0_PCS_SHIFT)) & PCC0_PCC_LPIT0_PCS_MASK) #define PCC0_PCC_LPIT0_INUSE_MASK (0x20000000U) #define PCC0_PCC_LPIT0_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_LPIT0_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPIT0_INUSE_SHIFT)) & PCC0_PCC_LPIT0_INUSE_MASK) #define PCC0_PCC_LPIT0_CGC_MASK (0x40000000U) #define PCC0_PCC_LPIT0_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_LPIT0_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPIT0_CGC_SHIFT)) & PCC0_PCC_LPIT0_CGC_MASK) #define PCC0_PCC_LPIT0_PR_MASK (0x80000000U) #define PCC0_PCC_LPIT0_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_LPIT0_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPIT0_PR_SHIFT)) & PCC0_PCC_LPIT0_PR_MASK) /*! @} */ /*! @name PCC_LPTIMER0 - PCC LPTIMER0 Register */ /*! @{ */ #define PCC0_PCC_LPTIMER0_INUSE_MASK (0x20000000U) #define PCC0_PCC_LPTIMER0_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_LPTIMER0_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPTIMER0_INUSE_SHIFT)) & PCC0_PCC_LPTIMER0_INUSE_MASK) #define PCC0_PCC_LPTIMER0_CGC_MASK (0x40000000U) #define PCC0_PCC_LPTIMER0_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_LPTIMER0_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPTIMER0_CGC_SHIFT)) & PCC0_PCC_LPTIMER0_CGC_MASK) #define PCC0_PCC_LPTIMER0_PR_MASK (0x80000000U) #define PCC0_PCC_LPTIMER0_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_LPTIMER0_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPTIMER0_PR_SHIFT)) & PCC0_PCC_LPTIMER0_PR_MASK) /*! @} */ /*! @name PCC_LPTIMER1 - PCC LPTIMER1 Register */ /*! @{ */ #define PCC0_PCC_LPTIMER1_INUSE_MASK (0x20000000U) #define PCC0_PCC_LPTIMER1_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_LPTIMER1_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPTIMER1_INUSE_SHIFT)) & PCC0_PCC_LPTIMER1_INUSE_MASK) #define PCC0_PCC_LPTIMER1_CGC_MASK (0x40000000U) #define PCC0_PCC_LPTIMER1_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_LPTIMER1_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPTIMER1_CGC_SHIFT)) & PCC0_PCC_LPTIMER1_CGC_MASK) #define PCC0_PCC_LPTIMER1_PR_MASK (0x80000000U) #define PCC0_PCC_LPTIMER1_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_LPTIMER1_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPTIMER1_PR_SHIFT)) & PCC0_PCC_LPTIMER1_PR_MASK) /*! @} */ /*! @name PCC_TPM0 - PCC TPM0 Register */ /*! @{ */ #define PCC0_PCC_TPM0_PCS_MASK (0x7000000U) #define PCC0_PCC_TPM0_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC0_PCC_TPM0_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TPM0_PCS_SHIFT)) & PCC0_PCC_TPM0_PCS_MASK) #define PCC0_PCC_TPM0_INUSE_MASK (0x20000000U) #define PCC0_PCC_TPM0_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_TPM0_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TPM0_INUSE_SHIFT)) & PCC0_PCC_TPM0_INUSE_MASK) #define PCC0_PCC_TPM0_CGC_MASK (0x40000000U) #define PCC0_PCC_TPM0_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_TPM0_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TPM0_CGC_SHIFT)) & PCC0_PCC_TPM0_CGC_MASK) #define PCC0_PCC_TPM0_PR_MASK (0x80000000U) #define PCC0_PCC_TPM0_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_TPM0_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TPM0_PR_SHIFT)) & PCC0_PCC_TPM0_PR_MASK) /*! @} */ /*! @name PCC_TPM1 - PCC TPM1 Register */ /*! @{ */ #define PCC0_PCC_TPM1_PCS_MASK (0x7000000U) #define PCC0_PCC_TPM1_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC0_PCC_TPM1_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TPM1_PCS_SHIFT)) & PCC0_PCC_TPM1_PCS_MASK) #define PCC0_PCC_TPM1_INUSE_MASK (0x20000000U) #define PCC0_PCC_TPM1_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_TPM1_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TPM1_INUSE_SHIFT)) & PCC0_PCC_TPM1_INUSE_MASK) #define PCC0_PCC_TPM1_CGC_MASK (0x40000000U) #define PCC0_PCC_TPM1_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_TPM1_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TPM1_CGC_SHIFT)) & PCC0_PCC_TPM1_CGC_MASK) #define PCC0_PCC_TPM1_PR_MASK (0x80000000U) #define PCC0_PCC_TPM1_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_TPM1_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_TPM1_PR_SHIFT)) & PCC0_PCC_TPM1_PR_MASK) /*! @} */ /*! @name PCC_FLEXIO0 - PCC FLEXIO0 Register */ /*! @{ */ #define PCC0_PCC_FLEXIO0_PCS_MASK (0x7000000U) #define PCC0_PCC_FLEXIO0_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC0_PCC_FLEXIO0_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_FLEXIO0_PCS_SHIFT)) & PCC0_PCC_FLEXIO0_PCS_MASK) #define PCC0_PCC_FLEXIO0_INUSE_MASK (0x20000000U) #define PCC0_PCC_FLEXIO0_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_FLEXIO0_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_FLEXIO0_INUSE_SHIFT)) & PCC0_PCC_FLEXIO0_INUSE_MASK) #define PCC0_PCC_FLEXIO0_CGC_MASK (0x40000000U) #define PCC0_PCC_FLEXIO0_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_FLEXIO0_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_FLEXIO0_CGC_SHIFT)) & PCC0_PCC_FLEXIO0_CGC_MASK) #define PCC0_PCC_FLEXIO0_PR_MASK (0x80000000U) #define PCC0_PCC_FLEXIO0_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_FLEXIO0_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_FLEXIO0_PR_SHIFT)) & PCC0_PCC_FLEXIO0_PR_MASK) /*! @} */ /*! @name PCC_LPI2C0 - PCC LPI2C0 Register */ /*! @{ */ #define PCC0_PCC_LPI2C0_PCS_MASK (0x7000000U) #define PCC0_PCC_LPI2C0_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC0_PCC_LPI2C0_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPI2C0_PCS_SHIFT)) & PCC0_PCC_LPI2C0_PCS_MASK) #define PCC0_PCC_LPI2C0_INUSE_MASK (0x20000000U) #define PCC0_PCC_LPI2C0_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_LPI2C0_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPI2C0_INUSE_SHIFT)) & PCC0_PCC_LPI2C0_INUSE_MASK) #define PCC0_PCC_LPI2C0_CGC_MASK (0x40000000U) #define PCC0_PCC_LPI2C0_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_LPI2C0_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPI2C0_CGC_SHIFT)) & PCC0_PCC_LPI2C0_CGC_MASK) #define PCC0_PCC_LPI2C0_PR_MASK (0x80000000U) #define PCC0_PCC_LPI2C0_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_LPI2C0_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPI2C0_PR_SHIFT)) & PCC0_PCC_LPI2C0_PR_MASK) /*! @} */ /*! @name PCC_LPI2C1 - PCC LPI2C1 Register */ /*! @{ */ #define PCC0_PCC_LPI2C1_PCS_MASK (0x7000000U) #define PCC0_PCC_LPI2C1_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC0_PCC_LPI2C1_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPI2C1_PCS_SHIFT)) & PCC0_PCC_LPI2C1_PCS_MASK) #define PCC0_PCC_LPI2C1_INUSE_MASK (0x20000000U) #define PCC0_PCC_LPI2C1_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_LPI2C1_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPI2C1_INUSE_SHIFT)) & PCC0_PCC_LPI2C1_INUSE_MASK) #define PCC0_PCC_LPI2C1_CGC_MASK (0x40000000U) #define PCC0_PCC_LPI2C1_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_LPI2C1_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPI2C1_CGC_SHIFT)) & PCC0_PCC_LPI2C1_CGC_MASK) #define PCC0_PCC_LPI2C1_PR_MASK (0x80000000U) #define PCC0_PCC_LPI2C1_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_LPI2C1_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPI2C1_PR_SHIFT)) & PCC0_PCC_LPI2C1_PR_MASK) /*! @} */ /*! @name PCC_LPI2C2 - PCC LPI2C2 Register */ /*! @{ */ #define PCC0_PCC_LPI2C2_PCS_MASK (0x7000000U) #define PCC0_PCC_LPI2C2_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC0_PCC_LPI2C2_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPI2C2_PCS_SHIFT)) & PCC0_PCC_LPI2C2_PCS_MASK) #define PCC0_PCC_LPI2C2_INUSE_MASK (0x20000000U) #define PCC0_PCC_LPI2C2_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_LPI2C2_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPI2C2_INUSE_SHIFT)) & PCC0_PCC_LPI2C2_INUSE_MASK) #define PCC0_PCC_LPI2C2_CGC_MASK (0x40000000U) #define PCC0_PCC_LPI2C2_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_LPI2C2_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPI2C2_CGC_SHIFT)) & PCC0_PCC_LPI2C2_CGC_MASK) #define PCC0_PCC_LPI2C2_PR_MASK (0x80000000U) #define PCC0_PCC_LPI2C2_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_LPI2C2_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPI2C2_PR_SHIFT)) & PCC0_PCC_LPI2C2_PR_MASK) /*! @} */ /*! @name PCC_LPI2C3 - PCC LPI2C3 Register */ /*! @{ */ #define PCC0_PCC_LPI2C3_PCS_MASK (0x7000000U) #define PCC0_PCC_LPI2C3_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC0_PCC_LPI2C3_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPI2C3_PCS_SHIFT)) & PCC0_PCC_LPI2C3_PCS_MASK) #define PCC0_PCC_LPI2C3_INUSE_MASK (0x20000000U) #define PCC0_PCC_LPI2C3_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_LPI2C3_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPI2C3_INUSE_SHIFT)) & PCC0_PCC_LPI2C3_INUSE_MASK) #define PCC0_PCC_LPI2C3_CGC_MASK (0x40000000U) #define PCC0_PCC_LPI2C3_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_LPI2C3_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPI2C3_CGC_SHIFT)) & PCC0_PCC_LPI2C3_CGC_MASK) #define PCC0_PCC_LPI2C3_PR_MASK (0x80000000U) #define PCC0_PCC_LPI2C3_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_LPI2C3_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPI2C3_PR_SHIFT)) & PCC0_PCC_LPI2C3_PR_MASK) /*! @} */ /*! @name PCC_SAI0 - PCC SAI0 Register */ /*! @{ */ #define PCC0_PCC_SAI0_PCD_MASK (0xFFFFU) #define PCC0_PCC_SAI0_PCD_SHIFT (0U) /*! PCD - Peripheral Clock Divider Select */ #define PCC0_PCC_SAI0_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_SAI0_PCD_SHIFT)) & PCC0_PCC_SAI0_PCD_MASK) #define PCC0_PCC_SAI0_FRAC_MASK (0xFF0000U) #define PCC0_PCC_SAI0_FRAC_SHIFT (16U) /*! FRAC - Peripheral Clock Divider Fraction * 0b00000000..Fractional value is 0. * 0b00000001..Fractional value is 1. */ #define PCC0_PCC_SAI0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_SAI0_FRAC_SHIFT)) & PCC0_PCC_SAI0_FRAC_MASK) #define PCC0_PCC_SAI0_PCS_MASK (0x7000000U) #define PCC0_PCC_SAI0_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. An external clock can be enabled for this peripheral. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC0_PCC_SAI0_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_SAI0_PCS_SHIFT)) & PCC0_PCC_SAI0_PCS_MASK) #define PCC0_PCC_SAI0_INUSE_MASK (0x20000000U) #define PCC0_PCC_SAI0_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_SAI0_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_SAI0_INUSE_SHIFT)) & PCC0_PCC_SAI0_INUSE_MASK) #define PCC0_PCC_SAI0_CGC_MASK (0x40000000U) #define PCC0_PCC_SAI0_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_SAI0_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_SAI0_CGC_SHIFT)) & PCC0_PCC_SAI0_CGC_MASK) #define PCC0_PCC_SAI0_PR_MASK (0x80000000U) #define PCC0_PCC_SAI0_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_SAI0_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_SAI0_PR_SHIFT)) & PCC0_PCC_SAI0_PR_MASK) /*! @} */ /*! @name PCC_LPSPI0 - PCC LPSPI0 Register */ /*! @{ */ #define PCC0_PCC_LPSPI0_PCS_MASK (0x7000000U) #define PCC0_PCC_LPSPI0_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC0_PCC_LPSPI0_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI0_PCS_SHIFT)) & PCC0_PCC_LPSPI0_PCS_MASK) #define PCC0_PCC_LPSPI0_INUSE_MASK (0x20000000U) #define PCC0_PCC_LPSPI0_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_LPSPI0_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI0_INUSE_SHIFT)) & PCC0_PCC_LPSPI0_INUSE_MASK) #define PCC0_PCC_LPSPI0_CGC_MASK (0x40000000U) #define PCC0_PCC_LPSPI0_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_LPSPI0_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI0_CGC_SHIFT)) & PCC0_PCC_LPSPI0_CGC_MASK) #define PCC0_PCC_LPSPI0_PR_MASK (0x80000000U) #define PCC0_PCC_LPSPI0_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_LPSPI0_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI0_PR_SHIFT)) & PCC0_PCC_LPSPI0_PR_MASK) /*! @} */ /*! @name PCC_LPSPI1 - PCC LPSPI1 Register */ /*! @{ */ #define PCC0_PCC_LPSPI1_PCS_MASK (0x7000000U) #define PCC0_PCC_LPSPI1_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC0_PCC_LPSPI1_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI1_PCS_SHIFT)) & PCC0_PCC_LPSPI1_PCS_MASK) #define PCC0_PCC_LPSPI1_INUSE_MASK (0x20000000U) #define PCC0_PCC_LPSPI1_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_LPSPI1_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI1_INUSE_SHIFT)) & PCC0_PCC_LPSPI1_INUSE_MASK) #define PCC0_PCC_LPSPI1_CGC_MASK (0x40000000U) #define PCC0_PCC_LPSPI1_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_LPSPI1_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI1_CGC_SHIFT)) & PCC0_PCC_LPSPI1_CGC_MASK) #define PCC0_PCC_LPSPI1_PR_MASK (0x80000000U) #define PCC0_PCC_LPSPI1_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_LPSPI1_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPSPI1_PR_SHIFT)) & PCC0_PCC_LPSPI1_PR_MASK) /*! @} */ /*! @name PCC_LPUART0 - PCC LPUART0 Register */ /*! @{ */ #define PCC0_PCC_LPUART0_PCS_MASK (0x7000000U) #define PCC0_PCC_LPUART0_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC0_PCC_LPUART0_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPUART0_PCS_SHIFT)) & PCC0_PCC_LPUART0_PCS_MASK) #define PCC0_PCC_LPUART0_INUSE_MASK (0x20000000U) #define PCC0_PCC_LPUART0_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_LPUART0_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPUART0_INUSE_SHIFT)) & PCC0_PCC_LPUART0_INUSE_MASK) #define PCC0_PCC_LPUART0_CGC_MASK (0x40000000U) #define PCC0_PCC_LPUART0_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_LPUART0_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPUART0_CGC_SHIFT)) & PCC0_PCC_LPUART0_CGC_MASK) #define PCC0_PCC_LPUART0_PR_MASK (0x80000000U) #define PCC0_PCC_LPUART0_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_LPUART0_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPUART0_PR_SHIFT)) & PCC0_PCC_LPUART0_PR_MASK) /*! @} */ /*! @name PCC_LPUART1 - PCC LPUART1 Register */ /*! @{ */ #define PCC0_PCC_LPUART1_PCS_MASK (0x7000000U) #define PCC0_PCC_LPUART1_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC0_PCC_LPUART1_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPUART1_PCS_SHIFT)) & PCC0_PCC_LPUART1_PCS_MASK) #define PCC0_PCC_LPUART1_INUSE_MASK (0x20000000U) #define PCC0_PCC_LPUART1_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_LPUART1_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPUART1_INUSE_SHIFT)) & PCC0_PCC_LPUART1_INUSE_MASK) #define PCC0_PCC_LPUART1_CGC_MASK (0x40000000U) #define PCC0_PCC_LPUART1_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_LPUART1_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPUART1_CGC_SHIFT)) & PCC0_PCC_LPUART1_CGC_MASK) #define PCC0_PCC_LPUART1_PR_MASK (0x80000000U) #define PCC0_PCC_LPUART1_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_LPUART1_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_LPUART1_PR_SHIFT)) & PCC0_PCC_LPUART1_PR_MASK) /*! @} */ /*! @name PCC_PCTLA - PCC PCTLA Register */ /*! @{ */ #define PCC0_PCC_PCTLA_INUSE_MASK (0x20000000U) #define PCC0_PCC_PCTLA_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_PCTLA_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_PCTLA_INUSE_SHIFT)) & PCC0_PCC_PCTLA_INUSE_MASK) #define PCC0_PCC_PCTLA_CGC_MASK (0x40000000U) #define PCC0_PCC_PCTLA_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_PCTLA_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_PCTLA_CGC_SHIFT)) & PCC0_PCC_PCTLA_CGC_MASK) #define PCC0_PCC_PCTLA_PR_MASK (0x80000000U) #define PCC0_PCC_PCTLA_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_PCTLA_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_PCTLA_PR_SHIFT)) & PCC0_PCC_PCTLA_PR_MASK) /*! @} */ /*! @name PCC_PCTLB - PCC PCTLB Register */ /*! @{ */ #define PCC0_PCC_PCTLB_INUSE_MASK (0x20000000U) #define PCC0_PCC_PCTLB_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_PCTLB_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_PCTLB_INUSE_SHIFT)) & PCC0_PCC_PCTLB_INUSE_MASK) #define PCC0_PCC_PCTLB_CGC_MASK (0x40000000U) #define PCC0_PCC_PCTLB_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_PCTLB_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_PCTLB_CGC_SHIFT)) & PCC0_PCC_PCTLB_CGC_MASK) #define PCC0_PCC_PCTLB_PR_MASK (0x80000000U) #define PCC0_PCC_PCTLB_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_PCTLB_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_PCTLB_PR_SHIFT)) & PCC0_PCC_PCTLB_PR_MASK) /*! @} */ /*! @name PCC_ADC0 - PCC ADC0 Register */ /*! @{ */ #define PCC0_PCC_ADC0_PCS_MASK (0x7000000U) #define PCC0_PCC_ADC0_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC0_PCC_ADC0_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_ADC0_PCS_SHIFT)) & PCC0_PCC_ADC0_PCS_MASK) #define PCC0_PCC_ADC0_INUSE_MASK (0x20000000U) #define PCC0_PCC_ADC0_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_ADC0_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_ADC0_INUSE_SHIFT)) & PCC0_PCC_ADC0_INUSE_MASK) #define PCC0_PCC_ADC0_CGC_MASK (0x40000000U) #define PCC0_PCC_ADC0_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_ADC0_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_ADC0_CGC_SHIFT)) & PCC0_PCC_ADC0_CGC_MASK) #define PCC0_PCC_ADC0_PR_MASK (0x80000000U) #define PCC0_PCC_ADC0_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_ADC0_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_ADC0_PR_SHIFT)) & PCC0_PCC_ADC0_PR_MASK) /*! @} */ /*! @name PCC_CMP0 - PCC CMP0 Register */ /*! @{ */ #define PCC0_PCC_CMP0_INUSE_MASK (0x20000000U) #define PCC0_PCC_CMP0_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_CMP0_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_CMP0_INUSE_SHIFT)) & PCC0_PCC_CMP0_INUSE_MASK) #define PCC0_PCC_CMP0_CGC_MASK (0x40000000U) #define PCC0_PCC_CMP0_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_CMP0_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_CMP0_CGC_SHIFT)) & PCC0_PCC_CMP0_CGC_MASK) #define PCC0_PCC_CMP0_PR_MASK (0x80000000U) #define PCC0_PCC_CMP0_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_CMP0_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_CMP0_PR_SHIFT)) & PCC0_PCC_CMP0_PR_MASK) /*! @} */ /*! @name PCC_CMP1 - PCC CMP1 Register */ /*! @{ */ #define PCC0_PCC_CMP1_INUSE_MASK (0x20000000U) #define PCC0_PCC_CMP1_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_CMP1_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_CMP1_INUSE_SHIFT)) & PCC0_PCC_CMP1_INUSE_MASK) #define PCC0_PCC_CMP1_CGC_MASK (0x40000000U) #define PCC0_PCC_CMP1_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_CMP1_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_CMP1_CGC_SHIFT)) & PCC0_PCC_CMP1_CGC_MASK) #define PCC0_PCC_CMP1_PR_MASK (0x80000000U) #define PCC0_PCC_CMP1_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_CMP1_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_CMP1_PR_SHIFT)) & PCC0_PCC_CMP1_PR_MASK) /*! @} */ /*! @name PCC_DAC0 - PCC DAC0 Register */ /*! @{ */ #define PCC0_PCC_DAC0_PCD_MASK (0x7U) #define PCC0_PCC_DAC0_PCD_SHIFT (0U) /*! PCD - Peripheral Clock Divider Select * 0b000..Divide by 1. * 0b001..Divide by 2. * 0b010..Divide by 3. * 0b011..Divide by 4. * 0b100..Divide by 5. * 0b101..Divide by 6. * 0b110..Divide by 7. * 0b111..Divide by 8. */ #define PCC0_PCC_DAC0_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC0_PCD_SHIFT)) & PCC0_PCC_DAC0_PCD_MASK) #define PCC0_PCC_DAC0_FRAC_MASK (0x8U) #define PCC0_PCC_DAC0_FRAC_SHIFT (3U) /*! FRAC - Peripheral Clock Divider Fraction * 0b0..Fractional value is 0. * 0b1..Fractional value is 1. */ #define PCC0_PCC_DAC0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC0_FRAC_SHIFT)) & PCC0_PCC_DAC0_FRAC_MASK) #define PCC0_PCC_DAC0_PCS_MASK (0x7000000U) #define PCC0_PCC_DAC0_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC0_PCC_DAC0_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC0_PCS_SHIFT)) & PCC0_PCC_DAC0_PCS_MASK) #define PCC0_PCC_DAC0_INUSE_MASK (0x20000000U) #define PCC0_PCC_DAC0_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_DAC0_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC0_INUSE_SHIFT)) & PCC0_PCC_DAC0_INUSE_MASK) #define PCC0_PCC_DAC0_CGC_MASK (0x40000000U) #define PCC0_PCC_DAC0_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_DAC0_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC0_CGC_SHIFT)) & PCC0_PCC_DAC0_CGC_MASK) #define PCC0_PCC_DAC0_PR_MASK (0x80000000U) #define PCC0_PCC_DAC0_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_DAC0_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC0_PR_SHIFT)) & PCC0_PCC_DAC0_PR_MASK) /*! @} */ /*! @name PCC_DAC1 - PCC DAC1 Register */ /*! @{ */ #define PCC0_PCC_DAC1_PCD_MASK (0x7U) #define PCC0_PCC_DAC1_PCD_SHIFT (0U) /*! PCD - Peripheral Clock Divider Select * 0b000..Divide by 1. * 0b001..Divide by 2. * 0b010..Divide by 3. * 0b011..Divide by 4. * 0b100..Divide by 5. * 0b101..Divide by 6. * 0b110..Divide by 7. * 0b111..Divide by 8. */ #define PCC0_PCC_DAC1_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC1_PCD_SHIFT)) & PCC0_PCC_DAC1_PCD_MASK) #define PCC0_PCC_DAC1_FRAC_MASK (0x8U) #define PCC0_PCC_DAC1_FRAC_SHIFT (3U) /*! FRAC - Peripheral Clock Divider Fraction * 0b0..Fractional value is 0. * 0b1..Fractional value is 1. */ #define PCC0_PCC_DAC1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC1_FRAC_SHIFT)) & PCC0_PCC_DAC1_FRAC_MASK) #define PCC0_PCC_DAC1_PCS_MASK (0x7000000U) #define PCC0_PCC_DAC1_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC0_PCC_DAC1_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC1_PCS_SHIFT)) & PCC0_PCC_DAC1_PCS_MASK) #define PCC0_PCC_DAC1_INUSE_MASK (0x20000000U) #define PCC0_PCC_DAC1_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_DAC1_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC1_INUSE_SHIFT)) & PCC0_PCC_DAC1_INUSE_MASK) #define PCC0_PCC_DAC1_CGC_MASK (0x40000000U) #define PCC0_PCC_DAC1_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_DAC1_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC1_CGC_SHIFT)) & PCC0_PCC_DAC1_CGC_MASK) #define PCC0_PCC_DAC1_PR_MASK (0x80000000U) #define PCC0_PCC_DAC1_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_DAC1_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_DAC1_PR_SHIFT)) & PCC0_PCC_DAC1_PR_MASK) /*! @} */ /*! @name PCC_SNVS - PCC SNVS Register */ /*! @{ */ #define PCC0_PCC_SNVS_INUSE_MASK (0x20000000U) #define PCC0_PCC_SNVS_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC0_PCC_SNVS_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_SNVS_INUSE_SHIFT)) & PCC0_PCC_SNVS_INUSE_MASK) #define PCC0_PCC_SNVS_CGC_MASK (0x40000000U) #define PCC0_PCC_SNVS_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC0_PCC_SNVS_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_SNVS_CGC_SHIFT)) & PCC0_PCC_SNVS_CGC_MASK) #define PCC0_PCC_SNVS_PR_MASK (0x80000000U) #define PCC0_PCC_SNVS_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC0_PCC_SNVS_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC0_PCC_SNVS_PR_SHIFT)) & PCC0_PCC_SNVS_PR_MASK) /*! @} */ /*! * @} */ /* end of group PCC0_Register_Masks */ /* PCC0 - Peripheral instance base addresses */ /** Peripheral PCC0 base address */ #define PCC0_BASE (0x41026000u) /** Peripheral PCC0 base pointer */ #define PCC0 ((PCC0_Type *)PCC0_BASE) /** Array initializer of PCC0 peripheral base addresses */ #define PCC0_BASE_ADDRS { PCC0_BASE } /** Array initializer of PCC0 peripheral base pointers */ #define PCC0_BASE_PTRS { PCC0 } /*! * @} */ /* end of group PCC0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PCC1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PCC1_Peripheral_Access_Layer PCC1 Peripheral Access Layer * @{ */ /** PCC1 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[80]; __IO uint32_t PCC_TPIU; /**< PCC TPIU Register, offset: 0x50 */ uint8_t RESERVED_1[64]; __IO uint32_t PCC_QSPI_OTFAD; /**< PCC QSPI_OTFAD Register, offset: 0x94 */ uint8_t RESERVED_2[8]; __IO uint32_t PCC_TPM2; /**< PCC TPM2 Register, offset: 0xA0 */ __IO uint32_t PCC_TPM3; /**< PCC TPM3 Register, offset: 0xA4 */ __IO uint32_t PCC_SAI1; /**< PCC SAI1 Register, offset: 0xA8 */ __IO uint32_t PCC_LPUART2; /**< PCC LPUART2 Register, offset: 0xAC */ __IO uint32_t PCC_LPUART3; /**< PCC LPUART3 Register, offset: 0xB0 */ __IO uint32_t PCC_ADC1; /**< PCC ADC1 Register, offset: 0xB4 */ } PCC1_Type; /* ---------------------------------------------------------------------------- -- PCC1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PCC1_Register_Masks PCC1 Register Masks * @{ */ /*! @name PCC_TPIU - PCC TPIU Register */ /*! @{ */ #define PCC1_PCC_TPIU_PCD_MASK (0x7U) #define PCC1_PCC_TPIU_PCD_SHIFT (0U) /*! PCD - Peripheral Clock Divider Select * 0b000..Divide by 1. * 0b001..Divide by 2. * 0b010..Divide by 3. * 0b011..Divide by 4. * 0b100..Divide by 5. * 0b101..Divide by 6. * 0b110..Divide by 7. * 0b111..Divide by 8. */ #define PCC1_PCC_TPIU_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPIU_PCD_SHIFT)) & PCC1_PCC_TPIU_PCD_MASK) #define PCC1_PCC_TPIU_FRAC_MASK (0x8U) #define PCC1_PCC_TPIU_FRAC_SHIFT (3U) /*! FRAC - Peripheral Clock Divider Fraction * 0b0..Fractional value is 0. * 0b1..Fractional value is 1. */ #define PCC1_PCC_TPIU_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPIU_FRAC_SHIFT)) & PCC1_PCC_TPIU_FRAC_MASK) #define PCC1_PCC_TPIU_PCS_MASK (0x7000000U) #define PCC1_PCC_TPIU_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC1_PCC_TPIU_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPIU_PCS_SHIFT)) & PCC1_PCC_TPIU_PCS_MASK) #define PCC1_PCC_TPIU_INUSE_MASK (0x20000000U) #define PCC1_PCC_TPIU_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC1_PCC_TPIU_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPIU_INUSE_SHIFT)) & PCC1_PCC_TPIU_INUSE_MASK) #define PCC1_PCC_TPIU_CGC_MASK (0x40000000U) #define PCC1_PCC_TPIU_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC1_PCC_TPIU_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPIU_CGC_SHIFT)) & PCC1_PCC_TPIU_CGC_MASK) #define PCC1_PCC_TPIU_PR_MASK (0x80000000U) #define PCC1_PCC_TPIU_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC1_PCC_TPIU_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPIU_PR_SHIFT)) & PCC1_PCC_TPIU_PR_MASK) /*! @} */ /*! @name PCC_QSPI_OTFAD - PCC QSPI_OTFAD Register */ /*! @{ */ #define PCC1_PCC_QSPI_OTFAD_PCD_MASK (0x7U) #define PCC1_PCC_QSPI_OTFAD_PCD_SHIFT (0U) /*! PCD - Peripheral Clock Divider Select * 0b000..Divide by 1. * 0b001..Divide by 2. * 0b010..Divide by 3. * 0b011..Divide by 4. * 0b100..Divide by 5. * 0b101..Divide by 6. * 0b110..Divide by 7. * 0b111..Divide by 8. */ #define PCC1_PCC_QSPI_OTFAD_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_QSPI_OTFAD_PCD_SHIFT)) & PCC1_PCC_QSPI_OTFAD_PCD_MASK) #define PCC1_PCC_QSPI_OTFAD_FRAC_MASK (0x8U) #define PCC1_PCC_QSPI_OTFAD_FRAC_SHIFT (3U) /*! FRAC - Peripheral Clock Divider Fraction * 0b0..Fractional value is 0. * 0b1..Fractional value is 1. */ #define PCC1_PCC_QSPI_OTFAD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_QSPI_OTFAD_FRAC_SHIFT)) & PCC1_PCC_QSPI_OTFAD_FRAC_MASK) #define PCC1_PCC_QSPI_OTFAD_PCS_MASK (0x7000000U) #define PCC1_PCC_QSPI_OTFAD_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC1_PCC_QSPI_OTFAD_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_QSPI_OTFAD_PCS_SHIFT)) & PCC1_PCC_QSPI_OTFAD_PCS_MASK) #define PCC1_PCC_QSPI_OTFAD_INUSE_MASK (0x20000000U) #define PCC1_PCC_QSPI_OTFAD_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC1_PCC_QSPI_OTFAD_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_QSPI_OTFAD_INUSE_SHIFT)) & PCC1_PCC_QSPI_OTFAD_INUSE_MASK) #define PCC1_PCC_QSPI_OTFAD_CGC_MASK (0x40000000U) #define PCC1_PCC_QSPI_OTFAD_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC1_PCC_QSPI_OTFAD_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_QSPI_OTFAD_CGC_SHIFT)) & PCC1_PCC_QSPI_OTFAD_CGC_MASK) #define PCC1_PCC_QSPI_OTFAD_PR_MASK (0x80000000U) #define PCC1_PCC_QSPI_OTFAD_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC1_PCC_QSPI_OTFAD_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_QSPI_OTFAD_PR_SHIFT)) & PCC1_PCC_QSPI_OTFAD_PR_MASK) /*! @} */ /*! @name PCC_TPM2 - PCC TPM2 Register */ /*! @{ */ #define PCC1_PCC_TPM2_PCS_MASK (0x7000000U) #define PCC1_PCC_TPM2_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC1_PCC_TPM2_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM2_PCS_SHIFT)) & PCC1_PCC_TPM2_PCS_MASK) #define PCC1_PCC_TPM2_INUSE_MASK (0x20000000U) #define PCC1_PCC_TPM2_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC1_PCC_TPM2_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM2_INUSE_SHIFT)) & PCC1_PCC_TPM2_INUSE_MASK) #define PCC1_PCC_TPM2_CGC_MASK (0x40000000U) #define PCC1_PCC_TPM2_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC1_PCC_TPM2_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM2_CGC_SHIFT)) & PCC1_PCC_TPM2_CGC_MASK) #define PCC1_PCC_TPM2_PR_MASK (0x80000000U) #define PCC1_PCC_TPM2_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC1_PCC_TPM2_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM2_PR_SHIFT)) & PCC1_PCC_TPM2_PR_MASK) /*! @} */ /*! @name PCC_TPM3 - PCC TPM3 Register */ /*! @{ */ #define PCC1_PCC_TPM3_PCS_MASK (0x7000000U) #define PCC1_PCC_TPM3_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC1_PCC_TPM3_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM3_PCS_SHIFT)) & PCC1_PCC_TPM3_PCS_MASK) #define PCC1_PCC_TPM3_INUSE_MASK (0x20000000U) #define PCC1_PCC_TPM3_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC1_PCC_TPM3_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM3_INUSE_SHIFT)) & PCC1_PCC_TPM3_INUSE_MASK) #define PCC1_PCC_TPM3_CGC_MASK (0x40000000U) #define PCC1_PCC_TPM3_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC1_PCC_TPM3_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM3_CGC_SHIFT)) & PCC1_PCC_TPM3_CGC_MASK) #define PCC1_PCC_TPM3_PR_MASK (0x80000000U) #define PCC1_PCC_TPM3_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC1_PCC_TPM3_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_TPM3_PR_SHIFT)) & PCC1_PCC_TPM3_PR_MASK) /*! @} */ /*! @name PCC_SAI1 - PCC SAI1 Register */ /*! @{ */ #define PCC1_PCC_SAI1_PCD_MASK (0xFFFFU) #define PCC1_PCC_SAI1_PCD_SHIFT (0U) /*! PCD - Peripheral Clock Divider Select */ #define PCC1_PCC_SAI1_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SAI1_PCD_SHIFT)) & PCC1_PCC_SAI1_PCD_MASK) #define PCC1_PCC_SAI1_FRAC_MASK (0xFF0000U) #define PCC1_PCC_SAI1_FRAC_SHIFT (16U) /*! FRAC - Peripheral Clock Divider Fraction * 0b00000000..Fractional value is 0. * 0b00000001..Fractional value is 1. */ #define PCC1_PCC_SAI1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SAI1_FRAC_SHIFT)) & PCC1_PCC_SAI1_FRAC_MASK) #define PCC1_PCC_SAI1_PCS_MASK (0x7000000U) #define PCC1_PCC_SAI1_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. An external clock can be enabled for this peripheral. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC1_PCC_SAI1_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SAI1_PCS_SHIFT)) & PCC1_PCC_SAI1_PCS_MASK) #define PCC1_PCC_SAI1_INUSE_MASK (0x20000000U) #define PCC1_PCC_SAI1_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC1_PCC_SAI1_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SAI1_INUSE_SHIFT)) & PCC1_PCC_SAI1_INUSE_MASK) #define PCC1_PCC_SAI1_CGC_MASK (0x40000000U) #define PCC1_PCC_SAI1_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC1_PCC_SAI1_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SAI1_CGC_SHIFT)) & PCC1_PCC_SAI1_CGC_MASK) #define PCC1_PCC_SAI1_PR_MASK (0x80000000U) #define PCC1_PCC_SAI1_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC1_PCC_SAI1_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_SAI1_PR_SHIFT)) & PCC1_PCC_SAI1_PR_MASK) /*! @} */ /*! @name PCC_LPUART2 - PCC LPUART2 Register */ /*! @{ */ #define PCC1_PCC_LPUART2_PCS_MASK (0x7000000U) #define PCC1_PCC_LPUART2_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC1_PCC_LPUART2_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART2_PCS_SHIFT)) & PCC1_PCC_LPUART2_PCS_MASK) #define PCC1_PCC_LPUART2_INUSE_MASK (0x20000000U) #define PCC1_PCC_LPUART2_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC1_PCC_LPUART2_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART2_INUSE_SHIFT)) & PCC1_PCC_LPUART2_INUSE_MASK) #define PCC1_PCC_LPUART2_CGC_MASK (0x40000000U) #define PCC1_PCC_LPUART2_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC1_PCC_LPUART2_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART2_CGC_SHIFT)) & PCC1_PCC_LPUART2_CGC_MASK) #define PCC1_PCC_LPUART2_PR_MASK (0x80000000U) #define PCC1_PCC_LPUART2_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC1_PCC_LPUART2_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART2_PR_SHIFT)) & PCC1_PCC_LPUART2_PR_MASK) /*! @} */ /*! @name PCC_LPUART3 - PCC LPUART3 Register */ /*! @{ */ #define PCC1_PCC_LPUART3_PCS_MASK (0x7000000U) #define PCC1_PCC_LPUART3_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC1_PCC_LPUART3_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART3_PCS_SHIFT)) & PCC1_PCC_LPUART3_PCS_MASK) #define PCC1_PCC_LPUART3_INUSE_MASK (0x20000000U) #define PCC1_PCC_LPUART3_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC1_PCC_LPUART3_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART3_INUSE_SHIFT)) & PCC1_PCC_LPUART3_INUSE_MASK) #define PCC1_PCC_LPUART3_CGC_MASK (0x40000000U) #define PCC1_PCC_LPUART3_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC1_PCC_LPUART3_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART3_CGC_SHIFT)) & PCC1_PCC_LPUART3_CGC_MASK) #define PCC1_PCC_LPUART3_PR_MASK (0x80000000U) #define PCC1_PCC_LPUART3_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC1_PCC_LPUART3_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_LPUART3_PR_SHIFT)) & PCC1_PCC_LPUART3_PR_MASK) /*! @} */ /*! @name PCC_ADC1 - PCC ADC1 Register */ /*! @{ */ #define PCC1_PCC_ADC1_PCS_MASK (0x7000000U) #define PCC1_PCC_ADC1_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC1_PCC_ADC1_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_ADC1_PCS_SHIFT)) & PCC1_PCC_ADC1_PCS_MASK) #define PCC1_PCC_ADC1_INUSE_MASK (0x20000000U) #define PCC1_PCC_ADC1_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC1_PCC_ADC1_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_ADC1_INUSE_SHIFT)) & PCC1_PCC_ADC1_INUSE_MASK) #define PCC1_PCC_ADC1_CGC_MASK (0x40000000U) #define PCC1_PCC_ADC1_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC1_PCC_ADC1_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_ADC1_CGC_SHIFT)) & PCC1_PCC_ADC1_CGC_MASK) #define PCC1_PCC_ADC1_PR_MASK (0x80000000U) #define PCC1_PCC_ADC1_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC1_PCC_ADC1_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC1_PCC_ADC1_PR_SHIFT)) & PCC1_PCC_ADC1_PR_MASK) /*! @} */ /*! * @} */ /* end of group PCC1_Register_Masks */ /* PCC1 - Peripheral instance base addresses */ /** Peripheral PCC1 base address */ #define PCC1_BASE (0x410B2000u) /** Peripheral PCC1 base pointer */ #define PCC1 ((PCC1_Type *)PCC1_BASE) /** Array initializer of PCC1 peripheral base addresses */ #define PCC1_BASE_ADDRS { PCC1_BASE } /** Array initializer of PCC1 peripheral base pointers */ #define PCC1_BASE_PTRS { PCC1 } /*! * @} */ /* end of group PCC1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PCC2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PCC2_Peripheral_Access_Layer PCC2 Peripheral Access Layer * @{ */ /** PCC2 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[32]; __IO uint32_t PCC_DMA1; /**< PCC DMA1 Register, offset: 0x20 */ uint8_t RESERVED_1[24]; __IO uint32_t PCC_RGPIO2P1; /**< PCC RGPIO2P1 Register, offset: 0x3C */ __IO uint32_t PCC_FLEXBUS; /**< PCC FLEXBUS Register, offset: 0x40 */ uint8_t RESERVED_2[40]; __IO uint32_t PCC_SEMA42_1; /**< PCC SEMA42_1 Register, offset: 0x6C */ uint8_t RESERVED_3[20]; __IO uint32_t PCC_DMA_MUX1; /**< PCC DMA_MUX1 Register, offset: 0x84 */ uint8_t RESERVED_4[8]; __IO uint32_t PCC_CAAM; /**< PCC CAAM Register, offset: 0x90 */ __IO uint32_t PCC_TPM4; /**< PCC TPM4 Register, offset: 0x94 */ __IO uint32_t PCC_TPM5; /**< PCC TPM5 Register, offset: 0x98 */ __IO uint32_t PCC_LPIT1; /**< PCC LPIT1 Register, offset: 0x9C */ uint8_t RESERVED_5[4]; __IO uint32_t PCC_LPSPI2; /**< PCC LPSPI2 Register, offset: 0xA4 */ __IO uint32_t PCC_LPSPI3; /**< PCC LPSPI3 Register, offset: 0xA8 */ __IO uint32_t PCC_LPI2C4; /**< PCC LPI2C4 Register, offset: 0xAC */ __IO uint32_t PCC_LPI2C5; /**< PCC LPI2C5 Register, offset: 0xB0 */ __IO uint32_t PCC_LPUART4; /**< PCC LPUART4 Register, offset: 0xB4 */ __IO uint32_t PCC_LPUART5; /**< PCC LPUART5 Register, offset: 0xB8 */ uint8_t RESERVED_6[8]; __IO uint32_t PCC_FLEXIO1; /**< PCC FLEXIO1 Register, offset: 0xC4 */ uint8_t RESERVED_7[4]; __IO uint32_t PCC_USB0; /**< PCC USB0 Register, offset: 0xCC */ uint32_t PCC_USB1; /**< PCC USB1 Register, offset: 0xD0 */ __IO uint32_t PCC_USB_PHY; /**< PCC USB_PHY Register, offset: 0xD4 */ uint32_t PCC_USB_PL301; /**< PCC USB_PL301 Register, offset: 0xD8 */ __IO uint32_t PCC_USDHC0; /**< PCC USDHC0 Register, offset: 0xDC */ __IO uint32_t PCC_USDHC1; /**< PCC USDHC1 Register, offset: 0xE0 */ uint8_t RESERVED_8[16]; __IO uint32_t PCC_WDOG1; /**< PCC WDOG1 Register, offset: 0xF4 */ uint8_t RESERVED_9[20]; __IO uint32_t PCC_WDOG2; /**< PCC WDOG2 Register, offset: 0x10C */ } PCC2_Type; /* ---------------------------------------------------------------------------- -- PCC2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PCC2_Register_Masks PCC2 Register Masks * @{ */ /*! @name PCC_DMA1 - PCC DMA1 Register */ /*! @{ */ #define PCC2_PCC_DMA1_INUSE_MASK (0x20000000U) #define PCC2_PCC_DMA1_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_DMA1_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_DMA1_INUSE_SHIFT)) & PCC2_PCC_DMA1_INUSE_MASK) #define PCC2_PCC_DMA1_CGC_MASK (0x40000000U) #define PCC2_PCC_DMA1_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_DMA1_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_DMA1_CGC_SHIFT)) & PCC2_PCC_DMA1_CGC_MASK) #define PCC2_PCC_DMA1_PR_MASK (0x80000000U) #define PCC2_PCC_DMA1_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_DMA1_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_DMA1_PR_SHIFT)) & PCC2_PCC_DMA1_PR_MASK) /*! @} */ /*! @name PCC_RGPIO2P1 - PCC RGPIO2P1 Register */ /*! @{ */ #define PCC2_PCC_RGPIO2P1_INUSE_MASK (0x20000000U) #define PCC2_PCC_RGPIO2P1_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_RGPIO2P1_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_RGPIO2P1_INUSE_SHIFT)) & PCC2_PCC_RGPIO2P1_INUSE_MASK) #define PCC2_PCC_RGPIO2P1_CGC_MASK (0x40000000U) #define PCC2_PCC_RGPIO2P1_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_RGPIO2P1_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_RGPIO2P1_CGC_SHIFT)) & PCC2_PCC_RGPIO2P1_CGC_MASK) #define PCC2_PCC_RGPIO2P1_PR_MASK (0x80000000U) #define PCC2_PCC_RGPIO2P1_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_RGPIO2P1_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_RGPIO2P1_PR_SHIFT)) & PCC2_PCC_RGPIO2P1_PR_MASK) /*! @} */ /*! @name PCC_FLEXBUS - PCC FLEXBUS Register */ /*! @{ */ #define PCC2_PCC_FLEXBUS_INUSE_MASK (0x20000000U) #define PCC2_PCC_FLEXBUS_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_FLEXBUS_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_FLEXBUS_INUSE_SHIFT)) & PCC2_PCC_FLEXBUS_INUSE_MASK) #define PCC2_PCC_FLEXBUS_CGC_MASK (0x40000000U) #define PCC2_PCC_FLEXBUS_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_FLEXBUS_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_FLEXBUS_CGC_SHIFT)) & PCC2_PCC_FLEXBUS_CGC_MASK) #define PCC2_PCC_FLEXBUS_PR_MASK (0x80000000U) #define PCC2_PCC_FLEXBUS_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_FLEXBUS_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_FLEXBUS_PR_SHIFT)) & PCC2_PCC_FLEXBUS_PR_MASK) /*! @} */ /*! @name PCC_SEMA42_1 - PCC SEMA42_1 Register */ /*! @{ */ #define PCC2_PCC_SEMA42_1_INUSE_MASK (0x20000000U) #define PCC2_PCC_SEMA42_1_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_SEMA42_1_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_SEMA42_1_INUSE_SHIFT)) & PCC2_PCC_SEMA42_1_INUSE_MASK) #define PCC2_PCC_SEMA42_1_CGC_MASK (0x40000000U) #define PCC2_PCC_SEMA42_1_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_SEMA42_1_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_SEMA42_1_CGC_SHIFT)) & PCC2_PCC_SEMA42_1_CGC_MASK) #define PCC2_PCC_SEMA42_1_PR_MASK (0x80000000U) #define PCC2_PCC_SEMA42_1_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_SEMA42_1_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_SEMA42_1_PR_SHIFT)) & PCC2_PCC_SEMA42_1_PR_MASK) /*! @} */ /*! @name PCC_DMA_MUX1 - PCC DMA_MUX1 Register */ /*! @{ */ #define PCC2_PCC_DMA_MUX1_INUSE_MASK (0x20000000U) #define PCC2_PCC_DMA_MUX1_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_DMA_MUX1_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_DMA_MUX1_INUSE_SHIFT)) & PCC2_PCC_DMA_MUX1_INUSE_MASK) #define PCC2_PCC_DMA_MUX1_CGC_MASK (0x40000000U) #define PCC2_PCC_DMA_MUX1_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_DMA_MUX1_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_DMA_MUX1_CGC_SHIFT)) & PCC2_PCC_DMA_MUX1_CGC_MASK) #define PCC2_PCC_DMA_MUX1_PR_MASK (0x80000000U) #define PCC2_PCC_DMA_MUX1_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_DMA_MUX1_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_DMA_MUX1_PR_SHIFT)) & PCC2_PCC_DMA_MUX1_PR_MASK) /*! @} */ /*! @name PCC_CAAM - PCC CAAM Register */ /*! @{ */ #define PCC2_PCC_CAAM_INUSE_MASK (0x20000000U) #define PCC2_PCC_CAAM_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_CAAM_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_CAAM_INUSE_SHIFT)) & PCC2_PCC_CAAM_INUSE_MASK) #define PCC2_PCC_CAAM_CGC_MASK (0x40000000U) #define PCC2_PCC_CAAM_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_CAAM_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_CAAM_CGC_SHIFT)) & PCC2_PCC_CAAM_CGC_MASK) #define PCC2_PCC_CAAM_PR_MASK (0x80000000U) #define PCC2_PCC_CAAM_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_CAAM_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_CAAM_PR_SHIFT)) & PCC2_PCC_CAAM_PR_MASK) /*! @} */ /*! @name PCC_TPM4 - PCC TPM4 Register */ /*! @{ */ #define PCC2_PCC_TPM4_PCS_MASK (0x7000000U) #define PCC2_PCC_TPM4_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC2_PCC_TPM4_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM4_PCS_SHIFT)) & PCC2_PCC_TPM4_PCS_MASK) #define PCC2_PCC_TPM4_INUSE_MASK (0x20000000U) #define PCC2_PCC_TPM4_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_TPM4_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM4_INUSE_SHIFT)) & PCC2_PCC_TPM4_INUSE_MASK) #define PCC2_PCC_TPM4_CGC_MASK (0x40000000U) #define PCC2_PCC_TPM4_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_TPM4_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM4_CGC_SHIFT)) & PCC2_PCC_TPM4_CGC_MASK) #define PCC2_PCC_TPM4_PR_MASK (0x80000000U) #define PCC2_PCC_TPM4_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_TPM4_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM4_PR_SHIFT)) & PCC2_PCC_TPM4_PR_MASK) /*! @} */ /*! @name PCC_TPM5 - PCC TPM5 Register */ /*! @{ */ #define PCC2_PCC_TPM5_PCS_MASK (0x7000000U) #define PCC2_PCC_TPM5_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC2_PCC_TPM5_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM5_PCS_SHIFT)) & PCC2_PCC_TPM5_PCS_MASK) #define PCC2_PCC_TPM5_INUSE_MASK (0x20000000U) #define PCC2_PCC_TPM5_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_TPM5_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM5_INUSE_SHIFT)) & PCC2_PCC_TPM5_INUSE_MASK) #define PCC2_PCC_TPM5_CGC_MASK (0x40000000U) #define PCC2_PCC_TPM5_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_TPM5_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM5_CGC_SHIFT)) & PCC2_PCC_TPM5_CGC_MASK) #define PCC2_PCC_TPM5_PR_MASK (0x80000000U) #define PCC2_PCC_TPM5_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_TPM5_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_TPM5_PR_SHIFT)) & PCC2_PCC_TPM5_PR_MASK) /*! @} */ /*! @name PCC_LPIT1 - PCC LPIT1 Register */ /*! @{ */ #define PCC2_PCC_LPIT1_PCS_MASK (0x7000000U) #define PCC2_PCC_LPIT1_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC2_PCC_LPIT1_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPIT1_PCS_SHIFT)) & PCC2_PCC_LPIT1_PCS_MASK) #define PCC2_PCC_LPIT1_INUSE_MASK (0x20000000U) #define PCC2_PCC_LPIT1_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_LPIT1_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPIT1_INUSE_SHIFT)) & PCC2_PCC_LPIT1_INUSE_MASK) #define PCC2_PCC_LPIT1_CGC_MASK (0x40000000U) #define PCC2_PCC_LPIT1_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_LPIT1_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPIT1_CGC_SHIFT)) & PCC2_PCC_LPIT1_CGC_MASK) #define PCC2_PCC_LPIT1_PR_MASK (0x80000000U) #define PCC2_PCC_LPIT1_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_LPIT1_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPIT1_PR_SHIFT)) & PCC2_PCC_LPIT1_PR_MASK) /*! @} */ /*! @name PCC_LPSPI2 - PCC LPSPI2 Register */ /*! @{ */ #define PCC2_PCC_LPSPI2_PCS_MASK (0x7000000U) #define PCC2_PCC_LPSPI2_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC2_PCC_LPSPI2_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI2_PCS_SHIFT)) & PCC2_PCC_LPSPI2_PCS_MASK) #define PCC2_PCC_LPSPI2_INUSE_MASK (0x20000000U) #define PCC2_PCC_LPSPI2_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_LPSPI2_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI2_INUSE_SHIFT)) & PCC2_PCC_LPSPI2_INUSE_MASK) #define PCC2_PCC_LPSPI2_CGC_MASK (0x40000000U) #define PCC2_PCC_LPSPI2_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_LPSPI2_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI2_CGC_SHIFT)) & PCC2_PCC_LPSPI2_CGC_MASK) #define PCC2_PCC_LPSPI2_PR_MASK (0x80000000U) #define PCC2_PCC_LPSPI2_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_LPSPI2_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI2_PR_SHIFT)) & PCC2_PCC_LPSPI2_PR_MASK) /*! @} */ /*! @name PCC_LPSPI3 - PCC LPSPI3 Register */ /*! @{ */ #define PCC2_PCC_LPSPI3_PCS_MASK (0x7000000U) #define PCC2_PCC_LPSPI3_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC2_PCC_LPSPI3_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI3_PCS_SHIFT)) & PCC2_PCC_LPSPI3_PCS_MASK) #define PCC2_PCC_LPSPI3_INUSE_MASK (0x20000000U) #define PCC2_PCC_LPSPI3_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_LPSPI3_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI3_INUSE_SHIFT)) & PCC2_PCC_LPSPI3_INUSE_MASK) #define PCC2_PCC_LPSPI3_CGC_MASK (0x40000000U) #define PCC2_PCC_LPSPI3_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_LPSPI3_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI3_CGC_SHIFT)) & PCC2_PCC_LPSPI3_CGC_MASK) #define PCC2_PCC_LPSPI3_PR_MASK (0x80000000U) #define PCC2_PCC_LPSPI3_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_LPSPI3_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPSPI3_PR_SHIFT)) & PCC2_PCC_LPSPI3_PR_MASK) /*! @} */ /*! @name PCC_LPI2C4 - PCC LPI2C4 Register */ /*! @{ */ #define PCC2_PCC_LPI2C4_PCS_MASK (0x7000000U) #define PCC2_PCC_LPI2C4_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC2_PCC_LPI2C4_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C4_PCS_SHIFT)) & PCC2_PCC_LPI2C4_PCS_MASK) #define PCC2_PCC_LPI2C4_INUSE_MASK (0x20000000U) #define PCC2_PCC_LPI2C4_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_LPI2C4_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C4_INUSE_SHIFT)) & PCC2_PCC_LPI2C4_INUSE_MASK) #define PCC2_PCC_LPI2C4_CGC_MASK (0x40000000U) #define PCC2_PCC_LPI2C4_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_LPI2C4_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C4_CGC_SHIFT)) & PCC2_PCC_LPI2C4_CGC_MASK) #define PCC2_PCC_LPI2C4_PR_MASK (0x80000000U) #define PCC2_PCC_LPI2C4_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_LPI2C4_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C4_PR_SHIFT)) & PCC2_PCC_LPI2C4_PR_MASK) /*! @} */ /*! @name PCC_LPI2C5 - PCC LPI2C5 Register */ /*! @{ */ #define PCC2_PCC_LPI2C5_PCS_MASK (0x7000000U) #define PCC2_PCC_LPI2C5_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC2_PCC_LPI2C5_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C5_PCS_SHIFT)) & PCC2_PCC_LPI2C5_PCS_MASK) #define PCC2_PCC_LPI2C5_INUSE_MASK (0x20000000U) #define PCC2_PCC_LPI2C5_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_LPI2C5_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C5_INUSE_SHIFT)) & PCC2_PCC_LPI2C5_INUSE_MASK) #define PCC2_PCC_LPI2C5_CGC_MASK (0x40000000U) #define PCC2_PCC_LPI2C5_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_LPI2C5_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C5_CGC_SHIFT)) & PCC2_PCC_LPI2C5_CGC_MASK) #define PCC2_PCC_LPI2C5_PR_MASK (0x80000000U) #define PCC2_PCC_LPI2C5_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_LPI2C5_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPI2C5_PR_SHIFT)) & PCC2_PCC_LPI2C5_PR_MASK) /*! @} */ /*! @name PCC_LPUART4 - PCC LPUART4 Register */ /*! @{ */ #define PCC2_PCC_LPUART4_PCS_MASK (0x7000000U) #define PCC2_PCC_LPUART4_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC2_PCC_LPUART4_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART4_PCS_SHIFT)) & PCC2_PCC_LPUART4_PCS_MASK) #define PCC2_PCC_LPUART4_INUSE_MASK (0x20000000U) #define PCC2_PCC_LPUART4_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_LPUART4_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART4_INUSE_SHIFT)) & PCC2_PCC_LPUART4_INUSE_MASK) #define PCC2_PCC_LPUART4_CGC_MASK (0x40000000U) #define PCC2_PCC_LPUART4_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_LPUART4_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART4_CGC_SHIFT)) & PCC2_PCC_LPUART4_CGC_MASK) #define PCC2_PCC_LPUART4_PR_MASK (0x80000000U) #define PCC2_PCC_LPUART4_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_LPUART4_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART4_PR_SHIFT)) & PCC2_PCC_LPUART4_PR_MASK) /*! @} */ /*! @name PCC_LPUART5 - PCC LPUART5 Register */ /*! @{ */ #define PCC2_PCC_LPUART5_PCS_MASK (0x7000000U) #define PCC2_PCC_LPUART5_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC2_PCC_LPUART5_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART5_PCS_SHIFT)) & PCC2_PCC_LPUART5_PCS_MASK) #define PCC2_PCC_LPUART5_INUSE_MASK (0x20000000U) #define PCC2_PCC_LPUART5_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_LPUART5_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART5_INUSE_SHIFT)) & PCC2_PCC_LPUART5_INUSE_MASK) #define PCC2_PCC_LPUART5_CGC_MASK (0x40000000U) #define PCC2_PCC_LPUART5_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_LPUART5_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART5_CGC_SHIFT)) & PCC2_PCC_LPUART5_CGC_MASK) #define PCC2_PCC_LPUART5_PR_MASK (0x80000000U) #define PCC2_PCC_LPUART5_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_LPUART5_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_LPUART5_PR_SHIFT)) & PCC2_PCC_LPUART5_PR_MASK) /*! @} */ /*! @name PCC_FLEXIO1 - PCC FLEXIO1 Register */ /*! @{ */ #define PCC2_PCC_FLEXIO1_PCS_MASK (0x7000000U) #define PCC2_PCC_FLEXIO1_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC2_PCC_FLEXIO1_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_FLEXIO1_PCS_SHIFT)) & PCC2_PCC_FLEXIO1_PCS_MASK) #define PCC2_PCC_FLEXIO1_INUSE_MASK (0x20000000U) #define PCC2_PCC_FLEXIO1_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_FLEXIO1_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_FLEXIO1_INUSE_SHIFT)) & PCC2_PCC_FLEXIO1_INUSE_MASK) #define PCC2_PCC_FLEXIO1_CGC_MASK (0x40000000U) #define PCC2_PCC_FLEXIO1_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_FLEXIO1_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_FLEXIO1_CGC_SHIFT)) & PCC2_PCC_FLEXIO1_CGC_MASK) #define PCC2_PCC_FLEXIO1_PR_MASK (0x80000000U) #define PCC2_PCC_FLEXIO1_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_FLEXIO1_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_FLEXIO1_PR_SHIFT)) & PCC2_PCC_FLEXIO1_PR_MASK) /*! @} */ /*! @name PCC_USB0 - PCC USB0 Register */ /*! @{ */ #define PCC2_PCC_USB0_PCD_MASK (0x7U) #define PCC2_PCC_USB0_PCD_SHIFT (0U) /*! PCD - Peripheral Clock Divider Select * 0b000..Divide by 1. * 0b001..Divide by 2. * 0b010..Divide by 3. * 0b011..Divide by 4. * 0b100..Divide by 5. * 0b101..Divide by 6. * 0b110..Divide by 7. * 0b111..Divide by 8. */ #define PCC2_PCC_USB0_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USB0_PCD_SHIFT)) & PCC2_PCC_USB0_PCD_MASK) #define PCC2_PCC_USB0_FRAC_MASK (0x8U) #define PCC2_PCC_USB0_FRAC_SHIFT (3U) /*! FRAC - Peripheral Clock Divider Fraction * 0b0..Fractional value is 0. * 0b1..Fractional value is 1. */ #define PCC2_PCC_USB0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USB0_FRAC_SHIFT)) & PCC2_PCC_USB0_FRAC_MASK) #define PCC2_PCC_USB0_PCS_MASK (0x7000000U) #define PCC2_PCC_USB0_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. An external clock can be enabled for this peripheral. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC2_PCC_USB0_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USB0_PCS_SHIFT)) & PCC2_PCC_USB0_PCS_MASK) #define PCC2_PCC_USB0_INUSE_MASK (0x20000000U) #define PCC2_PCC_USB0_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_USB0_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USB0_INUSE_SHIFT)) & PCC2_PCC_USB0_INUSE_MASK) #define PCC2_PCC_USB0_CGC_MASK (0x40000000U) #define PCC2_PCC_USB0_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_USB0_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USB0_CGC_SHIFT)) & PCC2_PCC_USB0_CGC_MASK) #define PCC2_PCC_USB0_PR_MASK (0x80000000U) #define PCC2_PCC_USB0_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_USB0_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USB0_PR_SHIFT)) & PCC2_PCC_USB0_PR_MASK) /*! @} */ /*! @name PCC_USB_PHY - PCC USB_PHY Register */ /*! @{ */ #define PCC2_PCC_USB_PHY_INUSE_MASK (0x20000000U) #define PCC2_PCC_USB_PHY_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_USB_PHY_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USB_PHY_INUSE_SHIFT)) & PCC2_PCC_USB_PHY_INUSE_MASK) #define PCC2_PCC_USB_PHY_CGC_MASK (0x40000000U) #define PCC2_PCC_USB_PHY_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_USB_PHY_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USB_PHY_CGC_SHIFT)) & PCC2_PCC_USB_PHY_CGC_MASK) #define PCC2_PCC_USB_PHY_PR_MASK (0x80000000U) #define PCC2_PCC_USB_PHY_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_USB_PHY_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USB_PHY_PR_SHIFT)) & PCC2_PCC_USB_PHY_PR_MASK) /*! @} */ /*! @name PCC_USDHC0 - PCC USDHC0 Register */ /*! @{ */ #define PCC2_PCC_USDHC0_PCD_MASK (0x7U) #define PCC2_PCC_USDHC0_PCD_SHIFT (0U) /*! PCD - Peripheral Clock Divider Select * 0b000..Divide by 1. * 0b001..Divide by 2. * 0b010..Divide by 3. * 0b011..Divide by 4. * 0b100..Divide by 5. * 0b101..Divide by 6. * 0b110..Divide by 7. * 0b111..Divide by 8. */ #define PCC2_PCC_USDHC0_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USDHC0_PCD_SHIFT)) & PCC2_PCC_USDHC0_PCD_MASK) #define PCC2_PCC_USDHC0_FRAC_MASK (0x8U) #define PCC2_PCC_USDHC0_FRAC_SHIFT (3U) /*! FRAC - Peripheral Clock Divider Fraction * 0b0..Fractional value is 0. * 0b1..Fractional value is 1. */ #define PCC2_PCC_USDHC0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USDHC0_FRAC_SHIFT)) & PCC2_PCC_USDHC0_FRAC_MASK) #define PCC2_PCC_USDHC0_PCS_MASK (0x7000000U) #define PCC2_PCC_USDHC0_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. An external clock can be enabled for this peripheral. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC2_PCC_USDHC0_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USDHC0_PCS_SHIFT)) & PCC2_PCC_USDHC0_PCS_MASK) #define PCC2_PCC_USDHC0_INUSE_MASK (0x20000000U) #define PCC2_PCC_USDHC0_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_USDHC0_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USDHC0_INUSE_SHIFT)) & PCC2_PCC_USDHC0_INUSE_MASK) #define PCC2_PCC_USDHC0_CGC_MASK (0x40000000U) #define PCC2_PCC_USDHC0_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_USDHC0_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USDHC0_CGC_SHIFT)) & PCC2_PCC_USDHC0_CGC_MASK) #define PCC2_PCC_USDHC0_PR_MASK (0x80000000U) #define PCC2_PCC_USDHC0_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_USDHC0_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USDHC0_PR_SHIFT)) & PCC2_PCC_USDHC0_PR_MASK) /*! @} */ /*! @name PCC_USDHC1 - PCC USDHC1 Register */ /*! @{ */ #define PCC2_PCC_USDHC1_PCD_MASK (0x7U) #define PCC2_PCC_USDHC1_PCD_SHIFT (0U) /*! PCD - Peripheral Clock Divider Select * 0b000..Divide by 1. * 0b001..Divide by 2. * 0b010..Divide by 3. * 0b011..Divide by 4. * 0b100..Divide by 5. * 0b101..Divide by 6. * 0b110..Divide by 7. * 0b111..Divide by 8. */ #define PCC2_PCC_USDHC1_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USDHC1_PCD_SHIFT)) & PCC2_PCC_USDHC1_PCD_MASK) #define PCC2_PCC_USDHC1_FRAC_MASK (0x8U) #define PCC2_PCC_USDHC1_FRAC_SHIFT (3U) /*! FRAC - Peripheral Clock Divider Fraction * 0b0..Fractional value is 0. * 0b1..Fractional value is 1. */ #define PCC2_PCC_USDHC1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USDHC1_FRAC_SHIFT)) & PCC2_PCC_USDHC1_FRAC_MASK) #define PCC2_PCC_USDHC1_PCS_MASK (0x7000000U) #define PCC2_PCC_USDHC1_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. An external clock can be enabled for this peripheral. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC2_PCC_USDHC1_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USDHC1_PCS_SHIFT)) & PCC2_PCC_USDHC1_PCS_MASK) #define PCC2_PCC_USDHC1_INUSE_MASK (0x20000000U) #define PCC2_PCC_USDHC1_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_USDHC1_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USDHC1_INUSE_SHIFT)) & PCC2_PCC_USDHC1_INUSE_MASK) #define PCC2_PCC_USDHC1_CGC_MASK (0x40000000U) #define PCC2_PCC_USDHC1_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_USDHC1_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USDHC1_CGC_SHIFT)) & PCC2_PCC_USDHC1_CGC_MASK) #define PCC2_PCC_USDHC1_PR_MASK (0x80000000U) #define PCC2_PCC_USDHC1_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_USDHC1_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_USDHC1_PR_SHIFT)) & PCC2_PCC_USDHC1_PR_MASK) /*! @} */ /*! @name PCC_WDOG1 - PCC WDOG1 Register */ /*! @{ */ #define PCC2_PCC_WDOG1_PCD_MASK (0x7U) #define PCC2_PCC_WDOG1_PCD_SHIFT (0U) /*! PCD - Peripheral Clock Divider Select * 0b000..Divide by 1. * 0b001..Divide by 2. * 0b010..Divide by 3. * 0b011..Divide by 4. * 0b100..Divide by 5. * 0b101..Divide by 6. * 0b110..Divide by 7. * 0b111..Divide by 8. */ #define PCC2_PCC_WDOG1_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG1_PCD_SHIFT)) & PCC2_PCC_WDOG1_PCD_MASK) #define PCC2_PCC_WDOG1_FRAC_MASK (0x8U) #define PCC2_PCC_WDOG1_FRAC_SHIFT (3U) /*! FRAC - Peripheral Clock Divider Fraction * 0b0..Fractional value is 0. * 0b1..Fractional value is 1. */ #define PCC2_PCC_WDOG1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG1_FRAC_SHIFT)) & PCC2_PCC_WDOG1_FRAC_MASK) #define PCC2_PCC_WDOG1_PCS_MASK (0x7000000U) #define PCC2_PCC_WDOG1_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC2_PCC_WDOG1_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG1_PCS_SHIFT)) & PCC2_PCC_WDOG1_PCS_MASK) #define PCC2_PCC_WDOG1_INUSE_MASK (0x20000000U) #define PCC2_PCC_WDOG1_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_WDOG1_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG1_INUSE_SHIFT)) & PCC2_PCC_WDOG1_INUSE_MASK) #define PCC2_PCC_WDOG1_CGC_MASK (0x40000000U) #define PCC2_PCC_WDOG1_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_WDOG1_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG1_CGC_SHIFT)) & PCC2_PCC_WDOG1_CGC_MASK) #define PCC2_PCC_WDOG1_PR_MASK (0x80000000U) #define PCC2_PCC_WDOG1_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_WDOG1_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG1_PR_SHIFT)) & PCC2_PCC_WDOG1_PR_MASK) /*! @} */ /*! @name PCC_WDOG2 - PCC WDOG2 Register */ /*! @{ */ #define PCC2_PCC_WDOG2_PCD_MASK (0x7U) #define PCC2_PCC_WDOG2_PCD_SHIFT (0U) /*! PCD - Peripheral Clock Divider Select * 0b000..Divide by 1. * 0b001..Divide by 2. * 0b010..Divide by 3. * 0b011..Divide by 4. * 0b100..Divide by 5. * 0b101..Divide by 6. * 0b110..Divide by 7. * 0b111..Divide by 8. */ #define PCC2_PCC_WDOG2_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG2_PCD_SHIFT)) & PCC2_PCC_WDOG2_PCD_MASK) #define PCC2_PCC_WDOG2_FRAC_MASK (0x8U) #define PCC2_PCC_WDOG2_FRAC_SHIFT (3U) /*! FRAC - Peripheral Clock Divider Fraction * 0b0..Fractional value is 0. * 0b1..Fractional value is 1. */ #define PCC2_PCC_WDOG2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG2_FRAC_SHIFT)) & PCC2_PCC_WDOG2_FRAC_MASK) #define PCC2_PCC_WDOG2_PCS_MASK (0x7000000U) #define PCC2_PCC_WDOG2_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC2_PCC_WDOG2_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG2_PCS_SHIFT)) & PCC2_PCC_WDOG2_PCS_MASK) #define PCC2_PCC_WDOG2_INUSE_MASK (0x20000000U) #define PCC2_PCC_WDOG2_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC2_PCC_WDOG2_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG2_INUSE_SHIFT)) & PCC2_PCC_WDOG2_INUSE_MASK) #define PCC2_PCC_WDOG2_CGC_MASK (0x40000000U) #define PCC2_PCC_WDOG2_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC2_PCC_WDOG2_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG2_CGC_SHIFT)) & PCC2_PCC_WDOG2_CGC_MASK) #define PCC2_PCC_WDOG2_PR_MASK (0x80000000U) #define PCC2_PCC_WDOG2_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC2_PCC_WDOG2_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC2_PCC_WDOG2_PR_SHIFT)) & PCC2_PCC_WDOG2_PR_MASK) /*! @} */ /*! * @} */ /* end of group PCC2_Register_Masks */ /* PCC2 - Peripheral instance base addresses */ /** Peripheral PCC2 base address */ #define PCC2_BASE (0x403F0000u) /** Peripheral PCC2 base pointer */ #define PCC2 ((PCC2_Type *)PCC2_BASE) /** Array initializer of PCC2 peripheral base addresses */ #define PCC2_BASE_ADDRS { PCC2_BASE } /** Array initializer of PCC2 peripheral base pointers */ #define PCC2_BASE_PTRS { PCC2 } /*! * @} */ /* end of group PCC2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PCC3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PCC3_Peripheral_Access_Layer PCC3 Peripheral Access Layer * @{ */ /** PCC3 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[132]; __IO uint32_t PCC_TPM6; /**< PCC TPM6 Register, offset: 0x84 */ __IO uint32_t PCC_TPM7; /**< PCC TPM7 Register, offset: 0x88 */ uint8_t RESERVED_1[4]; __IO uint32_t PCC_LPI2C6; /**< PCC LPI2C6 Register, offset: 0x90 */ __IO uint32_t PCC_LPI2C7; /**< PCC LPI2C7 Register, offset: 0x94 */ __IO uint32_t PCC_LPUART6; /**< PCC LPUART6 Register, offset: 0x98 */ __IO uint32_t PCC_LPUART7; /**< PCC LPUART7 Register, offset: 0x9C */ __IO uint32_t PCC_VIU; /**< PCC VIU Register, offset: 0xA0 */ __IO uint32_t PCC_DSI; /**< PCC DSI Register, offset: 0xA4 */ __IO uint32_t PCC_LCDIF; /**< PCC LCDIF Register, offset: 0xA8 */ __IO uint32_t PCC_MMDC; /**< PCC MMDC Register, offset: 0xAC */ uint8_t RESERVED_2[8]; __IO uint32_t PCC_PCTLC; /**< PCC PCTLC Register, offset: 0xB8 */ __IO uint32_t PCC_PCTLD; /**< PCC PCTLD Register, offset: 0xBC */ __IO uint32_t PCC_PCTLE; /**< PCC PCTLE Register, offset: 0xC0 */ __IO uint32_t PCC_PCTLF; /**< PCC PCTLF Register, offset: 0xC4 */ uint8_t RESERVED_3[120]; __IO uint32_t PCC_GPU3D; /**< PCC GPU3D Register, offset: 0x140 */ __IO uint32_t PCC_GPU2D; /**< PCC GPU2D Register, offset: 0x144 */ } PCC3_Type; /* ---------------------------------------------------------------------------- -- PCC3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PCC3_Register_Masks PCC3 Register Masks * @{ */ /*! @name PCC_TPM6 - PCC TPM6 Register */ /*! @{ */ #define PCC3_PCC_TPM6_PCS_MASK (0x7000000U) #define PCC3_PCC_TPM6_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC3_PCC_TPM6_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM6_PCS_SHIFT)) & PCC3_PCC_TPM6_PCS_MASK) #define PCC3_PCC_TPM6_INUSE_MASK (0x20000000U) #define PCC3_PCC_TPM6_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC3_PCC_TPM6_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM6_INUSE_SHIFT)) & PCC3_PCC_TPM6_INUSE_MASK) #define PCC3_PCC_TPM6_CGC_MASK (0x40000000U) #define PCC3_PCC_TPM6_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC3_PCC_TPM6_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM6_CGC_SHIFT)) & PCC3_PCC_TPM6_CGC_MASK) #define PCC3_PCC_TPM6_PR_MASK (0x80000000U) #define PCC3_PCC_TPM6_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC3_PCC_TPM6_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM6_PR_SHIFT)) & PCC3_PCC_TPM6_PR_MASK) /*! @} */ /*! @name PCC_TPM7 - PCC TPM7 Register */ /*! @{ */ #define PCC3_PCC_TPM7_PCS_MASK (0x7000000U) #define PCC3_PCC_TPM7_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC3_PCC_TPM7_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM7_PCS_SHIFT)) & PCC3_PCC_TPM7_PCS_MASK) #define PCC3_PCC_TPM7_INUSE_MASK (0x20000000U) #define PCC3_PCC_TPM7_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC3_PCC_TPM7_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM7_INUSE_SHIFT)) & PCC3_PCC_TPM7_INUSE_MASK) #define PCC3_PCC_TPM7_CGC_MASK (0x40000000U) #define PCC3_PCC_TPM7_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC3_PCC_TPM7_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM7_CGC_SHIFT)) & PCC3_PCC_TPM7_CGC_MASK) #define PCC3_PCC_TPM7_PR_MASK (0x80000000U) #define PCC3_PCC_TPM7_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC3_PCC_TPM7_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_TPM7_PR_SHIFT)) & PCC3_PCC_TPM7_PR_MASK) /*! @} */ /*! @name PCC_LPI2C6 - PCC LPI2C6 Register */ /*! @{ */ #define PCC3_PCC_LPI2C6_PCS_MASK (0x7000000U) #define PCC3_PCC_LPI2C6_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC3_PCC_LPI2C6_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C6_PCS_SHIFT)) & PCC3_PCC_LPI2C6_PCS_MASK) #define PCC3_PCC_LPI2C6_INUSE_MASK (0x20000000U) #define PCC3_PCC_LPI2C6_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC3_PCC_LPI2C6_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C6_INUSE_SHIFT)) & PCC3_PCC_LPI2C6_INUSE_MASK) #define PCC3_PCC_LPI2C6_CGC_MASK (0x40000000U) #define PCC3_PCC_LPI2C6_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC3_PCC_LPI2C6_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C6_CGC_SHIFT)) & PCC3_PCC_LPI2C6_CGC_MASK) #define PCC3_PCC_LPI2C6_PR_MASK (0x80000000U) #define PCC3_PCC_LPI2C6_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC3_PCC_LPI2C6_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C6_PR_SHIFT)) & PCC3_PCC_LPI2C6_PR_MASK) /*! @} */ /*! @name PCC_LPI2C7 - PCC LPI2C7 Register */ /*! @{ */ #define PCC3_PCC_LPI2C7_PCS_MASK (0x7000000U) #define PCC3_PCC_LPI2C7_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC3_PCC_LPI2C7_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C7_PCS_SHIFT)) & PCC3_PCC_LPI2C7_PCS_MASK) #define PCC3_PCC_LPI2C7_INUSE_MASK (0x20000000U) #define PCC3_PCC_LPI2C7_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC3_PCC_LPI2C7_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C7_INUSE_SHIFT)) & PCC3_PCC_LPI2C7_INUSE_MASK) #define PCC3_PCC_LPI2C7_CGC_MASK (0x40000000U) #define PCC3_PCC_LPI2C7_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC3_PCC_LPI2C7_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C7_CGC_SHIFT)) & PCC3_PCC_LPI2C7_CGC_MASK) #define PCC3_PCC_LPI2C7_PR_MASK (0x80000000U) #define PCC3_PCC_LPI2C7_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC3_PCC_LPI2C7_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPI2C7_PR_SHIFT)) & PCC3_PCC_LPI2C7_PR_MASK) /*! @} */ /*! @name PCC_LPUART6 - PCC LPUART6 Register */ /*! @{ */ #define PCC3_PCC_LPUART6_PCS_MASK (0x7000000U) #define PCC3_PCC_LPUART6_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC3_PCC_LPUART6_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART6_PCS_SHIFT)) & PCC3_PCC_LPUART6_PCS_MASK) #define PCC3_PCC_LPUART6_INUSE_MASK (0x20000000U) #define PCC3_PCC_LPUART6_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC3_PCC_LPUART6_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART6_INUSE_SHIFT)) & PCC3_PCC_LPUART6_INUSE_MASK) #define PCC3_PCC_LPUART6_CGC_MASK (0x40000000U) #define PCC3_PCC_LPUART6_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC3_PCC_LPUART6_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART6_CGC_SHIFT)) & PCC3_PCC_LPUART6_CGC_MASK) #define PCC3_PCC_LPUART6_PR_MASK (0x80000000U) #define PCC3_PCC_LPUART6_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC3_PCC_LPUART6_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART6_PR_SHIFT)) & PCC3_PCC_LPUART6_PR_MASK) /*! @} */ /*! @name PCC_LPUART7 - PCC LPUART7 Register */ /*! @{ */ #define PCC3_PCC_LPUART7_PCS_MASK (0x7000000U) #define PCC3_PCC_LPUART7_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC3_PCC_LPUART7_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART7_PCS_SHIFT)) & PCC3_PCC_LPUART7_PCS_MASK) #define PCC3_PCC_LPUART7_INUSE_MASK (0x20000000U) #define PCC3_PCC_LPUART7_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC3_PCC_LPUART7_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART7_INUSE_SHIFT)) & PCC3_PCC_LPUART7_INUSE_MASK) #define PCC3_PCC_LPUART7_CGC_MASK (0x40000000U) #define PCC3_PCC_LPUART7_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC3_PCC_LPUART7_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART7_CGC_SHIFT)) & PCC3_PCC_LPUART7_CGC_MASK) #define PCC3_PCC_LPUART7_PR_MASK (0x80000000U) #define PCC3_PCC_LPUART7_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC3_PCC_LPUART7_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LPUART7_PR_SHIFT)) & PCC3_PCC_LPUART7_PR_MASK) /*! @} */ /*! @name PCC_VIU - PCC VIU Register */ /*! @{ */ #define PCC3_PCC_VIU_INUSE_MASK (0x20000000U) #define PCC3_PCC_VIU_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC3_PCC_VIU_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_VIU_INUSE_SHIFT)) & PCC3_PCC_VIU_INUSE_MASK) #define PCC3_PCC_VIU_CGC_MASK (0x40000000U) #define PCC3_PCC_VIU_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC3_PCC_VIU_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_VIU_CGC_SHIFT)) & PCC3_PCC_VIU_CGC_MASK) #define PCC3_PCC_VIU_PR_MASK (0x80000000U) #define PCC3_PCC_VIU_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC3_PCC_VIU_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_VIU_PR_SHIFT)) & PCC3_PCC_VIU_PR_MASK) /*! @} */ /*! @name PCC_DSI - PCC DSI Register */ /*! @{ */ #define PCC3_PCC_DSI_PCD_MASK (0x7U) #define PCC3_PCC_DSI_PCD_SHIFT (0U) /*! PCD - Peripheral Clock Divider Select * 0b000..Divide by 1. * 0b001..Divide by 2. * 0b010..Divide by 3. * 0b011..Divide by 4. * 0b100..Divide by 5. * 0b101..Divide by 6. * 0b110..Divide by 7. * 0b111..Divide by 8. */ #define PCC3_PCC_DSI_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DSI_PCD_SHIFT)) & PCC3_PCC_DSI_PCD_MASK) #define PCC3_PCC_DSI_FRAC_MASK (0x8U) #define PCC3_PCC_DSI_FRAC_SHIFT (3U) /*! FRAC - Peripheral Clock Divider Fraction * 0b0..Fractional value is 0. * 0b1..Fractional value is 1. */ #define PCC3_PCC_DSI_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DSI_FRAC_SHIFT)) & PCC3_PCC_DSI_FRAC_MASK) #define PCC3_PCC_DSI_PCS_MASK (0x7000000U) #define PCC3_PCC_DSI_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. An external clock can be enabled for this peripheral. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC3_PCC_DSI_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DSI_PCS_SHIFT)) & PCC3_PCC_DSI_PCS_MASK) #define PCC3_PCC_DSI_INUSE_MASK (0x20000000U) #define PCC3_PCC_DSI_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC3_PCC_DSI_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DSI_INUSE_SHIFT)) & PCC3_PCC_DSI_INUSE_MASK) #define PCC3_PCC_DSI_CGC_MASK (0x40000000U) #define PCC3_PCC_DSI_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC3_PCC_DSI_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DSI_CGC_SHIFT)) & PCC3_PCC_DSI_CGC_MASK) #define PCC3_PCC_DSI_PR_MASK (0x80000000U) #define PCC3_PCC_DSI_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC3_PCC_DSI_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_DSI_PR_SHIFT)) & PCC3_PCC_DSI_PR_MASK) /*! @} */ /*! @name PCC_LCDIF - PCC LCDIF Register */ /*! @{ */ #define PCC3_PCC_LCDIF_PCD_MASK (0x7U) #define PCC3_PCC_LCDIF_PCD_SHIFT (0U) /*! PCD - Peripheral Clock Divider Select * 0b000..Divide by 1. * 0b001..Divide by 2. * 0b010..Divide by 3. * 0b011..Divide by 4. * 0b100..Divide by 5. * 0b101..Divide by 6. * 0b110..Divide by 7. * 0b111..Divide by 8. */ #define PCC3_PCC_LCDIF_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LCDIF_PCD_SHIFT)) & PCC3_PCC_LCDIF_PCD_MASK) #define PCC3_PCC_LCDIF_FRAC_MASK (0x8U) #define PCC3_PCC_LCDIF_FRAC_SHIFT (3U) /*! FRAC - Peripheral Clock Divider Fraction * 0b0..Fractional value is 0. * 0b1..Fractional value is 1. */ #define PCC3_PCC_LCDIF_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LCDIF_FRAC_SHIFT)) & PCC3_PCC_LCDIF_FRAC_MASK) #define PCC3_PCC_LCDIF_PCS_MASK (0x7000000U) #define PCC3_PCC_LCDIF_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. An external clock can be enabled for this peripheral. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC3_PCC_LCDIF_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LCDIF_PCS_SHIFT)) & PCC3_PCC_LCDIF_PCS_MASK) #define PCC3_PCC_LCDIF_INUSE_MASK (0x20000000U) #define PCC3_PCC_LCDIF_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC3_PCC_LCDIF_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LCDIF_INUSE_SHIFT)) & PCC3_PCC_LCDIF_INUSE_MASK) #define PCC3_PCC_LCDIF_CGC_MASK (0x40000000U) #define PCC3_PCC_LCDIF_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC3_PCC_LCDIF_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LCDIF_CGC_SHIFT)) & PCC3_PCC_LCDIF_CGC_MASK) #define PCC3_PCC_LCDIF_PR_MASK (0x80000000U) #define PCC3_PCC_LCDIF_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC3_PCC_LCDIF_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_LCDIF_PR_SHIFT)) & PCC3_PCC_LCDIF_PR_MASK) /*! @} */ /*! @name PCC_MMDC - PCC MMDC Register */ /*! @{ */ #define PCC3_PCC_MMDC_INUSE_MASK (0x20000000U) #define PCC3_PCC_MMDC_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC3_PCC_MMDC_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_MMDC_INUSE_SHIFT)) & PCC3_PCC_MMDC_INUSE_MASK) #define PCC3_PCC_MMDC_CGC_MASK (0x40000000U) #define PCC3_PCC_MMDC_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC3_PCC_MMDC_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_MMDC_CGC_SHIFT)) & PCC3_PCC_MMDC_CGC_MASK) #define PCC3_PCC_MMDC_PR_MASK (0x80000000U) #define PCC3_PCC_MMDC_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC3_PCC_MMDC_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_MMDC_PR_SHIFT)) & PCC3_PCC_MMDC_PR_MASK) /*! @} */ /*! @name PCC_PCTLC - PCC PCTLC Register */ /*! @{ */ #define PCC3_PCC_PCTLC_INUSE_MASK (0x20000000U) #define PCC3_PCC_PCTLC_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC3_PCC_PCTLC_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_PCTLC_INUSE_SHIFT)) & PCC3_PCC_PCTLC_INUSE_MASK) #define PCC3_PCC_PCTLC_CGC_MASK (0x40000000U) #define PCC3_PCC_PCTLC_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC3_PCC_PCTLC_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_PCTLC_CGC_SHIFT)) & PCC3_PCC_PCTLC_CGC_MASK) #define PCC3_PCC_PCTLC_PR_MASK (0x80000000U) #define PCC3_PCC_PCTLC_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC3_PCC_PCTLC_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_PCTLC_PR_SHIFT)) & PCC3_PCC_PCTLC_PR_MASK) /*! @} */ /*! @name PCC_PCTLD - PCC PCTLD Register */ /*! @{ */ #define PCC3_PCC_PCTLD_INUSE_MASK (0x20000000U) #define PCC3_PCC_PCTLD_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC3_PCC_PCTLD_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_PCTLD_INUSE_SHIFT)) & PCC3_PCC_PCTLD_INUSE_MASK) #define PCC3_PCC_PCTLD_CGC_MASK (0x40000000U) #define PCC3_PCC_PCTLD_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC3_PCC_PCTLD_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_PCTLD_CGC_SHIFT)) & PCC3_PCC_PCTLD_CGC_MASK) #define PCC3_PCC_PCTLD_PR_MASK (0x80000000U) #define PCC3_PCC_PCTLD_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC3_PCC_PCTLD_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_PCTLD_PR_SHIFT)) & PCC3_PCC_PCTLD_PR_MASK) /*! @} */ /*! @name PCC_PCTLE - PCC PCTLE Register */ /*! @{ */ #define PCC3_PCC_PCTLE_INUSE_MASK (0x20000000U) #define PCC3_PCC_PCTLE_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC3_PCC_PCTLE_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_PCTLE_INUSE_SHIFT)) & PCC3_PCC_PCTLE_INUSE_MASK) #define PCC3_PCC_PCTLE_CGC_MASK (0x40000000U) #define PCC3_PCC_PCTLE_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC3_PCC_PCTLE_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_PCTLE_CGC_SHIFT)) & PCC3_PCC_PCTLE_CGC_MASK) #define PCC3_PCC_PCTLE_PR_MASK (0x80000000U) #define PCC3_PCC_PCTLE_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC3_PCC_PCTLE_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_PCTLE_PR_SHIFT)) & PCC3_PCC_PCTLE_PR_MASK) /*! @} */ /*! @name PCC_PCTLF - PCC PCTLF Register */ /*! @{ */ #define PCC3_PCC_PCTLF_INUSE_MASK (0x20000000U) #define PCC3_PCC_PCTLF_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC3_PCC_PCTLF_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_PCTLF_INUSE_SHIFT)) & PCC3_PCC_PCTLF_INUSE_MASK) #define PCC3_PCC_PCTLF_CGC_MASK (0x40000000U) #define PCC3_PCC_PCTLF_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC3_PCC_PCTLF_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_PCTLF_CGC_SHIFT)) & PCC3_PCC_PCTLF_CGC_MASK) #define PCC3_PCC_PCTLF_PR_MASK (0x80000000U) #define PCC3_PCC_PCTLF_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC3_PCC_PCTLF_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_PCTLF_PR_SHIFT)) & PCC3_PCC_PCTLF_PR_MASK) /*! @} */ /*! @name PCC_GPU3D - PCC GPU3D Register */ /*! @{ */ #define PCC3_PCC_GPU3D_PCS_MASK (0x7000000U) #define PCC3_PCC_GPU3D_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC3_PCC_GPU3D_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_GPU3D_PCS_SHIFT)) & PCC3_PCC_GPU3D_PCS_MASK) #define PCC3_PCC_GPU3D_INUSE_MASK (0x20000000U) #define PCC3_PCC_GPU3D_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC3_PCC_GPU3D_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_GPU3D_INUSE_SHIFT)) & PCC3_PCC_GPU3D_INUSE_MASK) #define PCC3_PCC_GPU3D_CGC_MASK (0x40000000U) #define PCC3_PCC_GPU3D_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC3_PCC_GPU3D_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_GPU3D_CGC_SHIFT)) & PCC3_PCC_GPU3D_CGC_MASK) #define PCC3_PCC_GPU3D_PR_MASK (0x80000000U) #define PCC3_PCC_GPU3D_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC3_PCC_GPU3D_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_GPU3D_PR_SHIFT)) & PCC3_PCC_GPU3D_PR_MASK) /*! @} */ /*! @name PCC_GPU2D - PCC GPU2D Register */ /*! @{ */ #define PCC3_PCC_GPU2D_PCS_MASK (0x7000000U) #define PCC3_PCC_GPU2D_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off. * 0b001..Clock option 1 * 0b010..Clock option 2 * 0b011..Clock option 3 * 0b100..Clock option 4 * 0b101..Clock option 5 * 0b110..Clock option 6 * 0b111..Clock option 7 */ #define PCC3_PCC_GPU2D_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_GPU2D_PCS_SHIFT)) & PCC3_PCC_GPU2D_PCS_MASK) #define PCC3_PCC_GPU2D_INUSE_MASK (0x20000000U) #define PCC3_PCC_GPU2D_INUSE_SHIFT (29U) /*! INUSE - In use flag * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC3_PCC_GPU2D_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_GPU2D_INUSE_SHIFT)) & PCC3_PCC_GPU2D_INUSE_MASK) #define PCC3_PCC_GPU2D_CGC_MASK (0x40000000U) #define PCC3_PCC_GPU2D_CGC_SHIFT (30U) /*! CGC - Clock Gate Control * 0b0..Clock disabled. The current clock selection and divider options are not locked and can be modified. * 0b1..Clock enabled. The current clock selection and divider options are locked and cannot be modified. */ #define PCC3_PCC_GPU2D_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_GPU2D_CGC_SHIFT)) & PCC3_PCC_GPU2D_CGC_MASK) #define PCC3_PCC_GPU2D_PR_MASK (0x80000000U) #define PCC3_PCC_GPU2D_PR_SHIFT (31U) /*! PR - Present * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC3_PCC_GPU2D_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC3_PCC_GPU2D_PR_SHIFT)) & PCC3_PCC_GPU2D_PR_MASK) /*! @} */ /*! * @} */ /* end of group PCC3_Register_Masks */ /* PCC3 - Peripheral instance base addresses */ /** Peripheral PCC3 base address */ #define PCC3_BASE (0x40B30000u) /** Peripheral PCC3 base pointer */ #define PCC3 ((PCC3_Type *)PCC3_BASE) /** Array initializer of PCC3 peripheral base addresses */ #define PCC3_BASE_ADDRS { PCC3_BASE } /** Array initializer of PCC3 peripheral base pointers */ #define PCC3_BASE_PTRS { PCC3 } /*! * @} */ /* end of group PCC3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PMC0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PMC0_Peripheral_Access_Layer PMC0 Peripheral Access Layer * @{ */ /** PMC0 - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< PMC 0 Version register, offset: 0x0 */ __I uint32_t PM_STAT; /**< PMC 0 Power Mode Status register, offset: 0x4 */ __IO uint32_t HSRUN; /**< PMC 0 HSRUN mode register, offset: 0x8 */ __IO uint32_t RUN; /**< PMC 0 RUN mode register, offset: 0xC */ __IO uint32_t VLPR; /**< PMC 0 VLPR mode register, offset: 0x10 */ __IO uint32_t STOP; /**< PMC 0 STOP mode register, offset: 0x14 */ __IO uint32_t VLPS; /**< PMC 0 VLPS mode register, offset: 0x18 */ __IO uint32_t LLS; /**< PMC 0 LLS mode register, offset: 0x1C */ __IO uint32_t VLLS; /**< PMC 0 VLLS mode register, offset: 0x20 */ __I uint32_t STATUS; /**< PMC 0 Status register, offset: 0x24 */ __IO uint32_t CTRL; /**< PMC 0 Control register, offset: 0x28 */ uint8_t RESERVED_0[4]; __IO uint32_t ACTRL; /**< PMC 0 Analog Core Control register, offset: 0x30 */ uint8_t RESERVED_1[4]; __IO uint32_t BCTRL; /**< PMC 0 Biasing Control register, offset: 0x38 */ uint8_t RESERVED_2[12]; __IO uint32_t SRAMCTRL_0; /**< PMC 0 SRAMs Control 0 register, offset: 0x48 */ __IO uint32_t SRAMCTRL_1; /**< PMC 0 SRAMs Control 1 register, offset: 0x4C */ __IO uint32_t SRAMCTRL_2; /**< PMC 0 SRAMs Control 2 register, offset: 0x50 */ } PMC0_Type; /* ---------------------------------------------------------------------------- -- PMC0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PMC0_Register_Masks PMC0 Register Masks * @{ */ /*! @name VERID - PMC 0 Version register */ /*! @{ */ #define PMC0_VERID_FEATURE_MASK (0xFFFFU) #define PMC0_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Standard features implemented */ #define PMC0_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VERID_FEATURE_SHIFT)) & PMC0_VERID_FEATURE_MASK) #define PMC0_VERID_MINOR_MASK (0xFF0000U) #define PMC0_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define PMC0_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VERID_MINOR_SHIFT)) & PMC0_VERID_MINOR_MASK) #define PMC0_VERID_MAJOR_MASK (0xFF000000U) #define PMC0_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define PMC0_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VERID_MAJOR_SHIFT)) & PMC0_VERID_MAJOR_MASK) /*! @} */ /*! @name PM_STAT - PMC 0 Power Mode Status register */ /*! @{ */ #define PMC0_PM_STAT_PMC0CURRPM_MASK (0x7U) #define PMC0_PM_STAT_PMC0CURRPM_SHIFT (0U) /*! PMC0CURRPM - PMC 0 Current Power Mode * 0b000..HSRUN Mode * 0b001..RUN Mode * 0b010..STOP Mode * 0b011..VLPR Mode * 0b100..VLPS Mode * 0b101..LLS Mode * 0b110..VLLS Mode */ #define PMC0_PM_STAT_PMC0CURRPM(x) (((uint32_t)(((uint32_t)(x)) << PMC0_PM_STAT_PMC0CURRPM_SHIFT)) & PMC0_PM_STAT_PMC0CURRPM_MASK) #define PMC0_PM_STAT_PMC0TRANPM_MASK (0x10U) #define PMC0_PM_STAT_PMC0TRANPM_SHIFT (4U) /*! PMC0TRANPM - PMC 0 Power Mode transition status * 0b0..PMC 0 is not in a power mode transition. * 0b1..PMC 0 is in a power mode transition. */ #define PMC0_PM_STAT_PMC0TRANPM(x) (((uint32_t)(((uint32_t)(x)) << PMC0_PM_STAT_PMC0TRANPM_SHIFT)) & PMC0_PM_STAT_PMC0TRANPM_MASK) #define PMC0_PM_STAT_PMC1CURRPM_MASK (0x70000U) #define PMC0_PM_STAT_PMC1CURRPM_SHIFT (16U) /*! PMC1CURRPM - PMC 1 Current Power Mode * 0b000..HSRUN Mode * 0b001..RUN Mode * 0b010..STOP Mode * 0b011..VLPR Mode * 0b100..VLPS Mode * 0b101..LLS Mode * 0b110..VLLS Mode */ #define PMC0_PM_STAT_PMC1CURRPM(x) (((uint32_t)(((uint32_t)(x)) << PMC0_PM_STAT_PMC1CURRPM_SHIFT)) & PMC0_PM_STAT_PMC1CURRPM_MASK) #define PMC0_PM_STAT_PMC1TRANPM_MASK (0x100000U) #define PMC0_PM_STAT_PMC1TRANPM_SHIFT (20U) /*! PMC1TRANPM - PMC 1 Power Mode transition status * 0b0..PMC 1 is not in a power mode transition. * 0b1..PMC 1 is in a power mode transition. */ #define PMC0_PM_STAT_PMC1TRANPM(x) (((uint32_t)(((uint32_t)(x)) << PMC0_PM_STAT_PMC1TRANPM_SHIFT)) & PMC0_PM_STAT_PMC1TRANPM_MASK) /*! @} */ /*! @name HSRUN - PMC 0 HSRUN mode register */ /*! @{ */ #define PMC0_HSRUN_COREREGVL_MASK (0x3F0000U) #define PMC0_HSRUN_COREREGVL_SHIFT (16U) /*! COREREGVL - Core Regulator Voltage Level * 0b000000..Core Voltage Level is 0.596V * 0b000001..Core Voltage Level is 0.607V * 0b110001..Core Voltage Level is 1.127V * 0b110010..Core Voltage Level is 1.138V */ #define PMC0_HSRUN_COREREGVL(x) (((uint32_t)(((uint32_t)(x)) << PMC0_HSRUN_COREREGVL_SHIFT)) & PMC0_HSRUN_COREREGVL_MASK) #define PMC0_HSRUN_FBBEN_MASK (0x1000000U) #define PMC0_HSRUN_FBBEN_SHIFT (24U) /*! FBBEN - Forward Back Bias Enable * 0b0..FBB is disabled * 0b1..FBB is enabled */ #define PMC0_HSRUN_FBBEN(x) (((uint32_t)(((uint32_t)(x)) << PMC0_HSRUN_FBBEN_SHIFT)) & PMC0_HSRUN_FBBEN_MASK) /*! @} */ /*! @name RUN - PMC 0 RUN mode register */ /*! @{ */ #define PMC0_RUN_COREREGVL_MASK (0x3F0000U) #define PMC0_RUN_COREREGVL_SHIFT (16U) /*! COREREGVL - Core Regulator Voltage Level * 0b000000..Core Voltage Level is 0.596V * 0b000001..Core Voltage Level is 0.607V * 0b110001..Core Voltage Level is 1.127V * 0b110010..Core Voltage Level is 1.138V */ #define PMC0_RUN_COREREGVL(x) (((uint32_t)(((uint32_t)(x)) << PMC0_RUN_COREREGVL_SHIFT)) & PMC0_RUN_COREREGVL_MASK) /*! @} */ /*! @name VLPR - PMC 0 VLPR mode register */ /*! @{ */ #define PMC0_VLPR_ARRAYREG_MASK (0x1U) #define PMC0_VLPR_ARRAYREG_SHIFT (0U) /*! ARRAYREG - Array Regulator * 0b0..LP Regulator is on * 0b1..HP Regulator is on */ #define PMC0_VLPR_ARRAYREG(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VLPR_ARRAYREG_SHIFT)) & PMC0_VLPR_ARRAYREG_MASK) #define PMC0_VLPR_COREREG_MASK (0x4U) #define PMC0_VLPR_COREREG_SHIFT (2U) /*! COREREG - Core Regulator Enable * 0b0..LP Regulator is on * 0b1..HP Regulator is on */ #define PMC0_VLPR_COREREG(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VLPR_COREREG_SHIFT)) & PMC0_VLPR_COREREG_MASK) #define PMC0_VLPR_MONLVD_MASK (0x10U) #define PMC0_VLPR_MONLVD_SHIFT (4U) /*! MONLVD - 1.2V LVD HP Monitor Enable * 0b0..LP monitor is enabled * 0b1..HP monitor is enabled */ #define PMC0_VLPR_MONLVD(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VLPR_MONLVD_SHIFT)) & PMC0_VLPR_MONLVD_MASK) #define PMC0_VLPR_MONHVD_MASK (0x20U) #define PMC0_VLPR_MONHVD_SHIFT (5U) /*! MONHVD - 1.8V HVD HP Monitor Enable * 0b0..The monitor is disabled * 0b1..The monitor is enabled */ #define PMC0_VLPR_MONHVD(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VLPR_MONHVD_SHIFT)) & PMC0_VLPR_MONHVD_MASK) #define PMC0_VLPR_FBGHP_MASK (0x80U) #define PMC0_VLPR_FBGHP_SHIFT (7U) /*! FBGHP - Force HP band-gap * 0b0..No action * 0b1..Turn on the HP band-gap */ #define PMC0_VLPR_FBGHP(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VLPR_FBGHP_SHIFT)) & PMC0_VLPR_FBGHP_MASK) #define PMC0_VLPR_COREREGVL_MASK (0x3F0000U) #define PMC0_VLPR_COREREGVL_SHIFT (16U) /*! COREREGVL - Core Regulator Voltage Level * 0b000000..Core Voltage Level is 0.596V * 0b000001..Core Voltage Level is 0.607V * 0b110001..Core Voltage Level is 1.127V * 0b110010..Core Voltage Level is 1.138V */ #define PMC0_VLPR_COREREGVL(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VLPR_COREREGVL_SHIFT)) & PMC0_VLPR_COREREGVL_MASK) #define PMC0_VLPR_RBBEN_MASK (0x10000000U) #define PMC0_VLPR_RBBEN_SHIFT (28U) /*! RBBEN - Reverse Back Bias Enable * 0b0..RBB is disabled * 0b1..RBB is enabled */ #define PMC0_VLPR_RBBEN(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VLPR_RBBEN_SHIFT)) & PMC0_VLPR_RBBEN_MASK) /*! @} */ /*! @name STOP - PMC 0 STOP mode register */ /*! @{ */ #define PMC0_STOP_COREREGVL_MASK (0x3F0000U) #define PMC0_STOP_COREREGVL_SHIFT (16U) /*! COREREGVL - Core Regulator Voltage Level * 0b000000..Core Voltage Level is 0.596V * 0b000001..Core Voltage Level is 0.607V * 0b110001..Core Voltage Level is 1.127V * 0b110010..Core Voltage Level is 1.138V */ #define PMC0_STOP_COREREGVL(x) (((uint32_t)(((uint32_t)(x)) << PMC0_STOP_COREREGVL_SHIFT)) & PMC0_STOP_COREREGVL_MASK) /*! @} */ /*! @name VLPS - PMC 0 VLPS mode register */ /*! @{ */ #define PMC0_VLPS_ARRAYREG_MASK (0x1U) #define PMC0_VLPS_ARRAYREG_SHIFT (0U) /*! ARRAYREG - Array Regulator * 0b0..LP Regulator is on * 0b1..HP Regulator is on */ #define PMC0_VLPS_ARRAYREG(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VLPS_ARRAYREG_SHIFT)) & PMC0_VLPS_ARRAYREG_MASK) #define PMC0_VLPS_COREREG_MASK (0x4U) #define PMC0_VLPS_COREREG_SHIFT (2U) /*! COREREG - Core Regulator * 0b0..LP Regulator is on * 0b1..HP Regulator is on */ #define PMC0_VLPS_COREREG(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VLPS_COREREG_SHIFT)) & PMC0_VLPS_COREREG_MASK) #define PMC0_VLPS_MONLVD_MASK (0x10U) #define PMC0_VLPS_MONLVD_SHIFT (4U) /*! MONLVD - 1.2V LVD HP Monitor Enable * 0b0..LP monitor is enabled * 0b1..HP monitor is enabled */ #define PMC0_VLPS_MONLVD(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VLPS_MONLVD_SHIFT)) & PMC0_VLPS_MONLVD_MASK) #define PMC0_VLPS_MONHVD_MASK (0x20U) #define PMC0_VLPS_MONHVD_SHIFT (5U) /*! MONHVD - 1.8V HVD HP Monitor Enable * 0b0..The monitor is disabled * 0b1..The monitor is enabled */ #define PMC0_VLPS_MONHVD(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VLPS_MONHVD_SHIFT)) & PMC0_VLPS_MONHVD_MASK) #define PMC0_VLPS_FBGHP_MASK (0x80U) #define PMC0_VLPS_FBGHP_SHIFT (7U) /*! FBGHP - Force HP band-gap * 0b0..No action * 0b1..Turn on the HP band-gap */ #define PMC0_VLPS_FBGHP(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VLPS_FBGHP_SHIFT)) & PMC0_VLPS_FBGHP_MASK) #define PMC0_VLPS_COREREGVL_MASK (0x3F0000U) #define PMC0_VLPS_COREREGVL_SHIFT (16U) /*! COREREGVL - Core Regulator Voltage Level * 0b000000..Core Voltage Level is 0.596V * 0b000001..Core Voltage Level is 0.607V * 0b110001..Core Voltage Level is 1.127V * 0b110010..Core Voltage Level is 1.138V */ #define PMC0_VLPS_COREREGVL(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VLPS_COREREGVL_SHIFT)) & PMC0_VLPS_COREREGVL_MASK) #define PMC0_VLPS_RBBEN_MASK (0x10000000U) #define PMC0_VLPS_RBBEN_SHIFT (28U) /*! RBBEN - Reverse Back Bias Enable * 0b0..RBB is disabled * 0b1..RBB is enabled */ #define PMC0_VLPS_RBBEN(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VLPS_RBBEN_SHIFT)) & PMC0_VLPS_RBBEN_MASK) /*! @} */ /*! @name LLS - PMC 0 LLS mode register */ /*! @{ */ #define PMC0_LLS_ARRAYREG_MASK (0x1U) #define PMC0_LLS_ARRAYREG_SHIFT (0U) /*! ARRAYREG - Array Regulator * 0b0..LP Regulator is on * 0b1..HP Regulator is on */ #define PMC0_LLS_ARRAYREG(x) (((uint32_t)(((uint32_t)(x)) << PMC0_LLS_ARRAYREG_SHIFT)) & PMC0_LLS_ARRAYREG_MASK) #define PMC0_LLS_COREREG_MASK (0x4U) #define PMC0_LLS_COREREG_SHIFT (2U) /*! COREREG - Core Regulator * 0b0..LP Regulator is on * 0b1..HP Regulator is on */ #define PMC0_LLS_COREREG(x) (((uint32_t)(((uint32_t)(x)) << PMC0_LLS_COREREG_SHIFT)) & PMC0_LLS_COREREG_MASK) #define PMC0_LLS_MONLVD_MASK (0x10U) #define PMC0_LLS_MONLVD_SHIFT (4U) /*! MONLVD - 1.2V LVD HP Monitor Enable * 0b0..LP monitor is enabled * 0b1..HP monitor is enabled */ #define PMC0_LLS_MONLVD(x) (((uint32_t)(((uint32_t)(x)) << PMC0_LLS_MONLVD_SHIFT)) & PMC0_LLS_MONLVD_MASK) #define PMC0_LLS_MONHVD_MASK (0x20U) #define PMC0_LLS_MONHVD_SHIFT (5U) /*! MONHVD - 1.8V HVD HP Monitor Enable * 0b0..The monitor is disabled * 0b1..The monitor is enabled */ #define PMC0_LLS_MONHVD(x) (((uint32_t)(((uint32_t)(x)) << PMC0_LLS_MONHVD_SHIFT)) & PMC0_LLS_MONHVD_MASK) #define PMC0_LLS_FBGHP_MASK (0x80U) #define PMC0_LLS_FBGHP_SHIFT (7U) /*! FBGHP - Force HP band-gap * 0b0..No action * 0b1..Turn on the HP band-gap */ #define PMC0_LLS_FBGHP(x) (((uint32_t)(((uint32_t)(x)) << PMC0_LLS_FBGHP_SHIFT)) & PMC0_LLS_FBGHP_MASK) #define PMC0_LLS_COREREGVL_MASK (0x3F0000U) #define PMC0_LLS_COREREGVL_SHIFT (16U) /*! COREREGVL - Core Regulator Voltage Level * 0b000000..Core Voltage Level is 0.596V * 0b000001..Core Voltage Level is 0.607V * 0b110001..Core Voltage Level is 1.127V * 0b110010..Core Voltage Level is 1.138V */ #define PMC0_LLS_COREREGVL(x) (((uint32_t)(((uint32_t)(x)) << PMC0_LLS_COREREGVL_SHIFT)) & PMC0_LLS_COREREGVL_MASK) #define PMC0_LLS_RBBEN_MASK (0x10000000U) #define PMC0_LLS_RBBEN_SHIFT (28U) /*! RBBEN - Reverse Back Bias Enable * 0b0..RBB is disabled * 0b1..RBB is enabled */ #define PMC0_LLS_RBBEN(x) (((uint32_t)(((uint32_t)(x)) << PMC0_LLS_RBBEN_SHIFT)) & PMC0_LLS_RBBEN_MASK) /*! @} */ /*! @name VLLS - PMC 0 VLLS mode register */ /*! @{ */ #define PMC0_VLLS_ARRAYREG_MASK (0x3U) #define PMC0_VLLS_ARRAYREG_SHIFT (0U) /*! ARRAYREG - Array Regulator * 0b00..Regulator is off * 0b01..Reserved * 0b10..LP Regulator is on * 0b11..HP Regulator is on */ #define PMC0_VLLS_ARRAYREG(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VLLS_ARRAYREG_SHIFT)) & PMC0_VLLS_ARRAYREG_MASK) #define PMC0_VLLS_MONLVD_MASK (0x10U) #define PMC0_VLLS_MONLVD_SHIFT (4U) /*! MONLVD - 1.2V LVD HP Monitor Enable * 0b0..LP monitor is enabled * 0b1..HP monitor is enabled */ #define PMC0_VLLS_MONLVD(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VLLS_MONLVD_SHIFT)) & PMC0_VLLS_MONLVD_MASK) #define PMC0_VLLS_MONHVD_MASK (0x20U) #define PMC0_VLLS_MONHVD_SHIFT (5U) /*! MONHVD - 1.8V HVD HP Monitor Enable * 0b0..The monitor is disabled * 0b1..The monitor is enabled */ #define PMC0_VLLS_MONHVD(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VLLS_MONHVD_SHIFT)) & PMC0_VLLS_MONHVD_MASK) #define PMC0_VLLS_FBGHP_MASK (0x80U) #define PMC0_VLLS_FBGHP_SHIFT (7U) /*! FBGHP - Force HP band-gap * 0b0..No action * 0b1..Turn on the HP band-gap */ #define PMC0_VLLS_FBGHP(x) (((uint32_t)(((uint32_t)(x)) << PMC0_VLLS_FBGHP_SHIFT)) & PMC0_VLLS_FBGHP_MASK) /*! @} */ /*! @name STATUS - PMC 0 Status register */ /*! @{ */ #define PMC0_STATUS_LVDF_MASK (0x1U) #define PMC0_STATUS_LVDF_SHIFT (0U) /*! LVDF - 1.2V Low-Voltage Detector Flag * 0b0..Low-voltage event was not detected by the 1.2V LVD monitor in the PMC 0 * 0b1..Low-voltage event was detected by the 1.2V LVD monitor in the PMC 0 */ #define PMC0_STATUS_LVDF(x) (((uint32_t)(((uint32_t)(x)) << PMC0_STATUS_LVDF_SHIFT)) & PMC0_STATUS_LVDF_MASK) #define PMC0_STATUS_LVDV_MASK (0x2U) #define PMC0_STATUS_LVDV_SHIFT (1U) /*! LVDV - 1.2V Low-Voltage Detector Value * 0b0..Low-voltage event was not detected by the 1.2V LVD monitor in the PMC 0 * 0b1..Low-voltage event was detected by the 1.2V LVD monitor in the PMC 0 */ #define PMC0_STATUS_LVDV(x) (((uint32_t)(((uint32_t)(x)) << PMC0_STATUS_LVDV_SHIFT)) & PMC0_STATUS_LVDV_MASK) #define PMC0_STATUS_HVDF_MASK (0x10U) #define PMC0_STATUS_HVDF_SHIFT (4U) /*! HVDF - 1.8V High-Voltage Detector Flag * 0b0..High-voltage event was not detected by the 1.8V HVD monitor in the PMC 0 * 0b1..High-voltage event was detected by the 1.8V HVD monitor in the PMC 0 */ #define PMC0_STATUS_HVDF(x) (((uint32_t)(((uint32_t)(x)) << PMC0_STATUS_HVDF_SHIFT)) & PMC0_STATUS_HVDF_MASK) #define PMC0_STATUS_HVDV_MASK (0x20U) #define PMC0_STATUS_HVDV_SHIFT (5U) /*! HVDV - 1.8V High-Voltage Detector Value * 0b0..High-voltage event was not detected by the 1.8V HVD monitor in the PMC 0 * 0b1..High-voltage event was detected by the 1.8V HVD monitor in the PMC 0 */ #define PMC0_STATUS_HVDV(x) (((uint32_t)(((uint32_t)(x)) << PMC0_STATUS_HVDV_SHIFT)) & PMC0_STATUS_HVDV_MASK) #define PMC0_STATUS_COREVLF_MASK (0x100U) #define PMC0_STATUS_COREVLF_SHIFT (8U) /*! COREVLF - Core Regulator Voltage Level Flag * 0b0..Core Regulator Voltage Level is stable * 0b1..Core Regulator Voltage Level is changing */ #define PMC0_STATUS_COREVLF(x) (((uint32_t)(((uint32_t)(x)) << PMC0_STATUS_COREVLF_SHIFT)) & PMC0_STATUS_COREVLF_MASK) #define PMC0_STATUS_SRAMF_MASK (0x1000000U) #define PMC0_STATUS_SRAMF_SHIFT (24U) /*! SRAMF - SRAM Flag * 0b0..No change request in the SRAMs. * 0b1..A change mode request is being processed in the SRAMs. */ #define PMC0_STATUS_SRAMF(x) (((uint32_t)(((uint32_t)(x)) << PMC0_STATUS_SRAMF_SHIFT)) & PMC0_STATUS_SRAMF_MASK) #define PMC0_STATUS_PMC1VSRC_MASK (0x80000000U) #define PMC0_STATUS_PMC1VSRC_SHIFT (31U) /*! PMC1VSRC - PMC 1 Voltage Source * 0b0..The internal LDO supplies the PMC 1, the PMC 1's LVD/HVD sense point is at the supply of the LDO regulator. * 0b1..The external PMIC supplies the PMC 1; the PMC 1's LVD/HVD sense point is at the pin connected to the PMIC. */ #define PMC0_STATUS_PMC1VSRC(x) (((uint32_t)(((uint32_t)(x)) << PMC0_STATUS_PMC1VSRC_SHIFT)) & PMC0_STATUS_PMC1VSRC_MASK) /*! @} */ /*! @name CTRL - PMC 0 Control register */ /*! @{ */ #define PMC0_CTRL_LVDIE_MASK (0x1U) #define PMC0_CTRL_LVDIE_SHIFT (0U) /*! LVDIE - 1.2V Low-Voltage Detector Interrupt Enable * 0b0..1.2V low-voltage detector interrupt is disabled * 0b1..1.2V low-voltage detector interrupt is enabled */ #define PMC0_CTRL_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << PMC0_CTRL_LVDIE_SHIFT)) & PMC0_CTRL_LVDIE_MASK) #define PMC0_CTRL_LVDACK_MASK (0x2U) #define PMC0_CTRL_LVDACK_SHIFT (1U) /*! LVDACK - 1.2V Low-Voltage Detector Acknowledge */ #define PMC0_CTRL_LVDACK(x) (((uint32_t)(((uint32_t)(x)) << PMC0_CTRL_LVDACK_SHIFT)) & PMC0_CTRL_LVDACK_MASK) #define PMC0_CTRL_HVDIE_MASK (0x4U) #define PMC0_CTRL_HVDIE_SHIFT (2U) /*! HVDIE - 1.8V High-Voltage Detector Interrupt Enable * 0b0..1.8V high-voltage detector interrupt is disabled * 0b1..1.8V high-voltage detector interrupt is enabled */ #define PMC0_CTRL_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << PMC0_CTRL_HVDIE_SHIFT)) & PMC0_CTRL_HVDIE_MASK) #define PMC0_CTRL_HVDACK_MASK (0x8U) #define PMC0_CTRL_HVDACK_SHIFT (3U) /*! HVDACK - 1.8V High-Voltage Detector Acknowledge */ #define PMC0_CTRL_HVDACK(x) (((uint32_t)(((uint32_t)(x)) << PMC0_CTRL_HVDACK_SHIFT)) & PMC0_CTRL_HVDACK_MASK) #define PMC0_CTRL_LVDRE_MASK (0x100U) #define PMC0_CTRL_LVDRE_SHIFT (8U) /*! LVDRE - 1.2V Low-Voltage Detector Reset Enable * 0b0..1.2V low-voltage detector reset is disabled * 0b1..1.2V low-voltage detector reset is enabled */ #define PMC0_CTRL_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << PMC0_CTRL_LVDRE_SHIFT)) & PMC0_CTRL_LVDRE_MASK) #define PMC0_CTRL_HVDRE_MASK (0x400U) #define PMC0_CTRL_HVDRE_SHIFT (10U) /*! HVDRE - 1.8V High-Voltage Detector Reset Enable * 0b0..1.8V high-voltage detector reset is disabled * 0b1..1.8V high-voltage detector reset is enabled */ #define PMC0_CTRL_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << PMC0_CTRL_HVDRE_SHIFT)) & PMC0_CTRL_HVDRE_MASK) #define PMC0_CTRL_ISOACK_MASK (0x4000U) #define PMC0_CTRL_ISOACK_SHIFT (14U) /*! ISOACK - Isolation Acknowledge */ #define PMC0_CTRL_ISOACK(x) (((uint32_t)(((uint32_t)(x)) << PMC0_CTRL_ISOACK_SHIFT)) & PMC0_CTRL_ISOACK_MASK) #define PMC0_CTRL_PMC1ON_MASK (0x1000000U) #define PMC0_CTRL_PMC1ON_SHIFT (24U) /*! PMC1ON - PMC 1 Power On */ #define PMC0_CTRL_PMC1ON(x) (((uint32_t)(((uint32_t)(x)) << PMC0_CTRL_PMC1ON_SHIFT)) & PMC0_CTRL_PMC1ON_MASK) #define PMC0_CTRL_LDOOKDIS_MASK (0x40000000U) #define PMC0_CTRL_LDOOKDIS_SHIFT (30U) /*! LDOOKDIS - Disable to Wait LDO OK Signal * 0b0..The PMC will wait for the OK signal from LDO Regulator * 0b1..The PMC will not wait for the OK signal from LDO Regulator */ #define PMC0_CTRL_LDOOKDIS(x) (((uint32_t)(((uint32_t)(x)) << PMC0_CTRL_LDOOKDIS_SHIFT)) & PMC0_CTRL_LDOOKDIS_MASK) #define PMC0_CTRL_LDOEN_MASK (0x80000000U) #define PMC0_CTRL_LDOEN_SHIFT (31U) /*! LDOEN - PMC 1 LDO Regulator Enable * 0b0..PMC 1 LDO Regulator is disabled. * 0b1..PMC 1 LDO Regulator is enabled. */ #define PMC0_CTRL_LDOEN(x) (((uint32_t)(((uint32_t)(x)) << PMC0_CTRL_LDOEN_SHIFT)) & PMC0_CTRL_LDOEN_MASK) /*! @} */ /*! @name ACTRL - PMC 0 Analog Core Control register */ /*! @{ */ #define PMC0_ACTRL_BUFEN_MASK (0x1U) #define PMC0_ACTRL_BUFEN_SHIFT (0U) /*! BUFEN - Buffer Enable * 0b0..Analog buffer is disabled. * 0b1..Analog buffer is enabled. */ #define PMC0_ACTRL_BUFEN(x) (((uint32_t)(((uint32_t)(x)) << PMC0_ACTRL_BUFEN_SHIFT)) & PMC0_ACTRL_BUFEN_MASK) #define PMC0_ACTRL_BUFFLIP_MASK (0x2U) #define PMC0_ACTRL_BUFFLIP_SHIFT (1U) /*! BUFFLIP - Buffer Flip * 0b0..Buffer input not flipped. * 0b1..Buffer input flipped. */ #define PMC0_ACTRL_BUFFLIP(x) (((uint32_t)(((uint32_t)(x)) << PMC0_ACTRL_BUFFLIP_SHIFT)) & PMC0_ACTRL_BUFFLIP_MASK) #define PMC0_ACTRL_BUFSEL_MASK (0xCU) #define PMC0_ACTRL_BUFSEL_SHIFT (2U) /*! BUFSEL - Buffer Selection */ #define PMC0_ACTRL_BUFSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC0_ACTRL_BUFSEL_SHIFT)) & PMC0_ACTRL_BUFSEL_MASK) #define PMC0_ACTRL_TSENSEN_MASK (0x100U) #define PMC0_ACTRL_TSENSEN_SHIFT (8U) /*! TSENSEN - Temperature Sensor Enable * 0b0..The temperature sensor is disabled. * 0b1..The temperature sensor is enabled. */ #define PMC0_ACTRL_TSENSEN(x) (((uint32_t)(((uint32_t)(x)) << PMC0_ACTRL_TSENSEN_SHIFT)) & PMC0_ACTRL_TSENSEN_MASK) #define PMC0_ACTRL_TSENSM_MASK (0x7000U) #define PMC0_ACTRL_TSENSM_SHIFT (12U) /*! TSENSM - Temperature Sensor Mode */ #define PMC0_ACTRL_TSENSM(x) (((uint32_t)(((uint32_t)(x)) << PMC0_ACTRL_TSENSM_SHIFT)) & PMC0_ACTRL_TSENSM_MASK) #define PMC0_ACTRL_SWRBBEN_MASK (0x10000U) #define PMC0_ACTRL_SWRBBEN_SHIFT (16U) /*! SWRBBEN - PMC 1 Switch RBB Enable * 0b0..Switch RBB is disabled. * 0b1..Switch RBB is enabled. */ #define PMC0_ACTRL_SWRBBEN(x) (((uint32_t)(((uint32_t)(x)) << PMC0_ACTRL_SWRBBEN_SHIFT)) & PMC0_ACTRL_SWRBBEN_MASK) #define PMC0_ACTRL_OSC1KHZSEL_MASK (0x700000U) #define PMC0_ACTRL_OSC1KHZSEL_SHIFT (20U) /*! OSC1KHZSEL - 1KHz Oscillator Select */ #define PMC0_ACTRL_OSC1KHZSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC0_ACTRL_OSC1KHZSEL_SHIFT)) & PMC0_ACTRL_OSC1KHZSEL_MASK) #define PMC0_ACTRL_CORECTRL_MASK (0xFF000000U) #define PMC0_ACTRL_CORECTRL_SHIFT (24U) /*! CORECTRL - Controls to Analog PMC Core */ #define PMC0_ACTRL_CORECTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC0_ACTRL_CORECTRL_SHIFT)) & PMC0_ACTRL_CORECTRL_MASK) /*! @} */ /*! @name BCTRL - PMC 0 Biasing Control register */ /*! @{ */ #define PMC0_BCTRL_RBBNLEVEL_MASK (0xFU) #define PMC0_BCTRL_RBBNLEVEL_SHIFT (0U) /*! RBBNLEVEL - RBB N-Well Voltage Level * 0b0000..Voltage level at 0.5V. * 0b0001..Voltage level at 0.6V. * 0b0010..Voltage level at 0.7V. * 0b0011..Voltage level at 0.8V. * 0b0100..Voltage level at 0.9V. * 0b0101..Voltage level at 1.0V. * 0b0110..Voltage level at 1.1V. * 0b0111..Voltage level at 1.2V. * 0b1000..Voltage level at 1.3V. */ #define PMC0_BCTRL_RBBNLEVEL(x) (((uint32_t)(((uint32_t)(x)) << PMC0_BCTRL_RBBNLEVEL_SHIFT)) & PMC0_BCTRL_RBBNLEVEL_MASK) #define PMC0_BCTRL_RBBPLEVEL_MASK (0xF00U) #define PMC0_BCTRL_RBBPLEVEL_SHIFT (8U) /*! RBBPLEVEL - RBB P-Well Voltage Level * 0b0000..Voltage level at -0.5V. * 0b0001..Voltage level at -0.6V. * 0b0010..Voltage level at -0.7V. * 0b0011..Voltage level at -0.8V. * 0b0100..Voltage level at -0.9V. * 0b0101..Voltage level at -1.0V. * 0b0110..Voltage level at -1.1V. * 0b0111..Voltage level at -1.2V. * 0b1000..Voltage level at -1.3V. */ #define PMC0_BCTRL_RBBPLEVEL(x) (((uint32_t)(((uint32_t)(x)) << PMC0_BCTRL_RBBPLEVEL_SHIFT)) & PMC0_BCTRL_RBBPLEVEL_MASK) #define PMC0_BCTRL_RBBPDDIS_MASK (0x8000U) #define PMC0_BCTRL_RBBPDDIS_SHIFT (15U) /*! RBBPDDIS - RBB Pull-down Disable * 0b0..RBB pull-down is enabled. * 0b1..RBB pull-down is disabled. */ #define PMC0_BCTRL_RBBPDDIS(x) (((uint32_t)(((uint32_t)(x)) << PMC0_BCTRL_RBBPDDIS_SHIFT)) & PMC0_BCTRL_RBBPDDIS_MASK) #define PMC0_BCTRL_FBBNLEVEL_MASK (0xF0000U) #define PMC0_BCTRL_FBBNLEVEL_SHIFT (16U) /*! FBBNLEVEL - FBB N-Well Voltage Level * 0b0000..No BIAS condition. * 0b0001..Voltage level at -50mV. * 0b0011..Voltage level at -100mV. * 0b0010..Voltage level at -150mV. * 0b0110..Voltage level at -200mV. * 0b0111..Voltage level at -250mV. * 0b0101..Voltage level at -300mV. * 0b0100..Voltage level at -350mV. */ #define PMC0_BCTRL_FBBNLEVEL(x) (((uint32_t)(((uint32_t)(x)) << PMC0_BCTRL_FBBNLEVEL_SHIFT)) & PMC0_BCTRL_FBBNLEVEL_MASK) #define PMC0_BCTRL_FBBPLEVEL_MASK (0xF000000U) #define PMC0_BCTRL_FBBPLEVEL_SHIFT (24U) /*! FBBPLEVEL - FBB P-Well Voltage Level * 0b0000..No BIAS condition. * 0b0001..Voltage level at 50mV. * 0b0011..Voltage level at 100mV. * 0b0010..Voltage level at 150mV. * 0b0110..Voltage level at 200mV. * 0b0111..Voltage level at 250mV. * 0b0101..Voltage level at 300mV. * 0b0100..Voltage level at 350mV. */ #define PMC0_BCTRL_FBBPLEVEL(x) (((uint32_t)(((uint32_t)(x)) << PMC0_BCTRL_FBBPLEVEL_SHIFT)) & PMC0_BCTRL_FBBPLEVEL_MASK) /*! @} */ /*! @name SRAMCTRL_0 - PMC 0 SRAMs Control 0 register */ /*! @{ */ #define PMC0_SRAMCTRL_0_SRAM_PD_MASK (0x1FU) #define PMC0_SRAMCTRL_0_SRAM_PD_SHIFT (0U) /*! SRAM_PD - PMC 0 SRAM Bank Power Down */ #define PMC0_SRAMCTRL_0_SRAM_PD(x) (((uint32_t)(((uint32_t)(x)) << PMC0_SRAMCTRL_0_SRAM_PD_SHIFT)) & PMC0_SRAMCTRL_0_SRAM_PD_MASK) /*! @} */ /*! @name SRAMCTRL_1 - PMC 0 SRAMs Control 1 register */ /*! @{ */ #define PMC0_SRAMCTRL_1_SRAM_PDS_MASK (0x1FU) #define PMC0_SRAMCTRL_1_SRAM_PDS_SHIFT (0U) /*! SRAM_PDS - PMC 0 SRAM Bank Power Down in Stop Modes */ #define PMC0_SRAMCTRL_1_SRAM_PDS(x) (((uint32_t)(((uint32_t)(x)) << PMC0_SRAMCTRL_1_SRAM_PDS_SHIFT)) & PMC0_SRAMCTRL_1_SRAM_PDS_MASK) /*! @} */ /*! @name SRAMCTRL_2 - PMC 0 SRAMs Control 2 register */ /*! @{ */ #define PMC0_SRAMCTRL_2_SRAM_STDY_MASK (0x1FU) #define PMC0_SRAMCTRL_2_SRAM_STDY_SHIFT (0U) /*! SRAM_STDY - PMC 0 SRAM Bank in Standby Mode */ #define PMC0_SRAMCTRL_2_SRAM_STDY(x) (((uint32_t)(((uint32_t)(x)) << PMC0_SRAMCTRL_2_SRAM_STDY_SHIFT)) & PMC0_SRAMCTRL_2_SRAM_STDY_MASK) /*! @} */ /*! * @} */ /* end of group PMC0_Register_Masks */ /* PMC0 - Peripheral instance base addresses */ /** Peripheral PMC0 base address */ #define PMC0_BASE (0x410A1000u) /** Peripheral PMC0 base pointer */ #define PMC0 ((PMC0_Type *)PMC0_BASE) /** Array initializer of PMC0 peripheral base addresses */ #define PMC0_BASE_ADDRS { PMC0_BASE } /** Array initializer of PMC0 peripheral base pointers */ #define PMC0_BASE_PTRS { PMC0 } /** Interrupt vectors for the PMC0 peripheral type */ #define PMC0_IRQS { PMC0_IRQn } /*! * @} */ /* end of group PMC0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PMC1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PMC1_Peripheral_Access_Layer PMC1 Peripheral Access Layer * @{ */ /** PMC1 - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< PMC 1 Version register, offset: 0x0 */ __IO uint32_t HSRUN; /**< PMC 1 HSRUN mode register, offset: 0x4 */ __IO uint32_t RUN; /**< PMC 1 RUN mode register, offset: 0x8 */ __IO uint32_t VLPR; /**< PMC 1 VLPR mode register, offset: 0xC */ __IO uint32_t STOP; /**< PMC 1 STOP mode register, offset: 0x10 */ __IO uint32_t VLPS; /**< PMC 1 VLPS mode register, offset: 0x14 */ __IO uint32_t LLS; /**< PMC 1 LLS mode register, offset: 0x18 */ __IO uint32_t VLLS; /**< PMC 1 VLLS mode register, offset: 0x1C */ __I uint32_t STATUS; /**< PMC 1 Status register, offset: 0x20 */ __IO uint32_t CTRL; /**< PMC 1 Control register, offset: 0x24 */ uint8_t RESERVED_0[12]; __IO uint32_t BCTRL; /**< PMC 1 Biasing Control register, offset: 0x34 */ uint8_t RESERVED_1[12]; __IO uint32_t SRAMCTRL; /**< PMC 1 SRAMs Control register, offset: 0x44 */ } PMC1_Type; /* ---------------------------------------------------------------------------- -- PMC1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PMC1_Register_Masks PMC1 Register Masks * @{ */ /*! @name VERID - PMC 1 Version register */ /*! @{ */ #define PMC1_VERID_FEATURE_MASK (0xFFFFU) #define PMC1_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Standard features implemented */ #define PMC1_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PMC1_VERID_FEATURE_SHIFT)) & PMC1_VERID_FEATURE_MASK) #define PMC1_VERID_MINOR_MASK (0xFF0000U) #define PMC1_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define PMC1_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PMC1_VERID_MINOR_SHIFT)) & PMC1_VERID_MINOR_MASK) #define PMC1_VERID_MAJOR_MASK (0xFF000000U) #define PMC1_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define PMC1_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PMC1_VERID_MAJOR_SHIFT)) & PMC1_VERID_MAJOR_MASK) /*! @} */ /*! @name HSRUN - PMC 1 HSRUN mode register */ /*! @{ */ #define PMC1_HSRUN_LDOVL_MASK (0x3F0000U) #define PMC1_HSRUN_LDOVL_SHIFT (16U) /*! LDOVL - LDO Regulator Voltage Level * 0b000000..LDO Voltage Level is 0.60V * 0b000001..LDO Voltage Level is 0.61V * 0b110001..LDO Voltage Level is 1.09V * 0b110010..LDO Voltage Level is 1.10V */ #define PMC1_HSRUN_LDOVL(x) (((uint32_t)(((uint32_t)(x)) << PMC1_HSRUN_LDOVL_SHIFT)) & PMC1_HSRUN_LDOVL_MASK) #define PMC1_HSRUN_FBBEN_MASK (0x1000000U) #define PMC1_HSRUN_FBBEN_SHIFT (24U) /*! FBBEN - Forward Back Bias Enable * 0b0..FBB is disabled * 0b1..FBB is enabled */ #define PMC1_HSRUN_FBBEN(x) (((uint32_t)(((uint32_t)(x)) << PMC1_HSRUN_FBBEN_SHIFT)) & PMC1_HSRUN_FBBEN_MASK) /*! @} */ /*! @name RUN - PMC 1 RUN mode register */ /*! @{ */ #define PMC1_RUN_LDOVL_MASK (0x3F0000U) #define PMC1_RUN_LDOVL_SHIFT (16U) /*! LDOVL - LDO Regulator Voltage Level * 0b000000..LDO Voltage Level is 0.60V * 0b000001..LDO Voltage Level is 0.61V * 0b110001..LDO Voltage Level is 1.09V * 0b110010..LDO Voltage Level is 1.10V */ #define PMC1_RUN_LDOVL(x) (((uint32_t)(((uint32_t)(x)) << PMC1_RUN_LDOVL_SHIFT)) & PMC1_RUN_LDOVL_MASK) /*! @} */ /*! @name VLPR - PMC 1 VLPR mode register */ /*! @{ */ #define PMC1_VLPR_LDOM_MASK (0x1U) #define PMC1_VLPR_LDOM_SHIFT (0U) /*! LDOM - LDO Regulator Mode * 0b0..Linear LDO LP Regulator is enabled. * 0b1..Linear LDO HP Regulator is enabled. */ #define PMC1_VLPR_LDOM(x) (((uint32_t)(((uint32_t)(x)) << PMC1_VLPR_LDOM_SHIFT)) & PMC1_VLPR_LDOM_MASK) #define PMC1_VLPR_MONLVD_MASK (0x10U) #define PMC1_VLPR_MONLVD_SHIFT (4U) /*! MONLVD - Low-Voltage Detector * 0b0..LP monitor is enabled. * 0b1..HP monitor is enabled. */ #define PMC1_VLPR_MONLVD(x) (((uint32_t)(((uint32_t)(x)) << PMC1_VLPR_MONLVD_SHIFT)) & PMC1_VLPR_MONLVD_MASK) #define PMC1_VLPR_MONHVD_MASK (0x20U) #define PMC1_VLPR_MONHVD_SHIFT (5U) /*! MONHVD - 1.2V HP High-Voltage Detector * 0b0..The monitor is disabled. * 0b1..The monitor is enabled. */ #define PMC1_VLPR_MONHVD(x) (((uint32_t)(((uint32_t)(x)) << PMC1_VLPR_MONHVD_SHIFT)) & PMC1_VLPR_MONHVD_MASK) #define PMC1_VLPR_LDOVL_MASK (0x3F0000U) #define PMC1_VLPR_LDOVL_SHIFT (16U) /*! LDOVL - LDO Regulator Voltage Level * 0b000000..LDO Voltage Level is 0.60V * 0b000001..LDO Voltage Level is 0.61V * 0b110001..LDO Voltage Level is 1.09V * 0b110010..LDO Voltage Level is 1.10V */ #define PMC1_VLPR_LDOVL(x) (((uint32_t)(((uint32_t)(x)) << PMC1_VLPR_LDOVL_SHIFT)) & PMC1_VLPR_LDOVL_MASK) /*! @} */ /*! @name STOP - PMC 1 STOP mode register */ /*! @{ */ #define PMC1_STOP_LDOVL_MASK (0x3F0000U) #define PMC1_STOP_LDOVL_SHIFT (16U) /*! LDOVL - LDO Regulator Voltage Level * 0b000000..LDO Voltage Level is 0.60V * 0b000001..LDO Voltage Level is 0.61V * 0b110001..LDO Voltage Level is 1.09V * 0b110010..LDO Voltage Level is 1.10V */ #define PMC1_STOP_LDOVL(x) (((uint32_t)(((uint32_t)(x)) << PMC1_STOP_LDOVL_SHIFT)) & PMC1_STOP_LDOVL_MASK) /*! @} */ /*! @name VLPS - PMC 1 VLPS mode register */ /*! @{ */ #define PMC1_VLPS_LDOM_MASK (0x1U) #define PMC1_VLPS_LDOM_SHIFT (0U) /*! LDOM - LDO Regulator Mode * 0b0..Linear LDO LP Regulator is enabled. * 0b1..Linear LDO HP Regulator is enabled. */ #define PMC1_VLPS_LDOM(x) (((uint32_t)(((uint32_t)(x)) << PMC1_VLPS_LDOM_SHIFT)) & PMC1_VLPS_LDOM_MASK) #define PMC1_VLPS_MONLVD_MASK (0x10U) #define PMC1_VLPS_MONLVD_SHIFT (4U) /*! MONLVD - Low-Voltage Detector * 0b0..LP monitor is enabled. * 0b1..HP monitor is enabled. */ #define PMC1_VLPS_MONLVD(x) (((uint32_t)(((uint32_t)(x)) << PMC1_VLPS_MONLVD_SHIFT)) & PMC1_VLPS_MONLVD_MASK) #define PMC1_VLPS_MONHVD_MASK (0x20U) #define PMC1_VLPS_MONHVD_SHIFT (5U) /*! MONHVD - 1.2V HP High-Voltage Detector * 0b0..The monitor is disabled. * 0b1..The monitor is enabled. */ #define PMC1_VLPS_MONHVD(x) (((uint32_t)(((uint32_t)(x)) << PMC1_VLPS_MONHVD_SHIFT)) & PMC1_VLPS_MONHVD_MASK) #define PMC1_VLPS_LDOVL_MASK (0x3F0000U) #define PMC1_VLPS_LDOVL_SHIFT (16U) /*! LDOVL - LDO Regulator Voltage Level * 0b000000..LDO Voltage Level is 0.60V * 0b000001..LDO Voltage Level is 0.61V * 0b110001..LDO Voltage Level is 1.09V * 0b110010..LDO Voltage Level is 1.10V */ #define PMC1_VLPS_LDOVL(x) (((uint32_t)(((uint32_t)(x)) << PMC1_VLPS_LDOVL_SHIFT)) & PMC1_VLPS_LDOVL_MASK) #define PMC1_VLPS_RBBEN_MASK (0x10000000U) #define PMC1_VLPS_RBBEN_SHIFT (28U) /*! RBBEN - Reverse Back Bias Enable * 0b0..RBB is disabled * 0b1..RBB is enabled */ #define PMC1_VLPS_RBBEN(x) (((uint32_t)(((uint32_t)(x)) << PMC1_VLPS_RBBEN_SHIFT)) & PMC1_VLPS_RBBEN_MASK) /*! @} */ /*! @name LLS - PMC 1 LLS mode register */ /*! @{ */ #define PMC1_LLS_LDOM_MASK (0x1U) #define PMC1_LLS_LDOM_SHIFT (0U) /*! LDOM - LDO Regulator Mode * 0b0..Linear LDO LP Regulator is enabled. * 0b1..Linear LDO HP Regulator is enabled. */ #define PMC1_LLS_LDOM(x) (((uint32_t)(((uint32_t)(x)) << PMC1_LLS_LDOM_SHIFT)) & PMC1_LLS_LDOM_MASK) #define PMC1_LLS_MONLVD_MASK (0x10U) #define PMC1_LLS_MONLVD_SHIFT (4U) /*! MONLVD - Low-Voltage Detector * 0b0..LP monitor is enabled. * 0b1..HP monitor is enabled. */ #define PMC1_LLS_MONLVD(x) (((uint32_t)(((uint32_t)(x)) << PMC1_LLS_MONLVD_SHIFT)) & PMC1_LLS_MONLVD_MASK) #define PMC1_LLS_MONHVD_MASK (0x20U) #define PMC1_LLS_MONHVD_SHIFT (5U) /*! MONHVD - 1.2V HP High-Voltage Detector * 0b0..The monitor is disabled. * 0b1..The monitor is enabled. */ #define PMC1_LLS_MONHVD(x) (((uint32_t)(((uint32_t)(x)) << PMC1_LLS_MONHVD_SHIFT)) & PMC1_LLS_MONHVD_MASK) #define PMC1_LLS_LDOVL_MASK (0x3F0000U) #define PMC1_LLS_LDOVL_SHIFT (16U) /*! LDOVL - Linear LDO Regulator Voltage Level * 0b000000..LDO Voltage Level is 0.60V * 0b000001..LDO Voltage Level is 0.61V * 0b110001..LDO Voltage Level is 1.09V * 0b110010..LDO Voltage Level is 1.10V */ #define PMC1_LLS_LDOVL(x) (((uint32_t)(((uint32_t)(x)) << PMC1_LLS_LDOVL_SHIFT)) & PMC1_LLS_LDOVL_MASK) #define PMC1_LLS_RBBEN_MASK (0x10000000U) #define PMC1_LLS_RBBEN_SHIFT (28U) /*! RBBEN - Reverse Back Bias Enable * 0b0..RBB is disabled * 0b1..RBB is enabled */ #define PMC1_LLS_RBBEN(x) (((uint32_t)(((uint32_t)(x)) << PMC1_LLS_RBBEN_SHIFT)) & PMC1_LLS_RBBEN_MASK) /*! @} */ /*! @name VLLS - PMC 1 VLLS mode register */ /*! @{ */ #define PMC1_VLLS_LDOM_MASK (0x1U) #define PMC1_VLLS_LDOM_SHIFT (0U) /*! LDOM - LDO Regulator Mode * 0b0..Linear LDO LP Regulator is enabled. * 0b1..Linear LDO HP Regulator is enabled. */ #define PMC1_VLLS_LDOM(x) (((uint32_t)(((uint32_t)(x)) << PMC1_VLLS_LDOM_SHIFT)) & PMC1_VLLS_LDOM_MASK) #define PMC1_VLLS_MONLVD_MASK (0x10U) #define PMC1_VLLS_MONLVD_SHIFT (4U) /*! MONLVD - Low-Voltage Detector * 0b0..LP monitor is enabled. * 0b1..HP monitor is enabled. */ #define PMC1_VLLS_MONLVD(x) (((uint32_t)(((uint32_t)(x)) << PMC1_VLLS_MONLVD_SHIFT)) & PMC1_VLLS_MONLVD_MASK) #define PMC1_VLLS_MONHVD_MASK (0x20U) #define PMC1_VLLS_MONHVD_SHIFT (5U) /*! MONHVD - 1.2V HP High-Voltage Detector * 0b0..The monitor is disabled. * 0b1..The monitor is enabled. */ #define PMC1_VLLS_MONHVD(x) (((uint32_t)(((uint32_t)(x)) << PMC1_VLLS_MONHVD_SHIFT)) & PMC1_VLLS_MONHVD_MASK) /*! @} */ /*! @name STATUS - PMC 1 Status register */ /*! @{ */ #define PMC1_STATUS_LVDF_MASK (0x1U) #define PMC1_STATUS_LVDF_SHIFT (0U) /*! LVDF - 1.2V Low-Voltage Detector Flag * 0b0..Low-voltage event was not detected by the 1.2V LVD monitor in the PMC 1 * 0b1..Low-voltage event was detected by the 1.2V LVD monitor in the PMC 1 */ #define PMC1_STATUS_LVDF(x) (((uint32_t)(((uint32_t)(x)) << PMC1_STATUS_LVDF_SHIFT)) & PMC1_STATUS_LVDF_MASK) #define PMC1_STATUS_LVDV_MASK (0x2U) #define PMC1_STATUS_LVDV_SHIFT (1U) /*! LVDV - 1.2V Low-Voltage Detector Value * 0b0..Low-voltage event was not detected by the 1.2V LVD monitor in the PMC 1 * 0b1..Low-voltage event was detected by the 1.2V LVD monitor in the PMC 1 */ #define PMC1_STATUS_LVDV(x) (((uint32_t)(((uint32_t)(x)) << PMC1_STATUS_LVDV_SHIFT)) & PMC1_STATUS_LVDV_MASK) #define PMC1_STATUS_HVDF_MASK (0x10U) #define PMC1_STATUS_HVDF_SHIFT (4U) /*! HVDF - 1.2V High-Voltage Detector Flag * 0b0..High-voltage event was not detected by the 1.2V HVD monitor in PMC 1 * 0b1..High-voltage event was detected by the 1.2V HVD monitor in PMC 1 */ #define PMC1_STATUS_HVDF(x) (((uint32_t)(((uint32_t)(x)) << PMC1_STATUS_HVDF_SHIFT)) & PMC1_STATUS_HVDF_MASK) #define PMC1_STATUS_HVDV_MASK (0x20U) #define PMC1_STATUS_HVDV_SHIFT (5U) /*! HVDV - 1.2V High-Voltage Detector Value * 0b0..High-voltage event was not detected by the 1.2V HVD monitor in PMC 1 * 0b1..High-voltage event was detected by the 1.2V HVD monitor in PMC 1 */ #define PMC1_STATUS_HVDV(x) (((uint32_t)(((uint32_t)(x)) << PMC1_STATUS_HVDV_SHIFT)) & PMC1_STATUS_HVDV_MASK) #define PMC1_STATUS_LDOVLF_MASK (0x100U) #define PMC1_STATUS_LDOVLF_SHIFT (8U) /*! LDOVLF - LDO Voltage Level Flag * 0b0..LDO Voltage Level is stable * 0b1..LDO Voltage Level is changing */ #define PMC1_STATUS_LDOVLF(x) (((uint32_t)(((uint32_t)(x)) << PMC1_STATUS_LDOVLF_SHIFT)) & PMC1_STATUS_LDOVLF_MASK) #define PMC1_STATUS_SRAMF_MASK (0x1000000U) #define PMC1_STATUS_SRAMF_SHIFT (24U) /*! SRAMF - SRAM Flag * 0b0..No change request in the SRAMs. * 0b1..A change mode request is being processed in the SRAMs. */ #define PMC1_STATUS_SRAMF(x) (((uint32_t)(((uint32_t)(x)) << PMC1_STATUS_SRAMF_SHIFT)) & PMC1_STATUS_SRAMF_MASK) /*! @} */ /*! @name CTRL - PMC 1 Control register */ /*! @{ */ #define PMC1_CTRL_LVDIE_MASK (0x1U) #define PMC1_CTRL_LVDIE_SHIFT (0U) /*! LVDIE - Low-Voltage Detector Interrupt Enable * 0b0..Low-voltage detector interrupt is disabled * 0b1..Low-voltage detector interrupt is enabled */ #define PMC1_CTRL_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << PMC1_CTRL_LVDIE_SHIFT)) & PMC1_CTRL_LVDIE_MASK) #define PMC1_CTRL_LVDACK_MASK (0x2U) #define PMC1_CTRL_LVDACK_SHIFT (1U) /*! LVDACK - 1.2V Low-Voltage Detector Acknowledge */ #define PMC1_CTRL_LVDACK(x) (((uint32_t)(((uint32_t)(x)) << PMC1_CTRL_LVDACK_SHIFT)) & PMC1_CTRL_LVDACK_MASK) #define PMC1_CTRL_HVDIE_MASK (0x4U) #define PMC1_CTRL_HVDIE_SHIFT (2U) /*! HVDIE - 1.2V High-Voltage Detector Interrupt Enable * 0b0..1.2V high-voltage detector interrupt is disabled * 0b1..1.2V high-voltage detector interrupt is enabled */ #define PMC1_CTRL_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << PMC1_CTRL_HVDIE_SHIFT)) & PMC1_CTRL_HVDIE_MASK) #define PMC1_CTRL_HVDACK_MASK (0x8U) #define PMC1_CTRL_HVDACK_SHIFT (3U) /*! HVDACK - 1.2V High-Voltage Detector Acknowledge */ #define PMC1_CTRL_HVDACK(x) (((uint32_t)(((uint32_t)(x)) << PMC1_CTRL_HVDACK_SHIFT)) & PMC1_CTRL_HVDACK_MASK) #define PMC1_CTRL_LVDRE_MASK (0x100U) #define PMC1_CTRL_LVDRE_SHIFT (8U) /*! LVDRE - Low-Voltage Detector Reset Enable * 0b0..Low-voltage detector reset is disabled * 0b1..Low-voltage detector reset is enabled */ #define PMC1_CTRL_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << PMC1_CTRL_LVDRE_SHIFT)) & PMC1_CTRL_LVDRE_MASK) #define PMC1_CTRL_HVDRE_MASK (0x400U) #define PMC1_CTRL_HVDRE_SHIFT (10U) /*! HVDRE - 1.2V High-Voltage Detector Reset Enable * 0b0..1.2V high-voltage detector reset is disabled * 0b1..1.2V high-voltage detector reset is enabled */ #define PMC1_CTRL_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << PMC1_CTRL_HVDRE_SHIFT)) & PMC1_CTRL_HVDRE_MASK) #define PMC1_CTRL_ISOACK_MASK (0x4000U) #define PMC1_CTRL_ISOACK_SHIFT (14U) /*! ISOACK - Isolation Acknowledge */ #define PMC1_CTRL_ISOACK(x) (((uint32_t)(((uint32_t)(x)) << PMC1_CTRL_ISOACK_SHIFT)) & PMC1_CTRL_ISOACK_MASK) /*! @} */ /*! @name BCTRL - PMC 1 Biasing Control register */ /*! @{ */ #define PMC1_BCTRL_RBBNLEVEL_MASK (0xFU) #define PMC1_BCTRL_RBBNLEVEL_SHIFT (0U) /*! RBBNLEVEL - RBB N-Well Voltage Level * 0b0000..Voltage level at 0.5V. * 0b0001..Voltage level at 0.6V. * 0b0010..Voltage level at 0.7V. * 0b0011..Voltage level at 0.8V. * 0b0100..Voltage level at 0.9V. * 0b0101..Voltage level at 1.0V. * 0b0110..Voltage level at 1.1V. * 0b0111..Voltage level at 1.2V. * 0b1000..Voltage level at 1.3V. */ #define PMC1_BCTRL_RBBNLEVEL(x) (((uint32_t)(((uint32_t)(x)) << PMC1_BCTRL_RBBNLEVEL_SHIFT)) & PMC1_BCTRL_RBBNLEVEL_MASK) #define PMC1_BCTRL_RBBPLEVEL_MASK (0xF00U) #define PMC1_BCTRL_RBBPLEVEL_SHIFT (8U) /*! RBBPLEVEL - RBB P-Well Voltage Level * 0b0000..Voltage level at -0.5V. * 0b0001..Voltage level at -0.6V. * 0b0010..Voltage level at -0.7V. * 0b0011..Voltage level at -0.8V. * 0b0100..Voltage level at -0.9V. * 0b0101..Voltage level at -1.0V. * 0b0110..Voltage level at -1.1V. * 0b0111..Voltage level at -1.2V. * 0b1000..Voltage level at -1.3V. */ #define PMC1_BCTRL_RBBPLEVEL(x) (((uint32_t)(((uint32_t)(x)) << PMC1_BCTRL_RBBPLEVEL_SHIFT)) & PMC1_BCTRL_RBBPLEVEL_MASK) #define PMC1_BCTRL_FBBNLEVEL_MASK (0xF0000U) #define PMC1_BCTRL_FBBNLEVEL_SHIFT (16U) /*! FBBNLEVEL - FBB N-Well Voltage Level * 0b0000..No BIAS condition. * 0b0001..Voltage level at -50mV. * 0b0011..Voltage level at -100mV. * 0b0010..Voltage level at -150mV. * 0b0110..Voltage level at -200mV. * 0b0111..Voltage level at -250mV. * 0b0101..Voltage level at -300mV. * 0b0100..Voltage level at -350mV. */ #define PMC1_BCTRL_FBBNLEVEL(x) (((uint32_t)(((uint32_t)(x)) << PMC1_BCTRL_FBBNLEVEL_SHIFT)) & PMC1_BCTRL_FBBNLEVEL_MASK) #define PMC1_BCTRL_FBBPLEVEL_MASK (0xF000000U) #define PMC1_BCTRL_FBBPLEVEL_SHIFT (24U) /*! FBBPLEVEL - FBB P-Well Voltage Level * 0b0000..No BIAS condition. * 0b0001..Voltage level at 50mV. * 0b0011..Voltage level at 100mV. * 0b0010..Voltage level at 150mV. * 0b0110..Voltage level at 200mV. * 0b0111..Voltage level at 250mV. * 0b0101..Voltage level at 300mV. * 0b0100..Voltage level at 350mV. */ #define PMC1_BCTRL_FBBPLEVEL(x) (((uint32_t)(((uint32_t)(x)) << PMC1_BCTRL_FBBPLEVEL_SHIFT)) & PMC1_BCTRL_FBBPLEVEL_MASK) /*! @} */ /*! @name SRAMCTRL - PMC 1 SRAMs Control register */ /*! @{ */ #define PMC1_SRAMCTRL_SRAM_STDY_MASK (0xFFU) #define PMC1_SRAMCTRL_SRAM_STDY_SHIFT (0U) /*! SRAM_STDY - PMC 1 SRAM Bank in Standby Mode */ #define PMC1_SRAMCTRL_SRAM_STDY(x) (((uint32_t)(((uint32_t)(x)) << PMC1_SRAMCTRL_SRAM_STDY_SHIFT)) & PMC1_SRAMCTRL_SRAM_STDY_MASK) /*! @} */ /*! * @} */ /* end of group PMC1_Register_Masks */ /* PMC1 - Peripheral instance base addresses */ /** Peripheral PMC1 base address */ #define PMC1_BASE (0x40400000u) /** Peripheral PMC1 base pointer */ #define PMC1 ((PMC1_Type *)PMC1_BASE) /** Array initializer of PMC1 peripheral base addresses */ #define PMC1_BASE_ADDRS { PMC1_BASE } /** Array initializer of PMC1 peripheral base pointers */ #define PMC1_BASE_PTRS { PMC1 } /*! * @} */ /* end of group PMC1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PORT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer * @{ */ /** PORT - Register Layout Typedef */ typedef struct { __IO uint32_t PCR[32]; /**< Pin Control Register 0..Pin Control Register 19, array offset: 0x0, array step: 0x4 */ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ __O uint32_t GICLR; /**< Global Interrupt Control Low Register, offset: 0x88 */ __O uint32_t GICHR; /**< Global Interrupt Control High Register, offset: 0x8C */ uint8_t RESERVED_0[16]; __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ } PORT_Type; /* ---------------------------------------------------------------------------- -- PORT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PORT_Register_Masks PORT Register Masks * @{ */ /*! @name PCR - Pin Control Register 0..Pin Control Register 19 */ /*! @{ */ #define PORT_PCR_IRQC_MASK (0xF0000U) #define PORT_PCR_IRQC_SHIFT (16U) /*! IRQC - Interrupt Configuration * 0b0000..Interrupt Status Flag (ISF) is disabled. * 0b0001..ISF flag and DMA request on rising edge. * 0b0010..ISF flag and DMA request on falling edge. * 0b0011..ISF flag and DMA request on either edge. * 0b0100..Reserved. * 0b0101..Flag sets on rising edge. * 0b0110..Flag sets on falling edge. * 0b0111..Flag sets on either edge. * 0b1000..ISF flag and Interrupt when logic 0. * 0b1001..ISF flag and Interrupt on rising-edge. * 0b1010..ISF flag and Interrupt on falling-edge. * 0b1011..ISF flag and Interrupt on either edge. * 0b1100..ISF flag and Interrupt when logic 1. * 0b1101..Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, * which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are * configured, then they are ORed together to create the trigger)] * 0b1110..Enable active low trigger output, flag is disabled. * 0b1111..Reserved. */ #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) #define PORT_PCR_ISF_MASK (0x1000000U) #define PORT_PCR_ISF_SHIFT (24U) /*! ISF - Interrupt Status Flag * 0b0..Configured interrupt is not detected. * 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the * corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the * flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive * interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. */ #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) /*! @} */ /* The count of PORT_PCR */ #define PORT_PCR_COUNT (32U) /*! @name GPCLR - Global Pin Control Low Register */ /*! @{ */ #define PORT_GPCLR_GPWD_MASK (0xFFFFU) #define PORT_GPCLR_GPWD_SHIFT (0U) /*! GPWD - Global Pin Write Data */ #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) #define PORT_GPCLR_GPWE_SHIFT (16U) /*! GPWE - Global Pin Write Enable */ #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) /*! @} */ /*! @name GPCHR - Global Pin Control High Register */ /*! @{ */ #define PORT_GPCHR_GPWD_MASK (0xFFFFU) #define PORT_GPCHR_GPWD_SHIFT (0U) /*! GPWD - Global Pin Write Data */ #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) #define PORT_GPCHR_GPWE_SHIFT (16U) /*! GPWE - Global Pin Write Enable */ #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) /*! @} */ /*! @name GICLR - Global Interrupt Control Low Register */ /*! @{ */ #define PORT_GICLR_GIWE_MASK (0xFFFFU) #define PORT_GICLR_GIWE_SHIFT (0U) /*! GIWE - Global Interrupt Write Enable */ #define PORT_GICLR_GIWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWE_SHIFT)) & PORT_GICLR_GIWE_MASK) #define PORT_GICLR_GIWD_MASK (0xFFFF0000U) #define PORT_GICLR_GIWD_SHIFT (16U) /*! GIWD - Global Interrupt Write Data */ #define PORT_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWD_SHIFT)) & PORT_GICLR_GIWD_MASK) /*! @} */ /*! @name GICHR - Global Interrupt Control High Register */ /*! @{ */ #define PORT_GICHR_GIWE_MASK (0xFFFFU) #define PORT_GICHR_GIWE_SHIFT (0U) /*! GIWE - Global Interrupt Write Enable */ #define PORT_GICHR_GIWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWE_SHIFT)) & PORT_GICHR_GIWE_MASK) #define PORT_GICHR_GIWD_MASK (0xFFFF0000U) #define PORT_GICHR_GIWD_SHIFT (16U) /*! GIWD - Global Interrupt Write Data */ #define PORT_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWD_SHIFT)) & PORT_GICHR_GIWD_MASK) /*! @} */ /*! @name ISFR - Interrupt Status Flag Register */ /*! @{ */ #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) #define PORT_ISFR_ISF_SHIFT (0U) /*! ISF - Interrupt Status Flag */ #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) /*! @} */ /*! * @} */ /* end of group PORT_Register_Masks */ /* PORT - Peripheral instance base addresses */ /** Peripheral PORTA base address */ #define PORTA_BASE (0x4103F000u) /** Peripheral PORTA base pointer */ #define PORTA ((PORT_Type *)PORTA_BASE) /** Peripheral PORTB base address */ #define PORTB_BASE (0x41040000u) /** Peripheral PORTB base pointer */ #define PORTB ((PORT_Type *)PORTB_BASE) /** Peripheral PORTC base address */ #define PORTC_BASE (0x40AE0000u) /** Peripheral PORTC base pointer */ #define PORTC ((PORT_Type *)PORTC_BASE) /** Peripheral PORTD base address */ #define PORTD_BASE (0x40AF0000u) /** Peripheral PORTD base pointer */ #define PORTD ((PORT_Type *)PORTD_BASE) /** Peripheral PORTE base address */ #define PORTE_BASE (0x40B00000u) /** Peripheral PORTE base pointer */ #define PORTE ((PORT_Type *)PORTE_BASE) /** Peripheral PORTF base address */ #define PORTF_BASE (0x40B10000u) /** Peripheral PORTF base pointer */ #define PORTF ((PORT_Type *)PORTF_BASE) /** Array initializer of PORT peripheral base addresses */ #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE, PORTF_BASE } /** Array initializer of PORT peripheral base pointers */ #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE, PORTF } /** Interrupt vectors for the PORT peripheral type */ #define PORT_IRQS { PCTLA_IRQn, PCTLB_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } /*! * @} */ /* end of group PORT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- QuadSPI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer * @{ */ /** QuadSPI - Register Layout Typedef */ typedef struct { __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ uint8_t RESERVED_0[4]; __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ __IO uint32_t FLSHCR; /**< Flash Configuration Register, offset: 0xC */ __IO uint32_t BUF0CR; /**< Buffer0 Configuration Register, offset: 0x10 */ __IO uint32_t BUF1CR; /**< Buffer1 Configuration Register, offset: 0x14 */ __IO uint32_t BUF2CR; /**< Buffer2 Configuration Register, offset: 0x18 */ __IO uint32_t BUF3CR; /**< Buffer3 Configuration Register, offset: 0x1C */ __IO uint32_t BFGENCR; /**< Buffer Generic Configuration Register, offset: 0x20 */ __IO uint32_t SOCCR; /**< SOC Configuration Register, offset: 0x24 */ uint8_t RESERVED_1[8]; __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ __IO uint32_t BUF1IND; /**< Buffer1 Top Index Register, offset: 0x34 */ __IO uint32_t BUF2IND; /**< Buffer2 Top Index Register, offset: 0x38 */ uint8_t RESERVED_2[196]; __IO uint32_t SFAR; /**< Serial Flash Address Register, offset: 0x100 */ __IO uint32_t SFACR; /**< Serial Flash Address Configuration Register, offset: 0x104 */ __IO uint32_t SMPR; /**< Sampling Register, offset: 0x108 */ __I uint32_t RBSR; /**< RX Buffer Status Register, offset: 0x10C */ __IO uint32_t RBCT; /**< RX Buffer Control Register, offset: 0x110 */ uint8_t RESERVED_3[60]; __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ __IO uint32_t TBCT; /**< Tx Buffer Control Register, offset: 0x158 */ __I uint32_t SR; /**< Status Register, offset: 0x15C */ __IO uint32_t FR; /**< Flag Register, offset: 0x160 */ __IO uint32_t RSER; /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */ __I uint32_t SPNDST; /**< Sequence Suspend Status Register, offset: 0x168 */ __O uint32_t SPTRCLR; /**< Sequence Pointer Clear Register, offset: 0x16C */ uint8_t RESERVED_4[16]; __IO uint32_t SFA1AD; /**< Serial Flash A1 Top Address, offset: 0x180 */ __IO uint32_t SFA2AD; /**< Serial Flash A2 Top Address, offset: 0x184 */ uint8_t RESERVED_5[8]; __IO uint32_t DLPR; /**< Data Learn Pattern Register, offset: 0x190 */ uint8_t RESERVED_6[108]; __I uint32_t RBDR[16]; /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_7[192]; __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x300 */ __IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x304 */ uint8_t RESERVED_8[8]; __IO uint32_t LUT[64]; /**< Look-up Table register, array offset: 0x310, array step: 0x4 */ } QuadSPI_Type; /* ---------------------------------------------------------------------------- -- QuadSPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks * @{ */ /*! @name MCR - Module Configuration Register */ /*! @{ */ #define QuadSPI_MCR_SWRSTSD_MASK (0x1U) #define QuadSPI_MCR_SWRSTSD_SHIFT (0U) /*! SWRSTSD * 0b0..No action * 0b1..Serial Flash domain flops are reset. Does not reset configuration registers. It is advisable to reset * both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side * effects. The software resets need the clock to be running to propagate to the design. The MCR[MDIS] should * therefore be set to 0 when the software reset bits are asserted. Also, before they can be deasserted again * (by setting MCR[SWRSTSD] to 0), it is recommended to set the MCR[MDIS] bit to 1. Once the software resets * have been deasserted, the normal operation can be started by setting the MCR[MDIS] bit to 0. */ #define QuadSPI_MCR_SWRSTSD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTSD_SHIFT)) & QuadSPI_MCR_SWRSTSD_MASK) #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) #define QuadSPI_MCR_SWRSTHD_SHIFT (1U) /*! SWRSTHD * 0b0..No action * 0b1..AHB domain flops are reset. Does not reset configuration registers. It is advisable to reset both the * serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects. * The software resets need the clock to be running to propagate to the design. The MCR[MDIS] should therefore * be set to 0 when the software reset bits are asserted. Also, before they can be deasserted again (by * setting MCR[SWRSTHD] to 0), it is recommended to set the MCR[MDIS] bit to 1. Once the software resets have been * deasserted, the normal operation can be started by setting the MCR[MDIS] bit to 0. */ #define QuadSPI_MCR_SWRSTHD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK) #define QuadSPI_MCR_END_CFG_MASK (0xCU) #define QuadSPI_MCR_END_CFG_SHIFT (2U) #define QuadSPI_MCR_END_CFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_END_CFG_SHIFT)) & QuadSPI_MCR_END_CFG_MASK) #define QuadSPI_MCR_DQS_LAT_EN_MASK (0x20U) #define QuadSPI_MCR_DQS_LAT_EN_SHIFT (5U) /*! DQS_LAT_EN * 0b0..DQS Latency disabled * 0b1..DQS feature with latency included enabled */ #define QuadSPI_MCR_DQS_LAT_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_LAT_EN_SHIFT)) & QuadSPI_MCR_DQS_LAT_EN_MASK) #define QuadSPI_MCR_DQS_EN_MASK (0x40U) #define QuadSPI_MCR_DQS_EN_SHIFT (6U) /*! DQS_EN * 0b0..DQS disabled. * 0b1..DQS enabled. When enabled, the incoming data is sampled on both the edges of DQS input when * QSPI_MCR[DDR_EN] is set, else, on only one edge when QSPI_MCR[DDR_EN] is 0. The QSPI_SMPR[DDR_SMP] values are ignored. */ #define QuadSPI_MCR_DQS_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_EN_SHIFT)) & QuadSPI_MCR_DQS_EN_MASK) #define QuadSPI_MCR_DDR_EN_MASK (0x80U) #define QuadSPI_MCR_DDR_EN_SHIFT (7U) /*! DDR_EN * 0b0..2x and 4x clocks are disabled for SDR instructions only * 0b1..2x and 4x clocks are enabled supports both SDR and DDR instruction. */ #define QuadSPI_MCR_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DDR_EN_SHIFT)) & QuadSPI_MCR_DDR_EN_MASK) #define QuadSPI_MCR_CLR_RXF_MASK (0x400U) #define QuadSPI_MCR_CLR_RXF_SHIFT (10U) /*! CLR_RXF * 0b0..No action. * 0b1..Read and write pointers of the RX Buffer are reset to 0. QSPI_RBSR[RDBFL] is reset to 0. */ #define QuadSPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_RXF_SHIFT)) & QuadSPI_MCR_CLR_RXF_MASK) #define QuadSPI_MCR_CLR_TXF_MASK (0x800U) #define QuadSPI_MCR_CLR_TXF_SHIFT (11U) /*! CLR_TXF * 0b0..No action. * 0b1..Read and write pointers of the TX Buffer are reset to 0. QSPI_TBSR[TRCTR] is reset to 0. */ #define QuadSPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_TXF_SHIFT)) & QuadSPI_MCR_CLR_TXF_MASK) #define QuadSPI_MCR_MDIS_MASK (0x4000U) #define QuadSPI_MCR_MDIS_SHIFT (14U) /*! MDIS * 0b0..Enable QuadSPI clocks. * 0b1..Allow external logic to disable QuadSPI clocks. */ #define QuadSPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_MDIS_SHIFT)) & QuadSPI_MCR_MDIS_MASK) #define QuadSPI_MCR_ISD2FA_MASK (0x10000U) #define QuadSPI_MCR_ISD2FA_SHIFT (16U) /*! ISD2FA * 0b0..IOFA[2] is driven to logic L * 0b1..IOFA[2] is driven to logic H */ #define QuadSPI_MCR_ISD2FA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_ISD2FA_SHIFT)) & QuadSPI_MCR_ISD2FA_MASK) #define QuadSPI_MCR_ISD3FA_MASK (0x20000U) #define QuadSPI_MCR_ISD3FA_SHIFT (17U) /*! ISD3FA * 0b0..IOFA[3] is driven to logic L * 0b1..IOFA[3] is driven to logic H */ #define QuadSPI_MCR_ISD3FA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_ISD3FA_SHIFT)) & QuadSPI_MCR_ISD3FA_MASK) #define QuadSPI_MCR_SCLKCFG_MASK (0xFF000000U) #define QuadSPI_MCR_SCLKCFG_SHIFT (24U) #define QuadSPI_MCR_SCLKCFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SCLKCFG_SHIFT)) & QuadSPI_MCR_SCLKCFG_MASK) /*! @} */ /*! @name IPCR - IP Configuration Register */ /*! @{ */ #define QuadSPI_IPCR_IDATSZ_MASK (0xFFFFU) #define QuadSPI_IPCR_IDATSZ_SHIFT (0U) #define QuadSPI_IPCR_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_IDATSZ_SHIFT)) & QuadSPI_IPCR_IDATSZ_MASK) #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) #define QuadSPI_IPCR_SEQID_SHIFT (24U) #define QuadSPI_IPCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK) /*! @} */ /*! @name FLSHCR - Flash Configuration Register */ /*! @{ */ #define QuadSPI_FLSHCR_TCSS_MASK (0xFU) #define QuadSPI_FLSHCR_TCSS_SHIFT (0U) #define QuadSPI_FLSHCR_TCSS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSS_SHIFT)) & QuadSPI_FLSHCR_TCSS_MASK) #define QuadSPI_FLSHCR_TCSH_MASK (0xF00U) #define QuadSPI_FLSHCR_TCSH_SHIFT (8U) #define QuadSPI_FLSHCR_TCSH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSH_SHIFT)) & QuadSPI_FLSHCR_TCSH_MASK) #define QuadSPI_FLSHCR_TDH_MASK (0x30000U) #define QuadSPI_FLSHCR_TDH_SHIFT (16U) /*! TDH * 0b00..Data aligned with the posedge of Internal reference clock of QuadSPI * 0b01..Data aligned with 2x serial flash half clock * 0b10..Data aligned with 4x serial flash half clock */ #define QuadSPI_FLSHCR_TDH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK) /*! @} */ /*! @name BUF0CR - Buffer0 Configuration Register */ /*! @{ */ #define QuadSPI_BUF0CR_MSTRID_MASK (0xFU) #define QuadSPI_BUF0CR_MSTRID_SHIFT (0U) #define QuadSPI_BUF0CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_MSTRID_SHIFT)) & QuadSPI_BUF0CR_MSTRID_MASK) #define QuadSPI_BUF0CR_ADATSZ_MASK (0x7F00U) #define QuadSPI_BUF0CR_ADATSZ_SHIFT (8U) /*! ADATSZ - AHB data transfer size */ #define QuadSPI_BUF0CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_ADATSZ_SHIFT)) & QuadSPI_BUF0CR_ADATSZ_MASK) #define QuadSPI_BUF0CR_HP_EN_MASK (0x80000000U) #define QuadSPI_BUF0CR_HP_EN_SHIFT (31U) #define QuadSPI_BUF0CR_HP_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_HP_EN_SHIFT)) & QuadSPI_BUF0CR_HP_EN_MASK) /*! @} */ /*! @name BUF1CR - Buffer1 Configuration Register */ /*! @{ */ #define QuadSPI_BUF1CR_MSTRID_MASK (0xFU) #define QuadSPI_BUF1CR_MSTRID_SHIFT (0U) #define QuadSPI_BUF1CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_MSTRID_SHIFT)) & QuadSPI_BUF1CR_MSTRID_MASK) #define QuadSPI_BUF1CR_ADATSZ_MASK (0x7F00U) #define QuadSPI_BUF1CR_ADATSZ_SHIFT (8U) /*! ADATSZ - AHB data transfer size */ #define QuadSPI_BUF1CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_ADATSZ_SHIFT)) & QuadSPI_BUF1CR_ADATSZ_MASK) /*! @} */ /*! @name BUF2CR - Buffer2 Configuration Register */ /*! @{ */ #define QuadSPI_BUF2CR_MSTRID_MASK (0xFU) #define QuadSPI_BUF2CR_MSTRID_SHIFT (0U) #define QuadSPI_BUF2CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_MSTRID_SHIFT)) & QuadSPI_BUF2CR_MSTRID_MASK) #define QuadSPI_BUF2CR_ADATSZ_MASK (0x7F00U) #define QuadSPI_BUF2CR_ADATSZ_SHIFT (8U) /*! ADATSZ - AHB data transfer size */ #define QuadSPI_BUF2CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_ADATSZ_SHIFT)) & QuadSPI_BUF2CR_ADATSZ_MASK) /*! @} */ /*! @name BUF3CR - Buffer3 Configuration Register */ /*! @{ */ #define QuadSPI_BUF3CR_MSTRID_MASK (0xFU) #define QuadSPI_BUF3CR_MSTRID_SHIFT (0U) #define QuadSPI_BUF3CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_MSTRID_SHIFT)) & QuadSPI_BUF3CR_MSTRID_MASK) #define QuadSPI_BUF3CR_ADATSZ_MASK (0x7F00U) #define QuadSPI_BUF3CR_ADATSZ_SHIFT (8U) /*! ADATSZ - AHB data transfer size */ #define QuadSPI_BUF3CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ADATSZ_SHIFT)) & QuadSPI_BUF3CR_ADATSZ_MASK) #define QuadSPI_BUF3CR_ALLMST_MASK (0x80000000U) #define QuadSPI_BUF3CR_ALLMST_SHIFT (31U) #define QuadSPI_BUF3CR_ALLMST(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ALLMST_SHIFT)) & QuadSPI_BUF3CR_ALLMST_MASK) /*! @} */ /*! @name BFGENCR - Buffer Generic Configuration Register */ /*! @{ */ #define QuadSPI_BFGENCR_SEQID_MASK (0xF000U) #define QuadSPI_BFGENCR_SEQID_SHIFT (12U) #define QuadSPI_BFGENCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_SEQID_SHIFT)) & QuadSPI_BFGENCR_SEQID_MASK) /*! @} */ /*! @name SOCCR - SOC Configuration Register */ /*! @{ */ #define QuadSPI_SOCCR_SOCCFG_MASK (0xFFFFFFFFU) #define QuadSPI_SOCCR_SOCCFG_SHIFT (0U) #define QuadSPI_SOCCR_SOCCFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_SOCCFG_SHIFT)) & QuadSPI_SOCCR_SOCCFG_MASK) /*! @} */ /*! @name BUF0IND - Buffer0 Top Index Register */ /*! @{ */ #define QuadSPI_BUF0IND_TPINDX0_MASK (0xFFFFFFF8U) #define QuadSPI_BUF0IND_TPINDX0_SHIFT (3U) #define QuadSPI_BUF0IND_TPINDX0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0IND_TPINDX0_SHIFT)) & QuadSPI_BUF0IND_TPINDX0_MASK) /*! @} */ /*! @name BUF1IND - Buffer1 Top Index Register */ /*! @{ */ #define QuadSPI_BUF1IND_TPINDX1_MASK (0xFFFFFFF8U) #define QuadSPI_BUF1IND_TPINDX1_SHIFT (3U) #define QuadSPI_BUF1IND_TPINDX1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1IND_TPINDX1_SHIFT)) & QuadSPI_BUF1IND_TPINDX1_MASK) /*! @} */ /*! @name BUF2IND - Buffer2 Top Index Register */ /*! @{ */ #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) #define QuadSPI_BUF2IND_TPINDX2_SHIFT (3U) #define QuadSPI_BUF2IND_TPINDX2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK) /*! @} */ /*! @name SFAR - Serial Flash Address Register */ /*! @{ */ #define QuadSPI_SFAR_SFADR_MASK (0xFFFFFFFFU) #define QuadSPI_SFAR_SFADR_SHIFT (0U) #define QuadSPI_SFAR_SFADR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFAR_SFADR_SHIFT)) & QuadSPI_SFAR_SFADR_MASK) /*! @} */ /*! @name SFACR - Serial Flash Address Configuration Register */ /*! @{ */ #define QuadSPI_SFACR_CAS_MASK (0xFU) #define QuadSPI_SFACR_CAS_SHIFT (0U) /*! CAS - Column Address Space */ #define QuadSPI_SFACR_CAS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFACR_CAS_SHIFT)) & QuadSPI_SFACR_CAS_MASK) #define QuadSPI_SFACR_WA_MASK (0x10000U) #define QuadSPI_SFACR_WA_SHIFT (16U) /*! WA - Word Addressable * 0b0..Byte addressable serial flash mode. * 0b1..Word (2 byte) addressable serial flash mode. */ #define QuadSPI_SFACR_WA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFACR_WA_SHIFT)) & QuadSPI_SFACR_WA_MASK) /*! @} */ /*! @name SMPR - Sampling Register */ /*! @{ */ #define QuadSPI_SMPR_HSENA_MASK (0x1U) #define QuadSPI_SMPR_HSENA_SHIFT (0U) /*! HSENA - Half Speed serial flash clock Enable * 0b0..Disable divide by 2 of serial flash clock for half speed commands * 0b1..Enable divide by 2 of serial flash clock for half speed commands */ #define QuadSPI_SMPR_HSENA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSENA_SHIFT)) & QuadSPI_SMPR_HSENA_MASK) #define QuadSPI_SMPR_HSPHS_MASK (0x2U) #define QuadSPI_SMPR_HSPHS_SHIFT (1U) /*! HSPHS - Half Speed Phase selection for SDR instructions. * 0b0..Select sampling at non-inverted clock * 0b1..Select sampling at inverted clock */ #define QuadSPI_SMPR_HSPHS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSPHS_SHIFT)) & QuadSPI_SMPR_HSPHS_MASK) #define QuadSPI_SMPR_HSDLY_MASK (0x4U) #define QuadSPI_SMPR_HSDLY_SHIFT (2U) /*! HSDLY - Half Speed Delay selection for SDR instructions. * 0b0..One clock cycle delay * 0b1..Two clock cycle delay */ #define QuadSPI_SMPR_HSDLY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSDLY_SHIFT)) & QuadSPI_SMPR_HSDLY_MASK) #define QuadSPI_SMPR_FSPHS_MASK (0x20U) #define QuadSPI_SMPR_FSPHS_SHIFT (5U) /*! FSPHS - Full Speed Phase selection for SDR instructions. * 0b0..Select sampling at non-inverted clock * 0b1..Select sampling at inverted clock. */ #define QuadSPI_SMPR_FSPHS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_FSPHS_SHIFT)) & QuadSPI_SMPR_FSPHS_MASK) #define QuadSPI_SMPR_FSDLY_MASK (0x40U) #define QuadSPI_SMPR_FSDLY_SHIFT (6U) /*! FSDLY - Full Speed Delay selection for SDR instructions. Select the delay with respect to the * reference edge for the sample point valid for full speed commands. * 0b0..One clock cycle delay * 0b1..Two clock cycles delay. */ #define QuadSPI_SMPR_FSDLY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_FSDLY_SHIFT)) & QuadSPI_SMPR_FSDLY_MASK) #define QuadSPI_SMPR_DDRSMP_MASK (0x70000U) #define QuadSPI_SMPR_DDRSMP_SHIFT (16U) /*! DDRSMP - DDR Sampling point */ #define QuadSPI_SMPR_DDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_DDRSMP_SHIFT)) & QuadSPI_SMPR_DDRSMP_MASK) /*! @} */ /*! @name RBSR - RX Buffer Status Register */ /*! @{ */ #define QuadSPI_RBSR_RDBFL_MASK (0x1F00U) #define QuadSPI_RBSR_RDBFL_SHIFT (8U) #define QuadSPI_RBSR_RDBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDBFL_SHIFT)) & QuadSPI_RBSR_RDBFL_MASK) #define QuadSPI_RBSR_RDCTR_MASK (0xFFFF0000U) #define QuadSPI_RBSR_RDCTR_SHIFT (16U) #define QuadSPI_RBSR_RDCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDCTR_SHIFT)) & QuadSPI_RBSR_RDCTR_MASK) /*! @} */ /*! @name RBCT - RX Buffer Control Register */ /*! @{ */ #define QuadSPI_RBCT_WMRK_MASK (0xFU) #define QuadSPI_RBCT_WMRK_SHIFT (0U) #define QuadSPI_RBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_WMRK_SHIFT)) & QuadSPI_RBCT_WMRK_MASK) #define QuadSPI_RBCT_RXBRD_MASK (0x100U) #define QuadSPI_RBCT_RXBRD_SHIFT (8U) /*! RXBRD * 0b0..RX Buffer content is read using the AHB Bus registers QSPI_ARDB0 to QSPI_ARDB15 . For details, refer to * Exclusive Access to Serial Flash for AHB Commands. * 0b1..RX Buffer content is read using the IP Bus registers QSPI_RBDR0 to QSPI_RBDR15 . */ #define QuadSPI_RBCT_RXBRD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_RXBRD_SHIFT)) & QuadSPI_RBCT_RXBRD_MASK) /*! @} */ /*! @name TBSR - TX Buffer Status Register */ /*! @{ */ #define QuadSPI_TBSR_TRBFL_MASK (0x1F00U) #define QuadSPI_TBSR_TRBFL_SHIFT (8U) #define QuadSPI_TBSR_TRBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRBFL_SHIFT)) & QuadSPI_TBSR_TRBFL_MASK) #define QuadSPI_TBSR_TRCTR_MASK (0xFFFF0000U) #define QuadSPI_TBSR_TRCTR_SHIFT (16U) #define QuadSPI_TBSR_TRCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRCTR_SHIFT)) & QuadSPI_TBSR_TRCTR_MASK) /*! @} */ /*! @name TBDR - TX Buffer Data Register */ /*! @{ */ #define QuadSPI_TBDR_TXDATA_MASK (0xFFFFFFFFU) #define QuadSPI_TBDR_TXDATA_SHIFT (0U) #define QuadSPI_TBDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBDR_TXDATA_SHIFT)) & QuadSPI_TBDR_TXDATA_MASK) /*! @} */ /*! @name TBCT - Tx Buffer Control Register */ /*! @{ */ #define QuadSPI_TBCT_WMRK_MASK (0xFU) #define QuadSPI_TBCT_WMRK_SHIFT (0U) #define QuadSPI_TBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBCT_WMRK_SHIFT)) & QuadSPI_TBCT_WMRK_MASK) /*! @} */ /*! @name SR - Status Register */ /*! @{ */ #define QuadSPI_SR_BUSY_MASK (0x1U) #define QuadSPI_SR_BUSY_SHIFT (0U) #define QuadSPI_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_BUSY_SHIFT)) & QuadSPI_SR_BUSY_MASK) #define QuadSPI_SR_IP_ACC_MASK (0x2U) #define QuadSPI_SR_IP_ACC_SHIFT (1U) #define QuadSPI_SR_IP_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_IP_ACC_SHIFT)) & QuadSPI_SR_IP_ACC_MASK) #define QuadSPI_SR_AHB_ACC_MASK (0x4U) #define QuadSPI_SR_AHB_ACC_SHIFT (2U) #define QuadSPI_SR_AHB_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB_ACC_SHIFT)) & QuadSPI_SR_AHB_ACC_MASK) #define QuadSPI_SR_AHBGNT_MASK (0x20U) #define QuadSPI_SR_AHBGNT_SHIFT (5U) #define QuadSPI_SR_AHBGNT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBGNT_SHIFT)) & QuadSPI_SR_AHBGNT_MASK) #define QuadSPI_SR_AHBTRN_MASK (0x40U) #define QuadSPI_SR_AHBTRN_SHIFT (6U) #define QuadSPI_SR_AHBTRN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBTRN_SHIFT)) & QuadSPI_SR_AHBTRN_MASK) #define QuadSPI_SR_AHB0NE_MASK (0x80U) #define QuadSPI_SR_AHB0NE_SHIFT (7U) #define QuadSPI_SR_AHB0NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK) #define QuadSPI_SR_AHB1NE_MASK (0x100U) #define QuadSPI_SR_AHB1NE_SHIFT (8U) #define QuadSPI_SR_AHB1NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1NE_SHIFT)) & QuadSPI_SR_AHB1NE_MASK) #define QuadSPI_SR_AHB2NE_MASK (0x200U) #define QuadSPI_SR_AHB2NE_SHIFT (9U) #define QuadSPI_SR_AHB2NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2NE_SHIFT)) & QuadSPI_SR_AHB2NE_MASK) #define QuadSPI_SR_AHB3NE_MASK (0x400U) #define QuadSPI_SR_AHB3NE_SHIFT (10U) #define QuadSPI_SR_AHB3NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3NE_SHIFT)) & QuadSPI_SR_AHB3NE_MASK) #define QuadSPI_SR_AHB0FUL_MASK (0x800U) #define QuadSPI_SR_AHB0FUL_SHIFT (11U) #define QuadSPI_SR_AHB0FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK) #define QuadSPI_SR_AHB1FUL_MASK (0x1000U) #define QuadSPI_SR_AHB1FUL_SHIFT (12U) #define QuadSPI_SR_AHB1FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1FUL_SHIFT)) & QuadSPI_SR_AHB1FUL_MASK) #define QuadSPI_SR_AHB2FUL_MASK (0x2000U) #define QuadSPI_SR_AHB2FUL_SHIFT (13U) #define QuadSPI_SR_AHB2FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2FUL_SHIFT)) & QuadSPI_SR_AHB2FUL_MASK) #define QuadSPI_SR_AHB3FUL_MASK (0x4000U) #define QuadSPI_SR_AHB3FUL_SHIFT (14U) #define QuadSPI_SR_AHB3FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3FUL_SHIFT)) & QuadSPI_SR_AHB3FUL_MASK) #define QuadSPI_SR_RXWE_MASK (0x10000U) #define QuadSPI_SR_RXWE_SHIFT (16U) #define QuadSPI_SR_RXWE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK) #define QuadSPI_SR_RXFULL_MASK (0x80000U) #define QuadSPI_SR_RXFULL_SHIFT (19U) #define QuadSPI_SR_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK) #define QuadSPI_SR_RXDMA_MASK (0x800000U) #define QuadSPI_SR_RXDMA_SHIFT (23U) #define QuadSPI_SR_RXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXDMA_SHIFT)) & QuadSPI_SR_RXDMA_MASK) #define QuadSPI_SR_TXEDA_MASK (0x1000000U) #define QuadSPI_SR_TXEDA_SHIFT (24U) /*! TXEDA - Tx Buffer Enough Data Available */ #define QuadSPI_SR_TXEDA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXEDA_SHIFT)) & QuadSPI_SR_TXEDA_MASK) #define QuadSPI_SR_TXWA_MASK (0x2000000U) #define QuadSPI_SR_TXWA_SHIFT (25U) /*! TXWA - TX Buffer watermark Available */ #define QuadSPI_SR_TXWA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXWA_SHIFT)) & QuadSPI_SR_TXWA_MASK) #define QuadSPI_SR_TXDMA_MASK (0x4000000U) #define QuadSPI_SR_TXDMA_SHIFT (26U) /*! TXDMA - TXDMA */ #define QuadSPI_SR_TXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXDMA_SHIFT)) & QuadSPI_SR_TXDMA_MASK) #define QuadSPI_SR_TXFULL_MASK (0x8000000U) #define QuadSPI_SR_TXFULL_SHIFT (27U) #define QuadSPI_SR_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK) #define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) #define QuadSPI_SR_DLPSMP_SHIFT (29U) #define QuadSPI_SR_DLPSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK) /*! @} */ /*! @name FR - Flag Register */ /*! @{ */ #define QuadSPI_FR_TFF_MASK (0x1U) #define QuadSPI_FR_TFF_SHIFT (0U) #define QuadSPI_FR_TFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TFF_SHIFT)) & QuadSPI_FR_TFF_MASK) #define QuadSPI_FR_IPGEF_MASK (0x10U) #define QuadSPI_FR_IPGEF_SHIFT (4U) #define QuadSPI_FR_IPGEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPGEF_SHIFT)) & QuadSPI_FR_IPGEF_MASK) #define QuadSPI_FR_IPIEF_MASK (0x40U) #define QuadSPI_FR_IPIEF_SHIFT (6U) #define QuadSPI_FR_IPIEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPIEF_SHIFT)) & QuadSPI_FR_IPIEF_MASK) #define QuadSPI_FR_IPAEF_MASK (0x80U) #define QuadSPI_FR_IPAEF_SHIFT (7U) #define QuadSPI_FR_IPAEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPAEF_SHIFT)) & QuadSPI_FR_IPAEF_MASK) #define QuadSPI_FR_ABOF_MASK (0x1000U) #define QuadSPI_FR_ABOF_SHIFT (12U) #define QuadSPI_FR_ABOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABOF_SHIFT)) & QuadSPI_FR_ABOF_MASK) #define QuadSPI_FR_AIBSEF_MASK (0x2000U) #define QuadSPI_FR_AIBSEF_SHIFT (13U) #define QuadSPI_FR_AIBSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AIBSEF_SHIFT)) & QuadSPI_FR_AIBSEF_MASK) #define QuadSPI_FR_AITEF_MASK (0x4000U) #define QuadSPI_FR_AITEF_SHIFT (14U) #define QuadSPI_FR_AITEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AITEF_SHIFT)) & QuadSPI_FR_AITEF_MASK) #define QuadSPI_FR_ABSEF_MASK (0x8000U) #define QuadSPI_FR_ABSEF_SHIFT (15U) #define QuadSPI_FR_ABSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK) #define QuadSPI_FR_RBDF_MASK (0x10000U) #define QuadSPI_FR_RBDF_SHIFT (16U) #define QuadSPI_FR_RBDF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBDF_SHIFT)) & QuadSPI_FR_RBDF_MASK) #define QuadSPI_FR_RBOF_MASK (0x20000U) #define QuadSPI_FR_RBOF_SHIFT (17U) #define QuadSPI_FR_RBOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBOF_SHIFT)) & QuadSPI_FR_RBOF_MASK) #define QuadSPI_FR_ILLINE_MASK (0x800000U) #define QuadSPI_FR_ILLINE_SHIFT (23U) #define QuadSPI_FR_ILLINE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK) #define QuadSPI_FR_TBUF_MASK (0x4000000U) #define QuadSPI_FR_TBUF_SHIFT (26U) #define QuadSPI_FR_TBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBUF_SHIFT)) & QuadSPI_FR_TBUF_MASK) #define QuadSPI_FR_TBFF_MASK (0x8000000U) #define QuadSPI_FR_TBFF_SHIFT (27U) #define QuadSPI_FR_TBFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBFF_SHIFT)) & QuadSPI_FR_TBFF_MASK) #define QuadSPI_FR_DLPFF_MASK (0x80000000U) #define QuadSPI_FR_DLPFF_SHIFT (31U) #define QuadSPI_FR_DLPFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_DLPFF_SHIFT)) & QuadSPI_FR_DLPFF_MASK) /*! @} */ /*! @name RSER - Interrupt and DMA Request Select and Enable Register */ /*! @{ */ #define QuadSPI_RSER_TFIE_MASK (0x1U) #define QuadSPI_RSER_TFIE_SHIFT (0U) /*! TFIE * 0b0..No TFF interrupt will be generated * 0b1..TFF interrupt will be generated */ #define QuadSPI_RSER_TFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TFIE_SHIFT)) & QuadSPI_RSER_TFIE_MASK) #define QuadSPI_RSER_IPGEIE_MASK (0x10U) #define QuadSPI_RSER_IPGEIE_SHIFT (4U) /*! IPGEIE * 0b0..No IPGEF interrupt will be generated * 0b1..IPGEF interrupt will be generated */ #define QuadSPI_RSER_IPGEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPGEIE_SHIFT)) & QuadSPI_RSER_IPGEIE_MASK) #define QuadSPI_RSER_IPIEIE_MASK (0x40U) #define QuadSPI_RSER_IPIEIE_SHIFT (6U) /*! IPIEIE * 0b0..No IPIEF interrupt will be generated * 0b1..IPIEF interrupt will be generated */ #define QuadSPI_RSER_IPIEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPIEIE_SHIFT)) & QuadSPI_RSER_IPIEIE_MASK) #define QuadSPI_RSER_IPAEIE_MASK (0x80U) #define QuadSPI_RSER_IPAEIE_SHIFT (7U) /*! IPAEIE * 0b0..No IPAEF interrupt will be generated * 0b1..IPAEF interrupt will be generated */ #define QuadSPI_RSER_IPAEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPAEIE_SHIFT)) & QuadSPI_RSER_IPAEIE_MASK) #define QuadSPI_RSER_ABOIE_MASK (0x1000U) #define QuadSPI_RSER_ABOIE_SHIFT (12U) /*! ABOIE * 0b0..No ABOF interrupt will be generated * 0b1..ABOF interrupt will be generated */ #define QuadSPI_RSER_ABOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABOIE_SHIFT)) & QuadSPI_RSER_ABOIE_MASK) #define QuadSPI_RSER_AIBSIE_MASK (0x2000U) #define QuadSPI_RSER_AIBSIE_SHIFT (13U) /*! AIBSIE * 0b0..No AIBSEF interrupt will be generated * 0b1..AIBSEF interrupt will be generated */ #define QuadSPI_RSER_AIBSIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_AIBSIE_SHIFT)) & QuadSPI_RSER_AIBSIE_MASK) #define QuadSPI_RSER_AITIE_MASK (0x4000U) #define QuadSPI_RSER_AITIE_SHIFT (14U) /*! AITIE * 0b0..No AITEF interrupt will be generated * 0b1..AITEF interrupt will be generated */ #define QuadSPI_RSER_AITIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_AITIE_SHIFT)) & QuadSPI_RSER_AITIE_MASK) #define QuadSPI_RSER_ABSEIE_MASK (0x8000U) #define QuadSPI_RSER_ABSEIE_SHIFT (15U) /*! ABSEIE * 0b0..No ABSEF interrupt will be generated * 0b1..ABSEF interrupt will be generated */ #define QuadSPI_RSER_ABSEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABSEIE_SHIFT)) & QuadSPI_RSER_ABSEIE_MASK) #define QuadSPI_RSER_RBDIE_MASK (0x10000U) #define QuadSPI_RSER_RBDIE_SHIFT (16U) /*! RBDIE * 0b0..No RBDF interrupt will be generated * 0b1..RBDF Interrupt will be generated */ #define QuadSPI_RSER_RBDIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDIE_SHIFT)) & QuadSPI_RSER_RBDIE_MASK) #define QuadSPI_RSER_RBOIE_MASK (0x20000U) #define QuadSPI_RSER_RBOIE_SHIFT (17U) /*! RBOIE * 0b0..No RBOF interrupt will be generated * 0b1..RBOF interrupt will be generated */ #define QuadSPI_RSER_RBOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBOIE_SHIFT)) & QuadSPI_RSER_RBOIE_MASK) #define QuadSPI_RSER_RBDDE_MASK (0x200000U) #define QuadSPI_RSER_RBDDE_SHIFT (21U) /*! RBDDE * 0b0..No DMA request will be generated * 0b1..DMA request will be generated */ #define QuadSPI_RSER_RBDDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDDE_SHIFT)) & QuadSPI_RSER_RBDDE_MASK) #define QuadSPI_RSER_ILLINIE_MASK (0x800000U) #define QuadSPI_RSER_ILLINIE_SHIFT (23U) /*! ILLINIE * 0b0..No ILLINE interrupt will be generated * 0b1..ILLINE interrupt will be generated */ #define QuadSPI_RSER_ILLINIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ILLINIE_SHIFT)) & QuadSPI_RSER_ILLINIE_MASK) #define QuadSPI_RSER_TBFDE_MASK (0x2000000U) #define QuadSPI_RSER_TBFDE_SHIFT (25U) /*! TBFDE - TX Buffer Fill DMA Enable * 0b0..No DMA request will be generated * 0b1..DMA request will be generated */ #define QuadSPI_RSER_TBFDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFDE_SHIFT)) & QuadSPI_RSER_TBFDE_MASK) #define QuadSPI_RSER_TBUIE_MASK (0x4000000U) #define QuadSPI_RSER_TBUIE_SHIFT (26U) /*! TBUIE * 0b0..No TBUF interrupt will be generated * 0b1..TBUF interrupt will be generated */ #define QuadSPI_RSER_TBUIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBUIE_SHIFT)) & QuadSPI_RSER_TBUIE_MASK) #define QuadSPI_RSER_TBFIE_MASK (0x8000000U) #define QuadSPI_RSER_TBFIE_SHIFT (27U) /*! TBFIE * 0b0..No TBFF interrupt will be generated * 0b1..TBFF interrupt will be generated */ #define QuadSPI_RSER_TBFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFIE_SHIFT)) & QuadSPI_RSER_TBFIE_MASK) #define QuadSPI_RSER_DLPFIE_MASK (0x80000000U) #define QuadSPI_RSER_DLPFIE_SHIFT (31U) /*! DLPFIE * 0b0..No DLPFF interrupt will be generated * 0b1..DLPFF interrupt will be generated */ #define QuadSPI_RSER_DLPFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_DLPFIE_SHIFT)) & QuadSPI_RSER_DLPFIE_MASK) /*! @} */ /*! @name SPNDST - Sequence Suspend Status Register */ /*! @{ */ #define QuadSPI_SPNDST_SUSPND_MASK (0x1U) #define QuadSPI_SPNDST_SUSPND_SHIFT (0U) #define QuadSPI_SPNDST_SUSPND(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SUSPND_SHIFT)) & QuadSPI_SPNDST_SUSPND_MASK) #define QuadSPI_SPNDST_SPDBUF_MASK (0xC0U) #define QuadSPI_SPNDST_SPDBUF_SHIFT (6U) #define QuadSPI_SPNDST_SPDBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SPDBUF_SHIFT)) & QuadSPI_SPNDST_SPDBUF_MASK) #define QuadSPI_SPNDST_DATLFT_MASK (0x7E00U) #define QuadSPI_SPNDST_DATLFT_SHIFT (9U) #define QuadSPI_SPNDST_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_DATLFT_SHIFT)) & QuadSPI_SPNDST_DATLFT_MASK) /*! @} */ /*! @name SPTRCLR - Sequence Pointer Clear Register */ /*! @{ */ #define QuadSPI_SPTRCLR_BFPTRC_MASK (0x1U) #define QuadSPI_SPTRCLR_BFPTRC_SHIFT (0U) #define QuadSPI_SPTRCLR_BFPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_BFPTRC_SHIFT)) & QuadSPI_SPTRCLR_BFPTRC_MASK) #define QuadSPI_SPTRCLR_IPPTRC_MASK (0x100U) #define QuadSPI_SPTRCLR_IPPTRC_SHIFT (8U) #define QuadSPI_SPTRCLR_IPPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_IPPTRC_SHIFT)) & QuadSPI_SPTRCLR_IPPTRC_MASK) /*! @} */ /*! @name SFA1AD - Serial Flash A1 Top Address */ /*! @{ */ #define QuadSPI_SFA1AD_TPADA1_MASK (0xFFFFFC00U) #define QuadSPI_SFA1AD_TPADA1_SHIFT (10U) #define QuadSPI_SFA1AD_TPADA1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA1AD_TPADA1_SHIFT)) & QuadSPI_SFA1AD_TPADA1_MASK) /*! @} */ /*! @name SFA2AD - Serial Flash A2 Top Address */ /*! @{ */ #define QuadSPI_SFA2AD_TPADA2_MASK (0xFFFFFC00U) #define QuadSPI_SFA2AD_TPADA2_SHIFT (10U) #define QuadSPI_SFA2AD_TPADA2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA2AD_TPADA2_SHIFT)) & QuadSPI_SFA2AD_TPADA2_MASK) /*! @} */ /*! @name DLPR - Data Learn Pattern Register */ /*! @{ */ #define QuadSPI_DLPR_DLPV_MASK (0xFFFFFFFFU) #define QuadSPI_DLPR_DLPV_SHIFT (0U) #define QuadSPI_DLPR_DLPV(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLPR_DLPV_SHIFT)) & QuadSPI_DLPR_DLPV_MASK) /*! @} */ /*! @name RBDR - RX Buffer Data Register */ /*! @{ */ #define QuadSPI_RBDR_RXDATA_MASK (0xFFFFFFFFU) #define QuadSPI_RBDR_RXDATA_SHIFT (0U) #define QuadSPI_RBDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBDR_RXDATA_SHIFT)) & QuadSPI_RBDR_RXDATA_MASK) /*! @} */ /* The count of QuadSPI_RBDR */ #define QuadSPI_RBDR_COUNT (16U) /*! @name LUTKEY - LUT Key Register */ /*! @{ */ #define QuadSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) #define QuadSPI_LUTKEY_KEY_SHIFT (0U) #define QuadSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUTKEY_KEY_SHIFT)) & QuadSPI_LUTKEY_KEY_MASK) /*! @} */ /*! @name LCKCR - LUT Lock Configuration Register */ /*! @{ */ #define QuadSPI_LCKCR_LOCK_MASK (0x1U) #define QuadSPI_LCKCR_LOCK_SHIFT (0U) #define QuadSPI_LCKCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK) #define QuadSPI_LCKCR_UNLOCK_MASK (0x2U) #define QuadSPI_LCKCR_UNLOCK_SHIFT (1U) #define QuadSPI_LCKCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_UNLOCK_SHIFT)) & QuadSPI_LCKCR_UNLOCK_MASK) /*! @} */ /*! @name LUT - Look-up Table register */ /*! @{ */ #define QuadSPI_LUT_OPRND0_MASK (0xFFU) #define QuadSPI_LUT_OPRND0_SHIFT (0U) /*! OPRND0 - Operand for INSTR0. */ #define QuadSPI_LUT_OPRND0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND0_SHIFT)) & QuadSPI_LUT_OPRND0_MASK) #define QuadSPI_LUT_PAD0_MASK (0x300U) #define QuadSPI_LUT_PAD0_SHIFT (8U) /*! PAD0 - Pad information for INSTR0. * 0b00..1 Pad * 0b01..2 Pads * 0b10..4 Pads * 0b11..8 Pads */ #define QuadSPI_LUT_PAD0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD0_SHIFT)) & QuadSPI_LUT_PAD0_MASK) #define QuadSPI_LUT_INSTR0_MASK (0xFC00U) #define QuadSPI_LUT_INSTR0_SHIFT (10U) /*! INSTR0 - Instruction 0 */ #define QuadSPI_LUT_INSTR0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR0_SHIFT)) & QuadSPI_LUT_INSTR0_MASK) #define QuadSPI_LUT_OPRND1_MASK (0xFF0000U) #define QuadSPI_LUT_OPRND1_SHIFT (16U) /*! OPRND1 - Operand for INSTR1. */ #define QuadSPI_LUT_OPRND1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND1_SHIFT)) & QuadSPI_LUT_OPRND1_MASK) #define QuadSPI_LUT_PAD1_MASK (0x3000000U) #define QuadSPI_LUT_PAD1_SHIFT (24U) /*! PAD1 - Pad information for INSTR1. * 0b00..1 Pad * 0b01..2 Pads * 0b10..4 Pads * 0b11..8 Pads */ #define QuadSPI_LUT_PAD1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD1_SHIFT)) & QuadSPI_LUT_PAD1_MASK) #define QuadSPI_LUT_INSTR1_MASK (0xFC000000U) #define QuadSPI_LUT_INSTR1_SHIFT (26U) /*! INSTR1 - Instruction 1 */ #define QuadSPI_LUT_INSTR1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR1_SHIFT)) & QuadSPI_LUT_INSTR1_MASK) /*! @} */ /* The count of QuadSPI_LUT */ #define QuadSPI_LUT_COUNT (64U) /*! * @} */ /* end of group QuadSPI_Register_Masks */ /* QuadSPI - Peripheral instance base addresses */ /** Peripheral QuadSPI0 base address */ #define QuadSPI0_BASE (0x410A5000u) /** Peripheral QuadSPI0 base pointer */ #define QuadSPI0 ((QuadSPI_Type *)QuadSPI0_BASE) /** Array initializer of QuadSPI peripheral base addresses */ #define QuadSPI_BASE_ADDRS { QuadSPI0_BASE } /** Array initializer of QuadSPI peripheral base pointers */ #define QuadSPI_BASE_PTRS { QuadSPI0 } /** Interrupt vectors for the QuadSPI peripheral type */ #define QuadSPI_IRQS { QSPI_IRQn } /*! * @} */ /* end of group QuadSPI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ROMC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer * @{ */ /** ROMC - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[212]; __IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */ __IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */ uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */ __IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */ __IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_1[200]; __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */ } ROMC_Type; /* ---------------------------------------------------------------------------- -- ROMC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ROMC_Register_Masks ROMC Register Masks * @{ */ /*! @name ROMPATCHD - ROMC Data Registers */ /*! @{ */ #define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) #define ROMC_ROMPATCHD_DATAX_SHIFT (0U) /*! DATAX - DATAX */ #define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK) /*! @} */ /* The count of ROMC_ROMPATCHD */ #define ROMC_ROMPATCHD_COUNT (8U) /*! @name ROMPATCHCNTL - ROMC Control Register */ /*! @{ */ #define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU) #define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U) /*! DATAFIX - DATAFIX * 0b00000000..Address comparator triggers a opcode patch * 0b00000001..Address comparator triggers a data fix */ #define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK) #define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U) #define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U) /*! DIS - DIS * 0b0..Does not affect any ROMC functions (default) * 0b1..Disable all ROMC functions: data fixing, and opcode patching */ #define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK) /*! @} */ /*! @name ROMPATCHENL - ROMC Enable Register Low */ /*! @{ */ #define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU) #define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U) /*! ENABLE - ENABLE * 0b0000000000000000..Address comparator disabled * 0b0000000000000001..Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address */ #define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK) /*! @} */ /*! @name ROMPATCHA - ROMC Address Registers */ /*! @{ */ #define ROMC_ROMPATCHA_THUMBX_MASK (0x1U) #define ROMC_ROMPATCHA_THUMBX_SHIFT (0U) /*! THUMBX - THUMBX * 0b0..ARM patch * 0b1..THUMB patch (ignore if data fix) */ #define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK) #define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) #define ROMC_ROMPATCHA_ADDRX_SHIFT (1U) /*! ADDRX - ADDRX */ #define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK) /*! @} */ /* The count of ROMC_ROMPATCHA */ #define ROMC_ROMPATCHA_COUNT (16U) /*! @name ROMPATCHSR - ROMC Status Register */ /*! @{ */ #define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU) #define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U) /*! SOURCE - SOURCE * 0b000000..Address Comparator 0 matched * 0b000001..Address Comparator 1 matched * 0b001111..Address Comparator 15 matched */ #define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK) #define ROMC_ROMPATCHSR_SW_MASK (0x20000U) #define ROMC_ROMPATCHSR_SW_SHIFT (17U) /*! SW - SW * 0b0..no event or comparator collisions * 0b1..a collision has occurred */ #define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) /*! @} */ /*! * @} */ /* end of group ROMC_Register_Masks */ /* ROMC - Peripheral instance base addresses */ /** Peripheral ROMC0 base address */ #define ROMC0_BASE (0x41090000u) /** Peripheral ROMC0 base pointer */ #define ROMC0 ((ROMC_Type *)ROMC0_BASE) /** Peripheral ROMC1 base address */ #define ROMC1_BASE (0x40900000u) /** Peripheral ROMC1 base pointer */ #define ROMC1 ((ROMC_Type *)ROMC1_BASE) /** Array initializer of ROMC peripheral base addresses */ #define ROMC_BASE_ADDRS { ROMC0_BASE, ROMC1_BASE } /** Array initializer of ROMC peripheral base pointers */ #define ROMC_BASE_PTRS { ROMC0, ROMC1 } /*! * @} */ /* end of group ROMC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SCG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer * @{ */ /** SCG - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ uint8_t RESERVED_0[8]; __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ __IO uint32_t RCCR; /**< Run Clock Control Register, offset: 0x14 */ __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ __IO uint32_t HCCR; /**< HSRUN Clock Control Register, offset: 0x1C */ __IO uint32_t CLKOUTCNFG; /**< SCG CLKOUT Configuration Register, offset: 0x20 */ uint8_t RESERVED_1[12]; __IO uint32_t DDRCCR; /**< DDR Clock Control Register, offset: 0x30 */ uint8_t RESERVED_2[12]; __IO uint32_t NICCCR; /**< NIC Clock Control Register, offset: 0x40 */ __I uint32_t NICCSR; /**< NIC Clock Status Register, offset: 0x44 */ uint8_t RESERVED_3[184]; __IO uint32_t SOSCCSR; /**< System OSC Control Status Register, offset: 0x100 */ __IO uint32_t SOSCDIV; /**< System OSC Divide Register, offset: 0x104 */ __IO uint32_t SOSCCFG; /**< System Oscillator Configuration Register, offset: 0x108 */ uint8_t RESERVED_4[244]; __IO uint32_t SIRCCSR; /**< Slow IRC Control Status Register, offset: 0x200 */ __IO uint32_t SIRCDIV; /**< Slow IRC Divide Register, offset: 0x204 */ __IO uint32_t SIRCCFG; /**< Slow IRC Configuration Register, offset: 0x208 */ uint8_t RESERVED_5[244]; __IO uint32_t FIRCCSR; /**< Fast IRC Control Status Register, offset: 0x300 */ __IO uint32_t FIRCDIV; /**< Fast IRC Divide Register, offset: 0x304 */ __IO uint32_t FIRCCFG; /**< Fast IRC Configuration Register, offset: 0x308 */ __IO uint32_t FIRCTCFG; /**< Fast IRC Trim Configuration Register, offset: 0x30C */ uint8_t RESERVED_6[8]; __IO uint32_t FIRCSTAT; /**< Fast IRC Status Register, offset: 0x318 */ uint8_t RESERVED_7[228]; __IO uint32_t ROSCCSR; /**< RTC OSC Control Status Register, offset: 0x400 */ uint8_t RESERVED_8[252]; __IO uint32_t APLLCSR; /**< Auxiliary PLL Control Status Register, offset: 0x500 */ __IO uint32_t APLLDIV; /**< Auxiliary PLL Divide Register, offset: 0x504 */ __IO uint32_t APLLCFG; /**< Auxiliary PLL Configuration Register, offset: 0x508 */ __IO uint32_t APLLPFD; /**< Auxiliary PLL PFD Register, offset: 0x50C */ __IO uint32_t APLLNUM; /**< Auxiliary PLL Numerator Register, offset: 0x510 */ __IO uint32_t APLLDENOM; /**< Auxiliary PLL Denominator Register, offset: 0x514 */ __IO uint32_t APLLSS; /**< Auxiliary PLL Spread Spectrum Register, offset: 0x518 */ uint8_t RESERVED_9[220]; __IO uint32_t APLLLOCK_CNFG; /**< Auxiliary PLL LOCK Configuration Register, offset: 0x5F8 */ uint8_t RESERVED_10[4]; __IO uint32_t SPLLCSR; /**< System PLL Control Status Register, offset: 0x600 */ __IO uint32_t SPLLDIV; /**< System PLL Divide Register, offset: 0x604 */ __IO uint32_t SPLLCFG; /**< System PLL Configuration Register, offset: 0x608 */ __IO uint32_t SPLLPFD; /**< System PLL PFD Register, offset: 0x60C */ __IO uint32_t SPLLNUM; /**< System PLL Numerator Register, offset: 0x610 */ __IO uint32_t SPLLDENOM; /**< System PLL Denominator Register, offset: 0x614 */ __IO uint32_t SPLLSS; /**< System PLL Spread Spectrum Register, offset: 0x618 */ uint8_t RESERVED_11[220]; __IO uint32_t SPLLLOCK_CNFG; /**< System PLL LOCK Configuration Register, offset: 0x6F8 */ } SCG_Type; /* ---------------------------------------------------------------------------- -- SCG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SCG_Register_Masks SCG Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define SCG_VERID_VERSION_MASK (0xFFFFFFFFU) #define SCG_VERID_VERSION_SHIFT (0U) /*! VERSION - SCG Version Number */ #define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define SCG_PARAM_CLKPRES_MASK (0xFFU) #define SCG_PARAM_CLKPRES_SHIFT (0U) /*! CLKPRES - Clock Present * 0b00000000-0b00000001..Reserved * 0bxxxxxx1x..System OSC (SOSC) is present. * 0bxxxxx1xx..Slow IRC (SIRC) is present. * 0bxxxx1xxx..Fast IRC (FIRC) is present. * 0bxx1xxxxx..Auxiliary PLL (APLL) is present. * 0bx1xxxxxx..System PLL (SPLL) is present. */ #define SCG_PARAM_CLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_CLKPRES_SHIFT)) & SCG_PARAM_CLKPRES_MASK) #define SCG_PARAM_DIVPRES_MASK (0xF8000000U) #define SCG_PARAM_DIVPRES_SHIFT (27U) /*! DIVPRES - Divider Present * 0b1xxxx..System DIVCORE is present. */ #define SCG_PARAM_DIVPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_DIVPRES_SHIFT)) & SCG_PARAM_DIVPRES_MASK) /*! @} */ /*! @name CSR - Clock Status Register */ /*! @{ */ #define SCG_CSR_DIVSLOW_MASK (0xFU) #define SCG_CSR_DIVSLOW_SHIFT (0U) /*! DIVSLOW - Slow Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_CSR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK) #define SCG_CSR_DIVBUS_MASK (0xF0U) #define SCG_CSR_DIVBUS_SHIFT (4U) /*! DIVBUS - Bus Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_CSR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVBUS_SHIFT)) & SCG_CSR_DIVBUS_MASK) #define SCG_CSR_DIVPLAT_MASK (0xF000U) #define SCG_CSR_DIVPLAT_SHIFT (12U) /*! DIVPLAT - Platform Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Reserved * 0b0010..Reserved * 0b0011..Reserved * 0b0100..Reserved * 0b0101..Reserved * 0b0110..Reserved * 0b0111..Reserved * 0b1000..Reserved * 0b1001..Reserved * 0b1010..Reserved * 0b1011..Reserved * 0b1100..Reserved * 0b1101..Reserved * 0b1110..Reserved * 0b1111..Reserved */ #define SCG_CSR_DIVPLAT(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVPLAT_SHIFT)) & SCG_CSR_DIVPLAT_MASK) #define SCG_CSR_DIVCORE_MASK (0xF0000U) #define SCG_CSR_DIVCORE_SHIFT (16U) /*! DIVCORE - Core Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_CSR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVCORE_SHIFT)) & SCG_CSR_DIVCORE_MASK) #define SCG_CSR_SCS_MASK (0xF000000U) #define SCG_CSR_SCS_SHIFT (24U) /*! SCS - System Clock Source * 0b0000..Reserved * 0b0001..System OSC (SOSC_CLK) * 0b0010..Slow IRC (SIRC_CLK) * 0b0011..Fast IRC (FIRC_CLK) * 0b0100..Reserved * 0b0101..Auxiliary PLL (APLL_CLK) * 0b0110..System PLL (SPLL_CLK) * 0b0111..Reserved */ #define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK) /*! @} */ /*! @name RCCR - Run Clock Control Register */ /*! @{ */ #define SCG_RCCR_DIVSLOW_MASK (0xFU) #define SCG_RCCR_DIVSLOW_SHIFT (0U) /*! DIVSLOW - Slow Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_RCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVSLOW_SHIFT)) & SCG_RCCR_DIVSLOW_MASK) #define SCG_RCCR_DIVBUS_MASK (0xF0U) #define SCG_RCCR_DIVBUS_SHIFT (4U) /*! DIVBUS - Bus Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_RCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVBUS_SHIFT)) & SCG_RCCR_DIVBUS_MASK) #define SCG_RCCR_DIVPLAT_MASK (0xF000U) #define SCG_RCCR_DIVPLAT_SHIFT (12U) /*! DIVPLAT - Platform Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Reserved * 0b0010..Reserved * 0b0011..Reserved * 0b0100..Reserved * 0b0101..Reserved * 0b0110..Reserved * 0b0111..Reserved * 0b1000..Reserved * 0b1001..Reserved * 0b1010..Reserved * 0b1011..Reserved * 0b1100..Reserved * 0b1101..Reserved * 0b1110..Reserved * 0b1111..Reserved */ #define SCG_RCCR_DIVPLAT(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVPLAT_SHIFT)) & SCG_RCCR_DIVPLAT_MASK) #define SCG_RCCR_DIVCORE_MASK (0xF0000U) #define SCG_RCCR_DIVCORE_SHIFT (16U) /*! DIVCORE - Core Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_RCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVCORE_SHIFT)) & SCG_RCCR_DIVCORE_MASK) #define SCG_RCCR_SCS_MASK (0x7000000U) #define SCG_RCCR_SCS_SHIFT (24U) /*! SCS - System Clock Source * 0b000..Reserved * 0b001..System OSC (SOSC_CLK) * 0b010..Slow IRC (SIRC_CLK) * 0b011..Fast IRC (FIRC_CLK) * 0b100..Reserved * 0b101..Auxiliary PLL (APLL_CLK) * 0b110..System PLL (SPLL_CLK) * 0b111..Reserved */ #define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK) /*! @} */ /*! @name VCCR - VLPR Clock Control Register */ /*! @{ */ #define SCG_VCCR_DIVSLOW_MASK (0xFU) #define SCG_VCCR_DIVSLOW_SHIFT (0U) /*! DIVSLOW - Slow Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_VCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVSLOW_SHIFT)) & SCG_VCCR_DIVSLOW_MASK) #define SCG_VCCR_DIVBUS_MASK (0xF0U) #define SCG_VCCR_DIVBUS_SHIFT (4U) /*! DIVBUS - Bus Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_VCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVBUS_SHIFT)) & SCG_VCCR_DIVBUS_MASK) #define SCG_VCCR_DIVPLAT_MASK (0xF000U) #define SCG_VCCR_DIVPLAT_SHIFT (12U) /*! DIVPLAT - Platform Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Reserved * 0b0010..Reserved * 0b0011..Reserved * 0b0100..Reserved * 0b0101..Reserved * 0b0110..Reserved * 0b0111..Reserved * 0b1000..Reserved * 0b1001..Reserved * 0b1010..Reserved * 0b1011..Reserved * 0b1100..Reserved * 0b1101..Reserved * 0b1110..Reserved * 0b1111..Reserved */ #define SCG_VCCR_DIVPLAT(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVPLAT_SHIFT)) & SCG_VCCR_DIVPLAT_MASK) #define SCG_VCCR_DIVCORE_MASK (0xF0000U) #define SCG_VCCR_DIVCORE_SHIFT (16U) /*! DIVCORE - Core Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_VCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK) #define SCG_VCCR_SCS_MASK (0xF000000U) #define SCG_VCCR_SCS_SHIFT (24U) /*! SCS - System Clock Source * 0b0000..Reserved * 0b0001..System OSC (SOSC_CLK) * 0b0010..Slow IRC (SIRC_CLK) * 0b0011..Fast IRC (FIRC_CLK) * 0b0100..Reserved * 0b0101..Reserved * 0b0110..Reserved * 0b0111..Reserved */ #define SCG_VCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_SCS_SHIFT)) & SCG_VCCR_SCS_MASK) /*! @} */ /*! @name HCCR - HSRUN Clock Control Register */ /*! @{ */ #define SCG_HCCR_DIVSLOW_MASK (0xFU) #define SCG_HCCR_DIVSLOW_SHIFT (0U) /*! DIVSLOW - Slow Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_HCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVSLOW_SHIFT)) & SCG_HCCR_DIVSLOW_MASK) #define SCG_HCCR_DIVBUS_MASK (0xF0U) #define SCG_HCCR_DIVBUS_SHIFT (4U) /*! DIVBUS - Bus Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_HCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVBUS_SHIFT)) & SCG_HCCR_DIVBUS_MASK) #define SCG_HCCR_DIVPLAT_MASK (0xF000U) #define SCG_HCCR_DIVPLAT_SHIFT (12U) /*! DIVPLAT - Platform Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Reserved * 0b0010..Reserved * 0b0011..Reserved * 0b0100..Reserved * 0b0101..Reserved * 0b0110..Reserved * 0b0111..Reserved * 0b1000..Reserved * 0b1001..Reserved * 0b1010..Reserved * 0b1011..Reserved * 0b1100..Reserved * 0b1101..Reserved * 0b1110..Reserved * 0b1111..Reserved */ #define SCG_HCCR_DIVPLAT(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVPLAT_SHIFT)) & SCG_HCCR_DIVPLAT_MASK) #define SCG_HCCR_DIVCORE_MASK (0xF0000U) #define SCG_HCCR_DIVCORE_SHIFT (16U) /*! DIVCORE - Core Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_HCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK) #define SCG_HCCR_SCS_MASK (0xF000000U) #define SCG_HCCR_SCS_SHIFT (24U) /*! SCS - System Clock Source * 0b0000..Reserved * 0b0001..System OSC (SOSC_CLK) * 0b0010..Slow IRC (SIRC_CLK) * 0b0011..Fast IRC (FIRC_CLK) * 0b0100..Reserved * 0b0101..Auxiliary PLL (APLL_CLK) * 0b0110..System PLL (SPLL_CLK) * 0b0111..Reserved */ #define SCG_HCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_SCS_SHIFT)) & SCG_HCCR_SCS_MASK) /*! @} */ /*! @name CLKOUTCNFG - SCG CLKOUT Configuration Register */ /*! @{ */ #define SCG_CLKOUTCNFG_CLKOUTSEL_MASK (0xF000000U) #define SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT (24U) /*! CLKOUTSEL - SCG Clkout Select * 0b0000..Reserved * 0b0001..System OSC (SOSC_CLK) * 0b0010..Slow IRC (SIRC_CLK) * 0b0011..Fast IRC (FIRC_CLK) * 0b0100..Reserved * 0b0101..Auxiliary PLL (APLL_CLK) * 0b0110..System PLL (SPLL_CLK) * 0b0111..Reserved * 0b1111..NIC1 EXT CLK */ #define SCG_CLKOUTCNFG_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT)) & SCG_CLKOUTCNFG_CLKOUTSEL_MASK) /*! @} */ /*! @name DDRCCR - DDR Clock Control Register */ /*! @{ */ #define SCG_DDRCCR_DDRDIV_MASK (0x7U) #define SCG_DDRCCR_DDRDIV_SHIFT (0U) /*! DDRDIV - DDR Divider * 0b000..Output disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_DDRCCR_DDRDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_DDRCCR_DDRDIV_SHIFT)) & SCG_DDRCCR_DDRDIV_MASK) #define SCG_DDRCCR_DDRCS_MASK (0x3000000U) #define SCG_DDRCCR_DDRCS_SHIFT (24U) /*! DDRCS - DDR Clock Source * 0b00..APLL PLLS Clock * 0b01..RESERVED. Software should write 0 to this bit to maintain compatibility. * 0b10..RESERVED * 0b11..RESERVED */ #define SCG_DDRCCR_DDRCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_DDRCCR_DDRCS_SHIFT)) & SCG_DDRCCR_DDRCS_MASK) /*! @} */ /*! @name NICCCR - NIC Clock Control Register */ /*! @{ */ #define SCG_NICCCR_NIC1_DIVBUS_MASK (0xF0U) #define SCG_NICCCR_NIC1_DIVBUS_SHIFT (4U) /*! NIC1_DIVBUS - NIC1 Bus Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_NICCCR_NIC1_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_NICCCR_NIC1_DIVBUS_SHIFT)) & SCG_NICCCR_NIC1_DIVBUS_MASK) #define SCG_NICCCR_NIC1_DIVEXT_MASK (0xF00U) #define SCG_NICCCR_NIC1_DIVEXT_SHIFT (8U) /*! NIC1_DIVEXT - NIC1 External Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_NICCCR_NIC1_DIVEXT(x) (((uint32_t)(((uint32_t)(x)) << SCG_NICCCR_NIC1_DIVEXT_SHIFT)) & SCG_NICCCR_NIC1_DIVEXT_MASK) #define SCG_NICCCR_NIC1_DIV_MASK (0xF0000U) #define SCG_NICCCR_NIC1_DIV_SHIFT (16U) /*! NIC1_DIV - NIC1 Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_NICCCR_NIC1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_NICCCR_NIC1_DIV_SHIFT)) & SCG_NICCCR_NIC1_DIV_MASK) #define SCG_NICCCR_GPU_DIV_MASK (0xF00000U) #define SCG_NICCCR_GPU_DIV_SHIFT (20U) /*! GPU_DIV - GPU Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_NICCCR_GPU_DIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_NICCCR_GPU_DIV_SHIFT)) & SCG_NICCCR_GPU_DIV_MASK) #define SCG_NICCCR_NIC0_DIV_MASK (0xF000000U) #define SCG_NICCCR_NIC0_DIV_SHIFT (24U) /*! NIC0_DIV - NIC0 Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_NICCCR_NIC0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_NICCCR_NIC0_DIV_SHIFT)) & SCG_NICCCR_NIC0_DIV_MASK) #define SCG_NICCCR_NICCS_MASK (0x30000000U) #define SCG_NICCCR_NICCS_SHIFT (28U) /*! NICCS - NIC Clock Source * 0b00..Fast IRC * 0b01..DDR Clock * 0b10..NIC External PLL * 0b11..RESERVED */ #define SCG_NICCCR_NICCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_NICCCR_NICCS_SHIFT)) & SCG_NICCCR_NICCS_MASK) /*! @} */ /*! @name NICCSR - NIC Clock Status Register */ /*! @{ */ #define SCG_NICCSR_NIC1_DIVBUS_MASK (0xF0U) #define SCG_NICCSR_NIC1_DIVBUS_SHIFT (4U) /*! NIC1_DIVBUS - NIC1 Bus Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_NICCSR_NIC1_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_NICCSR_NIC1_DIVBUS_SHIFT)) & SCG_NICCSR_NIC1_DIVBUS_MASK) #define SCG_NICCSR_NIC1_DIVEXT_MASK (0xF00U) #define SCG_NICCSR_NIC1_DIVEXT_SHIFT (8U) /*! NIC1_DIVEXT - NIC1 External Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_NICCSR_NIC1_DIVEXT(x) (((uint32_t)(((uint32_t)(x)) << SCG_NICCSR_NIC1_DIVEXT_SHIFT)) & SCG_NICCSR_NIC1_DIVEXT_MASK) #define SCG_NICCSR_NIC1_DIV_MASK (0xF0000U) #define SCG_NICCSR_NIC1_DIV_SHIFT (16U) /*! NIC1_DIV - NIC1 Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_NICCSR_NIC1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_NICCSR_NIC1_DIV_SHIFT)) & SCG_NICCSR_NIC1_DIV_MASK) #define SCG_NICCSR_GPU_DIV_MASK (0xF00000U) #define SCG_NICCSR_GPU_DIV_SHIFT (20U) /*! GPU_DIV - GPU Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_NICCSR_GPU_DIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_NICCSR_GPU_DIV_SHIFT)) & SCG_NICCSR_GPU_DIV_MASK) #define SCG_NICCSR_NIC0_DIV_MASK (0xF000000U) #define SCG_NICCSR_NIC0_DIV_SHIFT (24U) /*! NIC0_DIV - NIC0 Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_NICCSR_NIC0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_NICCSR_NIC0_DIV_SHIFT)) & SCG_NICCSR_NIC0_DIV_MASK) #define SCG_NICCSR_NICCS_MASK (0x30000000U) #define SCG_NICCSR_NICCS_SHIFT (28U) /*! NICCS - NIC Clock Source * 0b00..Fast IRC * 0b01..DDR Clock * 0b10..NIC External PLL * 0b11..Reserved */ #define SCG_NICCSR_NICCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_NICCSR_NICCS_SHIFT)) & SCG_NICCSR_NICCS_MASK) /*! @} */ /*! @name SOSCCSR - System OSC Control Status Register */ /*! @{ */ #define SCG_SOSCCSR_SOSCEN_MASK (0x1U) #define SCG_SOSCCSR_SOSCEN_SHIFT (0U) /*! SOSCEN - System OSC Enable * 0b0..System OSC is disabled * 0b1..System OSC is enabled */ #define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK) #define SCG_SOSCCSR_SOSCSTEN_MASK (0x2U) #define SCG_SOSCCSR_SOSCSTEN_SHIFT (1U) /*! SOSCSTEN - System OSC Stop Enable * 0b0..System OSC is disabled in Stop modes * 0b1..System OSC is enabled in Stop modes if SOSCEN=1. In VLLS0, system oscillator is disabled even if * SOSCSTEN=1 and SOSCEN=1. When selected as the reference clock to the System PLL and if the System PLL is enabled * in STOP mode, the SOSC will stay enabled even if SOSCSTEN=0. */ #define SCG_SOSCCSR_SOSCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK) #define SCG_SOSCCSR_SOSCLPEN_MASK (0x4U) #define SCG_SOSCCSR_SOSCLPEN_SHIFT (2U) /*! SOSCLPEN - System OSC Low Power Enable * 0b0..System OSC is disabled in VLP modes * 0b1..System OSC is enabled in VLP modes */ #define SCG_SOSCCSR_SOSCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCLPEN_SHIFT)) & SCG_SOSCCSR_SOSCLPEN_MASK) #define SCG_SOSCCSR_SOSCCM_MASK (0x10000U) #define SCG_SOSCCSR_SOSCCM_SHIFT (16U) /*! SOSCCM - System OSC Clock Monitor Enable * 0b0..System OSC Clock Monitor is disabled * 0b1..System OSC Clock Monitor is enabled */ #define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK) #define SCG_SOSCCSR_SOSCCMRE_MASK (0x20000U) #define SCG_SOSCCSR_SOSCCMRE_SHIFT (17U) /*! SOSCCMRE - System OSC Clock Monitor Reset Enable * 0b0..Clock Monitor generates interrupt when error detected * 0b1..Clock Monitor generates reset when error detected */ #define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK) #define SCG_SOSCCSR_LK_MASK (0x800000U) #define SCG_SOSCCSR_LK_SHIFT (23U) /*! LK - Lock Register * 0b0..This Control Status Register can be written. * 0b1..This Control Status Register cannot be written. */ #define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK) #define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U) #define SCG_SOSCCSR_SOSCVLD_SHIFT (24U) /*! SOSCVLD - System OSC Valid * 0b0..System OSC is not enabled or clock is not valid * 0b1..System OSC is enabled and output clock is valid */ #define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK) #define SCG_SOSCCSR_SOSCSEL_MASK (0x2000000U) #define SCG_SOSCCSR_SOSCSEL_SHIFT (25U) /*! SOSCSEL - System OSC Selected * 0b0..System OSC is not the system clock source * 0b1..System OSC is the system clock source */ #define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK) #define SCG_SOSCCSR_SOSCERR_MASK (0x4000000U) #define SCG_SOSCCSR_SOSCERR_SHIFT (26U) /*! SOSCERR - System OSC Clock Error * 0b0..System OSC Clock Monitor is disabled or has not detected an error * 0b1..System OSC Clock Monitor is enabled and detected an error */ #define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK) /*! @} */ /*! @name SOSCDIV - System OSC Divide Register */ /*! @{ */ #define SCG_SOSCDIV_SOSCDIV1_MASK (0x7U) #define SCG_SOSCDIV_SOSCDIV1_SHIFT (0U) /*! SOSCDIV1 - System OSC Clock Divide 1 * 0b000..Output disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_SOSCDIV_SOSCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV1_SHIFT)) & SCG_SOSCDIV_SOSCDIV1_MASK) #define SCG_SOSCDIV_SOSCDIV2_MASK (0x700U) #define SCG_SOSCDIV_SOSCDIV2_SHIFT (8U) /*! SOSCDIV2 - System OSC Clock Divide 2 * 0b000..Output disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_SOSCDIV_SOSCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV2_SHIFT)) & SCG_SOSCDIV_SOSCDIV2_MASK) #define SCG_SOSCDIV_SOSCDIV3_MASK (0x70000U) #define SCG_SOSCDIV_SOSCDIV3_SHIFT (16U) /*! SOSCDIV3 - System OSC Clock Divide 3 * 0b000..Output disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_SOSCDIV_SOSCDIV3(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV3_SHIFT)) & SCG_SOSCDIV_SOSCDIV3_MASK) /*! @} */ /*! @name SOSCCFG - System Oscillator Configuration Register */ /*! @{ */ #define SCG_SOSCCFG_EREFS_MASK (0x4U) #define SCG_SOSCCFG_EREFS_SHIFT (2U) /*! EREFS - External Reference Select * 0b0..External reference clock selected * 0b1..Internal crystal oscillator of OSC requested. In VLLS0, the internal oscillator of OSC is disabled even if SOSCEN=1 and SOSCSTEN=1. */ #define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_EREFS_SHIFT)) & SCG_SOSCCFG_EREFS_MASK) #define SCG_SOSCCFG_HGO_MASK (0x8U) #define SCG_SOSCCFG_HGO_SHIFT (3U) /*! HGO - High Gain Oscillator Select * 0b0..Configure crystal oscillator for low-power operation * 0b1..Configure crystal oscillator for high-gain operation */ #define SCG_SOSCCFG_HGO(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_HGO_SHIFT)) & SCG_SOSCCFG_HGO_MASK) /*! @} */ /*! @name SIRCCSR - Slow IRC Control Status Register */ /*! @{ */ #define SCG_SIRCCSR_SIRCEN_MASK (0x1U) #define SCG_SIRCCSR_SIRCEN_SHIFT (0U) /*! SIRCEN - Slow IRC Enable * 0b0..Slow IRC is disabled * 0b1..Slow IRC is enabled */ #define SCG_SIRCCSR_SIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCEN_SHIFT)) & SCG_SIRCCSR_SIRCEN_MASK) #define SCG_SIRCCSR_SIRCSTEN_MASK (0x2U) #define SCG_SIRCCSR_SIRCSTEN_SHIFT (1U) /*! SIRCSTEN - Slow IRC Stop Enable * 0b0..Slow IRC is disabled in Stop modes * 0b1..Slow IRC is enabled in Stop modes */ #define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK) #define SCG_SIRCCSR_SIRCLPEN_MASK (0x4U) #define SCG_SIRCCSR_SIRCLPEN_SHIFT (2U) /*! SIRCLPEN - Slow IRC Low Power Enable * 0b0..Slow IRC is disabled in VLP modes * 0b1..Slow IRC is enabled in VLP modes */ #define SCG_SIRCCSR_SIRCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCLPEN_SHIFT)) & SCG_SIRCCSR_SIRCLPEN_MASK) #define SCG_SIRCCSR_LPOPO_MASK (0x10U) #define SCG_SIRCCSR_LPOPO_SHIFT (4U) /*! LPOPO - LPO Power Option * 0b0..LPO clock is enabled in LLS/VLLSx * 0b1..LPO clock is disabled in LLS/VLLSx */ #define SCG_SIRCCSR_LPOPO(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LPOPO_SHIFT)) & SCG_SIRCCSR_LPOPO_MASK) #define SCG_SIRCCSR_LK_MASK (0x800000U) #define SCG_SIRCCSR_LK_SHIFT (23U) /*! LK - Lock Register * 0b0..Control Status Register can be written. * 0b1..Control Status Register cannot be written. */ #define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK) #define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U) #define SCG_SIRCCSR_SIRCVLD_SHIFT (24U) /*! SIRCVLD - Slow IRC Valid * 0b0..Slow IRC is not enabled or clock is not valid * 0b1..Slow IRC is enabled and output clock is valid */ #define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK) #define SCG_SIRCCSR_SIRCSEL_MASK (0x2000000U) #define SCG_SIRCCSR_SIRCSEL_SHIFT (25U) /*! SIRCSEL - Slow IRC Selected * 0b0..Slow IRC is not the system clock source * 0b1..Slow IRC is the system clock source */ #define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK) /*! @} */ /*! @name SIRCDIV - Slow IRC Divide Register */ /*! @{ */ #define SCG_SIRCDIV_SIRCDIV1_MASK (0x7U) #define SCG_SIRCDIV_SIRCDIV1_SHIFT (0U) /*! SIRCDIV1 - Slow IRC Clock Divide 1 * 0b000..Output disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_SIRCDIV_SIRCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV1_SHIFT)) & SCG_SIRCDIV_SIRCDIV1_MASK) #define SCG_SIRCDIV_SIRCDIV2_MASK (0x700U) #define SCG_SIRCDIV_SIRCDIV2_SHIFT (8U) /*! SIRCDIV2 - Slow IRC Clock Divide 2 * 0b000..Output disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_SIRCDIV_SIRCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV2_SHIFT)) & SCG_SIRCDIV_SIRCDIV2_MASK) #define SCG_SIRCDIV_SIRCDIV3_MASK (0x70000U) #define SCG_SIRCDIV_SIRCDIV3_SHIFT (16U) /*! SIRCDIV3 - Slow IRC Clock Divider 3 * 0b000..Output disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_SIRCDIV_SIRCDIV3(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV3_SHIFT)) & SCG_SIRCDIV_SIRCDIV3_MASK) /*! @} */ /*! @name SIRCCFG - Slow IRC Configuration Register */ /*! @{ */ #define SCG_SIRCCFG_RANGE_MASK (0x1U) #define SCG_SIRCCFG_RANGE_SHIFT (0U) /*! RANGE - Frequency Range * 0b0..Slow IRC low range clock ( 4MHz) * 0b1..Slow IRC high range clock ( 16 MHz) */ #define SCG_SIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCFG_RANGE_SHIFT)) & SCG_SIRCCFG_RANGE_MASK) /*! @} */ /*! @name FIRCCSR - Fast IRC Control Status Register */ /*! @{ */ #define SCG_FIRCCSR_FIRCEN_MASK (0x1U) #define SCG_FIRCCSR_FIRCEN_SHIFT (0U) /*! FIRCEN - Fast IRC Enable * 0b0..Fast IRC is disabled * 0b1..Fast IRC is enabled */ #define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK) #define SCG_FIRCCSR_FIRCSTEN_MASK (0x2U) #define SCG_FIRCCSR_FIRCSTEN_SHIFT (1U) /*! FIRCSTEN - Fast IRC Stop Enable * 0b0..Fast IRC is disabled in Stop modes. * 0b1..Fast IRC is enabled in Stop modes */ #define SCG_FIRCCSR_FIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK) #define SCG_FIRCCSR_FIRCLPEN_MASK (0x4U) #define SCG_FIRCCSR_FIRCLPEN_SHIFT (2U) /*! FIRCLPEN - Fast IRC Low Power Enable * 0b0..Fast IRC is disabled in VLP modes * 0b1..Fast IRC is enabled in VLP modes */ #define SCG_FIRCCSR_FIRCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCLPEN_SHIFT)) & SCG_FIRCCSR_FIRCLPEN_MASK) #define SCG_FIRCCSR_FIRCTREN_MASK (0x100U) #define SCG_FIRCCSR_FIRCTREN_SHIFT (8U) /*! FIRCTREN - Fast IRC Trim Enable * 0b0..Disable trimming Fast IRC to an external clock source * 0b1..Enable trimming Fast IRC to an external clock source */ #define SCG_FIRCCSR_FIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTREN_SHIFT)) & SCG_FIRCCSR_FIRCTREN_MASK) #define SCG_FIRCCSR_FIRCTRUP_MASK (0x200U) #define SCG_FIRCCSR_FIRCTRUP_SHIFT (9U) /*! FIRCTRUP - Fast IRC Trim Update * 0b0..Disable Fast IRC trimming updates * 0b1..Enable Fast IRC trimming updates */ #define SCG_FIRCCSR_FIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTRUP_SHIFT)) & SCG_FIRCCSR_FIRCTRUP_MASK) #define SCG_FIRCCSR_POSTDIV_MASK (0x3000U) #define SCG_FIRCCSR_POSTDIV_SHIFT (12U) /*! POSTDIV - Fast IRC Divider * 0b00..Divide by 1 * 0b01..Divide by 2 * 0b10..Divide by 3 * 0b11..Divide by 4 */ #define SCG_FIRCCSR_POSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_POSTDIV_SHIFT)) & SCG_FIRCCSR_POSTDIV_MASK) #define SCG_FIRCCSR_LK_MASK (0x800000U) #define SCG_FIRCCSR_LK_SHIFT (23U) /*! LK - Lock Register * 0b0..Control Status Register can be written. * 0b1..Control Status Register cannot be written. */ #define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK) #define SCG_FIRCCSR_FIRCVLD_MASK (0x1000000U) #define SCG_FIRCCSR_FIRCVLD_SHIFT (24U) /*! FIRCVLD - Fast IRC Valid status * 0b0..Fast IRC is not enabled or clock is not valid. * 0b1..Fast IRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog. */ #define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK) #define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) #define SCG_FIRCCSR_FIRCSEL_SHIFT (25U) /*! FIRCSEL - Fast IRC Selected status * 0b0..Fast IRC is not the system clock source * 0b1..Fast IRC is the system clock source */ #define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK) #define SCG_FIRCCSR_FIRCERR_MASK (0x4000000U) #define SCG_FIRCCSR_FIRCERR_SHIFT (26U) /*! FIRCERR - Fast IRC Clock Error * 0b0..Error not detected with the Fast IRC trimming. * 0b1..Error detected with the Fast IRC trimming. */ #define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK) /*! @} */ /*! @name FIRCDIV - Fast IRC Divide Register */ /*! @{ */ #define SCG_FIRCDIV_FIRCDIV1_MASK (0x7U) #define SCG_FIRCDIV_FIRCDIV1_SHIFT (0U) /*! FIRCDIV1 - Fast IRC Clock Divide 1 * 0b000..Output disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_FIRCDIV_FIRCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV1_SHIFT)) & SCG_FIRCDIV_FIRCDIV1_MASK) #define SCG_FIRCDIV_FIRCDIV2_MASK (0x700U) #define SCG_FIRCDIV_FIRCDIV2_SHIFT (8U) /*! FIRCDIV2 - Fast IRC Clock Divide 2 * 0b000..Output disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_FIRCDIV_FIRCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV2_SHIFT)) & SCG_FIRCDIV_FIRCDIV2_MASK) #define SCG_FIRCDIV_FIRCDIV3_MASK (0x70000U) #define SCG_FIRCDIV_FIRCDIV3_SHIFT (16U) /*! FIRCDIV3 - Fast IRC Clock Divider 3 * 0b000..Clock disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_FIRCDIV_FIRCDIV3(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV3_SHIFT)) & SCG_FIRCDIV_FIRCDIV3_MASK) /*! @} */ /*! @name FIRCCFG - Fast IRC Configuration Register */ /*! @{ */ #define SCG_FIRCCFG_RANGE_MASK (0x3U) #define SCG_FIRCCFG_RANGE_SHIFT (0U) /*! RANGE - Frequency Range * 0b00..Fast IRC is trimmed to 48 MHz * 0b01..Fast IRC is trimmed to 52 MHz * 0b10..Fast IRC is trimmed to 56 MHz * 0b11..Fast IRC is trimmed to 60 MHz */ #define SCG_FIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_RANGE_SHIFT)) & SCG_FIRCCFG_RANGE_MASK) /*! @} */ /*! @name FIRCTCFG - Fast IRC Trim Configuration Register */ /*! @{ */ #define SCG_FIRCTCFG_TRIMSRC_MASK (0x3U) #define SCG_FIRCTCFG_TRIMSRC_SHIFT (0U) /*! TRIMSRC - Trim Source * 0b00..Reserved * 0b01..Reserved * 0b10..System OSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency slower than 32kHz. * 0b11..RTC OSC (32.768 kHz) */ #define SCG_FIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMSRC_SHIFT)) & SCG_FIRCTCFG_TRIMSRC_MASK) #define SCG_FIRCTCFG_TRIMDIV_MASK (0x700U) #define SCG_FIRCTCFG_TRIMDIV_SHIFT (8U) /*! TRIMDIV - Fast IRC Trim Predivide * 0b000..Divide by 1 * 0b001..Divide by 128 * 0b010..Divide by 256 * 0b011..Divide by 512 * 0b100..Divide by 1024 * 0b101..Divide by 2048 * 0b110..Reserved. Writing this value will result in Divide by 1. * 0b111..Reserved. Writing this value will result in a Divide by 1. */ #define SCG_FIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMDIV_SHIFT)) & SCG_FIRCTCFG_TRIMDIV_MASK) /*! @} */ /*! @name FIRCSTAT - Fast IRC Status Register */ /*! @{ */ #define SCG_FIRCSTAT_TRIMFINE_MASK (0x7FU) #define SCG_FIRCSTAT_TRIMFINE_SHIFT (0U) /*! TRIMFINE - Trim Fine */ #define SCG_FIRCSTAT_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMFINE_SHIFT)) & SCG_FIRCSTAT_TRIMFINE_MASK) #define SCG_FIRCSTAT_TRIMCOAR_MASK (0x3F00U) #define SCG_FIRCSTAT_TRIMCOAR_SHIFT (8U) /*! TRIMCOAR - Trim Coarse */ #define SCG_FIRCSTAT_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMCOAR_SHIFT)) & SCG_FIRCSTAT_TRIMCOAR_MASK) /*! @} */ /*! @name ROSCCSR - RTC OSC Control Status Register */ /*! @{ */ #define SCG_ROSCCSR_ROSCCM_MASK (0x10000U) #define SCG_ROSCCSR_ROSCCM_SHIFT (16U) /*! ROSCCM - RTC OSC Clock Monitor * 0b0..RTC OSC Clock Monitor is disabled * 0b1..RTC OSC Clock Monitor is enabled */ #define SCG_ROSCCSR_ROSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCM_SHIFT)) & SCG_ROSCCSR_ROSCCM_MASK) #define SCG_ROSCCSR_ROSCCMRE_MASK (0x20000U) #define SCG_ROSCCSR_ROSCCMRE_SHIFT (17U) /*! ROSCCMRE - RTC OSC Clock Monitor Reset Enable * 0b0..Clock Monitor generates interrupt when error detected * 0b1..Clock Monitor generates reset when error detected */ #define SCG_ROSCCSR_ROSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCMRE_SHIFT)) & SCG_ROSCCSR_ROSCCMRE_MASK) #define SCG_ROSCCSR_LK_MASK (0x800000U) #define SCG_ROSCCSR_LK_SHIFT (23U) /*! LK - Lock Register * 0b0..Control Status Register can be written. * 0b1..Control Status Register cannot be written. */ #define SCG_ROSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_LK_SHIFT)) & SCG_ROSCCSR_LK_MASK) #define SCG_ROSCCSR_ROSCVLD_MASK (0x1000000U) #define SCG_ROSCCSR_ROSCVLD_SHIFT (24U) /*! ROSCVLD - RTC OSC Valid * 0b0..RTC OSC is not enabled or clock is not valid * 0b1..RTC OSC is enabled and output clock is valid */ #define SCG_ROSCCSR_ROSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCVLD_SHIFT)) & SCG_ROSCCSR_ROSCVLD_MASK) #define SCG_ROSCCSR_ROSCSEL_MASK (0x2000000U) #define SCG_ROSCCSR_ROSCSEL_SHIFT (25U) /*! ROSCSEL - RTC OSC Selected * 0b0..RTC OSC is not the system clock source * 0b1..RTC OSC is the system clock source */ #define SCG_ROSCCSR_ROSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCSEL_SHIFT)) & SCG_ROSCCSR_ROSCSEL_MASK) #define SCG_ROSCCSR_ROSCERR_MASK (0x4000000U) #define SCG_ROSCCSR_ROSCERR_SHIFT (26U) /*! ROSCERR - RTC OSC Clock Error * 0b0..RTC OSC Clock Monitor is disabled or has not detected an error * 0b1..RTC OSC Clock Monitor is enabled and detected an RTC loss of clock error */ #define SCG_ROSCCSR_ROSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCERR_SHIFT)) & SCG_ROSCCSR_ROSCERR_MASK) /*! @} */ /*! @name APLLCSR - Auxiliary PLL Control Status Register */ /*! @{ */ #define SCG_APLLCSR_APLLEN_MASK (0x1U) #define SCG_APLLCSR_APLLEN_SHIFT (0U) /*! APLLEN - Auxiliary PLL (APLL) Enable * 0b0..APLL is disabled * 0b1..APLL is enabled */ #define SCG_APLLCSR_APLLEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLEN_SHIFT)) & SCG_APLLCSR_APLLEN_MASK) #define SCG_APLLCSR_APLLSTEN_MASK (0x2U) #define SCG_APLLCSR_APLLSTEN_SHIFT (1U) /*! APLLSTEN - APLL Stop Enable * 0b0..APLL is disabled in Stop modes * 0b1..APLL is enabled in Stop modes */ #define SCG_APLLCSR_APLLSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLSTEN_SHIFT)) & SCG_APLLCSR_APLLSTEN_MASK) #define SCG_APLLCSR_LK_MASK (0x800000U) #define SCG_APLLCSR_LK_SHIFT (23U) /*! LK - Lock Register * 0b0..Control Status Register can be written. * 0b1..Control Status Register cannot be written. */ #define SCG_APLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_LK_SHIFT)) & SCG_APLLCSR_LK_MASK) #define SCG_APLLCSR_APLLVLD_MASK (0x1000000U) #define SCG_APLLCSR_APLLVLD_SHIFT (24U) /*! APLLVLD - APLL Valid * 0b0..APLL is not enabled or clock is not valid * 0b1..APLL is enabled and output clock is valid */ #define SCG_APLLCSR_APLLVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLVLD_SHIFT)) & SCG_APLLCSR_APLLVLD_MASK) #define SCG_APLLCSR_APLLSEL_MASK (0x2000000U) #define SCG_APLLCSR_APLLSEL_SHIFT (25U) /*! APLLSEL - APLL Selected * 0b0..APLL is not the system clock source * 0b1..APLL is the system clock source */ #define SCG_APLLCSR_APLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLSEL_SHIFT)) & SCG_APLLCSR_APLLSEL_MASK) /*! @} */ /*! @name APLLDIV - Auxiliary PLL Divide Register */ /*! @{ */ #define SCG_APLLDIV_APLLDIV1_MASK (0x7U) #define SCG_APLLDIV_APLLDIV1_SHIFT (0U) /*! APLLDIV1 - Auxiliary PLL Clock Divide 1 * 0b000..Clock disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_APLLDIV_APLLDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLDIV_APLLDIV1_SHIFT)) & SCG_APLLDIV_APLLDIV1_MASK) #define SCG_APLLDIV_APLLDIV2_MASK (0x700U) #define SCG_APLLDIV_APLLDIV2_SHIFT (8U) /*! APLLDIV2 - Auxiliary PLL Clock Divide 2 * 0b000..Clock disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_APLLDIV_APLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLDIV_APLLDIV2_SHIFT)) & SCG_APLLDIV_APLLDIV2_MASK) #define SCG_APLLDIV_APLLDIV3_MASK (0x70000U) #define SCG_APLLDIV_APLLDIV3_SHIFT (16U) /*! APLLDIV3 - Auxiliary PLL Clock Divide 3 * 0b000..Clock disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_APLLDIV_APLLDIV3(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLDIV_APLLDIV3_SHIFT)) & SCG_APLLDIV_APLLDIV3_MASK) /*! @} */ /*! @name APLLCFG - Auxiliary PLL Configuration Register */ /*! @{ */ #define SCG_APLLCFG_SOURCE_MASK (0x1U) #define SCG_APLLCFG_SOURCE_SHIFT (0U) /*! SOURCE - Clock Source * 0b0..System OSC * 0b1..Reserved */ #define SCG_APLLCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCFG_SOURCE_SHIFT)) & SCG_APLLCFG_SOURCE_MASK) #define SCG_APLLCFG_PLLS_MASK (0x2U) #define SCG_APLLCFG_PLLS_SHIFT (1U) /*! PLLS - PLL Select * 0b1..APLL PFD output clock selected * 0b0..APLL clock selected. */ #define SCG_APLLCFG_PLLS(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCFG_PLLS_SHIFT)) & SCG_APLLCFG_PLLS_MASK) #define SCG_APLLCFG_PREDIV_MASK (0x700U) #define SCG_APLLCFG_PREDIV_SHIFT (8U) /*! PREDIV - PLL Reference Clock Divider */ #define SCG_APLLCFG_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCFG_PREDIV_SHIFT)) & SCG_APLLCFG_PREDIV_MASK) #define SCG_APLLCFG_PFDSEL_MASK (0xC000U) #define SCG_APLLCFG_PFDSEL_SHIFT (14U) /*! PFDSEL - PFD Clock Select * 0b00..PFD0 output clock selected. * 0b01..PFD1 output clock selected. * 0b10..PFD2 output clock selected. * 0b11..PFD3 output clock selected. */ #define SCG_APLLCFG_PFDSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCFG_PFDSEL_SHIFT)) & SCG_APLLCFG_PFDSEL_MASK) #define SCG_APLLCFG_MULT_MASK (0x7F0000U) #define SCG_APLLCFG_MULT_SHIFT (16U) /*! MULT - Auxiliary PLL Multiplier */ #define SCG_APLLCFG_MULT(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCFG_MULT_SHIFT)) & SCG_APLLCFG_MULT_MASK) #define SCG_APLLCFG_PLLPOSTDIV1_MASK (0xF000000U) #define SCG_APLLCFG_PLLPOSTDIV1_SHIFT (24U) /*! PLLPOSTDIV1 - Auxiliary PLL Post Clock Divide1 Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_APLLCFG_PLLPOSTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCFG_PLLPOSTDIV1_SHIFT)) & SCG_APLLCFG_PLLPOSTDIV1_MASK) #define SCG_APLLCFG_PLLPOSTDIV2_MASK (0xF0000000U) #define SCG_APLLCFG_PLLPOSTDIV2_SHIFT (28U) /*! PLLPOSTDIV2 - Auxiliary PLL Post Clock Divide2 Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_APLLCFG_PLLPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCFG_PLLPOSTDIV2_SHIFT)) & SCG_APLLCFG_PLLPOSTDIV2_MASK) /*! @} */ /*! @name APLLPFD - Auxiliary PLL PFD Register */ /*! @{ */ #define SCG_APLLPFD_PFD0_MASK (0x3FU) #define SCG_APLLPFD_PFD0_SHIFT (0U) /*! PFD0 - PLL Fractional Divider 0 */ #define SCG_APLLPFD_PFD0(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPFD_PFD0_SHIFT)) & SCG_APLLPFD_PFD0_MASK) #define SCG_APLLPFD_PFD0_VALID_MASK (0x40U) #define SCG_APLLPFD_PFD0_VALID_SHIFT (6U) /*! PFD0_VALID - PFD0_VALID */ #define SCG_APLLPFD_PFD0_VALID(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPFD_PFD0_VALID_SHIFT)) & SCG_APLLPFD_PFD0_VALID_MASK) #define SCG_APLLPFD_PFD0_CLKGATE_MASK (0x80U) #define SCG_APLLPFD_PFD0_CLKGATE_SHIFT (7U) /*! PFD0_CLKGATE - PFD0_CLKGATE * 0b0..PFD0 clock is not gated. * 0b1..PFD0 clock is gated. */ #define SCG_APLLPFD_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPFD_PFD0_CLKGATE_SHIFT)) & SCG_APLLPFD_PFD0_CLKGATE_MASK) #define SCG_APLLPFD_PFD1_MASK (0x3F00U) #define SCG_APLLPFD_PFD1_SHIFT (8U) /*! PFD1 - PLL Fractional Divider 1 */ #define SCG_APLLPFD_PFD1(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPFD_PFD1_SHIFT)) & SCG_APLLPFD_PFD1_MASK) #define SCG_APLLPFD_PFD1_VALID_MASK (0x4000U) #define SCG_APLLPFD_PFD1_VALID_SHIFT (14U) /*! PFD1_VALID - PFD1_VALID */ #define SCG_APLLPFD_PFD1_VALID(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPFD_PFD1_VALID_SHIFT)) & SCG_APLLPFD_PFD1_VALID_MASK) #define SCG_APLLPFD_PFD1_CLKGATE_MASK (0x8000U) #define SCG_APLLPFD_PFD1_CLKGATE_SHIFT (15U) /*! PFD1_CLKGATE - PFD1_CLKGATE * 0b0..PFD1 clock is not gated. * 0b1..PFD1 clock is gated. */ #define SCG_APLLPFD_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPFD_PFD1_CLKGATE_SHIFT)) & SCG_APLLPFD_PFD1_CLKGATE_MASK) #define SCG_APLLPFD_PFD2_MASK (0x3F0000U) #define SCG_APLLPFD_PFD2_SHIFT (16U) /*! PFD2 - PLL Fractional Divider 2 */ #define SCG_APLLPFD_PFD2(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPFD_PFD2_SHIFT)) & SCG_APLLPFD_PFD2_MASK) #define SCG_APLLPFD_PFD2_VALID_MASK (0x400000U) #define SCG_APLLPFD_PFD2_VALID_SHIFT (22U) /*! PFD2_VALID - PFD2_VALID */ #define SCG_APLLPFD_PFD2_VALID(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPFD_PFD2_VALID_SHIFT)) & SCG_APLLPFD_PFD2_VALID_MASK) #define SCG_APLLPFD_PFD2_CLKGATE_MASK (0x800000U) #define SCG_APLLPFD_PFD2_CLKGATE_SHIFT (23U) /*! PFD2_CLKGATE - PFD2_CLKGATE * 0b0..PFD2 clock is not gated. * 0b1..PFD2 clock is gated. */ #define SCG_APLLPFD_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPFD_PFD2_CLKGATE_SHIFT)) & SCG_APLLPFD_PFD2_CLKGATE_MASK) #define SCG_APLLPFD_PFD3_MASK (0x3F000000U) #define SCG_APLLPFD_PFD3_SHIFT (24U) /*! PFD3 - PLL Fractional Divider 3 */ #define SCG_APLLPFD_PFD3(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPFD_PFD3_SHIFT)) & SCG_APLLPFD_PFD3_MASK) #define SCG_APLLPFD_PFD3_VALID_MASK (0x40000000U) #define SCG_APLLPFD_PFD3_VALID_SHIFT (30U) /*! PFD3_VALID - PFD3_VALID */ #define SCG_APLLPFD_PFD3_VALID(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPFD_PFD3_VALID_SHIFT)) & SCG_APLLPFD_PFD3_VALID_MASK) #define SCG_APLLPFD_PFD3_CLKGATE_MASK (0x80000000U) #define SCG_APLLPFD_PFD3_CLKGATE_SHIFT (31U) /*! PFD3_CLKGATE - PFD3_CLKGATE * 0b0..PFD3 clock is not gated. * 0b1..PFD3 clock is gated. */ #define SCG_APLLPFD_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPFD_PFD3_CLKGATE_SHIFT)) & SCG_APLLPFD_PFD3_CLKGATE_MASK) /*! @} */ /*! @name APLLNUM - Auxiliary PLL Numerator Register */ /*! @{ */ #define SCG_APLLNUM_NUM_MASK (0x3FFFFFFFU) #define SCG_APLLNUM_NUM_SHIFT (0U) /*! NUM - 30-bit numerator of the Auxiliary PLL Fractional-Loop divider */ #define SCG_APLLNUM_NUM(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLNUM_NUM_SHIFT)) & SCG_APLLNUM_NUM_MASK) /*! @} */ /*! @name APLLDENOM - Auxiliary PLL Denominator Register */ /*! @{ */ #define SCG_APLLDENOM_DENOM_MASK (0x3FFFFFFFU) #define SCG_APLLDENOM_DENOM_SHIFT (0U) /*! DENOM - 30-bit denominator of the Auxiliary PLL Fractional-Loop divider */ #define SCG_APLLDENOM_DENOM(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLDENOM_DENOM_SHIFT)) & SCG_APLLDENOM_DENOM_MASK) /*! @} */ /*! @name APLLSS - Auxiliary PLL Spread Spectrum Register */ /*! @{ */ #define SCG_APLLSS_STEP_MASK (0x7FFFU) #define SCG_APLLSS_STEP_SHIFT (0U) /*! STEP - STOP and STEP together control the modulation depth (maximum frequency change) and * modulation frequency. Modulation Depth = (STOP/DENOM)*Fref where DENOM is the DENOM field value in * DENOM register. Modulation Frequency = (STEP/(2*STOP))*Fref, where Fref = 24Mhz. */ #define SCG_APLLSS_STEP(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSS_STEP_SHIFT)) & SCG_APLLSS_STEP_MASK) #define SCG_APLLSS_ENABLE_MASK (0x8000U) #define SCG_APLLSS_ENABLE_SHIFT (15U) /*! ENABLE - Enables the spread spectrum modulation. * 0b0..Spectrum modulation is disabled * 0b1..Spectrum modulation is enabled */ #define SCG_APLLSS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSS_ENABLE_SHIFT)) & SCG_APLLSS_ENABLE_MASK) #define SCG_APLLSS_STOP_MASK (0xFFFF0000U) #define SCG_APLLSS_STOP_SHIFT (16U) /*! STOP - STOP and STEP together control the modulation depth (maximum frequency change) and * modulation depth. Modulation Depth = (STOP/DENOM)*Fref where DENOM is the DENOM field value in DENOM * register. Modulation Frequency = (STEP/(2*STOP))*Fref, where Fref = 24Mhz. */ #define SCG_APLLSS_STOP(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSS_STOP_SHIFT)) & SCG_APLLSS_STOP_MASK) /*! @} */ /*! @name APLLLOCK_CNFG - Auxiliary PLL LOCK Configuration Register */ /*! @{ */ #define SCG_APLLLOCK_CNFG_LOCK_TIME_MASK (0xFFFFU) #define SCG_APLLLOCK_CNFG_LOCK_TIME_SHIFT (0U) /*! LOCK_TIME - Configures the number of reference clocks to count before APLL is considered locked and valid. */ #define SCG_APLLLOCK_CNFG_LOCK_TIME(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLLOCK_CNFG_LOCK_TIME_SHIFT)) & SCG_APLLLOCK_CNFG_LOCK_TIME_MASK) /*! @} */ /*! @name SPLLCSR - System PLL Control Status Register */ /*! @{ */ #define SCG_SPLLCSR_SPLLEN_MASK (0x1U) #define SCG_SPLLCSR_SPLLEN_SHIFT (0U) /*! SPLLEN - System PLL Enable * 0b0..System PLL is disabled * 0b1..System PLL is enabled */ #define SCG_SPLLCSR_SPLLEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLEN_SHIFT)) & SCG_SPLLCSR_SPLLEN_MASK) #define SCG_SPLLCSR_SPLLSTEN_MASK (0x2U) #define SCG_SPLLCSR_SPLLSTEN_SHIFT (1U) /*! SPLLSTEN - System PLL Stop Enable * 0b0..System PLL is disabled in Stop modes * 0b1..System PLL is enabled in Stop modes */ #define SCG_SPLLCSR_SPLLSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSTEN_SHIFT)) & SCG_SPLLCSR_SPLLSTEN_MASK) #define SCG_SPLLCSR_LK_MASK (0x800000U) #define SCG_SPLLCSR_LK_SHIFT (23U) /*! LK - Lock Register * 0b0..Control Status Register can be written. * 0b1..Control Status Register cannot be written. */ #define SCG_SPLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_LK_SHIFT)) & SCG_SPLLCSR_LK_MASK) #define SCG_SPLLCSR_SPLLVLD_MASK (0x1000000U) #define SCG_SPLLCSR_SPLLVLD_SHIFT (24U) /*! SPLLVLD - System PLL Valid * 0b0..System PLL is not enabled or clock is not valid * 0b1..System PLL is enabled and output clock is valid */ #define SCG_SPLLCSR_SPLLVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLVLD_SHIFT)) & SCG_SPLLCSR_SPLLVLD_MASK) #define SCG_SPLLCSR_SPLLSEL_MASK (0x2000000U) #define SCG_SPLLCSR_SPLLSEL_SHIFT (25U) /*! SPLLSEL - System PLL Selected * 0b0..System PLL is not the system clock source * 0b1..System PLL is the system clock source */ #define SCG_SPLLCSR_SPLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSEL_SHIFT)) & SCG_SPLLCSR_SPLLSEL_MASK) #define SCG_SPLLCSR_SPLLERR_MASK (0x4000000U) #define SCG_SPLLCSR_SPLLERR_SHIFT (26U) /*! SPLLERR - System PLL Clock Error * 0b0..System PLL Clock Monitor is disabled or has not detected an error * 0b1..System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set when * System OSC is selected as its source and SOSCERR has set. */ #define SCG_SPLLCSR_SPLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLERR_SHIFT)) & SCG_SPLLCSR_SPLLERR_MASK) /*! @} */ /*! @name SPLLDIV - System PLL Divide Register */ /*! @{ */ #define SCG_SPLLDIV_SPLLDIV1_MASK (0x7U) #define SCG_SPLLDIV_SPLLDIV1_SHIFT (0U) /*! SPLLDIV1 - System PLL Clock Divide 1 * 0b000..Clock disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_SPLLDIV_SPLLDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDIV1_SHIFT)) & SCG_SPLLDIV_SPLLDIV1_MASK) #define SCG_SPLLDIV_SPLLDIV2_MASK (0x700U) #define SCG_SPLLDIV_SPLLDIV2_SHIFT (8U) /*! SPLLDIV2 - System PLL Clock Divide 2 * 0b000..Clock disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_SPLLDIV_SPLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDIV2_SHIFT)) & SCG_SPLLDIV_SPLLDIV2_MASK) #define SCG_SPLLDIV_SPLLDIV3_MASK (0x70000U) #define SCG_SPLLDIV_SPLLDIV3_SHIFT (16U) /*! SPLLDIV3 - System PLL Clock Divide 3 * 0b000..Clock disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_SPLLDIV_SPLLDIV3(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDIV3_SHIFT)) & SCG_SPLLDIV_SPLLDIV3_MASK) /*! @} */ /*! @name SPLLCFG - System PLL Configuration Register */ /*! @{ */ #define SCG_SPLLCFG_SOURCE_MASK (0x1U) #define SCG_SPLLCFG_SOURCE_SHIFT (0U) /*! SOURCE - Clock Source * 0b0..System OSC (SOSC) * 0b1..Reserved */ #define SCG_SPLLCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCFG_SOURCE_SHIFT)) & SCG_SPLLCFG_SOURCE_MASK) #define SCG_SPLLCFG_PLLS_MASK (0x2U) #define SCG_SPLLCFG_PLLS_SHIFT (1U) /*! PLLS - PLL Select * 0b0..SPLL output clocks selected * 0b1..SPLL PFD output clock selected. */ #define SCG_SPLLCFG_PLLS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCFG_PLLS_SHIFT)) & SCG_SPLLCFG_PLLS_MASK) #define SCG_SPLLCFG_PREDIV_MASK (0x700U) #define SCG_SPLLCFG_PREDIV_SHIFT (8U) /*! PREDIV - PLL Reference Clock Divider */ #define SCG_SPLLCFG_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCFG_PREDIV_SHIFT)) & SCG_SPLLCFG_PREDIV_MASK) #define SCG_SPLLCFG_PFDSEL_MASK (0xC000U) #define SCG_SPLLCFG_PFDSEL_SHIFT (14U) /*! PFDSEL - PFD Clock Select * 0b00..PFD0 output clock selected. * 0b01..PFD1 output clock selected. * 0b10..PFD2 output clock selected. * 0b11..PFD3 output clock selected. */ #define SCG_SPLLCFG_PFDSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCFG_PFDSEL_SHIFT)) & SCG_SPLLCFG_PFDSEL_MASK) #define SCG_SPLLCFG_MULT_MASK (0x7F0000U) /* Merged from fields with different position or width, of widths (3, 7), largest definition used */ #define SCG_SPLLCFG_MULT_SHIFT (16U) /*! MULT - System PLL Multiplier */ #define SCG_SPLLCFG_MULT(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCFG_MULT_SHIFT)) & SCG_SPLLCFG_MULT_MASK) /* Merged from fields with different position or width, of widths (3, 7), largest definition used */ /*! @} */ /*! @name SPLLPFD - System PLL PFD Register */ /*! @{ */ #define SCG_SPLLPFD_PFD0_MASK (0x3FU) #define SCG_SPLLPFD_PFD0_SHIFT (0U) /*! PFD0 - PLL Fractional Divider 0 */ #define SCG_SPLLPFD_PFD0(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPFD_PFD0_SHIFT)) & SCG_SPLLPFD_PFD0_MASK) #define SCG_SPLLPFD_PFD0_VALID_MASK (0x40U) #define SCG_SPLLPFD_PFD0_VALID_SHIFT (6U) /*! PFD0_VALID - PFD0_VALID */ #define SCG_SPLLPFD_PFD0_VALID(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPFD_PFD0_VALID_SHIFT)) & SCG_SPLLPFD_PFD0_VALID_MASK) #define SCG_SPLLPFD_PFD0_CLKGATE_MASK (0x80U) #define SCG_SPLLPFD_PFD0_CLKGATE_SHIFT (7U) /*! PFD0_CLKGATE - PFD0_CLKGATE * 0b0..PFD0 clock is not gated. * 0b1..PFD0 clock is gated. */ #define SCG_SPLLPFD_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPFD_PFD0_CLKGATE_SHIFT)) & SCG_SPLLPFD_PFD0_CLKGATE_MASK) #define SCG_SPLLPFD_PFD1_MASK (0x3F00U) #define SCG_SPLLPFD_PFD1_SHIFT (8U) /*! PFD1 - PLL Fractional Divider 5 */ #define SCG_SPLLPFD_PFD1(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPFD_PFD1_SHIFT)) & SCG_SPLLPFD_PFD1_MASK) #define SCG_SPLLPFD_PFD1_VALID_MASK (0x4000U) #define SCG_SPLLPFD_PFD1_VALID_SHIFT (14U) /*! PFD1_VALID - PFD1_VALID */ #define SCG_SPLLPFD_PFD1_VALID(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPFD_PFD1_VALID_SHIFT)) & SCG_SPLLPFD_PFD1_VALID_MASK) #define SCG_SPLLPFD_PFD1_CLKGATE_MASK (0x8000U) #define SCG_SPLLPFD_PFD1_CLKGATE_SHIFT (15U) /*! PFD1_CLKGATE - PFD1_CLKGATE * 0b0..PFD1 clock is not gated. * 0b1..PFD1 clock is gated. */ #define SCG_SPLLPFD_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPFD_PFD1_CLKGATE_SHIFT)) & SCG_SPLLPFD_PFD1_CLKGATE_MASK) #define SCG_SPLLPFD_PFD2_MASK (0x3F0000U) #define SCG_SPLLPFD_PFD2_SHIFT (16U) /*! PFD2 - PLL Fractional Divider 2 */ #define SCG_SPLLPFD_PFD2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPFD_PFD2_SHIFT)) & SCG_SPLLPFD_PFD2_MASK) #define SCG_SPLLPFD_PFD2_VALID_MASK (0x400000U) #define SCG_SPLLPFD_PFD2_VALID_SHIFT (22U) /*! PFD2_VALID - PFD2_VALID */ #define SCG_SPLLPFD_PFD2_VALID(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPFD_PFD2_VALID_SHIFT)) & SCG_SPLLPFD_PFD2_VALID_MASK) #define SCG_SPLLPFD_PFD2_CLKGATE_MASK (0x800000U) #define SCG_SPLLPFD_PFD2_CLKGATE_SHIFT (23U) /*! PFD2_CLKGATE - PFD2_CLKGATE * 0b0..PFD2 clock is not gated. * 0b1..PFD2 clock is gated. */ #define SCG_SPLLPFD_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPFD_PFD2_CLKGATE_SHIFT)) & SCG_SPLLPFD_PFD2_CLKGATE_MASK) #define SCG_SPLLPFD_PFD3_MASK (0x3F000000U) #define SCG_SPLLPFD_PFD3_SHIFT (24U) /*! PFD3 - PLL Fractional Divider 3 */ #define SCG_SPLLPFD_PFD3(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPFD_PFD3_SHIFT)) & SCG_SPLLPFD_PFD3_MASK) #define SCG_SPLLPFD_PFD3_VALID_MASK (0x40000000U) #define SCG_SPLLPFD_PFD3_VALID_SHIFT (30U) /*! PFD3_VALID - PFD3_VALID */ #define SCG_SPLLPFD_PFD3_VALID(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPFD_PFD3_VALID_SHIFT)) & SCG_SPLLPFD_PFD3_VALID_MASK) #define SCG_SPLLPFD_PFD3_CLKGATE_MASK (0x80000000U) #define SCG_SPLLPFD_PFD3_CLKGATE_SHIFT (31U) /*! PFD3_CLKGATE - PFD3_CLKGATE * 0b0..PFD3 clock is not gated. * 0b1..PFD3 clock is gated. */ #define SCG_SPLLPFD_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPFD_PFD3_CLKGATE_SHIFT)) & SCG_SPLLPFD_PFD3_CLKGATE_MASK) /*! @} */ /*! @name SPLLNUM - System PLL Numerator Register */ /*! @{ */ #define SCG_SPLLNUM_NUM_MASK (0x3FFFFFFFU) #define SCG_SPLLNUM_NUM_SHIFT (0U) /*! NUM - 30-bit numerator of the System PLL Fractional-Loop divider */ #define SCG_SPLLNUM_NUM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLNUM_NUM_SHIFT)) & SCG_SPLLNUM_NUM_MASK) /*! @} */ /*! @name SPLLDENOM - System PLL Denominator Register */ /*! @{ */ #define SCG_SPLLDENOM_DENOM_MASK (0x3FFFFFFFU) #define SCG_SPLLDENOM_DENOM_SHIFT (0U) /*! DENOM - 30-bit denominator of the System PLL Fractional-Loop divider */ #define SCG_SPLLDENOM_DENOM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDENOM_DENOM_SHIFT)) & SCG_SPLLDENOM_DENOM_MASK) /*! @} */ /*! @name SPLLSS - System PLL Spread Spectrum Register */ /*! @{ */ #define SCG_SPLLSS_STEP_MASK (0x7FFFU) #define SCG_SPLLSS_STEP_SHIFT (0U) /*! STEP - STOP and STEP together control the modulation depth (maximum frequency change) and * Modulation Depth. Modulation Depth = (STOP/DENOM)*Fref where DENOM is the DENOM field value in DENOM * register. Modulation Frequency = (STEP/(2*STOP))*Fref, where Fref = 24Mhz. */ #define SCG_SPLLSS_STEP(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSS_STEP_SHIFT)) & SCG_SPLLSS_STEP_MASK) #define SCG_SPLLSS_ENABLE_MASK (0x8000U) #define SCG_SPLLSS_ENABLE_SHIFT (15U) /*! ENABLE - Spread Spectrum Modulation Enable * 0b0..Spectrum modulation is disabled * 0b1..Spectrum modulation is enabled */ #define SCG_SPLLSS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSS_ENABLE_SHIFT)) & SCG_SPLLSS_ENABLE_MASK) #define SCG_SPLLSS_STOP_MASK (0xFFFF0000U) #define SCG_SPLLSS_STOP_SHIFT (16U) /*! STOP - STOP and STEP together control the modulation depth (maximum frequency change) and * Modulation Depth. Modulation Depth = (STOP/DENOM)*Fref where DENOM is the DENOM field value in DENOM * register. Modulation Frequency = (STEP/(2*STOP))*Fref, where Fref = 24Mhz. */ #define SCG_SPLLSS_STOP(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSS_STOP_SHIFT)) & SCG_SPLLSS_STOP_MASK) /*! @} */ /*! @name SPLLLOCK_CNFG - System PLL LOCK Configuration Register */ /*! @{ */ #define SCG_SPLLLOCK_CNFG_LOCK_TIME_MASK (0xFFFFU) #define SCG_SPLLLOCK_CNFG_LOCK_TIME_SHIFT (0U) /*! LOCK_TIME - Configures the number of reference clocks to count before SPLL is considered locked and valid. */ #define SCG_SPLLLOCK_CNFG_LOCK_TIME(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLLOCK_CNFG_LOCK_TIME_SHIFT)) & SCG_SPLLLOCK_CNFG_LOCK_TIME_MASK) /*! @} */ /*! * @} */ /* end of group SCG_Register_Masks */ /* SCG - Peripheral instance base addresses */ /** Peripheral SCG0 base address */ #define SCG0_BASE (0x41027000u) /** Peripheral SCG0 base pointer */ #define SCG0 ((SCG_Type *)SCG0_BASE) /** Peripheral SCG1 base address */ #define SCG1_BASE (0x403E0000u) /** Peripheral SCG1 base pointer */ #define SCG1 ((SCG_Type *)SCG1_BASE) /** Array initializer of SCG peripheral base addresses */ #define SCG_BASE_ADDRS { SCG0_BASE, SCG1_BASE } /** Array initializer of SCG peripheral base pointers */ #define SCG_BASE_PTRS { SCG0, SCG1 } /** Interrupt vectors for the SCG peripheral type */ #define SCG_IRQS { SCG0_IRQn, NotAvail_IRQn } /*! * @} */ /* end of group SCG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SEMA42 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer * @{ */ /** SEMA42 - Register Layout Typedef */ typedef struct { __IO uint8_t GATE3; /**< Gate Register, offset: 0x0 */ __IO uint8_t GATE2; /**< Gate Register, offset: 0x1 */ __IO uint8_t GATE1; /**< Gate Register, offset: 0x2 */ __IO uint8_t GATE0; /**< Gate Register, offset: 0x3 */ __IO uint8_t GATE7; /**< Gate Register, offset: 0x4 */ __IO uint8_t GATE6; /**< Gate Register, offset: 0x5 */ __IO uint8_t GATE5; /**< Gate Register, offset: 0x6 */ __IO uint8_t GATE4; /**< Gate Register, offset: 0x7 */ __IO uint8_t GATE11; /**< Gate Register, offset: 0x8 */ __IO uint8_t GATE10; /**< Gate Register, offset: 0x9 */ __IO uint8_t GATE9; /**< Gate Register, offset: 0xA */ __IO uint8_t GATE8; /**< Gate Register, offset: 0xB */ __IO uint8_t GATE15; /**< Gate Register, offset: 0xC */ __IO uint8_t GATE14; /**< Gate Register, offset: 0xD */ __IO uint8_t GATE13; /**< Gate Register, offset: 0xE */ __IO uint8_t GATE12; /**< Gate Register, offset: 0xF */ uint8_t RESERVED_0[50]; union { /* offset: 0x42 */ __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ }; } SEMA42_Type; /* ---------------------------------------------------------------------------- -- SEMA42 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks * @{ */ /*! @name GATE3 - Gate Register */ /*! @{ */ #define SEMA42_GATE3_GTFSM_MASK (0xFU) #define SEMA42_GATE3_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE3_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK) /*! @} */ /*! @name GATE2 - Gate Register */ /*! @{ */ #define SEMA42_GATE2_GTFSM_MASK (0xFU) #define SEMA42_GATE2_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE2_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK) /*! @} */ /*! @name GATE1 - Gate Register */ /*! @{ */ #define SEMA42_GATE1_GTFSM_MASK (0xFU) #define SEMA42_GATE1_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE1_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK) /*! @} */ /*! @name GATE0 - Gate Register */ /*! @{ */ #define SEMA42_GATE0_GTFSM_MASK (0xFU) #define SEMA42_GATE0_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE0_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK) /*! @} */ /*! @name GATE7 - Gate Register */ /*! @{ */ #define SEMA42_GATE7_GTFSM_MASK (0xFU) #define SEMA42_GATE7_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE7_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK) /*! @} */ /*! @name GATE6 - Gate Register */ /*! @{ */ #define SEMA42_GATE6_GTFSM_MASK (0xFU) #define SEMA42_GATE6_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE6_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK) /*! @} */ /*! @name GATE5 - Gate Register */ /*! @{ */ #define SEMA42_GATE5_GTFSM_MASK (0xFU) #define SEMA42_GATE5_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE5_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK) /*! @} */ /*! @name GATE4 - Gate Register */ /*! @{ */ #define SEMA42_GATE4_GTFSM_MASK (0xFU) #define SEMA42_GATE4_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE4_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK) /*! @} */ /*! @name GATE11 - Gate Register */ /*! @{ */ #define SEMA42_GATE11_GTFSM_MASK (0xFU) #define SEMA42_GATE11_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK) /*! @} */ /*! @name GATE10 - Gate Register */ /*! @{ */ #define SEMA42_GATE10_GTFSM_MASK (0xFU) #define SEMA42_GATE10_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK) /*! @} */ /*! @name GATE9 - Gate Register */ /*! @{ */ #define SEMA42_GATE9_GTFSM_MASK (0xFU) #define SEMA42_GATE9_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE9_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK) /*! @} */ /*! @name GATE8 - Gate Register */ /*! @{ */ #define SEMA42_GATE8_GTFSM_MASK (0xFU) #define SEMA42_GATE8_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE8_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK) /*! @} */ /*! @name GATE15 - Gate Register */ /*! @{ */ #define SEMA42_GATE15_GTFSM_MASK (0xFU) #define SEMA42_GATE15_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK) /*! @} */ /*! @name GATE14 - Gate Register */ /*! @{ */ #define SEMA42_GATE14_GTFSM_MASK (0xFU) #define SEMA42_GATE14_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK) /*! @} */ /*! @name GATE13 - Gate Register */ /*! @{ */ #define SEMA42_GATE13_GTFSM_MASK (0xFU) #define SEMA42_GATE13_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK) /*! @} */ /*! @name GATE12 - Gate Register */ /*! @{ */ #define SEMA42_GATE12_GTFSM_MASK (0xFU) #define SEMA42_GATE12_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK) /*! @} */ /*! @name RSTGT_R - Reset Gate Read */ /*! @{ */ #define SEMA42_RSTGT_R_RSTGTN_MASK (0xFFU) #define SEMA42_RSTGT_R_RSTGTN_SHIFT (0U) /*! RSTGTN - Reset gate number */ #define SEMA42_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK) #define SEMA42_RSTGT_R_RSTGMS_MASK (0xF00U) #define SEMA42_RSTGT_R_RSTGMS_SHIFT (8U) /*! RSTGMS - Reset gate domain */ #define SEMA42_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK) #define SEMA42_RSTGT_R_RSTGSM_MASK (0x3000U) #define SEMA42_RSTGT_R_RSTGSM_SHIFT (12U) /*! RSTGSM - Reset gate finite state machine * 0b00..Idle, waiting for the first data pattern write. * 0b01..Waiting for the second data pattern write * 0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, * this machine returns to the idle (waiting for first data pattern write) state. * 0b11..This state encoding is never used and therefore reserved. */ #define SEMA42_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK) #define SEMA42_RSTGT_R_ROZ_MASK (0xC000U) #define SEMA42_RSTGT_R_ROZ_SHIFT (14U) /*! ROZ - ROZ */ #define SEMA42_RSTGT_R_ROZ(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_ROZ_SHIFT)) & SEMA42_RSTGT_R_ROZ_MASK) /*! @} */ /*! @name RSTGT_W - Reset Gate Write */ /*! @{ */ #define SEMA42_RSTGT_W_RSTGTN_MASK (0xFFU) #define SEMA42_RSTGT_W_RSTGTN_SHIFT (0U) /*! RSTGTN - Reset gate number */ #define SEMA42_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK) #define SEMA42_RSTGT_W_RSTGDP_MASK (0xFF00U) #define SEMA42_RSTGT_W_RSTGDP_SHIFT (8U) /*! RSTGDP - Reset gate data pattern */ #define SEMA42_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK) /*! @} */ /*! * @} */ /* end of group SEMA42_Register_Masks */ /* SEMA42 - Peripheral instance base addresses */ /** Peripheral SEMA42_0 base address */ #define SEMA42_0_BASE (0x4101B000u) /** Peripheral SEMA42_0 base pointer */ #define SEMA42_0 ((SEMA42_Type *)SEMA42_0_BASE) /** Peripheral SEMA42_1 base address */ #define SEMA42_1_BASE (0x401B0000u) /** Peripheral SEMA42_1 base pointer */ #define SEMA42_1 ((SEMA42_Type *)SEMA42_1_BASE) /** Array initializer of SEMA42 peripheral base addresses */ #define SEMA42_BASE_ADDRS { SEMA42_0_BASE, SEMA42_1_BASE } /** Array initializer of SEMA42 peripheral base pointers */ #define SEMA42_BASE_PTRS { SEMA42_0, SEMA42_1 } /*! * @} */ /* end of group SEMA42_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SIM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer * @{ */ /** SIM - Register Layout Typedef */ typedef struct { __IO uint32_t SOPT1; /**< SIM Systems Options Register 1, offset: 0x0 */ __IO uint32_t SOPT1CFG; /**< SIM SOPT1 Configuration Register, offset: 0x4 */ uint8_t RESERVED_0[4]; __IO uint32_t HSIC_CAL; /**< HW SIM HSIC CAL Register, offset: 0xC */ uint8_t RESERVED_1[24]; __IO uint32_t SNVS_MISC_CTRL; /**< SNVS Misc Control Register, offset: 0x28 */ __IO uint32_t GPR0; /**< HW SIM General Purpose Register 0, offset: 0x2C */ __IO uint32_t GPR1; /**< HW SIM General Purpose Register 1, offset: 0x30 */ uint32_t GPR2; /**< HW SIM General Purpose Register 2, offset: 0x34 */ uint32_t GPR3; /**< HW SIM General Purpose Register 3, offset: 0x38 */ __IO uint32_t MISC_CTRL0; /**< HW SIM MISC Register 0, offset: 0x3C */ uint8_t RESERVED_2[16]; __IO uint32_t SIM_DGO_CTRL0; /**< SIM DGO Control Register 0, offset: 0x50 */ __IO uint32_t SIM_DGO_CTRL1; /**< SIM DGO Control Register 1, offset: 0x54 */ __IO uint32_t SIM_DGO_GP1; /**< SIM DGO General Purpose Register 1, offset: 0x58 */ __IO uint32_t SIM_DGO_GP2; /**< SIM DGO general Purpose Register 2, offset: 0x5C */ __IO uint32_t SIM_DGO_GP3; /**< SIM DGO General Purpose Register 3, offset: 0x60 */ __IO uint32_t SIM_DGO_GP4; /**< SIM DGO General Purpose Register 4, offset: 0x64 */ __IO uint32_t SIM_DGO_GP5; /**< SIM DGO General Purpose Register 5, offset: 0x68 */ __IO uint32_t SIM_DGO_GP6; /**< SIM DGO General Purpose Register 6, offset: 0x6C */ __IO uint32_t SIM_DGO_GP7; /**< SIM DGO General Purpose Register 7, offset: 0x70 */ __IO uint32_t SIM_DGO_GP8; /**< SIM DGO General Purpose Register 8, offset: 0x74 */ __IO uint32_t SIM_DGO_GP9; /**< SIM DGO General Purpose Register 9, offset: 0x78 */ __IO uint32_t SIM_DGO_GP10; /**< SIM DGO General Purpose Register 10, offset: 0x7C */ __IO uint32_t SIM_DGO_GP11; /**< SIM DGO General Purpose Register 11, offset: 0x80 */ uint8_t RESERVED_3[4]; __IO uint32_t WKPU_WAKEUP_EN; /**< WKPU Wake-up Enable, offset: 0x88 */ __I uint32_t JTAG_ID_REG; /**< Mirror of JTAG ID Register, offset: 0x8C */ __IO uint32_t A7_TSTMR_CMP_VAL_L; /**< Lower A7 TS Timer compare value, offset: 0x90 */ __IO uint32_t A7_TSTMR_CMP_VAL_H; /**< Upper A7 TS Timer compare value, offset: 0x94 */ __IO uint32_t COMP_CELL_OVERRIDE; /**< Override Control for Compensation Codes, offset: 0x98 */ } SIM_Type; /* ---------------------------------------------------------------------------- -- SIM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SIM_Register_Masks SIM Register Masks * @{ */ /*! @name SOPT1 - SIM Systems Options Register 1 */ /*! @{ */ #define SIM_SOPT1_A7_SW_RESET_MASK (0x1U) #define SIM_SOPT1_A7_SW_RESET_SHIFT (0U) /*! A7_SW_RESET - SW reset for A7 domain. */ #define SIM_SOPT1_A7_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_A7_SW_RESET_SHIFT)) & SIM_SOPT1_A7_SW_RESET_MASK) #define SIM_SOPT1_PMIC_STBY_REQ_MASK (0x4U) #define SIM_SOPT1_PMIC_STBY_REQ_SHIFT (2U) /*! PMIC_STBY_REQ - PMIC Standby Request. */ #define SIM_SOPT1_PMIC_STBY_REQ(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_PMIC_STBY_REQ_SHIFT)) & SIM_SOPT1_PMIC_STBY_REQ_MASK) #define SIM_SOPT1_MIPI_ISO_DISABLE_MASK (0x8U) #define SIM_SOPT1_MIPI_ISO_DISABLE_SHIFT (3U) /*! MIPI_ISO_DISABLE - MIPI Isolation Disable. */ #define SIM_SOPT1_MIPI_ISO_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_MIPI_ISO_DISABLE_SHIFT)) & SIM_SOPT1_MIPI_ISO_DISABLE_MASK) #define SIM_SOPT1_M4_FPU_DISABLE_MASK (0x20U) #define SIM_SOPT1_M4_FPU_DISABLE_SHIFT (5U) /*! M4_FPU_DISABLE - Disables M4 FPU unit. */ #define SIM_SOPT1_M4_FPU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_M4_FPU_DISABLE_SHIFT)) & SIM_SOPT1_M4_FPU_DISABLE_MASK) #define SIM_SOPT1_M4_MPU_DISABLE_MASK (0x40U) #define SIM_SOPT1_M4_MPU_DISABLE_SHIFT (6U) /*! M4_MPU_DISABLE - Disables M4 MPU unit. */ #define SIM_SOPT1_M4_MPU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_M4_MPU_DISABLE_SHIFT)) & SIM_SOPT1_M4_MPU_DISABLE_MASK) #define SIM_SOPT1_EN_SNVS_HARD_RST_MASK (0x100U) #define SIM_SOPT1_EN_SNVS_HARD_RST_SHIFT (8U) /*! EN_SNVS_HARD_RST - SNVS_HP system reset enable (Write Once). */ #define SIM_SOPT1_EN_SNVS_HARD_RST(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_EN_SNVS_HARD_RST_SHIFT)) & SIM_SOPT1_EN_SNVS_HARD_RST_MASK) #define SIM_SOPT1_EN_WDG2_HARD_RST_MASK (0x200U) #define SIM_SOPT1_EN_WDG2_HARD_RST_SHIFT (9U) /*! EN_WDG2_HARD_RST - Watchdog 2 Reset Enable. */ #define SIM_SOPT1_EN_WDG2_HARD_RST(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_EN_WDG2_HARD_RST_SHIFT)) & SIM_SOPT1_EN_WDG2_HARD_RST_MASK) /*! @} */ /*! @name SOPT1CFG - SIM SOPT1 Configuration Register */ /*! @{ */ #define SIM_SOPT1CFG_MASK_DPM_PANIC_OUT_MASK (0x1U) #define SIM_SOPT1CFG_MASK_DPM_PANIC_OUT_SHIFT (0U) /*! MASK_DPM_PANIC_OUT - DPM Panic Out Mask (Write Once). */ #define SIM_SOPT1CFG_MASK_DPM_PANIC_OUT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_MASK_DPM_PANIC_OUT_SHIFT)) & SIM_SOPT1CFG_MASK_DPM_PANIC_OUT_MASK) #define SIM_SOPT1CFG_MASK_DPM_PANIC_IN_MASK (0x2U) #define SIM_SOPT1CFG_MASK_DPM_PANIC_IN_SHIFT (1U) /*! MASK_DPM_PANIC_IN - DPM Panic In Mask (Write Once). */ #define SIM_SOPT1CFG_MASK_DPM_PANIC_IN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_MASK_DPM_PANIC_IN_SHIFT)) & SIM_SOPT1CFG_MASK_DPM_PANIC_IN_MASK) #define SIM_SOPT1CFG_DSI_PLL_EN_MASK (0x80U) #define SIM_SOPT1CFG_DSI_PLL_EN_SHIFT (7U) /*! DSI_PLL_EN - DSI PLL Enable. */ #define SIM_SOPT1CFG_DSI_PLL_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_DSI_PLL_EN_SHIFT)) & SIM_SOPT1CFG_DSI_PLL_EN_MASK) #define SIM_SOPT1CFG_DSI_CM_MASK (0x100U) #define SIM_SOPT1CFG_DSI_CM_SHIFT (8U) /*! DSI_CM - DSI Color Mode Control. */ #define SIM_SOPT1CFG_DSI_CM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_DSI_CM_SHIFT)) & SIM_SOPT1CFG_DSI_CM_MASK) #define SIM_SOPT1CFG_DSI_SD_MASK (0x200U) #define SIM_SOPT1CFG_DSI_SD_SHIFT (9U) /*! DSI_SD - DSI Shutdown Control. */ #define SIM_SOPT1CFG_DSI_SD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_DSI_SD_SHIFT)) & SIM_SOPT1CFG_DSI_SD_MASK) #define SIM_SOPT1CFG_QSPI_PULL_TIM_RELAX_B_MASK (0x400U) #define SIM_SOPT1CFG_QSPI_PULL_TIM_RELAX_B_SHIFT (10U) /*! QSPI_PULL_TIM_RELAX_b - QSPI OBE Assertion Control. */ #define SIM_SOPT1CFG_QSPI_PULL_TIM_RELAX_B(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_QSPI_PULL_TIM_RELAX_B_SHIFT)) & SIM_SOPT1CFG_QSPI_PULL_TIM_RELAX_B_MASK) #define SIM_SOPT1CFG_DSI_RST_BYTE_N_MASK (0x20000000U) #define SIM_SOPT1CFG_DSI_RST_BYTE_N_SHIFT (29U) /*! DSI_RST_BYTE_N - DSI Reset Byte Control. */ #define SIM_SOPT1CFG_DSI_RST_BYTE_N(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_DSI_RST_BYTE_N_SHIFT)) & SIM_SOPT1CFG_DSI_RST_BYTE_N_MASK) #define SIM_SOPT1CFG_DSI_RST_ESC_N_MASK (0x40000000U) #define SIM_SOPT1CFG_DSI_RST_ESC_N_SHIFT (30U) /*! DSI_RST_ESC_N - DSI Reset Escape Control. */ #define SIM_SOPT1CFG_DSI_RST_ESC_N(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_DSI_RST_ESC_N_SHIFT)) & SIM_SOPT1CFG_DSI_RST_ESC_N_MASK) #define SIM_SOPT1CFG_DSI_RST_DPI_N_MASK (0x80000000U) #define SIM_SOPT1CFG_DSI_RST_DPI_N_SHIFT (31U) /*! DSI_RST_DPI_N - DSI Reset DPI Control. */ #define SIM_SOPT1CFG_DSI_RST_DPI_N(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_DSI_RST_DPI_N_SHIFT)) & SIM_SOPT1CFG_DSI_RST_DPI_N_MASK) /*! @} */ /*! @name HSIC_CAL - HW SIM HSIC CAL Register */ /*! @{ */ #define SIM_HSIC_CAL_HSIC_ZQ_VOH_MASK (0x1FU) #define SIM_HSIC_CAL_HSIC_ZQ_VOH_SHIFT (0U) /*! HSIC_ZQ_VOH - HSIC ZQ pull-up resistance. */ #define SIM_HSIC_CAL_HSIC_ZQ_VOH(x) (((uint32_t)(((uint32_t)(x)) << SIM_HSIC_CAL_HSIC_ZQ_VOH_SHIFT)) & SIM_HSIC_CAL_HSIC_ZQ_VOH_MASK) #define SIM_HSIC_CAL_HSIC_ZQ_COMPARE_MASK (0x20U) #define SIM_HSIC_CAL_HSIC_ZQ_COMPARE_SHIFT (5U) /*! HSIC_ZQ_COMPARE - HSIC ZQ Compare. */ #define SIM_HSIC_CAL_HSIC_ZQ_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << SIM_HSIC_CAL_HSIC_ZQ_COMPARE_SHIFT)) & SIM_HSIC_CAL_HSIC_ZQ_COMPARE_MASK) #define SIM_HSIC_CAL_HSIC_ZQ_CAL_EN_MASK (0x80U) #define SIM_HSIC_CAL_HSIC_ZQ_CAL_EN_SHIFT (7U) /*! HSIC_ZQ_CAL_EN - HSIC ZQ compare enable. */ #define SIM_HSIC_CAL_HSIC_ZQ_CAL_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_HSIC_CAL_HSIC_ZQ_CAL_EN_SHIFT)) & SIM_HSIC_CAL_HSIC_ZQ_CAL_EN_MASK) #define SIM_HSIC_CAL_HSIC_ZQ_VOH_M1_MASK (0x1F00U) #define SIM_HSIC_CAL_HSIC_ZQ_VOH_M1_SHIFT (8U) /*! HSIC_ZQ_VOH_M1 - HSIC ZQ pull-up resistance incremented. */ #define SIM_HSIC_CAL_HSIC_ZQ_VOH_M1(x) (((uint32_t)(((uint32_t)(x)) << SIM_HSIC_CAL_HSIC_ZQ_VOH_M1_SHIFT)) & SIM_HSIC_CAL_HSIC_ZQ_VOH_M1_MASK) #define SIM_HSIC_CAL_HSIC_ZQ_VOL_MASK (0x1F0000U) #define SIM_HSIC_CAL_HSIC_ZQ_VOL_SHIFT (16U) /*! HSIC_ZQ_VOL - HSIC ZQ pull-down resistance. */ #define SIM_HSIC_CAL_HSIC_ZQ_VOL(x) (((uint32_t)(((uint32_t)(x)) << SIM_HSIC_CAL_HSIC_ZQ_VOL_SHIFT)) & SIM_HSIC_CAL_HSIC_ZQ_VOL_MASK) #define SIM_HSIC_CAL_HSIC_ZQ_VOL_M1_MASK (0x1F000000U) #define SIM_HSIC_CAL_HSIC_ZQ_VOL_M1_SHIFT (24U) /*! HSIC_ZQ_VOL_M1 - HSIC ZQ pull-down resistance incremented. */ #define SIM_HSIC_CAL_HSIC_ZQ_VOL_M1(x) (((uint32_t)(((uint32_t)(x)) << SIM_HSIC_CAL_HSIC_ZQ_VOL_M1_SHIFT)) & SIM_HSIC_CAL_HSIC_ZQ_VOL_M1_MASK) /*! @} */ /*! @name SNVS_MISC_CTRL - SNVS Misc Control Register */ /*! @{ */ #define SIM_SNVS_MISC_CTRL_OSC_CAP_TRIM_MASK (0xFU) #define SIM_SNVS_MISC_CTRL_OSC_CAP_TRIM_SHIFT (0U) /*! OSC_CAP_TRIM - Trims to control the CAP on 32K Oscillator. */ #define SIM_SNVS_MISC_CTRL_OSC_CAP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SNVS_MISC_CTRL_OSC_CAP_TRIM_SHIFT)) & SIM_SNVS_MISC_CTRL_OSC_CAP_TRIM_MASK) #define SIM_SNVS_MISC_CTRL_COIN_CELL_CHARGE_EN_MASK (0x80000000U) #define SIM_SNVS_MISC_CTRL_COIN_CELL_CHARGE_EN_SHIFT (31U) /*! COIN_CELL_CHARGE_EN - Enables Signal Isolation on SNVS Software Trims and Pull controls * (PUS/PUE) until the software writes "1" to this register field. This ensures trim values are held * until registers get updated by software after boot up. */ #define SIM_SNVS_MISC_CTRL_COIN_CELL_CHARGE_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SNVS_MISC_CTRL_COIN_CELL_CHARGE_EN_SHIFT)) & SIM_SNVS_MISC_CTRL_COIN_CELL_CHARGE_EN_MASK) /*! @} */ /*! @name GPR0 - HW SIM General Purpose Register 0 */ /*! @{ */ #define SIM_GPR0_MTR_CLK_DIS_MASK (0x1U) #define SIM_GPR0_MTR_CLK_DIS_SHIFT (0U) /*! MTR_CLK_DIS - MBIST clocks disable. */ #define SIM_GPR0_MTR_CLK_DIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_GPR0_MTR_CLK_DIS_SHIFT)) & SIM_GPR0_MTR_CLK_DIS_MASK) #define SIM_GPR0_OCOTP_CLK_DIS_MASK (0x2U) #define SIM_GPR0_OCOTP_CLK_DIS_SHIFT (1U) /*! OCOTP_CLK_DIS - OCOTP clocks disable. */ #define SIM_GPR0_OCOTP_CLK_DIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_GPR0_OCOTP_CLK_DIS_SHIFT)) & SIM_GPR0_OCOTP_CLK_DIS_MASK) /*! @} */ /*! @name GPR1 - HW SIM General Purpose Register 1 */ /*! @{ */ #define SIM_GPR1_USB_PHY_WAKEUP_ISO_DISABLE_MASK (0x1U) #define SIM_GPR1_USB_PHY_WAKEUP_ISO_DISABLE_SHIFT (0U) /*! USB_PHY_WAKEUP_ISO_DISABLE - USB PHY wakeup ISO disable. */ #define SIM_GPR1_USB_PHY_WAKEUP_ISO_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SIM_GPR1_USB_PHY_WAKEUP_ISO_DISABLE_SHIFT)) & SIM_GPR1_USB_PHY_WAKEUP_ISO_DISABLE_MASK) #define SIM_GPR1_USB_PHY_NON_VLLS_WAKEUP_EN_MASK (0x2U) #define SIM_GPR1_USB_PHY_NON_VLLS_WAKEUP_EN_SHIFT (1U) /*! USB_PHY_NON_VLLS_WAKEUP_EN - USB PHY non VLLS wakeup enable. */ #define SIM_GPR1_USB_PHY_NON_VLLS_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_GPR1_USB_PHY_NON_VLLS_WAKEUP_EN_SHIFT)) & SIM_GPR1_USB_PHY_NON_VLLS_WAKEUP_EN_MASK) /*! @} */ /*! @name MISC_CTRL0 - HW SIM MISC Register 0 */ /*! @{ */ #define SIM_MISC_CTRL0_FB_DELAY_OE_EXTS_MASK (0x1U) #define SIM_MISC_CTRL0_FB_DELAY_OE_EXTS_SHIFT (0U) /*! FB_DELAY_OE_EXTS - Flexbus control of FB_OE_b signal delay when CSCR[EXTS] is enabled. */ #define SIM_MISC_CTRL0_FB_DELAY_OE_EXTS(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTRL0_FB_DELAY_OE_EXTS_SHIFT)) & SIM_MISC_CTRL0_FB_DELAY_OE_EXTS_MASK) #define SIM_MISC_CTRL0_OBS_CLK_ENABLE_MASK (0x10U) #define SIM_MISC_CTRL0_OBS_CLK_ENABLE_SHIFT (4U) /*! OBS_CLK_ENABLE - Enable that clocks can be observed at M4 CLKOUT, A7 CLKOUT and LVDS clock pads. */ #define SIM_MISC_CTRL0_OBS_CLK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTRL0_OBS_CLK_ENABLE_SHIFT)) & SIM_MISC_CTRL0_OBS_CLK_ENABLE_MASK) #define SIM_MISC_CTRL0_M4_OBS_CLK_SRC_SEL_MASK (0x3C0U) #define SIM_MISC_CTRL0_M4_OBS_CLK_SRC_SEL_SHIFT (6U) /*! M4_OBS_CLK_SRC_SEL - Selects the clock to be observed on M4 domain. */ #define SIM_MISC_CTRL0_M4_OBS_CLK_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTRL0_M4_OBS_CLK_SRC_SEL_SHIFT)) & SIM_MISC_CTRL0_M4_OBS_CLK_SRC_SEL_MASK) #define SIM_MISC_CTRL0_M4_OBS_CLK_DIV_RATIO_MASK (0x1C00U) #define SIM_MISC_CTRL0_M4_OBS_CLK_DIV_RATIO_SHIFT (10U) /*! M4_OBS_CLK_DIV_RATIO - Selection of division rate (2**n) of M4 observation clock div rate = 2**n (n=0..7). */ #define SIM_MISC_CTRL0_M4_OBS_CLK_DIV_RATIO(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTRL0_M4_OBS_CLK_DIV_RATIO_SHIFT)) & SIM_MISC_CTRL0_M4_OBS_CLK_DIV_RATIO_MASK) #define SIM_MISC_CTRL0_A7_OBS_CLK_SRC_SEL_MASK (0x1E000U) #define SIM_MISC_CTRL0_A7_OBS_CLK_SRC_SEL_SHIFT (13U) /*! A7_OBS_CLK_SRC_SEL - Selects the clock to be observed on A7 domain. */ #define SIM_MISC_CTRL0_A7_OBS_CLK_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTRL0_A7_OBS_CLK_SRC_SEL_SHIFT)) & SIM_MISC_CTRL0_A7_OBS_CLK_SRC_SEL_MASK) #define SIM_MISC_CTRL0_A7_OBS_CLK_DIV_RATIO_MASK (0xE0000U) #define SIM_MISC_CTRL0_A7_OBS_CLK_DIV_RATIO_SHIFT (17U) /*! A7_OBS_CLK_DIV_RATIO - Selection of division rate (2**n) of A7 observation clock div rate = 2**n (n=0..7). */ #define SIM_MISC_CTRL0_A7_OBS_CLK_DIV_RATIO(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTRL0_A7_OBS_CLK_DIV_RATIO_SHIFT)) & SIM_MISC_CTRL0_A7_OBS_CLK_DIV_RATIO_MASK) #define SIM_MISC_CTRL0_TESTCLK_TRIM_MASK (0x700000U) #define SIM_MISC_CTRL0_TESTCLK_TRIM_SHIFT (20U) /*! TESTCLK_TRIM - Trim Delay for LVDS TESTCLK_P/TESTCLK_N pad. */ #define SIM_MISC_CTRL0_TESTCLK_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTRL0_TESTCLK_TRIM_SHIFT)) & SIM_MISC_CTRL0_TESTCLK_TRIM_MASK) #define SIM_MISC_CTRL0_TESTCLK_OBE_MASK (0x800000U) #define SIM_MISC_CTRL0_TESTCLK_OBE_SHIFT (23U) /*! TESTCLK_OBE - Output Buffer Enable for LVDS TESTCLK_P/TESTCLK_N pad. */ #define SIM_MISC_CTRL0_TESTCLK_OBE(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTRL0_TESTCLK_OBE_SHIFT)) & SIM_MISC_CTRL0_TESTCLK_OBE_MASK) #define SIM_MISC_CTRL0_DISABLE_DDR_HW_AUTO_LP_MODE_MASK (0x1000000U) #define SIM_MISC_CTRL0_DISABLE_DDR_HW_AUTO_LP_MODE_SHIFT (24U) /*! DISABLE_DDR_HW_AUTO_LP_MODE - Disable control to put DDR in self-refresh mode automatically by HW during low power modes. */ #define SIM_MISC_CTRL0_DISABLE_DDR_HW_AUTO_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTRL0_DISABLE_DDR_HW_AUTO_LP_MODE_SHIFT)) & SIM_MISC_CTRL0_DISABLE_DDR_HW_AUTO_LP_MODE_MASK) #define SIM_MISC_CTRL0_A7_TSTMR_COMP_EN_MASK (0x2000000U) #define SIM_MISC_CTRL0_A7_TSTMR_COMP_EN_SHIFT (25U) /*! A7_TSTMR_COMP_EN - Enables the compare of A7 TS Timer versus a programmed value. */ #define SIM_MISC_CTRL0_A7_TSTMR_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTRL0_A7_TSTMR_COMP_EN_SHIFT)) & SIM_MISC_CTRL0_A7_TSTMR_COMP_EN_MASK) #define SIM_MISC_CTRL0_A7_TO_M4_RST_IRQ_CTRL_MASK (0x4000000U) #define SIM_MISC_CTRL0_A7_TO_M4_RST_IRQ_CTRL_SHIFT (26U) /*! A7_TO_M4_RST_IRQ_CTRL - Controls the assertion of A7 reset as IRQ/Wake-up to M4. */ #define SIM_MISC_CTRL0_A7_TO_M4_RST_IRQ_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTRL0_A7_TO_M4_RST_IRQ_CTRL_SHIFT)) & SIM_MISC_CTRL0_A7_TO_M4_RST_IRQ_CTRL_MASK) #define SIM_MISC_CTRL0_A7_TO_M4_RST_IRQ_EN_MASK (0x8000000U) #define SIM_MISC_CTRL0_A7_TO_M4_RST_IRQ_EN_SHIFT (27U) /*! A7_TO_M4_RST_IRQ_EN - Enables the assertion of A7 reset as IRQ/Wake-up to M4. */ #define SIM_MISC_CTRL0_A7_TO_M4_RST_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTRL0_A7_TO_M4_RST_IRQ_EN_SHIFT)) & SIM_MISC_CTRL0_A7_TO_M4_RST_IRQ_EN_MASK) #define SIM_MISC_CTRL0_A7_TSTMR_COMP_IRQ_CTRL_MASK (0x20000000U) #define SIM_MISC_CTRL0_A7_TSTMR_COMP_IRQ_CTRL_SHIFT (29U) /*! A7_TSTMR_COMP_IRQ_CTRL - Controls the compare of A7 reset as IRQ. */ #define SIM_MISC_CTRL0_A7_TSTMR_COMP_IRQ_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTRL0_A7_TSTMR_COMP_IRQ_CTRL_SHIFT)) & SIM_MISC_CTRL0_A7_TSTMR_COMP_IRQ_CTRL_MASK) /*! @} */ /*! @name SIM_DGO_CTRL0 - SIM DGO Control Register 0 */ /*! @{ */ #define SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP1_MASK (0x1U) #define SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP1_SHIFT (0U) /*! UPDATE_DGO_GP1 - Writing 1 to this bit field indicates corresponding DGO_GP1 register has been updated with new values. */ #define SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP1_SHIFT)) & SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP1_MASK) #define SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP2_MASK (0x2U) #define SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP2_SHIFT (1U) /*! UPDATE_DGO_GP2 - Writing 1 to this bit field indicates corresponding DGO_GP2 register has been updated with new values. */ #define SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP2_SHIFT)) & SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP2_MASK) #define SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP3_MASK (0x4U) #define SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP3_SHIFT (2U) /*! UPDATE_DGO_GP3 - Writing 1 to this bit field indicates corresponding DGO_GP3 register has been updated with new values. */ #define SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP3_SHIFT)) & SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP3_MASK) #define SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP4_MASK (0x8U) #define SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP4_SHIFT (3U) /*! UPDATE_DGO_GP4 - Writing 1 to this bit field indicates corresponding DGO_GP4 register has been updated with new values. */ #define SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP4_SHIFT)) & SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP4_MASK) #define SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP5_MASK (0x10U) #define SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP5_SHIFT (4U) /*! UPDATE_DGO_GP5 - Writing 1 to this bit field indicates corresponding DGO_GP5 register has been updated with new values. */ #define SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP5_SHIFT)) & SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP5_MASK) #define SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP6_MASK (0x20U) #define SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP6_SHIFT (5U) /*! UPDATE_DGO_GP6 - Writing 1 to this bit field indicates corresponding DGO_GP6 register has been updated with new values. */ #define SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP6(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP6_SHIFT)) & SIM_SIM_DGO_CTRL0_UPDATE_DGO_GP6_MASK) #define SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP1_MASK (0x2000U) #define SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP1_SHIFT (13U) /*! WR_ACK_DGO_GP1 - This bit field is set automatically when corresponding DGO_GP1 register is * shadowed in DGO domain. SW needs to write "1" to clear. */ #define SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP1_SHIFT)) & SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP1_MASK) #define SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP2_MASK (0x4000U) #define SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP2_SHIFT (14U) /*! WR_ACK_DGO_GP2 - This bit field is set automatically when corresponding DGO_GP2 register is * shadowed in DGO domain. SW needs to write "1" to clear. */ #define SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP2_SHIFT)) & SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP2_MASK) #define SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP3_MASK (0x8000U) #define SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP3_SHIFT (15U) /*! WR_ACK_DGO_GP3 - This bit field is set automatically when corresponding DGO_GP3 register is * shadowed in DGO domain. SW needs to write "1" to clear. */ #define SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP3_SHIFT)) & SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP3_MASK) #define SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP4_MASK (0x10000U) #define SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP4_SHIFT (16U) /*! WR_ACK_DGO_GP4 - This bit field is set automatically when corresponding DGO_GP4 register is * shadowed in DGO domain. SW needs to write "1" to clear. */ #define SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP4_SHIFT)) & SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP4_MASK) #define SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP5_MASK (0x20000U) #define SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP5_SHIFT (17U) /*! WR_ACK_DGO_GP5 - This bit field is set automatically when corresponding DGO_GP5 register is * shadowed in DGO domain. SW needs to write "1" to clear. */ #define SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP5_SHIFT)) & SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP5_MASK) #define SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP6_MASK (0x40000U) #define SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP6_SHIFT (18U) /*! WR_ACK_DGO_GP6 - This bit field is set automatically when corresponding DGO_GP6 register is * shadowed in DGO domain. SW needs to write "1" to clear. */ #define SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP6(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP6_SHIFT)) & SIM_SIM_DGO_CTRL0_WR_ACK_DGO_GP6_MASK) #define SIM_SIM_DGO_CTRL0_INT_EN_ACK1_MASK (0x4000000U) #define SIM_SIM_DGO_CTRL0_INT_EN_ACK1_SHIFT (26U) /*! INT_EN_ACK1 - Interrupt enable for WR_ACK_DGO_GP1 bit field. */ #define SIM_SIM_DGO_CTRL0_INT_EN_ACK1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL0_INT_EN_ACK1_SHIFT)) & SIM_SIM_DGO_CTRL0_INT_EN_ACK1_MASK) #define SIM_SIM_DGO_CTRL0_INT_EN_ACK2_MASK (0x8000000U) #define SIM_SIM_DGO_CTRL0_INT_EN_ACK2_SHIFT (27U) /*! INT_EN_ACK2 - Interrupt enable for WR_ACK_DGO_GP2 bit field. */ #define SIM_SIM_DGO_CTRL0_INT_EN_ACK2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL0_INT_EN_ACK2_SHIFT)) & SIM_SIM_DGO_CTRL0_INT_EN_ACK2_MASK) #define SIM_SIM_DGO_CTRL0_INT_EN_ACK3_MASK (0x10000000U) #define SIM_SIM_DGO_CTRL0_INT_EN_ACK3_SHIFT (28U) /*! INT_EN_ACK3 - Interrupt enable for WR_ACK_DGO_GP3 bit field. */ #define SIM_SIM_DGO_CTRL0_INT_EN_ACK3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL0_INT_EN_ACK3_SHIFT)) & SIM_SIM_DGO_CTRL0_INT_EN_ACK3_MASK) #define SIM_SIM_DGO_CTRL0_INT_EN_ACK4_MASK (0x20000000U) #define SIM_SIM_DGO_CTRL0_INT_EN_ACK4_SHIFT (29U) /*! INT_EN_ACK4 - Interrupt enable for WR_ACK_DGO_GP4 bit field. */ #define SIM_SIM_DGO_CTRL0_INT_EN_ACK4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL0_INT_EN_ACK4_SHIFT)) & SIM_SIM_DGO_CTRL0_INT_EN_ACK4_MASK) #define SIM_SIM_DGO_CTRL0_INT_EN_ACK5_MASK (0x40000000U) #define SIM_SIM_DGO_CTRL0_INT_EN_ACK5_SHIFT (30U) /*! INT_EN_ACK5 - Interrupt enable for WR_ACK_DGO_GP5 bit field. */ #define SIM_SIM_DGO_CTRL0_INT_EN_ACK5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL0_INT_EN_ACK5_SHIFT)) & SIM_SIM_DGO_CTRL0_INT_EN_ACK5_MASK) #define SIM_SIM_DGO_CTRL0_INT_EN_ACK6_MASK (0x80000000U) #define SIM_SIM_DGO_CTRL0_INT_EN_ACK6_SHIFT (31U) /*! INT_EN_ACK6 - Interrupt enable for WR_ACK_DGO_GP6 bit field. */ #define SIM_SIM_DGO_CTRL0_INT_EN_ACK6(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL0_INT_EN_ACK6_SHIFT)) & SIM_SIM_DGO_CTRL0_INT_EN_ACK6_MASK) /*! @} */ /*! @name SIM_DGO_CTRL1 - SIM DGO Control Register 1 */ /*! @{ */ #define SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP7_MASK (0x1U) #define SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP7_SHIFT (0U) /*! UPDATE_DGO_GP7 - Writing 1 to this bit field indicates corresponding DGO_GP7 register has been updated with new values. */ #define SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP7(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP7_SHIFT)) & SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP7_MASK) #define SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP8_MASK (0x2U) #define SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP8_SHIFT (1U) /*! UPDATE_DGO_GP8 - Writing 1 to this bit field indicates corresponding DGO_GP8 register has been updated with new values. */ #define SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP8(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP8_SHIFT)) & SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP8_MASK) #define SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP9_MASK (0x4U) #define SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP9_SHIFT (2U) /*! UPDATE_DGO_GP9 - Writing 1 to this bit field indicates corresponding DGO_GP9 register has been updated with new values. */ #define SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP9(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP9_SHIFT)) & SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP9_MASK) #define SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP10_MASK (0x8U) #define SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP10_SHIFT (3U) /*! UPDATE_DGO_GP10 - Writing 1 to this bit field indicates corresponding DGO_GP10 register has been updated with new values. */ #define SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP10(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP10_SHIFT)) & SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP10_MASK) #define SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP11_MASK (0x10U) #define SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP11_SHIFT (4U) /*! UPDATE_DGO_GP11 - Writing 1 to this bit field indicates corresponding DGO_GP11 register has been updated with new values. */ #define SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP11(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP11_SHIFT)) & SIM_SIM_DGO_CTRL1_UPDATE_DGO_GP11_MASK) #define SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP7_MASK (0x2000U) #define SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP7_SHIFT (13U) /*! WR_ACK_DGO_GP7 - This bit field is set automatically when corresponding DGO_GP7 register is * shadowed in DGO domain. SW needs to write "1" to clear. */ #define SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP7(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP7_SHIFT)) & SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP7_MASK) #define SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP8_MASK (0x4000U) #define SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP8_SHIFT (14U) /*! WR_ACK_DGO_GP8 - This bit field is set automatically when corresponding DGO_GP8 register is * shadowed in DGO domain. SW needs to write "1" to clear. */ #define SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP8(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP8_SHIFT)) & SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP8_MASK) #define SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP9_MASK (0x8000U) #define SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP9_SHIFT (15U) /*! WR_ACK_DGO_GP9 - This bit field is set automatically when corresponding DGO_GP9 register is * shadowed in DGO domain. SW needs to write "1" to clear. */ #define SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP9(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP9_SHIFT)) & SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP9_MASK) #define SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP10_MASK (0x10000U) #define SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP10_SHIFT (16U) /*! WR_ACK_DGO_GP10 - This bit field is set automatically when corresponding DGO_GP10 register is * shadowed in DGO domain. SW needs to write "1" to clear. */ #define SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP10(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP10_SHIFT)) & SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP10_MASK) #define SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP11_MASK (0x20000U) #define SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP11_SHIFT (17U) /*! WR_ACK_DGO_GP11 - This bit field is set automatically when corresponding DGO_GP11 register is * shadowed in DGO domain. SW needs to write "1" to clear. */ #define SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP11(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP11_SHIFT)) & SIM_SIM_DGO_CTRL1_WR_ACK_DGO_GP11_MASK) #define SIM_SIM_DGO_CTRL1_INT_EN_ACK7_MASK (0x8000000U) #define SIM_SIM_DGO_CTRL1_INT_EN_ACK7_SHIFT (27U) /*! INT_EN_ACK7 - Interrupt enable for WR_ACK_DGO_GP7 bit field. */ #define SIM_SIM_DGO_CTRL1_INT_EN_ACK7(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL1_INT_EN_ACK7_SHIFT)) & SIM_SIM_DGO_CTRL1_INT_EN_ACK7_MASK) #define SIM_SIM_DGO_CTRL1_INT_EN_ACK8_MASK (0x10000000U) #define SIM_SIM_DGO_CTRL1_INT_EN_ACK8_SHIFT (28U) /*! INT_EN_ACK8 - Interrupt enable for WR_ACK_DGO_GP8 bit field. */ #define SIM_SIM_DGO_CTRL1_INT_EN_ACK8(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL1_INT_EN_ACK8_SHIFT)) & SIM_SIM_DGO_CTRL1_INT_EN_ACK8_MASK) #define SIM_SIM_DGO_CTRL1_INT_EN_ACK9_MASK (0x20000000U) #define SIM_SIM_DGO_CTRL1_INT_EN_ACK9_SHIFT (29U) /*! INT_EN_ACK9 - Interrupt enable for WR_ACK_DGO_GP9 bit field. */ #define SIM_SIM_DGO_CTRL1_INT_EN_ACK9(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL1_INT_EN_ACK9_SHIFT)) & SIM_SIM_DGO_CTRL1_INT_EN_ACK9_MASK) #define SIM_SIM_DGO_CTRL1_INT_EN_ACK10_MASK (0x40000000U) #define SIM_SIM_DGO_CTRL1_INT_EN_ACK10_SHIFT (30U) /*! INT_EN_ACK10 - Interrupt enable for WR_ACK_DGO_GP10 bit field. */ #define SIM_SIM_DGO_CTRL1_INT_EN_ACK10(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL1_INT_EN_ACK10_SHIFT)) & SIM_SIM_DGO_CTRL1_INT_EN_ACK10_MASK) #define SIM_SIM_DGO_CTRL1_INT_EN_ACK11_MASK (0x80000000U) #define SIM_SIM_DGO_CTRL1_INT_EN_ACK11_SHIFT (31U) /*! INT_EN_ACK11 - Interrupt enable for WR_ACK_DGO_GP11 bit field. */ #define SIM_SIM_DGO_CTRL1_INT_EN_ACK11(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_CTRL1_INT_EN_ACK11_SHIFT)) & SIM_SIM_DGO_CTRL1_INT_EN_ACK11_MASK) /*! @} */ /*! @name SIM_DGO_GP1 - SIM DGO General Purpose Register 1 */ /*! @{ */ #define SIM_SIM_DGO_GP1_SIM_DGO_GP1_MASK (0xFFFFFFFFU) #define SIM_SIM_DGO_GP1_SIM_DGO_GP1_SHIFT (0U) /*! SIM_DGO_GP1 - SIM DGO General purpose register 1. Contents are retained between power cycles */ #define SIM_SIM_DGO_GP1_SIM_DGO_GP1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_GP1_SIM_DGO_GP1_SHIFT)) & SIM_SIM_DGO_GP1_SIM_DGO_GP1_MASK) /*! @} */ /*! @name SIM_DGO_GP2 - SIM DGO general Purpose Register 2 */ /*! @{ */ #define SIM_SIM_DGO_GP2_SIM_DGO_GP2_MASK (0xFFFFFFFFU) #define SIM_SIM_DGO_GP2_SIM_DGO_GP2_SHIFT (0U) /*! SIM_DGO_GP2 - SIM DGO General purpose register 2. Contents are retained between power cycles */ #define SIM_SIM_DGO_GP2_SIM_DGO_GP2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_GP2_SIM_DGO_GP2_SHIFT)) & SIM_SIM_DGO_GP2_SIM_DGO_GP2_MASK) /*! @} */ /*! @name SIM_DGO_GP3 - SIM DGO General Purpose Register 3 */ /*! @{ */ #define SIM_SIM_DGO_GP3_SIM_DGO_GP3_MASK (0xFFFFFFFFU) #define SIM_SIM_DGO_GP3_SIM_DGO_GP3_SHIFT (0U) /*! SIM_DGO_GP3 - SIM DGO General purpose register 3. Contents are retained between power cycles */ #define SIM_SIM_DGO_GP3_SIM_DGO_GP3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_GP3_SIM_DGO_GP3_SHIFT)) & SIM_SIM_DGO_GP3_SIM_DGO_GP3_MASK) /*! @} */ /*! @name SIM_DGO_GP4 - SIM DGO General Purpose Register 4 */ /*! @{ */ #define SIM_SIM_DGO_GP4_SIM_DGO_GP4_MASK (0xFFFFFFFFU) #define SIM_SIM_DGO_GP4_SIM_DGO_GP4_SHIFT (0U) /*! SIM_DGO_GP4 - SIM DGO General purpose register 4. Contents are retained between power cycles */ #define SIM_SIM_DGO_GP4_SIM_DGO_GP4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_GP4_SIM_DGO_GP4_SHIFT)) & SIM_SIM_DGO_GP4_SIM_DGO_GP4_MASK) /*! @} */ /*! @name SIM_DGO_GP5 - SIM DGO General Purpose Register 5 */ /*! @{ */ #define SIM_SIM_DGO_GP5_SIM_DGO_GP5_MASK (0xFFFFFFFFU) #define SIM_SIM_DGO_GP5_SIM_DGO_GP5_SHIFT (0U) /*! SIM_DGO_GP5 - SIM DGO General purpose register 5. Contents are retained between power cycles */ #define SIM_SIM_DGO_GP5_SIM_DGO_GP5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_GP5_SIM_DGO_GP5_SHIFT)) & SIM_SIM_DGO_GP5_SIM_DGO_GP5_MASK) /*! @} */ /*! @name SIM_DGO_GP6 - SIM DGO General Purpose Register 6 */ /*! @{ */ #define SIM_SIM_DGO_GP6_SIM_DGO_GP6_MASK (0xFFFFFFFFU) #define SIM_SIM_DGO_GP6_SIM_DGO_GP6_SHIFT (0U) /*! SIM_DGO_GP6 - SIM DGO General purpose register 6. Contents are retained between power cycles */ #define SIM_SIM_DGO_GP6_SIM_DGO_GP6(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_GP6_SIM_DGO_GP6_SHIFT)) & SIM_SIM_DGO_GP6_SIM_DGO_GP6_MASK) /*! @} */ /*! @name SIM_DGO_GP7 - SIM DGO General Purpose Register 7 */ /*! @{ */ #define SIM_SIM_DGO_GP7_SIM_DGO_GP7_MASK (0xFFFFFFFFU) #define SIM_SIM_DGO_GP7_SIM_DGO_GP7_SHIFT (0U) /*! SIM_DGO_GP7 - SIM DGO General purpose register 7. Contents are retained between power cycles */ #define SIM_SIM_DGO_GP7_SIM_DGO_GP7(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_GP7_SIM_DGO_GP7_SHIFT)) & SIM_SIM_DGO_GP7_SIM_DGO_GP7_MASK) /*! @} */ /*! @name SIM_DGO_GP8 - SIM DGO General Purpose Register 8 */ /*! @{ */ #define SIM_SIM_DGO_GP8_SIM_DGO_GP8_MASK (0xFFFFFFFFU) #define SIM_SIM_DGO_GP8_SIM_DGO_GP8_SHIFT (0U) /*! SIM_DGO_GP8 - SIM DGO General purpose register 8. Contents are retained between power cycles */ #define SIM_SIM_DGO_GP8_SIM_DGO_GP8(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_GP8_SIM_DGO_GP8_SHIFT)) & SIM_SIM_DGO_GP8_SIM_DGO_GP8_MASK) /*! @} */ /*! @name SIM_DGO_GP9 - SIM DGO General Purpose Register 9 */ /*! @{ */ #define SIM_SIM_DGO_GP9_SIM_DGO_GP9_MASK (0xFFFFFFFFU) #define SIM_SIM_DGO_GP9_SIM_DGO_GP9_SHIFT (0U) /*! SIM_DGO_GP9 - SIM DGO General purpose register 9. Contents are retained between power cycles */ #define SIM_SIM_DGO_GP9_SIM_DGO_GP9(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_GP9_SIM_DGO_GP9_SHIFT)) & SIM_SIM_DGO_GP9_SIM_DGO_GP9_MASK) /*! @} */ /*! @name SIM_DGO_GP10 - SIM DGO General Purpose Register 10 */ /*! @{ */ #define SIM_SIM_DGO_GP10_SIM_DGO_GP10_MASK (0xFFFFFFFFU) #define SIM_SIM_DGO_GP10_SIM_DGO_GP10_SHIFT (0U) /*! SIM_DGO_GP10 - SIM DGO General purpose register 10. Contents are retained between power cycles */ #define SIM_SIM_DGO_GP10_SIM_DGO_GP10(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_GP10_SIM_DGO_GP10_SHIFT)) & SIM_SIM_DGO_GP10_SIM_DGO_GP10_MASK) /*! @} */ /*! @name SIM_DGO_GP11 - SIM DGO General Purpose Register 11 */ /*! @{ */ #define SIM_SIM_DGO_GP11_DBG_SPIDEN_SPNIDEN_MASK (0x1U) #define SIM_SIM_DGO_GP11_DBG_SPIDEN_SPNIDEN_SHIFT (0U) /*! DBG_SPIDEN_SPNIDEN - Debug secured access enable. */ #define SIM_SIM_DGO_GP11_DBG_SPIDEN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_GP11_DBG_SPIDEN_SPNIDEN_SHIFT)) & SIM_SIM_DGO_GP11_DBG_SPIDEN_SPNIDEN_MASK) #define SIM_SIM_DGO_GP11_NMI_VLLS_WAKEUP_EN_MASK (0x80U) #define SIM_SIM_DGO_GP11_NMI_VLLS_WAKEUP_EN_SHIFT (7U) /*! NMI_VLLS_WAKEUP_EN - Enables NMI pin as VLLS wakeup source (not necessary for non-VLLS modes). */ #define SIM_SIM_DGO_GP11_NMI_VLLS_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_GP11_NMI_VLLS_WAKEUP_EN_SHIFT)) & SIM_SIM_DGO_GP11_NMI_VLLS_WAKEUP_EN_MASK) #define SIM_SIM_DGO_GP11_USB_PHY_VLLS_WAKEUP_EN_MASK (0x1000U) #define SIM_SIM_DGO_GP11_USB_PHY_VLLS_WAKEUP_EN_SHIFT (12U) /*! USB_PHY_VLLS_WAKEUP_EN - USB PHY VLLS wakeup enable. */ #define SIM_SIM_DGO_GP11_USB_PHY_VLLS_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_GP11_USB_PHY_VLLS_WAKEUP_EN_SHIFT)) & SIM_SIM_DGO_GP11_USB_PHY_VLLS_WAKEUP_EN_MASK) #define SIM_SIM_DGO_GP11_PTA_RANGE_CTRL_MASK (0x30000U) #define SIM_SIM_DGO_GP11_PTA_RANGE_CTRL_SHIFT (16U) /*! PTA_RANGE_CTRL - PTA Range Control. */ #define SIM_SIM_DGO_GP11_PTA_RANGE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_GP11_PTA_RANGE_CTRL_SHIFT)) & SIM_SIM_DGO_GP11_PTA_RANGE_CTRL_MASK) #define SIM_SIM_DGO_GP11_PTB_RANGE_CTRL_MASK (0xC0000U) #define SIM_SIM_DGO_GP11_PTB_RANGE_CTRL_SHIFT (18U) /*! PTB_RANGE_CTRL - PTB Range Control. */ #define SIM_SIM_DGO_GP11_PTB_RANGE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_GP11_PTB_RANGE_CTRL_SHIFT)) & SIM_SIM_DGO_GP11_PTB_RANGE_CTRL_MASK) #define SIM_SIM_DGO_GP11_PTC_RANGE_CTRL_MASK (0x300000U) #define SIM_SIM_DGO_GP11_PTC_RANGE_CTRL_SHIFT (20U) /*! PTC_RANGE_CTRL - PTC Range Control. */ #define SIM_SIM_DGO_GP11_PTC_RANGE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_GP11_PTC_RANGE_CTRL_SHIFT)) & SIM_SIM_DGO_GP11_PTC_RANGE_CTRL_MASK) #define SIM_SIM_DGO_GP11_PTE_RANGE_CTRL_MASK (0xC00000U) #define SIM_SIM_DGO_GP11_PTE_RANGE_CTRL_SHIFT (22U) /*! PTE_RANGE_CTRL - PTE Range Control. */ #define SIM_SIM_DGO_GP11_PTE_RANGE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_GP11_PTE_RANGE_CTRL_SHIFT)) & SIM_SIM_DGO_GP11_PTE_RANGE_CTRL_MASK) #define SIM_SIM_DGO_GP11_PTF_RANGE_CTRL_MASK (0x3000000U) #define SIM_SIM_DGO_GP11_PTF_RANGE_CTRL_SHIFT (24U) /*! PTF_RANGE_CTRL - PTF Range Control. */ #define SIM_SIM_DGO_GP11_PTF_RANGE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SIM_DGO_GP11_PTF_RANGE_CTRL_SHIFT)) & SIM_SIM_DGO_GP11_PTF_RANGE_CTRL_MASK) /*! @} */ /*! @name WKPU_WAKEUP_EN - WKPU Wake-up Enable */ /*! @{ */ #define SIM_WKPU_WAKEUP_EN_WKPU_CH_WAKEUP_EN_MASK (0xFFFFFFFFU) #define SIM_WKPU_WAKEUP_EN_WKPU_CH_WAKEUP_EN_SHIFT (0U) /*! WKPU_CH_WAKEUP_EN - Bit used to disable wake-up events through this channel. Each channel may * have one or multiple wake-up sources associated to it. */ #define SIM_WKPU_WAKEUP_EN_WKPU_CH_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_WKPU_WAKEUP_EN_WKPU_CH_WAKEUP_EN_SHIFT)) & SIM_WKPU_WAKEUP_EN_WKPU_CH_WAKEUP_EN_MASK) /*! @} */ /*! @name JTAG_ID_REG - Mirror of JTAG ID Register */ /*! @{ */ #define SIM_JTAG_ID_REG_JTAG_INIT_BIT_MASK (0x1U) #define SIM_JTAG_ID_REG_JTAG_INIT_BIT_SHIFT (0U) /*! JTAG_INIT_BIT - JTAG ID initial bit. */ #define SIM_JTAG_ID_REG_JTAG_INIT_BIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_JTAG_ID_REG_JTAG_INIT_BIT_SHIFT)) & SIM_JTAG_ID_REG_JTAG_INIT_BIT_MASK) #define SIM_JTAG_ID_REG_COMPANY_IDCODE_MASK (0xFFEU) #define SIM_JTAG_ID_REG_COMPANY_IDCODE_SHIFT (1U) /*! COMPANY_IDCODE - Company ID Code. */ #define SIM_JTAG_ID_REG_COMPANY_IDCODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_JTAG_ID_REG_COMPANY_IDCODE_SHIFT)) & SIM_JTAG_ID_REG_COMPANY_IDCODE_MASK) #define SIM_JTAG_ID_REG_PIN_PLUG_MASK (0x3FF000U) #define SIM_JTAG_ID_REG_PIN_PLUG_SHIFT (12U) /*! PIN_PLUG - Part Identification Number. */ #define SIM_JTAG_ID_REG_PIN_PLUG(x) (((uint32_t)(((uint32_t)(x)) << SIM_JTAG_ID_REG_PIN_PLUG_SHIFT)) & SIM_JTAG_ID_REG_PIN_PLUG_MASK) #define SIM_JTAG_ID_REG_DESIGN_CENTER_IDCODE_MASK (0xFC00000U) #define SIM_JTAG_ID_REG_DESIGN_CENTER_IDCODE_SHIFT (22U) /*! DESIGN_CENTER_IDCODE - Design Center ID Code. */ #define SIM_JTAG_ID_REG_DESIGN_CENTER_IDCODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_JTAG_ID_REG_DESIGN_CENTER_IDCODE_SHIFT)) & SIM_JTAG_ID_REG_DESIGN_CENTER_IDCODE_MASK) #define SIM_JTAG_ID_REG_PRN_PLUG_MASK (0xF0000000U) #define SIM_JTAG_ID_REG_PRN_PLUG_SHIFT (28U) /*! PRN_PLUG - Part Revision Number. */ #define SIM_JTAG_ID_REG_PRN_PLUG(x) (((uint32_t)(((uint32_t)(x)) << SIM_JTAG_ID_REG_PRN_PLUG_SHIFT)) & SIM_JTAG_ID_REG_PRN_PLUG_MASK) /*! @} */ /*! @name A7_TSTMR_CMP_VAL_L - Lower A7 TS Timer compare value */ /*! @{ */ #define SIM_A7_TSTMR_CMP_VAL_L_A7_TSTMR_CMP_VAL_L_MASK (0xFFFFFFFFU) #define SIM_A7_TSTMR_CMP_VAL_L_A7_TSTMR_CMP_VAL_L_SHIFT (0U) /*! A7_TSTMR_CMP_VAL_L - Lower A7 TS Timer compare value. */ #define SIM_A7_TSTMR_CMP_VAL_L_A7_TSTMR_CMP_VAL_L(x) (((uint32_t)(((uint32_t)(x)) << SIM_A7_TSTMR_CMP_VAL_L_A7_TSTMR_CMP_VAL_L_SHIFT)) & SIM_A7_TSTMR_CMP_VAL_L_A7_TSTMR_CMP_VAL_L_MASK) /*! @} */ /*! @name A7_TSTMR_CMP_VAL_H - Upper A7 TS Timer compare value */ /*! @{ */ #define SIM_A7_TSTMR_CMP_VAL_H_A7_TSTMR_CMP_VAL_H_MASK (0xFFFFFFFFU) #define SIM_A7_TSTMR_CMP_VAL_H_A7_TSTMR_CMP_VAL_H_SHIFT (0U) /*! A7_TSTMR_CMP_VAL_H - Upper A7 TS Timer compare value. */ #define SIM_A7_TSTMR_CMP_VAL_H_A7_TSTMR_CMP_VAL_H(x) (((uint32_t)(((uint32_t)(x)) << SIM_A7_TSTMR_CMP_VAL_H_A7_TSTMR_CMP_VAL_H_SHIFT)) & SIM_A7_TSTMR_CMP_VAL_H_A7_TSTMR_CMP_VAL_H_MASK) /*! @} */ /*! @name COMP_CELL_OVERRIDE - Override Control for Compensation Codes */ /*! @{ */ #define SIM_COMP_CELL_OVERRIDE_RASRCN_MASK (0xFU) #define SIM_COMP_CELL_OVERRIDE_RASRCN_SHIFT (0U) /*! RASRCN - 4-bit NMOS compensation codes. */ #define SIM_COMP_CELL_OVERRIDE_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << SIM_COMP_CELL_OVERRIDE_RASRCN_SHIFT)) & SIM_COMP_CELL_OVERRIDE_RASRCN_MASK) #define SIM_COMP_CELL_OVERRIDE_RASRCP_MASK (0xF0U) #define SIM_COMP_CELL_OVERRIDE_RASRCP_SHIFT (4U) /*! RASRCP - 4-bit PMOS compensation codes. */ #define SIM_COMP_CELL_OVERRIDE_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << SIM_COMP_CELL_OVERRIDE_RASRCP_SHIFT)) & SIM_COMP_CELL_OVERRIDE_RASRCP_MASK) #define SIM_COMP_CELL_OVERRIDE_READ_MODE_MASK (0x100U) #define SIM_COMP_CELL_OVERRIDE_READ_MODE_SHIFT (8U) /*! READ_MODE - Read Mode. */ #define SIM_COMP_CELL_OVERRIDE_READ_MODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_COMP_CELL_OVERRIDE_READ_MODE_SHIFT)) & SIM_COMP_CELL_OVERRIDE_READ_MODE_MASK) #define SIM_COMP_CELL_OVERRIDE_FASTFREEZE_MASK (0x200U) #define SIM_COMP_CELL_OVERRIDE_FASTFREEZE_SHIFT (9U) /*! FASTFREEZE - Fast-Freeze. */ #define SIM_COMP_CELL_OVERRIDE_FASTFREEZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_COMP_CELL_OVERRIDE_FASTFREEZE_SHIFT)) & SIM_COMP_CELL_OVERRIDE_FASTFREEZE_MASK) #define SIM_COMP_CELL_OVERRIDE_FREEZE_MASK (0x400U) #define SIM_COMP_CELL_OVERRIDE_FREEZE_SHIFT (10U) /*! FREEZE - Freeze. */ #define SIM_COMP_CELL_OVERRIDE_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_COMP_CELL_OVERRIDE_FREEZE_SHIFT)) & SIM_COMP_CELL_OVERRIDE_FREEZE_MASK) #define SIM_COMP_CELL_OVERRIDE_NASRCN_MASK (0xF0000U) #define SIM_COMP_CELL_OVERRIDE_NASRCN_SHIFT (16U) /*! NASRCN - 4-bit NMOS compensation measured/generated codes. */ #define SIM_COMP_CELL_OVERRIDE_NASRCN(x) (((uint32_t)(((uint32_t)(x)) << SIM_COMP_CELL_OVERRIDE_NASRCN_SHIFT)) & SIM_COMP_CELL_OVERRIDE_NASRCN_MASK) #define SIM_COMP_CELL_OVERRIDE_NASRCP_MASK (0xF00000U) #define SIM_COMP_CELL_OVERRIDE_NASRCP_SHIFT (20U) /*! NASRCP - 4-bit PMOS compensation measured/generated codes. */ #define SIM_COMP_CELL_OVERRIDE_NASRCP(x) (((uint32_t)(((uint32_t)(x)) << SIM_COMP_CELL_OVERRIDE_NASRCP_SHIFT)) & SIM_COMP_CELL_OVERRIDE_NASRCP_MASK) #define SIM_COMP_CELL_OVERRIDE_COMPOK_MASK (0x1000000U) #define SIM_COMP_CELL_OVERRIDE_COMPOK_SHIFT (24U) /*! COMPOK - Compensation OK. */ #define SIM_COMP_CELL_OVERRIDE_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << SIM_COMP_CELL_OVERRIDE_COMPOK_SHIFT)) & SIM_COMP_CELL_OVERRIDE_COMPOK_MASK) /*! @} */ /*! * @} */ /* end of group SIM_Register_Masks */ /* SIM - Peripheral instance base addresses */ /** Peripheral SIM base address */ #define SIM_BASE (0x410A3000u) /** Peripheral SIM base pointer */ #define SIM ((SIM_Type *)SIM_BASE) /** Array initializer of SIM peripheral base addresses */ #define SIM_BASE_ADDRS { SIM_BASE } /** Array initializer of SIM peripheral base pointers */ #define SIM_BASE_PTRS { SIM } /** Interrupt vectors for the SIM peripheral type */ #define SIM_IRQS { SIM_IRQn } /*! * @} */ /* end of group SIM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SMC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer * @{ */ /** SMC - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __IO uint32_t PMPROT; /**< Power Mode Protection register, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t PMCTRL; /**< Power Mode Control register, offset: 0x10 */ uint8_t RESERVED_1[4]; __I uint32_t PMSTAT; /**< Power Mode Status register, offset: 0x18 */ uint8_t RESERVED_2[4]; __I uint32_t SRS; /**< System Reset Status, offset: 0x20 */ __IO uint32_t RPC; /**< Reset Pin Control, offset: 0x24 */ __IO uint32_t SSRS; /**< Sticky System Reset Status, offset: 0x28 */ __IO uint32_t SRIE; /**< System Reset Interrupt Enable, offset: 0x2C */ __IO uint32_t SRIF; /**< System Reset Interrupt Flag, offset: 0x30 */ __IO uint32_t CSRE; /**< Core Software Reset Enable, offset: 0x34 */ uint8_t RESERVED_3[8]; __I uint32_t MR; /**< Mode Register, offset: 0x40 */ uint8_t RESERVED_4[28]; __IO uint32_t FM; /**< Force Mode Register, offset: 0x60 */ } SMC_Type; /* ---------------------------------------------------------------------------- -- SMC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SMC_Register_Masks SMC Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define SMC_VERID_FEATURE_MASK (0xFFFFU) #define SMC_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000010101010..Default features supported */ #define SMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_FEATURE_SHIFT)) & SMC_VERID_FEATURE_MASK) #define SMC_VERID_MINOR_MASK (0xFF0000U) #define SMC_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define SMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MINOR_SHIFT)) & SMC_VERID_MINOR_MASK) #define SMC_VERID_MAJOR_MASK (0xFF000000U) #define SMC_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define SMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MAJOR_SHIFT)) & SMC_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define SMC_PARAM_PWRD_INDPT_MASK (0x1U) #define SMC_PARAM_PWRD_INDPT_SHIFT (0U) /*! PWRD_INDPT - Power Domains Independent */ #define SMC_PARAM_PWRD_INDPT(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_PWRD_INDPT_SHIFT)) & SMC_PARAM_PWRD_INDPT_MASK) /*! @} */ /*! @name PMPROT - Power Mode Protection register */ /*! @{ */ #define SMC_PMPROT_AVLLS_MASK (0x2U) #define SMC_PMPROT_AVLLS_SHIFT (1U) /*! AVLLS - Allow Very-Low-Leakage Stop Mode * 0b0..VLLS mode is not allowed * 0b1..VLLS mode is allowed */ #define SMC_PMPROT_AVLLS(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) #define SMC_PMPROT_ALLS_MASK (0x8U) #define SMC_PMPROT_ALLS_SHIFT (3U) /*! ALLS - Allow Low-Leakage Stop Mode * 0b0..LLS is not allowed * 0b1..LLS is allowed */ #define SMC_PMPROT_ALLS(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK) #define SMC_PMPROT_AVLP_MASK (0x20U) #define SMC_PMPROT_AVLP_SHIFT (5U) /*! AVLP - Allow Very-Low-Power Modes * 0b0..VLPR, VLPW, and VLPS are not allowed. * 0b1..VLPR, VLPW, and VLPS are allowed. */ #define SMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) #define SMC_PMPROT_AHSRUN_MASK (0x80U) #define SMC_PMPROT_AHSRUN_SHIFT (7U) /*! AHSRUN - Allow High Speed Run mode * 0b0..HSRUN is not allowed * 0b1..HSRUN is allowed */ #define SMC_PMPROT_AHSRUN(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK) /*! @} */ /*! @name PMCTRL - Power Mode Control register */ /*! @{ */ #define SMC_PMCTRL_STOPM_MASK (0x7U) #define SMC_PMCTRL_STOPM_SHIFT (0U) /*! STOPM - Stop Mode Control * 0b000..Normal Stop (STOP) * 0b001..Reserved * 0b010..Very-Low-Power Stop (VLPS) * 0b011..Low-Leakage Stop (LLS) * 0b100..Very-Low-Leakage Stop (VLLS) * 0b101..Reserved * 0b110..Reserved * 0b111..Reserved */ #define SMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) #define SMC_PMCTRL_RUNM_MASK (0x300U) #define SMC_PMCTRL_RUNM_SHIFT (8U) /*! RUNM - Run Mode Control * 0b00..Normal Run mode (RUN) * 0b01..Reserved * 0b10..Very-Low-Power Run mode (VLPR) * 0b11..High Speed Run mode (HSRUN) */ #define SMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) #define SMC_PMCTRL_PSTOPO_MASK (0x30000U) #define SMC_PMCTRL_PSTOPO_SHIFT (16U) /*! PSTOPO - Partial Stop Option * 0b00..STOP - Normal Stop mode * 0b01..PSTOP1 - Partial Stop with system and bus clock disabled * 0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled * 0b11..PSTOP3 - Partial Stop with system clock enabled and bus clock enabled */ #define SMC_PMCTRL_PSTOPO(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_PSTOPO_SHIFT)) & SMC_PMCTRL_PSTOPO_MASK) #define SMC_PMCTRL_STOPA_MASK (0x1000000U) #define SMC_PMCTRL_STOPA_SHIFT (24U) /*! STOPA - Stop Abort Flag */ #define SMC_PMCTRL_STOPA(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) /*! @} */ /*! @name PMSTAT - Power Mode Status register */ /*! @{ */ #define SMC_PMSTAT_PMSTAT_MASK (0xFFU) #define SMC_PMSTAT_PMSTAT_SHIFT (0U) /*! PMSTAT - Power Mode Status * 0b00000001..Current power mode is RUN. * 0b00000010..Current power mode is any STOP mode. * 0b00000100..Current power mode is VLPR. * 0b10000000..Current power mode is HSRUN */ #define SMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) /*! @} */ /*! @name SRS - System Reset Status */ /*! @{ */ #define SMC_SRS_WAKEUP_MASK (0x1U) #define SMC_SRS_WAKEUP_SHIFT (0U) /*! WAKEUP - Wakeup Reset * 0b0..Reset not generated by wakeup from VLLS mode. * 0b1..Reset generated by wakeup from VLLS mode. */ #define SMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_WAKEUP_SHIFT)) & SMC_SRS_WAKEUP_MASK) #define SMC_SRS_POR_MASK (0x2U) #define SMC_SRS_POR_SHIFT (1U) /*! POR - POR Reset * 0b0..Reset not generated by POR. * 0b1..Reset generated by POR. */ #define SMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_POR_SHIFT)) & SMC_SRS_POR_MASK) #define SMC_SRS_LVD_MASK (0x4U) #define SMC_SRS_LVD_SHIFT (2U) /*! LVD - LVD Reset * 0b0..Reset not generated by LVD. * 0b1..Reset generated by LVD. */ #define SMC_SRS_LVD(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_LVD_SHIFT)) & SMC_SRS_LVD_MASK) #define SMC_SRS_HVD_MASK (0x8U) #define SMC_SRS_HVD_SHIFT (3U) /*! HVD - HVD Reset * 0b0..Reset not generated by HVD. * 0b1..Reset generated by HVD. */ #define SMC_SRS_HVD(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_HVD_SHIFT)) & SMC_SRS_HVD_MASK) #define SMC_SRS_WARM_MASK (0x10U) #define SMC_SRS_WARM_SHIFT (4U) /*! WARM - Warm Reset * 0b0..Reset not generated by Warm Reset source. * 0b1..Reset generated by Warm Reset source. */ #define SMC_SRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_WARM_SHIFT)) & SMC_SRS_WARM_MASK) #define SMC_SRS_FATAL_MASK (0x20U) #define SMC_SRS_FATAL_SHIFT (5U) /*! FATAL - Fatal Reset * 0b0..Reset was not generated by a fatal reset source. * 0b1..Reset was generated by a fatal reset source. */ #define SMC_SRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_FATAL_SHIFT)) & SMC_SRS_FATAL_MASK) #define SMC_SRS_CORE_MASK (0x80U) #define SMC_SRS_CORE_SHIFT (7U) /*! CORE - Core Reset * 0b0..Reset source was not core only reset. * 0b1..Reset source was core reset and reset the core only. */ #define SMC_SRS_CORE(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_CORE_SHIFT)) & SMC_SRS_CORE_MASK) #define SMC_SRS_PIN_MASK (0x100U) #define SMC_SRS_PIN_SHIFT (8U) /*! PIN - Pin Reset * 0b0..Reset was not generated from the assertion of RESET_B pin. * 0b1..Reset was generated from the assertion of RESET_B pin. */ #define SMC_SRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_PIN_SHIFT)) & SMC_SRS_PIN_MASK) #define SMC_SRS_MDM_MASK (0x200U) #define SMC_SRS_MDM_SHIFT (9U) /*! MDM - MDM Reset * 0b0..Reset was not generated from the MDM reset request. * 0b1..Reset was generated from the MDM reset request. */ #define SMC_SRS_MDM(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_MDM_SHIFT)) & SMC_SRS_MDM_MASK) #define SMC_SRS_RSTACK_MASK (0x400U) #define SMC_SRS_RSTACK_SHIFT (10U) /*! RSTACK - Reset Timeout * 0b0..Reset not generated from Reset Controller Timeout. * 0b1..Reset generated from Reset Controller Timeout. */ #define SMC_SRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_RSTACK_SHIFT)) & SMC_SRS_RSTACK_MASK) #define SMC_SRS_STOPACK_MASK (0x800U) #define SMC_SRS_STOPACK_SHIFT (11U) /*! STOPACK - Stop Timeout Reset * 0b0..Reset not generated by Stop Controller Timeout. * 0b1..Reset generated by Stop Controller Timeout. */ #define SMC_SRS_STOPACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_STOPACK_SHIFT)) & SMC_SRS_STOPACK_MASK) #define SMC_SRS_SCG_MASK (0x1000U) #define SMC_SRS_SCG_SHIFT (12U) /*! SCG - SCG Reset * 0b0..Reset is not generated from an SCG loss of lock or loss of clock. * 0b1..Reset is generated from an SCG loss of lock or loss of clock. */ #define SMC_SRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_SCG_SHIFT)) & SMC_SRS_SCG_MASK) #define SMC_SRS_WDOG_MASK (0x2000U) #define SMC_SRS_WDOG_SHIFT (13U) /*! WDOG - Watchdog Reset * 0b0..Reset is not generated from the WatchDog timeout. * 0b1..Reset is generated from the WatchDog timeout. */ #define SMC_SRS_WDOG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_WDOG_SHIFT)) & SMC_SRS_WDOG_MASK) #define SMC_SRS_SW_MASK (0x4000U) #define SMC_SRS_SW_SHIFT (14U) /*! SW - Software Reset * 0b0..Reset not generated by software request from core. * 0b1..Reset generated by software request from core. */ #define SMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_SW_SHIFT)) & SMC_SRS_SW_MASK) #define SMC_SRS_LOCKUP_MASK (0x8000U) #define SMC_SRS_LOCKUP_SHIFT (15U) /*! LOCKUP - Lockup Reset * 0b0..Reset not generated by core lockup or exception. * 0b1..Reset generated by core lockup or exception. */ #define SMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_LOCKUP_SHIFT)) & SMC_SRS_LOCKUP_MASK) #define SMC_SRS_CORE0_MASK (0x10000U) #define SMC_SRS_CORE0_SHIFT (16U) /*! CORE0 - Core0 System Reset * 0b0..Reset not generated from Core0 system reset source. * 0b1..Reset generated from Core0 system reset source. */ #define SMC_SRS_CORE0(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_CORE0_SHIFT)) & SMC_SRS_CORE0_MASK) #define SMC_SRS_CORE1_MASK (0x10000U) #define SMC_SRS_CORE1_SHIFT (16U) /*! CORE1 - Core1 System Reset * 0b0..Reset not generated from Core1 system reset source. * 0b1..Reset generated from Core1 system reset source. */ #define SMC_SRS_CORE1(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_CORE1_SHIFT)) & SMC_SRS_CORE1_MASK) #define SMC_SRS_VBAT_MASK (0x1000000U) #define SMC_SRS_VBAT_SHIFT (24U) /*! VBAT - VBAT System Reset * 0b0..Reset not generated by VBAT system reset. * 0b1..Reset generated by VBAT system reset. */ #define SMC_SRS_VBAT(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_VBAT_SHIFT)) & SMC_SRS_VBAT_MASK) #define SMC_SRS_JTAG_MASK (0x10000000U) #define SMC_SRS_JTAG_SHIFT (28U) /*! JTAG - JTAG System Reset * 0b0..Reset not generated by JTAG system reset. * 0b1..Reset generated by JTAG system reset. */ #define SMC_SRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_JTAG_SHIFT)) & SMC_SRS_JTAG_MASK) #define SMC_SRS_TZWDG_MASK (0x20000000U) #define SMC_SRS_TZWDG_SHIFT (29U) /*! TZWDG - TrustZone WatchDog Reset * 0b0..Reset not generated by TrustZone WatchDog timeout. * 0b1..Reset generated by TrustZone WatchDog timeout. */ #define SMC_SRS_TZWDG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_TZWDG_SHIFT)) & SMC_SRS_TZWDG_MASK) #define SMC_SRS_SECVIO_MASK (0x40000000U) #define SMC_SRS_SECVIO_SHIFT (30U) /*! SECVIO - Security Violation Reset * 0b0..Reset not generated by security violation. * 0b1..Reset generated by security violation. */ #define SMC_SRS_SECVIO(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_SECVIO_SHIFT)) & SMC_SRS_SECVIO_MASK) #define SMC_SRS_TAMPER_MASK (0x80000000U) #define SMC_SRS_TAMPER_SHIFT (31U) /*! TAMPER - Tamper Reset * 0b0..Reset not generated by tamper detection. * 0b1..Reset generated by tamper detection. */ #define SMC_SRS_TAMPER(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_TAMPER_SHIFT)) & SMC_SRS_TAMPER_MASK) /*! @} */ /*! @name RPC - Reset Pin Control */ /*! @{ */ #define SMC_RPC_FILTCFG_MASK (0x1FU) #define SMC_RPC_FILTCFG_SHIFT (0U) /*! FILTCFG - Reset Filter Configuration */ #define SMC_RPC_FILTCFG(x) (((uint32_t)(((uint32_t)(x)) << SMC_RPC_FILTCFG_SHIFT)) & SMC_RPC_FILTCFG_MASK) #define SMC_RPC_FILTEN_MASK (0x100U) #define SMC_RPC_FILTEN_SHIFT (8U) /*! FILTEN - Filter Enable * 0b0..Slow clock reset pin filter disabled. * 0b1..Slow clock reset pin filter enabled in Run modes. */ #define SMC_RPC_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << SMC_RPC_FILTEN_SHIFT)) & SMC_RPC_FILTEN_MASK) /*! @} */ /*! @name SSRS - Sticky System Reset Status */ /*! @{ */ #define SMC_SSRS_WAKEUP_MASK (0x1U) #define SMC_SSRS_WAKEUP_SHIFT (0U) /*! WAKEUP - Wakeup Reset * 0b0..Reset not generated by wakeup from VLLS mode. * 0b1..Reset generated by wakeup from VLLS mode. */ #define SMC_SSRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_WAKEUP_SHIFT)) & SMC_SSRS_WAKEUP_MASK) #define SMC_SSRS_POR_MASK (0x2U) #define SMC_SSRS_POR_SHIFT (1U) /*! POR - POR Reset * 0b0..Reset not generated by POR. * 0b1..Reset generated by POR. */ #define SMC_SSRS_POR(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_POR_SHIFT)) & SMC_SSRS_POR_MASK) #define SMC_SSRS_LVD_MASK (0x4U) #define SMC_SSRS_LVD_SHIFT (2U) /*! LVD - LVD Reset * 0b0..Reset not generated by LVD. * 0b1..Reset generated by LVD. */ #define SMC_SSRS_LVD(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_LVD_SHIFT)) & SMC_SSRS_LVD_MASK) #define SMC_SSRS_HVD_MASK (0x8U) #define SMC_SSRS_HVD_SHIFT (3U) /*! HVD - HVD Reset * 0b0..Reset not generated by HVD. * 0b1..Reset generated by HVD. */ #define SMC_SSRS_HVD(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_HVD_SHIFT)) & SMC_SSRS_HVD_MASK) #define SMC_SSRS_WARM_MASK (0x10U) #define SMC_SSRS_WARM_SHIFT (4U) /*! WARM - Warm Reset * 0b0..Reset not generated by system reset source. * 0b1..Reset generated by system reset source. */ #define SMC_SSRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_WARM_SHIFT)) & SMC_SSRS_WARM_MASK) #define SMC_SSRS_FATAL_MASK (0x20U) #define SMC_SSRS_FATAL_SHIFT (5U) /*! FATAL - Fatal Reset * 0b0..Reset was not generated by a fatal reset source. * 0b1..Reset was generated by a fatal reset source. */ #define SMC_SSRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_FATAL_SHIFT)) & SMC_SSRS_FATAL_MASK) #define SMC_SSRS_PIN_MASK (0x100U) #define SMC_SSRS_PIN_SHIFT (8U) /*! PIN - Pin Reset * 0b0..Reset was not generated from the RESET_B pin. * 0b1..Reset was generated from the RESET_B pin. */ #define SMC_SSRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_PIN_SHIFT)) & SMC_SSRS_PIN_MASK) #define SMC_SSRS_MDM_MASK (0x200U) #define SMC_SSRS_MDM_SHIFT (9U) /*! MDM - MDM Reset * 0b0..Reset was not generated from the MDM reset request. * 0b1..Reset was generated from the MDM reset request. */ #define SMC_SSRS_MDM(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_MDM_SHIFT)) & SMC_SSRS_MDM_MASK) #define SMC_SSRS_RSTACK_MASK (0x400U) #define SMC_SSRS_RSTACK_SHIFT (10U) /*! RSTACK - Reset Timeout * 0b0..Reset not generated from Reset Controller Timeout. * 0b1..Reset generated from Reset Controller Timeout. */ #define SMC_SSRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_RSTACK_SHIFT)) & SMC_SSRS_RSTACK_MASK) #define SMC_SSRS_STOPACK_MASK (0x800U) #define SMC_SSRS_STOPACK_SHIFT (11U) /*! STOPACK - Stop Timeout Reset * 0b0..Reset not generated by Stop Controller Timeout. * 0b1..Reset generated by Stop Controller Timeout. */ #define SMC_SSRS_STOPACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_STOPACK_SHIFT)) & SMC_SSRS_STOPACK_MASK) #define SMC_SSRS_SCG_MASK (0x1000U) #define SMC_SSRS_SCG_SHIFT (12U) /*! SCG - SCG Reset * 0b0..Reset is not generated from an SCG loss of lock or loss of clock. * 0b1..Reset is generated from an SCG loss of lock or loss of clock. */ #define SMC_SSRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_SCG_SHIFT)) & SMC_SSRS_SCG_MASK) #define SMC_SSRS_WDOG_MASK (0x2000U) #define SMC_SSRS_WDOG_SHIFT (13U) /*! WDOG - Watchdog Reset * 0b0..Reset is not generated from the WatchDog timeout. * 0b1..Reset is generated from the WatchDog timeout. */ #define SMC_SSRS_WDOG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_WDOG_SHIFT)) & SMC_SSRS_WDOG_MASK) #define SMC_SSRS_SW_MASK (0x4000U) #define SMC_SSRS_SW_SHIFT (14U) /*! SW - Software Reset * 0b0..Reset not generated by software request from core. * 0b1..Reset generated by software request from core. */ #define SMC_SSRS_SW(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_SW_SHIFT)) & SMC_SSRS_SW_MASK) #define SMC_SSRS_LOCKUP_MASK (0x8000U) #define SMC_SSRS_LOCKUP_SHIFT (15U) /*! LOCKUP - Lockup Reset * 0b0..Reset not generated by core lockup. * 0b1..Reset generated by core lockup. */ #define SMC_SSRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_LOCKUP_SHIFT)) & SMC_SSRS_LOCKUP_MASK) #define SMC_SSRS_CORE0_MASK (0x10000U) #define SMC_SSRS_CORE0_SHIFT (16U) /*! CORE0 - Core0 Reset * 0b0..Reset not generated from Core0 reset source. * 0b1..Reset generated from Core0 reset source. */ #define SMC_SSRS_CORE0(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_CORE0_SHIFT)) & SMC_SSRS_CORE0_MASK) #define SMC_SSRS_CORE1_MASK (0x10000U) #define SMC_SSRS_CORE1_SHIFT (16U) /*! CORE1 - Core1 System Reset * 0b0..Reset not generated from Core1 system reset source. * 0b1..Reset generated from Core1 system reset source. */ #define SMC_SSRS_CORE1(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_CORE1_SHIFT)) & SMC_SSRS_CORE1_MASK) #define SMC_SSRS_VBAT_MASK (0x1000000U) #define SMC_SSRS_VBAT_SHIFT (24U) /*! VBAT - VBAT System Reset * 0b0..Reset not generated by VBAT system reset. * 0b1..Reset generated by VBAT system reset. */ #define SMC_SSRS_VBAT(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_VBAT_SHIFT)) & SMC_SSRS_VBAT_MASK) #define SMC_SSRS_JTAG_MASK (0x10000000U) #define SMC_SSRS_JTAG_SHIFT (28U) /*! JTAG - JTAG System Reset * 0b0..Reset not generated by JTAG system reset. * 0b1..Reset generated by JTAG system reset. */ #define SMC_SSRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_JTAG_SHIFT)) & SMC_SSRS_JTAG_MASK) #define SMC_SSRS_TZWDG_MASK (0x20000000U) #define SMC_SSRS_TZWDG_SHIFT (29U) /*! TZWDG - TrustZone WatchDog Reset * 0b0..Reset not generated by TrustZone WatchDog timeout. * 0b1..Reset generated by TrustZone WatchDog timeout. */ #define SMC_SSRS_TZWDG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_TZWDG_SHIFT)) & SMC_SSRS_TZWDG_MASK) #define SMC_SSRS_SECVIO_MASK (0x40000000U) #define SMC_SSRS_SECVIO_SHIFT (30U) /*! SECVIO - Security Violation Reset * 0b0..Reset not generated by Security Violation detection. * 0b1..Reset generated by Security Violation detection. */ #define SMC_SSRS_SECVIO(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_SECVIO_SHIFT)) & SMC_SSRS_SECVIO_MASK) #define SMC_SSRS_TAMPER_MASK (0x80000000U) #define SMC_SSRS_TAMPER_SHIFT (31U) /*! TAMPER - Tamper Reset * 0b0..Reset not generated by tamper detection. * 0b1..Reset generated by tamper detection. */ #define SMC_SSRS_TAMPER(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_TAMPER_SHIFT)) & SMC_SSRS_TAMPER_MASK) /*! @} */ /*! @name SRIE - System Reset Interrupt Enable */ /*! @{ */ #define SMC_SRIE_PIN_MASK (0x100U) #define SMC_SRIE_PIN_SHIFT (8U) /*! PIN - Pin Reset * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define SMC_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_PIN_SHIFT)) & SMC_SRIE_PIN_MASK) #define SMC_SRIE_MDM_MASK (0x200U) #define SMC_SRIE_MDM_SHIFT (9U) /*! MDM - MDM Reset * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define SMC_SRIE_MDM(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_MDM_SHIFT)) & SMC_SRIE_MDM_MASK) #define SMC_SRIE_STOPACK_MASK (0x800U) #define SMC_SRIE_STOPACK_SHIFT (11U) /*! STOPACK - Stop Timeout Reset * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define SMC_SRIE_STOPACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_STOPACK_SHIFT)) & SMC_SRIE_STOPACK_MASK) #define SMC_SRIE_WDOG_MASK (0x2000U) #define SMC_SRIE_WDOG_SHIFT (13U) /*! WDOG - Watchdog Reset * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define SMC_SRIE_WDOG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_WDOG_SHIFT)) & SMC_SRIE_WDOG_MASK) #define SMC_SRIE_SW_MASK (0x4000U) #define SMC_SRIE_SW_SHIFT (14U) /*! SW - Software Reset * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define SMC_SRIE_SW(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_SW_SHIFT)) & SMC_SRIE_SW_MASK) #define SMC_SRIE_LOCKUP_MASK (0x8000U) #define SMC_SRIE_LOCKUP_SHIFT (15U) /*! LOCKUP - Lockup Reset * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define SMC_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_LOCKUP_SHIFT)) & SMC_SRIE_LOCKUP_MASK) #define SMC_SRIE_VBAT_MASK (0x1000000U) #define SMC_SRIE_VBAT_SHIFT (24U) /*! VBAT - VBAT System Reset * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define SMC_SRIE_VBAT(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_VBAT_SHIFT)) & SMC_SRIE_VBAT_MASK) /*! @} */ /*! @name SRIF - System Reset Interrupt Flag */ /*! @{ */ #define SMC_SRIF_PIN_MASK (0x100U) #define SMC_SRIF_PIN_SHIFT (8U) /*! PIN - Pin Reset * 0b0..Reset source not pending. * 0b1..Reset source pending. */ #define SMC_SRIF_PIN(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_PIN_SHIFT)) & SMC_SRIF_PIN_MASK) #define SMC_SRIF_MDM_MASK (0x200U) #define SMC_SRIF_MDM_SHIFT (9U) /*! MDM - MDM Reset * 0b0..Reset source not pending. * 0b1..Reset source pending. */ #define SMC_SRIF_MDM(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_MDM_SHIFT)) & SMC_SRIF_MDM_MASK) #define SMC_SRIF_STOPACK_MASK (0x800U) #define SMC_SRIF_STOPACK_SHIFT (11U) /*! STOPACK - Stop Timeout Reset * 0b0..Reset source not pending. * 0b1..Reset source pending. */ #define SMC_SRIF_STOPACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_STOPACK_SHIFT)) & SMC_SRIF_STOPACK_MASK) #define SMC_SRIF_WDOG_MASK (0x2000U) #define SMC_SRIF_WDOG_SHIFT (13U) /*! WDOG - Watchdog Reset * 0b0..Reset source not pending. * 0b1..Reset source pending. */ #define SMC_SRIF_WDOG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_WDOG_SHIFT)) & SMC_SRIF_WDOG_MASK) #define SMC_SRIF_SW_MASK (0x4000U) #define SMC_SRIF_SW_SHIFT (14U) /*! SW - Software Reset * 0b0..Reset source not pending. * 0b1..Reset source pending. */ #define SMC_SRIF_SW(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_SW_SHIFT)) & SMC_SRIF_SW_MASK) #define SMC_SRIF_LOCKUP_MASK (0x8000U) #define SMC_SRIF_LOCKUP_SHIFT (15U) /*! LOCKUP - Lockup Reset * 0b0..Reset source not pending. * 0b1..Reset source pending. */ #define SMC_SRIF_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_LOCKUP_SHIFT)) & SMC_SRIF_LOCKUP_MASK) #define SMC_SRIF_VBAT_MASK (0x1000000U) #define SMC_SRIF_VBAT_SHIFT (24U) /*! VBAT - VBAT System Reset * 0b0..Reset source not pending. * 0b1..Reset source pending. */ #define SMC_SRIF_VBAT(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_VBAT_SHIFT)) & SMC_SRIF_VBAT_MASK) /*! @} */ /*! @name CSRE - Core Software Reset Enable */ /*! @{ */ #define SMC_CSRE_PIN_MASK (0x100U) #define SMC_CSRE_PIN_SHIFT (8U) /*! PIN - Pin Reset * 0b0..Core software reset disabled. * 0b1..Core software reset enabled. */ #define SMC_CSRE_PIN(x) (((uint32_t)(((uint32_t)(x)) << SMC_CSRE_PIN_SHIFT)) & SMC_CSRE_PIN_MASK) #define SMC_CSRE_MDM_MASK (0x200U) #define SMC_CSRE_MDM_SHIFT (9U) /*! MDM - MDM Reset * 0b0..Core software reset disabled. * 0b1..Core software reset enabled. */ #define SMC_CSRE_MDM(x) (((uint32_t)(((uint32_t)(x)) << SMC_CSRE_MDM_SHIFT)) & SMC_CSRE_MDM_MASK) #define SMC_CSRE_STOPACK_MASK (0x800U) #define SMC_CSRE_STOPACK_SHIFT (11U) /*! STOPACK - Stop Timeout Reset * 0b0..Core software reset disabled. * 0b1..Core software reset enabled. */ #define SMC_CSRE_STOPACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_CSRE_STOPACK_SHIFT)) & SMC_CSRE_STOPACK_MASK) #define SMC_CSRE_WDOG_MASK (0x2000U) #define SMC_CSRE_WDOG_SHIFT (13U) /*! WDOG - Watchdog Reset * 0b0..Core software reset disabled. * 0b1..Core software reset enabled. */ #define SMC_CSRE_WDOG(x) (((uint32_t)(((uint32_t)(x)) << SMC_CSRE_WDOG_SHIFT)) & SMC_CSRE_WDOG_MASK) #define SMC_CSRE_SW_MASK (0x4000U) #define SMC_CSRE_SW_SHIFT (14U) /*! SW - Software Reset * 0b0..Core software reset disabled. * 0b1..Core software reset enabled. */ #define SMC_CSRE_SW(x) (((uint32_t)(((uint32_t)(x)) << SMC_CSRE_SW_SHIFT)) & SMC_CSRE_SW_MASK) #define SMC_CSRE_LOCKUP_MASK (0x8000U) #define SMC_CSRE_LOCKUP_SHIFT (15U) /*! LOCKUP - Lockup Reset * 0b0..Core software reset disabled. * 0b1..Core software reset enabled. */ #define SMC_CSRE_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_CSRE_LOCKUP_SHIFT)) & SMC_CSRE_LOCKUP_MASK) #define SMC_CSRE_CORE0_MASK (0x10000U) #define SMC_CSRE_CORE0_SHIFT (16U) /*! CORE0 - Core0 Reset * 0b0..Core software reset disabled. * 0b1..Core software reset enabled. */ #define SMC_CSRE_CORE0(x) (((uint32_t)(((uint32_t)(x)) << SMC_CSRE_CORE0_SHIFT)) & SMC_CSRE_CORE0_MASK) #define SMC_CSRE_CORE1_MASK (0x10000U) #define SMC_CSRE_CORE1_SHIFT (16U) /*! CORE1 - Core1 System Reset * 0b0..Reset not generated from Core1 system reset source. * 0b1..Reset generated from Core1 system reset source. */ #define SMC_CSRE_CORE1(x) (((uint32_t)(((uint32_t)(x)) << SMC_CSRE_CORE1_SHIFT)) & SMC_CSRE_CORE1_MASK) #define SMC_CSRE_VBAT_MASK (0x1000000U) #define SMC_CSRE_VBAT_SHIFT (24U) /*! VBAT - VBAT System Reset * 0b0..Core software reset disabled. * 0b1..Core software reset enabled. */ #define SMC_CSRE_VBAT(x) (((uint32_t)(((uint32_t)(x)) << SMC_CSRE_VBAT_SHIFT)) & SMC_CSRE_VBAT_MASK) /*! @} */ /*! @name MR - Mode Register */ /*! @{ */ #define SMC_MR_BOOTCFG_MASK (0xFFFFFFFFU) #define SMC_MR_BOOTCFG_SHIFT (0U) /*! BOOTCFG - Boot Configuration */ #define SMC_MR_BOOTCFG(x) (((uint32_t)(((uint32_t)(x)) << SMC_MR_BOOTCFG_SHIFT)) & SMC_MR_BOOTCFG_MASK) /*! @} */ /*! @name FM - Force Mode Register */ /*! @{ */ #define SMC_FM_FORCECFG_MASK (0xFFFFFFFFU) #define SMC_FM_FORCECFG_SHIFT (0U) /*! FORCECFG - Boot Configuration * 0b00000000000000000000000000000000..No effect. * 0b00000000000000000000000000000001..Assert corresponding bit in Mode Register on next system reset. */ #define SMC_FM_FORCECFG(x) (((uint32_t)(((uint32_t)(x)) << SMC_FM_FORCECFG_SHIFT)) & SMC_FM_FORCECFG_MASK) /*! @} */ /*! * @} */ /* end of group SMC_Register_Masks */ /* SMC - Peripheral instance base addresses */ /** Peripheral MSMC0 base address */ #define MSMC0_BASE (0x410A4000u) /** Peripheral MSMC0 base pointer */ #define MSMC0 ((SMC_Type *)MSMC0_BASE) /** Peripheral MSMC1 base address */ #define MSMC1_BASE (0x40410000u) /** Peripheral MSMC1 base pointer */ #define MSMC1 ((SMC_Type *)MSMC1_BASE) /** Array initializer of SMC peripheral base addresses */ #define SMC_BASE_ADDRS { MSMC0_BASE, MSMC1_BASE } /** Array initializer of SMC peripheral base pointers */ #define SMC_BASE_PTRS { MSMC0, MSMC1 } /** Interrupt vectors for the SMC peripheral type */ #define SMC_IRQS { CMC0_IRQn, CMC1_IRQn } /* Backward compatibility */ #define BT0CFG_LPBOOT_MASK 0x1 #define BT0CFG_DUALBOOT_MASK 0x2 /*! * @} */ /* end of group SMC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SNVS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer * @{ */ /** SNVS - Register Layout Typedef */ typedef struct { __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ __IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */ __IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */ __IO uint32_t HPSICR; /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */ __IO uint32_t HPSVCR; /**< SNVS_HP Security Violation Control Register, offset: 0x10 */ __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ __IO uint32_t HPSVSR; /**< SNVS_HP Security Violation Status Register, offset: 0x18 */ __IO uint32_t HPHACIVR; /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */ __I uint32_t HPHACR; /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */ __IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */ __IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */ __IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */ __IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */ __IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */ __IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */ __IO uint32_t LPMKCR; /**< SNVS_LP Master Key Control Register, offset: 0x3C */ __IO uint32_t LPSVCR; /**< SNVS_LP Security Violation Control Register, offset: 0x40 */ uint8_t RESERVED_0[4]; __IO uint32_t LPTDCR; /**< SNVS_LP Tamper Detectors Configuration Register, offset: 0x48 */ __IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */ __IO uint32_t LPSRTCMR; /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */ __IO uint32_t LPSRTCLR; /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */ __IO uint32_t LPTAR; /**< SNVS_LP Time Alarm Register, offset: 0x58 */ __I uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */ __I uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */ __IO uint32_t LPPGDR; /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */ __IO uint32_t LPGPR0_LEGACY_ALIAS; /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */ __IO uint32_t LPZMKR[8]; /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */ uint8_t RESERVED_2[96]; __IO uint32_t LPGPR[8]; /**< SNVS_LP General Purpose Registers 0 .. 7, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_3[2776]; __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ } SNVS_Type; /* ---------------------------------------------------------------------------- -- SNVS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SNVS_Register_Masks SNVS Register Masks * @{ */ /*! @name HPLR - SNVS_HP Lock Register */ /*! @{ */ #define SNVS_HPLR_ZMK_WSL_MASK (0x1U) #define SNVS_HPLR_ZMK_WSL_SHIFT (0U) /*! ZMK_WSL * 0b0..Write access is allowed * 0b1..Write access is not allowed */ #define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK) #define SNVS_HPLR_ZMK_RSL_MASK (0x2U) #define SNVS_HPLR_ZMK_RSL_SHIFT (1U) /*! ZMK_RSL * 0b0..Read access is allowed (only in software Programming mode) * 0b1..Read access is not allowed */ #define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK) #define SNVS_HPLR_SRTC_SL_MASK (0x4U) #define SNVS_HPLR_SRTC_SL_SHIFT (2U) /*! SRTC_SL * 0b0..Write access is allowed * 0b1..Write access is not allowed */ #define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK) #define SNVS_HPLR_LPCALB_SL_MASK (0x8U) #define SNVS_HPLR_LPCALB_SL_SHIFT (3U) /*! LPCALB_SL * 0b0..Write access is allowed * 0b1..Write access is not allowed */ #define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK) #define SNVS_HPLR_MC_SL_MASK (0x10U) #define SNVS_HPLR_MC_SL_SHIFT (4U) /*! MC_SL * 0b0..Write access (increment) is allowed * 0b1..Write access (increment) is not allowed */ #define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK) #define SNVS_HPLR_GPR_SL_MASK (0x20U) #define SNVS_HPLR_GPR_SL_SHIFT (5U) /*! GPR_SL * 0b0..Write access is allowed * 0b1..Write access is not allowed */ #define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK) #define SNVS_HPLR_LPSVCR_SL_MASK (0x40U) #define SNVS_HPLR_LPSVCR_SL_SHIFT (6U) /*! LPSVCR_SL * 0b0..Write access is allowed * 0b1..Write access is not allowed */ #define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK) #define SNVS_HPLR_LPTDCR_SL_MASK (0x100U) #define SNVS_HPLR_LPTDCR_SL_SHIFT (8U) /*! LPTDCR_SL * 0b0..Write access is allowed * 0b1..Write access is not allowed */ #define SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK) #define SNVS_HPLR_MKS_SL_MASK (0x200U) #define SNVS_HPLR_MKS_SL_SHIFT (9U) /*! MKS_SL * 0b0..Write access is allowed * 0b1..Write access is not allowed */ #define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK) #define SNVS_HPLR_HPSVCR_L_MASK (0x10000U) #define SNVS_HPLR_HPSVCR_L_SHIFT (16U) /*! HPSVCR_L * 0b0..Write access is allowed * 0b1..Write access is not allowed */ #define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK) #define SNVS_HPLR_HPSICR_L_MASK (0x20000U) #define SNVS_HPLR_HPSICR_L_SHIFT (17U) /*! HPSICR_L * 0b0..Write access is allowed * 0b1..Write access is not allowed */ #define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK) #define SNVS_HPLR_HAC_L_MASK (0x40000U) #define SNVS_HPLR_HAC_L_SHIFT (18U) /*! HAC_L * 0b0..Write access is allowed * 0b1..Write access is not allowed */ #define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK) /*! @} */ /*! @name HPCOMR - SNVS_HP Command Register */ /*! @{ */ #define SNVS_HPCOMR_SSM_ST_MASK (0x1U) #define SNVS_HPCOMR_SSM_ST_SHIFT (0U) #define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK) #define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U) #define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U) /*! SSM_ST_DIS * 0b0..Secure to Trusted State transition is enabled * 0b1..Secure to Trusted State transition is disabled */ #define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK) #define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U) #define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U) /*! SSM_SFNS_DIS * 0b0..Soft Fail to Non-Secure State transition is enabled * 0b1..Soft Fail to Non-Secure State transition is disabled */ #define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK) #define SNVS_HPCOMR_LP_SWR_MASK (0x10U) #define SNVS_HPCOMR_LP_SWR_SHIFT (4U) /*! LP_SWR * 0b0..No Action * 0b1..Reset LP section */ #define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK) #define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U) #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U) /*! LP_SWR_DIS * 0b0..LP software reset is enabled * 0b1..LP software reset is disabled */ #define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK) #define SNVS_HPCOMR_SW_SV_MASK (0x100U) #define SNVS_HPCOMR_SW_SV_SHIFT (8U) #define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK) #define SNVS_HPCOMR_SW_FSV_MASK (0x200U) #define SNVS_HPCOMR_SW_FSV_SHIFT (9U) #define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK) #define SNVS_HPCOMR_SW_LPSV_MASK (0x400U) #define SNVS_HPCOMR_SW_LPSV_SHIFT (10U) #define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK) #define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U) #define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U) /*! PROG_ZMK * 0b0..No Action * 0b1..Activate hardware key programming mechanism */ #define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK) #define SNVS_HPCOMR_MKS_EN_MASK (0x2000U) #define SNVS_HPCOMR_MKS_EN_SHIFT (13U) /*! MKS_EN * 0b0..OTP master key is selected as an SNVS master key * 0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR */ #define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK) #define SNVS_HPCOMR_HAC_EN_MASK (0x10000U) #define SNVS_HPCOMR_HAC_EN_SHIFT (16U) /*! HAC_EN * 0b0..High Assurance Counter is disabled * 0b1..High Assurance Counter is enabled */ #define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK) #define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U) #define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U) /*! HAC_LOAD * 0b0..No Action * 0b1..Load the HAC */ #define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK) #define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U) #define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U) /*! HAC_CLEAR * 0b0..No Action * 0b1..Clear the HAC */ #define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK) #define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U) #define SNVS_HPCOMR_HAC_STOP_SHIFT (19U) #define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK) #define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) #define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) #define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) /*! @} */ /*! @name HPCR - SNVS_HP Control Register */ /*! @{ */ #define SNVS_HPCR_RTC_EN_MASK (0x1U) #define SNVS_HPCR_RTC_EN_SHIFT (0U) /*! RTC_EN * 0b0..RTC is disabled * 0b1..RTC is enabled */ #define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) #define SNVS_HPCR_HPTA_EN_MASK (0x2U) #define SNVS_HPCR_HPTA_EN_SHIFT (1U) /*! HPTA_EN * 0b0..HP Time Alarm Interrupt is disabled * 0b1..HP Time Alarm Interrupt is enabled */ #define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) #define SNVS_HPCR_DIS_PI_MASK (0x4U) #define SNVS_HPCR_DIS_PI_SHIFT (2U) /*! DIS_PI * 0b0..Periodic interrupt will trigger a functional interrupt * 0b1..Disable periodic interrupt in the function interrupt */ #define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK) #define SNVS_HPCR_PI_EN_MASK (0x8U) #define SNVS_HPCR_PI_EN_SHIFT (3U) /*! PI_EN * 0b0..HP Periodic Interrupt is disabled * 0b1..HP Periodic Interrupt is enabled */ #define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) #define SNVS_HPCR_PI_FREQ_MASK (0xF0U) #define SNVS_HPCR_PI_FREQ_SHIFT (4U) /*! PI_FREQ * 0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt * 0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt * 0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt * 0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt * 0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt * 0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt * 0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt * 0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt * 0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt * 0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt * 0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt * 0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt * 0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt * 0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt * 0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt * 0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt */ #define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK) #define SNVS_HPCR_HPCALB_EN_MASK (0x100U) #define SNVS_HPCR_HPCALB_EN_SHIFT (8U) /*! HPCALB_EN * 0b0..HP Timer calibration disabled * 0b1..HP Timer calibration enabled */ #define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) #define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) #define SNVS_HPCR_HPCALB_VAL_SHIFT (10U) /*! HPCALB_VAL * 0b00000..+0 counts per each 32768 ticks of the counter * 0b00001..+1 counts per each 32768 ticks of the counter * 0b00010..+2 counts per each 32768 ticks of the counter * 0b01111..+15 counts per each 32768 ticks of the counter * 0b10000..-16 counts per each 32768 ticks of the counter * 0b10001..-15 counts per each 32768 ticks of the counter * 0b11110..-2 counts per each 32768 ticks of the counter * 0b11111..-1 counts per each 32768 ticks of the counter */ #define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) #define SNVS_HPCR_HP_TS_MASK (0x10000U) #define SNVS_HPCR_HP_TS_SHIFT (16U) /*! HP_TS * 0b0..No Action * 0b1..Synchronize the HP Time Counter to the LP Time Counter */ #define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK) #define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U) #define SNVS_HPCR_BTN_CONFIG_SHIFT (24U) #define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK) #define SNVS_HPCR_BTN_MASK_MASK (0x8000000U) #define SNVS_HPCR_BTN_MASK_SHIFT (27U) #define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) /*! @} */ /*! @name HPSICR - SNVS_HP Security Interrupt Control Register */ /*! @{ */ #define SNVS_HPSICR_SV0_EN_MASK (0x1U) #define SNVS_HPSICR_SV0_EN_SHIFT (0U) /*! SV0_EN * 0b0..CAAM Security Violation Interrupt is Disabled * 0b1..CAAM Security Violation Interrupt is Enabled */ #define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK) #define SNVS_HPSICR_SV1_EN_MASK (0x2U) #define SNVS_HPSICR_SV1_EN_SHIFT (1U) /*! SV1_EN * 0b0..JTAG Active Interrupt is Disabled * 0b1..JTAG Active Interrupt is Enabled */ #define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK) #define SNVS_HPSICR_SV2_EN_MASK (0x4U) #define SNVS_HPSICR_SV2_EN_SHIFT (2U) /*! SV2_EN * 0b0..Watchdog 2 Reset Interrupt is Disabled * 0b1..Watchdog 2 Reset Interrupt is Enabled */ #define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK) #define SNVS_HPSICR_SV3_EN_MASK (0x8U) #define SNVS_HPSICR_SV3_EN_SHIFT (3U) /*! SV3_EN * 0b0..unused Interrupt is Disabled * 0b1..unused Interrupt is Enabled */ #define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK) #define SNVS_HPSICR_SV4_EN_MASK (0x10U) #define SNVS_HPSICR_SV4_EN_SHIFT (4U) /*! SV4_EN * 0b0..Internal Boot Interrupt is Disabled * 0b1..Internal Boot Interrupt is Enabled */ #define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK) #define SNVS_HPSICR_SV5_EN_MASK (0x20U) #define SNVS_HPSICR_SV5_EN_SHIFT (5U) /*! SV5_EN * 0b0..External Tamper-detection Pad Interrupt is Disabled * 0b1..External Tamper-detection Pad Interrupt is Enabled */ #define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK) #define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U) #define SNVS_HPSICR_LPSVI_EN_SHIFT (31U) /*! LPSVI_EN * 0b0..LP Security Violation Interrupt is Disabled * 0b1..LP Security Violation Interrupt is Enabled */ #define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK) /*! @} */ /*! @name HPSVCR - SNVS_HP Security Violation Control Register */ /*! @{ */ #define SNVS_HPSVCR_SV0_CFG_MASK (0x1U) #define SNVS_HPSVCR_SV0_CFG_SHIFT (0U) /*! SV0_CFG * 0b0..CAAM Security Violation is a non-fatal violation * 0b1..CAAM Security Violation is a fatal violation */ #define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK) #define SNVS_HPSVCR_SV1_CFG_MASK (0x2U) #define SNVS_HPSVCR_SV1_CFG_SHIFT (1U) /*! SV1_CFG * 0b0..JTAG Active is a non-fatal violation * 0b1..JTAG Active is a fatal violation */ #define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK) #define SNVS_HPSVCR_SV2_CFG_MASK (0x4U) #define SNVS_HPSVCR_SV2_CFG_SHIFT (2U) /*! SV2_CFG * 0b0..Watchdog 2 Reset is a non-fatal violation * 0b1..Watchdog 2 Reset is a fatal violation */ #define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK) #define SNVS_HPSVCR_SV3_CFG_MASK (0x8U) #define SNVS_HPSVCR_SV3_CFG_SHIFT (3U) /*! SV3_CFG * 0b0..unused is a non-fatal violation * 0b1..unused is a fatal violation */ #define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK) #define SNVS_HPSVCR_SV4_CFG_MASK (0x10U) #define SNVS_HPSVCR_SV4_CFG_SHIFT (4U) /*! SV4_CFG * 0b0..Internal Boot is a non-fatal violation * 0b1..Internal Boot is a fatal violation */ #define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK) #define SNVS_HPSVCR_SV5_CFG_MASK (0x60U) #define SNVS_HPSVCR_SV5_CFG_SHIFT (5U) /*! SV5_CFG * 0b00..External Tamper-detection Pad is disabled * 0b01..External Tamper-detection Pad is a non-fatal violation * 0b1x..External Tamper-detection Pad is a fatal violation */ #define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK) #define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U) #define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U) /*! LPSV_CFG * 0b00..LP security violation is disabled * 0b01..LP security violation is a non-fatal violation * 0b1x..LP security violation is a fatal violation */ #define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK) /*! @} */ /*! @name HPSR - SNVS_HP Status Register */ /*! @{ */ #define SNVS_HPSR_HPTA_MASK (0x1U) #define SNVS_HPSR_HPTA_SHIFT (0U) /*! HPTA * 0b0..No time alarm interrupt occurred. * 0b1..A time alarm interrupt occurred. */ #define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK) #define SNVS_HPSR_PI_MASK (0x2U) #define SNVS_HPSR_PI_SHIFT (1U) /*! PI * 0b0..No periodic interrupt occurred. * 0b1..A periodic interrupt occurred. */ #define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK) #define SNVS_HPSR_LPDIS_MASK (0x10U) #define SNVS_HPSR_LPDIS_SHIFT (4U) #define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK) #define SNVS_HPSR_BTN_MASK (0x40U) #define SNVS_HPSR_BTN_SHIFT (6U) #define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK) #define SNVS_HPSR_BI_MASK (0x80U) #define SNVS_HPSR_BI_SHIFT (7U) #define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK) #define SNVS_HPSR_SSM_STATE_MASK (0xF00U) #define SNVS_HPSR_SSM_STATE_SHIFT (8U) /*! SSM_STATE * 0b0000..Init * 0b0001..Hard Fail * 0b0011..Soft Fail * 0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) * 0b1001..Check * 0b1011..Non-Secure * 0b1101..Trusted * 0b1111..Secure */ #define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK) #define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U) #define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U) /*! SECURITY_CONFIG * 0b0000, 0b1000..FAB configuration * 0b0001, 0b0010, 0b0011..OPEN configuration * 0b1010, 0b1001, 0b1011..CLOSED configuration * 0bx1xx..FIELD RETURN configuration */ #define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK) #define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U) #define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U) #define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK) #define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U) #define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U) /*! OTPMK_ZERO * 0b0..The OTPMK is not zero. * 0b1..The OTPMK is zero. */ #define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK) #define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U) #define SNVS_HPSR_ZMK_ZERO_SHIFT (31U) /*! ZMK_ZERO * 0b0..The ZMK is not zero. * 0b1..The ZMK is zero. */ #define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK) /*! @} */ /*! @name HPSVSR - SNVS_HP Security Violation Status Register */ /*! @{ */ #define SNVS_HPSVSR_SV0_MASK (0x1U) #define SNVS_HPSVSR_SV0_SHIFT (0U) /*! SV0 * 0b0..No CAAM Security Violation security violation was detected. * 0b1..CAAM Security Violation security violation was detected. */ #define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK) #define SNVS_HPSVSR_SV1_MASK (0x2U) #define SNVS_HPSVSR_SV1_SHIFT (1U) /*! SV1 * 0b0..No JTAG Active security violation was detected. * 0b1..JTAG Active security violation was detected. */ #define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK) #define SNVS_HPSVSR_SV2_MASK (0x4U) #define SNVS_HPSVSR_SV2_SHIFT (2U) /*! SV2 * 0b0..No Watchdog 2 Reset security violation was detected. * 0b1..Watchdog 2 Reset security violation was detected. */ #define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK) #define SNVS_HPSVSR_SV3_MASK (0x8U) #define SNVS_HPSVSR_SV3_SHIFT (3U) /*! SV3 * 0b0..No unused security violation was detected. * 0b1..unused security violation was detected. */ #define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK) #define SNVS_HPSVSR_SV4_MASK (0x10U) #define SNVS_HPSVSR_SV4_SHIFT (4U) /*! SV4 * 0b0..No Internal Boot security violation was detected. * 0b1..Internal Boot security violation was detected. */ #define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK) #define SNVS_HPSVSR_SV5_MASK (0x20U) #define SNVS_HPSVSR_SV5_SHIFT (5U) /*! SV5 * 0b0..No External Tamper-detection Pad security violation was detected. * 0b1..External Tamper-detection Pad security violation was detected. */ #define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK) #define SNVS_HPSVSR_SW_SV_MASK (0x2000U) #define SNVS_HPSVSR_SW_SV_SHIFT (13U) #define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK) #define SNVS_HPSVSR_SW_FSV_MASK (0x4000U) #define SNVS_HPSVSR_SW_FSV_SHIFT (14U) #define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK) #define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U) #define SNVS_HPSVSR_SW_LPSV_SHIFT (15U) #define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK) #define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U) #define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U) #define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK) #define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U) #define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U) /*! ZMK_ECC_FAIL * 0b0..ZMK ECC Failure was not detected. * 0b1..ZMK ECC Failure was detected. */ #define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK) #define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U) #define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U) #define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK) /*! @} */ /*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */ /*! @{ */ #define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU) #define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U) #define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK) /*! @} */ /*! @name HPHACR - SNVS_HP High Assurance Counter Register */ /*! @{ */ #define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU) #define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U) #define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK) /*! @} */ /*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */ /*! @{ */ #define SNVS_HPRTCMR_RTC_MASK (0x7FFFU) #define SNVS_HPRTCMR_RTC_SHIFT (0U) #define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) /*! @} */ /*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */ /*! @{ */ #define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) #define SNVS_HPRTCLR_RTC_SHIFT (0U) #define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) /*! @} */ /*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ /*! @{ */ #define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU) #define SNVS_HPTAMR_HPTA_MS_SHIFT (0U) #define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK) /*! @} */ /*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ /*! @{ */ #define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU) #define SNVS_HPTALR_HPTA_LS_SHIFT (0U) #define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK) /*! @} */ /*! @name LPLR - SNVS_LP Lock Register */ /*! @{ */ #define SNVS_LPLR_ZMK_WHL_MASK (0x1U) #define SNVS_LPLR_ZMK_WHL_SHIFT (0U) /*! ZMK_WHL * 0b0..Write access is allowed. * 0b1..Write access is not allowed. */ #define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK) #define SNVS_LPLR_ZMK_RHL_MASK (0x2U) #define SNVS_LPLR_ZMK_RHL_SHIFT (1U) /*! ZMK_RHL * 0b0..Read access is allowed (only in software programming mode). * 0b1..Read access is not allowed. */ #define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK) #define SNVS_LPLR_SRTC_HL_MASK (0x4U) #define SNVS_LPLR_SRTC_HL_SHIFT (2U) /*! SRTC_HL * 0b0..Write access is allowed. * 0b1..Write access is not allowed. */ #define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK) #define SNVS_LPLR_LPCALB_HL_MASK (0x8U) #define SNVS_LPLR_LPCALB_HL_SHIFT (3U) /*! LPCALB_HL * 0b0..Write access is allowed. * 0b1..Write access is not allowed. */ #define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK) #define SNVS_LPLR_MC_HL_MASK (0x10U) #define SNVS_LPLR_MC_HL_SHIFT (4U) /*! MC_HL * 0b0..Write access (increment) is allowed. * 0b1..Write access (increment) is not allowed. */ #define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) #define SNVS_LPLR_GPR_HL_MASK (0x20U) #define SNVS_LPLR_GPR_HL_SHIFT (5U) /*! GPR_HL * 0b0..Write access is allowed. * 0b1..Write access is not allowed. */ #define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) #define SNVS_LPLR_LPSVCR_HL_MASK (0x40U) #define SNVS_LPLR_LPSVCR_HL_SHIFT (6U) /*! LPSVCR_HL * 0b0..Write access is allowed. * 0b1..Write access is not allowed. */ #define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK) #define SNVS_LPLR_LPTDCR_HL_MASK (0x100U) #define SNVS_LPLR_LPTDCR_HL_SHIFT (8U) /*! LPTDCR_HL * 0b0..Write access is allowed. * 0b1..Write access is not allowed. */ #define SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK) #define SNVS_LPLR_MKS_HL_MASK (0x200U) #define SNVS_LPLR_MKS_HL_SHIFT (9U) /*! MKS_HL * 0b0..Write access is allowed. * 0b1..Write access is not allowed. */ #define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK) /*! @} */ /*! @name LPCR - SNVS_LP Control Register */ /*! @{ */ #define SNVS_LPCR_SRTC_ENV_MASK (0x1U) #define SNVS_LPCR_SRTC_ENV_SHIFT (0U) /*! SRTC_ENV * 0b0..SRTC is disabled or invalid. * 0b1..SRTC is enabled and valid. */ #define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK) #define SNVS_LPCR_LPTA_EN_MASK (0x2U) #define SNVS_LPCR_LPTA_EN_SHIFT (1U) /*! LPTA_EN * 0b0..LP time alarm interrupt is disabled. * 0b1..LP time alarm interrupt is enabled. */ #define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK) #define SNVS_LPCR_MC_ENV_MASK (0x4U) #define SNVS_LPCR_MC_ENV_SHIFT (2U) /*! MC_ENV * 0b0..MC is disabled or invalid. * 0b1..MC is enabled and valid. */ #define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) #define SNVS_LPCR_LPWUI_EN_MASK (0x8U) #define SNVS_LPCR_LPWUI_EN_SHIFT (3U) #define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK) #define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U) #define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U) /*! SRTC_INV_EN * 0b0..SRTC stays valid in the case of security violation. * 0b1..SRTC is invalidated in the case of security violation. */ #define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK) #define SNVS_LPCR_DP_EN_MASK (0x20U) #define SNVS_LPCR_DP_EN_SHIFT (5U) /*! DP_EN * 0b0..Smart PMIC enabled. * 0b1..Dumb PMIC enabled. */ #define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK) #define SNVS_LPCR_TOP_MASK (0x40U) #define SNVS_LPCR_TOP_SHIFT (6U) /*! TOP * 0b0..Leave system power on. * 0b1..Turn off system power. */ #define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK) #define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U) #define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U) #define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK) #define SNVS_LPCR_LPCALB_EN_MASK (0x100U) #define SNVS_LPCR_LPCALB_EN_SHIFT (8U) /*! LPCALB_EN * 0b0..SRTC Time calibration is disabled. * 0b1..SRTC Time calibration is enabled. */ #define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK) #define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U) #define SNVS_LPCR_LPCALB_VAL_SHIFT (10U) /*! LPCALB_VAL * 0b00000..+0 counts per each 32768 ticks of the counter clock * 0b00001..+1 counts per each 32768 ticks of the counter clock * 0b00010..+2 counts per each 32768 ticks of the counter clock * 0b01111..+15 counts per each 32768 ticks of the counter clock * 0b10000..-16 counts per each 32768 ticks of the counter clock * 0b10001..-15 counts per each 32768 ticks of the counter clock * 0b11110..-2 counts per each 32768 ticks of the counter clock * 0b11111..-1 counts per each 32768 ticks of the counter clock */ #define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK) #define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U) #define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U) #define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK) #define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U) #define SNVS_LPCR_DEBOUNCE_SHIFT (18U) #define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK) #define SNVS_LPCR_ON_TIME_MASK (0x300000U) #define SNVS_LPCR_ON_TIME_SHIFT (20U) #define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK) #define SNVS_LPCR_PK_EN_MASK (0x400000U) #define SNVS_LPCR_PK_EN_SHIFT (22U) #define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK) #define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U) #define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U) #define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK) #define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U) #define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U) #define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK) /*! @} */ /*! @name LPMKCR - SNVS_LP Master Key Control Register */ /*! @{ */ #define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U) #define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U) /*! MASTER_KEY_SEL * 0b0x..Select one time programmable master key. * 0b10..Select zeroizable master key when MKS_EN bit is set . * 0b11..Select combined master key when MKS_EN bit is set . */ #define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK) #define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U) #define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U) /*! ZMK_HWP * 0b0..ZMK is in the software programming mode. * 0b1..ZMK is in the hardware programming mode. */ #define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK) #define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U) #define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U) /*! ZMK_VAL * 0b0..ZMK is not valid. * 0b1..ZMK is valid. */ #define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK) #define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U) #define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U) /*! ZMK_ECC_EN * 0b0..ZMK ECC check is disabled. * 0b1..ZMK ECC check is enabled. */ #define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK) #define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U) #define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U) #define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK) /*! @} */ /*! @name LPSVCR - SNVS_LP Security Violation Control Register */ /*! @{ */ #define SNVS_LPSVCR_SV0_EN_MASK (0x1U) #define SNVS_LPSVCR_SV0_EN_SHIFT (0U) /*! SV0_EN * 0b0..CAAM Security Violation is disabled in the LP domain. * 0b1..CAAM Security Violation is enabled in the LP domain. */ #define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK) #define SNVS_LPSVCR_SV1_EN_MASK (0x2U) #define SNVS_LPSVCR_SV1_EN_SHIFT (1U) /*! SV1_EN * 0b0..JTAG Active is disabled in the LP domain. * 0b1..JTAG Active is enabled in the LP domain. */ #define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK) #define SNVS_LPSVCR_SV2_EN_MASK (0x4U) #define SNVS_LPSVCR_SV2_EN_SHIFT (2U) /*! SV2_EN * 0b0..Watchdog 2 Reset is disabled in the LP domain. * 0b1..Watchdog 2 Reset is enabled in the LP domain. */ #define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK) #define SNVS_LPSVCR_SV3_EN_MASK (0x8U) #define SNVS_LPSVCR_SV3_EN_SHIFT (3U) /*! SV3_EN * 0b0..unused is disabled in the LP domain. * 0b1..unused is enabled in the LP domain. */ #define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK) #define SNVS_LPSVCR_SV4_EN_MASK (0x10U) #define SNVS_LPSVCR_SV4_EN_SHIFT (4U) /*! SV4_EN * 0b0..Internal Boot is disabled in the LP domain. * 0b1..Internal Boot is enabled in the LP domain. */ #define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK) #define SNVS_LPSVCR_SV5_EN_MASK (0x20U) #define SNVS_LPSVCR_SV5_EN_SHIFT (5U) /*! SV5_EN * 0b0..External Tamper-detection Pad is disabled in the LP domain. * 0b1..External Tamper-detection Pad is enabled in the LP domain. */ #define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK) /*! @} */ /*! @name LPTDCR - SNVS_LP Tamper Detectors Configuration Register */ /*! @{ */ #define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U) #define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U) /*! SRTCR_EN * 0b0..SRTC rollover is disabled. * 0b1..SRTC rollover is enabled. */ #define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK) #define SNVS_LPTDCR_MCR_EN_MASK (0x4U) #define SNVS_LPTDCR_MCR_EN_SHIFT (2U) /*! MCR_EN * 0b0..MC rollover is disabled. * 0b1..MC rollover is enabled. */ #define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK) #define SNVS_LPTDCR_ET1_EN_MASK (0x200U) #define SNVS_LPTDCR_ET1_EN_SHIFT (9U) /*! ET1_EN * 0b0..External tamper 1 is disabled. * 0b1..External tamper 1 is enabled. */ #define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK) #define SNVS_LPTDCR_ET1P_MASK (0x800U) #define SNVS_LPTDCR_ET1P_SHIFT (11U) /*! ET1P * 0b0..External tamper 1 is active low. * 0b1..External tamper 1 is active high. */ #define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK) #define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U) #define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U) #define SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK) #define SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U) #define SNVS_LPTDCR_POR_OBSERV_SHIFT (15U) #define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK) #define SNVS_LPTDCR_OSCB_MASK (0x10000000U) #define SNVS_LPTDCR_OSCB_SHIFT (28U) /*! OSCB * 0b0..Normal SRTC clock oscillator not bypassed. * 0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source. */ #define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK) /*! @} */ /*! @name LPSR - SNVS_LP Status Register */ /*! @{ */ #define SNVS_LPSR_LPTA_MASK (0x1U) #define SNVS_LPSR_LPTA_SHIFT (0U) /*! LPTA * 0b0..No time alarm interrupt occurred. * 0b1..A time alarm interrupt occurred. */ #define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK) #define SNVS_LPSR_SRTCR_MASK (0x2U) #define SNVS_LPSR_SRTCR_SHIFT (1U) /*! SRTCR * 0b0..SRTC has not reached its maximum value. * 0b1..SRTC has reached its maximum value. */ #define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK) #define SNVS_LPSR_MCR_MASK (0x4U) #define SNVS_LPSR_MCR_SHIFT (2U) /*! MCR * 0b0..MC has not reached its maximum value. * 0b1..MC has reached its maximum value. */ #define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) #define SNVS_LPSR_PGD_MASK (0x8U) #define SNVS_LPSR_PGD_SHIFT (3U) #define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK) #define SNVS_LPSR_ET1D_MASK (0x200U) #define SNVS_LPSR_ET1D_SHIFT (9U) /*! ET1D * 0b0..External tampering 1 not detected. * 0b1..External tampering 1 detected. */ #define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK) #define SNVS_LPSR_ESVD_MASK (0x10000U) #define SNVS_LPSR_ESVD_SHIFT (16U) /*! ESVD * 0b0..No external security violation. * 0b1..External security violation is detected. */ #define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK) #define SNVS_LPSR_EO_MASK (0x20000U) #define SNVS_LPSR_EO_SHIFT (17U) /*! EO * 0b0..Emergency off was not detected. * 0b1..Emergency off was detected. */ #define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK) #define SNVS_LPSR_SPO_MASK (0x40000U) #define SNVS_LPSR_SPO_SHIFT (18U) /*! SPO * 0b0..Set Power Off was not detected. * 0b1..Set Power Off was detected. */ #define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK) #define SNVS_LPSR_LPNS_MASK (0x40000000U) #define SNVS_LPSR_LPNS_SHIFT (30U) /*! LPNS * 0b0..LP section was not programmed in the non-secure state. * 0b1..LP section was programmed in the non-secure state. */ #define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK) #define SNVS_LPSR_LPS_MASK (0x80000000U) #define SNVS_LPSR_LPS_SHIFT (31U) /*! LPS * 0b0..LP section was not programmed in secure or trusted state. * 0b1..LP section was programmed in secure or trusted state. */ #define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK) /*! @} */ /*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */ /*! @{ */ #define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU) #define SNVS_LPSRTCMR_SRTC_SHIFT (0U) #define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK) /*! @} */ /*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */ /*! @{ */ #define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU) #define SNVS_LPSRTCLR_SRTC_SHIFT (0U) #define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK) /*! @} */ /*! @name LPTAR - SNVS_LP Time Alarm Register */ /*! @{ */ #define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU) #define SNVS_LPTAR_LPTA_SHIFT (0U) #define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK) /*! @} */ /*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ /*! @{ */ #define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) #define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) #define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) #define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) #define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) #define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) /*! @} */ /*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ /*! @{ */ #define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) #define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) #define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) /*! @} */ /*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */ /*! @{ */ #define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU) #define SNVS_LPPGDR_PGD_SHIFT (0U) #define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK) /*! @} */ /*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */ /*! @{ */ #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU) #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U) #define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK) /*! @} */ /*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */ /*! @{ */ #define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU) #define SNVS_LPZMKR_ZMK_SHIFT (0U) #define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK) /*! @} */ /* The count of SNVS_LPZMKR */ #define SNVS_LPZMKR_COUNT (8U) /*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */ /*! @{ */ #define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU) #define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U) #define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK) /*! @} */ /* The count of SNVS_LPGPR_ALIAS */ #define SNVS_LPGPR_ALIAS_COUNT (4U) /*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 7 */ /*! @{ */ #define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) #define SNVS_LPGPR_GPR_SHIFT (0U) #define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) /*! @} */ /* The count of SNVS_LPGPR */ #define SNVS_LPGPR_COUNT (8U) /*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ /*! @{ */ #define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) #define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) #define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) #define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U) #define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U) #define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK) #define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) #define SNVS_HPVIDR1_IP_ID_SHIFT (16U) #define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) /*! @} */ /*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ /*! @{ */ #define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) #define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) #define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) #define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U) #define SNVS_HPVIDR2_ECO_REV_SHIFT (8U) #define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK) #define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U) #define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U) #define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK) #define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) #define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) #define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) /*! @} */ /*! * @} */ /* end of group SNVS_Register_Masks */ /* SNVS - Peripheral instance base addresses */ /** Peripheral SNVS base address */ #define SNVS_BASE (0x41070000u) /** Peripheral SNVS base pointer */ #define SNVS ((SNVS_Type *)SNVS_BASE) /** Array initializer of SNVS peripheral base addresses */ #define SNVS_BASE_ADDRS { SNVS_BASE } /** Array initializer of SNVS peripheral base pointers */ #define SNVS_BASE_PTRS { SNVS } /** Interrupt vectors for the SNVS peripheral type */ #define SNVS_IRQS { SNVS_IRQn } /* Backward compatibility */ #define SNVS_SSM_STATE_INIT (0U) #define SNVS_SSM_STATE_HARD_FAIL (1U) #define SNVS_SSM_STATE_SOFT_FAIL (3U) #define SNVS_SSM_STATE_INIT_INT (8U) #define SNVS_SSM_STATE_CHECK (9U) #define SNVS_SSM_STATE_NON_SECURE (11U) #define SNVS_SSM_STATE_TRUSTED (13U) #define SNVS_SSM_STATE_SECURE (15U) /*! * @} */ /* end of group SNVS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- TPM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer * @{ */ /** TPM - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __IO uint32_t GLOBAL; /**< TPM Global Register, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t SC; /**< Status and Control, offset: 0x10 */ __IO uint32_t CNT; /**< Counter, offset: 0x14 */ __IO uint32_t MOD; /**< Modulo, offset: 0x18 */ __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x1C */ struct { /* offset: 0x20, array step: 0x8 */ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0x20, array step: 0x8 */ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x24, array step: 0x8 */ } CONTROLS[6]; uint8_t RESERVED_1[20]; __IO uint32_t COMBINE; /**< Combine Channel Register, offset: 0x64 */ uint8_t RESERVED_2[4]; __IO uint32_t TRIG; /**< Channel Trigger, offset: 0x6C */ __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */ uint8_t RESERVED_3[4]; __IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */ uint8_t RESERVED_4[4]; __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ } TPM_Type; /* ---------------------------------------------------------------------------- -- TPM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup TPM_Register_Masks TPM Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define TPM_VERID_FEATURE_MASK (0xFFFFU) #define TPM_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Identification Number * 0b0000000000000001..Standard feature set. * 0b0000000000000011..Standard feature set with Filter and Combine registers implemented. * 0b0000000000000111..Standard feature set with Filter, Combine and Quadrature registers implemented. */ #define TPM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_FEATURE_SHIFT)) & TPM_VERID_FEATURE_MASK) #define TPM_VERID_MINOR_MASK (0xFF0000U) #define TPM_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define TPM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MINOR_SHIFT)) & TPM_VERID_MINOR_MASK) #define TPM_VERID_MAJOR_MASK (0xFF000000U) #define TPM_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define TPM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MAJOR_SHIFT)) & TPM_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define TPM_PARAM_CHAN_MASK (0xFFU) #define TPM_PARAM_CHAN_SHIFT (0U) /*! CHAN - Channel Count */ #define TPM_PARAM_CHAN(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_CHAN_SHIFT)) & TPM_PARAM_CHAN_MASK) #define TPM_PARAM_TRIG_MASK (0xFF00U) #define TPM_PARAM_TRIG_SHIFT (8U) /*! TRIG - Trigger Count */ #define TPM_PARAM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_TRIG_SHIFT)) & TPM_PARAM_TRIG_MASK) #define TPM_PARAM_WIDTH_MASK (0xFF0000U) #define TPM_PARAM_WIDTH_SHIFT (16U) /*! WIDTH - Counter Width */ #define TPM_PARAM_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_WIDTH_SHIFT)) & TPM_PARAM_WIDTH_MASK) /*! @} */ /*! @name GLOBAL - TPM Global Register */ /*! @{ */ #define TPM_GLOBAL_RST_MASK (0x2U) #define TPM_GLOBAL_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Module is not reset. * 0b1..Module is reset. */ #define TPM_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_RST_SHIFT)) & TPM_GLOBAL_RST_MASK) /*! @} */ /*! @name SC - Status and Control */ /*! @{ */ #define TPM_SC_PS_MASK (0x7U) #define TPM_SC_PS_SHIFT (0U) /*! PS - Prescale Factor Selection * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 4 * 0b011..Divide by 8 * 0b100..Divide by 16 * 0b101..Divide by 32 * 0b110..Divide by 64 * 0b111..Divide by 128 */ #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK) #define TPM_SC_CMOD_MASK (0x18U) #define TPM_SC_CMOD_SHIFT (3U) /*! CMOD - Clock Mode Selection * 0b00..TPM counter is disabled * 0b01..TPM counter increments on every TPM counter clock * 0b10..TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock * 0b11..TPM counter increments on rising edge of the selected external input trigger. */ #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK) #define TPM_SC_CPWMS_MASK (0x20U) #define TPM_SC_CPWMS_SHIFT (5U) /*! CPWMS - Center-Aligned PWM Select * 0b0..TPM counter operates in up counting mode. * 0b1..TPM counter operates in up-down counting mode. */ #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK) #define TPM_SC_TOIE_MASK (0x40U) #define TPM_SC_TOIE_SHIFT (6U) /*! TOIE - Timer Overflow Interrupt Enable * 0b0..Disable TOF interrupts. Use software polling or DMA request. * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one. */ #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK) #define TPM_SC_TOF_MASK (0x80U) #define TPM_SC_TOF_SHIFT (7U) /*! TOF - Timer Overflow Flag * 0b0..TPM counter has not overflowed. * 0b1..TPM counter has overflowed. */ #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK) #define TPM_SC_DMA_MASK (0x100U) #define TPM_SC_DMA_SHIFT (8U) /*! DMA - DMA Enable * 0b0..Disables DMA transfers. * 0b1..Enables DMA transfers. */ #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK) /*! @} */ /*! @name CNT - Counter */ /*! @{ */ #define TPM_CNT_COUNT_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */ #define TPM_CNT_COUNT_SHIFT (0U) /*! COUNT - Counter value */ #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */ /*! @} */ /*! @name MOD - Modulo */ /*! @{ */ #define TPM_MOD_MOD_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */ #define TPM_MOD_MOD_SHIFT (0U) /*! MOD - Modulo value */ #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */ /*! @} */ /*! @name STATUS - Capture and Compare Status */ /*! @{ */ #define TPM_STATUS_CH0F_MASK (0x1U) #define TPM_STATUS_CH0F_SHIFT (0U) /*! CH0F - Channel 0 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK) #define TPM_STATUS_CH1F_MASK (0x2U) #define TPM_STATUS_CH1F_SHIFT (1U) /*! CH1F - Channel 1 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK) #define TPM_STATUS_CH2F_MASK (0x4U) #define TPM_STATUS_CH2F_SHIFT (2U) /*! CH2F - Channel 2 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK) #define TPM_STATUS_CH3F_MASK (0x8U) #define TPM_STATUS_CH3F_SHIFT (3U) /*! CH3F - Channel 3 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK) #define TPM_STATUS_CH4F_MASK (0x10U) #define TPM_STATUS_CH4F_SHIFT (4U) /*! CH4F - Channel 4 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK) #define TPM_STATUS_CH5F_MASK (0x20U) #define TPM_STATUS_CH5F_SHIFT (5U) /*! CH5F - Channel 5 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK) #define TPM_STATUS_TOF_MASK (0x100U) #define TPM_STATUS_TOF_SHIFT (8U) /*! TOF - Timer Overflow Flag * 0b0..TPM counter has not overflowed. * 0b1..TPM counter has overflowed. */ #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK) /*! @} */ /*! @name CnSC - Channel (n) Status and Control */ /*! @{ */ #define TPM_CnSC_DMA_MASK (0x1U) #define TPM_CnSC_DMA_SHIFT (0U) /*! DMA - DMA Enable * 0b0..Disable DMA transfers. * 0b1..Enable DMA transfers. */ #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK) #define TPM_CnSC_ELSA_MASK (0x4U) #define TPM_CnSC_ELSA_SHIFT (2U) /*! ELSA - Edge or Level Select */ #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK) #define TPM_CnSC_ELSB_MASK (0x8U) #define TPM_CnSC_ELSB_SHIFT (3U) /*! ELSB - Edge or Level Select */ #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK) #define TPM_CnSC_MSA_MASK (0x10U) #define TPM_CnSC_MSA_SHIFT (4U) /*! MSA - Channel Mode Select */ #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK) #define TPM_CnSC_MSB_MASK (0x20U) #define TPM_CnSC_MSB_SHIFT (5U) /*! MSB - Channel Mode Select */ #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK) #define TPM_CnSC_CHIE_MASK (0x40U) #define TPM_CnSC_CHIE_SHIFT (6U) /*! CHIE - Channel Interrupt Enable * 0b0..Disable channel interrupts. * 0b1..Enable channel interrupts. */ #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK) #define TPM_CnSC_CHF_MASK (0x80U) #define TPM_CnSC_CHF_SHIFT (7U) /*! CHF - Channel Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK) /*! @} */ /* The count of TPM_CnSC */ #define TPM_CnSC_COUNT (6U) /*! @name CnV - Channel (n) Value */ /*! @{ */ #define TPM_CnV_VAL_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */ #define TPM_CnV_VAL_SHIFT (0U) /*! VAL - Channel Value */ #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */ /*! @} */ /* The count of TPM_CnV */ #define TPM_CnV_COUNT (6U) /*! @name COMBINE - Combine Channel Register */ /*! @{ */ #define TPM_COMBINE_COMBINE0_MASK (0x1U) #define TPM_COMBINE_COMBINE0_SHIFT (0U) /*! COMBINE0 - Combine Channels 0 and 1 * 0b0..Channels 0 and 1 are independent. * 0b1..Channels 0 and 1 are combined. */ #define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK) #define TPM_COMBINE_COMSWAP0_MASK (0x2U) #define TPM_COMBINE_COMSWAP0_SHIFT (1U) /*! COMSWAP0 - Combine Channel 0 and 1 Swap * 0b0..Even channel is used for input capture and 1st compare. * 0b1..Odd channel is used for input capture and 1st compare. */ #define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK) #define TPM_COMBINE_COMBINE1_MASK (0x100U) #define TPM_COMBINE_COMBINE1_SHIFT (8U) /*! COMBINE1 - Combine Channels 2 and 3 * 0b0..Channels 2 and 3 are independent. * 0b1..Channels 2 and 3 are combined. */ #define TPM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK) #define TPM_COMBINE_COMSWAP1_MASK (0x200U) #define TPM_COMBINE_COMSWAP1_SHIFT (9U) /*! COMSWAP1 - Combine Channels 2 and 3 Swap * 0b0..Even channel is used for input capture and 1st compare. * 0b1..Odd channel is used for input capture and 1st compare. */ #define TPM_COMBINE_COMSWAP1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK) #define TPM_COMBINE_COMBINE2_MASK (0x10000U) #define TPM_COMBINE_COMBINE2_SHIFT (16U) /*! COMBINE2 - Combine Channels 4 and 5 * 0b0..Channels 4 and 5 are independent. * 0b1..Channels 4 and 5 are combined. */ #define TPM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE2_SHIFT)) & TPM_COMBINE_COMBINE2_MASK) #define TPM_COMBINE_COMSWAP2_MASK (0x20000U) #define TPM_COMBINE_COMSWAP2_SHIFT (17U) /*! COMSWAP2 - Combine Channels 4 and 5 Swap * 0b0..Even channel is used for input capture and 1st compare. * 0b1..Odd channel is used for input capture and 1st compare. */ #define TPM_COMBINE_COMSWAP2(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP2_SHIFT)) & TPM_COMBINE_COMSWAP2_MASK) /*! @} */ /*! @name TRIG - Channel Trigger */ /*! @{ */ #define TPM_TRIG_TRIG0_MASK (0x1U) #define TPM_TRIG_TRIG0_SHIFT (0U) /*! TRIG0 - Channel 0 Trigger * 0b0..No effect. * 0b1..Configures trigger input 0 to be used by channel 0. */ #define TPM_TRIG_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG0_SHIFT)) & TPM_TRIG_TRIG0_MASK) #define TPM_TRIG_TRIG1_MASK (0x2U) #define TPM_TRIG_TRIG1_SHIFT (1U) /*! TRIG1 - Channel 1 Trigger * 0b0..No effect. * 0b1..Configures trigger input 1 to be used by channel 1. */ #define TPM_TRIG_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG1_SHIFT)) & TPM_TRIG_TRIG1_MASK) #define TPM_TRIG_TRIG2_MASK (0x4U) #define TPM_TRIG_TRIG2_SHIFT (2U) /*! TRIG2 - Channel 2 Trigger * 0b0..No effect. * 0b1..Configures trigger input 0 to be used by channel 2. */ #define TPM_TRIG_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG2_SHIFT)) & TPM_TRIG_TRIG2_MASK) #define TPM_TRIG_TRIG3_MASK (0x8U) #define TPM_TRIG_TRIG3_SHIFT (3U) /*! TRIG3 - Channel 3 Trigger * 0b0..No effect. * 0b1..Configures trigger input 1 to be used by channel 3. */ #define TPM_TRIG_TRIG3(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG3_SHIFT)) & TPM_TRIG_TRIG3_MASK) #define TPM_TRIG_TRIG4_MASK (0x10U) #define TPM_TRIG_TRIG4_SHIFT (4U) /*! TRIG4 - Channel 4 Trigger * 0b0..No effect. * 0b1..Configures trigger input 0 to be used by channel 4. */ #define TPM_TRIG_TRIG4(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG4_SHIFT)) & TPM_TRIG_TRIG4_MASK) #define TPM_TRIG_TRIG5_MASK (0x20U) #define TPM_TRIG_TRIG5_SHIFT (5U) /*! TRIG5 - Channel 5 Trigger * 0b0..No effect. * 0b1..Configures trigger input 1 to be used by channel 5. */ #define TPM_TRIG_TRIG5(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG5_SHIFT)) & TPM_TRIG_TRIG5_MASK) /*! @} */ /*! @name POL - Channel Polarity */ /*! @{ */ #define TPM_POL_POL0_MASK (0x1U) #define TPM_POL_POL0_SHIFT (0U) /*! POL0 - Channel 0 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK) #define TPM_POL_POL1_MASK (0x2U) #define TPM_POL_POL1_SHIFT (1U) /*! POL1 - Channel 1 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK) #define TPM_POL_POL2_MASK (0x4U) #define TPM_POL_POL2_SHIFT (2U) /*! POL2 - Channel 2 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK) #define TPM_POL_POL3_MASK (0x8U) #define TPM_POL_POL3_SHIFT (3U) /*! POL3 - Channel 3 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK) #define TPM_POL_POL4_MASK (0x10U) #define TPM_POL_POL4_SHIFT (4U) /*! POL4 - Channel 4 Polarity * 0b0..The channel polarity is active high * 0b1..The channel polarity is active low. */ #define TPM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK) #define TPM_POL_POL5_MASK (0x20U) #define TPM_POL_POL5_SHIFT (5U) /*! POL5 - Channel 5 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define TPM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK) /*! @} */ /*! @name FILTER - Filter Control */ /*! @{ */ #define TPM_FILTER_CH0FVAL_MASK (0xFU) #define TPM_FILTER_CH0FVAL_SHIFT (0U) /*! CH0FVAL - Channel 0 Filter Value */ #define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK) #define TPM_FILTER_CH1FVAL_MASK (0xF0U) #define TPM_FILTER_CH1FVAL_SHIFT (4U) /*! CH1FVAL - Channel 1 Filter Value */ #define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK) #define TPM_FILTER_CH2FVAL_MASK (0xF00U) #define TPM_FILTER_CH2FVAL_SHIFT (8U) /*! CH2FVAL - Channel 2 Filter Value */ #define TPM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK) #define TPM_FILTER_CH3FVAL_MASK (0xF000U) #define TPM_FILTER_CH3FVAL_SHIFT (12U) /*! CH3FVAL - Channel 3 Filter Value */ #define TPM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK) #define TPM_FILTER_CH4FVAL_MASK (0xF0000U) #define TPM_FILTER_CH4FVAL_SHIFT (16U) /*! CH4FVAL - Channel 4 Filter Value */ #define TPM_FILTER_CH4FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH4FVAL_SHIFT)) & TPM_FILTER_CH4FVAL_MASK) #define TPM_FILTER_CH5FVAL_MASK (0xF00000U) #define TPM_FILTER_CH5FVAL_SHIFT (20U) /*! CH5FVAL - Channel 5 Filter Value */ #define TPM_FILTER_CH5FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH5FVAL_SHIFT)) & TPM_FILTER_CH5FVAL_MASK) /*! @} */ /*! @name QDCTRL - Quadrature Decoder Control and Status */ /*! @{ */ #define TPM_QDCTRL_QUADEN_MASK (0x1U) #define TPM_QDCTRL_QUADEN_SHIFT (0U) /*! QUADEN - QUADEN * 0b0..Quadrature decoder mode is disabled. * 0b1..Quadrature decoder mode is enabled. */ #define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK) #define TPM_QDCTRL_TOFDIR_MASK (0x2U) #define TPM_QDCTRL_TOFDIR_SHIFT (1U) /*! TOFDIR - TOFDIR * 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes * from its minimum value (zero) to its maximum value (MOD register). * 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from * its maximum value (MOD register) to its minimum value (zero). */ #define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK) #define TPM_QDCTRL_QUADIR_MASK (0x4U) #define TPM_QDCTRL_QUADIR_SHIFT (2U) /*! QUADIR - Counter Direction in Quadrature Decode Mode * 0b0..Counter direction is decreasing (counter decrement). * 0b1..Counter direction is increasing (counter increment). */ #define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK) #define TPM_QDCTRL_QUADMODE_MASK (0x8U) #define TPM_QDCTRL_QUADMODE_SHIFT (3U) /*! QUADMODE - Quadrature Decoder Mode * 0b0..Phase encoding mode. * 0b1..Count and direction encoding mode. */ #define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK) /*! @} */ /*! @name CONF - Configuration */ /*! @{ */ #define TPM_CONF_DOZEEN_MASK (0x20U) #define TPM_CONF_DOZEEN_SHIFT (5U) /*! DOZEEN - Doze Enable * 0b0..Internal TPM counter continues in Doze mode. * 0b1..Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture * events are ignored, and PWM outputs are forced to their default state. */ #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK) #define TPM_CONF_DBGMODE_MASK (0xC0U) #define TPM_CONF_DBGMODE_SHIFT (6U) /*! DBGMODE - Debug Mode * 0b00..TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events * are ignored, and PWM outputs are forced to their default state. * 0b11..TPM counter continues in debug mode. */ #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK) #define TPM_CONF_GTBSYNC_MASK (0x100U) #define TPM_CONF_GTBSYNC_SHIFT (8U) /*! GTBSYNC - Global Time Base Synchronization * 0b0..Global timebase synchronization disabled. * 0b1..Global timebase synchronization enabled. */ #define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK) #define TPM_CONF_GTBEEN_MASK (0x200U) #define TPM_CONF_GTBEEN_SHIFT (9U) /*! GTBEEN - Global time base enable * 0b0..All channels use the internally generated TPM counter as their timebase * 0b1..All channels use an externally generated global timebase as their timebase */ #define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK) #define TPM_CONF_CSOT_MASK (0x10000U) #define TPM_CONF_CSOT_SHIFT (16U) /*! CSOT - Counter Start on Trigger * 0b0..TPM counter starts to increment immediately, once it is enabled. * 0b1..TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, * after it has been enabled or after it has stopped due to overflow. */ #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK) #define TPM_CONF_CSOO_MASK (0x20000U) #define TPM_CONF_CSOO_SHIFT (17U) /*! CSOO - Counter Stop On Overflow * 0b0..TPM counter continues incrementing or decrementing after overflow * 0b1..TPM counter stops incrementing or decrementing after overflow. */ #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK) #define TPM_CONF_CROT_MASK (0x40000U) #define TPM_CONF_CROT_SHIFT (18U) /*! CROT - Counter Reload On Trigger * 0b0..Counter is not reloaded due to a rising edge on the selected input trigger * 0b1..Counter is reloaded when a rising edge is detected on the selected input trigger */ #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK) #define TPM_CONF_CPOT_MASK (0x80000U) #define TPM_CONF_CPOT_SHIFT (19U) /*! CPOT - Counter Pause On Trigger */ #define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK) #define TPM_CONF_TRGPOL_MASK (0x400000U) #define TPM_CONF_TRGPOL_SHIFT (22U) /*! TRGPOL - Trigger Polarity * 0b0..Trigger is active high. * 0b1..Trigger is active low. */ #define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK) #define TPM_CONF_TRGSRC_MASK (0x800000U) #define TPM_CONF_TRGSRC_SHIFT (23U) /*! TRGSRC - Trigger Source * 0b0..Trigger source selected by TRGSEL is external. * 0b1..Trigger source selected by TRGSEL is internal (channel pin input capture). */ #define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK) #define TPM_CONF_TRGSEL_MASK (0x3000000U) #define TPM_CONF_TRGSEL_SHIFT (24U) /*! TRGSEL - Trigger Select * 0b01..Channel 0 pin input capture * 0b10..Channel 1 pin input capture * 0b11..Channel 0 or Channel 1 pin input capture */ #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK) /*! @} */ /*! * @} */ /* end of group TPM_Register_Masks */ /* TPM - Peripheral instance base addresses */ /** Peripheral TPM0 base address */ #define TPM0_BASE (0x41030000u) /** Peripheral TPM0 base pointer */ #define TPM0 ((TPM_Type *)TPM0_BASE) /** Peripheral TPM1 base address */ #define TPM1_BASE (0x41031000u) /** Peripheral TPM1 base pointer */ #define TPM1 ((TPM_Type *)TPM1_BASE) /** Peripheral TPM2 base address */ #define TPM2_BASE (0x410A8000u) /** Peripheral TPM2 base pointer */ #define TPM2 ((TPM_Type *)TPM2_BASE) /** Peripheral TPM3 base address */ #define TPM3_BASE (0x410A9000u) /** Peripheral TPM3 base pointer */ #define TPM3 ((TPM_Type *)TPM3_BASE) /** Peripheral TPM4 base address */ #define TPM4_BASE (0x40250000u) /** Peripheral TPM4 base pointer */ #define TPM4 ((TPM_Type *)TPM4_BASE) /** Peripheral TPM5 base address */ #define TPM5_BASE (0x40260000u) /** Peripheral TPM5 base pointer */ #define TPM5 ((TPM_Type *)TPM5_BASE) /** Peripheral TPM6 base address */ #define TPM6_BASE (0x40A10000u) /** Peripheral TPM6 base pointer */ #define TPM6 ((TPM_Type *)TPM6_BASE) /** Peripheral TPM7 base address */ #define TPM7_BASE (0x40A20000u) /** Peripheral TPM7 base pointer */ #define TPM7 ((TPM_Type *)TPM7_BASE) /** Array initializer of TPM peripheral base addresses */ #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE, TPM7_BASE } /** Array initializer of TPM peripheral base pointers */ #define TPM_BASE_PTRS { TPM0, TPM1, TPM2, TPM3, TPM4, TPM5, TPM6, TPM7 } /** Interrupt vectors for the TPM peripheral type */ #define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } /*! * @} */ /* end of group TPM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- TRGMUX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup TRGMUX_Peripheral_Access_Layer TRGMUX Peripheral Access Layer * @{ */ /** TRGMUX - Register Layout Typedef */ typedef struct { __IO uint32_t TRGCFG[25]; /**< TRGMUX DMAMUX1_A Register..TRGMUX FLEXIO0 Register, array offset: 0x0, array step: 0x4 */ } TRGMUX_Type; /* ---------------------------------------------------------------------------- -- TRGMUX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup TRGMUX_Register_Masks TRGMUX Register Masks * @{ */ /*! @name TRGCFG - TRGMUX DMAMUX1_A Register..TRGMUX FLEXIO0 Register */ /*! @{ */ #define TRGMUX_TRGCFG_SEL0_MASK (0x7FU) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ #define TRGMUX_TRGCFG_SEL0_SHIFT (0U) /*! SEL0 - Trigger MUX Input 0 Source Select */ #define TRGMUX_TRGCFG_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL0_SHIFT)) & TRGMUX_TRGCFG_SEL0_MASK) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ #define TRGMUX_TRGCFG_SEL1_MASK (0x7F00U) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ #define TRGMUX_TRGCFG_SEL1_SHIFT (8U) /*! SEL1 - Trigger MUX Input 1 Source Select */ #define TRGMUX_TRGCFG_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL1_SHIFT)) & TRGMUX_TRGCFG_SEL1_MASK) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ #define TRGMUX_TRGCFG_SEL2_MASK (0x7F0000U) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ #define TRGMUX_TRGCFG_SEL2_SHIFT (16U) /*! SEL2 - Trigger MUX Input 2 Source Select */ #define TRGMUX_TRGCFG_SEL2(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL2_SHIFT)) & TRGMUX_TRGCFG_SEL2_MASK) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ #define TRGMUX_TRGCFG_SEL3_MASK (0x7F000000U) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ #define TRGMUX_TRGCFG_SEL3_SHIFT (24U) /*! SEL3 - Trigger MUX Input 3 Source Select */ #define TRGMUX_TRGCFG_SEL3(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL3_SHIFT)) & TRGMUX_TRGCFG_SEL3_MASK) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ #define TRGMUX_TRGCFG_LK_MASK (0x80000000U) #define TRGMUX_TRGCFG_LK_SHIFT (31U) /*! LK - TRGMUX register lock. * 0b0..Register can be written. * 0b1..Register cannot be written until the next system Reset. */ #define TRGMUX_TRGCFG_LK(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_LK_SHIFT)) & TRGMUX_TRGCFG_LK_MASK) /*! @} */ /* The count of TRGMUX_TRGCFG */ #define TRGMUX_TRGCFG_COUNT (25U) /*! * @} */ /* end of group TRGMUX_Register_Masks */ /* TRGMUX - Peripheral instance base addresses */ /** Peripheral TRGMUX0 base address */ #define TRGMUX0_BASE (0x41024000u) /** Peripheral TRGMUX0 base pointer */ #define TRGMUX0 ((TRGMUX_Type *)TRGMUX0_BASE) /** Peripheral TRGMUX1 base address */ #define TRGMUX1_BASE (0x403A0000u) /** Peripheral TRGMUX1 base pointer */ #define TRGMUX1 ((TRGMUX_Type *)TRGMUX1_BASE) /** Array initializer of TRGMUX peripheral base addresses */ #define TRGMUX_BASE_ADDRS { TRGMUX0_BASE, TRGMUX1_BASE } /** Array initializer of TRGMUX peripheral base pointers */ #define TRGMUX_BASE_PTRS { TRGMUX0, TRGMUX1 } /*! * @} */ /* end of group TRGMUX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- TRNG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer * @{ */ /** TRNG - Register Layout Typedef */ typedef struct { __IO uint32_t MCTL; /**< Miscellaneous Control Register, offset: 0x0 */ __IO uint32_t SCMISC; /**< Statistical Check Miscellaneous Register, offset: 0x4 */ __IO uint32_t PKRRNG; /**< Poker Range Register, offset: 0x8 */ union { /* offset: 0xC */ __IO uint32_t PKRMAX; /**< Poker Maximum Limit Register, offset: 0xC */ __I uint32_t PKRSQ; /**< Poker Square Calculation Result Register, offset: 0xC */ }; __IO uint32_t SDCTL; /**< Seed Control Register, offset: 0x10 */ union { /* offset: 0x14 */ __IO uint32_t SBLIM; /**< Sparse Bit Limit Register, offset: 0x14 */ __I uint32_t TOTSAM; /**< Total Samples Register, offset: 0x14 */ }; __IO uint32_t FRQMIN; /**< Frequency Count Minimum Limit Register, offset: 0x18 */ union { /* offset: 0x1C */ __I uint32_t FRQCNT; /**< Frequency Count Register, offset: 0x1C */ __IO uint32_t FRQMAX; /**< Frequency Count Maximum Limit Register, offset: 0x1C */ }; union { /* offset: 0x20 */ __I uint32_t SCMC; /**< Statistical Check Monobit Count Register, offset: 0x20 */ __IO uint32_t SCML; /**< Statistical Check Monobit Limit Register, offset: 0x20 */ }; union { /* offset: 0x24 */ __I uint32_t SCR1C; /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */ __IO uint32_t SCR1L; /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */ }; union { /* offset: 0x28 */ __I uint32_t SCR2C; /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */ __IO uint32_t SCR2L; /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */ }; union { /* offset: 0x2C */ __I uint32_t SCR3C; /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */ __IO uint32_t SCR3L; /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */ }; union { /* offset: 0x30 */ __I uint32_t SCR4C; /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */ __IO uint32_t SCR4L; /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */ }; union { /* offset: 0x34 */ __I uint32_t SCR5C; /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */ __IO uint32_t SCR5L; /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */ }; union { /* offset: 0x38 */ __I uint32_t SCR6PC; /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */ __IO uint32_t SCR6PL; /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */ }; __I uint32_t STATUS; /**< Status Register, offset: 0x3C */ __I uint32_t ENT[16]; /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */ __I uint32_t PKRCNT10; /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */ __I uint32_t PKRCNT32; /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */ __I uint32_t PKRCNT54; /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */ __I uint32_t PKRCNT76; /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */ __I uint32_t PKRCNT98; /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */ __I uint32_t PKRCNTBA; /**< Statistical Check Poker Count B and A Register, offset: 0x94 */ __I uint32_t PKRCNTDC; /**< Statistical Check Poker Count D and C Register, offset: 0x98 */ __I uint32_t PKRCNTFE; /**< Statistical Check Poker Count F and E Register, offset: 0x9C */ __IO uint32_t SEC_CFG; /**< Security Configuration Register, offset: 0xA0 */ __IO uint32_t INT_CTRL; /**< Interrupt Control Register, offset: 0xA4 */ __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ uint8_t RESERVED_0[64]; __I uint32_t VID1; /**< Version ID Register (MS), offset: 0xF0 */ __I uint32_t VID2; /**< Version ID Register (LS), offset: 0xF4 */ } TRNG_Type; /* ---------------------------------------------------------------------------- -- TRNG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup TRNG_Register_Masks TRNG Register Masks * @{ */ /*! @name MCTL - Miscellaneous Control Register */ /*! @{ */ #define TRNG_MCTL_SAMP_MODE_MASK (0x3U) #define TRNG_MCTL_SAMP_MODE_SHIFT (0U) /*! SAMP_MODE * 0b00..use Von Neumann data into both Entropy shifter and Statistical Checker * 0b01..use raw data into both Entropy shifter and Statistical Checker * 0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker * 0b11..undefined/reserved. */ #define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK) #define TRNG_MCTL_OSC_DIV_MASK (0xCU) #define TRNG_MCTL_OSC_DIV_SHIFT (2U) /*! OSC_DIV * 0b00..use ring oscillator with no divide * 0b01..use ring oscillator divided-by-2 * 0b10..use ring oscillator divided-by-4 * 0b11..use ring oscillator divided-by-8 */ #define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK) #define TRNG_MCTL_UNUSED4_MASK (0x10U) #define TRNG_MCTL_UNUSED4_SHIFT (4U) #define TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK) #define TRNG_MCTL_TRNG_ACC_MASK (0x20U) #define TRNG_MCTL_TRNG_ACC_SHIFT (5U) #define TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK) #define TRNG_MCTL_RST_DEF_MASK (0x40U) #define TRNG_MCTL_RST_DEF_SHIFT (6U) #define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK) #define TRNG_MCTL_FOR_SCLK_MASK (0x80U) #define TRNG_MCTL_FOR_SCLK_SHIFT (7U) #define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK) #define TRNG_MCTL_FCT_FAIL_MASK (0x100U) #define TRNG_MCTL_FCT_FAIL_SHIFT (8U) #define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK) #define TRNG_MCTL_FCT_VAL_MASK (0x200U) #define TRNG_MCTL_FCT_VAL_SHIFT (9U) #define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK) #define TRNG_MCTL_ENT_VAL_MASK (0x400U) #define TRNG_MCTL_ENT_VAL_SHIFT (10U) #define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK) #define TRNG_MCTL_TST_OUT_MASK (0x800U) #define TRNG_MCTL_TST_OUT_SHIFT (11U) #define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK) #define TRNG_MCTL_ERR_MASK (0x1000U) #define TRNG_MCTL_ERR_SHIFT (12U) #define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK) #define TRNG_MCTL_TSTOP_OK_MASK (0x2000U) #define TRNG_MCTL_TSTOP_OK_SHIFT (13U) #define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK) #define TRNG_MCTL_PRGM_MASK (0x10000U) #define TRNG_MCTL_PRGM_SHIFT (16U) #define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK) /*! @} */ /*! @name SCMISC - Statistical Check Miscellaneous Register */ /*! @{ */ #define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU) #define TRNG_SCMISC_LRUN_MAX_SHIFT (0U) #define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK) #define TRNG_SCMISC_RTY_CT_MASK (0xF0000U) #define TRNG_SCMISC_RTY_CT_SHIFT (16U) #define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK) /*! @} */ /*! @name PKRRNG - Poker Range Register */ /*! @{ */ #define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU) #define TRNG_PKRRNG_PKR_RNG_SHIFT (0U) #define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK) /*! @} */ /*! @name PKRMAX - Poker Maximum Limit Register */ /*! @{ */ #define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU) #define TRNG_PKRMAX_PKR_MAX_SHIFT (0U) /*! PKR_MAX - Poker Maximum Limit. */ #define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK) /*! @} */ /*! @name PKRSQ - Poker Square Calculation Result Register */ /*! @{ */ #define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU) #define TRNG_PKRSQ_PKR_SQ_SHIFT (0U) /*! PKR_SQ - Poker Square Calculation Result. */ #define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK) /*! @} */ /*! @name SDCTL - Seed Control Register */ /*! @{ */ #define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU) #define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U) #define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK) #define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U) #define TRNG_SDCTL_ENT_DLY_SHIFT (16U) #define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK) /*! @} */ /*! @name SBLIM - Sparse Bit Limit Register */ /*! @{ */ #define TRNG_SBLIM_SB_LIM_MASK (0x3FFU) #define TRNG_SBLIM_SB_LIM_SHIFT (0U) #define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK) /*! @} */ /*! @name TOTSAM - Total Samples Register */ /*! @{ */ #define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU) #define TRNG_TOTSAM_TOT_SAM_SHIFT (0U) #define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK) /*! @} */ /*! @name FRQMIN - Frequency Count Minimum Limit Register */ /*! @{ */ #define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU) #define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U) #define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK) /*! @} */ /*! @name FRQCNT - Frequency Count Register */ /*! @{ */ #define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU) #define TRNG_FRQCNT_FRQ_CT_SHIFT (0U) #define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK) /*! @} */ /*! @name FRQMAX - Frequency Count Maximum Limit Register */ /*! @{ */ #define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU) #define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U) #define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK) /*! @} */ /*! @name SCMC - Statistical Check Monobit Count Register */ /*! @{ */ #define TRNG_SCMC_MONO_CT_MASK (0xFFFFU) #define TRNG_SCMC_MONO_CT_SHIFT (0U) #define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK) /*! @} */ /*! @name SCML - Statistical Check Monobit Limit Register */ /*! @{ */ #define TRNG_SCML_MONO_MAX_MASK (0xFFFFU) #define TRNG_SCML_MONO_MAX_SHIFT (0U) #define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK) #define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U) #define TRNG_SCML_MONO_RNG_SHIFT (16U) #define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK) /*! @} */ /*! @name SCR1C - Statistical Check Run Length 1 Count Register */ /*! @{ */ #define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU) #define TRNG_SCR1C_R1_0_CT_SHIFT (0U) #define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK) #define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U) #define TRNG_SCR1C_R1_1_CT_SHIFT (16U) #define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK) /*! @} */ /*! @name SCR1L - Statistical Check Run Length 1 Limit Register */ /*! @{ */ #define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU) #define TRNG_SCR1L_RUN1_MAX_SHIFT (0U) #define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK) #define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U) #define TRNG_SCR1L_RUN1_RNG_SHIFT (16U) #define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK) /*! @} */ /*! @name SCR2C - Statistical Check Run Length 2 Count Register */ /*! @{ */ #define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU) #define TRNG_SCR2C_R2_0_CT_SHIFT (0U) #define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK) #define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U) #define TRNG_SCR2C_R2_1_CT_SHIFT (16U) #define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK) /*! @} */ /*! @name SCR2L - Statistical Check Run Length 2 Limit Register */ /*! @{ */ #define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU) #define TRNG_SCR2L_RUN2_MAX_SHIFT (0U) #define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK) #define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U) #define TRNG_SCR2L_RUN2_RNG_SHIFT (16U) #define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK) /*! @} */ /*! @name SCR3C - Statistical Check Run Length 3 Count Register */ /*! @{ */ #define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU) #define TRNG_SCR3C_R3_0_CT_SHIFT (0U) #define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK) #define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U) #define TRNG_SCR3C_R3_1_CT_SHIFT (16U) #define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK) /*! @} */ /*! @name SCR3L - Statistical Check Run Length 3 Limit Register */ /*! @{ */ #define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU) #define TRNG_SCR3L_RUN3_MAX_SHIFT (0U) #define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK) #define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U) #define TRNG_SCR3L_RUN3_RNG_SHIFT (16U) #define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK) /*! @} */ /*! @name SCR4C - Statistical Check Run Length 4 Count Register */ /*! @{ */ #define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU) #define TRNG_SCR4C_R4_0_CT_SHIFT (0U) #define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK) #define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U) #define TRNG_SCR4C_R4_1_CT_SHIFT (16U) #define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK) /*! @} */ /*! @name SCR4L - Statistical Check Run Length 4 Limit Register */ /*! @{ */ #define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU) #define TRNG_SCR4L_RUN4_MAX_SHIFT (0U) #define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK) #define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U) #define TRNG_SCR4L_RUN4_RNG_SHIFT (16U) #define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK) /*! @} */ /*! @name SCR5C - Statistical Check Run Length 5 Count Register */ /*! @{ */ #define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU) #define TRNG_SCR5C_R5_0_CT_SHIFT (0U) #define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK) #define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U) #define TRNG_SCR5C_R5_1_CT_SHIFT (16U) #define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK) /*! @} */ /*! @name SCR5L - Statistical Check Run Length 5 Limit Register */ /*! @{ */ #define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU) #define TRNG_SCR5L_RUN5_MAX_SHIFT (0U) #define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK) #define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U) #define TRNG_SCR5L_RUN5_RNG_SHIFT (16U) #define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK) /*! @} */ /*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */ /*! @{ */ #define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU) #define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U) #define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK) #define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U) #define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U) #define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK) /*! @} */ /*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */ /*! @{ */ #define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU) #define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U) #define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK) #define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U) #define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U) #define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK) /*! @} */ /*! @name STATUS - Status Register */ /*! @{ */ #define TRNG_STATUS_TF1BR0_MASK (0x1U) #define TRNG_STATUS_TF1BR0_SHIFT (0U) #define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK) #define TRNG_STATUS_TF1BR1_MASK (0x2U) #define TRNG_STATUS_TF1BR1_SHIFT (1U) #define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK) #define TRNG_STATUS_TF2BR0_MASK (0x4U) #define TRNG_STATUS_TF2BR0_SHIFT (2U) #define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK) #define TRNG_STATUS_TF2BR1_MASK (0x8U) #define TRNG_STATUS_TF2BR1_SHIFT (3U) #define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK) #define TRNG_STATUS_TF3BR0_MASK (0x10U) #define TRNG_STATUS_TF3BR0_SHIFT (4U) #define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK) #define TRNG_STATUS_TF3BR1_MASK (0x20U) #define TRNG_STATUS_TF3BR1_SHIFT (5U) #define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK) #define TRNG_STATUS_TF4BR0_MASK (0x40U) #define TRNG_STATUS_TF4BR0_SHIFT (6U) #define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK) #define TRNG_STATUS_TF4BR1_MASK (0x80U) #define TRNG_STATUS_TF4BR1_SHIFT (7U) #define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK) #define TRNG_STATUS_TF5BR0_MASK (0x100U) #define TRNG_STATUS_TF5BR0_SHIFT (8U) #define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK) #define TRNG_STATUS_TF5BR1_MASK (0x200U) #define TRNG_STATUS_TF5BR1_SHIFT (9U) #define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK) #define TRNG_STATUS_TF6PBR0_MASK (0x400U) #define TRNG_STATUS_TF6PBR0_SHIFT (10U) #define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK) #define TRNG_STATUS_TF6PBR1_MASK (0x800U) #define TRNG_STATUS_TF6PBR1_SHIFT (11U) #define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK) #define TRNG_STATUS_TFSB_MASK (0x1000U) #define TRNG_STATUS_TFSB_SHIFT (12U) #define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK) #define TRNG_STATUS_TFLR_MASK (0x2000U) #define TRNG_STATUS_TFLR_SHIFT (13U) #define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK) #define TRNG_STATUS_TFP_MASK (0x4000U) #define TRNG_STATUS_TFP_SHIFT (14U) #define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK) #define TRNG_STATUS_TFMB_MASK (0x8000U) #define TRNG_STATUS_TFMB_SHIFT (15U) #define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK) #define TRNG_STATUS_RETRY_CT_MASK (0xF0000U) #define TRNG_STATUS_RETRY_CT_SHIFT (16U) #define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK) /*! @} */ /*! @name ENT - Entropy Read Register */ /*! @{ */ #define TRNG_ENT_ENT_MASK (0xFFFFFFFFU) #define TRNG_ENT_ENT_SHIFT (0U) #define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK) /*! @} */ /* The count of TRNG_ENT */ #define TRNG_ENT_COUNT (16U) /*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */ /*! @{ */ #define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU) #define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U) #define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK) #define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U) #define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK) /*! @} */ /*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */ /*! @{ */ #define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU) #define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U) #define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK) #define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U) #define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK) /*! @} */ /*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */ /*! @{ */ #define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU) #define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U) #define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK) #define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U) #define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK) /*! @} */ /*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */ /*! @{ */ #define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU) #define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U) #define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK) #define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U) #define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK) /*! @} */ /*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */ /*! @{ */ #define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU) #define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U) #define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK) #define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U) #define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK) /*! @} */ /*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */ /*! @{ */ #define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU) #define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U) #define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK) #define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U) #define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK) /*! @} */ /*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */ /*! @{ */ #define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU) #define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U) #define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK) #define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U) #define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK) /*! @} */ /*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */ /*! @{ */ #define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU) #define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U) #define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK) #define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U) #define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U) #define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK) /*! @} */ /*! @name SEC_CFG - Security Configuration Register */ /*! @{ */ #define TRNG_SEC_CFG_SH0_MASK (0x1U) #define TRNG_SEC_CFG_SH0_SHIFT (0U) /*! SH0 * 0b0..See DRNG version. * 0b1..See DRNG version. */ #define TRNG_SEC_CFG_SH0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SH0_SHIFT)) & TRNG_SEC_CFG_SH0_MASK) #define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U) #define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U) /*! NO_PRGM * 0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. * 0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming. */ #define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK) #define TRNG_SEC_CFG_SK_VAL_MASK (0x4U) #define TRNG_SEC_CFG_SK_VAL_SHIFT (2U) /*! SK_VAL * 0b0..See DRNG version. * 0b1..See DRNG version. */ #define TRNG_SEC_CFG_SK_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SK_VAL_SHIFT)) & TRNG_SEC_CFG_SK_VAL_MASK) /*! @} */ /*! @name INT_CTRL - Interrupt Control Register */ /*! @{ */ #define TRNG_INT_CTRL_HW_ERR_MASK (0x1U) #define TRNG_INT_CTRL_HW_ERR_SHIFT (0U) /*! HW_ERR * 0b0..Corresponding bit of INT_STATUS cleared. * 0b1..Corresponding bit of INT_STATUS active. */ #define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK) #define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U) #define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U) /*! ENT_VAL * 0b0..Same behavior as bit 0 above. * 0b1..Same behavior as bit 0 above. */ #define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK) #define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U) #define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U) /*! FRQ_CT_FAIL * 0b0..Same behavior as bit 0 above. * 0b1..Same behavior as bit 0 above. */ #define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) #define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U) #define TRNG_INT_CTRL_UNUSED_SHIFT (3U) #define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK) /*! @} */ /*! @name INT_MASK - Mask Register */ /*! @{ */ #define TRNG_INT_MASK_HW_ERR_MASK (0x1U) #define TRNG_INT_MASK_HW_ERR_SHIFT (0U) /*! HW_ERR * 0b0..Corresponding interrupt of INT_STATUS is masked. * 0b1..Corresponding bit of INT_STATUS is active. */ #define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK) #define TRNG_INT_MASK_ENT_VAL_MASK (0x2U) #define TRNG_INT_MASK_ENT_VAL_SHIFT (1U) /*! ENT_VAL * 0b0..Same behavior as bit 0 above. * 0b1..Same behavior as bit 0 above. */ #define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK) #define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U) #define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U) /*! FRQ_CT_FAIL * 0b0..Same behavior as bit 0 above. * 0b1..Same behavior as bit 0 above. */ #define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) /*! @} */ /*! @name INT_STATUS - Interrupt Status Register */ /*! @{ */ #define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) #define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) /*! HW_ERR * 0b0..no error * 0b1..error detected. */ #define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) #define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U) #define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U) /*! ENT_VAL * 0b0..Busy generation entropy. Any value read is invalid. * 0b1..TRNG can be stopped and entropy is valid if read. */ #define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK) #define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) #define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) /*! FRQ_CT_FAIL * 0b0..No hardware nor self test frequency errors. * 0b1..The frequency counter has detected a failure. */ #define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) /*! @} */ /*! @name VID1 - Version ID Register (MS) */ /*! @{ */ #define TRNG_VID1_MIN_REV_MASK (0xFFU) #define TRNG_VID1_MIN_REV_SHIFT (0U) /*! MIN_REV * 0b00000000..Minor revision number for TRNG. */ #define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK) #define TRNG_VID1_MAJ_REV_MASK (0xFF00U) #define TRNG_VID1_MAJ_REV_SHIFT (8U) /*! MAJ_REV * 0b00000001..Major revision number for TRNG. */ #define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK) #define TRNG_VID1_IP_ID_MASK (0xFFFF0000U) #define TRNG_VID1_IP_ID_SHIFT (16U) /*! IP_ID * 0b0000000000110000..ID for TRNG. */ #define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK) /*! @} */ /*! @name VID2 - Version ID Register (LS) */ /*! @{ */ #define TRNG_VID2_CONFIG_OPT_MASK (0xFFU) #define TRNG_VID2_CONFIG_OPT_SHIFT (0U) /*! CONFIG_OPT * 0b00000000..TRNG_CONFIG_OPT for TRNG. */ #define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK) #define TRNG_VID2_ECO_REV_MASK (0xFF00U) #define TRNG_VID2_ECO_REV_SHIFT (8U) /*! ECO_REV * 0b00000000..TRNG_ECO_REV for TRNG. */ #define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK) #define TRNG_VID2_INTG_OPT_MASK (0xFF0000U) #define TRNG_VID2_INTG_OPT_SHIFT (16U) /*! INTG_OPT * 0b00000000..INTG_OPT for TRNG. */ #define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK) #define TRNG_VID2_ERA_MASK (0xFF000000U) #define TRNG_VID2_ERA_SHIFT (24U) /*! ERA * 0b00000000..COMPILE_OPT for TRNG. */ #define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK) /*! @} */ /*! * @} */ /* end of group TRNG_Register_Masks */ /* TRNG - Peripheral instance base addresses */ /** Peripheral TRNG0 base address */ #define TRNG0_BASE (0x4102C000u) /** Peripheral TRNG0 base pointer */ #define TRNG0 ((TRNG_Type *)TRNG0_BASE) /** Array initializer of TRNG peripheral base addresses */ #define TRNG_BASE_ADDRS { TRNG0_BASE } /** Array initializer of TRNG peripheral base pointers */ #define TRNG_BASE_PTRS { TRNG0 } /** Interrupt vectors for the TRNG peripheral type */ #define TRNG_IRQS { TRNG0_IRQn } /*! * @} */ /* end of group TRNG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- TSTMR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup TSTMR_Peripheral_Access_Layer TSTMR Peripheral Access Layer * @{ */ /** TSTMR - Register Layout Typedef */ typedef struct { __I uint32_t L; /**< Time Stamp Timer Register Low, offset: 0x0 */ __I uint32_t H; /**< Time Stamp Timer Register High, offset: 0x4 */ } TSTMR_Type; /* ---------------------------------------------------------------------------- -- TSTMR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup TSTMR_Register_Masks TSTMR Register Masks * @{ */ /*! @name L - Time Stamp Timer Register Low */ /*! @{ */ #define TSTMR_L_VALUE_MASK (0xFFFFFFFFU) #define TSTMR_L_VALUE_SHIFT (0U) /*! VALUE - Time Stamp Timer Low */ #define TSTMR_L_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSTMR_L_VALUE_SHIFT)) & TSTMR_L_VALUE_MASK) /*! @} */ /*! @name H - Time Stamp Timer Register High */ /*! @{ */ #define TSTMR_H_VALUE_MASK (0xFFFFFFFFU) #define TSTMR_H_VALUE_SHIFT (0U) /*! VALUE - Time Stamp Timer High */ #define TSTMR_H_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSTMR_H_VALUE_SHIFT)) & TSTMR_H_VALUE_MASK) /*! @} */ /*! * @} */ /* end of group TSTMR_Register_Masks */ /* TSTMR - Peripheral instance base addresses */ /** Peripheral TSTMRA base address */ #define TSTMRA_BASE (0x410A3C00u) /** Peripheral TSTMRA base pointer */ #define TSTMRA ((TSTMR_Type *)TSTMRA_BASE) /** Peripheral TSTMRB base address */ #define TSTMRB_BASE (0x410A3C08u) /** Peripheral TSTMRB base pointer */ #define TSTMRB ((TSTMR_Type *)TSTMRB_BASE) /** Array initializer of TSTMR peripheral base addresses */ #define TSTMR_BASE_ADDRS { TSTMRA_BASE, TSTMRB_BASE } /** Array initializer of TSTMR peripheral base pointers */ #define TSTMR_BASE_PTRS { TSTMRA, TSTMRB } /*! * @} */ /* end of group TSTMR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer * @{ */ /** USB - Register Layout Typedef */ typedef struct { __I uint32_t ID; /**< Identification register, offset: 0x0 */ __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ uint8_t RESERVED_0[104]; __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ uint8_t RESERVED_1[108]; __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ uint8_t RESERVED_2[1]; __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ uint8_t RESERVED_3[20]; __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ uint8_t RESERVED_4[2]; __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ uint8_t RESERVED_5[24]; __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */ __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */ __IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */ __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ uint8_t RESERVED_6[4]; union { /* offset: 0x154 */ __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ }; union { /* offset: 0x158 */ __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ }; uint8_t RESERVED_7[4]; __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ uint8_t RESERVED_8[16]; __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */ __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ uint8_t RESERVED_9[28]; __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ } USB_Type; /* ---------------------------------------------------------------------------- -- USB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_Register_Masks USB Register Masks * @{ */ /*! @name ID - Identification register */ /*! @{ */ #define USB_ID_ID_MASK (0x3FU) #define USB_ID_ID_SHIFT (0U) #define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) #define USB_ID_NID_MASK (0x3F00U) #define USB_ID_NID_SHIFT (8U) #define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK) #define USB_ID_REVISION_MASK (0xFF0000U) #define USB_ID_REVISION_SHIFT (16U) #define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) /*! @} */ /*! @name HWGENERAL - Hardware General */ /*! @{ */ #define USB_HWGENERAL_PHYW_MASK (0x30U) #define USB_HWGENERAL_PHYW_SHIFT (4U) /*! PHYW * 0b00..8 bit wide data bus Software non-programmable * 0b01..16 bit wide data bus Software non-programmable * 0b10..Reset to 8 bit wide data bus Software programmable * 0b11..Reset to 16 bit wide data bus Software programmable */ #define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) #define USB_HWGENERAL_PHYM_MASK (0x1C0U) #define USB_HWGENERAL_PHYM_SHIFT (6U) /*! PHYM * 0b000..UTMI/UMTI+ * 0b001..ULPI DDR * 0b010..ULPI * 0b011..Serial Only * 0b100..Software programmable - reset to UTMI/UTMI+ * 0b101..Software programmable - reset to ULPI DDR * 0b110..Software programmable - reset to ULPI * 0b111..Software programmable - reset to Serial */ #define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) #define USB_HWGENERAL_SM_MASK (0x600U) #define USB_HWGENERAL_SM_SHIFT (9U) /*! SM * 0b00..No Serial Engine, always use parallel signalling. * 0b01..Serial Engine present, always use serial signalling for FS/LS. * 0b10..Software programmable - Reset to use parallel signalling for FS/LS * 0b11..Software programmable - Reset to use serial signalling for FS/LS */ #define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) /*! @} */ /*! @name HWHOST - Host Hardware Parameters */ /*! @{ */ #define USB_HWHOST_HC_MASK (0x1U) #define USB_HWHOST_HC_SHIFT (0U) /*! HC * 0b1..Supported * 0b0..Not supported */ #define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) #define USB_HWHOST_NPORT_MASK (0xEU) #define USB_HWHOST_NPORT_SHIFT (1U) #define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) /*! @} */ /*! @name HWDEVICE - Device Hardware Parameters */ /*! @{ */ #define USB_HWDEVICE_DC_MASK (0x1U) #define USB_HWDEVICE_DC_SHIFT (0U) /*! DC * 0b1..Supported * 0b0..Not supported */ #define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) #define USB_HWDEVICE_DEVEP_MASK (0x3EU) #define USB_HWDEVICE_DEVEP_SHIFT (1U) #define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) /*! @} */ /*! @name HWTXBUF - TX Buffer Hardware Parameters */ /*! @{ */ #define USB_HWTXBUF_TXBURST_MASK (0xFFU) #define USB_HWTXBUF_TXBURST_SHIFT (0U) #define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) #define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) #define USB_HWTXBUF_TXCHANADD_SHIFT (16U) #define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) /*! @} */ /*! @name HWRXBUF - RX Buffer Hardware Parameters */ /*! @{ */ #define USB_HWRXBUF_RXBURST_MASK (0xFFU) #define USB_HWRXBUF_RXBURST_SHIFT (0U) #define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) #define USB_HWRXBUF_RXADD_MASK (0xFF00U) #define USB_HWRXBUF_RXADD_SHIFT (8U) #define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) /*! @} */ /*! @name GPTIMER0LD - General Purpose Timer #0 Load */ /*! @{ */ #define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) #define USB_GPTIMER0LD_GPTLD_SHIFT (0U) #define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) /*! @} */ /*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ /*! @{ */ #define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) #define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) #define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) #define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) #define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) /*! GPTMODE * 0b0..One Shot Mode * 0b1..Repeat Mode */ #define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) #define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) #define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) /*! GPTRST * 0b0..No action * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD */ #define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) #define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) #define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) /*! GPTRUN * 0b0..Stop counting * 0b1..Run */ #define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) /*! @} */ /*! @name GPTIMER1LD - General Purpose Timer #1 Load */ /*! @{ */ #define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) #define USB_GPTIMER1LD_GPTLD_SHIFT (0U) #define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) /*! @} */ /*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ /*! @{ */ #define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) #define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) #define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) #define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) #define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) /*! GPTMODE * 0b0..One Shot Mode * 0b1..Repeat Mode */ #define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) #define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) #define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) /*! GPTRST * 0b0..No action * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD */ #define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) #define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) #define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) /*! GPTRUN * 0b0..Stop counting * 0b1..Run */ #define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) /*! @} */ /*! @name SBUSCFG - System Bus Config */ /*! @{ */ #define USB_SBUSCFG_AHBBRST_MASK (0x7U) #define USB_SBUSCFG_AHBBRST_SHIFT (0U) /*! AHBBRST * 0b000..Incremental burst of unspecified length only * 0b001..INCR4 burst, then single transfer * 0b010..INCR8 burst, INCR4 burst, then single transfer * 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer * 0b100..Reserved, don't use * 0b101..INCR4 burst, then incremental burst of unspecified length * 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length * 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length */ #define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) /*! @} */ /*! @name CAPLENGTH - Capability Registers Length */ /*! @{ */ #define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) #define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) #define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) /*! @} */ /*! @name HCIVERSION - Host Controller Interface Version */ /*! @{ */ #define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) #define USB_HCIVERSION_HCIVERSION_SHIFT (0U) #define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) /*! @} */ /*! @name HCSPARAMS - Host Controller Structural Parameters */ /*! @{ */ #define USB_HCSPARAMS_N_PORTS_MASK (0xFU) #define USB_HCSPARAMS_N_PORTS_SHIFT (0U) #define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) #define USB_HCSPARAMS_PPC_MASK (0x10U) #define USB_HCSPARAMS_PPC_SHIFT (4U) #define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK) #define USB_HCSPARAMS_N_PCC_MASK (0xF00U) #define USB_HCSPARAMS_N_PCC_SHIFT (8U) #define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) #define USB_HCSPARAMS_N_CC_MASK (0xF000U) #define USB_HCSPARAMS_N_CC_SHIFT (12U) /*! N_CC * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported. * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported. */ #define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) #define USB_HCSPARAMS_PI_MASK (0x10000U) #define USB_HCSPARAMS_PI_SHIFT (16U) #define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK) #define USB_HCSPARAMS_N_PTT_MASK (0xF00000U) #define USB_HCSPARAMS_N_PTT_SHIFT (20U) #define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK) #define USB_HCSPARAMS_N_TT_MASK (0xF000000U) #define USB_HCSPARAMS_N_TT_SHIFT (24U) #define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) /*! @} */ /*! @name HCCPARAMS - Host Controller Capability Parameters */ /*! @{ */ #define USB_HCCPARAMS_ADC_MASK (0x1U) #define USB_HCCPARAMS_ADC_SHIFT (0U) #define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) #define USB_HCCPARAMS_PFL_MASK (0x2U) #define USB_HCCPARAMS_PFL_SHIFT (1U) #define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK) #define USB_HCCPARAMS_ASP_MASK (0x4U) #define USB_HCCPARAMS_ASP_SHIFT (2U) #define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK) #define USB_HCCPARAMS_IST_MASK (0xF0U) #define USB_HCCPARAMS_IST_SHIFT (4U) #define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK) #define USB_HCCPARAMS_EECP_MASK (0xFF00U) #define USB_HCCPARAMS_EECP_SHIFT (8U) #define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) /*! @} */ /*! @name DCIVERSION - Device Controller Interface Version */ /*! @{ */ #define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) #define USB_DCIVERSION_DCIVERSION_SHIFT (0U) #define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) /*! @} */ /*! @name DCCPARAMS - Device Controller Capability Parameters */ /*! @{ */ #define USB_DCCPARAMS_DEN_MASK (0x1FU) #define USB_DCCPARAMS_DEN_SHIFT (0U) #define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) #define USB_DCCPARAMS_DC_MASK (0x80U) #define USB_DCCPARAMS_DC_SHIFT (7U) #define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK) #define USB_DCCPARAMS_HC_MASK (0x100U) #define USB_DCCPARAMS_HC_SHIFT (8U) #define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) /*! @} */ /*! @name USBCMD - USB Command Register */ /*! @{ */ #define USB_USBCMD_RS_MASK (0x1U) #define USB_USBCMD_RS_SHIFT (0U) #define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) #define USB_USBCMD_RST_MASK (0x2U) #define USB_USBCMD_RST_SHIFT (1U) #define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK) #define USB_USBCMD_FS_1_MASK (0xCU) #define USB_USBCMD_FS_1_SHIFT (2U) #define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) #define USB_USBCMD_PSE_MASK (0x10U) #define USB_USBCMD_PSE_SHIFT (4U) /*! PSE * 0b0..Do not process the Periodic Schedule * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule. */ #define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) #define USB_USBCMD_ASE_MASK (0x20U) #define USB_USBCMD_ASE_SHIFT (5U) /*! ASE * 0b0..Do not process the Asynchronous Schedule. * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule. */ #define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) #define USB_USBCMD_IAA_MASK (0x40U) #define USB_USBCMD_IAA_SHIFT (6U) #define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK) #define USB_USBCMD_ASP_MASK (0x300U) #define USB_USBCMD_ASP_SHIFT (8U) #define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK) #define USB_USBCMD_ASPE_MASK (0x800U) #define USB_USBCMD_ASPE_SHIFT (11U) #define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK) #define USB_USBCMD_SUTW_MASK (0x2000U) #define USB_USBCMD_SUTW_SHIFT (13U) #define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) #define USB_USBCMD_ATDTW_MASK (0x4000U) #define USB_USBCMD_ATDTW_SHIFT (14U) #define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK) #define USB_USBCMD_FS_2_MASK (0x8000U) #define USB_USBCMD_FS_2_SHIFT (15U) /*! FS_2 * 0b0..1024 elements (4096 bytes) Default value * 0b1..512 elements (2048 bytes) */ #define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) #define USB_USBCMD_ITC_MASK (0xFF0000U) #define USB_USBCMD_ITC_SHIFT (16U) /*! ITC * 0b00000000..Immediate (no threshold) * 0b00000001..1 micro-frame * 0b00000010..2 micro-frames * 0b00000100..4 micro-frames * 0b00001000..8 micro-frames * 0b00010000..16 micro-frames * 0b00100000..32 micro-frames * 0b01000000..64 micro-frames */ #define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) /*! @} */ /*! @name USBSTS - USB Status Register */ /*! @{ */ #define USB_USBSTS_UI_MASK (0x1U) #define USB_USBSTS_UI_SHIFT (0U) #define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) #define USB_USBSTS_UEI_MASK (0x2U) #define USB_USBSTS_UEI_SHIFT (1U) #define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) #define USB_USBSTS_PCI_MASK (0x4U) #define USB_USBSTS_PCI_SHIFT (2U) #define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) #define USB_USBSTS_FRI_MASK (0x8U) #define USB_USBSTS_FRI_SHIFT (3U) #define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) #define USB_USBSTS_SEI_MASK (0x10U) #define USB_USBSTS_SEI_SHIFT (4U) #define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) #define USB_USBSTS_AAI_MASK (0x20U) #define USB_USBSTS_AAI_SHIFT (5U) #define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) #define USB_USBSTS_URI_MASK (0x40U) #define USB_USBSTS_URI_SHIFT (6U) #define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) #define USB_USBSTS_SRI_MASK (0x80U) #define USB_USBSTS_SRI_SHIFT (7U) #define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) #define USB_USBSTS_SLI_MASK (0x100U) #define USB_USBSTS_SLI_SHIFT (8U) #define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) #define USB_USBSTS_ULPII_MASK (0x400U) #define USB_USBSTS_ULPII_SHIFT (10U) #define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) #define USB_USBSTS_HCH_MASK (0x1000U) #define USB_USBSTS_HCH_SHIFT (12U) #define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK) #define USB_USBSTS_RCL_MASK (0x2000U) #define USB_USBSTS_RCL_SHIFT (13U) #define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK) #define USB_USBSTS_PS_MASK (0x4000U) #define USB_USBSTS_PS_SHIFT (14U) #define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK) #define USB_USBSTS_AS_MASK (0x8000U) #define USB_USBSTS_AS_SHIFT (15U) #define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK) #define USB_USBSTS_NAKI_MASK (0x10000U) #define USB_USBSTS_NAKI_SHIFT (16U) #define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK) #define USB_USBSTS_UAI_MASK (0x40000U) #define USB_USBSTS_UAI_SHIFT (18U) /*! UAI - USB Host Asynchronous Interrupt (USBHSTASYNCINT) */ #define USB_USBSTS_UAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UAI_SHIFT)) & USB_USBSTS_UAI_MASK) #define USB_USBSTS_UPI_MASK (0x80000U) #define USB_USBSTS_UPI_SHIFT (19U) /*! UPI - USB Host Periodic Interrupt (USBHSTPERINT) */ #define USB_USBSTS_UPI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UPI_SHIFT)) & USB_USBSTS_UPI_MASK) #define USB_USBSTS_TI0_MASK (0x1000000U) #define USB_USBSTS_TI0_SHIFT (24U) #define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) #define USB_USBSTS_TI1_MASK (0x2000000U) #define USB_USBSTS_TI1_SHIFT (25U) #define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) /*! @} */ /*! @name USBINTR - Interrupt Enable Register */ /*! @{ */ #define USB_USBINTR_UE_MASK (0x1U) #define USB_USBINTR_UE_SHIFT (0U) #define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) #define USB_USBINTR_UEE_MASK (0x2U) #define USB_USBINTR_UEE_SHIFT (1U) #define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK) #define USB_USBINTR_PCE_MASK (0x4U) #define USB_USBINTR_PCE_SHIFT (2U) #define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK) #define USB_USBINTR_FRE_MASK (0x8U) #define USB_USBINTR_FRE_SHIFT (3U) #define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK) #define USB_USBINTR_SEE_MASK (0x10U) #define USB_USBINTR_SEE_SHIFT (4U) #define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK) #define USB_USBINTR_AAE_MASK (0x20U) #define USB_USBINTR_AAE_SHIFT (5U) #define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK) #define USB_USBINTR_URE_MASK (0x40U) #define USB_USBINTR_URE_SHIFT (6U) #define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK) #define USB_USBINTR_SRE_MASK (0x80U) #define USB_USBINTR_SRE_SHIFT (7U) #define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK) #define USB_USBINTR_SLE_MASK (0x100U) #define USB_USBINTR_SLE_SHIFT (8U) #define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK) #define USB_USBINTR_ULPIE_MASK (0x400U) #define USB_USBINTR_ULPIE_SHIFT (10U) #define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK) #define USB_USBINTR_NAKE_MASK (0x10000U) #define USB_USBINTR_NAKE_SHIFT (16U) #define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK) #define USB_USBINTR_UAIE_MASK (0x40000U) #define USB_USBINTR_UAIE_SHIFT (18U) #define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK) #define USB_USBINTR_UPIE_MASK (0x80000U) #define USB_USBINTR_UPIE_SHIFT (19U) #define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK) #define USB_USBINTR_TIE0_MASK (0x1000000U) #define USB_USBINTR_TIE0_SHIFT (24U) #define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK) #define USB_USBINTR_TIE1_MASK (0x2000000U) #define USB_USBINTR_TIE1_SHIFT (25U) #define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) /*! @} */ /*! @name FRINDEX - USB Frame Index */ /*! @{ */ #define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) #define USB_FRINDEX_FRINDEX_SHIFT (0U) /*! FRINDEX * 0b00000000000000..(1024) 12 * 0b00000000000001..(512) 11 * 0b00000000000010..(256) 10 * 0b00000000000011..(128) 9 * 0b00000000000100..(64) 8 * 0b00000000000101..(32) 7 * 0b00000000000110..(16) 6 * 0b00000000000111..(8) 5 */ #define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) /*! @} */ /*! @name DEVICEADDR - Device Address */ /*! @{ */ #define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) #define USB_DEVICEADDR_USBADRA_SHIFT (24U) #define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) #define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) #define USB_DEVICEADDR_USBADR_SHIFT (25U) #define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) /*! @} */ /*! @name PERIODICLISTBASE - Frame List Base Address */ /*! @{ */ #define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) #define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) #define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) /*! @} */ /*! @name ASYNCLISTADDR - Next Asynch. Address */ /*! @{ */ #define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) #define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) #define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) /*! @} */ /*! @name ENDPTLISTADDR - Endpoint List Address */ /*! @{ */ #define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) #define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) #define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) /*! @} */ /*! @name BURSTSIZE - Programmable Burst Size */ /*! @{ */ #define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) #define USB_BURSTSIZE_RXPBURST_SHIFT (0U) #define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) #define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U) #define USB_BURSTSIZE_TXPBURST_SHIFT (8U) #define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) /*! @} */ /*! @name TXFILLTUNING - TX FIFO Fill Tuning */ /*! @{ */ #define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU) #define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) #define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) #define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) #define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) #define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) #define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) #define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) #define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) /*! @} */ /*! @name ENDPTNAK - Endpoint NAK */ /*! @{ */ #define USB_ENDPTNAK_EPRN_MASK (0xFFU) #define USB_ENDPTNAK_EPRN_SHIFT (0U) #define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) #define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) #define USB_ENDPTNAK_EPTN_SHIFT (16U) #define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) /*! @} */ /*! @name ENDPTNAKEN - Endpoint NAK Enable */ /*! @{ */ #define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) #define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) #define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) #define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) #define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) #define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) /*! @} */ /*! @name CONFIGFLAG - Configure Flag Register */ /*! @{ */ #define USB_CONFIGFLAG_CF_MASK (0x1U) #define USB_CONFIGFLAG_CF_SHIFT (0U) /*! CF * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller. * 0b1..Port routing control logic default-routes all ports to this host controller. */ #define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) /*! @} */ /*! @name PORTSC1 - Port Status & Control */ /*! @{ */ #define USB_PORTSC1_CCS_MASK (0x1U) #define USB_PORTSC1_CCS_SHIFT (0U) #define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) #define USB_PORTSC1_CSC_MASK (0x2U) #define USB_PORTSC1_CSC_SHIFT (1U) #define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK) #define USB_PORTSC1_PE_MASK (0x4U) #define USB_PORTSC1_PE_SHIFT (2U) #define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK) #define USB_PORTSC1_PEC_MASK (0x8U) #define USB_PORTSC1_PEC_SHIFT (3U) #define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) #define USB_PORTSC1_OCA_MASK (0x10U) #define USB_PORTSC1_OCA_SHIFT (4U) /*! OCA * 0b1..This port currently has an over-current condition * 0b0..This port does not have an over-current condition. */ #define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) #define USB_PORTSC1_OCC_MASK (0x20U) #define USB_PORTSC1_OCC_SHIFT (5U) #define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK) #define USB_PORTSC1_FPR_MASK (0x40U) #define USB_PORTSC1_FPR_SHIFT (6U) #define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK) #define USB_PORTSC1_SUSP_MASK (0x80U) #define USB_PORTSC1_SUSP_SHIFT (7U) #define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK) #define USB_PORTSC1_PR_MASK (0x100U) #define USB_PORTSC1_PR_SHIFT (8U) #define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK) #define USB_PORTSC1_HSP_MASK (0x200U) #define USB_PORTSC1_HSP_SHIFT (9U) #define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) #define USB_PORTSC1_LS_MASK (0xC00U) #define USB_PORTSC1_LS_SHIFT (10U) /*! LS * 0b00..SE0 * 0b10..J-state * 0b01..K-state * 0b11..Undefined */ #define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) #define USB_PORTSC1_PP_MASK (0x1000U) #define USB_PORTSC1_PP_SHIFT (12U) #define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK) #define USB_PORTSC1_PO_MASK (0x2000U) #define USB_PORTSC1_PO_SHIFT (13U) #define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) #define USB_PORTSC1_PIC_MASK (0xC000U) #define USB_PORTSC1_PIC_SHIFT (14U) /*! PIC * 0b00..Port indicators are off * 0b01..Amber * 0b10..Green * 0b11..Undefined */ #define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) #define USB_PORTSC1_PTC_MASK (0xF0000U) #define USB_PORTSC1_PTC_SHIFT (16U) /*! PTC * 0b0000..TEST_MODE_DISABLE * 0b0001..J_STATE * 0b0010..K_STATE * 0b0011..SE0 (host) / NAK (device) * 0b0100..Packet * 0b0101..FORCE_ENABLE_HS * 0b0110..FORCE_ENABLE_FS * 0b0111..FORCE_ENABLE_LS */ #define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) #define USB_PORTSC1_WKCN_MASK (0x100000U) #define USB_PORTSC1_WKCN_SHIFT (20U) #define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK) #define USB_PORTSC1_WKDC_MASK (0x200000U) #define USB_PORTSC1_WKDC_SHIFT (21U) #define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK) #define USB_PORTSC1_WKOC_MASK (0x400000U) #define USB_PORTSC1_WKOC_SHIFT (22U) #define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) #define USB_PORTSC1_PHCD_MASK (0x800000U) #define USB_PORTSC1_PHCD_SHIFT (23U) /*! PHCD * 0b1..Disable PHY clock * 0b0..Enable PHY clock */ #define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) #define USB_PORTSC1_PFSC_MASK (0x1000000U) #define USB_PORTSC1_PFSC_SHIFT (24U) /*! PFSC * 0b1..Forced to full speed * 0b0..Normal operation */ #define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) #define USB_PORTSC1_PTS_2_MASK (0x2000000U) #define USB_PORTSC1_PTS_2_SHIFT (25U) #define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) #define USB_PORTSC1_PSPD_MASK (0xC000000U) #define USB_PORTSC1_PSPD_SHIFT (26U) /*! PSPD * 0b00..Full Speed * 0b01..Low Speed * 0b10..High Speed * 0b11..Undefined */ #define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) #define USB_PORTSC1_PTW_MASK (0x10000000U) #define USB_PORTSC1_PTW_SHIFT (28U) /*! PTW * 0b0..Select the 8-bit UTMI interface [60MHz] * 0b1..Select the 16-bit UTMI interface [30MHz] */ #define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) #define USB_PORTSC1_STS_MASK (0x20000000U) #define USB_PORTSC1_STS_SHIFT (29U) #define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK) #define USB_PORTSC1_PTS_1_MASK (0xC0000000U) #define USB_PORTSC1_PTS_1_SHIFT (30U) #define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) /*! @} */ /*! @name OTGSC - On-The-Go Status & control */ /*! @{ */ #define USB_OTGSC_VD_MASK (0x1U) #define USB_OTGSC_VD_SHIFT (0U) #define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) #define USB_OTGSC_VC_MASK (0x2U) #define USB_OTGSC_VC_SHIFT (1U) #define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK) #define USB_OTGSC_OT_MASK (0x8U) #define USB_OTGSC_OT_SHIFT (3U) #define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK) #define USB_OTGSC_DP_MASK (0x10U) #define USB_OTGSC_DP_SHIFT (4U) #define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK) #define USB_OTGSC_IDPU_MASK (0x20U) #define USB_OTGSC_IDPU_SHIFT (5U) #define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK) #define USB_OTGSC_ID_MASK (0x100U) #define USB_OTGSC_ID_SHIFT (8U) #define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK) #define USB_OTGSC_AVV_MASK (0x200U) #define USB_OTGSC_AVV_SHIFT (9U) #define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK) #define USB_OTGSC_ASV_MASK (0x400U) #define USB_OTGSC_ASV_SHIFT (10U) #define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK) #define USB_OTGSC_BSV_MASK (0x800U) #define USB_OTGSC_BSV_SHIFT (11U) #define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK) #define USB_OTGSC_BSE_MASK (0x1000U) #define USB_OTGSC_BSE_SHIFT (12U) #define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK) #define USB_OTGSC_TOG_1MS_MASK (0x2000U) #define USB_OTGSC_TOG_1MS_SHIFT (13U) #define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK) #define USB_OTGSC_DPS_MASK (0x4000U) #define USB_OTGSC_DPS_SHIFT (14U) #define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK) #define USB_OTGSC_IDIS_MASK (0x10000U) #define USB_OTGSC_IDIS_SHIFT (16U) #define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK) #define USB_OTGSC_AVVIS_MASK (0x20000U) #define USB_OTGSC_AVVIS_SHIFT (17U) #define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) #define USB_OTGSC_ASVIS_MASK (0x40000U) #define USB_OTGSC_ASVIS_SHIFT (18U) #define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) #define USB_OTGSC_BSVIS_MASK (0x80000U) #define USB_OTGSC_BSVIS_SHIFT (19U) #define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) #define USB_OTGSC_BSEIS_MASK (0x100000U) #define USB_OTGSC_BSEIS_SHIFT (20U) #define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) #define USB_OTGSC_STATUS_1MS_MASK (0x200000U) #define USB_OTGSC_STATUS_1MS_SHIFT (21U) #define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK) #define USB_OTGSC_DPIS_MASK (0x400000U) #define USB_OTGSC_DPIS_SHIFT (22U) #define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) #define USB_OTGSC_IDIE_MASK (0x1000000U) #define USB_OTGSC_IDIE_SHIFT (24U) #define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK) #define USB_OTGSC_AVVIE_MASK (0x2000000U) #define USB_OTGSC_AVVIE_SHIFT (25U) #define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK) #define USB_OTGSC_ASVIE_MASK (0x4000000U) #define USB_OTGSC_ASVIE_SHIFT (26U) #define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK) #define USB_OTGSC_BSVIE_MASK (0x8000000U) #define USB_OTGSC_BSVIE_SHIFT (27U) #define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK) #define USB_OTGSC_BSEIE_MASK (0x10000000U) #define USB_OTGSC_BSEIE_SHIFT (28U) #define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK) #define USB_OTGSC_EN_1MS_MASK (0x20000000U) #define USB_OTGSC_EN_1MS_SHIFT (29U) #define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK) #define USB_OTGSC_DPIE_MASK (0x40000000U) #define USB_OTGSC_DPIE_SHIFT (30U) #define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) /*! @} */ /*! @name USBMODE - USB Device Mode */ /*! @{ */ #define USB_USBMODE_CM_MASK (0x3U) #define USB_USBMODE_CM_SHIFT (0U) /*! CM * 0b00..Idle [Default for combination host/device] * 0b01..Reserved * 0b10..Device Controller [Default for device only controller] * 0b11..Host Controller [Default for host only controller] */ #define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) #define USB_USBMODE_ES_MASK (0x4U) #define USB_USBMODE_ES_SHIFT (2U) /*! ES * 0b0..Little Endian [Default] * 0b1..Big Endian */ #define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) #define USB_USBMODE_SLOM_MASK (0x8U) #define USB_USBMODE_SLOM_SHIFT (3U) /*! SLOM * 0b0..Setup Lockouts On (default); * 0b1..Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register . */ #define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) #define USB_USBMODE_SDIS_MASK (0x10U) #define USB_USBMODE_SDIS_SHIFT (4U) #define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) /*! @} */ /*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ /*! @{ */ #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) /*! @} */ /*! @name ENDPTPRIME - Endpoint Prime */ /*! @{ */ #define USB_ENDPTPRIME_PERB_MASK (0xFFU) #define USB_ENDPTPRIME_PERB_SHIFT (0U) #define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) #define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) #define USB_ENDPTPRIME_PETB_SHIFT (16U) #define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) /*! @} */ /*! @name ENDPTFLUSH - Endpoint Flush */ /*! @{ */ #define USB_ENDPTFLUSH_FERB_MASK (0xFFU) #define USB_ENDPTFLUSH_FERB_SHIFT (0U) #define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) #define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) #define USB_ENDPTFLUSH_FETB_SHIFT (16U) #define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) /*! @} */ /*! @name ENDPTSTAT - Endpoint Status */ /*! @{ */ #define USB_ENDPTSTAT_ERBR_MASK (0xFFU) #define USB_ENDPTSTAT_ERBR_SHIFT (0U) #define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) #define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) #define USB_ENDPTSTAT_ETBR_SHIFT (16U) #define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) /*! @} */ /*! @name ENDPTCOMPLETE - Endpoint Complete */ /*! @{ */ #define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) #define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) #define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) #define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) #define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) #define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) /*! @} */ /*! @name ENDPTCTRL0 - Endpoint Control0 */ /*! @{ */ #define USB_ENDPTCTRL0_RXS_MASK (0x1U) #define USB_ENDPTCTRL0_RXS_SHIFT (0U) #define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) #define USB_ENDPTCTRL0_RXT_MASK (0xCU) #define USB_ENDPTCTRL0_RXT_SHIFT (2U) #define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK) #define USB_ENDPTCTRL0_RXE_MASK (0x80U) #define USB_ENDPTCTRL0_RXE_SHIFT (7U) #define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK) #define USB_ENDPTCTRL0_TXS_MASK (0x10000U) #define USB_ENDPTCTRL0_TXS_SHIFT (16U) #define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK) #define USB_ENDPTCTRL0_TXT_MASK (0xC0000U) #define USB_ENDPTCTRL0_TXT_SHIFT (18U) #define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK) #define USB_ENDPTCTRL0_TXE_MASK (0x800000U) #define USB_ENDPTCTRL0_TXE_SHIFT (23U) #define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) /*! @} */ /*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ /*! @{ */ #define USB_ENDPTCTRL_RXS_MASK (0x1U) #define USB_ENDPTCTRL_RXS_SHIFT (0U) #define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) #define USB_ENDPTCTRL_RXD_MASK (0x2U) #define USB_ENDPTCTRL_RXD_SHIFT (1U) #define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK) #define USB_ENDPTCTRL_RXT_MASK (0xCU) #define USB_ENDPTCTRL_RXT_SHIFT (2U) #define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK) #define USB_ENDPTCTRL_RXI_MASK (0x20U) #define USB_ENDPTCTRL_RXI_SHIFT (5U) #define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK) #define USB_ENDPTCTRL_RXR_MASK (0x40U) #define USB_ENDPTCTRL_RXR_SHIFT (6U) #define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK) #define USB_ENDPTCTRL_RXE_MASK (0x80U) #define USB_ENDPTCTRL_RXE_SHIFT (7U) #define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK) #define USB_ENDPTCTRL_TXS_MASK (0x10000U) #define USB_ENDPTCTRL_TXS_SHIFT (16U) #define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK) #define USB_ENDPTCTRL_TXD_MASK (0x20000U) #define USB_ENDPTCTRL_TXD_SHIFT (17U) #define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK) #define USB_ENDPTCTRL_TXT_MASK (0xC0000U) #define USB_ENDPTCTRL_TXT_SHIFT (18U) #define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK) #define USB_ENDPTCTRL_TXI_MASK (0x200000U) #define USB_ENDPTCTRL_TXI_SHIFT (21U) #define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK) #define USB_ENDPTCTRL_TXR_MASK (0x400000U) #define USB_ENDPTCTRL_TXR_SHIFT (22U) #define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK) #define USB_ENDPTCTRL_TXE_MASK (0x800000U) #define USB_ENDPTCTRL_TXE_SHIFT (23U) #define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) /*! @} */ /* The count of USB_ENDPTCTRL */ #define USB_ENDPTCTRL_COUNT (7U) /*! * @} */ /* end of group USB_Register_Masks */ /* USB - Peripheral instance base addresses */ /** Peripheral USB0 base address */ #define USB0_BASE (0x40330000u) /** Peripheral USB0 base pointer */ #define USB0 ((USB_Type *)USB0_BASE) /** Peripheral USB1 base address */ #define USB1_BASE (0x40340000u) /** Peripheral USB1 base pointer */ #define USB1 ((USB_Type *)USB1_BASE) /** Array initializer of USB peripheral base addresses */ #define USB_BASE_ADDRS { USB0_BASE, USB1_BASE } /** Array initializer of USB peripheral base pointers */ #define USB_BASE_PTRS { USB0, USB1 } /** Interrupt vectors for the USB peripheral type */ #define USB_IRQS { USB0_IRQn, USB1_IRQn } /*! * @} */ /* end of group USB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USBHSDCD Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer * @{ */ /** USBHSDCD - Register Layout Typedef */ typedef struct { __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */ __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */ __I uint32_t STATUS; /**< Status register, offset: 0x8 */ __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override Register, offset: 0xC */ __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */ __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */ union { /* offset: 0x18 */ __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */ __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */ }; } USBHSDCD_Type; /* ---------------------------------------------------------------------------- -- USBHSDCD Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks * @{ */ /*! @name CONTROL - Control register */ /*! @{ */ #define USBHSDCD_CONTROL_IACK_MASK (0x1U) #define USBHSDCD_CONTROL_IACK_SHIFT (0U) /*! IACK - Interrupt Acknowledge * 0b0..Do not clear the interrupt. * 0b1..Clear the IF bit (interrupt flag). */ #define USBHSDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK) #define USBHSDCD_CONTROL_IF_MASK (0x100U) #define USBHSDCD_CONTROL_IF_SHIFT (8U) /*! IF - Interrupt Flag * 0b0..No interrupt is pending. * 0b1..An interrupt is pending. */ #define USBHSDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK) #define USBHSDCD_CONTROL_IE_MASK (0x10000U) #define USBHSDCD_CONTROL_IE_SHIFT (16U) /*! IE - Interrupt Enable * 0b0..Disable interrupts to the system. * 0b1..Enable interrupts to the system. */ #define USBHSDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK) #define USBHSDCD_CONTROL_BC12_MASK (0x20000U) #define USBHSDCD_CONTROL_BC12_SHIFT (17U) /*! BC12 - BC12 * 0b0..Compatible with BC1.1 (default) * 0b1..Compatible with BC1.2 */ #define USBHSDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK) #define USBHSDCD_CONTROL_START_MASK (0x1000000U) #define USBHSDCD_CONTROL_START_SHIFT (24U) /*! START - Start Change Detection Sequence * 0b0..Do not start the sequence. Writes of this value have no effect. * 0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect. */ #define USBHSDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK) #define USBHSDCD_CONTROL_SR_MASK (0x2000000U) #define USBHSDCD_CONTROL_SR_SHIFT (25U) /*! SR - Software Reset * 0b0..Do not perform a software reset. * 0b1..Perform a software reset. */ #define USBHSDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK) /*! @} */ /*! @name CLOCK - Clock register */ /*! @{ */ #define USBHSDCD_CLOCK_CLOCK_UNIT_MASK (0x1U) #define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT (0U) /*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed * 0b0..kHz Speed (between 1 kHz and 1023 kHz) * 0b1..MHz Speed (between 1 MHz and 1023 MHz) */ #define USBHSDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK) #define USBHSDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU) #define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT (2U) /*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary */ #define USBHSDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK) /*! @} */ /*! @name STATUS - Status register */ /*! @{ */ #define USBHSDCD_STATUS_SEQ_RES_MASK (0x30000U) #define USBHSDCD_STATUS_SEQ_RES_SHIFT (16U) /*! SEQ_RES - Charger Detection Sequence Results * 0b00..No results to report. * 0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected. * 0b10..Attached to a charging port. The exact meaning depends on bit 18 (value 0: Attached to either a CDP or a * DCP. The charger type detection has not completed. value 1: Attached to a CDP. The charger type * detection has completed.) * 0b11..Attached to a DCP. */ #define USBHSDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK) #define USBHSDCD_STATUS_SEQ_STAT_MASK (0xC0000U) #define USBHSDCD_STATUS_SEQ_STAT_SHIFT (18U) /*! SEQ_STAT - Charger Detection Sequence Status * 0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected. * 0b01..Data pin contact detection is complete. * 0b10..Charging port detection is complete. * 0b11..Charger type detection is complete. */ #define USBHSDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK) #define USBHSDCD_STATUS_ERR_MASK (0x100000U) #define USBHSDCD_STATUS_ERR_SHIFT (20U) /*! ERR - Error Flag * 0b0..No sequence errors. * 0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred. */ #define USBHSDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK) #define USBHSDCD_STATUS_TO_MASK (0x200000U) #define USBHSDCD_STATUS_TO_SHIFT (21U) /*! TO - Timeout Flag * 0b0..The detection sequence has not been running for over 1 s. * 0b1..It has been over 1 s since the data pin contact was detected and debounced. */ #define USBHSDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK) #define USBHSDCD_STATUS_ACTIVE_MASK (0x400000U) #define USBHSDCD_STATUS_ACTIVE_SHIFT (22U) /*! ACTIVE - Active Status Indicator * 0b0..The sequence is not running. * 0b1..The sequence is running. */ #define USBHSDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK) /*! @} */ /*! @name SIGNAL_OVERRIDE - Signal Override Register */ /*! @{ */ #define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U) #define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U) /*! PS - Phase Selection * 0b00..No overrides. Bit field must remain at this value during normal USB data communication to prevent * unexpected conditions on USB_DP and USB_DM pins. (Default) * 0b01..Reserved, not for customer use. * 0b10..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin. * 0b11..Reserved, not for customer use. */ #define USBHSDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK) /*! @} */ /*! @name TIMER0 - TIMER0 register */ /*! @{ */ #define USBHSDCD_TIMER0_TUNITCON_MASK (0xFFFU) #define USBHSDCD_TIMER0_TUNITCON_SHIFT (0U) /*! TUNITCON - Unit Connection Timer Elapse (in ms) */ #define USBHSDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK) #define USBHSDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U) #define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT (16U) /*! TSEQ_INIT - Sequence Initiation Time */ #define USBHSDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK) /*! @} */ /*! @name TIMER1 - TIMER1 register */ /*! @{ */ #define USBHSDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU) #define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT (0U) /*! TVDPSRC_ON - Time Period Comparator Enabled */ #define USBHSDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK) #define USBHSDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U) #define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT (16U) /*! TDCD_DBNC - Time Period to Debounce D+ Signal */ #define USBHSDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK) /*! @} */ /*! @name TIMER2_BC11 - TIMER2_BC11 register */ /*! @{ */ #define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU) #define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U) /*! CHECK_DM - Time Before Check of D- Line */ #define USBHSDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK) #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U) #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U) /*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup */ #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK) /*! @} */ /*! @name TIMER2_BC12 - TIMER2_BC12 register */ /*! @{ */ #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU) #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U) /*! TVDMSRC_ON - TVDMSRC_ON */ #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK) #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U) #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U) /*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD */ #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) /*! @} */ /*! * @} */ /* end of group USBHSDCD_Register_Masks */ /* USBHSDCD - Peripheral instance base addresses */ /** Peripheral DCD base address */ #define DCD_BASE (0x40350800u) /** Peripheral DCD base pointer */ #define DCD ((USBHSDCD_Type *)DCD_BASE) /** Array initializer of USBHSDCD peripheral base addresses */ #define USBHSDCD_BASE_ADDRS { DCD_BASE } /** Array initializer of USBHSDCD peripheral base pointers */ #define USBHSDCD_BASE_PTRS { DCD } /*! * @} */ /* end of group USBHSDCD_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USBNC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer * @{ */ /** USBNC - Register Layout Typedef */ typedef struct { __IO uint32_t OTGn_CTRL1; /**< USB OTG Control 1 Register, offset: 0x0 */ __IO uint32_t OTGn_CTRL2; /**< USB OTG Control 2 Register, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t OTGn_HSIC_CTRL; /**< USB Host HSIC Control Register, offset: 0x10 */ } USBNC_Type; /* ---------------------------------------------------------------------------- -- USBNC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBNC_Register_Masks USBNC Register Masks * @{ */ /*! @name OTGn_CTRL1 - USB OTG Control 1 Register */ /*! @{ */ #define USBNC_OTGn_CTRL1_OVER_CUR_DIS_MASK (0x80U) #define USBNC_OTGn_CTRL1_OVER_CUR_DIS_SHIFT (7U) /*! OVER_CUR_DIS * 0b1..Disables overcurrent detection * 0b0..Enables overcurrent detection */ #define USBNC_OTGn_CTRL1_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_OTGn_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_OTGn_CTRL1_OVER_CUR_DIS_MASK) #define USBNC_OTGn_CTRL1_OVER_CUR_POL_MASK (0x100U) #define USBNC_OTGn_CTRL1_OVER_CUR_POL_SHIFT (8U) /*! OVER_CUR_POL * 0b1..Low active (low on this signal represents an overcurrent condition) * 0b0..High active (high on this signal represents an overcurrent condition) */ #define USBNC_OTGn_CTRL1_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_OTGn_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_OTGn_CTRL1_OVER_CUR_POL_MASK) #define USBNC_OTGn_CTRL1_PWR_POL_MASK (0x200U) #define USBNC_OTGn_CTRL1_PWR_POL_SHIFT (9U) /*! PWR_POL * 0b1..PMIC Power Pin is High active. * 0b0..PMIC Power Pin is Low active. */ #define USBNC_OTGn_CTRL1_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_OTGn_CTRL1_PWR_POL_SHIFT)) & USBNC_OTGn_CTRL1_PWR_POL_MASK) #define USBNC_OTGn_CTRL1_WIE_MASK (0x400U) #define USBNC_OTGn_CTRL1_WIE_SHIFT (10U) /*! WIE * 0b1..Interrupt Enabled * 0b0..Interrupt Disabled */ #define USBNC_OTGn_CTRL1_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_OTGn_CTRL1_WIE_SHIFT)) & USBNC_OTGn_CTRL1_WIE_MASK) #define USBNC_OTGn_CTRL1_WKUP_SW_EN_MASK (0x4000U) #define USBNC_OTGn_CTRL1_WKUP_SW_EN_SHIFT (14U) /*! WKUP_SW_EN * 0b1..Enable * 0b0..Disable */ #define USBNC_OTGn_CTRL1_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_OTGn_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_OTGn_CTRL1_WKUP_SW_EN_MASK) #define USBNC_OTGn_CTRL1_WKUP_SW_MASK (0x8000U) #define USBNC_OTGn_CTRL1_WKUP_SW_SHIFT (15U) /*! WKUP_SW * 0b1..Force wake-up * 0b0..Inactive */ #define USBNC_OTGn_CTRL1_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_OTGn_CTRL1_WKUP_SW_SHIFT)) & USBNC_OTGn_CTRL1_WKUP_SW_MASK) #define USBNC_OTGn_CTRL1_WKUP_ID_EN_MASK (0x10000U) #define USBNC_OTGn_CTRL1_WKUP_ID_EN_SHIFT (16U) /*! WKUP_ID_EN * 0b1..Enable * 0b0..Disable */ #define USBNC_OTGn_CTRL1_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_OTGn_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_OTGn_CTRL1_WKUP_ID_EN_MASK) #define USBNC_OTGn_CTRL1_WKUP_VBUS_EN_MASK (0x20000U) #define USBNC_OTGn_CTRL1_WKUP_VBUS_EN_SHIFT (17U) /*! WKUP_VBUS_EN * 0b1..Enable * 0b0..Disable */ #define USBNC_OTGn_CTRL1_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_OTGn_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_OTGn_CTRL1_WKUP_VBUS_EN_MASK) #define USBNC_OTGn_CTRL1_ULPI_PHY_CLK_EN_MASK (0x100000U) #define USBNC_OTGn_CTRL1_ULPI_PHY_CLK_EN_SHIFT (20U) /*! ULPI_PHY_CLK_EN - ULPI PHY clock enable * 0b1..Enable * 0b0..Disable */ #define USBNC_OTGn_CTRL1_ULPI_PHY_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_OTGn_CTRL1_ULPI_PHY_CLK_EN_SHIFT)) & USBNC_OTGn_CTRL1_ULPI_PHY_CLK_EN_MASK) #define USBNC_OTGn_CTRL1_WKUP_DPDM_EN_MASK (0x20000000U) #define USBNC_OTGn_CTRL1_WKUP_DPDM_EN_SHIFT (29U) /*! WKUP_DPDM_EN - Wake-up on DPDM change enable * 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only. * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0. */ #define USBNC_OTGn_CTRL1_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_OTGn_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_OTGn_CTRL1_WKUP_DPDM_EN_MASK) #define USBNC_OTGn_CTRL1_WIR_MASK (0x80000000U) #define USBNC_OTGn_CTRL1_WIR_SHIFT (31U) /*! WIR * 0b1..Wake-up Interrupt Request received * 0b0..No wake-up interrupt request received */ #define USBNC_OTGn_CTRL1_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_OTGn_CTRL1_WIR_SHIFT)) & USBNC_OTGn_CTRL1_WIR_MASK) /*! @} */ /*! @name OTGn_CTRL2 - USB OTG Control 2 Register */ /*! @{ */ #define USBNC_OTGn_CTRL2_VBUS_SOURCE_SEL_MASK (0x3U) #define USBNC_OTGn_CTRL2_VBUS_SOURCE_SEL_SHIFT (0U) #define USBNC_OTGn_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_OTGn_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_OTGn_CTRL2_VBUS_SOURCE_SEL_MASK) #define USBNC_OTGn_CTRL2_AUTURESUME_EN_MASK (0x4U) #define USBNC_OTGn_CTRL2_AUTURESUME_EN_SHIFT (2U) /*! AUTURESUME_EN - Auto Resume Enable * 0b0..Default */ #define USBNC_OTGn_CTRL2_AUTURESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_OTGn_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_OTGn_CTRL2_AUTURESUME_EN_MASK) #define USBNC_OTGn_CTRL2_LOWSPEED_EN_MASK (0x8U) #define USBNC_OTGn_CTRL2_LOWSPEED_EN_SHIFT (3U) /*! LOWSPEED_EN * 0b0..Default */ #define USBNC_OTGn_CTRL2_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_OTGn_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_OTGn_CTRL2_LOWSPEED_EN_MASK) #define USBNC_OTGn_CTRL2_UTMI_CLK_VLD_MASK (0x80000000U) #define USBNC_OTGn_CTRL2_UTMI_CLK_VLD_SHIFT (31U) /*! UTMI_CLK_VLD * 0b0..Default */ #define USBNC_OTGn_CTRL2_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_OTGn_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_OTGn_CTRL2_UTMI_CLK_VLD_MASK) /*! @} */ /*! @name OTGn_HSIC_CTRL - USB Host HSIC Control Register */ /*! @{ */ #define USBNC_OTGn_HSIC_CTRL_HSIC_CLK_ON_MASK (0x800U) #define USBNC_OTGn_HSIC_CTRL_HSIC_CLK_ON_SHIFT (11U) /*! HSIC_CLK_ON * 0b1..Active * 0b0..Inactive */ #define USBNC_OTGn_HSIC_CTRL_HSIC_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USBNC_OTGn_HSIC_CTRL_HSIC_CLK_ON_SHIFT)) & USBNC_OTGn_HSIC_CTRL_HSIC_CLK_ON_MASK) #define USBNC_OTGn_HSIC_CTRL_HSIC_EN_MASK (0x1000U) #define USBNC_OTGn_HSIC_CTRL_HSIC_EN_SHIFT (12U) /*! HSIC_EN * 0b1..Enabled * 0b0..Disabled */ #define USBNC_OTGn_HSIC_CTRL_HSIC_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_OTGn_HSIC_CTRL_HSIC_EN_SHIFT)) & USBNC_OTGn_HSIC_CTRL_HSIC_EN_MASK) #define USBNC_OTGn_HSIC_CTRL_CLK_VLD_MASK (0x80000000U) #define USBNC_OTGn_HSIC_CTRL_CLK_VLD_SHIFT (31U) /*! CLK_VLD * 0b1..Valid */ #define USBNC_OTGn_HSIC_CTRL_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_OTGn_HSIC_CTRL_CLK_VLD_SHIFT)) & USBNC_OTGn_HSIC_CTRL_CLK_VLD_MASK) /*! @} */ /*! * @} */ /* end of group USBNC_Register_Masks */ /* USBNC - Peripheral instance base addresses */ /** Peripheral USBNC0 base address */ #define USBNC0_BASE (0x40330200u) /** Peripheral USBNC0 base pointer */ #define USBNC0 ((USBNC_Type *)USBNC0_BASE) /** Peripheral USBNC1 base address */ #define USBNC1_BASE (0x40340200u) /** Peripheral USBNC1 base pointer */ #define USBNC1 ((USBNC_Type *)USBNC1_BASE) /** Array initializer of USBNC peripheral base addresses */ #define USBNC_BASE_ADDRS { USBNC0_BASE, USBNC1_BASE } /** Array initializer of USBNC peripheral base pointers */ #define USBNC_BASE_PTRS { USBNC0, USBNC1 } /*! * @} */ /* end of group USBNC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USBPHY Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer * @{ */ /** USBPHY - Register Layout Typedef */ typedef struct { __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ uint8_t RESERVED_0[12]; __IO uint32_t DEBUG0; /**< USB PHY Debug Register 0, offset: 0x50 */ __IO uint32_t DEBUG0_SET; /**< USB PHY Debug Register 0, offset: 0x54 */ __IO uint32_t DEBUG0_CLR; /**< USB PHY Debug Register 0, offset: 0x58 */ __IO uint32_t DEBUG0_TOG; /**< USB PHY Debug Register 0, offset: 0x5C */ uint8_t RESERVED_1[16]; __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ uint8_t RESERVED_2[28]; __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */ __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */ __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */ __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */ uint8_t RESERVED_3[16]; __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */ __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */ __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */ __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */ __I uint32_t USB1_VBUS_DET_STAT; /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */ uint8_t RESERVED_4[12]; __IO uint32_t USB1_CHRG_DETECT; /**< USB PHY Charger Detect Control Register, offset: 0xE0 */ __IO uint32_t USB1_CHRG_DETECT_SET; /**< USB PHY Charger Detect Control Register, offset: 0xE4 */ __IO uint32_t USB1_CHRG_DETECT_CLR; /**< USB PHY Charger Detect Control Register, offset: 0xE8 */ __IO uint32_t USB1_CHRG_DETECT_TOG; /**< USB PHY Charger Detect Control Register, offset: 0xEC */ __I uint32_t USB1_CHRG_DET_STAT; /**< USB PHY Charger Detect Status Register, offset: 0xF0 */ uint8_t RESERVED_5[12]; __IO uint32_t ANACTRL; /**< USB PHY Analog Control Register, offset: 0x100 */ __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */ __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */ __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */ __IO uint32_t USB1_LOOPBACK; /**< USB PHY Loopback Control/Status Register, offset: 0x110 */ __IO uint32_t USB1_LOOPBACK_SET; /**< USB PHY Loopback Control/Status Register, offset: 0x114 */ __IO uint32_t USB1_LOOPBACK_CLR; /**< USB PHY Loopback Control/Status Register, offset: 0x118 */ __IO uint32_t USB1_LOOPBACK_TOG; /**< USB PHY Loopback Control/Status Register, offset: 0x11C */ __IO uint32_t USB1_LOOPBACK_HSFSCNT; /**< USB PHY Loopback Packet Number Select Register, offset: 0x120 */ __IO uint32_t USB1_LOOPBACK_HSFSCNT_SET; /**< USB PHY Loopback Packet Number Select Register, offset: 0x124 */ __IO uint32_t USB1_LOOPBACK_HSFSCNT_CLR; /**< USB PHY Loopback Packet Number Select Register, offset: 0x128 */ __IO uint32_t USB1_LOOPBACK_HSFSCNT_TOG; /**< USB PHY Loopback Packet Number Select Register, offset: 0x12C */ __IO uint32_t TRIM_OVERRIDE_EN; /**< USB PHY Trim Override Enable Register, offset: 0x130 */ __IO uint32_t TRIM_OVERRIDE_EN_SET; /**< USB PHY Trim Override Enable Register, offset: 0x134 */ __IO uint32_t TRIM_OVERRIDE_EN_CLR; /**< USB PHY Trim Override Enable Register, offset: 0x138 */ __IO uint32_t TRIM_OVERRIDE_EN_TOG; /**< USB PHY Trim Override Enable Register, offset: 0x13C */ } USBPHY_Type; /* ---------------------------------------------------------------------------- -- USBPHY Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBPHY_Register_Masks USBPHY Register Masks * @{ */ /*! @name PWD - USB PHY Power-Down Register */ /*! @{ */ #define USBPHY_PWD_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_TXPWDFS_SHIFT (10U) /*! TXPWDFS * 0b0..Normal operation. * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output */ #define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) #define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS * 0b0..Normal operation * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB * is in suspend mode. This effectively powers down the entire USB transmit path */ #define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) #define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I * 0b0..Normal operation. * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror */ #define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) #define USBPHY_PWD_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_RXPWDENV_SHIFT (17U) /*! RXPWDENV * 0b0..Normal operation. * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) */ #define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) #define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 * 0b0..Normal operation * 0b1..Power-down the USB full-speed differential receiver. */ #define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) #define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF * 0b0..Normal operation. * 0b1..Power-down the USB high-speed differential receiver */ #define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) #define USBPHY_PWD_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_RXPWDRX_SHIFT (20U) /*! RXPWDRX * 0b0..Normal operation * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver */ #define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) /*! @} */ /*! @name PWD_SET - USB PHY Power-Down Register */ /*! @{ */ #define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) /*! TXPWDFS * 0b0..Normal operation. * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output */ #define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) #define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS * 0b0..Normal operation * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB * is in suspend mode. This effectively powers down the entire USB transmit path */ #define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) #define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I * 0b0..Normal operation. * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror */ #define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) #define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) /*! RXPWDENV * 0b0..Normal operation. * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) */ #define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) #define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 * 0b0..Normal operation * 0b1..Power-down the USB full-speed differential receiver. */ #define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) #define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF * 0b0..Normal operation. * 0b1..Power-down the USB high-speed differential receiver */ #define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) #define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) /*! RXPWDRX * 0b0..Normal operation * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver */ #define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) /*! @} */ /*! @name PWD_CLR - USB PHY Power-Down Register */ /*! @{ */ #define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) /*! TXPWDFS * 0b0..Normal operation. * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output */ #define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS * 0b0..Normal operation * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB * is in suspend mode. This effectively powers down the entire USB transmit path */ #define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) #define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I * 0b0..Normal operation. * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror */ #define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) #define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) /*! RXPWDENV * 0b0..Normal operation. * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) */ #define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) #define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 * 0b0..Normal operation * 0b1..Power-down the USB full-speed differential receiver. */ #define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) #define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF * 0b0..Normal operation. * 0b1..Power-down the USB high-speed differential receiver */ #define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) #define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) /*! RXPWDRX * 0b0..Normal operation * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver */ #define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) /*! @} */ /*! @name PWD_TOG - USB PHY Power-Down Register */ /*! @{ */ #define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) /*! TXPWDFS * 0b0..Normal operation. * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output */ #define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS * 0b0..Normal operation * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB * is in suspend mode. This effectively powers down the entire USB transmit path */ #define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) #define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I * 0b0..Normal operation. * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror */ #define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) #define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) /*! RXPWDENV * 0b0..Normal operation. * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) */ #define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) #define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 * 0b0..Normal operation * 0b1..Power-down the USB full-speed differential receiver. */ #define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) #define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF * 0b0..Normal operation. * 0b1..Power-down the USB high-speed differential receiver */ #define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) #define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) /*! RXPWDRX * 0b0..Normal operation * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver */ #define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) /*! @} */ /*! @name TX - USB PHY Transmitter Control Register */ /*! @{ */ #define USBPHY_TX_D_CAL_MASK (0xFU) #define USBPHY_TX_D_CAL_SHIFT (0U) /*! D_CAL * 0b0000..Maximum current, approximately 19% above nominal. * 0b0111..Nominal * 0b1111..Minimum current, approximately 19% below nominal. */ #define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) #define USBPHY_TX_TXCAL45DM_MASK (0xF00U) #define USBPHY_TX_TXCAL45DM_SHIFT (8U) #define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK) #define USBPHY_TX_TXENCAL45DN_MASK (0x2000U) #define USBPHY_TX_TXENCAL45DN_SHIFT (13U) #define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK) #define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_TXCAL45DP_SHIFT (16U) #define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) #define USBPHY_TX_TXENCAL45DP_MASK (0x200000U) #define USBPHY_TX_TXENCAL45DP_SHIFT (21U) #define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK) /*! @} */ /*! @name TX_SET - USB PHY Transmitter Control Register */ /*! @{ */ #define USBPHY_TX_SET_D_CAL_MASK (0xFU) #define USBPHY_TX_SET_D_CAL_SHIFT (0U) /*! D_CAL * 0b0000..Maximum current, approximately 19% above nominal. * 0b0111..Nominal * 0b1111..Minimum current, approximately 19% below nominal. */ #define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) #define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U) #define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U) #define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK) #define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U) #define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U) #define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK) #define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) #define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) #define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U) #define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U) #define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK) /*! @} */ /*! @name TX_CLR - USB PHY Transmitter Control Register */ /*! @{ */ #define USBPHY_TX_CLR_D_CAL_MASK (0xFU) #define USBPHY_TX_CLR_D_CAL_SHIFT (0U) /*! D_CAL * 0b0000..Maximum current, approximately 19% above nominal. * 0b0111..Nominal * 0b1111..Minimum current, approximately 19% below nominal. */ #define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) #define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U) #define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U) #define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK) #define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U) #define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U) #define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK) #define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) #define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) #define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U) #define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U) #define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK) /*! @} */ /*! @name TX_TOG - USB PHY Transmitter Control Register */ /*! @{ */ #define USBPHY_TX_TOG_D_CAL_MASK (0xFU) #define USBPHY_TX_TOG_D_CAL_SHIFT (0U) /*! D_CAL * 0b0000..Maximum current, approximately 19% above nominal. * 0b0111..Nominal * 0b1111..Minimum current, approximately 19% below nominal. */ #define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) #define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U) #define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U) #define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK) #define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U) #define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U) #define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK) #define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) #define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) #define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U) #define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U) #define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK) /*! @} */ /*! @name RX - USB PHY Receiver Control Register */ /*! @{ */ #define USBPHY_RX_ENVADJ_MASK (0x7U) #define USBPHY_RX_ENVADJ_SHIFT (0U) /*! ENVADJ * 0b000..Trip-Level Voltage is 0.1000 V * 0b001..Trip-Level Voltage is 0.1125 V * 0b010..Trip-Level Voltage is 0.1250 V * 0b011..Trip-Level Voltage is 0.0875 V * 0b1xx..Reserved */ #define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) #define USBPHY_RX_DISCONADJ_MASK (0x70U) #define USBPHY_RX_DISCONADJ_SHIFT (4U) /*! DISCONADJ * 0b000..Trip-Level Voltage is 0.56875 V * 0b001..Trip-Level Voltage is 0.55000 V * 0b010..Trip-Level Voltage is 0.58125 V * 0b011..Trip-Level Voltage is 0.60000 V * 0b1xx..Reserved */ #define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) #define USBPHY_RX_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_RXDBYPASS_SHIFT (22U) /*! RXDBYPASS * 0b0..Normal operation. * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver */ #define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) /*! @} */ /*! @name RX_SET - USB PHY Receiver Control Register */ /*! @{ */ #define USBPHY_RX_SET_ENVADJ_MASK (0x7U) #define USBPHY_RX_SET_ENVADJ_SHIFT (0U) /*! ENVADJ * 0b000..Trip-Level Voltage is 0.1000 V * 0b001..Trip-Level Voltage is 0.1125 V * 0b010..Trip-Level Voltage is 0.1250 V * 0b011..Trip-Level Voltage is 0.0875 V * 0b1xx..Reserved */ #define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) #define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) #define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) /*! DISCONADJ * 0b000..Trip-Level Voltage is 0.56875 V * 0b001..Trip-Level Voltage is 0.55000 V * 0b010..Trip-Level Voltage is 0.58125 V * 0b011..Trip-Level Voltage is 0.60000 V * 0b1xx..Reserved */ #define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) #define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) /*! RXDBYPASS * 0b0..Normal operation. * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver */ #define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) /*! @} */ /*! @name RX_CLR - USB PHY Receiver Control Register */ /*! @{ */ #define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) #define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) /*! ENVADJ * 0b000..Trip-Level Voltage is 0.1000 V * 0b001..Trip-Level Voltage is 0.1125 V * 0b010..Trip-Level Voltage is 0.1250 V * 0b011..Trip-Level Voltage is 0.0875 V * 0b1xx..Reserved */ #define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) #define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) #define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) /*! DISCONADJ * 0b000..Trip-Level Voltage is 0.56875 V * 0b001..Trip-Level Voltage is 0.55000 V * 0b010..Trip-Level Voltage is 0.58125 V * 0b011..Trip-Level Voltage is 0.60000 V * 0b1xx..Reserved */ #define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) #define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) /*! RXDBYPASS * 0b0..Normal operation. * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver */ #define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) /*! @} */ /*! @name RX_TOG - USB PHY Receiver Control Register */ /*! @{ */ #define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) #define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) /*! ENVADJ * 0b000..Trip-Level Voltage is 0.1000 V * 0b001..Trip-Level Voltage is 0.1125 V * 0b010..Trip-Level Voltage is 0.1250 V * 0b011..Trip-Level Voltage is 0.0875 V * 0b1xx..Reserved */ #define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) #define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) #define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) /*! DISCONADJ * 0b000..Trip-Level Voltage is 0.56875 V * 0b001..Trip-Level Voltage is 0.55000 V * 0b010..Trip-Level Voltage is 0.58125 V * 0b011..Trip-Level Voltage is 0.60000 V * 0b1xx..Reserved */ #define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) #define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) /*! RXDBYPASS * 0b0..Normal operation. * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver */ #define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) /*! @} */ /*! @name CTRL - USB PHY General Control Register */ /*! @{ */ #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) #define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U) #define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U) /*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins */ #define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK) #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) #define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) #define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) #define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) #define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) #define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) #define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) #define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) #define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) #define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) #define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) #define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) #define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_CLKGATE_SHIFT (30U) #define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) #define USBPHY_CTRL_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SFTRST_SHIFT (31U) #define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) /*! @} */ /*! @name CTRL_SET - USB PHY General Control Register */ /*! @{ */ #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U) #define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U) /*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins */ #define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK) #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) #define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) #define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) #define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) #define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) #define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) #define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) #define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) #define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) #define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) #define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) #define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) /*! @} */ /*! @name CTRL_CLR - USB PHY General Control Register */ /*! @{ */ #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U) #define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U) /*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins */ #define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK) #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) #define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) #define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) #define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) #define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) #define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) #define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) #define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) #define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) #define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) /*! @} */ /*! @name CTRL_TOG - USB PHY General Control Register */ /*! @{ */ #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U) #define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U) /*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins */ #define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK) #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) #define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) #define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) #define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) #define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) #define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) #define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) #define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) #define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) #define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) /*! @} */ /*! @name STATUS - USB PHY Status Register */ /*! @{ */ #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) /*! HOSTDISCONDETECT_STATUS * 0b0..USB cable disconnect has not been detected at the local host * 0b1..USB cable disconnect has been detected at the local host */ #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) /*! DEVPLUGIN_STATUS - Status indicator for non-standard resistive plugged-in detection * 0b0..No attachment to a USB host is detected * 0b1..Cable attachment to a USB host is detected */ #define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) #define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) #define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) #define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) #define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) #define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) #define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) /*! @} */ /*! @name DEBUG0 - USB PHY Debug Register 0 */ /*! @{ */ #define USBPHY_DEBUG0_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG0_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_OTGIDPIOLOCK_MASK) #define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK (0x2U) #define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT (1U) #define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK) #define USBPHY_DEBUG0_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT (2U) #define USBPHY_DEBUG0_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT (4U) #define USBPHY_DEBUG0_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK) #define USBPHY_DEBUG0_TX2RXCOUNT_MASK (0xF00U) #define USBPHY_DEBUG0_TX2RXCOUNT_SHIFT (8U) #define USBPHY_DEBUG0_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TX2RXCOUNT_MASK) #define USBPHY_DEBUG0_ENTX2RXCOUNT_MASK (0x1000U) #define USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT (12U) #define USBPHY_DEBUG0_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_ENTX2RXCOUNT_MASK) #define USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK (0x1F0000U) #define USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT (16U) #define USBPHY_DEBUG0_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK) #define USBPHY_DEBUG0_ENSQUELCHRESET_MASK (0x1000000U) #define USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT (24U) #define USBPHY_DEBUG0_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_ENSQUELCHRESET_MASK) #define USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK (0x1E000000U) #define USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT (25U) #define USBPHY_DEBUG0_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK) #define USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK (0x20000000U) #define USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT (29U) #define USBPHY_DEBUG0_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK) #define USBPHY_DEBUG0_CLKGATE_MASK (0x40000000U) #define USBPHY_DEBUG0_CLKGATE_SHIFT (30U) #define USBPHY_DEBUG0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLKGATE_MASK) /*! @} */ /*! @name DEBUG0_SET - USB PHY Debug Register 0 */ /*! @{ */ #define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG0_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK) #define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) #define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) #define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK) #define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT (2U) #define USBPHY_DEBUG0_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT (4U) #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK) #define USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK (0xF00U) #define USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT (8U) #define USBPHY_DEBUG0_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK) #define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK (0x1000U) #define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT (12U) #define USBPHY_DEBUG0_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK) #define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) #define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT (16U) #define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK) #define USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK (0x1000000U) #define USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT (24U) #define USBPHY_DEBUG0_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK) #define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) #define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT (25U) #define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK) #define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) #define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT (29U) #define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK) #define USBPHY_DEBUG0_SET_CLKGATE_MASK (0x40000000U) #define USBPHY_DEBUG0_SET_CLKGATE_SHIFT (30U) #define USBPHY_DEBUG0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG0_SET_CLKGATE_MASK) /*! @} */ /*! @name DEBUG0_CLR - USB PHY Debug Register 0 */ /*! @{ */ #define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK) #define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) #define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) #define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK) #define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT (2U) #define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT (4U) #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK) #define USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK (0xF00U) #define USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT (8U) #define USBPHY_DEBUG0_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK) #define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK (0x1000U) #define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT (12U) #define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK) #define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) #define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT (16U) #define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK) #define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK (0x1000000U) #define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT (24U) #define USBPHY_DEBUG0_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK) #define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) #define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT (25U) #define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK) #define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) #define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT (29U) #define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK) #define USBPHY_DEBUG0_CLR_CLKGATE_MASK (0x40000000U) #define USBPHY_DEBUG0_CLR_CLKGATE_SHIFT (30U) #define USBPHY_DEBUG0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLR_CLKGATE_MASK) /*! @} */ /*! @name DEBUG0_TOG - USB PHY Debug Register 0 */ /*! @{ */ #define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK) #define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) #define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) #define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK) #define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT (2U) #define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT (4U) #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK) #define USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK (0xF00U) #define USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT (8U) #define USBPHY_DEBUG0_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK) #define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK (0x1000U) #define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT (12U) #define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK) #define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) #define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT (16U) #define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK) #define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK (0x1000000U) #define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT (24U) #define USBPHY_DEBUG0_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK) #define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) #define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT (25U) #define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK) #define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) #define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT (29U) #define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK) #define USBPHY_DEBUG0_TOG_CLKGATE_MASK (0x40000000U) #define USBPHY_DEBUG0_TOG_CLKGATE_SHIFT (30U) #define USBPHY_DEBUG0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG0_TOG_CLKGATE_MASK) /*! @} */ /*! @name DEBUG1 - UTMI Debug Status Register 1 */ /*! @{ */ #define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) #define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) /*! ENTAILADJVD * 0b00..Delay is nominal * 0b01..Delay is +20% * 0b10..Delay is -20% * 0b11..Delay is -40% */ #define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT (18U) /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */ #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK) #define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK (0x600000U) #define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT (21U) /*! USB2_REFBIAS_TST - Bias current control for usb2_phy */ #define USBPHY_DEBUG1_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK) /*! @} */ /*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ /*! @{ */ #define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) #define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) /*! ENTAILADJVD * 0b00..Delay is nominal * 0b01..Delay is +20% * 0b10..Delay is -20% * 0b11..Delay is -40% */ #define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U) /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */ #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK) #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK (0x600000U) #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U) /*! USB2_REFBIAS_TST - Bias current control for usb2_phy */ #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK) /*! @} */ /*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ /*! @{ */ #define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) #define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) /*! ENTAILADJVD * 0b00..Delay is nominal * 0b01..Delay is +20% * 0b10..Delay is -20% * 0b11..Delay is -40% */ #define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U) /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */ #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK) #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK (0x600000U) #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U) /*! USB2_REFBIAS_TST - Bias current control for usb2_phy */ #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK) /*! @} */ /*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ /*! @{ */ #define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) #define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) /*! ENTAILADJVD * 0b00..Delay is nominal * 0b01..Delay is +20% * 0b10..Delay is -20% * 0b11..Delay is -40% */ #define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U) /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */ #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK) #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK (0x600000U) #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U) /*! USB2_REFBIAS_TST - Bias current control for usb2_phy */ #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK) /*! @} */ /*! @name VERSION - UTMI RTL Version */ /*! @{ */ #define USBPHY_VERSION_STEP_MASK (0xFFFFU) #define USBPHY_VERSION_STEP_SHIFT (0U) #define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) #define USBPHY_VERSION_MINOR_MASK (0xFF0000U) #define USBPHY_VERSION_MINOR_SHIFT (16U) #define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) #define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) #define USBPHY_VERSION_MAJOR_SHIFT (24U) #define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) /*! @} */ /*! @name PLL_SIC - USB PHY PLL Control/Status Register */ /*! @{ */ #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) #define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) #define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) #define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U) #define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U) #define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK) #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL * 0b0..Selects PLL_POWER to control the reference bias * 0b1..Selects REFBIAS_PWD to control the reference bias. */ #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) /*! REFBIAS_PWD - Power down the reference bias */ #define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) #define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL * 0b000..Divide by 13 * 0b001..Divide by 15 * 0b010..Divide by 16 * 0b011..Divide by 20 * 0b100..Divide by 22 * 0b101..Divide by 25 * 0b110..Divide by 30 * 0b111..Divide by 240 */ #define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK * 0b0..PLL is not currently locked * 0b1..PLL is currently locked */ #define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) /*! @} */ /*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */ /*! @{ */ #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) #define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) #define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) #define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U) #define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U) #define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL * 0b0..Selects PLL_POWER to control the reference bias * 0b1..Selects REFBIAS_PWD to control the reference bias. */ #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) /*! REFBIAS_PWD - Power down the reference bias */ #define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL * 0b000..Divide by 13 * 0b001..Divide by 15 * 0b010..Divide by 16 * 0b011..Divide by 20 * 0b100..Divide by 22 * 0b101..Divide by 25 * 0b110..Divide by 30 * 0b111..Divide by 240 */ #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK * 0b0..PLL is not currently locked * 0b1..PLL is currently locked */ #define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) /*! @} */ /*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */ /*! @{ */ #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) #define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) #define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U) #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U) #define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL * 0b0..Selects PLL_POWER to control the reference bias * 0b1..Selects REFBIAS_PWD to control the reference bias. */ #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) /*! REFBIAS_PWD - Power down the reference bias */ #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL * 0b000..Divide by 13 * 0b001..Divide by 15 * 0b010..Divide by 16 * 0b011..Divide by 20 * 0b100..Divide by 22 * 0b101..Divide by 25 * 0b110..Divide by 30 * 0b111..Divide by 240 */ #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK * 0b0..PLL is not currently locked * 0b1..PLL is currently locked */ #define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) /*! @} */ /*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */ /*! @{ */ #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) #define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) #define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U) #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U) #define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL * 0b0..Selects PLL_POWER to control the reference bias * 0b1..Selects REFBIAS_PWD to control the reference bias. */ #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) /*! REFBIAS_PWD - Power down the reference bias */ #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL * 0b000..Divide by 13 * 0b001..Divide by 15 * 0b010..Divide by 16 * 0b011..Divide by 20 * 0b100..Divide by 22 * 0b101..Divide by 25 * 0b110..Divide by 30 * 0b111..Divide by 240 */ #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK * 0b0..PLL is not currently locked * 0b1..PLL is currently locked */ #define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH * 0b000..4.0 V * 0b001..4.1 V * 0b010..4.2 V * 0b011..4.3 V * 0b100..4.4 V (Default) * 0b101..4.5 V * 0b110..4.6 V * 0b111..4.7 V */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) /*! SESSEND_OVERRIDE - Override value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) /*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) /*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) * 0b01..Use the Session Valid comparator results for signal reported to the USB controller * 0b10..Use the Session Valid comparator results for signal reported to the USB controller * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x100000U) #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - Enables the VBUS_VALID comparator * 0b0..Powers down the VBUS_VALID comparator * 0b1..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS - Controls VBUS discharge resistor * 0b0..VBUS discharge resistor is disabled (Default) * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U) #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U) /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP */ #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH * 0b000..4.0 V * 0b001..4.1 V * 0b010..4.2 V * 0b011..4.3 V * 0b100..4.4 V (Default) * 0b101..4.5 V * 0b110..4.6 V * 0b111..4.7 V */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) /*! SESSEND_OVERRIDE - Override value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) /*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) /*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) * 0b01..Use the Session Valid comparator results for signal reported to the USB controller * 0b10..Use the Session Valid comparator results for signal reported to the USB controller * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x100000U) #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - Enables the VBUS_VALID comparator * 0b0..Powers down the VBUS_VALID comparator * 0b1..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS - Controls VBUS discharge resistor * 0b0..VBUS discharge resistor is disabled (Default) * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U) #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U) /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP */ #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH * 0b000..4.0 V * 0b001..4.1 V * 0b010..4.2 V * 0b011..4.3 V * 0b100..4.4 V (Default) * 0b101..4.5 V * 0b110..4.6 V * 0b111..4.7 V */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) /*! SESSEND_OVERRIDE - Override value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) /*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) /*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) * 0b01..Use the Session Valid comparator results for signal reported to the USB controller * 0b10..Use the Session Valid comparator results for signal reported to the USB controller * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x100000U) #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - Enables the VBUS_VALID comparator * 0b0..Powers down the VBUS_VALID comparator * 0b1..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS - Controls VBUS discharge resistor * 0b0..VBUS discharge resistor is disabled (Default) * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U) #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U) /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP */ #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH * 0b000..4.0 V * 0b001..4.1 V * 0b010..4.2 V * 0b011..4.3 V * 0b100..4.4 V (Default) * 0b101..4.5 V * 0b110..4.6 V * 0b111..4.7 V */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) /*! SESSEND_OVERRIDE - Override value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) /*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) /*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) * 0b01..Use the Session Valid comparator results for signal reported to the USB controller * 0b10..Use the Session Valid comparator results for signal reported to the USB controller * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x100000U) #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - Enables the VBUS_VALID comparator * 0b0..Powers down the VBUS_VALID comparator * 0b1..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS - Controls VBUS discharge resistor * 0b0..VBUS discharge resistor is disabled (Default) * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U) #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U) /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP */ #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK) /*! @} */ /*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */ /*! @{ */ #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U) #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U) /*! SESSEND - Session End indicator * 0b0..The VBUS voltage is above the Session Valid threshold * 0b1..The VBUS voltage is below the Session Valid threshold */ #define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK) #define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U) #define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U) /*! BVALID - B-Device Session Valid status * 0b0..The VBUS voltage is below the Session Valid threshold * 0b1..The VBUS voltage is above the Session Valid threshold */ #define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U) #define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U) /*! AVALID - A-Device Session Valid status * 0b0..The VBUS voltage is below the Session Valid threshold * 0b1..The VBUS voltage is above the Session Valid threshold */ #define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U) /*! VBUS_VALID - VBUS voltage status * 0b0..VBUS is below the comparator threshold * 0b1..VBUS is above the comparator threshold */ #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U) /*! VBUS_VALID_3V - VBUS_VALID_3V detector status * 0b0..VBUS voltage is below VBUS_VALID_3V threshold * 0b1..VBUS voltage is above VBUS_VALID_3V threshold */ #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) /*! @} */ /*! @name USB1_CHRG_DETECT - USB PHY Charger Detect Control Register */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U) #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK (0x800000U) #define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT (23U) /*! BGR_IBIAS - USB charge detector bias current reference * 0b0..Bias current is derived from the USB PHY internal current generator. * 0b1..Bias current is derived from the reference generator of the bandgap. */ #define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK) /*! @} */ /*! @name USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U) #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK (0x800000U) #define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT (23U) /*! BGR_IBIAS - USB charge detector bias current reference * 0b0..Bias current is derived from the USB PHY internal current generator. * 0b1..Bias current is derived from the reference generator of the bandgap. */ #define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK) /*! @} */ /*! @name USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U) #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK (0x800000U) #define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT (23U) /*! BGR_IBIAS - USB charge detector bias current reference * 0b0..Bias current is derived from the USB PHY internal current generator. * 0b1..Bias current is derived from the reference generator of the bandgap. */ #define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK) /*! @} */ /*! @name USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U) #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK (0x800000U) #define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT (23U) /*! BGR_IBIAS - USB charge detector bias current reference * 0b0..Bias current is derived from the USB PHY internal current generator. * 0b1..Bias current is derived from the reference generator of the bandgap. */ #define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK) /*! @} */ /*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */ /*! @{ */ #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U) #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U) /*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output * 0b0..No USB cable attachment has been detected * 0b1..A USB cable attachment between the device and host has been detected */ #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK) #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U) #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U) /*! CHRG_DETECTED - Battery Charging Primary Detection phase output * 0b0..Standard Downstream Port (SDP) has been detected * 0b1..Charging Port has been detected */ #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK) #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U) #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U) /*! DM_STATE * 0b0..USB_DM pin voltage is < 0.8V * 0b1..USB_DM pin voltage is > 2.0V */ #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U) #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U) /*! DP_STATE * 0b0..USB_DP pin voltage is < 0.8V * 0b1..USB_DP pin voltage is > 2.0V */ #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U) #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U) /*! SECDET_DCP - Battery Charging Secondary Detection phase output * 0b0..Charging Downstream Port (CDP) has been detected * 0b1..Downstream Charging Port (DCP) has been detected */ #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK) /*! @} */ /*! @name ANACTRL - USB PHY Analog Control Register */ /*! @{ */ #define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. */ #define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) /*! @} */ /*! @name ANACTRL_SET - USB PHY Analog Control Register */ /*! @{ */ #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. */ #define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) /*! @} */ /*! @name ANACTRL_CLR - USB PHY Analog Control Register */ /*! @{ */ #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. */ #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) /*! @} */ /*! @name ANACTRL_TOG - USB PHY Analog Control Register */ /*! @{ */ #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. */ #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) /*! @} */ /*! @name USB1_LOOPBACK - USB PHY Loopback Control/Status Register */ /*! @{ */ #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U) #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U) #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK) #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK (0x2U) #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U) #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK) #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK (0x4U) #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U) #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK) #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK) #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK) #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK (0x20U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT (5U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK) #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK (0x40U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT (6U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK) #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK (0x80U) #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U) #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK) #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK (0x100U) #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U) #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK) #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U) #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U) #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK) #define USBPHY_USB1_LOOPBACK_TSTPKT_MASK (0xFF0000U) #define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT (16U) #define USBPHY_USB1_LOOPBACK_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK) /*! @} */ /*! @name USB1_LOOPBACK_SET - USB PHY Loopback Control/Status Register */ /*! @{ */ #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U) #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U) #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK) #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U) #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U) #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK) #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U) #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U) #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK) #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U) #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U) #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK) #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U) #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U) #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK) #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK) #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK (0xFF0000U) #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT (16U) #define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK) /*! @} */ /*! @name USB1_LOOPBACK_CLR - USB PHY Loopback Control/Status Register */ /*! @{ */ #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK) #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U) #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U) #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK) #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U) #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U) #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK) #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK (0xFF0000U) #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT (16U) #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK) /*! @} */ /*! @name USB1_LOOPBACK_TOG - USB PHY Loopback Control/Status Register */ /*! @{ */ #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK) #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U) #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U) #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK) #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U) #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U) #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK) #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK (0xFF0000U) #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT (16U) #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK) /*! @} */ /*! @name USB1_LOOPBACK_HSFSCNT - USB PHY Loopback Packet Number Select Register */ /*! @{ */ #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK) /*! @} */ /*! @name USB1_LOOPBACK_HSFSCNT_SET - USB PHY Loopback Packet Number Select Register */ /*! @{ */ #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU) #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK) #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK) /*! @} */ /*! @name USB1_LOOPBACK_HSFSCNT_CLR - USB PHY Loopback Packet Number Select Register */ /*! @{ */ #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU) #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK) #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK) /*! @} */ /*! @name USB1_LOOPBACK_HSFSCNT_TOG - USB PHY Loopback Packet Number Select Register */ /*! @{ */ #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK) /*! @} */ /*! @name TRIM_OVERRIDE_EN - USB PHY Trim Override Enable Register */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U) /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */ #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U) /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */ #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK (0x6000U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT (13U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT (20U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK) /*! @} */ /*! @name TRIM_OVERRIDE_EN_SET - USB PHY Trim Override Enable Register */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U) /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U) /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK (0x6000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT (13U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT (20U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK) /*! @} */ /*! @name TRIM_OVERRIDE_EN_CLR - USB PHY Trim Override Enable Register */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U) /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U) /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK (0x6000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT (13U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT (20U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK) /*! @} */ /*! @name TRIM_OVERRIDE_EN_TOG - USB PHY Trim Override Enable Register */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U) /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U) /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK (0x6000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT (13U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT (20U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK) /*! @} */ /*! * @} */ /* end of group USBPHY_Register_Masks */ /* USBPHY - Peripheral instance base addresses */ /** Peripheral USBPHY base address */ #define USBPHY_BASE (0x40350000u) /** Peripheral USBPHY base pointer */ #define USBPHY ((USBPHY_Type *)USBPHY_BASE) /** Array initializer of USBPHY peripheral base addresses */ #define USBPHY_BASE_ADDRS { USBPHY_BASE } /** Array initializer of USBPHY peripheral base pointers */ #define USBPHY_BASE_PTRS { USBPHY } /** Interrupt vectors for the USBPHY peripheral type */ #define USBPHY_IRQS { USBPHY_IRQn } /*! * @} */ /* end of group USBPHY_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USDHC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer * @{ */ /** USDHC - Register Layout Typedef */ typedef struct { __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ uint8_t RESERVED_0[4]; __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status, offset: 0x54 */ __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ uint8_t RESERVED_1[4]; __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ uint8_t RESERVED_2[4]; __IO uint32_t STROBE_DLL_CTRL; /**< Strobe DLL control, offset: 0x70 */ __I uint32_t STROBE_DLL_STATUS; /**< Strobe DLL status, offset: 0x74 */ uint8_t RESERVED_3[72]; __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ __IO uint32_t MMC_BOOT; /**< MMC Boot, offset: 0xC4 */ __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ __IO uint32_t TUNING_CTRL; /**< Tuning Control, offset: 0xCC */ } USDHC_Type; /* ---------------------------------------------------------------------------- -- USDHC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USDHC_Register_Masks USDHC Register Masks * @{ */ /*! @name DS_ADDR - DMA System Address */ /*! @{ */ #define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) #define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) /*! DS_ADDR - System address */ #define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) /*! @} */ /*! @name BLK_ATT - Block Attributes */ /*! @{ */ #define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) #define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) /*! BLKSIZE - Transfer block size * 0b1000000000000..4096 bytes * 0b0100000000000..2048 bytes * 0b0001000000000..512 bytes * 0b0000111111111..511 bytes * 0b0000000000100..4 bytes * 0b0000000000011..3 bytes * 0b0000000000010..2 bytes * 0b0000000000001..1 byte * 0b0000000000000..No data transfer */ #define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) #define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) #define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) /*! BLKCNT - Blocks count for current transfer * 0b1111111111111111..65535 blocks * 0b0000000000000010..2 blocks * 0b0000000000000001..1 block * 0b0000000000000000..Stop count */ #define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) /*! @} */ /*! @name CMD_ARG - Command Argument */ /*! @{ */ #define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) #define USDHC_CMD_ARG_CMDARG_SHIFT (0U) /*! CMDARG - Command argument */ #define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) /*! @} */ /*! @name CMD_XFR_TYP - Command Transfer Type */ /*! @{ */ #define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) /*! RSPTYP - Response type select * 0b00..No response * 0b01..Response length 136 * 0b10..Response length 48 * 0b11..Response length 48, check busy after response */ #define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) #define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) /*! CCCEN - Command CRC check enable * 0b1..Enables command CRC check * 0b0..Disables command CRC check */ #define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) #define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) #define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) /*! CICEN - Command index check enable * 0b1..Enables command index check * 0b0..Disable command index check */ #define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) #define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) /*! DPSEL - Data present select * 0b1..Data present * 0b0..No data present */ #define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) #define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) /*! CMDTYP - Command type * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR * 0b10..Resume CMD52 for writing function select in CCCR * 0b01..Suspend CMD52 for writing bus suspend in CCCR * 0b00..Normal other commands */ #define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) #define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) /*! CMDINX - Command index */ #define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) /*! @} */ /*! @name CMD_RSP0 - Command Response0 */ /*! @{ */ #define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) /*! CMDRSP0 - Command response 0 */ #define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) /*! @} */ /*! @name CMD_RSP1 - Command Response1 */ /*! @{ */ #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) /*! CMDRSP1 - Command response 1 */ #define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) /*! @} */ /*! @name CMD_RSP2 - Command Response2 */ /*! @{ */ #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) /*! CMDRSP2 - Command response 2 */ #define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) /*! @} */ /*! @name CMD_RSP3 - Command Response3 */ /*! @{ */ #define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) /*! CMDRSP3 - Command response 3 */ #define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) /*! @} */ /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ /*! @{ */ #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) /*! DATCONT - Data content */ #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) /*! @} */ /*! @name PRES_STATE - Present State */ /*! @{ */ #define USDHC_PRES_STATE_CIHB_MASK (0x1U) #define USDHC_PRES_STATE_CIHB_SHIFT (0U) /*! CIHB - Command inhibit (CMD) * 0b1..Cannot issue command * 0b0..Can issue command using only CMD line */ #define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) #define USDHC_PRES_STATE_CDIHB_MASK (0x2U) #define USDHC_PRES_STATE_CDIHB_SHIFT (1U) /*! CDIHB - Command inhibit (DATA) * 0b1..Cannot issue command that uses the DATA line * 0b0..Can issue command that uses the DATA line */ #define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) #define USDHC_PRES_STATE_DLA_MASK (0x4U) #define USDHC_PRES_STATE_DLA_SHIFT (2U) /*! DLA - Data line active * 0b1..DATA line active * 0b0..DATA line inactive */ #define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) #define USDHC_PRES_STATE_SDSTB_MASK (0x8U) #define USDHC_PRES_STATE_SDSTB_SHIFT (3U) /*! SDSTB - SD clock stable * 0b1..Clock is stable. * 0b0..Clock is changing frequency and not stable. */ #define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) #define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) #define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) /*! IPGOFF - Peripheral clock gated off internally * 0b1..Peripheral clock is gated off. * 0b0..Peripheral clock is active. */ #define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) #define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) #define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) /*! HCKOFF - HCLK gated off internally * 0b1..HCLK is gated off. * 0b0..HCLK is active. */ #define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) #define USDHC_PRES_STATE_PEROFF_MASK (0x40U) #define USDHC_PRES_STATE_PEROFF_SHIFT (6U) /*! PEROFF - IPG_PERCLK gated off internally * 0b1..IPG_PERCLK is gated off. * 0b0..IPG_PERCLK is active. */ #define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) #define USDHC_PRES_STATE_SDOFF_MASK (0x80U) #define USDHC_PRES_STATE_SDOFF_SHIFT (7U) /*! SDOFF - SD clock gated off internally * 0b1..SD clock is gated off. * 0b0..SD clock is active. */ #define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) #define USDHC_PRES_STATE_WTA_MASK (0x100U) #define USDHC_PRES_STATE_WTA_SHIFT (8U) /*! WTA - Write transfer active * 0b1..Transferring data * 0b0..No valid data */ #define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) #define USDHC_PRES_STATE_RTA_MASK (0x200U) #define USDHC_PRES_STATE_RTA_SHIFT (9U) /*! RTA - Read transfer active * 0b1..Transferring data * 0b0..No valid data */ #define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) #define USDHC_PRES_STATE_BWEN_MASK (0x400U) #define USDHC_PRES_STATE_BWEN_SHIFT (10U) /*! BWEN - Buffer write enable * 0b1..Write enable * 0b0..Write disable */ #define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) #define USDHC_PRES_STATE_BREN_MASK (0x800U) #define USDHC_PRES_STATE_BREN_SHIFT (11U) /*! BREN - Buffer read enable * 0b1..Read enable * 0b0..Read disable */ #define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) #define USDHC_PRES_STATE_RTR_MASK (0x1000U) #define USDHC_PRES_STATE_RTR_SHIFT (12U) /*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode) * 0b1..Sampling clock needs re-tuning * 0b0..Fixed or well tuned sampling clock */ #define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) #define USDHC_PRES_STATE_TSCD_MASK (0x8000U) #define USDHC_PRES_STATE_TSCD_SHIFT (15U) /*! TSCD - Tape select change done * 0b1..Delay cell select change is finished. * 0b0..Delay cell select change is not finished. */ #define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) #define USDHC_PRES_STATE_CINST_MASK (0x10000U) #define USDHC_PRES_STATE_CINST_SHIFT (16U) /*! CINST - Card inserted * 0b1..Card inserted * 0b0..Power on reset or no card */ #define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) #define USDHC_PRES_STATE_CDPL_MASK (0x40000U) #define USDHC_PRES_STATE_CDPL_SHIFT (18U) /*! CDPL - Card detect pin level * 0b1..Card present (CD_B = 0) * 0b0..No card present (CD_B = 1) */ #define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) #define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) #define USDHC_PRES_STATE_WPSPL_SHIFT (19U) /*! WPSPL - Write protect switch pin level * 0b1..Write enabled (WP = 0) * 0b0..Write protected (WP = 1) */ #define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) #define USDHC_PRES_STATE_CLSL_MASK (0x800000U) #define USDHC_PRES_STATE_CLSL_SHIFT (23U) /*! CLSL - CMD line signal level */ #define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) #define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) #define USDHC_PRES_STATE_DLSL_SHIFT (24U) /*! DLSL - DATA[7:0] line signal level * 0b00000111..Data 7 line signal level * 0b00000110..Data 6 line signal level * 0b00000101..Data 5 line signal level * 0b00000100..Data 4 line signal level * 0b00000011..Data 3 line signal level * 0b00000010..Data 2 line signal level * 0b00000001..Data 1 line signal level * 0b00000000..Data 0 line signal level */ #define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) /*! @} */ /*! @name PROT_CTRL - Protocol Control */ /*! @{ */ #define USDHC_PROT_CTRL_LCTL_MASK (0x1U) #define USDHC_PROT_CTRL_LCTL_SHIFT (0U) /*! LCTL - LED control * 0b1..LED on * 0b0..LED off */ #define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) #define USDHC_PROT_CTRL_DTW_MASK (0x6U) #define USDHC_PROT_CTRL_DTW_SHIFT (1U) /*! DTW - Data transfer width * 0b10..8-bit mode * 0b01..4-bit mode * 0b00..1-bit mode * 0b11..Reserved */ #define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) #define USDHC_PROT_CTRL_D3CD_MASK (0x8U) #define USDHC_PROT_CTRL_D3CD_SHIFT (3U) /*! D3CD - DATA3 as card detection pin * 0b1..DATA3 as card detection pin * 0b0..DATA3 does not monitor card insertion */ #define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) #define USDHC_PROT_CTRL_EMODE_MASK (0x30U) #define USDHC_PROT_CTRL_EMODE_SHIFT (4U) /*! EMODE - Endian mode * 0b00..Big endian mode * 0b01..Half word big endian mode * 0b10..Little endian mode * 0b11..Reserved */ #define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) #define USDHC_PROT_CTRL_CDTL_MASK (0x40U) #define USDHC_PROT_CTRL_CDTL_SHIFT (6U) /*! CDTL - Card detect test level * 0b1..Card detect test level is 1, card inserted * 0b0..Card detect test level is 0, no card inserted */ #define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) #define USDHC_PROT_CTRL_CDSS_MASK (0x80U) #define USDHC_PROT_CTRL_CDSS_SHIFT (7U) /*! CDSS - Card detect signal selection * 0b1..Card detection test level is selected (for test purpose). * 0b0..Card detection level is selected (for normal purpose). */ #define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) #define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) #define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) /*! DMASEL - DMA select * 0b00..No DMA or simple DMA is selected. * 0b01..ADMA1 is selected. * 0b10..ADMA2 is selected. * 0b11..Reserved */ #define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) #define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) #define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) /*! SABGREQ - Stop at block gap request * 0b1..Stop * 0b0..Transfer */ #define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) #define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) #define USDHC_PROT_CTRL_CREQ_SHIFT (17U) /*! CREQ - Continue request * 0b1..Restart * 0b0..No effect */ #define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) #define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) #define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) /*! RWCTL - Read wait control * 0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set * 0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set */ #define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) #define USDHC_PROT_CTRL_IABG_MASK (0x80000U) #define USDHC_PROT_CTRL_IABG_SHIFT (19U) /*! IABG - Interrupt at block gap * 0b1..Enables interrupt at block gap * 0b0..Disables interrupt at block gap */ #define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) /*! RD_DONE_NO_8CLK - Read performed number 8 clock */ #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) #define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) #define USDHC_PROT_CTRL_WECINT_SHIFT (24U) /*! WECINT - Wakeup event enable on card interrupt * 0b1..Enables wakeup event enable on card interrupt * 0b0..Disables wakeup event enable on card interrupt */ #define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) #define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) #define USDHC_PROT_CTRL_WECINS_SHIFT (25U) /*! WECINS - Wakeup event enable on SD card insertion * 0b1..Enable wakeup event enable on SD card insertion * 0b0..Disable wakeup event enable on SD card insertion */ #define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) #define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) #define USDHC_PROT_CTRL_WECRM_SHIFT (26U) /*! WECRM - Wakeup event enable on SD card removal * 0b1..Enables wakeup event enable on SD card removal * 0b0..Disables wakeup event enable on SD card removal */ #define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) #define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U) #define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U) /*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP * 0bxx1..Burst length is enabled for INCR. * 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16. * 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP. */ #define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK) #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) /*! NON_EXACT_BLK_RD - Non-exact block read * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. * 0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read. */ #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) /*! @} */ /*! @name SYS_CTRL - System Control */ /*! @{ */ #define USDHC_SYS_CTRL_DVS_MASK (0xF0U) #define USDHC_SYS_CTRL_DVS_SHIFT (4U) /*! DVS - Divisor * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) #define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) #define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) /*! SDCLKFS - SDCLK frequency select */ #define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) #define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) #define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) /*! DTOCV - Data timeout counter value * 0b1111..SDCLK x 2 29 * 0b1110..SDCLK x 2 28 * 0b1101..SDCLK x 2 27 * 0b1100..SDCLK x 2 26 * 0b1011..SDCLK x 2 25 * 0b1010..SDCLK x 2 24 * 0b1001..SDCLK x 2 23 * 0b1000..SDCLK x 2 22 * 0b0111..SDCLK x 2 21 * 0b0110..SDCLK x 2 20 * 0b0101..SDCLK x 2 19 * 0b0100..SDCLK x 2 18 * 0b0011..SDCLK x 2 17 * 0b0010..SDCLK x 2 16 * 0b0001..SDCLK x 2 15 * 0b0000..SDCLK x 2 14 */ #define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) #define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) /*! IPP_RST_N - Hardware reset */ #define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) #define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) #define USDHC_SYS_CTRL_RSTA_SHIFT (24U) /*! RSTA - Software reset for all * 0b1..Reset * 0b0..No reset */ #define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) #define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) #define USDHC_SYS_CTRL_RSTC_SHIFT (25U) /*! RSTC - Software reset for CMD line * 0b1..Reset * 0b0..No reset */ #define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) #define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) #define USDHC_SYS_CTRL_RSTD_SHIFT (26U) /*! RSTD - Software reset for data line * 0b1..Reset * 0b0..No reset */ #define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) #define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) #define USDHC_SYS_CTRL_INITA_SHIFT (27U) /*! INITA - Initialization active */ #define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) #define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) #define USDHC_SYS_CTRL_RSTT_SHIFT (28U) /*! RSTT - Reset tuning */ #define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) /*! @} */ /*! @name INT_STATUS - Interrupt Status */ /*! @{ */ #define USDHC_INT_STATUS_CC_MASK (0x1U) #define USDHC_INT_STATUS_CC_SHIFT (0U) /*! CC - Command complete * 0b1..Command complete * 0b0..Command not complete */ #define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) #define USDHC_INT_STATUS_TC_MASK (0x2U) #define USDHC_INT_STATUS_TC_SHIFT (1U) /*! TC - Transfer complete * 0b1..Transfer complete * 0b0..Transfer does not complete */ #define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) #define USDHC_INT_STATUS_BGE_MASK (0x4U) #define USDHC_INT_STATUS_BGE_SHIFT (2U) /*! BGE - Block gap event * 0b1..Transaction stopped at block gap * 0b0..No block gap event */ #define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) #define USDHC_INT_STATUS_DINT_MASK (0x8U) #define USDHC_INT_STATUS_DINT_SHIFT (3U) /*! DINT - DMA interrupt * 0b1..DMA interrupt is generated. * 0b0..No DMA interrupt */ #define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) #define USDHC_INT_STATUS_BWR_MASK (0x10U) #define USDHC_INT_STATUS_BWR_SHIFT (4U) /*! BWR - Buffer write ready * 0b1..Ready to write buffer * 0b0..Not ready to write buffer */ #define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) #define USDHC_INT_STATUS_BRR_MASK (0x20U) #define USDHC_INT_STATUS_BRR_SHIFT (5U) /*! BRR - Buffer read ready * 0b1..Ready to read buffer * 0b0..Not ready to read buffer */ #define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) #define USDHC_INT_STATUS_CINS_MASK (0x40U) #define USDHC_INT_STATUS_CINS_SHIFT (6U) /*! CINS - Card insertion * 0b1..Card inserted * 0b0..Card state unstable or removed */ #define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) #define USDHC_INT_STATUS_CRM_MASK (0x80U) #define USDHC_INT_STATUS_CRM_SHIFT (7U) /*! CRM - Card removal * 0b1..Card removed * 0b0..Card state unstable or inserted */ #define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) #define USDHC_INT_STATUS_CINT_MASK (0x100U) #define USDHC_INT_STATUS_CINT_SHIFT (8U) /*! CINT - Card interrupt * 0b1..Generate card interrupt * 0b0..No card interrupt */ #define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) #define USDHC_INT_STATUS_RTE_MASK (0x1000U) #define USDHC_INT_STATUS_RTE_SHIFT (12U) /*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode) * 0b1..Re-tuning should be performed. * 0b0..Re-tuning is not required. */ #define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) #define USDHC_INT_STATUS_TP_MASK (0x4000U) #define USDHC_INT_STATUS_TP_SHIFT (14U) /*! TP - Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode) */ #define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) #define USDHC_INT_STATUS_CTOE_MASK (0x10000U) #define USDHC_INT_STATUS_CTOE_SHIFT (16U) /*! CTOE - Command timeout error * 0b1..Time out * 0b0..No error */ #define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) #define USDHC_INT_STATUS_CCE_MASK (0x20000U) #define USDHC_INT_STATUS_CCE_SHIFT (17U) /*! CCE - Command CRC error * 0b1..CRC error generated * 0b0..No error */ #define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) #define USDHC_INT_STATUS_CEBE_MASK (0x40000U) #define USDHC_INT_STATUS_CEBE_SHIFT (18U) /*! CEBE - Command end bit error * 0b1..End bit error generated * 0b0..No error */ #define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) #define USDHC_INT_STATUS_CIE_MASK (0x80000U) #define USDHC_INT_STATUS_CIE_SHIFT (19U) /*! CIE - Command index error * 0b1..Error * 0b0..No error */ #define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) #define USDHC_INT_STATUS_DTOE_MASK (0x100000U) #define USDHC_INT_STATUS_DTOE_SHIFT (20U) /*! DTOE - Data timeout error * 0b1..Time out * 0b0..No error */ #define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) #define USDHC_INT_STATUS_DCE_MASK (0x200000U) #define USDHC_INT_STATUS_DCE_SHIFT (21U) /*! DCE - Data CRC error * 0b1..Error * 0b0..No error */ #define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) #define USDHC_INT_STATUS_DEBE_MASK (0x400000U) #define USDHC_INT_STATUS_DEBE_SHIFT (22U) /*! DEBE - Data end bit error * 0b1..Error * 0b0..No error */ #define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) #define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) #define USDHC_INT_STATUS_AC12E_SHIFT (24U) /*! AC12E - Auto CMD12 error * 0b1..Error * 0b0..No error */ #define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) #define USDHC_INT_STATUS_TNE_MASK (0x4000000U) #define USDHC_INT_STATUS_TNE_SHIFT (26U) /*! TNE - Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode) */ #define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) #define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) #define USDHC_INT_STATUS_DMAE_SHIFT (28U) /*! DMAE - DMA error * 0b1..Error * 0b0..No error */ #define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) /*! @} */ /*! @name INT_STATUS_EN - Interrupt Status Enable */ /*! @{ */ #define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) #define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) /*! CCSEN - Command complete status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) #define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) #define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) /*! TCSEN - Transfer complete status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) #define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) #define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) /*! BGESEN - Block gap event status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) #define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) /*! DINTSEN - DMA interrupt status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) #define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) /*! BWRSEN - Buffer write ready status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) #define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) /*! BRRSEN - Buffer read ready status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) #define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) /*! CINSSEN - Card insertion status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) #define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) /*! CRMSEN - Card removal status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) #define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) /*! CINTSEN - Card interrupt status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) #define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) #define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) /*! RTESEN - Re-tuning event status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) #define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U) #define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U) /*! TPSEN - Tuning pass status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) #define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) /*! CTOESEN - Command timeout error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) #define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) #define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) /*! CCESEN - Command CRC error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) #define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) /*! CEBESEN - Command end bit error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) #define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) #define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) /*! CIESEN - Command index error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) #define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) /*! DTOESEN - Data timeout error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) #define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) #define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) /*! DCESEN - Data CRC error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) #define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) /*! DEBESEN - Data end bit error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) #define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) /*! AC12ESEN - Auto CMD12 error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) #define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) #define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) /*! TNESEN - Tuning error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) #define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) /*! DMAESEN - DMA error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) /*! @} */ /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ /*! @{ */ #define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) /*! CCIEN - Command complete interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) #define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) /*! TCIEN - Transfer complete interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) /*! BGEIEN - Block gap event interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) /*! DINTIEN - DMA interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) /*! BWRIEN - Buffer write ready interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) /*! BRRIEN - Buffer read ready interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) /*! CINSIEN - Card insertion interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) /*! CRMIEN - Card removal interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) /*! CINTIEN - Card interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) /*! RTEIEN - Re-tuning event interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) #define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U) #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U) /*! TPIEN - Tuning Pass interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) /*! CTOEIEN - Command timeout error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) /*! CCEIEN - Command CRC error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) /*! CEBEIEN - Command end bit error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) /*! CIEIEN - Command index error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) /*! DTOEIEN - Data timeout error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) /*! DCEIEN - Data CRC error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) /*! DEBEIEN - Data end bit error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) /*! AC12EIEN - Auto CMD12 error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) /*! TNEIEN - Tuning error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) /*! DMAEIEN - DMA error interrupt enable * 0b1..Enable * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) /*! @} */ /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ /*! @{ */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) /*! AC12NE - Auto CMD12 not executed * 0b1..Not executed * 0b0..Executed */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) /*! AC12TOE - Auto CMD12 / 23 timeout error * 0b1..Time out * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) /*! AC12EBE - Auto CMD12 / 23 end bit error * 0b1..End bit error generated * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) /*! AC12CE - Auto CMD12 / 23 CRC error * 0b1..CRC error met in Auto CMD12/23 response * 0b0..No CRC error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) /*! AC12IE - Auto CMD12 / 23 index error * 0b1..Error, the CMD index in response is not CMD12/23 * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) /*! CNIBAC12E - Command not issued by Auto CMD12 error * 0b1..Not issued * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) /*! EXECUTE_TUNING - Execute tuning */ #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) /*! SMP_CLK_SEL - Sample clock select * 0b1..Tuned clock is used to sample data * 0b0..Fixed clock is used to sample data */ #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) /*! @} */ /*! @name HOST_CTRL_CAP - Host Controller Capabilities */ /*! @{ */ #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) /*! SDR50_SUPPORT - SDR50 support */ #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) /*! SDR104_SUPPORT - SDR104 support */ #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) /*! DDR50_SUPPORT - DDR50 support */ #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U) #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U) /*! TIME_COUNT_RETUNING - Time counter for retuning */ #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) /*! USE_TUNING_SDR50 - Use Tuning for SDR50 * 0b1..SDR50 requires tuning. * 0b0..SDR does not require tuning. */ #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U) #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U) /*! RETUNING_MODE - Retuning Mode * 0b00..Mode 1 * 0b01..Mode 2 * 0b10..Mode 3 * 0b11..Reserved */ #define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) #define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) #define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) /*! MBL - Max block length * 0b000..512 bytes * 0b001..1024 bytes * 0b010..2048 bytes * 0b011..4096 bytes */ #define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) #define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) /*! ADMAS - ADMA support * 0b1..Advanced DMA supported * 0b0..Advanced DMA not supported */ #define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) #define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) #define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) /*! HSS - High speed support * 0b1..High speed supported * 0b0..High speed not supported */ #define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) #define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) /*! DMAS - DMA support * 0b1..DMA supported * 0b0..DMA not supported */ #define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) #define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) #define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) /*! SRS - Suspend / resume support * 0b1..Supported * 0b0..Not supported */ #define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) #define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) #define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) /*! VS33 - Voltage support 3.3 V * 0b1..3.3 V supported * 0b0..3.3 V not supported */ #define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) #define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) #define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) /*! VS30 - Voltage support 3.0 V * 0b1..3.0 V supported * 0b0..3.0 V not supported */ #define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) #define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) #define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) /*! VS18 - Voltage support 1.8 V * 0b1..1.8 V supported * 0b0..1.8 V not supported */ #define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) /*! @} */ /*! @name WTMK_LVL - Watermark Level */ /*! @{ */ #define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) #define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) /*! RD_WML - Read watermark level */ #define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) #define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U) #define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U) /*! RD_BRST_LEN - Read burst length due to system restriction, the actual burst length might not exceed 16 */ #define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK) #define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) #define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) /*! WR_WML - Write watermark level */ #define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) #define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) #define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) /*! WR_BRST_LEN - Write burst length due to system restriction, the actual burst length might not exceed 16 */ #define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) /*! @} */ /*! @name MIX_CTRL - Mixer Control */ /*! @{ */ #define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) #define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) /*! DMAEN - DMA enable * 0b1..Enable * 0b0..Disable */ #define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) #define USDHC_MIX_CTRL_BCEN_MASK (0x2U) #define USDHC_MIX_CTRL_BCEN_SHIFT (1U) /*! BCEN - Block count enable * 0b1..Enable * 0b0..Disable */ #define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) #define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) #define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) /*! AC12EN - Auto CMD12 enable * 0b1..Enable * 0b0..Disable */ #define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) #define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) #define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) /*! DDR_EN - Dual data rate mode selection */ #define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) #define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) #define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) /*! DTDSEL - Data transfer direction select * 0b1..Read (Card to host) * 0b0..Write (Host to card) */ #define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) #define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) #define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) /*! MSBSEL - Multi / Single block select * 0b1..Multiple blocks * 0b0..Single block */ #define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) /*! NIBBLE_POS - Nibble position indication */ #define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) #define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) #define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) /*! AC23EN - Auto CMD23 enable */ #define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) #define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) /*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) * 0b1..Execute tuning * 0b0..Not tuned or tuning completed */ #define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) /*! SMP_CLK_SEL - Clock selection * 0b1..Tuned clock is used to sample data / cmd * 0b0..Fixed clock is used to sample data / cmd */ #define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) /*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode) * 0b1..Enable auto tuning * 0b0..Disable auto tuning */ #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) #define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) /*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) * 0b1..Feedback clock comes from the ipp_card_clk_out * 0b0..Feedback clock comes from the loopback CLK */ #define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) #define USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U) #define USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U) /*! HS400_MODE - Enable HS400 mode */ #define USDHC_MIX_CTRL_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK) /*! @} */ /*! @name FORCE_EVENT - Force Event */ /*! @{ */ #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) /*! FEVTAC12NE - Force event auto command 12 not executed */ #define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) #define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) /*! FEVTAC12TOE - Force event auto command 12 time out error */ #define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) #define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) /*! FEVTAC12CE - Force event auto command 12 CRC error */ #define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) #define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) /*! FEVTAC12EBE - Force event Auto Command 12 end bit error */ #define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) #define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) /*! FEVTAC12IE - Force event Auto Command 12 index error */ #define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) /*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error */ #define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) #define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) #define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) /*! FEVTCTOE - Force event command time out error */ #define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) #define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) #define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) /*! FEVTCCE - Force event command CRC error */ #define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) #define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) #define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) /*! FEVTCEBE - Force event command end bit error */ #define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) #define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) #define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) /*! FEVTCIE - Force event command index error */ #define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) #define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) #define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) /*! FEVTDTOE - Force event data time out error */ #define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) #define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) #define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) /*! FEVTDCE - Force event data CRC error */ #define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) #define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) #define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) /*! FEVTDEBE - Force event data end bit error */ #define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) #define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) /*! FEVTAC12E - Force event Auto Command 12 error */ #define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) #define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) #define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) /*! FEVTTNE - Force tuning error */ #define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) #define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) #define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) /*! FEVTDMAE - Force event DMA error */ #define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) #define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) /*! FEVTCINT - Force event card interrupt */ #define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) /*! @} */ /*! @name ADMA_ERR_STATUS - ADMA Error Status */ /*! @{ */ #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) /*! ADMAES - ADMA error state (when ADMA error is occurred) */ #define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) /*! ADMALME - ADMA length mismatch error * 0b1..Error * 0b0..No error */ #define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) /*! ADMADCE - ADMA descriptor error * 0b1..Error * 0b0..No error */ #define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) /*! @} */ /*! @name ADMA_SYS_ADDR - ADMA System Address */ /*! @{ */ #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) /*! ADS_ADDR - ADMA system address */ #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) /*! @} */ /*! @name DLL_CTRL - DLL (Delay Line) Control */ /*! @{ */ #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) /*! DLL_CTRL_ENABLE - DLL and delay chain */ #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) #define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) /*! DLL_CTRL_RESET - DLL reset */ #define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) /*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) /*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0 */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) /*! DLL_CTRL_GATE_UPDATE - DLL gate update */ #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) /*! DLL_CTRL_SLV_OVERRIDE - DLL slave override */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) /*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) /*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1 */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) /*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) /*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval */ #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) /*! @} */ /*! @name DLL_STATUS - DLL Status */ /*! @{ */ #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) /*! DLL_STS_SLV_LOCK - Slave delay-line lock status */ #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) /*! DLL_STS_REF_LOCK - Reference DLL lock status */ #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) /*! DLL_STS_SLV_SEL - Slave delay line select status */ #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) /*! DLL_STS_REF_SEL - Reference delay line select taps */ #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) /*! @} */ /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ /*! @{ */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) /*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) /*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) /*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) /*! NXT_ERR - NXT error */ #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) /*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST */ #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) /*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT */ #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) /*! TAP_SEL_PRE - TAP_SEL_PRE */ #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) /*! PRE_ERR - PRE error */ #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) /*! @} */ /*! @name STROBE_DLL_CTRL - Strobe DLL control */ /*! @{ */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U) /*! STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U) /*! STROBE_DLL_CTRL_RESET - Strobe DLL control reset */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) /*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x38U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) /*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK (0x40U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT (6U) /*! STROBE_DLL_CTRL_GATE_UPDATE_0 - Strobe DLL control gate update */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK (0x80U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT (7U) /*! STROBE_DLL_CTRL_GATE_UPDATE_1 - Strobe DLL control gate update */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) /*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) /*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) /*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) /*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK) /*! @} */ /*! @name STROBE_DLL_STATUS - Strobe DLL status */ /*! @{ */ #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U) /*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock */ #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U) /*! STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock */ #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U) /*! STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select */ #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U) /*! STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select */ #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK) /*! @} */ /*! @name VEND_SPEC - Vendor Specific Register */ /*! @{ */ #define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) #define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) /*! VSELECT - Voltage selection * 0b1..Change the voltage to low voltage range, around 1.8 V * 0b0..Change the voltage to high voltage range, around 3.0 V */ #define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) /*! CONFLICT_CHK_EN - Conflict check enable * 0b0..Conflict check disable * 0b1..Conflict check enable */ #define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) /*! AC12_WR_CHKBUSY_EN - Check busy enable * 0b0..Do not check busy after auto CMD12 for write data packet * 0b1..Check busy after auto CMD12 for write data packet */ #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) /*! FRC_SDCLK_ON - Force CLK * 0b0..CLK active or inactive is fully controlled by the hardware. * 0b1..Force CLK active */ #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) /*! CRC_CHK_DIS - CRC Check Disable * 0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet * 0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet */ #define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) /*! CMD_BYTE_EN - Byte access * 0b0..Disable * 0b1..Enable */ #define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) /*! @} */ /*! @name MMC_BOOT - MMC Boot */ /*! @{ */ #define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) /*! DTOCV_ACK - Boot ACK time out * 0b0000..SDCLK x 2^14 * 0b0001..SDCLK x 2^15 * 0b0010..SDCLK x 2^16 * 0b0011..SDCLK x 2^17 * 0b0100..SDCLK x 2^18 * 0b0101..SDCLK x 2^19 * 0b0110..SDCLK x 2^20 * 0b0111..SDCLK x 2^21 * 0b1110..SDCLK x 2^28 * 0b1111..SDCLK x 2^29 */ #define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) #define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) /*! BOOT_ACK - BOOT ACK * 0b0..No ack * 0b1..Ack */ #define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) #define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) /*! BOOT_MODE - Boot mode * 0b0..Normal boot * 0b1..Alternative boot */ #define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) #define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) #define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) /*! BOOT_EN - Boot enable * 0b0..Fast boot disable * 0b1..Fast boot enable */ #define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) /*! AUTO_SABG_EN - Auto stop at block gap */ #define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) /*! DISABLE_TIME_OUT - Time out * 0b0..Enable time out * 0b1..Disable time out */ #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) /*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode */ #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) /*! @} */ /*! @name VEND_SPEC2 - Vendor Specific 2 Register */ /*! @{ */ #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) /*! CARD_INT_D3_TEST - Card interrupt detection test * 0b0..Check the card interrupt only when DATA3 is high. * 0b1..Check the card interrupt by ignoring the status of DATA3. */ #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) #define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) #define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) /*! TUNING_8bit_EN - Tuning 8bit enable */ #define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK) #define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U) #define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U) /*! TUNING_1bit_EN - Tuning 1bit enable */ #define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) /*! TUNING_CMD_EN - Tuning command enable * 0b0..Auto tuning circuit does not check the CMD line. * 0b1..Auto tuning circuit checks the CMD line. */ #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U) #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U) /*! HS400_WR_CLK_STOP_EN - HS400 write clock stop enable */ #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK) #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U) #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U) /*! HS400_RD_CLK_STOP_EN - HS400 read clock stop enable */ #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK) #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) /*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 * 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled. * 0b0..Disable */ #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) /*! @} */ /*! @name TUNING_CTRL - Tuning Control */ /*! @{ */ #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU) #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) /*! TUNING_START_TAP - Tuning start */ #define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) #define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) #define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) /*! TUNING_COUNTER - Tuning counter */ #define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) #define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) #define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) /*! TUNING_STEP - TUNING_STEP */ #define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) #define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) #define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) /*! TUNING_WINDOW - Data window */ #define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) /*! STD_TUNING_EN - Standard tuning circuit and procedure enable */ #define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) /*! @} */ /*! * @} */ /* end of group USDHC_Register_Masks */ /* USDHC - Peripheral instance base addresses */ /** Peripheral USDHC0 base address */ #define USDHC0_BASE (0x40370000u) /** Peripheral USDHC0 base pointer */ #define USDHC0 ((USDHC_Type *)USDHC0_BASE) /** Peripheral USDHC1 base address */ #define USDHC1_BASE (0x40380000u) /** Peripheral USDHC1 base pointer */ #define USDHC1 ((USDHC_Type *)USDHC1_BASE) /** Array initializer of USDHC peripheral base addresses */ #define USDHC_BASE_ADDRS { USDHC0_BASE, USDHC1_BASE } /** Array initializer of USDHC peripheral base pointers */ #define USDHC_BASE_PTRS { USDHC0, USDHC1 } /*! * @} */ /* end of group USDHC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- VIU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup VIU_Peripheral_Access_Layer VIU Peripheral Access Layer * @{ */ /** VIU - Register Layout Typedef */ typedef struct { __IO uint32_t SCR; /**< Status And Configuration Register, offset: 0x0 */ uint8_t RESERVED_0[4]; __IO uint32_t DINVSZ; /**< Detected Input Video Pixel and Line Counts, offset: 0x8 */ __IO uint32_t DINVFL; /**< Detected Input Video Frame Length, offset: 0xC */ uint8_t RESERVED_1[4]; __IO uint32_t DMA_ADDR; /**< Base Address Of Every Field/Frame Of Picture In Memory, offset: 0x14 */ __IO uint32_t DMA_INC; /**< Horizontal DMA Increment, offset: 0x18 */ __IO uint32_t INVSZ; /**< Input Video Pixel and Line Count, offset: 0x1C */ __IO uint32_t HPRALRM; /**< High Priority Bus Request Alarm, offset: 0x20 */ __IO uint32_t ALPHA; /**< Programable Alpha Value, offset: 0x24 */ __IO uint32_t HFACTOR; /**< Scaling Factor In Horizontal Direction, offset: 0x28 */ __IO uint32_t VFACTOR; /**< Down Scaling Factor In Vertical Direction, offset: 0x2C */ __IO uint32_t VID_SIZE; /**< Scaling Destination Pixel and Line Count, offset: 0x30 */ __IO uint32_t LUT_ADDR; /**< B/C Adjust Look-up-table Current Address, offset: 0x34 */ __IO uint32_t LUT_DATA; /**< B/C Adjust Look-up-table Data Entry, offset: 0x38 */ __IO uint32_t EXT_CONFIG; /**< Extended Configuration Register, offset: 0x3C */ uint8_t RESERVED_2[12]; __IO uint32_t ACT_ORG; /**< Active Image Origin, offset: 0x4C */ __IO uint32_t ACT_SIZE; /**< Active Image Size, offset: 0x50 */ } VIU_Type; /* ---------------------------------------------------------------------------- -- VIU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup VIU_Register_Masks VIU Register Masks * @{ */ /*! @name SCR - Status And Configuration Register */ /*! @{ */ #define VIU_SCR_SOFT_RESET_MASK (0x1U) #define VIU_SCR_SOFT_RESET_SHIFT (0U) /*! SOFT_RESET - SOFT_RESET */ #define VIU_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_SOFT_RESET_SHIFT)) & VIU_SCR_SOFT_RESET_MASK) #define VIU_SCR_FORMAT_CTRL_MASK (0xEU) #define VIU_SCR_FORMAT_CTRL_SHIFT (1U) /*! FORMAT_CTRL - FORMAT_CTRL */ #define VIU_SCR_FORMAT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_FORMAT_CTRL_SHIFT)) & VIU_SCR_FORMAT_CTRL_MASK) #define VIU_SCR_ERROR_CODE_MASK (0xF0U) #define VIU_SCR_ERROR_CODE_SHIFT (4U) /*! ERROR_CODE - ERROR_CODE * 0b0000..No error * 0b0001..DMA arm command given during vertical active, DMA_ACT does not accept the value on IPS bus. * 0b0010..DMA arm command given during vertical blanking when DMA_ACT is set. * 0b0100..Line too long * 0b0101..Too many lines in a field/frame * 0b0110..Line too short * 0b0111..Not enough lines in a field/frame * 0b1000..FIFO overflow * 0b1001..FIFO underflow * 0b1010..One bit ECC error * 0b1011..Two or more bits ECC error */ #define VIU_SCR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_ERROR_CODE_SHIFT)) & VIU_SCR_ERROR_CODE_MASK) #define VIU_SCR_FIELD_EN_MASK (0x100U) #define VIU_SCR_FIELD_EN_SHIFT (8U) /*! FIELD_EN - FIELD_EN */ #define VIU_SCR_FIELD_EN(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_FIELD_EN_SHIFT)) & VIU_SCR_FIELD_EN_MASK) #define VIU_SCR_VSYNC_EN_MASK (0x200U) #define VIU_SCR_VSYNC_EN_SHIFT (9U) /*! VSYNC_EN - VSYNC_EN */ #define VIU_SCR_VSYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_VSYNC_EN_SHIFT)) & VIU_SCR_VSYNC_EN_MASK) #define VIU_SCR_HSYNC_EN_MASK (0x400U) #define VIU_SCR_HSYNC_EN_SHIFT (10U) /*! HSYNC_EN - HSYNC_EN */ #define VIU_SCR_HSYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_HSYNC_EN_SHIFT)) & VIU_SCR_HSYNC_EN_MASK) #define VIU_SCR_VSTART_EN_MASK (0x800U) #define VIU_SCR_VSTART_EN_SHIFT (11U) /*! VSTART_EN - VSTART_EN */ #define VIU_SCR_VSTART_EN(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_VSTART_EN_SHIFT)) & VIU_SCR_VSTART_EN_MASK) #define VIU_SCR_DMA_END_EN_MASK (0x1000U) #define VIU_SCR_DMA_END_EN_SHIFT (12U) /*! DMA_END_EN - DMA_END_EN */ #define VIU_SCR_DMA_END_EN(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_DMA_END_EN_SHIFT)) & VIU_SCR_DMA_END_EN_MASK) #define VIU_SCR_ERROR_EN_MASK (0x2000U) #define VIU_SCR_ERROR_EN_SHIFT (13U) /*! ERROR_EN - ERROR_EN */ #define VIU_SCR_ERROR_EN(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_ERROR_EN_SHIFT)) & VIU_SCR_ERROR_EN_MASK) #define VIU_SCR_ECC_EN_MASK (0x4000U) #define VIU_SCR_ECC_EN_SHIFT (14U) /*! ECC_EN - ECC_EN */ #define VIU_SCR_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_ECC_EN_SHIFT)) & VIU_SCR_ECC_EN_MASK) #define VIU_SCR_FIELD_IRQ_MASK (0x10000U) #define VIU_SCR_FIELD_IRQ_SHIFT (16U) /*! FIELD_IRQ - FIELD_IRQ */ #define VIU_SCR_FIELD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_FIELD_IRQ_SHIFT)) & VIU_SCR_FIELD_IRQ_MASK) #define VIU_SCR_VSYNC_IRQ_MASK (0x20000U) #define VIU_SCR_VSYNC_IRQ_SHIFT (17U) /*! VSYNC_IRQ - VSYNC_IRQ */ #define VIU_SCR_VSYNC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_VSYNC_IRQ_SHIFT)) & VIU_SCR_VSYNC_IRQ_MASK) #define VIU_SCR_HSYNC_IRQ_MASK (0x40000U) #define VIU_SCR_HSYNC_IRQ_SHIFT (18U) /*! HSYNC_IRQ - HSYNC_IRQ */ #define VIU_SCR_HSYNC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_HSYNC_IRQ_SHIFT)) & VIU_SCR_HSYNC_IRQ_MASK) #define VIU_SCR_VSTART_IRQ_MASK (0x80000U) #define VIU_SCR_VSTART_IRQ_SHIFT (19U) /*! VSTART_IRQ - VSTART_IRQ */ #define VIU_SCR_VSTART_IRQ(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_VSTART_IRQ_SHIFT)) & VIU_SCR_VSTART_IRQ_MASK) #define VIU_SCR_DMA_END_IRQ_MASK (0x100000U) #define VIU_SCR_DMA_END_IRQ_SHIFT (20U) /*! DMA_END_IRQ - DMA_END_IRQ */ #define VIU_SCR_DMA_END_IRQ(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_DMA_END_IRQ_SHIFT)) & VIU_SCR_DMA_END_IRQ_MASK) #define VIU_SCR_ERROR_IRQ_MASK (0x200000U) #define VIU_SCR_ERROR_IRQ_SHIFT (21U) /*! ERROR_IRQ - ERROR_IRQ */ #define VIU_SCR_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_ERROR_IRQ_SHIFT)) & VIU_SCR_ERROR_IRQ_MASK) #define VIU_SCR_MODE444_MASK (0x800000U) #define VIU_SCR_MODE444_SHIFT (23U) /*! MODE444 - MODE444 */ #define VIU_SCR_MODE444(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_MODE444_SHIFT)) & VIU_SCR_MODE444_MASK) #define VIU_SCR_BC_EN_MASK (0x1000000U) #define VIU_SCR_BC_EN_SHIFT (24U) /*! BC_EN - BC_EN */ #define VIU_SCR_BC_EN(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_BC_EN_SHIFT)) & VIU_SCR_BC_EN_MASK) #define VIU_SCR_YUV2RGB_EN_MASK (0x2000000U) #define VIU_SCR_YUV2RGB_EN_SHIFT (25U) /*! YUV2RGB_EN - YUV2RGB_EN */ #define VIU_SCR_YUV2RGB_EN(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_YUV2RGB_EN_SHIFT)) & VIU_SCR_YUV2RGB_EN_MASK) #define VIU_SCR_SCALER_EN_MASK (0x4000000U) #define VIU_SCR_SCALER_EN_SHIFT (26U) /*! SCALER_EN - SCALER_EN */ #define VIU_SCR_SCALER_EN(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_SCALER_EN_SHIFT)) & VIU_SCR_SCALER_EN_MASK) #define VIU_SCR_DMA_ACT_MASK (0x8000000U) #define VIU_SCR_DMA_ACT_SHIFT (27U) /*! DMA_ACT - DMA_ACT */ #define VIU_SCR_DMA_ACT(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_DMA_ACT_SHIFT)) & VIU_SCR_DMA_ACT_MASK) #define VIU_SCR_FIELD_NO_MASK (0x10000000U) #define VIU_SCR_FIELD_NO_SHIFT (28U) /*! FIELD_NO - FIELD_NO */ #define VIU_SCR_FIELD_NO(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_FIELD_NO_SHIFT)) & VIU_SCR_FIELD_NO_MASK) #define VIU_SCR_DITHER_ON_MASK (0x20000000U) #define VIU_SCR_DITHER_ON_SHIFT (29U) /*! DITHER_ON - DITHER_ON */ #define VIU_SCR_DITHER_ON(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_DITHER_ON_SHIFT)) & VIU_SCR_DITHER_ON_MASK) #define VIU_SCR_ROUND_ON_MASK (0x40000000U) #define VIU_SCR_ROUND_ON_SHIFT (30U) /*! ROUND_ON - ROUND_ON */ #define VIU_SCR_ROUND_ON(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_ROUND_ON_SHIFT)) & VIU_SCR_ROUND_ON_MASK) #define VIU_SCR_MODE32BIT_MASK (0x80000000U) #define VIU_SCR_MODE32BIT_SHIFT (31U) /*! MODE32BIT - MODE32BIT * 0b0..16-bit RGB or YUV 4:2:2 output * 0b1..32-bit RGB or YUV 4:4:4 output. DITHER_ON and ROUND_ON are ignored if output is 32-bit RGB. */ #define VIU_SCR_MODE32BIT(x) (((uint32_t)(((uint32_t)(x)) << VIU_SCR_MODE32BIT_SHIFT)) & VIU_SCR_MODE32BIT_MASK) /*! @} */ /*! @name DINVSZ - Detected Input Video Pixel and Line Counts */ /*! @{ */ #define VIU_DINVSZ_DETECTED_PIXELC_MASK (0xFFFFU) #define VIU_DINVSZ_DETECTED_PIXELC_SHIFT (0U) /*! DETECTED_PIXELC - DETECTED_PIXELC */ #define VIU_DINVSZ_DETECTED_PIXELC(x) (((uint32_t)(((uint32_t)(x)) << VIU_DINVSZ_DETECTED_PIXELC_SHIFT)) & VIU_DINVSZ_DETECTED_PIXELC_MASK) #define VIU_DINVSZ_DETECTED_LINEC_MASK (0xFFFF0000U) #define VIU_DINVSZ_DETECTED_LINEC_SHIFT (16U) /*! DETECTED_LINEC - DETECTED_LINEC */ #define VIU_DINVSZ_DETECTED_LINEC(x) (((uint32_t)(((uint32_t)(x)) << VIU_DINVSZ_DETECTED_LINEC_SHIFT)) & VIU_DINVSZ_DETECTED_LINEC_MASK) /*! @} */ /*! @name DINVFL - Detected Input Video Frame Length */ /*! @{ */ #define VIU_DINVFL_DETECTED_FRAME_WIDTH_MASK (0xFFFFU) #define VIU_DINVFL_DETECTED_FRAME_WIDTH_SHIFT (0U) /*! DETECTED_FRAME_WIDTH - DETECTED_FRAME_WIDTH */ #define VIU_DINVFL_DETECTED_FRAME_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VIU_DINVFL_DETECTED_FRAME_WIDTH_SHIFT)) & VIU_DINVFL_DETECTED_FRAME_WIDTH_MASK) #define VIU_DINVFL_DETECTED_FRAME_HEIGHT_MASK (0xFFFF0000U) #define VIU_DINVFL_DETECTED_FRAME_HEIGHT_SHIFT (16U) /*! DETECTED_FRAME_HEIGHT - DETECTED_FRAME_HEIGHT */ #define VIU_DINVFL_DETECTED_FRAME_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VIU_DINVFL_DETECTED_FRAME_HEIGHT_SHIFT)) & VIU_DINVFL_DETECTED_FRAME_HEIGHT_MASK) /*! @} */ /*! @name DMA_ADDR - Base Address Of Every Field/Frame Of Picture In Memory */ /*! @{ */ #define VIU_DMA_ADDR_ADDR_MASK (0xFFFFFFF8U) #define VIU_DMA_ADDR_ADDR_SHIFT (3U) /*! ADDR - ADDR */ #define VIU_DMA_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VIU_DMA_ADDR_ADDR_SHIFT)) & VIU_DMA_ADDR_ADDR_MASK) /*! @} */ /*! @name DMA_INC - Horizontal DMA Increment */ /*! @{ */ #define VIU_DMA_INC_INC_MASK (0xFFF8U) #define VIU_DMA_INC_INC_SHIFT (3U) /*! INC - INC */ #define VIU_DMA_INC_INC(x) (((uint32_t)(((uint32_t)(x)) << VIU_DMA_INC_INC_SHIFT)) & VIU_DMA_INC_INC_MASK) /*! @} */ /*! @name INVSZ - Input Video Pixel and Line Count */ /*! @{ */ #define VIU_INVSZ_PIXELC_MASK (0xFFFFU) #define VIU_INVSZ_PIXELC_SHIFT (0U) /*! PIXELC - PIXELC */ #define VIU_INVSZ_PIXELC(x) (((uint32_t)(((uint32_t)(x)) << VIU_INVSZ_PIXELC_SHIFT)) & VIU_INVSZ_PIXELC_MASK) #define VIU_INVSZ_LINEC_MASK (0xFFFF0000U) #define VIU_INVSZ_LINEC_SHIFT (16U) /*! LINEC - LINEC */ #define VIU_INVSZ_LINEC(x) (((uint32_t)(((uint32_t)(x)) << VIU_INVSZ_LINEC_SHIFT)) & VIU_INVSZ_LINEC_MASK) /*! @} */ /*! @name HPRALRM - High Priority Bus Request Alarm */ /*! @{ */ #define VIU_HPRALRM_ALARM_MASK (0xFFFFU) #define VIU_HPRALRM_ALARM_SHIFT (0U) /*! ALARM - ALARM */ #define VIU_HPRALRM_ALARM(x) (((uint32_t)(((uint32_t)(x)) << VIU_HPRALRM_ALARM_SHIFT)) & VIU_HPRALRM_ALARM_MASK) /*! @} */ /*! @name ALPHA - Programable Alpha Value */ /*! @{ */ #define VIU_ALPHA_ALPHA_MASK (0xFFU) #define VIU_ALPHA_ALPHA_SHIFT (0U) /*! ALPHA - ALPHA */ #define VIU_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << VIU_ALPHA_ALPHA_SHIFT)) & VIU_ALPHA_ALPHA_MASK) /*! @} */ /*! @name HFACTOR - Scaling Factor In Horizontal Direction */ /*! @{ */ #define VIU_HFACTOR_FACTOR_MASK (0x7FFU) #define VIU_HFACTOR_FACTOR_SHIFT (0U) /*! FACTOR - FACTOR */ #define VIU_HFACTOR_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << VIU_HFACTOR_FACTOR_SHIFT)) & VIU_HFACTOR_FACTOR_MASK) /*! @} */ /*! @name VFACTOR - Down Scaling Factor In Vertical Direction */ /*! @{ */ #define VIU_VFACTOR_FACTOR_MASK (0x7FFU) #define VIU_VFACTOR_FACTOR_SHIFT (0U) /*! FACTOR - FACTOR */ #define VIU_VFACTOR_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << VIU_VFACTOR_FACTOR_SHIFT)) & VIU_VFACTOR_FACTOR_MASK) /*! @} */ /*! @name VID_SIZE - Scaling Destination Pixel and Line Count */ /*! @{ */ #define VIU_VID_SIZE_PIXELC_MASK (0xFFFFU) #define VIU_VID_SIZE_PIXELC_SHIFT (0U) /*! PIXELC - PIXELC */ #define VIU_VID_SIZE_PIXELC(x) (((uint32_t)(((uint32_t)(x)) << VIU_VID_SIZE_PIXELC_SHIFT)) & VIU_VID_SIZE_PIXELC_MASK) #define VIU_VID_SIZE_LINEC_MASK (0xFFFF0000U) #define VIU_VID_SIZE_LINEC_SHIFT (16U) /*! LINEC - LINEC */ #define VIU_VID_SIZE_LINEC(x) (((uint32_t)(((uint32_t)(x)) << VIU_VID_SIZE_LINEC_SHIFT)) & VIU_VID_SIZE_LINEC_MASK) /*! @} */ /*! @name LUT_ADDR - B/C Adjust Look-up-table Current Address */ /*! @{ */ #define VIU_LUT_ADDR_ADDR_MASK (0x3FCU) #define VIU_LUT_ADDR_ADDR_SHIFT (2U) /*! ADDR - ADDR */ #define VIU_LUT_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VIU_LUT_ADDR_ADDR_SHIFT)) & VIU_LUT_ADDR_ADDR_MASK) /*! @} */ /*! @name LUT_DATA - B/C Adjust Look-up-table Data Entry */ /*! @{ */ #define VIU_LUT_DATA_DATA_MASK (0xFFFFFFFFU) #define VIU_LUT_DATA_DATA_SHIFT (0U) /*! DATA - DATA */ #define VIU_LUT_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << VIU_LUT_DATA_DATA_SHIFT)) & VIU_LUT_DATA_DATA_MASK) /*! @} */ /*! @name EXT_CONFIG - Extended Configuration Register */ /*! @{ */ #define VIU_EXT_CONFIG_HMIRROR_EN_MASK (0x1U) #define VIU_EXT_CONFIG_HMIRROR_EN_SHIFT (0U) /*! HMIRROR_EN - HMIRROR_EN */ #define VIU_EXT_CONFIG_HMIRROR_EN(x) (((uint32_t)(((uint32_t)(x)) << VIU_EXT_CONFIG_HMIRROR_EN_SHIFT)) & VIU_EXT_CONFIG_HMIRROR_EN_MASK) #define VIU_EXT_CONFIG_DE_POL_MASK (0x2U) #define VIU_EXT_CONFIG_DE_POL_SHIFT (1U) /*! DE_POL - DE_POL * 0b0..Active high * 0b1..Active low */ #define VIU_EXT_CONFIG_DE_POL(x) (((uint32_t)(((uint32_t)(x)) << VIU_EXT_CONFIG_DE_POL_SHIFT)) & VIU_EXT_CONFIG_DE_POL_MASK) #define VIU_EXT_CONFIG_HSYNC_POL_MASK (0x4U) #define VIU_EXT_CONFIG_HSYNC_POL_SHIFT (2U) /*! HSYNC_POL - HSYNC_POL * 0b0..Active high * 0b1..Active low */ #define VIU_EXT_CONFIG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << VIU_EXT_CONFIG_HSYNC_POL_SHIFT)) & VIU_EXT_CONFIG_HSYNC_POL_MASK) #define VIU_EXT_CONFIG_VSYNC_POL_MASK (0x8U) #define VIU_EXT_CONFIG_VSYNC_POL_SHIFT (3U) /*! VSYNC_POL - VSYNC_POL * 0b0..Active high * 0b1..Active low */ #define VIU_EXT_CONFIG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << VIU_EXT_CONFIG_VSYNC_POL_SHIFT)) & VIU_EXT_CONFIG_VSYNC_POL_MASK) #define VIU_EXT_CONFIG_PCLK_POL_MASK (0x10U) #define VIU_EXT_CONFIG_PCLK_POL_SHIFT (4U) /*! PCLK_POL - PCLK_POL * 0b0..Active high * 0b1..Active low */ #define VIU_EXT_CONFIG_PCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << VIU_EXT_CONFIG_PCLK_POL_SHIFT)) & VIU_EXT_CONFIG_PCLK_POL_MASK) #define VIU_EXT_CONFIG_INP_FORMAT_MASK (0xE0U) #define VIU_EXT_CONFIG_INP_FORMAT_SHIFT (5U) /*! INP_FORMAT - INP_FORMAT * 0b000..10/8bit ITU stream * 0b001..24bit parallel YUV. Normally it is YUV444 * 0b010..8bit mono input. It is luminance Y. * 0b011..Reserved * 0b100..24bit parallel RGB. It is RGB888 * 0b101..8bit serial RGB. It is RGB888 serial * 0b110..18bit parallel RGB. It is RGB666 * 0b111..16bit parallel RGB. It is RGB565 */ #define VIU_EXT_CONFIG_INP_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << VIU_EXT_CONFIG_INP_FORMAT_SHIFT)) & VIU_EXT_CONFIG_INP_FORMAT_MASK) #define VIU_EXT_CONFIG_DE_VALID_MASK (0x100U) #define VIU_EXT_CONFIG_DE_VALID_SHIFT (8U) /*! DE_VALID - DE_VALID * 0b0..DE is invalid * 0b1..DE is valid */ #define VIU_EXT_CONFIG_DE_VALID(x) (((uint32_t)(((uint32_t)(x)) << VIU_EXT_CONFIG_DE_VALID_SHIFT)) & VIU_EXT_CONFIG_DE_VALID_MASK) #define VIU_EXT_CONFIG_RGB2YUV_EN_MASK (0x200U) #define VIU_EXT_CONFIG_RGB2YUV_EN_SHIFT (9U) /*! RGB2YUV_EN - RGB2YUV_EN */ #define VIU_EXT_CONFIG_RGB2YUV_EN(x) (((uint32_t)(((uint32_t)(x)) << VIU_EXT_CONFIG_RGB2YUV_EN_SHIFT)) & VIU_EXT_CONFIG_RGB2YUV_EN_MASK) #define VIU_EXT_CONFIG_LENDIAN_MASK (0x800U) #define VIU_EXT_CONFIG_LENDIAN_SHIFT (11U) /*! LENDIAN - LENDIAN * 0b0..Big endian * 0b1..Little endian */ #define VIU_EXT_CONFIG_LENDIAN(x) (((uint32_t)(((uint32_t)(x)) << VIU_EXT_CONFIG_LENDIAN_SHIFT)) & VIU_EXT_CONFIG_LENDIAN_MASK) #define VIU_EXT_CONFIG_CS_EN_MASK (0x1000U) #define VIU_EXT_CONFIG_CS_EN_SHIFT (12U) /*! CS_EN - CS_EN * 0b0..Chroma swap is disabled. * 0b1..Chroma swap is enabled. */ #define VIU_EXT_CONFIG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << VIU_EXT_CONFIG_CS_EN_SHIFT)) & VIU_EXT_CONFIG_CS_EN_MASK) #define VIU_EXT_CONFIG_MODE_8BIT_MASK (0x2000U) #define VIU_EXT_CONFIG_MODE_8BIT_SHIFT (13U) /*! MODE_8BIT - 8 bit mode output format selector * 0b0..8-bit output mode is not selected * 0b1..8-bit output mode is selected */ #define VIU_EXT_CONFIG_MODE_8BIT(x) (((uint32_t)(((uint32_t)(x)) << VIU_EXT_CONFIG_MODE_8BIT_SHIFT)) & VIU_EXT_CONFIG_MODE_8BIT_MASK) #define VIU_EXT_CONFIG_MONO_LSB_MASK (0x4000U) #define VIU_EXT_CONFIG_MONO_LSB_SHIFT (14U) /*! MONO_LSB - Data location selector on input data bus. * 0b0..8-bit MONO data is on LSB of input bus * 0b1..8-bit MONO data is on MSB of input bus */ #define VIU_EXT_CONFIG_MONO_LSB(x) (((uint32_t)(((uint32_t)(x)) << VIU_EXT_CONFIG_MONO_LSB_SHIFT)) & VIU_EXT_CONFIG_MONO_LSB_MASK) /*! @} */ /*! @name ACT_ORG - Active Image Origin */ /*! @{ */ #define VIU_ACT_ORG_ACT_ORG_X_MASK (0xFFFFU) #define VIU_ACT_ORG_ACT_ORG_X_SHIFT (0U) /*! ACT_ORG_X - ACT_ORG_X */ #define VIU_ACT_ORG_ACT_ORG_X(x) (((uint32_t)(((uint32_t)(x)) << VIU_ACT_ORG_ACT_ORG_X_SHIFT)) & VIU_ACT_ORG_ACT_ORG_X_MASK) #define VIU_ACT_ORG_ACT_ORG_Y_MASK (0xFFFF0000U) #define VIU_ACT_ORG_ACT_ORG_Y_SHIFT (16U) /*! ACT_ORG_Y - ACT_ORG_Y */ #define VIU_ACT_ORG_ACT_ORG_Y(x) (((uint32_t)(((uint32_t)(x)) << VIU_ACT_ORG_ACT_ORG_Y_SHIFT)) & VIU_ACT_ORG_ACT_ORG_Y_MASK) /*! @} */ /*! @name ACT_SIZE - Active Image Size */ /*! @{ */ #define VIU_ACT_SIZE_ACT_IMG_WIDTH_MASK (0xFFFFU) #define VIU_ACT_SIZE_ACT_IMG_WIDTH_SHIFT (0U) /*! ACT_IMG_WIDTH - ACT_IMG_WIDTH */ #define VIU_ACT_SIZE_ACT_IMG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VIU_ACT_SIZE_ACT_IMG_WIDTH_SHIFT)) & VIU_ACT_SIZE_ACT_IMG_WIDTH_MASK) #define VIU_ACT_SIZE_ACT_IMG_HEIGHT_MASK (0xFFFF0000U) #define VIU_ACT_SIZE_ACT_IMG_HEIGHT_SHIFT (16U) /*! ACT_IMG_HEIGHT - ACT_IMG_HEIGHT */ #define VIU_ACT_SIZE_ACT_IMG_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VIU_ACT_SIZE_ACT_IMG_HEIGHT_SHIFT)) & VIU_ACT_SIZE_ACT_IMG_HEIGHT_MASK) /*! @} */ /*! * @} */ /* end of group VIU_Register_Masks */ /* VIU - Peripheral instance base addresses */ /** Peripheral VIU base address */ #define VIU_BASE (0x40A80000u) /** Peripheral VIU base pointer */ #define VIU ((VIU_Type *)VIU_BASE) /** Array initializer of VIU peripheral base addresses */ #define VIU_BASE_ADDRS { VIU_BASE } /** Array initializer of VIU peripheral base pointers */ #define VIU_BASE_PTRS { VIU } /*! * @} */ /* end of group VIU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- WDOG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer * @{ */ /** WDOG - Register Layout Typedef */ typedef struct { __IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */ __IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */ __IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */ __IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */ } WDOG_Type; /* ---------------------------------------------------------------------------- -- WDOG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WDOG_Register_Masks WDOG Register Masks * @{ */ /*! @name CS - Watchdog Control and Status Register */ /*! @{ */ #define WDOG_CS_STOP_MASK (0x1U) #define WDOG_CS_STOP_SHIFT (0U) /*! STOP - Stop Enable * 0b0..Watchdog disabled in chip stop mode. * 0b1..Watchdog enabled in chip stop mode. */ #define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK) #define WDOG_CS_WAIT_MASK (0x2U) #define WDOG_CS_WAIT_SHIFT (1U) /*! WAIT - Wait Enable * 0b0..Watchdog disabled in chip wait mode. * 0b1..Watchdog enabled in chip wait mode. */ #define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK) #define WDOG_CS_DBG_MASK (0x4U) #define WDOG_CS_DBG_SHIFT (2U) /*! DBG - Debug Enable * 0b0..Watchdog disabled in chip debug mode. * 0b1..Watchdog enabled in chip debug mode. */ #define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK) #define WDOG_CS_TST_MASK (0x18U) #define WDOG_CS_TST_SHIFT (3U) /*! TST - Watchdog Test * 0b00..Watchdog test mode disabled. * 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should * use this setting to indicate that the watchdog is functioning normally in user mode. * 0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. * 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. */ #define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK) #define WDOG_CS_UPDATE_MASK (0x20U) #define WDOG_CS_UPDATE_SHIFT (5U) /*! UPDATE - Allow updates * 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. * 0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. */ #define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK) #define WDOG_CS_INT_MASK (0x40U) #define WDOG_CS_INT_SHIFT (6U) /*! INT - Watchdog Interrupt * 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed. * 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. */ #define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK) #define WDOG_CS_EN_MASK (0x80U) #define WDOG_CS_EN_SHIFT (7U) /*! EN - Watchdog Enable * 0b0..Watchdog disabled. * 0b1..Watchdog enabled. */ #define WDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK) #define WDOG_CS_CLK_MASK (0x300U) #define WDOG_CS_CLK_SHIFT (8U) /*! CLK - Watchdog Clock * 0b00..Bus clock * 0b01..LPO clock * 0b10..INTCLK (internal clock) * 0b11..ERCLK (external reference clock) */ #define WDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK) #define WDOG_CS_RCS_MASK (0x400U) #define WDOG_CS_RCS_SHIFT (10U) /*! RCS - Reconfiguration Success * 0b0..Reconfiguring WDOG. * 0b1..Reconfiguration is successful. */ #define WDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_RCS_SHIFT)) & WDOG_CS_RCS_MASK) #define WDOG_CS_ULK_MASK (0x800U) #define WDOG_CS_ULK_SHIFT (11U) /*! ULK - Unlock status * 0b0..WDOG is locked. * 0b1..WDOG is unlocked. */ #define WDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_ULK_SHIFT)) & WDOG_CS_ULK_MASK) #define WDOG_CS_PRES_MASK (0x1000U) #define WDOG_CS_PRES_SHIFT (12U) /*! PRES - Watchdog prescaler * 0b0..256 prescaler disabled. * 0b1..256 prescaler enabled. */ #define WDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK) #define WDOG_CS_CMD32EN_MASK (0x2000U) #define WDOG_CS_CMD32EN_SHIFT (13U) /*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words * 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. * 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. */ #define WDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK) #define WDOG_CS_FLG_MASK (0x4000U) #define WDOG_CS_FLG_SHIFT (14U) /*! FLG - Watchdog Interrupt Flag * 0b0..No interrupt occurred. * 0b1..An interrupt occurred. */ #define WDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK) #define WDOG_CS_WIN_MASK (0x8000U) #define WDOG_CS_WIN_SHIFT (15U) /*! WIN - Watchdog Window * 0b0..Window mode disabled. * 0b1..Window mode enabled. */ #define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK) /*! @} */ /*! @name CNT - Watchdog Counter Register */ /*! @{ */ #define WDOG_CNT_CNTLOW_MASK (0xFFU) #define WDOG_CNT_CNTLOW_SHIFT (0U) /*! CNTLOW - Low byte of the Watchdog Counter */ #define WDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK) #define WDOG_CNT_CNTHIGH_MASK (0xFF00U) #define WDOG_CNT_CNTHIGH_SHIFT (8U) /*! CNTHIGH - High byte of the Watchdog Counter */ #define WDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK) /*! @} */ /*! @name TOVAL - Watchdog Timeout Value Register */ /*! @{ */ #define WDOG_TOVAL_TOVALLOW_MASK (0xFFU) #define WDOG_TOVAL_TOVALLOW_SHIFT (0U) /*! TOVALLOW - Low byte of the timeout value */ #define WDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK) #define WDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) #define WDOG_TOVAL_TOVALHIGH_SHIFT (8U) /*! TOVALHIGH - High byte of the timeout value */ #define WDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK) /*! @} */ /*! @name WIN - Watchdog Window Register */ /*! @{ */ #define WDOG_WIN_WINLOW_MASK (0xFFU) #define WDOG_WIN_WINLOW_SHIFT (0U) /*! WINLOW - Low byte of Watchdog Window */ #define WDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK) #define WDOG_WIN_WINHIGH_MASK (0xFF00U) #define WDOG_WIN_WINHIGH_SHIFT (8U) /*! WINHIGH - High byte of Watchdog Window */ #define WDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK) /*! @} */ /*! * @} */ /* end of group WDOG_Register_Masks */ /* WDOG - Peripheral instance base addresses */ /** Peripheral WDOG0 base address */ #define WDOG0_BASE (0x41025000u) /** Peripheral WDOG0 base pointer */ #define WDOG0 ((WDOG_Type *)WDOG0_BASE) /** Peripheral WDOG1 base address */ #define WDOG1_BASE (0x403D0000u) /** Peripheral WDOG1 base pointer */ #define WDOG1 ((WDOG_Type *)WDOG1_BASE) /** Peripheral WDOG2 base address */ #define WDOG2_BASE (0x40430000u) /** Peripheral WDOG2 base pointer */ #define WDOG2 ((WDOG_Type *)WDOG2_BASE) /** Array initializer of WDOG peripheral base addresses */ #define WDOG_BASE_ADDRS { WDOG0_BASE, WDOG1_BASE, WDOG2_BASE } /** Array initializer of WDOG peripheral base pointers */ #define WDOG_BASE_PTRS { WDOG0, WDOG1, WDOG2 } /** Interrupt vectors for the WDOG peripheral type */ #define WDOG_IRQS { WDOG0_IRQn, WDOG1_IRQn, WDOG2_IRQn } /* Extra definition */ #define WDOG_UPDATE_KEY (0xD928C520U) #define WDOG_REFRESH_KEY (0xB480A602U) /*! * @} */ /* end of group WDOG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- XRDC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup XRDC_Peripheral_Access_Layer XRDC Peripheral Access Layer * @{ */ /** XRDC - Register Layout Typedef */ typedef struct { __IO uint32_t CR; /**< Control, offset: 0x0 */ uint8_t RESERVED_0[236]; __I uint32_t HWCFG0; /**< Hardware Configuration 0, offset: 0xF0 */ __I uint32_t HWCFG1; /**< Hardware Configuration 1, offset: 0xF4 */ __I uint32_t HWCFG2; /**< Hardware Configuration 2, offset: 0xF8 */ uint8_t RESERVED_1[4]; __I uint8_t MDACFG[14]; /**< Master Domain Assignment Configuration, array offset: 0x100, array step: 0x1 */ uint8_t RESERVED_2[50]; __I uint8_t MRCFG[7]; /**< Memory Region Configuration, array offset: 0x140, array step: 0x1 */ uint8_t RESERVED_3[185]; __I uint32_t DERRLOC[8]; /**< Domain Error Location, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_4[480]; __IO uint32_t DERR_W[20][4]; /**< Domain Error Word0..Domain Error Word3, array offset: 0x400, array step: index*0x10, index2*0x4 */ uint8_t RESERVED_5[448]; __IO uint32_t PID[4]; /**< Process Identifier, array offset: 0x700, array step: 0x4 */ uint8_t RESERVED_6[240]; struct { /* offset: 0x800, array step: 0x20 */ __IO uint32_t MDA_W[2]; /**< Master Domain Assignment, array offset: 0x800, array step: index*0x20, index2*0x4 */ uint8_t RESERVED_0[24]; } MDA[14]; uint8_t RESERVED_7[1600]; __IO uint32_t PDAC_W[438][2]; /**< Peripheral Domain Access Control, array offset: 0x1000, array step: index*0x8, index2*0x4 */ uint8_t RESERVED_8[592]; struct { /* offset: 0x2000, array step: 0x20 */ __IO uint32_t MRGD_W[4]; /**< Memory Region Descriptor, array offset: 0x2000, array step: index*0x20, index2*0x4 */ uint8_t RESERVED_0[16]; } MRGD[104]; } XRDC_Type; /* ---------------------------------------------------------------------------- -- XRDC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup XRDC_Register_Masks XRDC Register Masks * @{ */ /*! @name CR - Control */ /*! @{ */ #define XRDC_CR_GVLD_MASK (0x1U) #define XRDC_CR_GVLD_SHIFT (0U) /*! GVLD - Global Valid (XRDC global enable/disable). * 0b0..XRDC is disabled. All accesses from all bus masters to all slaves are allowed. * 0b1..XRDC is enabled. */ #define XRDC_CR_GVLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLD_SHIFT)) & XRDC_CR_GVLD_MASK) #define XRDC_CR_HRL_MASK (0x1EU) #define XRDC_CR_HRL_SHIFT (1U) /*! HRL - Hardware Revision Level */ #define XRDC_CR_HRL(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_HRL_SHIFT)) & XRDC_CR_HRL_MASK) #define XRDC_CR_MRF_MASK (0x80U) #define XRDC_CR_MRF_SHIFT (7U) /*! MRF - Memory Region Format * 0b0..Kinetis format based on ARM Cortex-M processor core definition. * 0b1..SMPU family format. */ #define XRDC_CR_MRF(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_MRF_SHIFT)) & XRDC_CR_MRF_MASK) #define XRDC_CR_VAW_MASK (0x100U) #define XRDC_CR_VAW_SHIFT (8U) /*! VAW - Virtualization aware * 0b0..Implementation is not virtualization aware. * 0b1..Implementation is virtualization aware. */ #define XRDC_CR_VAW(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_VAW_SHIFT)) & XRDC_CR_VAW_MASK) #define XRDC_CR_LK1_MASK (0x40000000U) #define XRDC_CR_LK1_SHIFT (30U) /*! LK1 - 1-bit Lock * 0b0..Register can be written by any secure privileged write. * 0b1..Register is locked (read-only) until the next reset. */ #define XRDC_CR_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_LK1_SHIFT)) & XRDC_CR_LK1_MASK) /*! @} */ /*! @name HWCFG0 - Hardware Configuration 0 */ /*! @{ */ #define XRDC_HWCFG0_NDID_MASK (0xFFU) #define XRDC_HWCFG0_NDID_SHIFT (0U) /*! NDID - Number of domains */ #define XRDC_HWCFG0_NDID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NDID_SHIFT)) & XRDC_HWCFG0_NDID_MASK) #define XRDC_HWCFG0_NMSTR_MASK (0xFF00U) #define XRDC_HWCFG0_NMSTR_SHIFT (8U) /*! NMSTR - Number of bus masters */ #define XRDC_HWCFG0_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMSTR_SHIFT)) & XRDC_HWCFG0_NMSTR_MASK) #define XRDC_HWCFG0_NMRC_MASK (0xFF0000U) #define XRDC_HWCFG0_NMRC_SHIFT (16U) /*! NMRC - Number of MRCs */ #define XRDC_HWCFG0_NMRC(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMRC_SHIFT)) & XRDC_HWCFG0_NMRC_MASK) #define XRDC_HWCFG0_NPAC_MASK (0xF000000U) #define XRDC_HWCFG0_NPAC_SHIFT (24U) /*! NPAC - Number of PACs */ #define XRDC_HWCFG0_NPAC(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NPAC_SHIFT)) & XRDC_HWCFG0_NPAC_MASK) #define XRDC_HWCFG0_MID_MASK (0xF0000000U) #define XRDC_HWCFG0_MID_SHIFT (28U) /*! MID - Module ID */ #define XRDC_HWCFG0_MID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_MID_SHIFT)) & XRDC_HWCFG0_MID_MASK) /*! @} */ /*! @name HWCFG1 - Hardware Configuration 1 */ /*! @{ */ #define XRDC_HWCFG1_DID_MASK (0xFU) #define XRDC_HWCFG1_DID_SHIFT (0U) /*! DID - Domain identifier number */ #define XRDC_HWCFG1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG1_DID_SHIFT)) & XRDC_HWCFG1_DID_MASK) /*! @} */ /*! @name HWCFG2 - Hardware Configuration 2 */ /*! @{ */ #define XRDC_HWCFG2_PIDP0_MASK (0x1U) #define XRDC_HWCFG2_PIDP0_SHIFT (0U) /*! PIDP0 - Process identifier * 0b0..Bus master 0 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 0 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP0(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP0_SHIFT)) & XRDC_HWCFG2_PIDP0_MASK) #define XRDC_HWCFG2_PIDP1_MASK (0x2U) #define XRDC_HWCFG2_PIDP1_SHIFT (1U) /*! PIDP1 - Process identifier * 0b0..Bus master 1 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 1 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP1_SHIFT)) & XRDC_HWCFG2_PIDP1_MASK) #define XRDC_HWCFG2_PIDP2_MASK (0x4U) #define XRDC_HWCFG2_PIDP2_SHIFT (2U) /*! PIDP2 - Process identifier * 0b0..Bus master 2 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 2 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP2_SHIFT)) & XRDC_HWCFG2_PIDP2_MASK) #define XRDC_HWCFG2_PIDP3_MASK (0x8U) #define XRDC_HWCFG2_PIDP3_SHIFT (3U) /*! PIDP3 - Process identifier * 0b0..Bus master 3 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 3 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP3(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP3_SHIFT)) & XRDC_HWCFG2_PIDP3_MASK) #define XRDC_HWCFG2_PIDP4_MASK (0x10U) #define XRDC_HWCFG2_PIDP4_SHIFT (4U) /*! PIDP4 - Process identifier * 0b0..Bus master 4 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 4 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP4(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP4_SHIFT)) & XRDC_HWCFG2_PIDP4_MASK) #define XRDC_HWCFG2_PIDP5_MASK (0x20U) #define XRDC_HWCFG2_PIDP5_SHIFT (5U) /*! PIDP5 - Process identifier * 0b0..Bus master 5 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 5 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP5(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP5_SHIFT)) & XRDC_HWCFG2_PIDP5_MASK) #define XRDC_HWCFG2_PIDP6_MASK (0x40U) #define XRDC_HWCFG2_PIDP6_SHIFT (6U) /*! PIDP6 - Process identifier * 0b0..Bus master 6 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 6 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP6(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP6_SHIFT)) & XRDC_HWCFG2_PIDP6_MASK) #define XRDC_HWCFG2_PIDP7_MASK (0x80U) #define XRDC_HWCFG2_PIDP7_SHIFT (7U) /*! PIDP7 - Process identifier * 0b0..Bus master 7 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 7 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP7(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP7_SHIFT)) & XRDC_HWCFG2_PIDP7_MASK) #define XRDC_HWCFG2_PIDP8_MASK (0x100U) #define XRDC_HWCFG2_PIDP8_SHIFT (8U) /*! PIDP8 - Process identifier * 0b0..Bus master 8 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 8 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP8(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP8_SHIFT)) & XRDC_HWCFG2_PIDP8_MASK) #define XRDC_HWCFG2_PIDP9_MASK (0x200U) #define XRDC_HWCFG2_PIDP9_SHIFT (9U) /*! PIDP9 - Process identifier * 0b0..Bus master 9 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 9 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP9(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP9_SHIFT)) & XRDC_HWCFG2_PIDP9_MASK) #define XRDC_HWCFG2_PIDP10_MASK (0x400U) #define XRDC_HWCFG2_PIDP10_SHIFT (10U) /*! PIDP10 - Process identifier * 0b0..Bus master 10 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 10 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP10(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP10_SHIFT)) & XRDC_HWCFG2_PIDP10_MASK) #define XRDC_HWCFG2_PIDP11_MASK (0x800U) #define XRDC_HWCFG2_PIDP11_SHIFT (11U) /*! PIDP11 - Process identifier * 0b0..Bus master 11 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 11 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP11(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP11_SHIFT)) & XRDC_HWCFG2_PIDP11_MASK) #define XRDC_HWCFG2_PIDP12_MASK (0x1000U) #define XRDC_HWCFG2_PIDP12_SHIFT (12U) /*! PIDP12 - Process identifier * 0b0..Bus master 12 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 12 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP12(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP12_SHIFT)) & XRDC_HWCFG2_PIDP12_MASK) #define XRDC_HWCFG2_PIDP13_MASK (0x2000U) #define XRDC_HWCFG2_PIDP13_SHIFT (13U) /*! PIDP13 - Process identifier * 0b0..Bus master 13 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 13 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP13(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP13_SHIFT)) & XRDC_HWCFG2_PIDP13_MASK) #define XRDC_HWCFG2_PIDP14_MASK (0x4000U) #define XRDC_HWCFG2_PIDP14_SHIFT (14U) /*! PIDP14 - Process identifier * 0b0..Bus master 14 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 14 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP14(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP14_SHIFT)) & XRDC_HWCFG2_PIDP14_MASK) #define XRDC_HWCFG2_PIDP15_MASK (0x8000U) #define XRDC_HWCFG2_PIDP15_SHIFT (15U) /*! PIDP15 - Process identifier * 0b0..Bus master 15 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 15 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP15(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP15_SHIFT)) & XRDC_HWCFG2_PIDP15_MASK) #define XRDC_HWCFG2_PIDP16_MASK (0x10000U) #define XRDC_HWCFG2_PIDP16_SHIFT (16U) /*! PIDP16 - Process identifier * 0b0..Bus master 16 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 16 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP16(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP16_SHIFT)) & XRDC_HWCFG2_PIDP16_MASK) #define XRDC_HWCFG2_PIDP17_MASK (0x20000U) #define XRDC_HWCFG2_PIDP17_SHIFT (17U) /*! PIDP17 - Process identifier * 0b0..Bus master 17 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 17 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP17(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP17_SHIFT)) & XRDC_HWCFG2_PIDP17_MASK) #define XRDC_HWCFG2_PIDP18_MASK (0x40000U) #define XRDC_HWCFG2_PIDP18_SHIFT (18U) /*! PIDP18 - Process identifier * 0b0..Bus master 18 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 18 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP18(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP18_SHIFT)) & XRDC_HWCFG2_PIDP18_MASK) #define XRDC_HWCFG2_PIDP19_MASK (0x80000U) #define XRDC_HWCFG2_PIDP19_SHIFT (19U) /*! PIDP19 - Process identifier * 0b0..Bus master 19 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 19 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP19(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP19_SHIFT)) & XRDC_HWCFG2_PIDP19_MASK) #define XRDC_HWCFG2_PIDP20_MASK (0x100000U) #define XRDC_HWCFG2_PIDP20_SHIFT (20U) /*! PIDP20 - Process identifier * 0b0..Bus master 20 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 20 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP20(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP20_SHIFT)) & XRDC_HWCFG2_PIDP20_MASK) #define XRDC_HWCFG2_PIDP21_MASK (0x200000U) #define XRDC_HWCFG2_PIDP21_SHIFT (21U) /*! PIDP21 - Process identifier * 0b0..Bus master 21 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 21 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP21(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP21_SHIFT)) & XRDC_HWCFG2_PIDP21_MASK) #define XRDC_HWCFG2_PIDP22_MASK (0x400000U) #define XRDC_HWCFG2_PIDP22_SHIFT (22U) /*! PIDP22 - Process identifier * 0b0..Bus master 22 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 22 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP22(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP22_SHIFT)) & XRDC_HWCFG2_PIDP22_MASK) #define XRDC_HWCFG2_PIDP23_MASK (0x800000U) #define XRDC_HWCFG2_PIDP23_SHIFT (23U) /*! PIDP23 - Process identifier * 0b0..Bus master 23 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 23 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP23(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP23_SHIFT)) & XRDC_HWCFG2_PIDP23_MASK) #define XRDC_HWCFG2_PIDP24_MASK (0x1000000U) #define XRDC_HWCFG2_PIDP24_SHIFT (24U) /*! PIDP24 - Process identifier * 0b0..Bus master 24 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 24 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP24(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP24_SHIFT)) & XRDC_HWCFG2_PIDP24_MASK) #define XRDC_HWCFG2_PIDP25_MASK (0x2000000U) #define XRDC_HWCFG2_PIDP25_SHIFT (25U) /*! PIDP25 - Process identifier * 0b0..Bus master 25 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 25 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP25(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP25_SHIFT)) & XRDC_HWCFG2_PIDP25_MASK) #define XRDC_HWCFG2_PIDP26_MASK (0x4000000U) #define XRDC_HWCFG2_PIDP26_SHIFT (26U) /*! PIDP26 - Process identifier * 0b0..Bus master 26 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 26 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP26(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP26_SHIFT)) & XRDC_HWCFG2_PIDP26_MASK) #define XRDC_HWCFG2_PIDP27_MASK (0x8000000U) #define XRDC_HWCFG2_PIDP27_SHIFT (27U) /*! PIDP27 - Process identifier * 0b0..Bus master 27 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 27 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP27(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP27_SHIFT)) & XRDC_HWCFG2_PIDP27_MASK) #define XRDC_HWCFG2_PIDP28_MASK (0x10000000U) #define XRDC_HWCFG2_PIDP28_SHIFT (28U) /*! PIDP28 - Process identifier * 0b0..Bus master 28 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 28 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP28(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP28_SHIFT)) & XRDC_HWCFG2_PIDP28_MASK) #define XRDC_HWCFG2_PIDP29_MASK (0x20000000U) #define XRDC_HWCFG2_PIDP29_SHIFT (29U) /*! PIDP29 - Process identifier * 0b0..Bus master 29 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 29 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP29(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP29_SHIFT)) & XRDC_HWCFG2_PIDP29_MASK) #define XRDC_HWCFG2_PIDP30_MASK (0x40000000U) #define XRDC_HWCFG2_PIDP30_SHIFT (30U) /*! PIDP30 - Process identifier * 0b0..Bus master 30 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 30 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP30(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP30_SHIFT)) & XRDC_HWCFG2_PIDP30_MASK) #define XRDC_HWCFG2_PIDP31_MASK (0x80000000U) #define XRDC_HWCFG2_PIDP31_SHIFT (31U) /*! PIDP31 - Process identifier * 0b0..Bus master 31 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. * 0b1..Bus master 31 sources a process identifier register to the XRDC_MDAC logic. */ #define XRDC_HWCFG2_PIDP31(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP31_SHIFT)) & XRDC_HWCFG2_PIDP31_MASK) /*! @} */ /*! @name MDACFG - Master Domain Assignment Configuration */ /*! @{ */ #define XRDC_MDACFG_NMDAR_MASK (0xFU) #define XRDC_MDACFG_NMDAR_SHIFT (0U) /*! NMDAR - Number of master domain assignment registers for bus master m */ #define XRDC_MDACFG_NMDAR(x) (((uint8_t)(((uint8_t)(x)) << XRDC_MDACFG_NMDAR_SHIFT)) & XRDC_MDACFG_NMDAR_MASK) #define XRDC_MDACFG_NCM_MASK (0x80U) #define XRDC_MDACFG_NCM_SHIFT (7U) /*! NCM - Non-CPU Master * 0b0..Bus master is a processor. * 0b1..Bus master is a non-processor. */ #define XRDC_MDACFG_NCM(x) (((uint8_t)(((uint8_t)(x)) << XRDC_MDACFG_NCM_SHIFT)) & XRDC_MDACFG_NCM_MASK) /*! @} */ /* The count of XRDC_MDACFG */ #define XRDC_MDACFG_COUNT (14U) /*! @name MRCFG - Memory Region Configuration */ /*! @{ */ #define XRDC_MRCFG_NMRGD_MASK (0x1FU) #define XRDC_MRCFG_NMRGD_SHIFT (0U) /*! NMRGD - Number of memory region descriptors for memory region controller n */ #define XRDC_MRCFG_NMRGD(x) (((uint8_t)(((uint8_t)(x)) << XRDC_MRCFG_NMRGD_SHIFT)) & XRDC_MRCFG_NMRGD_MASK) /*! @} */ /* The count of XRDC_MRCFG */ #define XRDC_MRCFG_COUNT (7U) /*! @name DERRLOC - Domain Error Location */ /*! @{ */ #define XRDC_DERRLOC_MRCINST_MASK (0xFFFFU) #define XRDC_DERRLOC_MRCINST_SHIFT (0U) /*! MRCINST - MRC instance */ #define XRDC_DERRLOC_MRCINST(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_MRCINST_SHIFT)) & XRDC_DERRLOC_MRCINST_MASK) #define XRDC_DERRLOC_PACINST_MASK (0xF0000U) #define XRDC_DERRLOC_PACINST_SHIFT (16U) /*! PACINST - PAC instance */ #define XRDC_DERRLOC_PACINST(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_PACINST_SHIFT)) & XRDC_DERRLOC_PACINST_MASK) /*! @} */ /* The count of XRDC_DERRLOC */ #define XRDC_DERRLOC_COUNT (8U) /*! @name DERR_W - Domain Error Word0..Domain Error Word3 */ /*! @{ */ #define XRDC_DERR_W_EADDR_MASK (0xFFFFFFFFU) #define XRDC_DERR_W_EADDR_SHIFT (0U) /*! EADDR - Error address */ #define XRDC_DERR_W_EADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EADDR_SHIFT)) & XRDC_DERR_W_EADDR_MASK) #define XRDC_DERR_W_EDID_MASK (0xFU) #define XRDC_DERR_W_EDID_SHIFT (0U) /*! EDID - Error domain identifier */ #define XRDC_DERR_W_EDID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EDID_SHIFT)) & XRDC_DERR_W_EDID_MASK) #define XRDC_DERR_W_EATR_MASK (0x700U) #define XRDC_DERR_W_EATR_SHIFT (8U) /*! EATR - Error attributes * 0b000..Secure user mode, instruction fetch access. * 0b001..Secure user mode, data access. * 0b010..Secure privileged mode, instruction fetch access. * 0b011..Secure privileged mode, data access. * 0b100..Nonsecure user mode, instruction fetch access. * 0b101..Nonsecure user mode, data access. * 0b110..Nonsecure privileged mode, instruction fetch access. * 0b111..Nonsecure privileged mode, data access. */ #define XRDC_DERR_W_EATR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EATR_SHIFT)) & XRDC_DERR_W_EATR_MASK) #define XRDC_DERR_W_ERW_MASK (0x800U) #define XRDC_DERR_W_ERW_SHIFT (11U) /*! ERW - Error read/write * 0b0..Read access * 0b1..Write access */ #define XRDC_DERR_W_ERW(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_ERW_SHIFT)) & XRDC_DERR_W_ERW_MASK) #define XRDC_DERR_W_EPORT_MASK (0x7000000U) #define XRDC_DERR_W_EPORT_SHIFT (24U) /*! EPORT - Error port */ #define XRDC_DERR_W_EPORT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EPORT_SHIFT)) & XRDC_DERR_W_EPORT_MASK) #define XRDC_DERR_W_EST_MASK (0xC0000000U) #define XRDC_DERR_W_EST_SHIFT (30U) /*! EST - Error state * 0b00..No access violation has been detected. * 0b01..No access violation has been detected. * 0b10..A single access violation has been detected. * 0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the * address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. */ #define XRDC_DERR_W_EST(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EST_SHIFT)) & XRDC_DERR_W_EST_MASK) #define XRDC_DERR_W_RECR_MASK (0xC0000000U) #define XRDC_DERR_W_RECR_SHIFT (30U) /*! RECR - Rearm Error Capture registers */ #define XRDC_DERR_W_RECR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_RECR_SHIFT)) & XRDC_DERR_W_RECR_MASK) /*! @} */ /* The count of XRDC_DERR_W */ #define XRDC_DERR_W_COUNT (20U) /* The count of XRDC_DERR_W */ #define XRDC_DERR_W_COUNT2 (4U) /*! @name PID - Process Identifier */ /*! @{ */ #define XRDC_PID_PID_MASK (0x3FU) #define XRDC_PID_PID_SHIFT (0U) /*! PID - Process identifier */ #define XRDC_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_PID_SHIFT)) & XRDC_PID_PID_MASK) #define XRDC_PID_LMNUM_MASK (0x3F0000U) #define XRDC_PID_LMNUM_SHIFT (16U) /*! LMNUM - Locked Master NUMber */ #define XRDC_PID_LMNUM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_LMNUM_SHIFT)) & XRDC_PID_LMNUM_MASK) #define XRDC_PID_ELK22H_MASK (0x1000000U) #define XRDC_PID_ELK22H_SHIFT (24U) /*! ELK22H - Enable (LK2 = 2) special handling */ #define XRDC_PID_ELK22H(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_ELK22H_SHIFT)) & XRDC_PID_ELK22H_MASK) #define XRDC_PID_TSM_MASK (0x10000000U) #define XRDC_PID_TSM_SHIFT (28U) /*! TSM - Three-state model */ #define XRDC_PID_TSM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_TSM_SHIFT)) & XRDC_PID_TSM_MASK) #define XRDC_PID_LK2_MASK (0x60000000U) #define XRDC_PID_LK2_SHIFT (29U) /*! LK2 - Lock * 0b00..Register can be written by any secure privileged write. * 0b01..Register can be written by any secure privileged write. * 0b10..Register can only be written by a secure privileged write from bus master m. * 0b11..Register is locked (read-only) until the next reset. */ #define XRDC_PID_LK2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_LK2_SHIFT)) & XRDC_PID_LK2_MASK) /*! @} */ /* The count of XRDC_PID */ #define XRDC_PID_COUNT (4U) /*! @name MDA_W - Master Domain Assignment */ /*! @{ */ #define XRDC_MDA_W_DID_MASK (0x7U) #define XRDC_MDA_W_DID_SHIFT (0U) /*! DID - Domain identifier */ #define XRDC_MDA_W_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DID_SHIFT)) & XRDC_MDA_W_DID_MASK) #define XRDC_MDA_W_DIDS_MASK (0x30U) #define XRDC_MDA_W_DIDS_SHIFT (4U) /*! DIDS - DID Select * 0b00..Use DID field of this register as the domain identifier. * 0b01..Use the input DID as the domain identifier. * 0b10..Use bits [3:2] of this register concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. * 0b11..Reserved for future use. */ #define XRDC_MDA_W_DIDS(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DIDS_SHIFT)) & XRDC_MDA_W_DIDS_MASK) #define XRDC_MDA_W_PA_MASK (0x30U) #define XRDC_MDA_W_PA_SHIFT (4U) /*! PA - Privileged attribute * 0b00..Force the bus attribute for this master to user. * 0b01..Force the bus attribute for this master to privileged. * 0b10..Use the bus master's privileged/user attribute directly. * 0b11..Use the bus master's privileged/user attribute directly. */ #define XRDC_MDA_W_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PA_SHIFT)) & XRDC_MDA_W_PA_MASK) #define XRDC_MDA_W_PE_MASK (0xC0U) #define XRDC_MDA_W_PE_SHIFT (6U) /*! PE - Process identifier enable * 0b00..No process identifier is included in the domain hit evaluation. * 0b01..No process identifier is included in the domain hit evaluation. * 0b10..The process identifier is included in the domain hit evaluation as defined by the expression: * partial_domain_hit = (PE == 10b) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) * 0b11..The process identifier is included in the domain hit evaluation as defined by the expression: * partial_domain_hit = (PE == 11b) && ~((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) */ #define XRDC_MDA_W_PE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PE_SHIFT)) & XRDC_MDA_W_PE_MASK) #define XRDC_MDA_W_SA_MASK (0xC0U) #define XRDC_MDA_W_SA_SHIFT (6U) /*! SA - Secure attribute * 0b00..Force the bus attribute for this master to secure. * 0b01..Force the bus attribute for this master to nonsecure. * 0b10..Use the bus master's secure/nonsecure attribute directly. * 0b11..Use the bus master's secure/nonsecure attribute directly. */ #define XRDC_MDA_W_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_SA_SHIFT)) & XRDC_MDA_W_SA_MASK) #define XRDC_MDA_W_DIDB_MASK (0x100U) #define XRDC_MDA_W_DIDB_SHIFT (8U) /*! DIDB - DID Bypass * 0b0..Use MDAn[3:0] as the domain identifier. * 0b1..Use the DID input as the domain identifier. */ #define XRDC_MDA_W_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DIDB_SHIFT)) & XRDC_MDA_W_DIDB_MASK) #define XRDC_MDA_W_PIDM_MASK (0x3F00U) #define XRDC_MDA_W_PIDM_SHIFT (8U) /*! PIDM - Process Identifier Mask */ #define XRDC_MDA_W_PIDM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PIDM_SHIFT)) & XRDC_MDA_W_PIDM_MASK) #define XRDC_MDA_W_PID_MASK (0x3F0000U) #define XRDC_MDA_W_PID_SHIFT (16U) /*! PID - Process Identifier */ #define XRDC_MDA_W_PID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PID_SHIFT)) & XRDC_MDA_W_PID_MASK) #define XRDC_MDA_W_DFMT_MASK (0x20000000U) #define XRDC_MDA_W_DFMT_SHIFT (29U) /*! DFMT - Domain format * 0b0..Processor-core domain assignment * 0b1..Non-processor domain assignment */ #define XRDC_MDA_W_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DFMT_SHIFT)) & XRDC_MDA_W_DFMT_MASK) #define XRDC_MDA_W_LK1_MASK (0x40000000U) #define XRDC_MDA_W_LK1_SHIFT (30U) /*! LK1 - 1-bit Lock * 0b0..Register can be written by any secure privileged write. * 0b1..Register is locked (read-only) until the next reset. */ #define XRDC_MDA_W_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_LK1_SHIFT)) & XRDC_MDA_W_LK1_MASK) #define XRDC_MDA_W_VLD_MASK (0x80000000U) #define XRDC_MDA_W_VLD_SHIFT (31U) /*! VLD - Valid * 0b0..The Wr domain assignment is invalid. * 0b1..The Wr domain assignment is valid. */ #define XRDC_MDA_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_VLD_SHIFT)) & XRDC_MDA_W_VLD_MASK) /*! @} */ /* The count of XRDC_MDA_W */ #define XRDC_MDA_W_COUNT (14U) /* The count of XRDC_MDA_W */ #define XRDC_MDA_W_COUNT2 (2U) /*! @name PDAC_W - Peripheral Domain Access Control */ /*! @{ */ #define XRDC_PDAC_W_D0ACP_MASK (0x7U) #define XRDC_PDAC_W_D0ACP_SHIFT (0U) /*! D0ACP - Domain 0 access control policy */ #define XRDC_PDAC_W_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D0ACP_SHIFT)) & XRDC_PDAC_W_D0ACP_MASK) #define XRDC_PDAC_W_D1ACP_MASK (0x38U) #define XRDC_PDAC_W_D1ACP_SHIFT (3U) /*! D1ACP - Domain 1 access control policy */ #define XRDC_PDAC_W_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D1ACP_SHIFT)) & XRDC_PDAC_W_D1ACP_MASK) #define XRDC_PDAC_W_D2ACP_MASK (0x1C0U) #define XRDC_PDAC_W_D2ACP_SHIFT (6U) /*! D2ACP - Domain 2 access control policy */ #define XRDC_PDAC_W_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D2ACP_SHIFT)) & XRDC_PDAC_W_D2ACP_MASK) #define XRDC_PDAC_W_D3ACP_MASK (0xE00U) #define XRDC_PDAC_W_D3ACP_SHIFT (9U) /*! D3ACP - Domain 3 access control policy */ #define XRDC_PDAC_W_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D3ACP_SHIFT)) & XRDC_PDAC_W_D3ACP_MASK) #define XRDC_PDAC_W_D4ACP_MASK (0x7000U) #define XRDC_PDAC_W_D4ACP_SHIFT (12U) /*! D4ACP - Domain 4 access control policy */ #define XRDC_PDAC_W_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D4ACP_SHIFT)) & XRDC_PDAC_W_D4ACP_MASK) #define XRDC_PDAC_W_D5ACP_MASK (0x38000U) #define XRDC_PDAC_W_D5ACP_SHIFT (15U) /*! D5ACP - Domain 5 access control policy */ #define XRDC_PDAC_W_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D5ACP_SHIFT)) & XRDC_PDAC_W_D5ACP_MASK) #define XRDC_PDAC_W_D6ACP_MASK (0x1C0000U) #define XRDC_PDAC_W_D6ACP_SHIFT (18U) /*! D6ACP - Domain 6 access control policy */ #define XRDC_PDAC_W_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D6ACP_SHIFT)) & XRDC_PDAC_W_D6ACP_MASK) #define XRDC_PDAC_W_D7ACP_MASK (0xE00000U) #define XRDC_PDAC_W_D7ACP_SHIFT (21U) /*! D7ACP - Domain 7 access control policy */ #define XRDC_PDAC_W_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D7ACP_SHIFT)) & XRDC_PDAC_W_D7ACP_MASK) #define XRDC_PDAC_W_SNUM_MASK (0xF000000U) #define XRDC_PDAC_W_SNUM_SHIFT (24U) /*! SNUM - Semaphore number */ #define XRDC_PDAC_W_SNUM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_SNUM_SHIFT)) & XRDC_PDAC_W_SNUM_MASK) #define XRDC_PDAC_W_LK2_MASK (0x60000000U) #define XRDC_PDAC_W_LK2_SHIFT (29U) /*! LK2 - Lock * 0b00..Entire PDACs can be written. * 0b01..Entire PDACs can be written. * 0b10..Domain x can only update the DxACP field; no other PDACs fields can be written. * 0b11..PDACs is locked (read-only) until the next reset. */ #define XRDC_PDAC_W_LK2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_LK2_SHIFT)) & XRDC_PDAC_W_LK2_MASK) #define XRDC_PDAC_W_SE_MASK (0x40000000U) #define XRDC_PDAC_W_SE_SHIFT (30U) /*! SE - Semaphore enable * 0b0..Do not include a semaphore in the DxACP evaluation. * 0b1..Include the semaphore defined by SNUM in the DxACP evaluation. */ #define XRDC_PDAC_W_SE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_SE_SHIFT)) & XRDC_PDAC_W_SE_MASK) #define XRDC_PDAC_W_VLD_MASK (0x80000000U) #define XRDC_PDAC_W_VLD_SHIFT (31U) /*! VLD - Valid * 0b0..The PDACs assignment is invalid. * 0b1..The PDACs assignment is valid. */ #define XRDC_PDAC_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_VLD_SHIFT)) & XRDC_PDAC_W_VLD_MASK) /*! @} */ /* The count of XRDC_PDAC_W */ #define XRDC_PDAC_W_COUNT (438U) /* The count of XRDC_PDAC_W */ #define XRDC_PDAC_W_COUNT2 (2U) /*! @name MRGD_W - Memory Region Descriptor */ /*! @{ */ #define XRDC_MRGD_W_D0ACP_MASK (0x7U) #define XRDC_MRGD_W_D0ACP_SHIFT (0U) /*! D0ACP - Domain 0 access control policy */ #define XRDC_MRGD_W_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D0ACP_SHIFT)) & XRDC_MRGD_W_D0ACP_MASK) #define XRDC_MRGD_W_SRD_MASK (0xFFU) #define XRDC_MRGD_W_SRD_SHIFT (0U) /*! SRD - Subregion disable */ #define XRDC_MRGD_W_SRD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_SRD_SHIFT)) & XRDC_MRGD_W_SRD_MASK) #define XRDC_MRGD_W_D1ACP_MASK (0x38U) #define XRDC_MRGD_W_D1ACP_SHIFT (3U) /*! D1ACP - Domain 1 access control policy */ #define XRDC_MRGD_W_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D1ACP_SHIFT)) & XRDC_MRGD_W_D1ACP_MASK) #define XRDC_MRGD_W_BASEADDR_MASK (0xFFFFFFE0U) #define XRDC_MRGD_W_BASEADDR_SHIFT (5U) /*! BASEADDR - Base Address */ #define XRDC_MRGD_W_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_BASEADDR_SHIFT)) & XRDC_MRGD_W_BASEADDR_MASK) #define XRDC_MRGD_W_D2ACP_MASK (0x1C0U) #define XRDC_MRGD_W_D2ACP_SHIFT (6U) /*! D2ACP - Domain 2 access control policy */ #define XRDC_MRGD_W_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D2ACP_SHIFT)) & XRDC_MRGD_W_D2ACP_MASK) #define XRDC_MRGD_W_SZ_MASK (0x1F00U) #define XRDC_MRGD_W_SZ_SHIFT (8U) /*! SZ - Region Size */ #define XRDC_MRGD_W_SZ(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_SZ_SHIFT)) & XRDC_MRGD_W_SZ_MASK) #define XRDC_MRGD_W_D3ACP_MASK (0xE00U) #define XRDC_MRGD_W_D3ACP_SHIFT (9U) /*! D3ACP - Domain 3 access control policy */ #define XRDC_MRGD_W_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D3ACP_SHIFT)) & XRDC_MRGD_W_D3ACP_MASK) #define XRDC_MRGD_W_D4ACP_MASK (0x7000U) #define XRDC_MRGD_W_D4ACP_SHIFT (12U) /*! D4ACP - Domain 4 access control policy */ #define XRDC_MRGD_W_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D4ACP_SHIFT)) & XRDC_MRGD_W_D4ACP_MASK) #define XRDC_MRGD_W_D5ACP_MASK (0x38000U) #define XRDC_MRGD_W_D5ACP_SHIFT (15U) /*! D5ACP - Domain 5 access control policy */ #define XRDC_MRGD_W_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D5ACP_SHIFT)) & XRDC_MRGD_W_D5ACP_MASK) #define XRDC_MRGD_W_D6ACP_MASK (0x1C0000U) #define XRDC_MRGD_W_D6ACP_SHIFT (18U) /*! D6ACP - Domain 6 access control policy */ #define XRDC_MRGD_W_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D6ACP_SHIFT)) & XRDC_MRGD_W_D6ACP_MASK) #define XRDC_MRGD_W_D7ACP_MASK (0xE00000U) #define XRDC_MRGD_W_D7ACP_SHIFT (21U) /*! D7ACP - Domain 7 access control policy */ #define XRDC_MRGD_W_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D7ACP_SHIFT)) & XRDC_MRGD_W_D7ACP_MASK) #define XRDC_MRGD_W_SNUM_MASK (0xF000000U) #define XRDC_MRGD_W_SNUM_SHIFT (24U) /*! SNUM - Semaphore number */ #define XRDC_MRGD_W_SNUM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_SNUM_SHIFT)) & XRDC_MRGD_W_SNUM_MASK) #define XRDC_MRGD_W_LK2_MASK (0x60000000U) #define XRDC_MRGD_W_LK2_SHIFT (29U) /*! LK2 - Lock * 0b00..Entire MRGDn can be written. * 0b01..Reserved * 0b10..Domain x can only update the DxACP field for domain x; no other ACP fields can be written. * 0b11..MRGDn is locked (read-only) until the next reset. */ #define XRDC_MRGD_W_LK2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_LK2_SHIFT)) & XRDC_MRGD_W_LK2_MASK) #define XRDC_MRGD_W_SE_MASK (0x40000000U) #define XRDC_MRGD_W_SE_SHIFT (30U) /*! SE - Semaphore enable * 0b0..Do not include a semaphore in the DxACP evaluation. * 0b1..Include the semaphore defined by SNUM in the DxACP evaluation. */ #define XRDC_MRGD_W_SE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_SE_SHIFT)) & XRDC_MRGD_W_SE_MASK) #define XRDC_MRGD_W_VLD_MASK (0x80000000U) #define XRDC_MRGD_W_VLD_SHIFT (31U) /*! VLD - Valid * 0b0..The MRGDn assignment is invalid. * 0b1..The MRGDn assignment is valid. */ #define XRDC_MRGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_VLD_SHIFT)) & XRDC_MRGD_W_VLD_MASK) /*! @} */ /* The count of XRDC_MRGD_W */ #define XRDC_MRGD_W_COUNT (104U) /* The count of XRDC_MRGD_W */ #define XRDC_MRGD_W_COUNT2 (4U) /*! * @} */ /* end of group XRDC_Register_Masks */ /* XRDC - Peripheral instance base addresses */ /** Peripheral XRDC base address */ #define XRDC_BASE (0x41014000u) /** Peripheral XRDC base pointer */ #define XRDC ((XRDC_Type *)XRDC_BASE) /** Array initializer of XRDC peripheral base addresses */ #define XRDC_BASE_ADDRS { XRDC_BASE } /** Array initializer of XRDC peripheral base pointers */ #define XRDC_BASE_PTRS { XRDC } /*! * @} */ /* end of group XRDC_Peripheral_Access_Layer */ /* ** End of section using anonymous unions */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #else #pragma pop #endif #elif defined(__GNUC__) /* leave anonymous unions enabled */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=default #else #error Not supported compiler type #endif /*! * @} */ /* end of group Peripheral_access_layer */ /* ---------------------------------------------------------------------------- -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). ---------------------------------------------------------------------------- */ /*! * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). * @{ */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang system_header #endif #elif defined(__IAR_SYSTEMS_ICC__) #pragma system_include #endif /** * @brief Mask and left-shift a bit field value for use in a register bit range. * @param field Name of the register bit field. * @param value Value of the bit field. * @return Masked and shifted value. */ #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) /** * @brief Mask and right-shift a register value to extract a bit field value. * @param field Name of the register bit field. * @param value Value of the register. * @return Masked and shifted bit field value. */ #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) /*! * @} */ /* end of group Bit_Field_Generic_Macros */ /* ---------------------------------------------------------------------------- -- SDK Compatibility ---------------------------------------------------------------------------- */ /*! * @addtogroup SDK_Compatibility_Symbols SDK Compatibility * @{ */ /* No SDK compatibility issues. */ /*! * @} */ /* end of group SDK_Compatibility_Symbols */ #endif /* _MCIMX7U3_CM4_H_ */