/* ** ################################################################### ** Processors: LPC54607J256BD208 ** LPC54607J256ET180 ** LPC54607J512ET180 ** ** Compilers: GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** ** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017 ** Version: rev. 1.2, 2017-06-08 ** Build: b201015 ** ** Abstract: ** Provides a system configuration function and a global variable that ** contains the system frequency. It configures the device and initializes ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2020 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2016-08-12) ** Initial version. ** - rev. 1.1 (2016-11-25) ** Update CANFD and Classic CAN register. ** Add MAC TIMERSTAMP registers. ** - rev. 1.2 (2017-06-08) ** Remove RTC_CTRL_RTC_OSC_BYPASS. ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. ** Remove RESET and HALT from SYSCON_AHBCLKDIV. ** ** ################################################################### */ /*! * @file LPC54607 * @version 1.2 * @date 2017-06-08 * @brief Device specific configuration file for LPC54607 (implementation file) * * Provides a system configuration function and a global variable that contains * the system frequency. It configures the device and initializes the oscillator * (PLL) that is part of the microcontroller device. */ #include #include "fsl_device_registers.h" #define NVALMAX (0x100) #define PVALMAX (0x20U) #define MVALMAX (0x8000U) #define PLL_MDEC_VAL_P (0U) /* MDEC is in bits 16:0 */ #define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P) #define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ #define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) #define PLL_PDEC_VAL_P (0U) /* PDEC is in bits 6:0 */ #define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P) static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46, 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61}; /* Get WATCH DOG Clk */ static uint32_t getWdtOscFreq(void) { uint8_t freq_sel, div_sel; if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) == SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) { return 0U; } else { div_sel = (uint8_t)((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1UL) << 1UL; freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)]; return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel); } } /* Find decoded N value for raw NDEC value */ static uint32_t pllDecodeN(uint32_t NDEC) { uint32_t n, x, i; /* Find NDec */ switch (NDEC) { case 0x3FFU: n = 0UL; break; case 0x302U: n = 1UL; break; case 0x202U: n = 2UL; break; default: x = 0x080UL; n = 0xFFFFFFFFUL; for (i = NVALMAX; i >= 3UL; i--) { x = (((x ^ (x >> 2UL) ^ (x >> 3UL) ^ (x >> 4UL)) & 1UL) << 7UL) | ((x >> 1UL) & 0x7FUL); if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) { /* Decoded value of NDEC */ n = i; } if (n != 0xFFFFFFFFUL) { break; } } break; } return n; } /* Find decoded P value for raw PDEC value */ static uint32_t pllDecodeP(uint32_t PDEC) { uint32_t p, x, i; /* Find PDec */ switch (PDEC) { case 0x7FU: p = 0UL; break; case 0x62U: p = 1UL; break; case 0x42U: p = 2UL; break; default: x = 0x10UL; p = 0xFFFFFFFFUL; for (i = PVALMAX; i >= 3UL; i--) { x = (((x ^ (x >> 2UL)) & 1UL) << 4UL) | ((x >> 1UL) & 0xFUL); if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) { /* Decoded value of PDEC */ p = i; } if (p != 0xFFFFFFFFUL) { break; } } break; } return p; } /* Find decoded M value for raw MDEC value */ static uint32_t pllDecodeM(uint32_t MDEC) { uint32_t m, i, x; /* Find MDec */ switch (MDEC) { case 0x1FFFFU: m = 0UL; break; case 0x18003U: m = 1UL; break; case 0x10003U: m = 2UL; break; default: x = 0x04000UL; m = 0xFFFFFFFFUL; for (i = MVALMAX; i >= 3UL; i--) { x = (((x ^ (x >> 1UL)) & 1UL) << 14UL) | ((x >> 1UL) & 0x3FFFUL); if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC) { /* Decoded value of MDEC */ m = i; } if (m != 0xFFFFFFFFUL) { break; } } break; } return m; } /* Get predivider (N) from PLL NDEC setting */ static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg) { uint32_t preDiv = 1U; /* Direct input is not used? */ if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0U) { /* Decode NDEC value to get (N) pre divider */ preDiv = pllDecodeN(nDecReg & 0x3FFU); if (preDiv == 0U) { preDiv = 1U; } } /* Adjusted by 1, directi is used to bypass */ return preDiv; } /* Get postdivider (P) from PLL PDEC setting */ static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg) { uint32_t postDiv = 1U; /* Direct input is not used? */ if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U) { /* Decode PDEC value to get (P) post divider */ postDiv = 2U * pllDecodeP(pDecReg & 0x7FU); if (postDiv == 0U) { postDiv = 2U; } } /* Adjusted by 1, directo is used to bypass */ return postDiv; } /* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) { uint32_t mMult = 1U; /* Decode MDEC value to get (M) multiplier */ mMult = pllDecodeM(mDecReg & 0x1FFFFU); if (mMult == 0U) { mMult = 1U; } return mMult; } /* ---------------------------------------------------------------------------- -- Core clock ---------------------------------------------------------------------------- */ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; /* ---------------------------------------------------------------------------- -- SystemInit() ---------------------------------------------------------------------------- */ void SystemInit (void) { #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ #if defined(__MCUXPRESSO) extern void(*const g_pfnVectors[]) (void); SCB->VTOR = (uint32_t) &g_pfnVectors; #else extern void *__Vectors; SCB->VTOR = (uint32_t) &__Vectors; #endif SYSCON->ARMTRACECLKDIV = 0U; /* Optionally enable RAM banks that may be off by default at reset */ #if !defined(DONT_ENABLE_DISABLED_RAMBANKS) SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK; #endif SystemInitHook(); } /* ---------------------------------------------------------------------------- -- SystemCoreClockUpdate() ---------------------------------------------------------------------------- */ void SystemCoreClockUpdate (void) { uint32_t clkRate = 0U; uint32_t prediv, postdiv; uint64_t workRate; switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) { case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) { case 0x00U: /* FRO 12 MHz (fro_12m) */ clkRate = CLK_FRO_12MHZ; break; case 0x01U: /* CLKIN Source (clk_in) */ clkRate = CLK_CLK_IN; break; case 0x02U: /* Watchdog oscillator (wdt_clk) */ clkRate = getWdtOscFreq(); break; default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */ if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) == SYSCON_FROCTRL_SEL_MASK) { clkRate = CLK_FRO_96MHZ; } else { clkRate = CLK_FRO_48MHZ; } break; } break; case 0x02U: /* System PLL clock (pll_clk)*/ switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) { case 0x00U: /* FRO 12 MHz (fro_12m) */ clkRate = CLK_FRO_12MHZ; break; case 0x01U: /* CLKIN Source (clk_in) */ clkRate = CLK_CLK_IN; break; case 0x02U: /* Watchdog oscillator (wdt_clk) */ clkRate = getWdtOscFreq(); break; case 0x03U: /* RTC oscillator 32 kHz output (32k_clk) */ clkRate = CLK_RTC_32K_CLK; break; default: clkRate = 0U; break; } if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0U) { /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC); postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC); /* Adjust input clock */ clkRate = clkRate / prediv; /* MDEC used for rate */ workRate = (uint64_t)(clkRate) * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC); clkRate = (uint32_t)(workRate / ((uint64_t)postdiv)); clkRate = clkRate * 2UL; /* PLL CCO output is divided by 2 before to M-Divider */ } break; case 0x03U: /* RTC oscillator 32 kHz output (32k_clk) */ clkRate = CLK_RTC_32K_CLK; break; default: clkRate = 0U; break; } SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL); } /* ---------------------------------------------------------------------------- -- SystemInitHook() ---------------------------------------------------------------------------- */ __attribute__ ((weak)) void SystemInitHook (void) { /* Void implementation of the weak function. */ }