/* * Copyright 2019 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ /*********************************************************************************************************************** * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. **********************************************************************************************************************/ /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo product: Pins v7.0 processor: K32L3A60xxx package_id: K32L3A60VPJ1A mcu_data: ksdk2_0 processor_version: 0.0.1 board: FRDM-K32L3A6 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ #include "fsl_common.h" #include "fsl_port.h" #include "fsl_gpio.h" #include "pin_mux.h" /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitBootPins * Description : Calls initialization functions. * * END ****************************************************************************************************************/ void BOARD_InitBootPins(void) { BOARD_InitPins_cm4(); BOARD_InitDEBUG_UARTPins(); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitPins_cm4: - options: {callFromInitBoot: 'true', coreID: cm4, enableClock: 'true'} - pin_list: [] * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitPins_cm4 * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ /* Function assigned for the Cortex-M4F */ void BOARD_InitPins_cm4(void) { } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitButtonsPins: - options: {coreID: cm4, enableClock: 'true'} - pin_list: - {pin_num: B10, peripheral: GPIOA, signal: 'GPIO, 0', pin_signal: PTA0/NMI_b, direction: INPUT, slew_rate: fast, open_drain: disable, pull_select: up, pull_enable: enable, passive_filter: disable} - {pin_num: P16, peripheral: GPIOE, signal: 'GPIO, 8', pin_signal: LPADC0_SE22/PTE8/LLWU_P23/SDHC0_D5/LPUART3_RX/LPSPI3_SIN/TPM1_CH0/LPTMR2_ALT1, direction: INPUT, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable} - {pin_num: N16, peripheral: GPIOE, signal: 'GPIO, 9', pin_signal: LPADC0_SE23/PTE9/LLWU_P24/SDHC0_CMD/LPUART3_TX/LPSPI3_PCS0/TPM1_CH1/FXIO0_D0, direction: INPUT, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable} - {pin_num: L12, peripheral: GPIOE, signal: 'GPIO, 12', pin_signal: PTE12/LLWU_P26/SDHC0_D2/LPI2C3_SDAS/TPM3_CLKIN/FXIO0_D2, direction: INPUT, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitButtonsPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ /* Function assigned for the Cortex-M4F */ void BOARD_InitButtonsPins(void) { /* Clock Gate Control: Clock enabled. The current clock selection and divider options are locked. */ CLOCK_EnableClock(kCLOCK_PortA); /* Clock Gate Control: Clock enabled. The current clock selection and divider options are locked. */ CLOCK_EnableClock(kCLOCK_PortE); CLOCK_EnableClock(kCLOCK_Rgpio1);//allow access to GPIOE_BASE address gpio_pin_config_t SW2_config = { .pinDirection = kGPIO_DigitalInput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PTA0 (pin B10) */ GPIO_PinInit(BOARD_INITBUTTONSPINS_SW2_GPIO, BOARD_INITBUTTONSPINS_SW2_PIN, &SW2_config); gpio_pin_config_t SW3_config = { .pinDirection = kGPIO_DigitalInput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PTE8 (pin P16) */ GPIO_PinInit(BOARD_INITBUTTONSPINS_SW3_GPIO, BOARD_INITBUTTONSPINS_SW3_PIN, &SW3_config); gpio_pin_config_t SW4_config = { .pinDirection = kGPIO_DigitalInput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PTE9 (pin N16) */ GPIO_PinInit(BOARD_INITBUTTONSPINS_SW4_GPIO, BOARD_INITBUTTONSPINS_SW4_PIN, &SW4_config); gpio_pin_config_t SW5_config = { .pinDirection = kGPIO_DigitalInput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PTE12 (pin L12) */ GPIO_PinInit(BOARD_INITBUTTONSPINS_SW5_GPIO, BOARD_INITBUTTONSPINS_SW5_PIN, &SW5_config); const port_pin_config_t SW2 = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Pin is configured as PTA0 */ kPORT_MuxAsGpio, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORTA0 (pin B10) is configured as PTA0 */ PORT_SetPinConfig(BOARD_INITBUTTONSPINS_SW2_PORT, BOARD_INITBUTTONSPINS_SW2_PIN, &SW2); const port_pin_config_t SW5 = {/* Internal pull-up/down resistor is disabled */ kPORT_PullDisable, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Pin is configured as PTE12 */ kPORT_MuxAsGpio, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORTE12 (pin L12) is configured as PTE12 */ PORT_SetPinConfig(BOARD_INITBUTTONSPINS_SW5_PORT, BOARD_INITBUTTONSPINS_SW5_PIN, &SW5); const port_pin_config_t SW3 = {/* Internal pull-up/down resistor is disabled */ kPORT_PullDisable, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Pin is configured as PTE8 */ kPORT_MuxAsGpio, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORTE8 (pin P16) is configured as PTE8 */ PORT_SetPinConfig(BOARD_INITBUTTONSPINS_SW3_PORT, BOARD_INITBUTTONSPINS_SW3_PIN, &SW3); const port_pin_config_t SW4 = {/* Internal pull-up/down resistor is disabled */ kPORT_PullDisable, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Pin is configured as PTE9 */ kPORT_MuxAsGpio, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORTE9 (pin N16) is configured as PTE9 */ PORT_SetPinConfig(BOARD_INITBUTTONSPINS_SW4_PORT, BOARD_INITBUTTONSPINS_SW4_PIN, &SW4); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitLEDsPins: - options: {coreID: cm4, enableClock: 'true'} - pin_list: - {pin_num: B6, peripheral: GPIOA, signal: 'GPIO, 22', pin_signal: PTA22/LLWU_P2/LPSPI2_PCS2/LPI2C2_HREQ/FB_AD16/TPM2_CH2, direction: OUTPUT, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable} - {pin_num: E6, peripheral: GPIOA, signal: 'GPIO, 23', pin_signal: PTA23/LPSPI2_SIN/LPSPI1_PCS3/LPI2C2_SDA/FB_AD15/TPM2_CH1, direction: OUTPUT, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable} - {pin_num: D6, peripheral: GPIOA, signal: 'GPIO, 24', pin_signal: PTA24/LPSPI2_PCS0/LPSPI1_SCK/LPI2C2_SCL/FB_OE_b/TPM2_CH0, direction: OUTPUT, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitLEDsPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ /* Function assigned for the Cortex-M4F */ void BOARD_InitLEDsPins(void) { /* Clock Gate Control: Clock enabled. The current clock selection and divider options are locked. */ CLOCK_EnableClock(kCLOCK_PortA); gpio_pin_config_t RGB_BLUE_config = { .pinDirection = kGPIO_DigitalOutput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PTA22 (pin B6) */ GPIO_PinInit(BOARD_INITLEDSPINS_RGB_BLUE_GPIO, BOARD_INITLEDSPINS_RGB_BLUE_PIN, &RGB_BLUE_config); gpio_pin_config_t RGB_GREEN_config = { .pinDirection = kGPIO_DigitalOutput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PTA23 (pin E6) */ GPIO_PinInit(BOARD_INITLEDSPINS_RGB_GREEN_GPIO, BOARD_INITLEDSPINS_RGB_GREEN_PIN, &RGB_GREEN_config); gpio_pin_config_t RGB_RED_config = { .pinDirection = kGPIO_DigitalOutput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PTA24 (pin D6) */ GPIO_PinInit(BOARD_INITLEDSPINS_RGB_RED_GPIO, BOARD_INITLEDSPINS_RGB_RED_PIN, &RGB_RED_config); const port_pin_config_t RGB_BLUE = {/* Internal pull-up/down resistor is disabled */ kPORT_PullDisable, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Pin is configured as PTA22 */ kPORT_MuxAsGpio, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORTA22 (pin B6) is configured as PTA22 */ PORT_SetPinConfig(BOARD_INITLEDSPINS_RGB_BLUE_PORT, BOARD_INITLEDSPINS_RGB_BLUE_PIN, &RGB_BLUE); const port_pin_config_t RGB_GREEN = {/* Internal pull-up/down resistor is disabled */ kPORT_PullDisable, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Pin is configured as PTA23 */ kPORT_MuxAsGpio, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORTA23 (pin E6) is configured as PTA23 */ PORT_SetPinConfig(BOARD_INITLEDSPINS_RGB_GREEN_PORT, BOARD_INITLEDSPINS_RGB_GREEN_PIN, &RGB_GREEN); const port_pin_config_t RGB_RED = {/* Internal pull-up/down resistor is disabled */ kPORT_PullDisable, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Pin is configured as PTA24 */ kPORT_MuxAsGpio, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORTA24 (pin D6) is configured as PTA24 */ PORT_SetPinConfig(BOARD_INITLEDSPINS_RGB_RED_PORT, BOARD_INITLEDSPINS_RGB_RED_PIN, &RGB_RED); /* Clock Gate Control: Clock enabled. The current clock selection and divider options are locked. */ CLOCK_EnableClock(kCLOCK_Rgpio1); CLOCK_EnableClock(kCLOCK_PortE); gpio_pin_config_t LED_RED_config = { .pinDirection = kGPIO_DigitalOutput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PTE0 */ GPIO_PinInit(BOARD_INITLEDSPINS_LED_RED_GPIO, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED_config); const port_pin_config_t LED_RED = {/* Internal pull-up/down resistor is disabled */ kPORT_PullDisable, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Pin is configured as PTE0 */ kPORT_MuxAsGpio, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORTE0 is configured as PTE0 */ PORT_SetPinConfig(BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitDEBUG_UARTPins: - options: {callFromInitBoot: 'true', coreID: cm4, enableClock: 'true'} - pin_list: - {pin_num: N2, peripheral: LPUART0, signal: RX, pin_signal: LPCMP0_IN0/PTC7/LLWU_P15/LPSPI0_PCS3/LPUART0_RX/LPI2C1_HREQ/TPM0_CH0/LPTMR1_ALT1, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable} - {pin_num: P3, peripheral: LPUART0, signal: TX, pin_signal: LPCMP0_IN1/PTC8/LPSPI0_SCK/LPUART0_TX/LPI2C0_HREQ/TPM0_CH1, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitDEBUG_UARTPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ /* Function assigned for the Cortex-M4F */ void BOARD_InitDEBUG_UARTPins(void) { /* Clock Gate Control: Clock enabled. The current clock selection and divider options are locked. */ CLOCK_EnableClock(kCLOCK_PortC); /* PORTC7 (pin N2) is configured as LPUART0_RX */ PORT_SetPinMux(BOARD_INITDEBUG_UARTPINS_DEBUG_UART0_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART0_RX_PIN, kPORT_MuxAlt3); PORTC->PCR[7] = ((PORTC->PCR[7] & /* Mask bits to zero which are setting */ (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK))) /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE * field is set. */ | PORT_PCR_PS(kPORT_PullDown) /* Pull Enable: Internal pull resistor is not enabled on the corresponding pin. */ | PORT_PCR_PE(kPORT_PullDisable) /* Slew Rate Enable: Fast slew rate is configured on the corresponding pin, if the pin is configured as * a digital output. */ | PORT_PCR_SRE(kPORT_FastSlewRate) /* Open Drain Enable: Open drain output is disabled on the corresponding pin. */ | PORT_PCR_ODE(kPORT_OpenDrainDisable)); /* PORTC8 (pin P3) is configured as LPUART0_TX */ PORT_SetPinMux(BOARD_INITDEBUG_UARTPINS_DEBUG_UART0_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART0_TX_PIN, kPORT_MuxAlt3); PORTC->PCR[8] = ((PORTC->PCR[8] & /* Mask bits to zero which are setting */ (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK))) /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE * field is set. */ | PORT_PCR_PS(kPORT_PullDown) /* Pull Enable: Internal pull resistor is not enabled on the corresponding pin. */ | PORT_PCR_PE(kPORT_PullDisable) /* Slew Rate Enable: Fast slew rate is configured on the corresponding pin, if the pin is configured as * a digital output. */ | PORT_PCR_SRE(kPORT_FastSlewRate) /* Open Drain Enable: Open drain output is disabled on the corresponding pin. */ | PORT_PCR_ODE(kPORT_OpenDrainDisable)); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitOSCPins: - options: {coreID: cm4, enableClock: 'true'} - pin_list: - {pin_num: E16, peripheral: RTC, signal: EXTAL32, pin_signal: EXTAL32} - {pin_num: E17, peripheral: RTC, signal: XTAL32, pin_signal: XTAL32} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitOSCPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ /* Function assigned for the Cortex-M4F */ void BOARD_InitOSCPins(void) { } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitACCELPins: - options: {coreID: cm4, enableClock: 'true'} - pin_list: - {pin_num: G17, peripheral: LPI2C3, signal: SCL, pin_signal: PTE30/LPUART3_TX/LPI2C3_SCL/TPM2_CLKIN/FXIO0_D31, slew_rate: fast, open_drain: enable, pull_select: up, pull_enable: enable} - {pin_num: G15, peripheral: LPI2C3, signal: SDA, pin_signal: PTE29/LPUART3_RX/LPI2C3_SDA/FXIO0_D30, slew_rate: fast, open_drain: enable, pull_select: up, pull_enable: enable} - {pin_num: R16, peripheral: GPIOE, signal: 'GPIO, 1', pin_signal: LPADC0_SE18/PTE1/LLWU_P21/SDHC0_D1/LPI2C0_SDAS/LPSPI3_PCS1/EWM_OUT_b/LPTMR1_ALT2, direction: INPUT, slew_rate: fast, open_drain: disable, pull_select: up, pull_enable: enable} - {pin_num: J16, peripheral: GPIOE, signal: 'GPIO, 22', pin_signal: PTE22/I2S0_RX_D1/LPI2C3_HREQ/TPM2_CH5/FXIO0_D11, direction: INPUT, slew_rate: fast, open_drain: disable, pull_select: up, pull_enable: enable} - {pin_num: H14, peripheral: GPIOE, signal: 'GPIO, 27', pin_signal: PTE27/LPUART3_CTS/LPI2C3_SDAS/FXIO0_D28, direction: OUTPUT, slew_rate: slow, open_drain: disable, pull_select: down, pull_enable: disable} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitACCELPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ /* Function assigned for the Cortex-M4F */ void BOARD_InitACCELPins(void) { /* Clock Gate Control: Clock enabled. The current clock selection and divider options are locked. */ CLOCK_EnableClock(kCLOCK_PortE); CLOCK_EnableClock(kCLOCK_Rgpio1);//allow access to GPIOE_BASE address gpio_pin_config_t ACCEL_INT1_config = { .pinDirection = kGPIO_DigitalInput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PTE1 (pin R16) */ GPIO_PinInit(BOARD_INITACCELPINS_ACCEL_INT1_GPIO, BOARD_INITACCELPINS_ACCEL_INT1_PIN, &ACCEL_INT1_config); gpio_pin_config_t ACCEL_INT2_config = { .pinDirection = kGPIO_DigitalInput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PTE22 (pin J16) */ GPIO_PinInit(BOARD_INITACCELPINS_ACCEL_INT2_GPIO, BOARD_INITACCELPINS_ACCEL_INT2_PIN, &ACCEL_INT2_config); gpio_pin_config_t ACCEL_RST_config = { .pinDirection = kGPIO_DigitalOutput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PTE27 (pin H14) */ GPIO_PinInit(BOARD_INITACCELPINS_ACCEL_RST_GPIO, BOARD_INITACCELPINS_ACCEL_RST_PIN, &ACCEL_RST_config); const port_pin_config_t ACCEL_INT1 = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Pin is configured as PTE1 */ kPORT_MuxAsGpio, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORTE1 (pin R16) is configured as PTE1 */ PORT_SetPinConfig(BOARD_INITACCELPINS_ACCEL_INT1_PORT, BOARD_INITACCELPINS_ACCEL_INT1_PIN, &ACCEL_INT1); const port_pin_config_t ACCEL_INT2 = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Pin is configured as PTE22 */ kPORT_MuxAsGpio, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORTE22 (pin J16) is configured as PTE22 */ PORT_SetPinConfig(BOARD_INITACCELPINS_ACCEL_INT2_PORT, BOARD_INITACCELPINS_ACCEL_INT2_PIN, &ACCEL_INT2); const port_pin_config_t ACCEL_RST = {/* Internal pull-up/down resistor is disabled */ kPORT_PullDisable, /* Slow slew rate is configured */ kPORT_SlowSlewRate, /* Passive filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Pin is configured as PTE27 */ kPORT_MuxAsGpio, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORTE27 (pin H14) is configured as PTE27 */ PORT_SetPinConfig(BOARD_INITACCELPINS_ACCEL_RST_PORT, BOARD_INITACCELPINS_ACCEL_RST_PIN, &ACCEL_RST); const port_pin_config_t ACCEL_SDA = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain is enabled */ kPORT_OpenDrainEnable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Pin is configured as LPI2C3_SDA */ kPORT_MuxAlt3, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORTE29 (pin G15) is configured as LPI2C3_SDA */ PORT_SetPinConfig(BOARD_INITACCELPINS_ACCEL_SDA_PORT, BOARD_INITACCELPINS_ACCEL_SDA_PIN, &ACCEL_SDA); const port_pin_config_t ACCEL_SCL = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain is enabled */ kPORT_OpenDrainEnable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Pin is configured as LPI2C3_SCL */ kPORT_MuxAlt3, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORTE30 (pin G17) is configured as LPI2C3_SCL */ PORT_SetPinConfig(BOARD_INITACCELPINS_ACCEL_SCL_PORT, BOARD_INITACCELPINS_ACCEL_SCL_PIN, &ACCEL_SCL); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitLIGHT_SENSORPins: - options: {coreID: cm4, enableClock: 'true'} - pin_list: - {pin_num: F4, peripheral: GPIOB, signal: 'GPIO, 9', pin_signal: LPADC0_SE3/PTB9/SPM_LPREQ/LPSPI0_PCS1/LPI2C1_SCL/I2S0_RX_D1/FB_RW_b/FXIO0_D0} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitLIGHT_SENSORPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ /* Function assigned for the Cortex-M4F */ void BOARD_InitLIGHT_SENSORPins(void) { /* Clock Gate Control: Clock enabled. The current clock selection and divider options are locked. */ CLOCK_EnableClock(kCLOCK_PortB); /* PORTB9 (pin F4) is configured as PTB9 */ PORT_SetPinMux(BOARD_INITLIGHT_SENSORPINS_SNS_LIGHT_ADC_PORT, BOARD_INITLIGHT_SENSORPINS_SNS_LIGHT_ADC_PIN, kPORT_MuxAsGpio); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitUSBPins: - options: {coreID: cm4, enableClock: 'true'} - pin_list: - {pin_num: T12, peripheral: USB0, signal: DM, pin_signal: USB0_DM} - {pin_num: T11, peripheral: USB0, signal: DP, pin_signal: USB0_DP} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitUSBPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ /* Function assigned for the Cortex-M4F */ void BOARD_InitUSBPins(void) { } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitSDHCPins: - options: {coreID: cm4, enableClock: 'true'} - pin_list: - {pin_num: R11, peripheral: USDHC0, signal: 'DATA, 2', pin_signal: LPADC0_SE14/PTD11/SDHC0_D2/USB0_SOF_OUT/LPI2C1_SCL/CLKOUT/TPM2_CH0/FXIO0_D31, slew_rate: fast, open_drain: disable, pull_select: up, pull_enable: enable} - {pin_num: P11, peripheral: USDHC0, signal: 'DATA, 3', pin_signal: LPADC0_SE13/PTD10/LLWU_P20/SDHC0_D3/LPSPI2_PCS0/LPI2C1_SDA/TRACE_CLKOUT/TPM2_CH1/FXIO0_D30, slew_rate: fast, open_drain: disable, pull_select: up, pull_enable: enable} - {pin_num: U11, peripheral: USDHC0, signal: CMD, pin_signal: LPADC0_SE12/PTD9/SDHC0_CMD/LPSPI2_SIN/LPI2C1_SCLS/TRACE_D0/TPM2_CH2/FXIO0_D29, slew_rate: fast, open_drain: disable, pull_select: up, pull_enable: enable} - {pin_num: T9, peripheral: USDHC0, signal: DCLK, pin_signal: LPADC0_SE11/PTD8/LLWU_P19/SDHC0_DCLK/LPSPI2_PCS2/LPI2C1_SDAS/TRACE_D1/TPM2_CH3/FXIO0_D28, slew_rate: fast, open_drain: disable, pull_select: up, pull_enable: enable} - {pin_num: P10, peripheral: USDHC0, signal: 'DATA, 0', pin_signal: LPADC0_SE10/PTD7/SDHC0_D0/LPSPI2_SOUT/EMVSIM0_PD/TRACE_D2/TPM2_CH4/FXIO0_D27, slew_rate: fast, open_drain: disable, pull_select: up, pull_enable: enable} - {pin_num: U9, peripheral: USDHC0, signal: 'DATA, 1', pin_signal: LPADC0_SE9/PTD6/SDHC0_D1/LPSPI2_SCK/EMVSIM0_IO/TRACE_D3/TPM2_CH5/FXIO0_D26, slew_rate: fast, open_drain: disable, pull_select: up, pull_enable: enable} - {pin_num: P6, peripheral: GPIOC, signal: 'GPIO, 27', pin_signal: PTC27/TPM0_CH4, direction: INPUT, slew_rate: fast, open_drain: disable, pull_select: up, pull_enable: enable} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitSDHCPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ /* Function assigned for the Cortex-M4F */ void BOARD_InitSDHCPins(void) { /* Clock Gate Control: Clock enabled. The current clock selection and divider options are locked. */ CLOCK_EnableClock(kCLOCK_PortC); /* Clock Gate Control: Clock enabled. The current clock selection and divider options are locked. */ CLOCK_EnableClock(kCLOCK_PortD); gpio_pin_config_t SD_DETECT_config = { .pinDirection = kGPIO_DigitalInput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PTC27 (pin P6) */ GPIO_PinInit(BOARD_INITSDHCPINS_SD_DETECT_GPIO, BOARD_INITSDHCPINS_SD_DETECT_PIN, &SD_DETECT_config); const port_pin_config_t SD_DETECT = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Pin is configured as PTC27 */ kPORT_MuxAsGpio, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORTC27 (pin P6) is configured as PTC27 */ PORT_SetPinConfig(BOARD_INITSDHCPINS_SD_DETECT_PORT, BOARD_INITSDHCPINS_SD_DETECT_PIN, &SD_DETECT); /* PORTD10 (pin P11) is configured as SDHC0_D3 */ PORT_SetPinMux(BOARD_INITSDHCPINS_SDHC0_D3_PORT, BOARD_INITSDHCPINS_SDHC0_D3_PIN, kPORT_MuxAlt2); PORTD->PCR[10] = ((PORTD->PCR[10] & /* Mask bits to zero which are setting */ (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK))) /* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE * field is set. */ | (uint32_t)(kPORT_PullUp) /* Slew Rate Enable: Fast slew rate is configured on the corresponding pin, if the pin is configured as * a digital output. */ | PORT_PCR_SRE(kPORT_FastSlewRate) /* Open Drain Enable: Open drain output is disabled on the corresponding pin. */ | PORT_PCR_ODE(kPORT_OpenDrainDisable)); /* PORTD11 (pin R11) is configured as SDHC0_D2 */ PORT_SetPinMux(BOARD_INITSDHCPINS_SDHC0_D2_PORT, BOARD_INITSDHCPINS_SDHC0_D2_PIN, kPORT_MuxAlt2); PORTD->PCR[11] = ((PORTD->PCR[11] & /* Mask bits to zero which are setting */ (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK))) /* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE * field is set. */ | (uint32_t)(kPORT_PullUp) /* Slew Rate Enable: Fast slew rate is configured on the corresponding pin, if the pin is configured as * a digital output. */ | PORT_PCR_SRE(kPORT_FastSlewRate) /* Open Drain Enable: Open drain output is disabled on the corresponding pin. */ | PORT_PCR_ODE(kPORT_OpenDrainDisable)); const port_pin_config_t SDHC0_D1 = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Pin is configured as SDHC0_D1 */ kPORT_MuxAlt2, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORTD6 (pin U9) is configured as SDHC0_D1 */ PORT_SetPinConfig(BOARD_INITSDHCPINS_SDHC0_D1_PORT, BOARD_INITSDHCPINS_SDHC0_D1_PIN, &SDHC0_D1); const port_pin_config_t SDHC0_D0 = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Pin is configured as SDHC0_D0 */ kPORT_MuxAlt2, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORTD7 (pin P10) is configured as SDHC0_D0 */ PORT_SetPinConfig(BOARD_INITSDHCPINS_SDHC0_D0_PORT, BOARD_INITSDHCPINS_SDHC0_D0_PIN, &SDHC0_D0); /* PORTD8 (pin T9) is configured as SDHC0_DCLK */ PORT_SetPinMux(BOARD_INITSDHCPINS_SDHC0_DCLK_PORT, BOARD_INITSDHCPINS_SDHC0_DCLK_PIN, kPORT_MuxAlt2); PORTD->PCR[8] = ((PORTD->PCR[8] & /* Mask bits to zero which are setting */ (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK))) /* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE * field is set. */ | (uint32_t)(kPORT_PullUp) /* Slew Rate Enable: Fast slew rate is configured on the corresponding pin, if the pin is configured as * a digital output. */ | PORT_PCR_SRE(kPORT_FastSlewRate) /* Open Drain Enable: Open drain output is disabled on the corresponding pin. */ | PORT_PCR_ODE(kPORT_OpenDrainDisable)); /* PORTD9 (pin U11) is configured as SDHC0_CMD */ PORT_SetPinMux(BOARD_INITSDHCPINS_SDHC0_CMD_PORT, BOARD_INITSDHCPINS_SDHC0_CMD_PIN, kPORT_MuxAlt2); PORTD->PCR[9] = ((PORTD->PCR[9] & /* Mask bits to zero which are setting */ (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK))) /* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE * field is set. */ | (uint32_t)(kPORT_PullUp) /* Slew Rate Enable: Fast slew rate is configured on the corresponding pin, if the pin is configured as * a digital output. */ | PORT_PCR_SRE(kPORT_FastSlewRate) /* Open Drain Enable: Open drain output is disabled on the corresponding pin. */ | PORT_PCR_ODE(kPORT_OpenDrainDisable)); } /*********************************************************************************************************************** * EOF **********************************************************************************************************************/