/* * Copyright 2019 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ /*********************************************************************************************************************** * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. **********************************************************************************************************************/ /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo product: Pins v7.0 processor: MIMXRT685S package_id: MIMXRT685SFVKB mcu_data: ksdk2_0 processor_version: 0.0.2 board: MIMXRT685-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ #include "fsl_common.h" #include "fsl_gpio.h" #include "fsl_iopctl.h" #include "pin_mux.h" /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitBootPins * Description : Calls initialization functions. * * END ****************************************************************************************************************/ void BOARD_InitBootPins(void) { BOARD_InitPins(); BOARD_InitDEBUG_UARTPins(); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitPins: - options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'} - pin_list: [] * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ /* Function assigned for the Cortex-M33 */ void BOARD_InitPins(void) { } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitDEBUG_UARTPins: - options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'} - pin_list: - {pin_num: G4, peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_2/FC0_RXD_SDA_MOSI_DATA/CTIMER0_MAT2/I2S_BRIDGE_DATA_IN/SEC_PIO0_2, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: G2, peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_1/FC0_TXD_SCL_MISO_WS/CTIMER0_MAT1/I2S_BRIDGE_WS_IN/SEC_PIO0_1, pupdena: disabled, pupdsel: pullDown, ibena: disabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitDEBUG_UARTPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ /* Function assigned for the Cortex-M33 */ void BOARD_InitDEBUG_UARTPins(void) { const uint32_t port0_pin1_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */ IOPCTL_PIO_FUNC1 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Disable input buffer function */ IOPCTL_PIO_INBUF_DI | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT0 PIN1 (coords: G2) is configured as FC0_TXD_SCL_MISO_WS */ IOPCTL_PinMuxSet(IOPCTL, 0U, 1U, port0_pin1_config); const uint32_t port0_pin2_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */ IOPCTL_PIO_FUNC1 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT0 PIN2 (coords: G4) is configured as FC0_RXD_SDA_MOSI_DATA */ IOPCTL_PinMuxSet(IOPCTL, 0U, 2U, port0_pin2_config); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitFlexSPIFlashPins: - options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'} - pin_list: - {pin_num: L2, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA0, pin_signal: PIO1_11/HS_SPI_SCK/CTIMER2_MAT0/FLEXSPI0B_DATA0, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: M2, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA1, pin_signal: PIO1_12/HS_SPI_MISO/CTIMER2_MAT1/FLEXSPI0B_DATA1, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: N1, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA2, pin_signal: PIO1_13/HS_SPI_MOSI/CTIMER2_MAT2/FLEXSPI0B_DATA2, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: N2, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA3, pin_signal: PIO1_14/HS_SPI_SSEL0/CTIMER2_MAT3/FLEXSPI0B_DATA3, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: U1, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA4, pin_signal: PIO2_17/PDM_CLK23/FLEXSPI0B_DATA4, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: R2, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA5, pin_signal: PIO2_18/PDM_CLK45/FLEXSPI0B_DATA5, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA6, pin_signal: PIO2_22/PDM_DATA45/FLEXSPI0B_DATA6, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA7, pin_signal: PIO2_23/PDM_DATA67/FLEXSPI0B_DATA7, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: T2, peripheral: FLEXSPI, signal: FLEXSPI_B_SS0_B, pin_signal: PIO2_19/PDM_CLK67/FLEXSPI0B_SS0_N, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: U3, peripheral: FLEXSPI, signal: FLEXSPI_B_SCLK, pin_signal: PIO1_29/FLEXSPI0A_SS1_N/SCT0_OUT5/UTICK_CAP2/CTIMER_INP13/FLEXSPI0B_SCLK, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitFlexSPIFlashPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ /* Function assigned for the Cortex-M33 */ void BOARD_InitFlexSPIFlashPins(void) { const uint32_t port1_pin11_config = (/* Pin is configured as FLEXSPI0B_DATA0 */ IOPCTL_PIO_FUNC6 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN11 (coords: L2) is configured as FLEXSPI0B_DATA0 */ IOPCTL_PinMuxSet(IOPCTL, 1U, 11U, port1_pin11_config); const uint32_t port1_pin12_config = (/* Pin is configured as FLEXSPI0B_DATA1 */ IOPCTL_PIO_FUNC6 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN12 (coords: M2) is configured as FLEXSPI0B_DATA1 */ IOPCTL_PinMuxSet(IOPCTL, 1U, 12U, port1_pin12_config); const uint32_t port1_pin13_config = (/* Pin is configured as FLEXSPI0B_DATA2 */ IOPCTL_PIO_FUNC6 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN13 (coords: N1) is configured as FLEXSPI0B_DATA2 */ IOPCTL_PinMuxSet(IOPCTL, 1U, 13U, port1_pin13_config); const uint32_t port1_pin14_config = (/* Pin is configured as FLEXSPI0B_DATA3 */ IOPCTL_PIO_FUNC6 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN14 (coords: N2) is configured as FLEXSPI0B_DATA3 */ IOPCTL_PinMuxSet(IOPCTL, 1U, 14U, port1_pin14_config); const uint32_t port1_pin29_config = (/* Pin is configured as FLEXSPI0B_SCLK */ IOPCTL_PIO_FUNC5 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN29 (coords: U3) is configured as FLEXSPI0B_SCLK */ IOPCTL_PinMuxSet(IOPCTL, 1U, 29U, port1_pin29_config); const uint32_t port2_pin17_config = (/* Pin is configured as FLEXSPI0B_DATA4 */ IOPCTL_PIO_FUNC6 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT2 PIN17 (coords: U1) is configured as FLEXSPI0B_DATA4 */ IOPCTL_PinMuxSet(IOPCTL, 2U, 17U, port2_pin17_config); const uint32_t port2_pin18_config = (/* Pin is configured as FLEXSPI0B_DATA5 */ IOPCTL_PIO_FUNC6 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT2 PIN18 (coords: R2) is configured as FLEXSPI0B_DATA5 */ IOPCTL_PinMuxSet(IOPCTL, 2U, 18U, port2_pin18_config); const uint32_t port2_pin19_config = (/* Pin is configured as FLEXSPI0B_SS0_N */ IOPCTL_PIO_FUNC6 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT2 PIN19 (coords: T2) is configured as FLEXSPI0B_SS0_N */ IOPCTL_PinMuxSet(IOPCTL, 2U, 19U, port2_pin19_config); const uint32_t port2_pin22_config = (/* Pin is configured as FLEXSPI0B_DATA6 */ IOPCTL_PIO_FUNC6 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT2 PIN22 (coords: P3) is configured as FLEXSPI0B_DATA6 */ IOPCTL_PinMuxSet(IOPCTL, 2U, 22U, port2_pin22_config); const uint32_t port2_pin23_config = (/* Pin is configured as FLEXSPI0B_DATA7 */ IOPCTL_PIO_FUNC6 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT2 PIN23 (coords: P5) is configured as FLEXSPI0B_DATA7 */ IOPCTL_PinMuxSet(IOPCTL, 2U, 23U, port2_pin23_config); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitPSRAMPins: - options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'} - pin_list: - {pin_num: T5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: PIO1_20/FLEXSPI0A_DATA0/SCT0_GPI1/CTIMER4_MAT1} - {pin_num: U5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: PIO1_21/FLEXSPI0A_DATA1/SCT0_OUT1/CTIMER4_MAT2} - {pin_num: P6, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: PIO1_22/FLEXSPI0A_DATA2/SCT0_GPI2/CTIMER4_MAT3, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: P7, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: PIO1_23/FLEXSPI0A_DATA3/SCT0_OUT2/CTIMER_INP8, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: T7, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA4, pin_signal: PIO1_24/FLEXSPI0A_DATA4/SCT0_GPI3, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: U7, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA5, pin_signal: PIO1_25/FLEXSPI0A_DATA5/SCT0_OUT3, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: R7, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA6, pin_signal: PIO1_26/FLEXSPI0A_DATA6/SCT0_GPI4, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: T8, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA7, pin_signal: PIO1_27/FLEXSPI0A_DATA7/SCT0_OUT4, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: U9, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: PIO1_28/FLEXSPI0A_DQS/SCT0_GPI5, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: T9, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: PIO1_18/FLEXSPI0A_SCLK/SCT0_GPI0/CTIMER3_MAT3, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: T4, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: PIO1_19/FLEXSPI0A_SS0_N/SCT0_OUT0/CTIMER4_MAT0, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: disabled, iiena: disabled} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitPSRAMPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ /* Function assigned for the Cortex-M33 */ void BOARD_InitPSRAMPins(void) { const uint32_t port1_pin18_config = (/* Pin is configured as FLEXSPI0A_SCLK */ IOPCTL_PIO_FUNC1 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN18 (coords: T9) is configured as FLEXSPI0A_SCLK */ IOPCTL_PinMuxSet(IOPCTL, 1U, 18U, port1_pin18_config); const uint32_t port1_pin19_config = (/* Pin is configured as FLEXSPI0A_SS0_N */ IOPCTL_PIO_FUNC1 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN19 (coords: T4) is configured as FLEXSPI0A_SS0_N */ IOPCTL_PinMuxSet(IOPCTL, 1U, 19U, port1_pin19_config); const uint32_t port1_pin20_config = (/* Pin is configured as FLEXSPI0A_DATA0 */ IOPCTL_PIO_FUNC1 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Disable input buffer function */ IOPCTL_PIO_INBUF_DI | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN20 (coords: T5) is configured as FLEXSPI0A_DATA0 */ IOPCTL_PinMuxSet(IOPCTL, 1U, 20U, port1_pin20_config); const uint32_t port1_pin21_config = (/* Pin is configured as FLEXSPI0A_DATA1 */ IOPCTL_PIO_FUNC1 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Disable input buffer function */ IOPCTL_PIO_INBUF_DI | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN21 (coords: U5) is configured as FLEXSPI0A_DATA1 */ IOPCTL_PinMuxSet(IOPCTL, 1U, 21U, port1_pin21_config); const uint32_t port1_pin22_config = (/* Pin is configured as FLEXSPI0A_DATA2 */ IOPCTL_PIO_FUNC1 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN22 (coords: P6) is configured as FLEXSPI0A_DATA2 */ IOPCTL_PinMuxSet(IOPCTL, 1U, 22U, port1_pin22_config); const uint32_t port1_pin23_config = (/* Pin is configured as FLEXSPI0A_DATA3 */ IOPCTL_PIO_FUNC1 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN23 (coords: P7) is configured as FLEXSPI0A_DATA3 */ IOPCTL_PinMuxSet(IOPCTL, 1U, 23U, port1_pin23_config); const uint32_t port1_pin24_config = (/* Pin is configured as FLEXSPI0A_DATA4 */ IOPCTL_PIO_FUNC1 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN24 (coords: T7) is configured as FLEXSPI0A_DATA4 */ IOPCTL_PinMuxSet(IOPCTL, 1U, 24U, port1_pin24_config); const uint32_t port1_pin25_config = (/* Pin is configured as FLEXSPI0A_DATA5 */ IOPCTL_PIO_FUNC1 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN25 (coords: U7) is configured as FLEXSPI0A_DATA5 */ IOPCTL_PinMuxSet(IOPCTL, 1U, 25U, port1_pin25_config); const uint32_t port1_pin26_config = (/* Pin is configured as FLEXSPI0A_DATA6 */ IOPCTL_PIO_FUNC1 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN26 (coords: R7) is configured as FLEXSPI0A_DATA6 */ IOPCTL_PinMuxSet(IOPCTL, 1U, 26U, port1_pin26_config); const uint32_t port1_pin27_config = (/* Pin is configured as FLEXSPI0A_DATA7 */ IOPCTL_PIO_FUNC1 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN27 (coords: T8) is configured as FLEXSPI0A_DATA7 */ IOPCTL_PinMuxSet(IOPCTL, 1U, 27U, port1_pin27_config); const uint32_t port1_pin28_config = (/* Pin is configured as FLEXSPI0A_DQS */ IOPCTL_PIO_FUNC1 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN28 (coords: U9) is configured as FLEXSPI0A_DQS */ IOPCTL_PinMuxSet(IOPCTL, 1U, 28U, port1_pin28_config); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitUSDHC0Pins: - options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'} - pin_list: - {pin_num: R11, peripheral: USDHC0, signal: 'USDHC_DATA, 0', pin_signal: PIO2_0/SD0_D0/SCT0_GPI2, pupdena: enabled, pupdsel: pullUp, ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: T11, peripheral: USDHC0, signal: 'USDHC_DATA, 1', pin_signal: PIO2_1/SD0_D1/SCT0_GPI3, pupdena: enabled, pupdsel: pullUp, ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: U11, peripheral: USDHC0, signal: 'USDHC_DATA, 2', pin_signal: PIO2_2/SD0_D2/SCT0_OUT0, pupdena: enabled, pupdsel: pullUp, ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: T12, peripheral: USDHC0, signal: 'USDHC_DATA, 3', pin_signal: PIO2_3/SD0_D3/SCT0_OUT1, pupdena: enabled, pupdsel: pullUp, ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: P10, peripheral: USDHC0, signal: USDHC_CLK, pin_signal: PIO1_30/SD0_CLK/SCT0_GPI0, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: R9, peripheral: USDHC0, signal: USDHC_CMD, pin_signal: PIO1_31/SD0_CMD/SCT0_GPI1, pupdena: enabled, pupdsel: pullUp, ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: R13, peripheral: USDHC0, signal: USDHC_CD_B, pin_signal: PIO2_9/SD0_CARD_DET_N/SCT0_OUT5/CTIMER1_MAT3, pupdena: enabled, pupdsel: pullUp, ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: T15, peripheral: GPIO, signal: 'PIO2, 10', pin_signal: PIO2_10/SD0_RESET_N/SCT0_GPI6/CTIMER2_MAT0, pupdena: disabled, pupdsel: pullDown, ibena: disabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitUSDHC0Pins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ /* Function assigned for the Cortex-M33 */ void BOARD_InitUSDHC0Pins(void) { const uint32_t port1_pin30_config = (/* Pin is configured as SD0_CLK */ IOPCTL_PIO_FUNC1 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN30 (coords: P10) is configured as SD0_CLK */ IOPCTL_PinMuxSet(IOPCTL, 1U, 30U, port1_pin30_config); const uint32_t port1_pin31_config = (/* Pin is configured as SD0_CMD */ IOPCTL_PIO_FUNC1 | /* Enable pull-up / pull-down function */ IOPCTL_PIO_PUPD_EN | /* Enable pull-up function */ IOPCTL_PIO_PULLUP_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN31 (coords: R9) is configured as SD0_CMD */ IOPCTL_PinMuxSet(IOPCTL, 1U, 31U, port1_pin31_config); const uint32_t port2_pin0_config = (/* Pin is configured as SD0_D0 */ IOPCTL_PIO_FUNC1 | /* Enable pull-up / pull-down function */ IOPCTL_PIO_PUPD_EN | /* Enable pull-up function */ IOPCTL_PIO_PULLUP_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT2 PIN0 (coords: R11) is configured as SD0_D0 */ IOPCTL_PinMuxSet(IOPCTL, 2U, 0U, port2_pin0_config); const uint32_t port2_pin1_config = (/* Pin is configured as SD0_D1 */ IOPCTL_PIO_FUNC1 | /* Enable pull-up / pull-down function */ IOPCTL_PIO_PUPD_EN | /* Enable pull-up function */ IOPCTL_PIO_PULLUP_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT2 PIN1 (coords: T11) is configured as SD0_D1 */ IOPCTL_PinMuxSet(IOPCTL, 2U, 1U, port2_pin1_config); const uint32_t SD_RST_N = (/* Pin is configured as PIO2_10 */ IOPCTL_PIO_FUNC0 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Disable input buffer function */ IOPCTL_PIO_INBUF_DI | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT2 PIN10 (coords: T15) is configured as PIO2_10 */ IOPCTL_PinMuxSet(IOPCTL, BOARD_INITUSDHC0PINS_SD_RST_N_PORT, BOARD_INITUSDHC0PINS_SD_RST_N_PIN, SD_RST_N); const uint32_t port2_pin2_config = (/* Pin is configured as SD0_D2 */ IOPCTL_PIO_FUNC1 | /* Enable pull-up / pull-down function */ IOPCTL_PIO_PUPD_EN | /* Enable pull-up function */ IOPCTL_PIO_PULLUP_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT2 PIN2 (coords: U11) is configured as SD0_D2 */ IOPCTL_PinMuxSet(IOPCTL, 2U, 2U, port2_pin2_config); const uint32_t port2_pin3_config = (/* Pin is configured as SD0_D3 */ IOPCTL_PIO_FUNC1 | /* Enable pull-up / pull-down function */ IOPCTL_PIO_PUPD_EN | /* Enable pull-up function */ IOPCTL_PIO_PULLUP_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT2 PIN3 (coords: T12) is configured as SD0_D3 */ IOPCTL_PinMuxSet(IOPCTL, 2U, 3U, port2_pin3_config); const uint32_t port2_pin9_config = (/* Pin is configured as SD0_CARD_DET_N */ IOPCTL_PIO_FUNC1 | /* Enable pull-up / pull-down function */ IOPCTL_PIO_PUPD_EN | /* Enable pull-up function */ IOPCTL_PIO_PULLUP_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT2 PIN9 (coords: R13) is configured as SD0_CARD_DET_N */ IOPCTL_PinMuxSet(IOPCTL, 2U, 9U, port2_pin9_config); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitLEDsPins: - options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'} - pin_list: - {pin_num: A3, peripheral: GPIO, signal: 'PIO0, 14', pin_signal: PIO0_14/FC2_SCK/SCT0_GPI0/SCT0_OUT0/CTIMER2_MAT0/I2S_BRIDGE_CLK_IN/SEC_PIO0_14, direction: OUTPUT, gpio_init_state: 'true', pupdena: disabled, pupdsel: pullDown, ibena: disabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: A2, peripheral: GPIO, signal: 'PIO0, 26', pin_signal: PIO0_26/FC3_SSEL2/SCT0_GPI6/SCT0_OUT6/CTIMER_INP7/SEC_PIO0_26/ADC0_3, direction: OUTPUT, gpio_init_state: 'true', pupdena: disabled, pupdsel: pullDown, ibena: disabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: A11, peripheral: GPIO, signal: 'PIO0, 31', pin_signal: PIO0_31/FC4_CTS_SDA_SSEL0/SCT0_GPI0/SCT0_OUT6/CTIMER4_MAT3/FC3_SSEL2/SEC_PIO0_31, direction: OUTPUT, gpio_init_state: 'true', pupdena: disabled, pupdsel: pullDown, ibena: disabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitLEDsPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ /* Function assigned for the Cortex-M33 */ void BOARD_InitLEDsPins(void) { /* Enables the clock for the GPIO0 module */ CLOCK_EnableClock(kCLOCK_HsGpio0); gpio_pin_config_t LED_GREEN_config = { .pinDirection = kGPIO_DigitalOutput, .outputLogic = 1U }; /* Initialize GPIO functionality on pin PIO0_14 (pin A3) */ GPIO_PinInit(BOARD_INITLEDSPINS_LED_GREEN_GPIO, BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN_config); gpio_pin_config_t LED_BLUE_config = { .pinDirection = kGPIO_DigitalOutput, .outputLogic = 1U }; /* Initialize GPIO functionality on pin PIO0_26 (pin A2) */ GPIO_PinInit(BOARD_INITLEDSPINS_LED_BLUE_GPIO, BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE_config); gpio_pin_config_t LED_RED_config = { .pinDirection = kGPIO_DigitalOutput, .outputLogic = 1U }; /* Initialize GPIO functionality on pin PIO0_31 (pin A11) */ GPIO_PinInit(BOARD_INITLEDSPINS_LED_RED_GPIO, BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED_config); const uint32_t LED_GREEN = (/* Pin is configured as PIO0_14 */ IOPCTL_PIO_FUNC0 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Disable input buffer function */ IOPCTL_PIO_INBUF_DI | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT0 PIN14 (coords: A3) is configured as PIO0_14 */ IOPCTL_PinMuxSet(IOPCTL, BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, LED_GREEN); const uint32_t LED_BLUE = (/* Pin is configured as PIO0_26 */ IOPCTL_PIO_FUNC0 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Disable input buffer function */ IOPCTL_PIO_INBUF_DI | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT0 PIN26 (coords: A2) is configured as PIO0_26 */ IOPCTL_PinMuxSet(IOPCTL, BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, LED_BLUE); const uint32_t LED_RED = (/* Pin is configured as PIO0_31 */ IOPCTL_PIO_FUNC0 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Disable input buffer function */ IOPCTL_PIO_INBUF_DI | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT0 PIN31 (coords: A11) is configured as PIO0_31 */ IOPCTL_PinMuxSet(IOPCTL, BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, LED_RED); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitBUTTONsPins: - options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'} - pin_list: - {pin_num: J3, peripheral: GPIO, signal: 'PIO0, 10', pin_signal: PIO0_10/FC1_CTS_SDA_SSEL0/SCT0_GPI7/SCT0_OUT7/CTIMER1_MAT3/FC0_SSEL2/SEC_PIO0_10, direction: INPUT, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: G15, peripheral: GPIO, signal: 'PIO1, 1', pin_signal: PIO1_1/FC4_SSEL2/SCT0_GPI2/SCT0_OUT8/CTIMER1_MAT0, direction: INPUT, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: B15, peripheral: SYSCON, signal: RESET, pin_signal: RESETN} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitBUTTONsPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ /* Function assigned for the Cortex-M33 */ void BOARD_InitBUTTONsPins(void) { /* Enables the clock for the GPIO0 module */ CLOCK_EnableClock(kCLOCK_HsGpio0); /* Enables the clock for the GPIO1 module */ CLOCK_EnableClock(kCLOCK_HsGpio1); gpio_pin_config_t SW2_config = { .pinDirection = kGPIO_DigitalInput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PIO0_10 (pin J3) */ GPIO_PinInit(BOARD_INITBUTTONSPINS_SW2_GPIO, BOARD_INITBUTTONSPINS_SW2_PORT, BOARD_INITBUTTONSPINS_SW2_PIN, &SW2_config); gpio_pin_config_t SW1_config = { .pinDirection = kGPIO_DigitalInput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PIO1_1 (pin G15) */ GPIO_PinInit(BOARD_INITBUTTONSPINS_SW1_GPIO, BOARD_INITBUTTONSPINS_SW1_PORT, BOARD_INITBUTTONSPINS_SW1_PIN, &SW1_config); const uint32_t SW2 = (/* Pin is configured as PIO0_10 */ IOPCTL_PIO_FUNC0 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT0 PIN10 (coords: J3) is configured as PIO0_10 */ IOPCTL_PinMuxSet(IOPCTL, BOARD_INITBUTTONSPINS_SW2_PORT, BOARD_INITBUTTONSPINS_SW2_PIN, SW2); const uint32_t SW1 = (/* Pin is configured as PIO1_1 */ IOPCTL_PIO_FUNC0 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN1 (coords: G15) is configured as PIO1_1 */ IOPCTL_PinMuxSet(IOPCTL, BOARD_INITBUTTONSPINS_SW1_PORT, BOARD_INITBUTTONSPINS_SW1_PIN, SW1); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitACCELPins: - options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'} - pin_list: - {pin_num: B7, peripheral: FLEXCOMM2, signal: RTS_SCL_SSEL1, pin_signal: PIO0_18/FC2_RTS_SCL_SSEL1/SCT0_GPI6/SCT0_OUT6/CTIMER_INP4/FC5_SSEL3/SEC_PIO0_18, pupdena: enabled, pupdsel: pullUp, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: enabled, iiena: disabled} - {pin_num: D7, peripheral: FLEXCOMM2, signal: CTS_SDA_SSEL0, pin_signal: PIO0_17/FC2_CTS_SDA_SSEL0/SCT0_GPI3/SCT0_OUT3/CTIMER2_MAT3/FC5_SSEL2/SEC_PIO0_17, pupdena: enabled, pupdsel: pullUp, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: enabled, iiena: disabled} - {pin_num: J16, peripheral: GPIO, signal: 'PIO1, 5', pin_signal: PIO1_5/FC5_RXD_SDA_MOSI_DATA, direction: INPUT, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled} - {pin_num: J15, peripheral: GPIO, signal: 'PIO1, 7', pin_signal: PIO1_7/FC5_RTS_SCL_SSEL1/SCT0_GPI5/SCT0_OUT5/CTIMER_INP9/FC4_SSEL3, direction: OUTPUT, gpio_init_state: 'true', pupdena: disabled, pupdsel: pullDown, ibena: disabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitACCELPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ /* Function assigned for the Cortex-M33 */ void BOARD_InitACCELPins(void) { /* Enables the clock for the GPIO1 module */ CLOCK_EnableClock(kCLOCK_HsGpio1); gpio_pin_config_t ACC_INT_config = { .pinDirection = kGPIO_DigitalInput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PIO1_5 (pin J16) */ GPIO_PinInit(BOARD_INITACCELPINS_ACC_INT_GPIO, BOARD_INITACCELPINS_ACC_INT_PORT, BOARD_INITACCELPINS_ACC_INT_PIN, &ACC_INT_config); gpio_pin_config_t ACC_RESET_config = { .pinDirection = kGPIO_DigitalOutput, .outputLogic = 1U }; /* Initialize GPIO functionality on pin PIO1_7 (pin J15) */ GPIO_PinInit(BOARD_INITACCELPINS_ACC_RESET_GPIO, BOARD_INITACCELPINS_ACC_RESET_PORT, BOARD_INITACCELPINS_ACC_RESET_PIN, &ACC_RESET_config); const uint32_t port0_pin17_config = (/* Pin is configured as FC2_CTS_SDA_SSEL0 */ IOPCTL_PIO_FUNC1 | /* Enable pull-up / pull-down function */ IOPCTL_PIO_PUPD_EN | /* Enable pull-up function */ IOPCTL_PIO_PULLUP_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is enabled */ IOPCTL_PIO_PSEDRAIN_EN | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT0 PIN17 (coords: D7) is configured as FC2_CTS_SDA_SSEL0 */ IOPCTL_PinMuxSet(IOPCTL, 0U, 17U, port0_pin17_config); const uint32_t port0_pin18_config = (/* Pin is configured as FC2_RTS_SCL_SSEL1 */ IOPCTL_PIO_FUNC1 | /* Enable pull-up / pull-down function */ IOPCTL_PIO_PUPD_EN | /* Enable pull-up function */ IOPCTL_PIO_PULLUP_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Full drive enable */ IOPCTL_PIO_FULLDRIVE_EN | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is enabled */ IOPCTL_PIO_PSEDRAIN_EN | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT0 PIN18 (coords: B7) is configured as FC2_RTS_SCL_SSEL1 */ IOPCTL_PinMuxSet(IOPCTL, 0U, 18U, port0_pin18_config); const uint32_t ACC_INT = (/* Pin is configured as PIO1_5 */ IOPCTL_PIO_FUNC0 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Enables input buffer function */ IOPCTL_PIO_INBUF_EN | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN5 (coords: J16) is configured as PIO1_5 */ IOPCTL_PinMuxSet(IOPCTL, BOARD_INITACCELPINS_ACC_INT_PORT, BOARD_INITACCELPINS_ACC_INT_PIN, ACC_INT); const uint32_t ACC_RESET = (/* Pin is configured as PIO1_7 */ IOPCTL_PIO_FUNC0 | /* Disable pull-up / pull-down function */ IOPCTL_PIO_PUPD_DI | /* Enable pull-down function */ IOPCTL_PIO_PULLDOWN_EN | /* Disable input buffer function */ IOPCTL_PIO_INBUF_DI | /* Normal mode */ IOPCTL_PIO_SLEW_RATE_NORMAL | /* Normal drive */ IOPCTL_PIO_FULLDRIVE_DI | /* Analog mux is disabled */ IOPCTL_PIO_ANAMUX_DI | /* Pseudo Output Drain is disabled */ IOPCTL_PIO_PSEDRAIN_DI | /* Input function is not inverted */ IOPCTL_PIO_INV_DI); /* PORT1 PIN7 (coords: J15) is configured as PIO1_7 */ IOPCTL_PinMuxSet(IOPCTL, BOARD_INITACCELPINS_ACC_RESET_PORT, BOARD_INITACCELPINS_ACC_RESET_PIN, ACC_RESET); } /*********************************************************************************************************************** * EOF **********************************************************************************************************************/